MB89567CPFM [FUJITSU]
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| 型号： | MB89567CPFM |
| 厂家： | 
FUJITSU |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12555-1E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89560A Series
MB89567A/567AC/P568/PV560
■ DESCRIPTION
The MB89560A series has been developed as a general-purpose version of the F2MC*1-8L family consisting of
proprietary 8-bit, single-chip microcontrollers.
In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as I2C
interface*2, timers, 2 ch 8-bit PWM timers, 8/16-bit timer, 21-bit timebase timer, 8-bit PWC timer, 17-bit Watch
prescaler, Watch-dog timer, High speed UART, 8-bit SIO, UART/SIO, LCD controller/driver (optional booster),
Two type Programmable Pulse Generators (PPG), an A/D converter, and external interrupt.
*1 : F2MC stands for FUJITSU Flexible Microcontroller.
*2 : I2C of this product is complied to Intel Corp. System Management Bus Rev. 1.0 specification and to the Philips
I2C specification.
■ FEATURES
• F2MC-8L family CPU core
• Low-voltage operation (when an A/D converter is not used)
• Low current consumption (applicable to the dual-clock system)
• Minimum execution time: 0.32 µs at 12.5 MHz /3.5 V to 5.5 V
(Continued)
■ PACKAGES
80-pin Plastic LQFP
80-pin Plastic QFP
80-pin Plastic LQFP
80-pin Ceramic MQFP
FPT-80P-M05
FPT-80P-M06
FPT-80P-M11
MQP-80C-P01
MB89560A Series
(Continued)
• I2C interface circuit
• LCD controller/driver: 24 segments x 4 commons (Max 96 pixels, duty LCD mode and Static LCD mode)
• LCD booster function (option)
• Wild register (Max 6 different address locations)
• 10-bit A/D converter: 8 channels
• Three types of Serial Interface:
High Speed UART (Transfer rate from 300 bps to 192000 bps /10 MHz main clock)
8-bit Serial I/O (SIO)
UART/SIO
• Two type of Programmable Pulse Generator(PPG): 6-bit PPG and 12-bit PPG
• Six types of timer
8-bit PWM 2 channels timers
8/16-bit timer/counter (8 bits x 2 channels or 16 bits x 1 channel)
21-bit timebase timer
8-bit PWC timer operation
17-bit Watch prescaler
Watch-dog timer
• I/O ports: Max 50 channels
• External interrupt 1: 8 channels
• External interrupt 2 (wake-up function): 4 channels
• Low-power consumption modes (stop mode, sleep mode, and watch mode)
• LQFP-80 and QFP-80 package
• CMOS technology
2
MB89560A Series
■ PRODUCT LINEUP
Part number
MB89567A
MB89567AC
MB89P568
MB89PV560
Parameter
Mass production products
(mask ROM products)
Classification
OTP
Piggy-back
32 K x 8-bit
(internal mask ROM)
48 K x 8-bit
(internal PROM)
56 K x 8-bit
(external ROM)
ROM size
RAM size
1 K x 8-bit
1 K x 8-bit
Number of instructions
: 136
Instruction bit length
Instruction length
Data bit length
: 8-bit
: 1 to 3 bytes
: 1-, 8-, 16-bit
CPU functions
Minimum execution time
Minimum interrupt processing time
: 0.32 µs/12.5 MHz
: 2.88 µs/12.5 MHz
General-purpose I/O ports (N-channel open drain): 20 pins (2 shared with I2C inputs,
16 shared with LCD, 2 shared with other
resources)
Ports
General-purpose I/O ports (CMOS)
Total
: 30 pins (shared with resources)
: 50 pins
21-bit timebase
timer
21-bit
Interrupt cycle: (213, 215, 218 or 222)/FCH*7
Watchdog timer
Reset generate cycle: Min 221/FCH*7 for main clock, Min 214/FCL*7 for sub clock
17-bit
Watch prescaler
Interrupt cycle: 31.25 ms, 0.25 s, 0.50 s, 1.00 s, 2.00 s, 4.00 s/32.768 kHz for subclock
Can be operated either as a 2-channel 8-bit timer/counter (Timer 1 and Timer 2, each with its
own independent operating clock cycle), or as one 16-bit timer/counter
In Timer 1 or 16-bit timer/counter operation, event counter operation (external clock-triggered)
and square wave output capable
8/16-bit timer/
counter
8-bit interval timer operation (square wave output capable, operating clock cycle: 1 tinst, 8 tinst,
16 tinst, 64 tinst)
8-bit resolution PWM operation (conversion cycle: 128 x 1 tinst to 256 x 64 tinst)
8/16-bit timer/counter output for counter clock selectability
8-bit PWM 2 ch
timer
8-bit timer operation (count clock cycle: 1 tinst, 4 tinst, 32 tinst)
8-bit reload timer operation (toggle output possible, operating clock cycle: 1 to 32 tinst)
8-bit pulse width measurement (continuous measurement possible: H-width, L-width, rising
edge to rising edge, falling edge to falling edge, and rising edge to falling edge)
PWC timer
10-bit resolution × 8 channels
A/D conversion function (conversion time: 60 tinst)
Continuous activation by an 8/16-bit timer/counter output or a timebase timer output capable.
10-bit A/D
converter *2
Internal 6-bit counter
Pulse width and cycle are program selectable
6-bit PPG
Internal 12-bit counter
Pulse width and cycle are program selectable
12-bit PPG
(Continued)
3
MB89560A Series
(Continued)
Part number
MB89567A
MB89567AC
MB89P568
MB89PV560
Parameter
Not
I2C interface*4
1 channel
Available
Transfer data length: 4-, 6-, 7-, 8-bit
High speed UART Transfer rate (300 bps to 192000 bps /9.216 MHz main clock)
support sub-clock mode
Transfer data length: 7-, 8-bit for UART, 8-bit for SIO
UART/SIO
Transfer rate (1201 bps to 78125 bps / 10 MHz main clock)
support sub-clock mode
8-bit, LSB first/MSB first selectability
Transfer clocks (one external shift clock, three internal shift clocks: 2 tinst, 8 tinst, 32 tinst) *5
8-bit serial I/O
Common output: 4 (Max)
Segment output: 24 (Max)
LCD driving power (bias) pins: 4
LCD
LCD display RAM size: 12 bytes (24 × 4 bits, Max 96 pixels)
Duty LCD mode and Static LCD mode
Booster for LCD driving: option*1
Dividing resistor for LCD driving: option
Maximum of 6-byte data can be assigned in 6 different address.
Used to replace any data in the ROM when specific address and data are assigned in Wild
register.
Wild register
Wild register can be set up by using different communication methods through the device.
External interrupt 8 independent channels (interrupt vector, request flag, request output enable)
1 (wake-up
function)
Edge selectability (rising/falling)
Used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.)
External interrupt 4 channels (“L” level interrupts, independent input enable).
2 (wake-up
function)
Used also for wake-up from stop/sleep mode. (Low-level detection is also permitted in stop
mode.)
Standby mode
Process
Sub clock mode, sleep mode, stop mode and clock mode
CMOS
2.7 V to 5.5 V*3
Operating voltage *6
2.2 V to 5.5 V
2.7 V to 5.5 V
*1 : When booster is used, the bias is reduced by 1/3. It can be selected by mask option.
*2 : Voltage varies with product.
*3 : When external ROM is used, EPROM: MBM27C512-20 should be used, the operating voltage: 4.5 V to 5.5 V.
*4 : I2C is complied to Intel Corp. System Management Bus Rev. 1.0 specification and to the Philips I2C specification.
*5 : 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock
if main clock mode is selected, or 1/2 of the subclock if subclock mode is selected.
*6 : Varies with conditions such as the operating frequency. (See “■ELECTRICAL CHARACTERISTICS.”)
*7 : FCH : main clock source oscillation, FCL : sub clock source oscillation
4
MB89560A Series
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89567A
Package
MB89P568-101
MB89P568-102
MB89PV560-101
MB89PV560-102
MB89567AC
FPT-80P-M05
FPT-80P-M06
FPT-80P-M11
MQP-80C-P01
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the OTPROM (one-time PROM) products, verify its differences from the product that
will actually be used. Take particular care on the following points:
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
• For the MB89PV560, add the current consumed by the EPROM mounted in the piggy-back socket.
• When operating at low speed, the current consumed by the one-time PROM product is greater than that for
the mask ROM product. However, the current consumption is roughly the same in sleep or stop mode.
• For more information, see “■ ELECTRICAL CHARACTERISTICS.”
3. Mask Options
The functions available as options and the method of specifying options differ between products.
Before using options check “■ MASK OPTIONS.”
4. Wild register function
The Wild Register can be used in the following address spaces.
Device
Address Space
MB89PV560
4000H to FFFFH
4000H to FFFFH
8000H to FFFFH
MB89P568
MB89567A/567AC
5. P40, P41
It will take about 64 count clock of external oscillation to initialize P40 and P41 pins in MB89PV560/P568.
Therefore, these ports will be unstable for a while during power-on. For MB89567A/567AC, these ports will be
in High-Z during power-on.
5
MB89560A Series
■ PIN ASSIGNMENT
(Top view)
SEG07
P50/SEG08
P51/SEG09
P52/SEG10
P53/SEG11
P54/SEG12
P55/SEG13
P56/SEG14
P57/SEG15
P60/SEG16
P61/SEG17
P62/SEG18
Vss
P63/SEG19
P64/SEG20
P65/SEG21
P66/SEG22
P67/SEG23
AVR
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P44/UCK/SCK1
P43/PWM2/PPG2
P42/PWM1/EC1
P41/HCK*1/TO12
P40/WTO/TO11
P31/SDA
P30/SCL
Vcc
9
P27/INT23
P26/INT22
P25/INT21
P24/INT20
P23/PPG1
P22/SCK
P21/SO
P20/SI
X1
X0
MODA
10
11
12
13
14
15
16
17
18
19
20
AVcc
X1A
(FPT-80P-M05)
(FPT-80P-M11)
*1: Main clock divided by two output
*2: For built-in LCD booster only
Note: For mask option of *2, please refer to “■ MASK OPTIONS”.
(Continued)
6
MB89560A Series
(Top view)
SEG05
SEG06
SEG07
1
2
3
4
5
6
7
8
64
P46/UI/SI1
P45/UO/SO1
P44/UCK/SCK1
P43/PWM2/PPG2
P42/PWM1/EC1
P41/HCK*1/TO12
P40/WTO/TO11
P31/SDA
P30/SCL
Vcc
P27/INT23
P26/INT22
P25/INT21
P24/INT20
P23/PPG1
P22/SCK
P21/SO
P20/SI
X1
X0
MODA
X1A
X0A
RST
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P50/SEG08
P51/SEG09
P52/SEG10
P53/SEG11
P54/SEG12
P55/SEG13
P56/SEG14
P57/SEG15
P60/SEG16
P61/SEG17
P62/SEG18
Vss
P63/SEG19
P64/SEG20
P65/SEG21
P66/SEG22
P67/SEG23
AVR
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AVcc
P07/AN7
P06/AN6
(FPT-80P-M06)
*1: Main clock divided by two output
*2: For built-in LCD booster only
Note: For mask option of *2, please refer to “■ MASK OPTIONS”.
(Continued)
7
MB89560A Series
(Continued)
(Top view)
SEG05
SEG06
SEG07
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P46/UI/SI1
P45/UO/SO1
P44/UCK/SCK1
P43/PWM2/PPG2
P42/PWM1/EC1
P41/HCK*1/TO12
P40/WTO/TO11
P31/SDA
P30/SCL
Vcc
P27/INT23
P26/INT22
P25/INT21
P24/INT20
P23/PPG1
P22/SCK
P21/SO
P20/SI
X1
X0
MODA
X1A
X0A
RST
3
*
P50/SEG08
P51/SEG09
P52/SEG10
P53/SEG11
P54/SEG12
P55/SEG13
P56/SEG14
P57/SEG15
P60/SEG16
P61/SEG17
P62/SEG18
Vss
P63/SEG19
P64/SEG20
P65/SEG21
P66/SEG22
P67/SEG23
AVR
101
102
103
104
105
106
107
108
109
93
92
91
90
89
88
87
86
85
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AVcc
P07/AN7
P06/AN6
(MQP-80C-P01)
*1: Main clock divided by two output
*2: For built-in LCD booster only
*3: Pin assignment on package top (MB89PV560 only)
Pin no.
Pin
Pin no.
Pin
Pin no.
Pin
Pin no.
Pin
81
N.C.
89
AD2
97
N.C.
105
106
107
108
109
110
111
112
OE
82
83
84
85
86
87
88
A15
A12
AD7
AD6
AD5
AD4
AD3
90
91
92
93
94
95
96
AD1
AD0
N.C.
O1
98
04
O5
O6
07
N.C.
A11
A9
99
100
101
102
103
104
A8
O2
O8
CE
A10
A13
A14
VCC
O3
VSS
N.C.: Internally connected. Do not use.
Note: For mask option of *2, please refer to “■ MASK OPTIONS”.
8
MB89560A Series
■ PIN DESCRIPTION
Pin no.
I/O circuit
type
LQFP*1 MQFP*3
Pin name
Function
LQFP*2
QFP*4
43
45
X0
X1
Crystal or other resonator connector pins for the main clock.
The external clock can be connected to X0. When this is done,
be sure to leave X1 open.
A
C
44
46
Memory access mode setting pins.
Connect directly to VSS.
Hysteresis input type.
42
44
MODA
RST
Reset I/O pin
This pin is a CMOS output type with a pull-up resistor, and a
hysteresis input type.
39
41
D
“L” is output from this pin by an internal reset request (optional).
The internal circuit is initialized by the input of “L”.
General-purpose CMOS I/O ports
P24/INT20
to
P27/INT23
Also serve as an external interrupt 2 input (wake-up function).
External interrupt 2 input is hysteresis input.
Selectable pull-up resistor.
49 to 52 51 to 54
30 to 36, 32 to 38,
E
E
General-purpose CMOS I/O ports
P10/INT10
to
P17/INT17
Also serve as input for external interrupt 1 input.
External interrupt 1 input is hysteresis input.
Selectable pull-up resistor.
38
40
General-purpose CMOS I/O ports
Also serve as the clock I/O for the High-speed UART and Serial
I/O.
The peripheral is a hysteresis input type.
Selectable pull-up resistor.
P44/UCK/
SCK1
60
62
E
General-purpose CMOS I/O ports
Also serves as the data output for the High-speed UART and
Serial I/O.
P45/UO/
SO1
61
62
63
64
F
N-ch open drain general-purpose I/O ports
Also serves as the data input for the High-speed UART and Serial I/O.
The peripheral is a hysteresis input type.
P46/UI/SI1
P47/PWC
G
N-ch open drain general-purpose I/O port
Also serve as the external clock input for PWC.
The peripheral is a hysteresis input.
63
56
65
58
G
F
General-purpose CMOS I/O port
Also serves as an 8/16-bit timer/counter output and PWC output.
P40/WTO/
TO11
(Continued)
9
MB89560A Series
Pin no.
I/O circuit
LQFP*1
LQFP*2
MQFP*3
QFP*4
Pin name
Function
type
General-purpose CMOS I/O port
P41/HCK/
TO12
Also serves as an 8/16-bit timer/counter output.
and half of main clock output
57
59
F
Selectable pull-up resistor.
General-purpose CMOS I/O port
Also serves as the data input for the serial I/O.
The peripheral is a hysteresis input type.
Selectable pull-up resistor.
45
46
47
48
47
48
49
50
P20/SI
P21/SO
E
F
E
F
General-purpose CMOS I/O port
Also serves as the data output for the serial I/O.
Selectable pull-up resistor.
General-purpose CMOS I/O port
Also serves as the clock I/O for the serial I/O.
The peripheral is a hysteresis input type.
Selectable pull-up resistor.
P22/SCK
P23/PPG1
General-purpose CMOS I/O port
Also serves as the 6 bit PPG output pin.
Selectable pull-up resistor.
N-ch open-drain general-purpose I/O port
Clock I/O pin for I2C interface
54
55
56
57
P30/SCL
P31/SDA
G
G
N-ch open-drain general-purpose I/O port
Data I/O pin for I2C interface
65
64
67
66
C0
C1
Function as capacitor connection pin in the products with a
booster.
—
F
General-purpose CMOS I/O port
P43/
PWM2/
PPG2
Also serves PWM wave output for the 8-bit PWM timer 1 and
as 12 bit programmable pulse generator output.
Selectable pull-up resistor.
59
61
General-purpose CMOS I/O port
Also serves as the PWM wave output and external clock for
the 8/16 bit timer counter.
P42/
PWM1/
EC1
58
60
E
J
Selectable pull-up resistor.
P00/AN0
to
P07/AN7
General-purpose CMOS I/O ports
Also serve as the analog input for the A/D converter.
Selectable pull-up resistor.
21 to 28
23 to 30
(Continued)
10
MB89560A Series
(Continued)
Pin no.
I/O circuit
type
LQFP*1
LQFP*2
MQFP*3
QFP*4
Pin name
Function
P60/
SEG16 to
P67/
10 to 12
14 to 18
12 to 14
16 to 20
N-ch open-drain general-purpose output ports
Also serve as an LCD controller/driver segment output.
H
H
SEG23
P50/SEG8
to
N-ch open-drain general-purpose output ports
Also serve as an LCD controller/driver segment output.
2 to 9
4 to 11
P57/
SEG15
1 to 3
76 to 80
SEG0 to
SEG7
74 to 80, 1
70 to 73
I
I
LCD controller/driver segment output-only pins
LCD controller/driver common output-only pins
COM0
to
COM3
72 to 75
68 to 71
66 to 69
V0 to V3
—
B
LCD driving power supply pins.
40
41
53
37
13
20
19
42
43
55
39
15
22
21
X0A
X1A
Vcc
C
Crystal or other resonator connector pins for the subclock
(Subclock: 32.768 kHz)
—
—
—
—
—
Power supply pin
Capacitor connection pin *5
Vss
AVcc
AVR
Power supply (GND) pin
A/D converter power supply pin
A/D converter reference voltage input pin
A/D converter power supply pin
Use this pin at the same voltage as VSS.
29
31
AVss
—
*1: FPT-80P-M05
*2: FPT-80P-M11
*3: MQP-80C-P01
*4: FPT-80P-M06
*5: When MB89567A / MB89567AC / MB89PV560-101 / MB89PV560-102 is used, this pin will become NC pin
without internal connection. There is no problem to leave pins open, to fix pins at VCC and to fix pins at VSS.
When MB89P568-101 or MB89P568-102 is used, this pin must be connected to VSS.
11
MB89560A Series
• For External EPROM Socket (MB89PV560 ONLY)
Pin no.
Pin name
I/O
Function
82
83
84
85
86
87
88
89
90
91
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins
93
94
95
O1
O2
O3
I
Data input pins
96
Vss
O
Power supply (GND) pin
Data input pins
98
99
100
101
102
O4
O5
O6
O7
O8
I
ROM chip enable pin
Outputs “H” during standby.
103
104
105
CE
A10
O
O
O
Address output pin
ROM output enable pin
Outputs “L” at all times.
OE/Vpp
107
108
109
A11
A9
A8
O
Address output pins
110
111
112
A13
A14
Vcc
O
O
O
EPROM power supply pin
81
92
97
Internally connected pins
Be sure to leave them open.
N.C.
—
106
12
MB89560A Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
Main clock (main clock crystal oscillator)
• At an oscillation feedback resistor of
approximately 1 MΩ/5.0 V
X1
Nch Pch
Pch
X0
A
Nch
Main clock control signal
Subclock (subclock crystal oscillator)
• At an oscillation feedback resistor of
approximately 4.5 MΩ/5.0 V
X1A
Nch Pch
X0A
B
C
Nch
Sub clock control signal
• Hysteresis input
• CMOS output
• Hysteresis input
R
• At an output pull-up resistor (P-ch)
of approximately 50 kΩ/5.0 V
Pch
D
Nch
• CMOS output
• CMOS input
• The peripheral is a hysteresis input
type.
• Selectable pull-up resistor (P-ch) of
approximately 50 kΩ/5.0 V
R
Pull-up control
register
Pch
Pch
Nch
E
Port
Peripheral
(Continued)
13
MB89560A Series
(Continued)
Type
Circuit
Remarks
• CMOS output
• CMOS input
• Selectable pull-up resistor (P-ch) of
approximately 50 kΩ/5.0 V
Pull-up resistor
control register
R
Pch
Pch
Nch
F
Port
• N-ch open-drain input/output
• CMOS input
• The peripheral is a hysteresis input
Nch
type.
G
(P30,P31 are OR-type input for I2C)
Port
Peripheral
• N-ch open-drain output
• CMOS input
• LCD controller/driver segment
output
Pch
Nch
Pch
Nch
H
Nch
Port
• LCD controller/driver common/
segment output
Pch
Nch
I
Pch
Nch
• General CMOS I/O
• Analog input (A/D converter)
• Selectable pull-up resistor (P-ch) of
approximately 50 kΩ/5.0 V
• Pull-up resistors must be disabled
when used as an analog input.
R
Pull-up control
register
Pch
Pch
Nch
J
Port
ADEN
Analog input
14
MB89560A Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in “■ ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DVCC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the
transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power
is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up
from stop mode.
7. Unused LCD dedicated pins
When LCD dedicated pins are not in use, keep it open.
8. Ports shared with SEG pin
When using port shared with SEG pin, be sure that the input voltage to port does not exceed the voltage of V3
(SEG driving voltage). This is particularly important to those devices with booster. When power-on or reset, SEG
pin will output an initial value of “L”.
9. LCD not in use
When LCD is not in use, connect the V3 pin to Vcc and keep other LCD dedicated pins open.
10. Wild Register function
In MB89PV560, wild register function cannot be evaluated. To evaluate the wild register function, use MB89P568.
11. Programming operation on RAM
Program operation debugging at RAM is not possible even when using MB89PV560.
12. Note to Noise in the External Reset Pin (RST)
If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunc-
tions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST) .
15
MB89560A Series
■ PROGRAMMING TO THE EPROM ON THE MB89P568
The MB89P568 is an OTPROM version of the MB89567A and MB89567AC.
1. Features
• 48-Kbyte PROM on chip
• Equivalency to the MBM27C1001 in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in EPROM mode is diagrammed below.
EPROM mode
(Corresponding addresses on
the EPROM programmer)
Normal operation
0000 H
I/O
0080 H
0480 H
RAM
Not available
4000 H
FFFF H
4000 H
Program
area
(PROM)
Program
area
(PROM)
FFFF H
3. Programming to the EPROM
In EPROM mode, the MB89P568 functions equivalent to the MBM27C1001. This allows the PROM to be pro-
grammed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using
the dedicated socket adapter.
• Programming procedure
(1) Set the EPROM programmer to the MBM27C1001.
(2) Load program data into the EPROM programmer at 4000H to FFFFH
(3) Program with the EPROM programmer.
16
MB89560A Series
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure.
Program, verify
Program, verify
+100 °C, 48 h
Read
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Package
Compatible socket adapter
FPT-80P-M05
FPT-80P-M06
FPT-80P-M11
ROM-80SQF-32DP-8LA
ROM-80QF-32DP-8LA2
ROM-80QF2-32DP-8LA2
Inquiry: San Hayato Co., Ltd.: FAX +81-3-5396-9106 (Tokyo)
17
MB89560A Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C512-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
Adapter socket part number
LCC-32 (Rectangle)
ROM-32LC-28DP-YG
Inquiry: San Hayato Co., Ltd.: FAX +81-3-5396-9106 (Tokyo)
3. Memory Space
EPROM mode
(Corresponding addresses on
the EPROM programmer)
Normal operation
0000 H
I/O
0080 H
RAM
0480 H
Not available
2000 H
2000 H
Program area
(PROM)
Program area
(PROM)
FFFF H
FFFF H
4. Programming to EPROM
(1) Set the EPROM programmer to the MBM27C512.
(2) Load program data into the EPROM programmer at 2000H to FFFFH.
(3) Program to 2000H to FFFFH with the EPROM programmer.
18
MB89560A Series
■ BLOCK DIAGRAM
I2C*2
P30/SCL
P31/SDA
Main clock
X0
X1
Oscillator
N-ch open drain I/O port
SIO
Clock controller
P40/WTO/TO11
P41/HCK*1/TO12
P42/PWM1/EC1
High-speed
UART
Subclock
Low-power oscillator
(32.768 kHz)
X0A
X1A
12 bit PPG
Watch prescaler
P43/PWM2/PPG2
PWC
4
Reset circuit
(Watchdog timer)
*
8-bit
RST
timer/counter 1
(Timer 1)
P44/UCK/SCK1
P45/UO/SO1
*4
21-bit Time-base
timer
8-bit
timer/counter 2
(Timer 2)
8
8
P10/INT10
External interrupt 1
CMOS I/O port
8-bit PWM timer 2
8-bit PWM timer 1
to P17/INT17
P46/UI/SI1
P47/PWC
CMOS I/O port
(P46 and P47 are N-ch
Open-drain I/O Type)
6 bit PPG
P24/INT20
to P27/INT23
4
4
External interrupt 2
(wake-up function)
4
N-ch open-drain
output port
P60/SEG16 to
P63/SEG19
P64/SEG20 to
P67/SEG23
P23/PPG1
4
8
P20/SI
P21/SO
P22/SCK
UART/SIO
4
4
8
LCD controller/
P50/SEG8 to
P53/SEG11
driver
CMOS I/O port
P54/SEG12 to
P57/SEG15
8
Display RAM
(12 bytes)
SEG0 to SEG7
COM0 to COM3
V0 to V3
1K Byte RAM
4
4
2
F MC-8L
CPU
C0*3
Option
C1*3
Booster
Wild register
CMOS I/O port
8
P00/AN0
to P07/AN7
32K*6 Byte ROM
8
Other pins
MODA, C,*5 VCC, VSS
10-bit A/D converter
AVCC
AVSS
AVR
*1: Output of Main clock/2.
*2: I2C is not available in MB89567A.
*3: Selected by mask option
*4: Can be used as a 16-bit timer/counter by connecting Timer 1 output to Timer 2 input.
*5: C pin becomes NC pin in MB89567A/AC/PV560
*6: 48 K byte ROM for MB89P568
19
MB89560A Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89560A series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located the lowest address. The data area is provided immediately above the I/
O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89560A series is structured as illustrated below.
Memory space
MB89P568-101,102
MB89PV560-101,102
MB89567A, MB89567AC
0000 H
0000 H
0000 H
I/O
I/O
I/O
0080 H
0080 H
0100 H
0080 H
0100 H
RAM
RAM
RAM
0100 H
0200 H
Register
Register
Register
0200 H
0480 H
0492 H
0200 H
0480 H
0480 H
0492 H
*2
*2
*2
0492 H
Access
prohibited
Access
prohibited
Access
prohibited
2000 H
4000 H
External*1
ROM
8000 H
External*1
ROM
ROM
FFC0H
FFFF H
FFC0H
FFFF H
FFC0H
FFFF H
Vector table
(Reset • Interrupt • Vector call instruction)
*1 : MB89P568-101,102 has OTP ROM inside.
*2 : Wild register setting registers
20
MB89560A Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following registers are provided:
Program counter (PC)
Accumulator (A)
: A 16-bit register for indicating specifies instruction storage positions.
: A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator when
the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX)
Extra pointer (EP)
Stack pointer (SP)
Program status (PS)
: A 16-bit register for index modification
: A 16-bit pointer for indicating a memory address
: A 16-bit register for indicating a stack area
: A 16-bit register for storing a register pointer, a condition code
16 bits
Initial value
FFFDH
: Program counter
: Accumulator
P C
A
Undefined
: Temporally accumulator
: Indexing register
Undefined
Undefined
I X
: Extra pointer
Undefined
Undefined
E P
S P
P S
: Stuck pointer
: Program status
I Flag = 0, IL1, 0 = 11
other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
• Structure of program status
15
14
13
12
11
10
9
8
7
6
I
5
4
3
2
1
0
Va- Va-
cancy cancy cancy
Va-
RP
PS
H
IL1 IL0
N
Z
V
C
RP
CCR
21
MB89560A Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
• Rule for Conversion of Actual Addresses of the General-purpose Register Area
Operation Code
RP Upper
lower
b0
"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 b1
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Generated address
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag : Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag : Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
0
IL0
0
Interrupt level
High-low
High
1
0
1
1
0
2
3
1
1
Low = no interrupt
N-flag : Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag : Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag : Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag : Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
The following general-purpose registers are provided :
General-purpose registers : An 8-bit resister for storing data
22
MB89560A Series
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers. Up to a total of 32 banks can be used. The bank currently in use is indicated by the register bank
pointer (RP).
• Register Bank Configuration
This address = 0100H+8× (RP)
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
32 bank (MB89567A/567AC)
Memory range
23
MB89560A Series
■ I/O MAP
Address
00H
Register name
PDR0
Register Description
Port 0 data register
Read/Write
Initial value
XXXXXXXXB
00000000B
R/W
W
01H
DDR0
Port 0 data direction register
Port 1 data register
02H
PDR1
R/W
W
XXXXXXXXB
00000000B
03H
DDR1
Port 1 data direction register
04H to 06H
07H
(Vacancy)
SYCC
STBC
WDTC
TBTC
WPCR
PDR2
DDR2
PDR3
PDR4
DDR4
PDR5
System clock control register
Standby control register
Watchdog timer control register
Timebase timer control register
Watch prescaler control register
Port 2 data register
R/W
R/W
W
XXXMM100B
00010XXXB
0XXXXXXXB
00XXX000B
00XX0000B
XXXXXXXXB
00000000B
XXXXXX11B
XXXXXXXXB
XX000000B
00000000B
08H
09H
0AH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0BH
0CH
0DH
Port 2 data direction register
Port 3 data register
0EH
0FH
Port 4 data register
10H
Port 4 direction register
Port 5 data register
11H
12H
(Vacancy)
13H
PDR6
Port 6 data register
R/W
00000000B
14H to 19H
1AH
(Vacancy)
T2CR
T2DR
T1CR
T1DR
Timer2 control register
Timer2 data register
R/W
R/W
R/W
R/W
X00000X0B
XXXXXXXXB
X00000X0B
XXXXXXXXB
1BH
1CH
Timer1 control register
Timer1 data register
1DH
1EH to 21H
22H
(Vacancy)
SMC11
SRC1
SSD1
UART1 mode control register 1
UART1 mode data register
UART1 status/data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
00000000B
XX011000B
00100X1XB
XXXXXXXXB
XX100001B
00000000B
000X0000B
X000XXXXB
XXXXXXXXB
XXXXXXXXB
000XX000B
23H
24H
25H
SIDR1/SODR1 UART1 data register
26H
SMC12
CNTR1
CNTR2
CNTR3
COMR1
COMR2
PCR1
UART1 mode control register 2
27H
PWM control register 1
28H
PWM control register 2
29H
PWM control register 3
2AH
PWM compare register 1
PWM compare register 2
PWC pulse width control register 1
2BH
W
2CH
R/W
(Continued)
24
MB89560A Series
Address
2DH
2EH
Register name
PCR2
Register Description
PWC pulse width control register 2
PWC reload buffer register
Read/Write
R/W
Initial value
00000000B
XXXXXXXXB
00000000B
00000000B
00001XXXB
XXXXXXXXB
XXXXXXXXB
X00000X0B
X0000001B
XXXXXXXXB
XXXXXXXXB
00000000B
0X000000B
XX000000B
XX000000B
RLBR
R/W
2FH
SMC21
SMC22
SSD2
UART2/SIO mode control register
UART2/SIO mode control register 2
UART2/SIO status/data register
R/W
30H
R/W
31H
R/W
32H
SIDR2/SODR2 UART2/SIO data register
R/W
33H
SRC2
ADC1
UART2/SIO rate control register
A/D control register 1
R/W
34H
R/W
35H
ADC2
A/D control register 2
R/W
36H
ADDL
A/D data register L
R/W
37H
ADDH
RCR21
RCR23
RCR22
RCR24
A/D data register H
R/W
38H
PPG control register 1(PPG2)
PPG control register 3(PPG2)
PPG control register 2(PPG2)
PPG control register 4(PPG2)
(Vacancy)
R/W
39H
R/W
3AH
R/W
3BH
R/W
3CH to 3EH
3FH
EIC1
EIC2
EIC3
EIC4
External interrupt 1 control register 1
External interrupt 1 control register 2
External interrupt 1 control register 3
External interrupt 1 control register 4
(Vacancy)
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
40H
41H
42H
43H to 50H
51H
IBSR
IBCR
ICCR
IADR
IDAR
EIE2
I2C bus status register
R
00000000B
00000000B
000XXXXXB
XXXXXXXXB
XXXXXXXXB
XXXX0000B
XXXXXXX0B
00000000B
0X000000B
00000000B
00010000B
00000000B
XX000000B
XXXXXXXXB
(Continued)
52H
I2C bus control register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
53H
I2C clock control register
54H
I2C address register
55H
I2C data register
56H
External interrupt 2 enable register
External interrupt 2 flag register
PPG control register 1(PPG1)
PPG control register 2(PPG1)
Clock Output control register
LCD controller/driver control register 1
LCD controller/driver control register 2
LCD controller/driver control register 3
LCD data register 1
57H
EIF2
58H
RCR1
RCR2
CKR
59H
5AH
5BH
LCR1
LCR2
LCR3
LDR1
5CH
5DH
5EH
25
MB89560A Series
(Continued)
Address
5FH
Register name
Register Description
Read/Write
Initial value
(Vacancy)
60H to 6BH
6CH to 6FH
70H
VRAM
Display RAM
R/W
XXXXXXXXB
(Vacancy)
SMR
SDR
Serial I/O mode register
Serial I/O data register
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
XXXXXXXXB
11111111B
11111111B
11111111B
XX111111B
71H
72H
PURR0
PURR1
PURR2
PURR4
Pull-up resistor register 0
Pull-up resistor register 1
Pull-up resistor register 2
Pull-up resistor register 4
73H
74H
75H
76H
(Vacancy)
77H
WREN
WROR
ADEN
Wild register enable register
Wild register data test register
A/D port input enable register
R/W
R/W
R/W
XX000000B
XX000000B
11111111B
78H
79H
7AH
(Vacancy)
7BH
ILR1
ILR2
ILR3
ILR4
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Interrupt level setting register 4
W
W
W
W
11111111B
11111111B
11111111B
11111111B
7CH
7DH
7EH
Access
Prohibited
7FH
ITR
Interrupt test register
11111111B
Read/write access symbols
R/W : Readable and writable
R
W
: Read-only
: Write-only
Initial value symbols
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
M : The initial value of this bit is determined by mask option.
Note : Do not use vacancies.
26
MB89560A Series
■ WILD REGISTER I/O MAP
Address
480H
481H
482H
483H
484H
485H
486H
487H
488H
489H
48AH
48BH
48CH
48DH
48EH
48FH
490H
491H
Register name
WRARH1
WRARL1
WRDR1
Register description
Wild register high-byte address register1
Wild register low-byte address register1
Wild register data register1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
WRARH2
WRARL2
WRDR2
Wild register high-byte address register2
Wild register low-byte address register2
Wild register data register2
WRARH3
WRARL3
WRDR3
Wild register high-byte address register3
Wild register low-byte address register3
Wild register data register3
WRARH4
WRARL4
WRDR4
Wild register high-byte address register4
Wild register low-byte address register4
Wild register data register4
WRARH5
WRARL5
WRDR5
Wild register high-byte address register5
Wild register low-byte address register5
Wild register data register5
WRARH6
WRARL6
WRDR6
Wild register high-byte address register6
Wild register low-byte address register6
Wild register data register6
Read/write access symbols
R/W : Readable and writable
R
W
: Read-only
: Write-only
Initial value symbols
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
M : The initial value of this bit is determined by mask option.
Note : Do not use vacancies.
27
MB89560A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Rating
Symbol
Unit
Remarks
Parameter
Min
Max
VCC
AVCC
MB89567A, MB89567AC,
VSS – 0.3 VSS + 6.0
VSS – 0.3 VSS + 6.0
V
V
V
V
V
Power supply voltage
MB89P568 and MB89PV560*1
AVR must not exceed “AVcc + 0.3V”.
AVR
V0 to V3 should not exceed Vcc
Without booster
LCD power voltage
Program voltage
V0 to V3 VSS – 0.3 VSS + 6.0
VPP
VSS – 0.6 VSS +13.0
VSS – 0.3 VCC + 0.3
Only for the MB89P568
For pins other than P30, P31, P46,
P47, P50 to P57 and P60 to P67
P50 to P57, P60 to P67
Resister Ladder option
VSS – 0.3 VCC + 0.3
V
Input voltage
VI
P50 to P57, P60 to P67
LCD booster option
VSS – 0.3
V3
V
V
V
VSS – 0.3 VSS + 6.0
VSS – 0.3 VCC + 0.3
For P30, P31, P46, P47
For pins other than P30, P31, P46,
P47, P50 to P57 and P60 to P67
P50 to P57, P60 to P67
Resister Ladder option
VSS – 0.3 VCC + 0.3
V
Output voltage
VO
P50 to P57, P60 to P67
LCD booster option
VSS – 0.3
V3
V
V
VSS – 0.3 VSS + 6.0
For P30, P31, P46, P47
15
30
4
mA For pins other than P20 to P27
mA For P20 to P27 only
“L” level maximum output current
“L” level average output current
IOL
mA For pins other than P20 to P27*2
mA For P20 to P27 only*2
IOLAV
15
“L” level total maximum output
current
∑IOL
100
60
mA
“L” level total average output
current
∑IOLAV
mA *2
For pins other than P20 to P27, P30,
mA P31, P46, P47, P50 to P57, P60 to
P67
– 15
“H” level maximum output current
“H” level average output current
IOH
– 30
– 4
mA For P20 to P27 only
For pins other than P20 to P27*2
IOHAV
mA
– 15
For P20 to P27 only*2
(Continued)
28
MB89560A Series
(Continued)
(AVSS = VSS = 0.0 V)
Rating
Symbol
Unit
Remarks
Parameter
Min
Max
“H” level total maximum output
current
∑IOH
– 50
mA
“H” level total average output
current
∑IOHAV
– 30
mA *2
Power consumption
Operating temperature
Storage temperature
PD
TA
300
+ 85
mW
°C
– 40
– 55
Tstg
+ 150
°C
*1 : Use AVCC and VCC set at the same voltage.
Take care so that AVR does not exceed AVCC + 0.3 V, such as when power is turned on.
Take care so that AVCC does not exceed VCC, such as when power is turned on.
*2 : Average value (operating current × operating rate)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
29
MB89560A Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min
Max
2.2*
5.5*
V
V
V
V
For MB89567A and MB89567AC
Retains the RAM state in stop mode
for MB89567A and MB89567AC
1.5
5.5
5.5*
5.5
VCC
AVCC
Power supply voltage
2.7*
1.5
For MB89PV560 and MB89P568
Retains the RAM state in stop mode
for MB89PV560 and MB89P568
Liquid crystal power supply range :
without booster
(The best value is according to the
specification of LCD used.)
LCD power voltage
V0 to V3
Vss
VCC
V
A/D converter reference input
voltage
AVR
TA
3.5
AVCC
+ 85
V
Operating temperature
– 40
°C
* : These values depend on the operating conditions and the analog assurance range. See Figure “Operating Voltage
vs. Main Clock Operating Frequency (MB89567A, MB89567AC) ”, “Operating Voltage vs. Main Clock Operating
Frequency (MB89P568/MB89PV560) ” and “6. A/D Converter Electrical Characteristics.”
30
MB89560A Series
“Operating Voltage vs. Main Clock Operating Frequency (MB89567A, MB89567AC) and “Operating Voltage vs.
Main Clock Operating Frequency (MB89P568/MB89PV560) indicate the operating frequency of the external oscil-
lator at an instruction cycle of 4/FCH
Operating
A/D Converter accuracy assurance range: Vcc = AVcc =3.5 V to 5.5 V
Voltage (V)
5.5
5.0
Operation assurance range
4.0
3.5
3.0
2.7
2.2
2.0
Main clock
operating Freq. (MHz)
1.0
4.0
2.0
2.0
3.0
4.0
5.0
0.8
6.0
7.0
8.0
9.0
10.0 11.0 12.0 12.5
Min execution time
(inst. cycle) (µs)
0.4
0.32
Operating Voltage vs. Main Clock Operating Frequency (MB89567A, MB89567AC)
31
MB89560A Series
Operating
Voltage (V)
A/D Converter accuracy assurance range: Vcc = AVcc = 3.5 V to 5.5 V
5.5
5.0
4.5
4.0
3.5
Operation assurance range
3.0
2.7
2.5
2.2
2.0
Main clock
operating Freq. (MHz)
Operation assurance : TA = −10 °C to +55 °C (Only for MB89P568)
1.0
4.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0 10.0 12.0 11.0 12.5
Min execution time
(inst. cycle) (µs)
2.0
0.8
0.4
0.32
Operating Voltage vs. Main Clock Operating Frequency (MB89P568/MB89PV560)
Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the
operating speed is switched using a gear.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
32
MB89560A Series
3. DC Characteristics (power supply voltage : 5.0V)
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)
Value
Parameter Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P31,
P40 to P45,
P50 to P57,
P60 to P67
VIH
—
0.7 VCC
—
VCC + 0.3
V
CMOS
RST, MODA,
“H” level
INT10 to INT17,
INT20 to INT23,
SI,SCK,EC1,UCK,
SCK1,UI,SI1,PWC
input voltage
VIHS
—
0.8 VCC
—
VCC + 0.3
V
Hysteresis
SMB input
buffer selected
VIHSMB
—
—
VSS +1.4
0.7 VCC
—
—
VSS + 5.5
VSS + 5.5
V
V
SCL, SDA
I2C input buffer
selected
VIHI2C
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P31,
P40 to P45,
P50 to P57,
P60 to P67
VIL
—
—
VSS − 0.3
—
—
0.3 VCC
0.2 VCC
V
V
CMOS
RST, MODA,
“L” level
input voltage
INT10 to INT17,
INT20 to INT23,
SI,SCK,EC1,UCK,
SCK1,UI,SI1,PWC
VILS
VSS − 0.3
Hysteresis
SMB input
buffer selected
VILSMB
VILI2C
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
—
—
—
—
—
VSS + 0.6
0.3 VCC
VCC + 0.3
V3
V
V
V
V
V
SCL, SDA
I2C input buffer
selected
—
—
—
—
P60 to P67,
P50 to P57
Resister
Ladder option
Open-drain
output pin
application
voltage
P60 to P67,
P50 to P57
LCD booster
option
VD
P46, P47, P30,
P31
VSS + 5.5
P00 to P07,
P10 to P17,
P40 to P45
“H” level
output
voltage
IOH = –2.0 mA
IOH = –15.0 mA
4.0
4.0
—
—
—
—
VOH
V
P20 to P27
(Continued)
33
MB89560A Series
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)
Value
Parameter Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
P00 to P07,
P10 to P17,
P30, P31,
P40 to P47,
P50 to P57,
P60 to P67,
RST
“L” level
output
voltage
IOL = 4.0 mA
—
—
0.4
VOL
V
P20 to P27
IOL = 15.0 mA
—
—
—
0.4
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P45
Without
µA pull-up
− 5
+5
Resistor
Inputleakage
current
(High-Z
output
leakage
current)
0.0 V < VI < VCC
Resistor
µA Ladder
option
P50 to P57,
P60 to P67
− 5
—
+5
ILI
P50 to P57,
P60 to P67
LCD booster
option
0.0 V < VI < V3
0.0 V < VI < VCC
− 5
—
—
+5
µA
µA
MB89PV560
MB89P568
MODA
− 10
+10
Resistor
µA Ladder
P50 to P57,
P60 to P67
0.0 V < VI < VCC
—
—
+5
Open-drain
output
leakage
current
option
ILIOD
P50 to P57,
P60 to P67
LCD booster
option
0.0 V < VI < V3
—
—
—
—
+5
+5
µA
µA
P30, P31,
P46, P47
0.0 V < VI < Vss
+ 5.5 V
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P45,
RST
Whenpull-up
resistor
selected
Pull-up
resistance
RPULL
VI = 0.0 V
25
50
100
kΩ
except RST
Pull-down
resistance
MB89567A/
MB89567AC
RMODA
ICC1
MODA
VI = 3.0 V
50
—
—
—
—
—
—
100
15
8
200
20
13
8.5
3
kΩ
MB89PV560
MB89P568
FCH = 10 MHz,
*2
tinst = 0.4 µs,
mA
Main clock run
mode
MB89567A
MB89567AC
MB89PV560
MB89P568
FCH = 10 MHz,
5
*2
Powersupply
current *1
tinst = 6.4 µs,
ICC2
VCC
mA
mA
Main clock run
mode
MB89567A
MB89567AC
1
MB89PV560
MB89P568
FCH = 10 MHz,
tinst*2 = 0.4 µs,
Main clock sleep
mode
5
7
ICCS1
MB89567A
MB89567AC
2.5
5
(Continued)
34
MB89560A Series
(Continued)
(AVCC = VCC = 5.0 V, , AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
MB89PV560
MB89P568
—
1.5
3
FCH = 10 MHz,
tinst*2 = 6.4 µs,
Sleep mode
ICCS2
mA
MB89567A
MB89567AC
—
—
—
—
0.7
3
2
7
MB89PV560
MB89P568
FCL = 32.768
kHz,
Subclock mode,
TA = +25 °C
mA
ICCL
MB89567A
MB89567AC
50
30
85
50
µA
FCL = 32.768
kHz,
MB89PV560
MB89P568
Power supply
current *1
VCC
ICCLS
Subclock sleep
mode,
TA = +25 °C
µA
MB89567A
MB89567AC
—
15
5
30
15
FCL = 32.768
kHz,
TA = +25 °C,
Watch mode,
Main clock stop
mode
MB89PV560
MB89P568
µA
µA
ICCT
—
MB89567A
MB89567AC
1.6
15
MB89PV560
MB89P568
3
1
10
10
µA
µA
kΩ
TA = +25 °C,
Subclock stop
mode
Power supply
current *1
ICCH
VCC
—
MB89567A
MB89567AC
LCD divided
resistance
Between
VCC and VSS
RLCD
—
300
—
500
750
COM0 to COM3
output
impedance
RVCOM COM0 to COM3
—
—
—
10
5
15
1
kΩ
kΩ
µA
pF
V1 to V3 = 5.0 V
SEG0toSEG23
output
impedance
RVSEG
ILCDL
CIN
SEG0 to SEG23
—
− 1
—
LCD controller/
driver leakage
current
V0 to V3,
COM0 to COM3,
SEG0 to SEG23
—
OtherthanAVCC,
AVSS, VCC, and
VSS
Input
capacitance
f = 1 MHz
—
*1 : The power supply current is measured at the external clock
*2 : For information on tinst, see “5. AC Characteristics (4) Instruction Cycle.”
Note : For LCD and port multiplex pin (P50 to P57, P60 to P67), please refer to LCD specification when the port is
used, and refer to LCD specification when used as LCD pin.
35
MB89560A Series
4. DC Characteristics (power supply voltage : 3.0V)
(AVCC = VCC = 3.0V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)
Value
Typ
Parameter Symbol
Pin
Condition
Unit
Remarks
Min
Max
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P31,
P40 to P45,
P50 to P57,
P60 to P67
VIH
—
0.7 VCC
—
—
VCC + 0.3
V
CMOS
RST, MODA,
“H” level
input voltage
INT10 to INT17,
INT20 to INT23,
SI,SCK,EC1,UCK,
SCK1,UI,SI1,PWC
VIHS
—
0.8 VCC
VCC + 0.3
V
Hysteresis
SMB input
buffer selected
VIHSMB
—
—
VSS +1.4
0.7 VCC
—
—
VSS + 5.5
VSS + 5.5
V
V
SCL, SDA
I2C input buffer
selected
VIHI2C
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P31,
P40 to P45,
P50 to P57,
P60 to P67
VIL
—
—
VSS − 0.3
—
—
0.3 VCC
0.2 VCC
V
V
CMOS
RST, MODA,
“L” level
input voltage
INT10 to INT17,
INT20 to INT23,
SI,SCK,EC1,UCK,
SCK1,UI,SI1,PWC
VILS
VSS − 0.3
Hysteresis
SMB input
buffer selected
VILSMB
VILI2C
—
—
—
—
—
VSS - 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
—
—
—
—
—
VSS + 0.6
0.3 VCC
VCC + 0.3
V3
V
V
V
V
V
SCL, SDA
I2C input buffer
selected
P60 to P67,
P50 to P57
Resistor
Ladder option
Open-drain
output pin
application
voltage
P60 to P67,
P50 to P57
LCD booster
option
VD
P46, P47, P30,
P31
VSS + 5.5
P00 to P07,
P10 to P17,
P40 to P45
“H” level
output
voltage
IOH = –2.0 mA
IOH = –10 mA
2.4
2.4
—
—
—
—
VOH
V
P20 to P27
(Continued)
36
MB89560A Series
(AVCC = VCC = 3.0V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)
Value
Parameter Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
P00 to P07,
P10 to P17,
P30, P31,
P40 to P47,
P50 to P57,
P60 to P67,
RST
“L” level
output
voltage
IOL = 4.0 mA
IOL = 10 mA
—
—
0.4
VOL
V
P20 to P27
—
—
—
0.4
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P45
Without
–5
+5
µA pull-up
Resister
0.0 V < VI < VCC
Inputleakage
current
(Hi-z output
leakage
Resister
µA Ladder
option
P50 to P57,
P60 to P67
–5
—
+5
ILI
current)
P50 to P57,
P60 to P67
LCD booster
option
0.0 V < VI < V3
0.0 V < VI < VCC
–5
—
—
+5
µA
µA
MB89PV560
MB89P568
MODA
–10
+10
Resister
µA Ladder
P50 to P57,
P60 to P67
0.0 V < VI < VCC
—
—
+5
Open-drain
output
leakage
current
option
ILIOD
P50 to P57,
P60 to P67
LCD booster
option
0.0 V < VI < V3
—
—
—
—
+5
+5
µA
µA
P30, P31,
P46, P47
0.0 V < VI < Vss
+ 5.5 V
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P45,
RST
Whenpull-up
resistor
selected
Pull-up
resistance
RPULL
VI = 0.0 V
50
25
100
200
kΩ
except RST
Pull-down
resistance
MB89567A
MB89567AC
RMODA
ICC1
MODA
VI = 5.0 V
50
6
100
10
9
kΩ
MB89PV560
MB89P568
FCH = 10 MHz,
—
—
*2
tinst = 0.4 µs,
mA
Main clock run
mode
MB89567A
MB89567AC
4
Powersupply
current *1
VCC
MB89PV560
MB89P568
FCH = 10 MHz,
—
—
1.5
0.4
3
*2
tinst = 6.4 µs,
ICC2
mA
Main clock run
mode
MB89567A
MB89567AC
2
(Continued)
37
MB89560A Series
(Continued)
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
MB89PV560
MB89P568
FCH = 10 MHz,
tinst*2 = 0.4 µs,
Main clock
—
2
4
ICCS1
mA
MB89567A
MB89567AC
—
—
—
—
1
1
3
2
sleep mode
MB89PV560
MB89P568
FCH = 10 MHz,
tinst*2 = 6.4 µs,
Main clock
ICCS2
mA
MB89567A
MB89567AC
0.3
1
1.5
3
sleep mode
FCL = 32.768
kHz,
MB89PV560
MB89P568
mA
ICCL
Subclock
mode,
TA = +25 °C
MB89567A
MB89567AC
—
—
—
25
15
8
60
30
25
15
µA
Power supply
current *1
VCC
FCL = 32.768
kHz,
Subclock sleep
mode ,
MB89PV560
MB89P568
ICCLS
µA
MB89567A
MB89567AC
TA = +25 °C
FCL = 32.768
kHz,
TA = +25 °C,
Watch mode,
Main clock stop
mode
MB89PV560
MB89P568
5
µA
µA
ICCT
—
MB89567A
MB89567AC
1
1
14
5
TA = +25 °C,
Subclock stop
mode
ICCH
—
µA
LCD divided
resistance
Between VCC
and VSS
RLCD
—
300
—
500
—
750
5
kΩ
kΩ
kΩ
COM0 to COM3
output impedance
RVCOM
COM0 to COM3
SEG0 to SEG23
V1 to V3 = 3.0 V
SEG0 to 23 output
impedance
RVSEG
—
—
15
V0 to V3,
COM0 to COM3,
SEG0 to SEG23
LCD controller/
driver leakage
current
ILCDL
—
–1
—
—
1
µA
OtherthanAVCC,
AVSS, VCC, and
VSS
Input
capacitance
CIN
f = 1 MHz
10
—
pF
*1 : The power supply current is measured at the external clock
*2 : For information on tinst, see “5. AC Characteristics (4) Instruction Cycle.”
Note : For LCD and port multiplex pin (P50 to P57, P60 to P67), please refer to LCD specification when the port is
used, and refer to LCD specification when used as LCD pin.
38
MB89560A Series
5. AC Characteristics
(1) Reset Timing
(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Condition
Unit
Remarks
Parameter
Min
Max
RST “L” pulse width
tZLZH
—
48 tHCYL
—
ns
Notes : • tHCYL is the oscillation cycle (1/FCH) to input to the X0 pin.
• If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause
malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external
reset pin (RST) .
t ZLZH
RST
0.2 V CC
0.2 V CC
(2) Power-on Reset
Parameter
(AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Condition
Unit
Remarks
Min
0.5
1
Max
50
Power supply rising time
Power supply cut-off time
tR
ms
—
tOFF
—
ms Due to repeated operations
Note : Make sure that power supply rises within the selected oscillation stabilization time.
For example, when the main clock is operating at 10 MHz (FCH) and the oscillation stabilization time select
option has been set to 218/FCH, the oscillation stabilization delay time is 26.2 ms. Therefore, the maximum
value of power supply rising time is about 26.2 ms.
Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be
varied in the course of operation, a smooth voltage rise is recommended.
tOFF
tR
2.0 V
0.2 V
0.2 V
0.2 V
VCC
39
MB89560A Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)
Value
Typ
Symbol
Pin
Unit
Remarks
Parameter
Min
1
Max
12.5
—
FCH
FCL
X0, X1
X0A, X1A
X0, X1
—
MHz Main clock
kHz Subclock
ns Main clock
µs Subclock
Clock frequency
—
80
—
32.768
—
tHCYL
tLCYL
1000
—
Clock cycle time
X0A, X1A
30.5
PWH
PWL
Input clock pulse width
X0
X0
20
—
—
—
—
ns External clock
ns External clock
tCR
tCF
Input clock rising/falling time
10
X0 and X1 Timing and Conditions
tHCYL
PWH
PWL
tCF
tCR
0.8 VCC
0.8 VCC
0.2 VCC
X0
0.2 VCC
0.2VCC
Main Clock Conditions
When using a crystal oscillator
or ceramic oscillator
When using an external clock
X0
X1
X0
X1
Open
FCH
FCH
C1
C2
40
MB89560A Series
X0A and X1A Timing
tLCYL
0.7 VCC
0.7 VCC
0.3 VCC
X0A
0.3 VCC
0.3 VCC
When using a crystal oscillator
X0A
X1A
FCL
C2
C1
Note : External clock is not available.
(4) Instruction Cycle
Parameter
(AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)
Symbol
Value
Unit
Remarks
tinst = 0.32 µs when operating
at FCH = 12.5 MHz (4/FCH)
4/FCH, 8/FCH, 16/FCH, 64/FCH
µs
Instruction cycle
(minimum execution time)
tinst
tinst = 61.036 µs when
operating at FCL = 32.768 kHz
2/FCL
µs
41
MB89560A Series
(5) Serial I/O Timing
(Vcc = 5.0V, AVSS = VSS= 0.0 V, TA = –40 °C to +85 °C)
Value
Symbol
Pin
Condition
Unit Remarks
Parameter
Min
Max
Serial clock cycle time
tSCYC
SCK, SCK1, UCK
2 tinst*
—
µs
SCK, SO, SCK1,
SO1, UCK, UO
SCK ↓ → SO time
tSLOV
–200 +200
ns
Internal shift
clock mode
SI, SCK, SI1,
SCK1, UI, UCK
Valid SI → SCK ↑
tIVSH
tSHIX
200
200
—
—
ns
ns
SCK, SI, SCK1,
SI1, UCK, UI
SCK ↑ → valid SI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
1 tinst*
—
—
µs
µs
SCK, SCK1, UCK
tSLSH
1 tinst*
SCK, SO, SCK1,
SO1, UCK, UO
SCK ↓ → SO time
tSLOV
tIVSH
tSHIX
0
200
—
ns
ns
ns
Externalshift
clock mode
SI, SCK, SI1,
SCK1, UI, UCK
Valid SI → SCK ↑
200
200
SCK, SI, SCK1,
SI1, UCK, UI
SCK ↑ → valid SI hold time
—
* : For information on tinst, see “(4) Instruction Cycle.”
42
MB89560A Series
Internal Shift Clock Mode
tSCYC
SCK
SCK1
UCK
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
0.8 VCC
SO
SO1
UO
0.2 VCC
tIVSH
tSHIX
SI
SI1
UI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
External Shift Clock Mode
tSLSH
tSHSL
SCK
SCK1
UCK
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
0.8VCC
0.2 VCC
tIVSH
SO
SO1
UO
tSHIX
SI
SI1
UI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
(6) Peripheral Input Timing
Parameter
(Vcc = 5.0V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)
Value
Symbol
Pin
Condition
Unit Remarks
Min
Max
Peripheral input “H” pulse width 1
Peripheral input “L” pulse width 1
tILIH1
tIHIL1
INT10 to INT17,
INT20 to INT23,
EC, PWC
2 tinst*
—
µs
µs
—
2 tinst*
—
* : For information on tinst, see “(4) Instruction Cycle.”
tIHIL1
tILIH1
INT10
INT17,
INT20 INT23,
EC,PWC
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
43
MB89560A Series
(7) I2C timing
(Vcc = 5.0 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)
Value
Symbol Pin Condition
Unit Remarks
Parameter
Min
Max
SCL
SDA
1/4 tinst*1 ×
1/4 tinst ×
Master
mode
Start condition output
Stop condition output
Start condition detect
Stop condition detect
tSTA
tSTO
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
M*2 x N*3 - 20
M*2 x N*3 + 20
SCL
SDA
1/4 tinst ×
1/4 tinst ×
Master
mode
(M*2 × N*3 + 8) - 20 (M*2 × N*3 + 8) + 20
SCL
SDA
tSTA
1/4 tinst × 6 + 40
—
SCL
SDA
tSTO
1/4 tinst × 6 + 40
1/4 tinst ×
(M*2 × N*3 + 8) - 20 (M*2 × N*3 + 8) + 20
—
Re-start condition
output
SCL
SDA
1/4 tinst ×
Master
mode
tSTASU
tSTASU
tLOW
Re-start condition
detect
SCL
SDA
1/4 tinst × 4 + 40
—
SCL output LOW
width
1/4 tinst ×
M*2 × N*3 - 20
1/4 tinst ×
M*2 × N*3 + 20
Master
mode
SCL
SCL output HIGH
width
1/4 tinst ×
1/4 tinst ×
Master
mode
tHIGH
tDO
SCL
SDA
SDA
—
—
—
ns
ns
(M*2 × N*3 + 8) - 20 (M*2 × N*3 + 8) + 20
SDA output delay
1/4 tinst × 4 - 20
1/4 tinst × 4 + 20
SDA output setup
time after interrupt
tDOSU
1/4 tinst × 4 - 20
—
ns *4
ns
SCL input LOW
pulse width
tLOW
SCL
SCL
—
—
1/4 tinst × 6 + 40
1/4 tinst × 2 + 40
—
—
SCL input HIGH
pulse width
tHIGH
ns
SDA input setup time
SDA hold time
tSU
SDA
SDA
—
—
40
0
—
—
ns
ns
tHO
*1 : For information in tinst, see " (4) Instruction Cycle".
*2 : M is defined in the ICCR CS4 and CS3 (bit 4 to bit 3) . For details, please refer to the H/W manual register
explanation.
*3 : N is defined in the ICCR CS2 to CS0 (bit 2 to bit 0) .
*4 : When the interrupt period is greater than SCL "L" width, SDA and SCL output (Standard) value is based on
hypothesis when rising time is 0 ns.
44
MB89560A Series
Data transmit (master/slave)
tDO
tHO
tDO
tSU
tDOSU
SDA
ACK
tHO
tSTASU
tLOW
tSTA
SCL
1
9
Data receive (master/slave)
tDO
tDO
tSU
tHO
tDOSU
SDA
ACK
9
tHIGH
tLOW
tSTO
SCL
6
7
8
45
MB89560A Series
6. A/D Converter Electrical Characteristics
(1) For MB89567A/AC A/D Converter
(AVcc= 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)
Value
Typ
—
Parameter
Resolution
Symbol Pin
Condition
Unit
Remarks
Min
—
Max
10
—
bit
Total error
—
—
±3.0
±2.5
LSB
LSB
—
1LSB = AVR/1024
Non-linearity error
—
—
Differential
linearity error
—
—
±1.9
LSB
mV
mV
Zero transition
voltage
AVss –
AVss +
AVss +
AVR=AVCC
VOT
1.5 LSB 0.5 LSB 2.5 LSB
AVR – AVR – AVR +
3.5 LSB 1.5 LSB 1.5 LSB
—
Full-scale
transition voltage
VFST
Interchannel
disparity
—
—
—
60 tinst*1
16 tinst*1
—
4
—
LSB 1LSB = AVR/1024
A/D mode
conversion time *3
—
µs
A/D Sampling
time
—
—
—
—
Analog port input
current
IAIN
—
10
µA
AN0
to
AN7
Analog input
voltage
VAIN
AVss
—
AVR
V
when A/D
mA conversion is
activated
IA
—
4
6
Power supply
current
AVCC
when A/D
µA conversion is
stopped
IAH
—
TA = +25 °C
—
1
5
Reference
voltage
—
AVss+3.5
—
AVCC
V
AVR
Reference
voltage supply
current
IR
A/D is Activated
A/D is Stopped
—
—
200
—
—
5
µA
IRH
µA *2
*1 : For information on tinst, see “(4) Instruction Cycle” in “5. AC Characteristics.”
*2 : When A/D conversion is not in operation, and the CPU is in STOP mode.
*3 : Included sampling time
46
MB89560A Series
(2) For MB89P568/PV560 A/D Converter
(AVcc=3.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C)
Value
Parameter
Resolution
Symbol
Pin
Condition
Unit Remarks
Min
—
Typ
—
Max
10
—
bit
Total error
—
—
±3.0
±2.5
LSB
1LSB =
AVR/1024
—
Non-linearity error
—
—
LSB
Differential linearity
error
—
—
±1.9
LSB
mV
mV
AVss – 1.5
LSB
AVss + AVss +
0.5 LSB 2.5 LSB
AVR=AVCC
Zero transition voltage
VOT
—
Full-scale transition
voltage
AVR – 3.5
LSB
AVR – AVR +
1.5 LSB 1.5 LSB
VFST
1LSB =
LSB
Interchannel disparity
—
—
4
AVR/1024
A/D mode conversion
time *3
—
—
—
60 tinst*1
16 tinst*1
—
—
—
µs
A/D Sampling time
—
Analog port input cur-
rent
IAIN
—
10
µA
AN0to
AN7
Analog input voltage
Power supply current
Reference voltage
VAIN
AVss
—
AVR
V
when A/D
mA conversion
is activated
IA
—
—
—
4
1
6
5
AVCC
when A/D
µA conversion
is stopped
IAH
TA = +25 °C
—
—
AVss + 3.5
—
—
AVCC
V
A/D is
AVR Activated
IR
400
—
µA
Reference voltage
supply current
A/D is
Stopped
IRH
—
—
5
µA *2
*1 : For information on tinst, see “(4) Instruction Cycle” in “5. AC Characteristics.”
*2 : When A/D conversion is not in operation, and the CPU is in STOP mode.
*3 : Included sampling time
47
MB89560A Series
(3) A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
• Linearity error
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics
• Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error (unit: LSB)
The difference between theoretical and actual conversion values caused by the zero transition error, full-scale
transition error, linearity error, quantization error, and noise
Theoretical I/O characteristics
Total error
3FF
3FE
3FD
3FF
3FE
3FD
VFST
Actual Conversion
Characteristic
1.5 LSB
{1 LSB × N + 0.5 LSB}
004
003
002
001
004
003
002
001
V
NT
V
OT
Actual Conversion
Characteristic
Theoretical Conversion
1 LSB
Characteristic
0.5 LSB
AVR
AVR
AVSS
AVSS
Analog Input
Analog Input
Total error for digital output N =V
V
FST − VOT
NT − {1 LSB × N + 0.5 LSB}
1 LSB =
(V)
1022
1 LSB
(Continued)
48
MB89560A Series
(Continued)
Zero transition error
Full-scale transition error
Theoretical
Characteristic
004
003
002
001
ActualConversion
Characteristic
3FF
3FE
3FD
3FC
ActualConversion
Characteristics
VFST
(actual measured
value)
ActualConversion
Characteristic
ActualConversion
Characteristic
VOT (actual measured value)
AVR
AVSS
Linearity error
Differential linearity error
ActualConversion
3FF
3FE
3FD
ActualConversion
Characteristic
N + 1
{1 LSB × N + VOT}
Characteristic
V(N + 1)T
VFST
N
VNT
(actual measured
value)
004
003
002
001
N − 1
N − 2
VNT
(actual measured
ActualConversion
Characteristic
value)
Theoretical Characteristic
ActualConversion
Characteristic
(actual measured value)
VOT
AVR
AVSS
AVR
AVSS
Analog Input
Analog Input
VNT − {1 LSB × N + 0.5 LSB}
Linearity error in digital output N =
1 LSB
V(N + 1)T − VNT
− 1
Differential linearity error in digital output N =
1 LSB
49
MB89560A Series
(4) Precautions
• The smaller the | AVR–AVSS | is, the greater the error would become relatively.
• The output impedance of the external circuit for the analog input must satisfy the following conditions :
Output impedance of the external circuit < Approx. 10 kΩ
• If the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient.
Analog Input equivalent circuit
Sample hold circuit *
.
C = 45 pF
.
Analog input pin
Comparator
If the analog input impedance
is higher than 10 kΩ, it is
recommended to connect an
external capacitor of approx.
0.1 µF.
.
R = 2.2 kΩ
.
Close for 8 instruction cycles
after starting A/D conversion.
Analog channel selector
* : The value of R and C at the sample hold circuit depends on the following.
MB89567A/MB89567AC : R=: 2.2 kΩ, C=: 45 pF
MB89P568/MB89PV560 : R=: 1.4 kΩ, C=: 64 pF
50
MB89560A Series
■ EXAMPLE CHARACTERISTICS
(1) “L” Level Output Voltage
V
CC - VOL1 vs. IOL
V
CC = 5.0 V
V
CC = 2.5 V
V
CC = 3.0 V
VCC = 4.0 V
V
CC = 3.5 V
V
CC = 5.5 V
V
CC = 4.5 V
V
V
CC = 6.0 V
CC = 6.5 V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
2
4
6
8
10
12
14
16
18
20
I
OL (mA)
(2) “H” Level Output Voltage
V
CC - VOH1 vs. IOH
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
CC = 3.5 V
V
V
V
V
V
V
CC = 4.0 V
CC = 4.5 V
CC = 5.0 V
CC = 5.5 V
CC = 6.0 V
CC = 6.5 V
0
-2
-4
-6
-8
-10
I
OH (mA)
51
MB89560A Series
(3) “H” Level Input Voltage / “L” Level Input Voltage
CMOS input
Hysteresis input
5.0
4.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
T = + 25 °C
A
TA = + 25 °C
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
V
IHS
ILS
1
2
3
4
5
6
7
V
CC (V)
1
2
3
4
5
6
7
V
CC (V)
VIHS : Threshold when input voltage in hysteresis
characteristics is set to “H” level.
VILS : Threshold when input voltage in hysteresis
characteristics is set to “L” level.
52
MB89560A Series
(4) Power Supply Current (External Clock)
I
CC1 vs. VCC
I
CC2 vs. VCC
(Mask ROM products)
(Mask ROM products)
1.2
1.0
15
12
9
T = + 25 °C
A
F
CH = 12.5 MHz
T = + 25 °C
A
F
CH = 12.5 MHz
F
CH = 10.0 MHz
0.8
0.6
0.4
0.2
0.0
F
CH = 10.0 MHz
CH = 4.2 MHz
6
F
F
CH = 4.2 MHz
CH = 3.0 MHz
F
F
F
CH = 3.0 MHz
3
F
CH = 1.0 MHz
7
CH = 1.0 MHz
7
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
V
CC (V)
V
CC (V)
ICCS2 vs. VCC
(Mask ROM products)
ICCS1 vs. VCC
(Mask ROM products)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
TA = + 25 °C
TA = + 25 °C
FCH = 12.5 MHz
FCH = 10.0 MHz
FCH = 12.5 MHz
FCH = 10.0 MHz
FCH = 4.2 MHz
FCH = 4.2 MHz
FCH = 3.0 MHz
FCH = 3.0 MHz
FCH = 1.0 MHz
0.5
0.0
FCH = 1.0 MHz
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
VCC (V)
VCC (V)
I
CCL vs. VCC
I
CCT vs. VCC
(Mask ROM products)
(Mask ROM products)
4.0
100
80
60
40
20
0
T
A
= + 25 °C
3.6
3.2
2.8
2.4
2.0
TA = + 25 °C
F
CL = 32.768 kHz
F
CL = 32.768 kHz
1.6
1.2
0.8
0.4
0.0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
VCC (V)
V
CC (V)
(Continued)
53
MB89560A Series
(Continued)
ICCLS vs. VCC
(Mask ROM products)
22
20
18
16
14
12
10
8
TA = + 25 °C
6
4
2
0
0
1
2
3
4
5
6
7
VCC (V)
IR vs. AVR
IA VS. AVCC
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
200
180
160
140
120
100
80
TA = + 25 °C
F
CH = 10.0 MHz
TA = + 25 °C
60
40
20
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
AVCC (V)
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
AVR (V)
(5) Pull-up Resistance
Rpull vs.VCC
210
190
170
150
130
110
90
70
TA = + 93 °C
TA = + 25 °C
TA = − 40 °C
50
30
10
2
3
4
5
6
7
8
VCC (V)
54
MB89560A Series
■ MASK OPTIONS
MB89567A
MB89567AC
Model
MB89P568
MB89PV560
No.
Specify when
ordering mask.
Setting
unavailable.
Setting
unavailable.
Specification method
Main clock oscillation stabilization delay
time initial value* selection (FCH = 10 MHz)
• 01: 214/FCH (Approx. 1.6 ms)
218/FCH (Approx.
26.2 ms)
2 /FCH (approx.
26.2 ms)
18
1
2
Selectable
Selectable
• 10: 217/FCH (Approx. 13.1 ms)
• 11: 218/FCH (Approx. 26.2 ms)
-101
Internal voltage
divider
-102
On-chip voltage
booster
-101
Internal voltage
divider
-102
On-chip voltage
booster
LCD driving power supply
• On-chip voltage booster
• Internal voltage divider (external divider
resistors can be used)
■ ORDERING INFORMATION
Part number
Package
Remarks
MB89567APFV
MB89567ACPFV
MB89P568PFV-101
Without Booster
Resistor divider
80-pin Plastic LQFP
(FPT-80P-M05)
MB89567APFV
MB89567ACPFV
MB89P568PFV-102
With Booster
MB89567APF
MB89567ACPF
MB89P568PF-101
Without Booster
Resistor divider
80-pin Plastic QFP
(FPT-80P-M06)
MB89567APF
MB89567ACPF
MB89P568PF-102
With Booster
MB89567APFM
MB89567ACPFM
MB89P568PFM-101
Without Booster
Resistor divider
80-pin Plastic LQFP
(FPT-80P-M11)
MB89567APFM
MB89567ACPFM
MB89P568PFM-102
With Booster
Without Booster
Resistor divider
MB89PV560CF-101
MB89PV560CF-102
80-pin Ceramic MQFP
(MQP-80C-P01)
With Booster
55
MB89560A Series
■ PACKAGE DIMENSIONS
80-pin plastic LQFP
(FPT-80P-M05)
*Pins width and pins thickness include plating thickness.
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
0.145±0.055
(.006±.002)
60
41
61
40
0.08(.003)
Details of "A" part
1.50 –+00..1200
(Mounting height)
.059 –+..000048
0.10±0.10
(.004±.004)
(Stand off)
INDEX
0°~8°
80
21
"A"
0.25(.010)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
1
20
LEAD No.
0.50(.020)
0.20±0.05
(.008±.002)
M
0.08(.003)
C
2000 FUJITSU LIMITED F80008S-c-3-7
Dimensions in mm (inches)
(Continued)
56
MB89560A Series
80-pin plastic QFP
(FPT-80P-M06)
*Pins width and pins thickness include plating thickness.
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
64
41
65
40
0.10(.004)
17.90±0.40
(.705±.016)
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
80
25
0.25(.010)
3.05 –+00..2300
.120 –+..000182
(Mounting height)
1
24
0~8°
0.80(.031)
0.37±0.05
(.015±.002)
0.17±0.06
(.007±.002)
M
0.20(.008)
0.30 +–00..2150
0.80±0.20
(.031±.008)
"A"
.012 +–..001004
0.88±0.15
(Stand off)
(.035±.006)
C
2001 FUJITSU LIMITED F80010S-c-4-4
Dimensions in mm (inches)
(Continued)
57
MB89560A Series
80-pin plastic LQFP
(FPT-80P-M11)
*Pins width and pins thickness include plating thickness.
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
0.145±0.055
(.006±.002)
60
41
61
40
0.10(.004)
Details of "A" part
1.50 +–00..1200 .059 –+..000048
(Mounting height)
0.25(.010)
INDEX
0~8°
80
21
0.10±0.10
(.004±.004)
(Stand off)
0.50±0.20
(.020±.008)
"A"
0.60±0.15
1
20
(.024±.006)
0.65(.026)
0.32±0.05
(.013±.002)
M
0.13(.005)
C
2001 FUJITSU LIMITED F80016S-c-2-5
Dimensions in mm (inches)
(Continued)
58
MB89560A Series
(Continued)
80-pin ceramic
(MQP-80C-P01)
18.70(.736)TYP
12.00(.472)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
1.50(.059)TYP
1.00(.040)TYP
0.80±0.25
(.0315±.010)
INDEX AREA
1.20 –+00..2400
4.50(.177)
TYP
.047 –+..000186
0.80±0.25
(.0315±.010)
1.27±0.13
(.050±.005)
INDEX AREA
18.12±0.20
(.713±.008)
22.30±0.33
(.878±.013)
12.02(.473)
TYP
18.40(.724)
REF
10.16(.400)
TYP
14.22(.560)
TYP
0.30(.012)
TYP
24.70(.972)
TYP
INDEX
6.00(.236)
TYP
0.40±0.10
(.016±.004)
1.27±0.13
(.050±.005)
0.30(.012)TYP
0.40±0.10
(.016±.004)
1.20 –+00..2400
.047 –+..000186
1.50(.059)
TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
1.00(.040)
TYP
0.15±0.05 8.70(.343)
(.006±.002) MAX
C
1994 FUJITSU LIMITED M80001SC-4-2
Dimensions in mm (inches)
59
MB89560A Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0208
FUJITSU LIMITED Printed in Japan
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