MB89817A_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12507-2E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89810A Series

MB89816A/P817A

■ DESCRIPTION

The MB89810A series is a line of single-chip microcontrollers based on the F²MC*-8L CPU core which can

operate at low voltage but at high speed. The microcontrollers contain peripheral function such as timer, serial

interface, a UART, and an external interrupt. The MB89810A series is applicable to a wide range of applications

from welfare products to industrial equipment, including portable devices.

*: F²MC stands for FUJITSU Flexible Microcontroller.

■ FEATURES

High speed processing at low voltage

Minimum execution time: 0.8 µs/3.0 V, 1.33 µs/2.2 V

• F²MC-8L family CPU core

Multiplication and division instructions

16-bit arithmetic operations

Test and branch instructions

Instruction set optimized for controllers

Bit manipulation instructions, etc.

• Four types of timers

8-bit PWM timer: 2 channels (also serve as reload timers)

16-bit timer/counter

21-bit time-base timer

• Two serial interface

8-bit synchronous serial (Switchable transfer direction allows communication with various equipment.)

UART (5-, 7-, or 8-bit transfer capable)

(Continued)

■ PACKAGE

64-pin Plastic QFP

(FPT-64P-M06)

MB89810A Series

(Continued)

• External interrupt: 8 channels

Eight channels are independent and capable of wake-up from low-power consumption modes (with an edge

detection function).

• Low-power consumption modes

Stop mode (Oscillation stops to minimize the current consumption)

Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal)

■ PRODUCT LINEUP

Part number

MB89816A

MB89P817A

Parameter

Classification

Mass-production product

(mask ROM products)

One-time PROM product

(for evaluation and development)

ROM size

24 K × 8 bits

(internal mask ROM)

32 K × 8 bits

(internal PROM, programming with gen-

eral-purpose EPROM programmer)

RAM size

2048 × 8 bits

CPU functions

Number of instructions:

Instruction bit length:

Instruction length:

Data bit length:

Minimum execution time:

136

8 bits

1 to 3 bytes

1, 8, 16 bits

0.8 µs/5 MHz

Interrupt processing time: 7.2 µs/5 MHz

Ports

Input ports:

Output ports:

8 (All also serve as peripherals.)

8

I/O ports (N-ch open-drain): 5 (for LED driving)

I/O ports (CMOS):

Total:

32 (14 ports also serve as peripherals.)

53

8-bit PWM timer

Two internal channels

8-bit reload timer operation (toggled output capable, operating clock cycle:

3 different cycles)

8-bit resolution PWM operation (conversion cycle: 3 different cycles)

8-bit timer/counter

UART

16-bit timer operation

16-bit event counter operation

5-, 7-, or 8-bit transfer capable

Built-in baud rate generator

Clock synchronous/asynchronous data transfer capable

8-bit Serial I/O

8-bits

LSB-first/MSB first selectability

One clock selectable from four transfer clocks

(one external shift clock, three internal shift clocks)

External interrupt

8 independent channels (edge selection, interrupt vector, source flag)

4 channels: Level detection (level selectable)

4 channels: Edge detection (edge selectable)

Used also for wake-up from the stop/sleep mode. (Edge detection is also permitted in stop mode.)

(Continued)

2

MB89810A Series

(Continued)

Part number

MB89816A

MB89P817A

Parameter

Watch interrupt

Watchdog timer reset

Standby mode

Process

Interrupt cycles: 4 different cycles (subclock)

Reset occurrence cycle: 839 ms/5 MHz

Sleep mode, stop mode

CMOS

Package

FPT-64P-M06

Operating voltage

2.2 V to 6.0 V*

2.7 V to 6.0 V*

* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

■ PIN ASSIGNMENT

(Top view)

P30/PWE

P31/SCK

P32/SO

P33/SI

P34/PWO

P35/PWI

P36/PTO1

P37/PTO2

P60/INT0

P61/INT1

P62/INT2

V^CC

P63/INT3

P64/INT4

P65/INT5

P66/INT6

P67/INT7

X0A

1

2

3

4

5

6

7

8

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P50

V^SS

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

P20

9

10

11

12

13

14

15

16

17

18

19

X1A

(FPT-64P-M06)

3

MB89810A Series

■ PIN DESCRIPTION

Pinno.

23

Pin name

X0

Circuit type

Function

A

Main clock oscillator pins

24

X1

18

X0A

I

Subclock crystal oscillator pins

19

X1A

21

MOD0

MOD1

RST

B

C

Operating mode selection pins

Connect directly these pins directly to V^SS.

22

20

Reset I/O pin

This pin is an N-ch open-drain output type with a pull-up resistor

and a hysteresis input type.

“L” is output from this pin by an internal reset source. The internal

circuit is initialized by the input of “L”.

49 to 42

41 to 34

33 to 30

P00 to P07

P10 to P17

P20 to P23

D

F

General-purpose I/O ports

A pull-up resistor option is provided.

These ports have the port output inverting function.

General-purpose I/O ports

A pull-up resistor option is provided.

These ports have the port output inverting function.

General-purpose output ports

These ports have the port output inverting function.

29 to 26

1

P24 to P27

P30 /PWE

F

E

General-purpose output ports

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as a pulse width detection enable input (PWE).

PWE input is hysteresis input.

2

P31/SCK

E

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as the clock I/O for the 8-bit serial I/O (SCK).

SCK input is hysteresis input.

3

4

P32/SO

P33/SI

D

E

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as the data output for the 8-bit serial I/O (SO).

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as the data input for the 8-bit serial I/O (SI).

SI input is hysteresis input.

5

6

P34/PWO

P35/PWI

D

E

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as a pulse width detection output (PWO).

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as a pulse width detection input (PWI).

PWI input is hysteresis input.

7

P36/PTO1

D

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as the toggle output for the 8-bit PWM timer 1 (PTO1).

(Continued)

4

MB89810A Series

(Continued)

Pinno.

8

Pin name

Circuit type

Function

P37/PTO2

D

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as the toggle output for the 8-bit PWM timer 2 (PTO2).

56

58

P40

D

E

General-purpose I/O port

A pull-up resistor option is provided.

P41/EC

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as a 16-bit timer/counter input (EC).

EC input is hysteresis input.

59

60

P42/TXD1

P43/RXD1

D

E

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as the data output 1 for the UART (TXD1).

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as the data input 1 for the UART (RXD1).

RXD1 input is hysteresis input.

61

P44/SCL1

E

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as the clock I/O 1 for the UART (SCL1).

SCL1 input is hysteresis input.

62

63

P45/TXD2

P46/RXD2

D

E

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as the data output 2 for the UART (TXD2).

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as the data input 2 for the UART (RXD2).

RXD2 input is hysteresis input.

64

P47/SCL2

E

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as the clock I/O 2 for the UART (SCL2).

SCL2 input is hysteresis input.

51 to 55

9 to 11

P50 to P54

G

H

N-channel open-drain I/O ports

A pull-up resistor option is provided only for the MB89816A.

P60/INT0 to

P62/INT2

General-purpose I/O ports

A pull-up resistor option is provided.

Also serve as an external interrupt input (INT0 to INT2).

These ports are a hysteresis input type.

13 to 17

P63/INT3 to

P67/INT7

H

General-purpose I/O ports

A pull-up resistor option is provided.

Also serve as an external interrupt input (INT3 to INT7).

These ports are a hysteresis input type.

12, 57

25, 50

V^CC

V^SS

–

Power supply pin

Power supply (GND) pin

5

MB89810A Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• Main clock

X1

X0

• At an oscillation feedback resistor of approximately

2 MΩ (1 to 5 MHz)

• CR oscillator circuit selectability

Standby control signal

B

C

• At an output pull-up resistor (P-ch) of approximately

50 kΩ/5.0 V

R

• Hysteresis input

P-ch

N-ch

D

• CMOS output

• CMOS input

R

P-ch

N-ch

• Pull-up resistor optional

E

• CMOS output

• CMOS input

R

• Hysteresis input (resource input)

P-ch

N-ch

• Pull-up resistor optional

(Continued)

6

MB89810A Series

(Continued)

Type

Circuit

Remarks

F

• CMOS output

P-ch

N-ch

G

• N-ch open-drain output

• CMOS input

R

P-ch

N-ch

• Pull-up resistor optional (only for the MB89816A)

H

• Hysteresis input

• Pull-up resistor optional

I

• Subclock (30 to 40 kHz)

• At an oscillation feedback resistor of approximately

4.5 MΩ

X1A

X0A

7

MB89810A Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resistor.

3. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore

important. As stabilization guidelines, it is recommended to control power so that V^CCripple fluctuations (P-P

value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient

fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.

4. Precautions when Using an External Clock

Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and

wake-up from stop mode.

8

MB89810A Series

■ PROGRAMMING TO THE EPROM ON THE MB89P817A

In EPROM mode, the MB89P817A functions equivalent to the MBM27C256A. This allows the PROM to be

programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by

using the dedicated socket adapter.

• Writing Procedure

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 0007^Hto 7FFFH (note that addresses 8007H to FFFFH

while operating as operating mode assign to 0007H to 7FFFH in EPROM mode).

Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each

corresponding option, see “• Setting OTPROM Option Bit Map.”)

(3) Program with the EPROM programmer.

• Memory Space

Memory space is diagrammed below.

0000H

Option area

0007H

Program area

(PROM)

7FFFH

9

MB89810A Series

• Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

OTPROM (one-time PROM) microcomputer program.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

• Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

• EPROM Programmer Socket Adapter

Package

Compatible socket adapter

FPT-64P-M06

ROM-64QF-28DP-8L

Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760

Note: Connect the jumper pin to V^SSwhen using.

Depending on the EPROM programmer, inserting a capacitor of approx. 0.1 µF between V^PPand VSS or

V^CCand VSS can stabilize programming operations.

10

MB89810A Series

• OTPROM Option Bit Map

Bit 7 Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Vacancy

Single-clock Reset pin

setting output

Power-on

reset

Oscillation stabilization time

00 2⁴/FCH 01 2¹⁴/FCH

10 2¹⁷/FCH 11 2¹⁸/FCH

0000^H

0001^H

0002^H

0003^H

0004^H

0005^H

0006^H

Readable and Readable and Readable and 1: Dual-clock

1: Enabled 1: Enabled

0: Disabled 0: Disabled

writable

0: Single-clock

P07

P06

P05

P04

P03

P02

P01

P00

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P17

P16

P15

P14

P13

P12

P11

P10

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P37

P36

P35

P34

P33

P32

P31

P30

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P47

P46

P45

P44

P43

P42

P41

P40

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Vacancy

P64

P63

P62

P61

P60

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Readable and Readable and Readable and

writable

Vacancy

Oscillator type

P67

P66

P65

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Readable and Readable and Readable and Readable and 1: Crystal

writable writable writable writables 0: CR

Note: Each bit defaults to 1.

11

MB89810A Series

■ BLOCK DIAGRAM

Time-base

timer

X0

Main clock

X1

oscillator

8-bit PWM

timer 2

P37/PTO2

P36/PTO1

Clock controlletr

X0A

X1A

Subclock

oscillator

8-bit PWM

timer 1

Reset circuit

(WDT)

RST

P31/SCK

P33/SI

8-bit serial

I/O 1

P32/SO

8

P00 to P07

P10 to P17

Port 0 and port 1

CMOS I/O port

P30/PWE

P35/PWI

P34/PWO

Pulse width

detection

CMOS I/O port

8

Port 2

P20 to P27

CMOS output port

P44/SCL1

P47/SCL2

P43/RXD1

P46/RXD2

P42/TXD1

P45/TXD2

UART

RAM

(2048 × 8 bits)

16-bit

timer/counter

P41/EC

P40

F²MC-8L

CPU

CMOS I/O port

Port 5

N-ch open-drain

I/O port

5

8

P50 to P54

ROM

(24 K × 8 bits)

8

P60/INT0

External

interrupt

to P67/INT7

Other pins

V^CC× 2, VSS × 2

MOD0, MOD1

Input port

12

MB89810A Series

■ CPU CORE

1. Memory Space

The microcontrollers of the MB89810A series offer a memory space of 64 Kbytes for storing all of I/O, data, and

program areas. The I/O area is located at the lowest address. The data area is provided immediately above the

I/O area. The data area can be divided into register, stack, and direct areas according to the application. The

program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of

interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89810A series is structured as illustrated below.

Memory Space

MB89816A

I/O

MB89P817A

I/O

0000H

0080H

0000H

0080H

0100H

Register

0200H

RAM

2 KB

RAM

2 KB

0880H

Not available

8000^H

8007H

Optional PROM

A000^H

PROM

32 KB

ROM

24 KB

FFFFH

13

MB89810A Series

2. Registers

The F²MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The following dedicated registers are provided:

Program counter (PC):

Accumulator (A):

A 16-bit register for indicating instruction storage positions

A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator

Whenthe instructionisan8-bitdataprocessinginstruction, thelowerbyteisused.

Index register (IX):

Extra pointer (EP):

Stack pointer (SP):

Program status (PS):

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit register for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

16 bits

PC

Initial value

FFFD^H

: Program counter

: Accumulator

A

T

Undefined

: Temporary accumulator

: Index register

IX

EP

SP

PS

: Extra pointer

: Stack pointer

: Program status

I-flag = 0, IL1, 0 = 11

Other bits are undefined.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

PS

RP

Vacancy Vacancy Vacancy

H

IL1, 0

N

V

C

RP

CCR

14

MB89810A Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

Rule for Conversion of Actual Addresses of the General-purpose Register Area

Lower OP codes

RP

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0

when reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low = no interrupt

N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.

Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.

V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does

not occur.

C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.

Set to the shift-out value in the case of a shift instruction.

15

MB89810A Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 32 banks can be used on the MB89816A. The bank currently in use is indicated

by the register bank pointer (RP).

Register Bank Configuration

This address = 0100H + 8 × (RP)

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

32 banks

Memory area

16

MB89810A Series

■ I/O MAP

Address

00^H

01^H

02^H

03H

04^H

05^H

06H

07^H

08H

09^H

0AH

0BH

0C^H

0DH

0EH

0F^H

10H

11^H

12H

13H

14^H

15H

16H

17^H

18^H

19H

1AH

1B^H

1CH

1DH

1E^H

1FH

Read/write

(R/W)

(W)

Register name

PDR0

Register description

Port 0 data register

DDR0

Port 0 data direction register

Port 1 data register

Port 1 data direction register

Port 2 data register

Vacancy

(R/W)

(W)

PDR1

DDR1

(R/W)

PDR2

Vacancy

(R/W)

(W)

SYCC

STBC

WDTC

TBCR

WPCR

PDR3

DDR3

PDR4

DDR4

PDR5

PDR6

System clock control register

Standby control register

Watchdog timer control register

Time-base timer control register

Watch prescaler control register

Port 3 data register

Port 3 data direction register

Port 4 data register

Port 4 data direction register

Port 5 data register

Port 6 data register

Vacancy

(R/W)

(W)

(R/W)

(R)

Vacancy

(R/W)

PIVE

TMCR

TCHR

TCLR

Port inverting operation enable register

16-bit timer count register

16-bit timer count register (H)

16-bit timer count register (L)

Vacancy

(R/W)

SMR

SDR

Serial I/O mode register

Serial I/O data register

Vacancy

(Continued)

17

MB89810A Series

(Continued)

Address

20H

Read/write

(R/W)

Register name

SMC1

Register description

UART serial I/O mode control register 1

UART serial I/O rate control register

UART serial I/O status/data control register

UART serial I/O data control register

UART serial I/O mode control register 2

Vacancy

21H

(R/W)

SRC

22^H

(R/W)

SSD

23^H

(R/W)

SIDR/SODR

SMC2

24H

(R/W)

25^H

26^H

Vacancy

27H

Vacancy

28^H

(R/W)

(W)

CNTR1

CNTR2

CNTR3

COMR2

COMR1

PWM timer control register 1

PWM timer control register 2

PWM timer control register 3

PWM timer compare register 2

PWM timer compare register 1

Vacancy

29H

2A^H

2BH

2CH

2D^H

2EH

2FH

(W)

Vacancy

(R/W)

PWCR

EIC1

EIC2

EI2E

EI2F

Pulse width detection control register

External interrupt 1 control register 1

External interrupt 1 control register 2

External interrupt 2 enable register

External interrupt 2 flag register

Vacancy

30^H

31H

32^H

33H

34H

35^Hto 7AH

7BH

7CH

7D^H

7E^H

7FH

Vacancy

(W)

ILR1

ILR2

ILR3

ITR

Interrupt level register 1

Interrupt level register 2

Interrupt level register 3

Interrupt test register

(W)

Not available

Note: Do not use vacancies.

18

MB89810A Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Power supply voltage

Input voltage

Min.

Max.

V^CC

V^I1

VSS – 0.3

VSS + 7.0

VCC + 0.3

VSS + 7.0

VCC + 0.3

VSS + 7.0

V

Except P50 to P54

P50 to P54

V^I2

V^O1

V^O2

Except P50 to P54

P50 to P54

Output voltage

“L” level maximum output

current

I^OL

—

20

mA Peak value

Average value except pins other

than P50 to P54

I^OLAV1

I^OLAV2

∑I^OL

—

4

mA

“L” level average output current

10

mA Average value for P50 to P54

mA Peak value

“L” level total maximum output

current

100

“L” level total average output

current

∑I^OLAV

—

40

mA Average value

“H” level maximum output

current

I^OH

—

–20

–4

mA Peak value

mA Average value

mA Peak value

“H” level average output current

I^OHAV

∑I^OH

“H” level total maximum output

current

–50

“H” level total average output

current

∑I^OHAV

—

–20

mA Average value

Power consumption

Operating temperature

Storage temperature

P^D

—

300

+85

mW

°C

TA

–40

–55

Tstg

+150

°C

Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Func-

tional operation should be restricted to the conditions as detailed in the operational sections of this

data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device

reliability.

19

MB89810A Series

2. Recommended Operating Conditions

(VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

Normal operation assurance range

MB89816A

2.2*

6.0

V

Power supply voltage

V^CC

Normal operation assurance range

MB89P817A

2.7*

1.5

6.0

V

Retains the RAM state in stop mode

P00 to P07, P10 to P17, P30 to P37,

P40 to P47, P50 to P54

V^IH

0.7 VCC

VCC + 0.3

V

(with pull-up resistor)

“H” level voltage

“L” level voltage

RST, MOD0, MOD1, P60 to P67,

Pheripheral input for port 3 and port 4

V^IHS

V^IHS2

V^IL

0.8 VCC

VCC + 0.3

VSS + 6.0

0.3 VCC

V

P50 to P54 (without pull-up resistor)

P00 to P07, P10 to P17, P30 to P37,

P40 to P47, P50 to P54

VSS – 0.3

RST, MOD0, MOD1, P60 to P67,

Pheripheral input for port 3 and port4

V^ILS

VSS – 0.3

0.2 VCC

V

Open-drain output pin

application voltage

V^D

T^A

VSS – 0.3

–40

VSS + 6.0

+85

V

P50 to P54 (without pull-up resistor)

Operating temperature

°C

* : These values vary with the operating frequency. See Figure 1.

6

5

Operating assurance range

4

3

2

1

2.0

5.0

1.0

3.0

4.0

Main clock operating frequency (MHz) (at an instruction cycle of 4/FCH)

Note: The shaded area is assured only for the MB89816A

Figure 1 Operating Voltage vs. Main Clock Operating Frequency (for MB89816A)

20

MB89810A Series

3. DC Characteristics

(VCC = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Parameter

Condition

Unit

Remarks

Min.

Typ.

Max.

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47

“H” level output

voltage

V^OH

IOH = –2.0 mA

2.4

—

V

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47, P50 to P54

P60 to P67

V^OL1

IOL = 1.8 mA

—

0.4

V

“L” level output

voltage

IOL = 6 mA

V^CC= 3 V

P50 to P54

RST

V^OL2

V^OL3

—

0.5

0.4

V

IOL = 4.0 mA

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

Input leakage current

(Hi-z output leakage

current)

Without pull-up

resistor

P40 to P47, P50 to P54, 0.45 V < V^I< V^CC

P60 to P67,

ILI1

—

±5

µA

kΩ

MOD0, MOD1

P00 to P07, P10 to P17,

P30 to P37, P40 to P47,

VI = 0.0 V

With pull-up

resistor

Pull-up resistance

RPULL

25

—

50

4

100

6

P50 to P54, P60 to P67,

RST

FCH = 5 MHz

V^CC= 5.0 V

tinst = 0.8 µs

mA MB89816A

ICC1

I^CC2

I^CCS1

4.8

0.4

1.0

7.5

0.6

1.5

mA MB89P817A

mA MB89816A

mA MB89P817A

—

FCH = 5 MHz

VCC = 3.0 V

tinst = 6.4 µs

FCH = 5 MHz

VCC = 5.0 V

t^inst= 0.8 µs

Power supply

current^*

VCC

—

1.2

0.3

1.8

0.5

mA

Sleep mode

mA

FCH = 5 MHz

VCC = 3.0 V

tinst = 12.8 µs

I^CCS2

Subclock mode

—

50

100

700

µA

F^CL= 32.768 kHz

V^CC= 3.0 V

I^CCL

500

MB89P817A

(Continued)

21

MB89810A Series

(Continued)

(VCC = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Parameter

Condition

Unit

Remarks

Min.

Typ.

Max.

Subclock sleep

mode

F^CL= 32.768 kHz

V^CC= 3.0 V

ICCLS

—

15

50

µA

Watch mode

Main clock stop

mode at dual-

clock system

F^CL= 32.768 kHz

V^CC= 3.0 V

ICCT

—

15

µA

Power supply

current^*

VCC

Subclock stop

mode Main clock

stop mode at

single-clock

system

F^CL= 32.768 kHz

V^CC= 3.0 V

ICCH

—

10

—

µA

Other than VCC and

V^SS

Input capacitance CIN

f= 1 MHz

10

pF

* : The measurement conditions of power supply current are as follows: the external clock and TA = +25°C.

22

MB89810A Series

4. AC Characteristics

(1) Reset Timing

(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit

Remarks

Parameter

Min.

Max.

RST “L” pulse width

tZLZH

—

16 tCH

—

ns

Note: tCH is the cycle time of the main clock.

tZLZH

RST

0.2 VCC

(2) Power-on Reset

Parameter

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol Condition

Unit

Remarks

Min.

—

Max.

Power supply rising time

Power supply cut-off time

t^R

50

—

ms

Power-on reset function only

Due to repeated operations

—

t^OFF

1

Note: Make sure that power supply rises within the selected oscillation stabilization time.

If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is

recommended.

tOFF

t^R

2.0 V

0.2 V

V

CC

Note that a sudden increase in supply voltage may result in a power-on reset.

When increasing the supply voltage during operation, voltage variation should be within twice the intended increment so that the

voltage rises as smoothly as possible.

23

MB89810A Series

(3) Clock Timing

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Typ.

—

Symbol

Condition

Unit

Remarks

Parameter

Clock frequency

Clock cycle time

Min.

1

Max.

5

F^CH

F^CL

t^CH

X0, X1

MHz

kHz

ns

X0A, X1A

X0, X1

—

32.768

—

200

—

1000

—

t^CL

X0A, X1A

30.5

µs

—

PWH

PWL

External clock

X0

20

—

15.2

—

10

ns

µs

ns

Input clock pulse width

P^WHL

PWLL

X0A

X0

Input clock rising/falling

time

tCR

tCF

X0 and X1 Timing and Conditions

t^CH

PWH

PWL

t^CR

tCF

0.8 VCC

X0

0.2 VCC

Main Clock Conditions

When a crystal

or

ceramic resonator is used

when an external clock is used

X0

X1

X0

X1

Open

When a CR oscillator is used

X0

X1

24

MB89810A Series

X0A and X1A Timings and Conditions

t^CL

PWHL

PWLL

t^CR

tCF

0.8 VCC

X0A

0.2 VCC

Subclock Conditions

When a crystal

or

ceramic resonator is used

when an external clock is used

X0A

X1A

X0A

X1A

Open

(4) Serial I/O Timings

Parameter

(VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)

Value

Symbol

SCK

Condition

Unit Remarks

Min.

2 tinst

Max.

—

Serial clock cycle time

SCK ↓ → SO time

t^SCYC1

tSLOV1

tIVSH1

tSHIX1

tSHSL

ns

SCK, SO

SI, SCK

SCK, SI

–200

1/2 tinst

1 t^inst

200

—

Internal shift

clock mode

Valid SI → SCK ↑

SCK ↑ → valid SI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK ↓ → SO time

—

SCK

tSLSH

1 tinst

—

External shift

clock mode

tSLOV2

tIVSH2

tSHIX2

SCK, SO

SI, SCK

SCK, SI

0

200

—

Valid SI → SCK ↑

1/2 tinst

SCK ↑ → valid SI hold time

—

* : tinst represents the minimum instruction execution time. It varies with the selected system clock and operating

mode.

25

MB89810A Series

(5) UART Timings

(VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit Remarks

Parameter

Min.

2 t^inst

Max.

—

SCL1, SCL2

SCLx, TXDx

RXDx, SCLx

SCL1, RXD2

Serial clock cycle time

SCL ↓ → TXDx time

Valid RXDx → SCLx ↑

t^SCYC

t^SLOV1

tIVSH1

ns

–200

1/2 tinst

1 t^inst

200

—

Internal shift

clock mode

SCLx ↑ → valid RXDx hold time t^SHIX1

—

Serial clock “H” pulse width

Serial clock “L” pulse width

SCLx ↓ → TXDx time

t^SHSL

tSLSH

t^SLOV2

tIVSH2

—

SCL1, SCL2

1 tinst

—

External shift

clock mode

SCLx, TXDx

RXDx, SCLx

SCL1, RXD2

0

200

—

Valid RXDx → SCLx ↑

1/2 tinst

SCLx ↑ → valid RXDx hold time t^SHIX2

—

Notes: • tinst represents the minimum instruction execution time. It varies with the selected system clock and

operating mode.

• The edge polarity for the SLCx input is assumed when LSEL bit = 0 for SMC2. The polarity is inverted

when LSEL = 1.

Internal Shift Clock Mode

tSCYC

2.4 V

SCK/SCLx

0.8 V

tSLOV1

2.4 V

SO/TXDx

0.8 V

tIVSH1

tSHIX1

0.8 VCC

0.2 VCC

0.8 VCC

SI/RXDx

0.2 VCC

External Shift Clock Mode

tSLSH

tSHSL

0.8 VCC

SCK/SCLx

SO/TXDx

0.2 VCC

tSLOV2

2.4 V

0.8 V

tIVSH2

tSHIX2

0.8 VCC

0.2 VCC

0.8 VCC

SI/RXDx

0.2 VCC

26

MB89810A Series

(6) Peripheral Input Timings

(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit Remarks

Parameter

Min.

Max.

Peripheral input “H” pulse

width

EC,

INT0 to INT7

t^ILIH

t^IHIL

—

2 t^inst

—

ns

Peripheral input “L” pulse

width

EC,

INT0 to INT7

2 t^inst

—

“H” input pulse width of

pulse width detection

enable signal

512 t^CL+ 200

or 480 t^CL+ 200

t^PWEH

—

ns

PWE

“L” input pulse width of

pulse width detection

enable signal

512 t^CL+ 200

or 480 t^CL+ 200

t^PWEL

—

Notes: • tinst represents the minimum instruction execution time. It varies with the selected system clock and

operating mode.

• tCL represents the subclock cycle time.

• The PWE pulse width value varies with the first divider selection bit of the watch prescaler. The pulse width

is “512 tCL + 200” when divide by 16 is selected; or "480 tCL + 200" when divide by 15 is selected.

tIHIL

tILIH

EC,

INT0 to INT7

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

tPWEH

tPWEL

0.8 VCC

0.2 VCC

0.8 VCC

PWE

0.2 VCC

27

MB89810A Series

■ INSTRUCTIONS

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

#vct

#d8

#d16

dir: b

rel

@

Register indirect (Example: @A, @IX, @EP)

A

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

AH

AL

Lower 8 bits of accumulator A (8 bits)

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the

instruction in use.)

T

TH

TL

IX

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

(Continued)

28

MB89810A Series

(Continued)

Symbol

Meaning

EP

PC

SP

PS

dr

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

CCR

RP

Ri

Register bank pointer RP (5 bits)

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × )

(( × ))

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

Columns indicate the following:

Mnemonic:

~:

Assembler notation of an instruction

Number of instructions

Number of bytes

#:

Operation:

TL, TH, AH:

Operation of an instruction

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH immediately before the instruction

is executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

29

MB89810A Series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

47

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

48 to 4F

04

05

06

60

92

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

07

(A) ← (Ri)

(dir) ← d8

08 to 0F

85

86

87

88 to 8F

D5

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

–

AL

–

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

–

F0

Notes: • During byte transfer to A, T ← A is restricted to low bytes.

•Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

30

MB89810A Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3

C2

C0

D8 to DF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

(TL) − (AL)

(T) − (A)

–

13

03

→

A

C

←

C ← A

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

(A) − (Ri)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

31

MB89810A Series

(Continued)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

32

MB89810A Series

■ INSTRUCTION MAP

33

MB89810A Series

■ MASK OPTIONS

Part number

No.

MB89816A

MB89P817A

Specify when ordering masking

Specifying procedure

Set with EPROM programmer

Pull-up resistors

Can be set per pin.

(P50 to P54 are available only

for without a pull-up resistor.)

P00 to P07, P10 to P17,

P30 to P37, P40 to P47,

P50 to P54, P60 to P67

1

Specify by pin

Selectable

Power-on reset selection

With power-on reset

Without power-on reset

2

3

Setting possible

Main clock oscillation (5 MHz)

stabilization time selection

approx. 218/F^CH(approx. 52.4 ms)

Selectable

approx. 217/F^CH(approx. 26.2 ms)

approx. 214/F^CH(approx. 3.2 ms)

approx. 24/F^CH(approx. 0 ms)

Reset pin ouotput selection

With reset output

4

5

Selectable

Setting possible

Without reset output

Selection either single- or dual-

clock system

Single clock

Dual clock

Main clock oscillator type

selection

6

Selectable

Setting possible

Crystal or ceramic oscillator

CR

FCH: Main clock frequency

* : The main clock oscillation setting time is generated by dividing the main clock frequency. Note that the oscillation

cycle is not stable immediately after oscillation is started. The settling time value in this data sheet should be

used as a reference.

■ ORDERING INFORMATION

Part number

MB89816APF

Package

Remarks

64-pin Plastic QFP

(FPT-64P-M06)

MB89P817APF

34

MB89810A Series

■ PACKAGE DIMENSIONS

64-pin Plastic QFP

(FPT-64P-M06)

24.70±0.40(.972±.016)

20.00±0.20(.787±.008)

3.35(.132)MAX

51

33

0.05(.002)MIN

(STAND OFF)

52

32

14.00±0.20 18.70±0.40

(.551±.008) (.736±.016)

12.00(.472)

REF

16.30±0.40

(.642±.016)

INDEX

64

20

"A"

1

19

LEAD No.

0.15±0.05(.006±.002)

Details of "B" part

1.00(.0394)

TYP

0.40±0.10

(.016±.004)

M

0.20(.008)

Details of "A" part

0.25(.010)

"B"

0.30(.012)

0.18(.007)MAX

0.63(.025)MAX

0.10(.004)

18.00(.709)REF

22.30±0.40(.878±.016)

0

10°

1.20±0.20

(.047±.008)

Dimensions in mm (inches)

C

1994 FUJITSU LIMITED F64013S-3C-2

35

MB89810A Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 1015, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211, Japan

Tel: (044) 754-3753

Fax: (044) 754-3329

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, U.S.A.

Tel: (408) 922-9000

Fax: (408) 432-9044/9045

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

63303 Dreieich-Buchschlag

Germany

Circuit diagrams utilizing Fujitsu products are included as a

means of illustrating typical semiconductor applications. Com-

plete information sufficient for construction purposes is not nec-

essarily given.

Tel: (06103) 690-0

Fax: (06103) 690-122

The information contained in this document has been carefully

checked and is believed to be reliable. However, Fujitsu as-

sumes no responsibility for inaccuracies.

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LIMITED

No. 51 Bras Basah Road,

Plaza By The Park,

The information contained in this document does not convey any

license under the copyrights, patent rights or trademarks claimed

and owned by Fujitsu.

#06-04 to #06-07

Singapore 189554

Tel: 336-1600

Fujitsu reserves the right to change products or specifications

without notice.

Fax: 336-1609

No part of this publication may be copied or reproduced in any

form or by any means, or transferred to any third party without

prior written consent of Fujitsu.

The information contained in this document are not intended for

use with equipments which require extremely high reliability

such as aerospace equipments, undersea repeaters, nuclear con-

trol systems or medical equipments for life support.

F9606

FUJITSU LIMITED Printed in Japan

36


型号：	MB89817A
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontroller 8位微控制器专有微控制器
文件：	总36页 (文件大小：171K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89817A [FUJITSU]

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