MB89821_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12513-3E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89820 Series

MB89821/823/P825/PV820

■ DESCRIPTION

MB89820 series is a line of single-chip microcontrollers using the F²MC-8L* CPU core which can operate at low

voltage but at high speed. In addition to an LCD controller/driver allowing 200-pixel display the microcontrollers

contain a variety of peripheral functions such as timers, a UART, a serial interface, and an external interrupt. The

configuration of the MB89820 series is therefore best suited to control of LCD display panels.

*: F²MC stands for FUJITSU Flexible Microcontroller.

■ FEATURES

• Minimum execution time: 0.8 µs/5 MHz (VCC = +5.0 V)

• F²MC-8L family CPU core

Multiplication and division instructions

16-bit arithmetic operations

Test and branch instructions

Instruction set optimized for controllers

Bit manipulation instructions, etc.

• LCD controller/driver

Max. 50 segments × 4 commons

Divided resistor for LCD power supply

(Continued)

■ PACKAGES

80-pin Plastic QFP

80-pin Ceramic MQFP

(FPT-80P-M11)

(MQP-80C-P01)

MB89820 Series

(Continued)

• Three types of timers

8-bit PWM timer (also usable as a reload timer)

8-bit pulse width count timer (also usable as a reload timer)

20-bit time-base timer

• Two serial interfaces

8-bit synchronous serial interface (Switchable transfer direction allows communication with various equipment.)

UART (5-, 7-, 8-bit transfer capable)

• External interrupt: 2 channels

Capable of wake-up from low-power consumption modes (with an edge detection function)

• Low-power consumption modes

Stop mode (Oscillation stops to minimize the current consumption.)

Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)

■ PRODUCT LINEUP

Part number

MB89821

MB89823

MB89P825

MB89PV820

Parameter

Piggyback/evaluation

product for evaluation and

development

Classification

Mass production product

(mask ROM products)

One-time PROM

product

ROM size

4 K × 8 bits 8 K × 8 bits

(internal mask ROM) (internal mask ROM) (internal PROM,

programming with

16 K × 8 bits

32 K × 8 bits

(external ROM)

general-purpose

EPROM programmer)

RAM size

128 × 8 bits

256 × 8 bits

1024 × 8 bits

CPU functions

Number of instructions:

Instruction bit length:

Instruction length:

136

8 bits

1 to 3 bytes

1, 8, 16 bits

Data bit length:

Minimum execution time:

Interrupt processing time:

0.8 µs/5 MHz (V^CC= 5.0 V)

7.2 µs/5 MHz (V^CC= 5.0 V)

Ports

I/O ports (N-ch open-drain):

I/O ports (CMOS):

16 (All also serve as segment pins.)^*1

6

6 (5 ports also serve as peripheral I/O.)

4 (1 port also serves as an external

interrupt input.)

Input ports:

Total:

32 (max.)

8-bit PWM timer

8-bit reload timer operation (toggled output capable)

8-bit resolution PWM operation

Operating clock (pulse width count timer output: 0.8 µs, 12.8 µs, 51.2 µs/5 MHz)

8-bit pulse width

count timer

8-bit reload timer operation

8-bit pulse width count operation (continuous measurement capable “H” width, “L” width, or

single-cycle measurement capable)

Operating clock (0.8 µs, 3.2 µs, 25.6 µs/5 MHz)

8-bit serial I/O

8 bits

One clock selectable from four transfer clocks

(one external shift clock, three internal shift clock, three internal shift clocks: 1.6 µs, 6.4 µs, 25.6 µs/5 MHz)

LSB first/MSB first selectability

(Continued)

2

MB89820 Series

(Continued)

Part number

MB89823

5-, 7-, 8-bit transfer capable

MB89P825

MB89PV820

MB89821

Parameter

UART

Internal baud-rate generator (max. 78125 bps/5 MHz)

LCD controller/

driver

Common output: 4

Segment output: 50 (max.)

Operating mode: 1/2 bias, 1/2 duty; 1/3 bias, 1/3 duty; 1/3 bias, 1/4 duty

LCD display RAM size: 50 × 4 bits

Dividing resistor for LCD driving: Built-in (An external resistor selectable)

External interrupt

Standby mode

Process

2 channels (edge selectable) (1 channel also serves as a pulse width count timer input)

Sleep mode, stop mode

CMOS

Operating voltage^*2

2.2 V^*3to 6.0 V

2.7 V to 6.0 V

MBM27C256A-20TV

(LCC package)

EPROM for use

*1: The function is selected by the mask option.

*2: Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

*3: The operation at less than 2.2 V is assured separately. Please contact FUJITSU LIMITED.

■ PACKAGE AND CORRESPONDING PRODUCTS

MB89821

Package

MB89823

MB89PV820

MB89P825

FPT-80P-M11

MQP-80C-P01

×

: Available

× : Not available

Note: For more information about each package, see section “■ Package Dimensions.”

3

MB89820 Series

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the piggyback product, verify its differences from the product that will actually be used.

Take particular care on the following points:

• On the MB89821, the register bank address upper than 0140^Hcannot be used. On the MB89823 and

MB89P825, each register bank addresses upper than 0180H can be used.

• On the MB89P825, addresses BFF0H to BFF6H comprise the option setting area, option settings can be read

by reading these addresses.

• The stack area, etc., is set at the upper limit of the RAM.

2. Current Consumption

• In the case of the MB89PV820, add the current consumed by the EPROM which is connected to the top socket.

• However, the current consumption in sleep/stop modes is the same. (For more information, see section

“■ Electrical Characteristics.”

3. Mask Options

Functions that can be selected as options and how to designate these options vary by the product.

Before using options check section “■ Mask Options.”

Take particular care on the following point:

• Options are fixed on the MB89PV820.

4

MB89820 Series

(Top view)

SEG4

SEG3

SEG2

SEG1

SEG0

COM3

COM2

COM1

COM0

V3

V2

V1

X1

X0

V^SS

RST

1

2

3

4

5

6

7

8

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

V^CC

SEG30

SEG31

SEG32

SEG33

P00/SEG34

P01/SEG35

P02/SEG36

P03/SEG37

P04/SEG38

P05/SEG39

P06/SEG40

P07/SEG41

P10/SEG42

P11/SEG43

101

102

103

104

105

106

107

108

109

93

92

91

90

89

88

87

86

85

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

MOD1

MOD0

P45/SCK

P44/SO

P43/SI

P42/PWC/INT1

P41/PWM

P40

Each pin inside the dashed

line is for the MB89PV820 only.

(MQP-80C-P01)

•

Pin assignment on package top (MB89PV820 only)

Pin no.

81

Pin name

N.C.

VPP

Pin no.

89

Pin name

A2

Pin no.

97

Pin name

N.C.

O4

Pin no.

105

Pin name

OE

82

90

A1

98

106

N.C.

A11

A9

83

A12

A7

91

A0

99

O5

107

84

92

N.C.

O1

100

101

102

103

104

O6

108

85

A6

93

O7

109

A8

86

A5

94

O2

O8

110

A13

A14

VCC

87

A4

95

O3

CE

111

88

A3

96

VSS

A10

112

N.C.: Internally connected. Do not use.

6

MB89820 Series

■ PIN DESCRIPTION

Pin no.

Circuit

type

Pin name

Function

QFP^*1

MQFP^*2

14

3

2

6

5

4

X0

X1

A

B

C

Clock crystal oscillator pins

13

18

MOD0

MOD1

RST

Operating mode selection pins

Connect directly to V^SS.

17

16

Reset I/O pin

This pin is an N-ch open-drain type with a pull-up resistor, and

a hysteresis input type. “L” is output from this pin by an internal

reset source (optional function). The internal circuit is

initialized by the input of “L”.

39 to 32 50 to 43 P00/SEG34 to

P07/SEG41

D

General-purpose N-ch open-drain I/O ports

Also serve as an LCD controller/driver segment output.

The port and segment output are switched by mask option in

8-bit unit.

31 to 24 42 to 35 P10/SEG42 to

P17/SEG49

General-purpose N-ch open-drain I/O ports

Also serve as an LCD controller/driver segment output.

The port and segment output are switched by mask option in 4

to 1-bit unit.

22 to 17 34 to 29 P20 to P25

F

General-purpose N-ch open-drain I/O ports

A pull-up resistor option is provided.

16

28

P30/INT0

H

General-purpose input port

The input is hysteresis input.

Also serves as an external interrupt input (INT0).

A pull-up resistor option is provided.

15 to 13 27 to 25 P31 to P33

H

General-purpose input ports

These pins are a hysteresis input type.

A pull-up resistor option is provided.

12

11

24

23

P40

E

General-purpose I/O port

A pull-up resistor option is provided.

P41/PWM

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as an 8-bit PWM timer toggle output (PWM).

10

9

22

21

P42/PWC/INT1

P43/SI

E

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as an 8-bit pulse width count timer input (PWC)

and an external interrupt input (INT1).

The PWC and INT1 input is hysteresis input.

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as an 8-bit serial I/O and a UART data input (SI).

The SI input is hysteresis input.

*1: FPT-80P-M11

*2: MQP-80C-P01

(Continued)

7

MB89820 Series

(Continued)

Pin no.

Circuit

type

Pin name

Function

QFP^*1

MQFP^*2

8

20

P44/SO

E

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as a serial I/O and a UART data output (SO).

7

19

P45/SCK

E

General-purpose I/O port

A pull-up resistor option is provided.

Also serves as a serial I/O and a UART clock I/O (SCK).

The SCK input is hysteresis input.

73 to 40

77 to 74

5 to 1, SEG0 to

80 to 56, SEG33

54 to 51

G

LCD controller/driver segment output pins

9 to 6 COM0 to

COM3

LCD controller/driver common output pins

80 to 78 12 to 10 V1 to V3

—

LCD driving power supply pins

Power supply pin

23

1

55

15

V^CC

V^SS

Power supply (GND) pin

*1: FPT-80P-M11

*2: MQP-80C-P01

8

MB89820 Series

• External EPROM pins (MB89PV820 only)

Pin no.

Pin name

V^PP

I/O

O

Function

82

“H” level output pin

Address output pins

83

84

85

86

87

88

89

90

91

A12

A7

A6

A5

A4

A3

A2

A1

A0

O

93

94

95

O1

O2

O3

I

Data input pins

96

V^SS

O

I

Power supply (GND) pin

Data input pins

98

99

100

101

102

O4

O5

O6

O7

O8

103

CE

O

ROM chip enable pin

Outputs “H” during standby.

104

105

A10

OE

O

Address output pin

ROM output enable pin

Outputs “L” at all times.

107

108

109

A11

A9

A8

O

Address output pins

110

111

112

A13

A14

V^CC

O

EPROM power supply pin

81

92

N.C.

—

Internally connected pins

Be sure to leave them open.

97

106

9

MB89820 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Crystal oscillator circuit

A

• At an oscillation feedback resistor of approximately

1 MΩ/5.0 V

X1

X0

Standby control signal

B

C

• At an output pull-up resistor (P-ch) of approximately

50 kΩ/5.0 V

R

• Hysteresis input

P-ch

N-ch

D

• N-ch open-drain output

• CMOS input

P-ch

N-ch

P-ch

N-ch

Port

• Segment output optional

E

• CMOS output

• CMOS input

R

• Hysteresis input (peripheral input)

P-ch

N-ch

Peripheral

Port

• Pull-up resistor optional

(Continued)

10

MB89820 Series

(Continued)

Type

Circuit

Remarks

F

• N-ch open-drain output

• CMOS input

R

P-ch

N-ch

• Pull-up resistor optional

• LCD controller/driver

G

H

P-ch

N-ch

P-ch

N-ch

• Hysteresis input

R

• Pull-up resistor optional

11

MB89820 Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, take care to prevent the analog power supply (AV^CCand AVR) and analog input from exceeding the digital

power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters

Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore

important. As stabilization guidelines, it is recommended to control power so that V^CCripple fluctuations (P-P

value) will be less than 10% of the standard V^CCvalue at the commercial frequency (50 to 60 Hz) and the transient

fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.

6. Precautions when Using an External Clock

Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and

wake-up from stop mode.

12

MB89820 Series

■ PROGRAMMING TO THE EPROM ON THE MB89P825

The MB89P825 is an OTPROM (one-time PROM) version for the MB89820 series.

1. Features

• 16-Kbyte PROM on chip

• Options can be set using the EPROM programmer.

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in EPROM mode is diagrammed below.

Address

Single chip

EPROM mode

(Corresponding addresses on EPROM programmer)

0000^H

0080H

I/O

RAM

0180H

8000H

Not available

0000H

Vacancy

(Read value FFH)

Not available

Option area

BFF0H

BFF6H

3FF0H

Option area

3FF6H

Vacancy

(Read value FF^H)

4000^H

Not available

C000H

PROM

16 KB

EPROM

16 KB

FFFFH

7FFFH

3. Programming to the EPROM

In EPROM mode, the MB89P825 functions equivalent to the MBM27C256A. This allows the PROM to be

programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by

using the dedicated socket adapter.

•

Programming procedure

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 4000^Hto 7FFFH (note that addresses C000H to FFFFH

while operating as a single chip assign to 4000H to 7FFFH in EPROM mode).

Load option data into addresses 3FF0^Hto 3FF5H of the EPROM programmer. (For information about each

corresponding option, see “7. OTPROM Option Bit Map.”

(3) Program with the EPROM programmer.

13

MB89820 Series

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product for a product

with a blanked OTPROM microcomputer program.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

5. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

6. EPROM Programmer Socket Adapter

Package

Compatible socket adapter

FPT-80P-M11

ROM-80QF2-28DP-8L3

Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760

14

MB89820 Series

7. OTPROM Option Bit Map

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Oscillation

Vacancy

Reset pin

output

1: Yes

Power-on

reset

1: Yes

0: No

stabilization time

3FF0^H

3FF1^H

3FF2^H

3FF3^H

3FF4^H

3FF5^H

1: 2¹⁷/FC

Readable

0: 2¹³/FC

0: No

Vacancy

Readable

Vacancy

Readable

Vacancy

P25

P24

P23

P22

P21

P20

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Readable

Vacancy

P45

P44

P43

P42

P41

P40

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Readable

Vacancy

P33

P32

P31

P30

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Readable

Notes: • Set each bit to 1 to erase.

• Do not write 0 to the vacant bit.

The read value of the vacant bit is 1, unless 0 is written to it.

15

MB89820 Series

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TV

2. Programming Socket Adapter

To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato

Co., Ltd.) listed below.

Package

Adapter socket part number

LCC-32 (Rectangle)

ROM-32LC-28DP-YG

Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760

3. Memory Space

Memory space in each mode, such as 32 Kbyte PROM, option area is diagrammed below.

Address

0000H

Single chip

Corresponding addresses in EPROM programmer

I/O

0080H

0480H

RAM

Not available

8000H

0000^H

PROM

32 KB

EPROM

32 KB

FFFFH

7FFFH

4. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 0000^Hto 7FFFH.

(3) Program to 0000H to 7FFFH with the EPROM programmer.

16

MB89820 Series

■ BLOCK DIAGRAM

X0

X1

20-bit time-base

timer

Oscillator

Clock controller

P41/PWM

8-bit PWM timer

External

interrupt

Reset circuit

(WDT)

RST

8-bit pulse

width timer/

counter

Noise

P42/PWC/INT1

cancel-

lation

Port 2

N-ch open-drain

I/O port

6

P45/SCK

P44/SO

P43/SI

P20 to P25

8-bit serial I/O

External

interrupt

UART

P30/INT0

3

P40

Port 3

I/O port

CMOS I/O port

P31 to P33

N-ch open-drain I/O port

RAM

8

P00/SEG34

16

to P07/SEG41

F²MC-8L

CPU

8

P10/SEG42

to P17/SEG49

LCD

ROM

controller/driver

34

4

SEG0 to SEG33

COM0 to COM3

V1 to V3

Other pins

MOD0, MOD1,

V^CC, VSS

3

17

MB89820 Series

■ CPU CORE

1. Memory Space

The microcontrollers of the MB89820 series offer a memory space of 64 Kbytes for storing all of I/O, data, and

program areas. The I/O area is located at the lowest address. The data area is provided immediately above the

I/O area. The data area can be divided into register, stack, and direct areas according to the application. The

program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of

interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89820 series is structured as illustrated below.

Memory Space

MB89821

MB89823

MB89P825

MB89PV820

0000H

0080H

0000H

0080H

0000H

0080H

0000H

0080H

00C0H

0100H

0140H

I/O

Vacancy

RAM

0100^H

0200H

0100H

0180H

0100H

0180H

1 KB

192 B

256 B

Register

0480H

8000H

Unused

C000^H

External ROM

32 KB

E000^H

PROM

16 KB

F000^H

FFFF^H

ROM

8 KB

ROM

4 KB

FFFF^H

18

MB89820 Series

2. Registers

The F²MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The following dedicated registers are provided:

Program counter (PC):

Accumulator (A):

A 16-bit register for indicating instruction storage positions

A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator

When the instruction is an 8-bit data processing instruction, the lower byte is used.

Index register (IX):

Extra pointer (EP):

Stack pointer (SP):

Program status (PS):

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit register for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

Initial value

16 bits

PC

A

: Program counter

: Accumulator

FFFD^H

Undefined

T

: Temporary accumulator

: Index register

IX

EP

SP

PS

: Extra pointer

: Stack pointer

: Program status

I-flag = 0, IL1, IL0 = 11

Other bits are undefined.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

PS

RP

Vacancy Vacancy Vacancy

H

IL1, 0

N

V

C

RP

CCR

19

MB89820 Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

Rule for Conversion of Actual Addresses of the General-purpose Register Area

RP

Lower OP codes

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0

when reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low = no interrupt

N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.

Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.

V-flag: Setifthecomplementon2overflowsasaresultofanarithmeticoperation. Resetiftheoverflowdoesnot

occur.

C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.

Set to the shift-out value in the case of a shift instruction.

20

MB89820 Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 16 banks can be used on the MB89823 (RAM 256 × 8 bits). The bank currently

in use is indicated by the register bank pointer (RP).

Note: The number of register banks that can be used varies with the RAM size.

MB89821

MB89823

MB89P825

MB89PV820

0100^Hto 013FH

0100H to 017FH

0100H to 01FFH

8 banks

16 banks

32 banks

Register Bank Configuration

This address = 0100 H + 8 × (RP)

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

16 banks

Memory area

21

MB89820 Series

■ I/O MAP

Address

00^H

01^H

02^H

03H

04^H

05^H

06H

07^H

08H

09^H

0AH

0BH

0C^H

0DH

0EH

0F^H

10H

11^H

12H

13H

14^H

15H

16H

17^H

18^H

19H

1AH

1B^H

1CH

1DH

1E^H

1FH

Read/write

Register name

Register description

Port 0 data register

(R/W)

PDR0

Vacancy

(R/W)

PDR1

PDR2

Port 1 data register

Vacancy

Port 2 data register

Vacancy

(R/W)

STBC

WDTC

TBCR

Standby control register

Watchdog timer control register

Time-base timer control register

Vacancy

(R)

PDR3

Port 3 data register

Vacancy

(R/W)

(W)

PDR4

DDR4

Port 4 data register

Port 4 data direction register

Vacancy

(R/W)

(W)

CNTR

COMR

PCR1

PCR2

RLBR

NCCR

PWM timer control register

PWM timer compare register

PWC pulse width control register 1

PWC pulse width control register 2

PWC reload buffer register

PWC noise cancellation control register

Vacancy

(R/W)

Vacancy

(R/W)

SMR

SDR

Serial mode register

Serial data register

Vacancy

(Continued)

22

MB89820 Series

(Continued)

Address

Read/write

(R/W)

Register name

SMC1

Register description

20^H

21H

UART serial mode control register 1

(R/W)

SRC

UART serial rate control register

UART serial status/data register

UART serial data register

UART serial mode control register 2

Vacancy

22^H

(R/W)

SSD

23^H

(R/W)

SIDR/SODR

SMC2

24H

(R/W)

25^H

26^H

Vacancy

27H

Vacancy

28^H

Vacancy

29H

Vacancy

2A^H

Vacancy

2BH

Vacancy

2CH

Vacancy

2D^H

Vacancy

2EH

Vacancy

2FH

Vacancy

30^H

(R/W)

EIC1

External interrupt 1 control register

Vacancy

31H to 5FH

60^Hto 78H

79H

(R/W)

VRAM

LCR1

SEGR

Display data RAM

LCD controller/driver control register

Segment output selection register

Vacancy

7AH

7B^H

7CH

(W)

ILR1

ILR2

ILR3

Interrupt level setting register 1

Interrupt level setting register 2

Interrupt level setting register 3

Vacancy

7DH

7E^H

7F^H

Note: Do not use vacancies.

23

MB89820 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min.

Max.

VSS – 0.3

VSS + 7.0

Power supply voltage

V^CC

V3

V

LCD power supply voltage

V3 pin

V^I1must not exceed VSS + 7.0 V.

Except P00 to P07 and P10 to P17

for the MB89P825/PV820, and P20

to P25 without a pull-up resistor

VSS – 0.3

VCC + 0.3

V^I1

V

P00 to P07 and P10 to P17 (when

selected as ports) for the MB89821/

823, and P20 to P25 without a pull-

up resistor

Input voltage

VSS – 0.3

VSS + 7.0

V3 + 0.3

VCC + 0.3

V^I2

V^I3

V^O1

V

P00 to P07 and P10 to P17 for the

MB89P825/PV820

V^O1must not exceed VSS + 7.0 V.

Except P00 to P07 and P10 to P17

for the MB89P825/PV820, and P20

to P25 without a pull-up resistor

P00 to P07 and P10 to P17 (when

selected as ports) for the MB89821/

823, and P20 to P25 without a pull-

up resistor

Output voltage

VSS – 0.3

VSS + 7.0

V

V^O2

P00 to P07 and P10 to P17 for the

MB89P825/PV820

V^O3

I^OL

VSS – 0.3

V3 + 0.3

10

“L” level output current

—

mA Except power supply pins

Average value (operating current ×

mA operating rate)

“L” level average output

current

I^OLAV

—

4

Except power supply pins

Total “L” level output current

“H” level output current

ΣI^OL

—

40

–5

mA

IOH

mA Except power supply pins

Average value (operating current ×

mA operating rate)

“H” level average output

current

IOHAV

—

–2

Except power supply pins

Total “H” level output current

Power consumption

ΣIOH

P^D

—

–10

300

mA

mW

°C

Operating temperature

Storage temperature

TA

–40

–55

+85

Tstg

+150

°C

Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.

Functional operation should be restricted to the conditions as detailed in the operational sections of

this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

24

MB89820 Series

2. Recommended Operating Conditions

(VSS = 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min.

Max.

2.2*

6.0*

V

Normal operation assurance range*

Power supply voltage

V^CC

Retains the RAM state in stop

mode

1.5

6.0

V3 pin

LCD power supply range.

The optimum value is dependent on

the element in use.

LCD power supply voltage

Operating temperature

V3

T^A

V^SS

6.0

V

–40

+85

°C

* : The minimum operating power supply voltage varies with the operating frequency.

6

5

Operation assurance range

4

3

2

1

2

3

4

5

Clock operating frequency (MHz)

4.0 2.0

1.3

1.0

0.8

Minimum execution time (instruction cycle) (µs)

Note: The shaded area is assured only for the MB89821/823.

Figure 1 Operating Voltage vs. Clock Operating Frequency

Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FC.

25

MB89820 Series

3. DC Characteristics

(VCC = V3 = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min.

Typ.

Max.

P00 to P07,

P10 to P17,

P20 to P25,

P30 to P33,

P40 to P45

*1

V^IH

—

VCC + 0.3^*1

V

0.7 V^CC

“H” level input

voltage

RST, MOD0,

MOD1, INT0,

SCK, SI,

VCC + 0.3

V^IHS

—

0.8 VCC

V^CC– 0.3

VSS – 0.3

—

V

PWC/INT1

P00 to P07,

P10 to P17,

P22 to P25,

P30 to P33,

P40 to P45

*1

V^IL

0.3 V^CC

“L” level input

voltage

RST, MOD0,

MOD1, INT0,

SCK, SI,

V^ILS

0.2 VCC

PWC/INT1

P00 to P07 and P10

to P17 (when selected

as ports) for the

Open-drain

output pin

application

voltage

P20 to P25,

P00 to P07,

P10 to P17

V^D

—

VSS – 0.3

—

VCC + 6.0

V

MB89821/823, and

P20 to P25 without

pull-up resistor

“H” level output

voltage

V^OH

P40 to P45 IOH = –2 mA

P00 to P07,

P10 to P17,

I^OL= 1.8 mA

P20 to P25,

2.4

—

VOL1

0.4

V

“L” level output

voltage

P40 to P45

V^OL2

RST

IOL = 4 mA

—

0.4

MOD0, MOD1,

P30 to P33,

P40 to P45

Without pull-up

µA resistor for the

±5

MB89821/823

MOD0, MOD1,

P00 to P07,

P10 to P17,

P30 to P33,

P40 to P45

0.0 V < V^I< V^CC

I^LI1

Without pull-up

resistor for the

—

±5

µA

Input leakage

current

(Hi-z output

leakage current)

MB89P825/PV820

P00 to P07,

P10 to P17,

P20 to P25

Without pull-up

µA resistor for the

—

±1

MB89821/823

0.0 V < V^I< 6.0 V

ILI2

Without pull-up

resistor for the

P20 to P25

µA

MB89P825/PV820

(Continued)

26

MB89820 Series

(Continued)

(VCC =V3 = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min.

Typ.

Max.

P20 to P25,

P30 to P33,

P40 to P45,

RST

Pull-up

resistance

With pull-up

resistor

R^PULL

V1 = 0.0 V

25

50

100

kΩ

Common output

impedance

COM0 to COM3 V1 to V3 = +5.0 V

R^VCOM

RVSEG

R^LCD

—

30

—

60

2.5

15

kΩ

Segment output

impedance

SEG0 to SEG49 V1 to V3 = +5.0 V

LCD divided

resistance

Between V3

and V^SS

—

120

V1 to V3,

LCD leakage

current

COM0 to COM3,

SEG0 to SEG49

I^LCDL

—

±1

µA

MB89821,

mA MB89823,

MB89PV820

—

3.5

4.0

5.0

6.5

FC = 5 MHz

ICC

t^inst*3= 0.8 µs

mA MB89P825

MB89821,

FC = 5 MHz

t^inst*3= 0.8 µs

Sleep mode

Power supply

current^*2

MB89823,

mA

I^CCS

VCC

—

1.1

1.7

MB89PV820,

MB89P825

MB89821,

µA

—

0.1

10

1

MB89823

TA = +25°C

Stop mode

I^CCH

MB89PV820,

µA

10

—

MB89P825

Input

capacitance

Other than

VCC and VSS

C^IN

f = 1 MHz

pF

*1: The input voltage to P00 to P07 and P10 to P17 for the MB89P825/PV820 must not exceed the LCD power

supply voltage (V3 pin voltage).

*2: The measurement condition of power supply current is as follows: the external clock, open output pins and the

external LCD dividing resistor.

In the case of the MB89PV820, the current consumed by the connected EPROM and ICE is not included.

*3: For information on t^inst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

27

MB89820 Series

4. AC Characteristics

(1) Reset Timing

(V^CC= +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min.

Max.

RST “L” pulse width

tZLZH

—

48 tXCYL

—

ns

tZLZH

RST

0.2 VCC

(2) Power-on Reset

Parameter

(V^SS= 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit

Remarks

Min.

Max.

Power-on reset

function only

Power supply rising time

Power supply cut-off time

t^R

—

50

ms

—

Due to repeated

operations

t^OFF

1

—

Note: Make sure that power supply rises within the selected oscillation stabilization time.

If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.

2.0 V

VCC

0.2 V

tOFF

tR

28

MB89820 Series

(3) Clock Timing

Parameter

(V^SS= 0.0 V, TA = –40°C to +85°C)

Value

Typ.

—

Sym-

bol

Condition

Unit

Remarks

Min.

Max.

Clock frequency

F^C

1

5

MHz

ns

X0, X1

Crystal or ceramic

resonator

Clock cycle time

t^XCYL

duty

200

30

—

1000

70

—

Input clock duty ratio*

%

External clock

X0

Input clock rising/

falling time

t^CR

tCF

—

10

ns

* : duty = P^WH/tHCYL, PWL/tHCYL

X0 and X1 Timing and Conditions

tXCYL

PWH

PWL

tCF

tCR

0.8 VCC

X0

0.2 VCC

Clock Conditions

When a crystal

or

ceramic resonator is used

When an external clock in use

X0

X1

X0

X1

Open

F^C

FC

C0

C1

(4) Instruction Cycle

Parameter

Symbol

t^inst

Value (typical)

Unit

Remarks

Instruction cycle

(minimum execution time)

t^inst= 0.8 µs when operating at

4/FC

µs

FC = 5 MHz

29

MB89820 Series

(5) Serial I/O Timing

(V^CC= +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

SCK

Condition

Unit Remarks

Min.

2 t^inst*

–200

Max.

—

Serial clock cycle time

SCK ↓ → SO time

t^SCYC

t^SLOV

tIVSH

t^SHIX

t^SHSL

tSLSH

t^SLOV

tIVSH

t^SHIX

µs

ns

µs

ns

µs

Internal

shift clock

mode

SCK, SO

SI, SCK

SCK, SI

200

—

Valid SI → SCK ↑

0.5 tinst*

1 t^inst*

1 tinst*

0

SCK ↑ → valid SI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK ↓ → SO time

—

SCK

—

External

SCK, SO shift clock

200

—

mode

Valid SI → SCK ↑

SI, SCK

0.5 tinst*

SCK ↑ → valid SI hold time

SCK, SI

—

* : For information on t^inst, see “(4) Instruction Cycle.”

(6) UART Timing

(V^CC= +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

SCK

Condition

Unit Remarks

Min.

2 t^inst*

–200

Max.

—

Serial clock cycle time

SCK ↓ → SO time

t^SCYC

tSLOV

t^IVSH

tSHIX

tSHSL

t^SLSH

tSLOV

tIVSH

tSHIX

µs

ns

µs

ns

µs

Internal

shift clock

mode

SCK, SO

SI, SCK

SCK, SI

200

—

Valid SI → SCK ↑

0.5 tinst*

1 t^inst*

1 tinst*

0

SCK ↑ → valid SI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK ↓ → SO time

—

SCK

—

External

SCK, SO shift clock

200

—

mode

Valid SI → SCK ↑

SI, SCK

0.5 tinst*

SCK ↑ → valid SI hold time

SCK, SI

—

* : For information on t^inst, see “(4) Instruction Cycle.”

30

MB89820 Series

Internal Shift Clock Mode

tSCYC

2.4 V

SCK

SO

0.8 V

tSLOV

2.4 V

0.8 V

t^IVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SI

External Shift Clock Mode

tSHSL

tSLSH

0.8 VCC

SCK

SO

0.2 VCC

tSLOV

2.4 V

0.8 V

t^IVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SI

31

MB89820 Series

(7) Peripheral Input Timing

(V^CC= +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

t^ILIH

t^IHIL

Condition

Unit Remarks

Min.

Max.

Peripheral input “H” pulse

width

2 t^inst*

—

µs

PWC/INT1

INT0

—

Peripheral input “L” pulse

width

2 tinst*

—

* : For information on t^inst, see “(4) Instruction Cycle.”

tILIH

tIHIL

0.8 VCC

PWC/INT1

INT0

0.2 VCC

32

MB89820 Series

■ EXAMPLE CHARACTERISTICS

(1) “L” Level Output Voltage

(2) “H” Level Output Voltage

V^OLvs. IOL

V^CC– VOH vs. IOH

VCC = 2.5 V

V^CC= 2.5 V

V^CC= 2.0 V

V^CC– VOH (V)

1.0

V^OL1(V)

V^CC= 2.0 V

V^CC= 3.0 V

0.6

0.5

0.4

0.3

0.2

0.1

0

V^CC= 4.0 V

TA = +25°C

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

V^CC= 5.0 V

VCC = 6.0 V

VCC = 4.0 V

V^CC= 5.0 V

V^CC= 6.0 V

0

– 1

– 2

– 3

– 4

– 5

I^OH(mA)

0

1

2

3

4

5

6

7

8

9

10

I^OL(mA)

(3) “H” Level Input Voltage/“L” Level Input

Voltage (CMOS Input)

(4) “H” level Input Voltage/“L” Level Input

Voltage (CMOS Hysteresis Input)

V^INvs. VCC

V^IN(V)

V^INvs. VCC

5.0

V^IN(V)

5.0

TA = +25°C

4.5

TA = +25°C

4.5

4.0

VIHS

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3.5

3.0

2.5

2.0

VILS

1.5

1.0

0.5

0

1

2

3

4

5

6

7

V^CC(V)

1

2

3

4

5

6

7

V^CC(V)

VIHS: Threshold when input voltage in hysteresis

characteristics is set to “H” level

V^ILS: Threshold when input voltage in hysteresis

characteristics is set to “L” level

33

MB89820 Series

(5) Power Supply Current (External Clock)

I^CCvs. V CC

I^CCSvs. VCC

I^CC(mA)

I^CCS(mA)

1.5

5.0

TA = +25°C

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

4.5

FC = 5 MHz

4.0

FC = 4.2 MHz

3.5

FC = 3 MHz

3.0

FC = 4.2 MHz

FC = 3 MHz

2.5

2.0

1.5

FC = 1 MHz

1.0

FC = 1 MHz

0.5

0

1

2

3

4

5

6

7

V^CC(V)

1

2

3

4

5

6

7

V^CC(V)

(6) Pull-up Resistance

R^PULLvs. VCC

R^PULL(kΩ)

1,000

TA = +25°C

500

100

50

T^A= +25°C

10

1

2

3

4

5

6

7

V^CC(V)

34

MB89820 Series

■ INSTRUCTIONS

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

#vct

#d8

#d16

dir: b

rel

@

Register indirect (Example: @A, @IX, @EP)

A

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

AH

AL

Lower 8 bits of accumulator A (8 bits)

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the

instruction in use.)

T

TH

TL

IX

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

(Continued)

35

MB89820 Series

(Continued)

Symbol

Meaning

EP

PC

SP

PS

dr

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

Register bank pointer RP (5 bits)

CCR

RP

Ri

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × )

(( × ))

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

Columns indicate the following:

Mnemonic:

~:

Assembler notation of an instruction

Number of instructions

Number of bytes

#:

Operation:

TL, TH, AH:

Operation of an instruction

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH immediately before the instruction

is executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

36

MB89820 Series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

(dir) ← (A)

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

(A) ← (Ri)

(dir) ← d8

( (IX) +off ) ← d8

( (EP) ) ← d8

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

47

48 to 4F

04

05

06

60

92

07

08 to 0F

85

86

87

88 to 8F

D5

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(EP) ← (A)

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

(AH) ← (ext), (AL) ← (ext + 1) AL

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

AL

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

–

(A) ← (IX)

–

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

–

AL

–

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

(A) ↔ (EP)

(A) ↔ (IX)

–

(A) ↔ (SP)

(A) ← (PC)

–

F0

Notes: • During byte transfer to A, T ← A is restricted to low bytes.

• Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

37

MB89820 Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

TL

TH AH

NZVC

OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + (Ri) + C

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3

C2

C0

D8 toDF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

(TL) − (AL)

(T) − (A)

–

13

03

→

C

A

←

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

(A) − (Ri)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

DAS

XOR A

94

52

54

55

57

56

(A) ← (AL) (TL)

(A) ← (AL) d8

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

38

MB89820 Series

(Continued)

Mnemonic

~

#

Operation

TL

TH AH

NZVC

OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) +off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH

NZVC

OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH

NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

39

MB89820 Series

■ INSTRUCTION MAP

40

MB89820 Series

■ MASK OPTIONS

Part number

Specifying procedure

Pull-up resistors

MB89821/823

MB89P825

MB89PV820

No.

Specify when

orderingmasking

Set with EPROM

programmer

Setting not

possible (Fixed)

Without pull-up

resistor

1

2

Selectable by pin

Selectable

Can be set per pin

Can be set

P20 to P25, P30 to P33, P40 to P45

Power-on reset

With power-on

reset

With power-on reset

Without power-on reset

Oscillation stabilization time selection

(F^C= 5 MHz)^*1

Oscillation

stabilization time

Approx. 2¹⁷/FC

(Approx. 26.2 ms)

3

4

Selectable

Can be set

Approx. 2¹⁷/FC (Approx. 26.2 ms)

Approx. 2¹³/FC (Approx. 1.64 ms)

Reset pin output

With reset output

Without reset output

With reset output

Can be set^*3

Segment output switching

50 segments: No port selection

49 segments: Selection of P17

48 segments: Selection of P17 to P16

46 segments: Selection of P17 to P14

42 segments: Selection of P17 to P10

34 segments: Selection of P17 to P10

and P07 to P00

Selectable^*2

Can be set^*3

5

*1: The oscillation settling time is generated by dividing the oscillation clock frequency. Since the oscillation period

is not stable immediately after oscillation has been started, therefore, the oscillation settling time in the above

list should be regarded as a reference.

*2: Port selection must be same setting of the segment output selection register of LCD controller.

*3: Note that, when ports are set, the input voltage value for the port pins are different from those for mask ROM

products.

Ports are set by the register setting of the segment output selection register of LCD controller.

■ ORDERING INFORMATION

Part number

MB89821PFM

MB89823PFM

MB89P825PFM

Package

Remarks

80-pin Plastic QFP

(FPT-80P-M11)

80-pin Ceramic MQFP

(MQP-80C-P01)

MB89PV820CF

41

MB89820 Series

■ PACKAGE DIMENSIONS

80-pin Plastic QFP

(FPT-80P-M11)

16.00±0.20(.630±.008)SQ

1.50⁺^–0⁰^.^.¹²⁰⁰

.059⁺^–.^.⁰⁰⁰⁰⁴⁸

60

61

41

40

14.00±0.10(.551±.004)SQ

15.00

(.591)

NOM

12.35

(.486)

REF

1 PIN INDEX

80

21

1

Details of "A" part

0.10±0.10

LEAD No.

"A"

+0.05

20

(STAND OFF)

0.65(.0256)TYP

0.30±0.10

(.012±.004)

0.127^–0.02

M

(.004±.004)

0.13(.005)

+.002

.005–.001

0.50±0.20

(.020±.008)

0.10(.004)

0

10°

Dimensions in mm (inches)

C

1994 FUJITSU LIMITED F80016S-1C-2

80-pin Ceramic MQFP

(MQP-80P-P01)

18.70(.736)TYP

12.00(.472)TYP

16.30±0.33

(.642±.013)

15.58±0.20

(.613±.008)

1.50(.059)TYP

1.00(.040)TYP

0.80±0.25

(.0315±.010)

INDEX AREA

+0.40

1.20^–0.20

4.50(.177)

TYP

+.016

0.80±0.25

(.0315±.010)

.047^–.008

1.27±0.13

(.050±.005)

INDEX AREA

18.12±0.20

(.713±.008)

22.30±0.33

(.878±.013)

12.02(.473)

TYP

18.40(.724)

REF

10.16(.400)

14.22(.560)

TYP

0.30(.012)

24.70(.972)

TYP

INDEX

6.00(.236)

TYP

0.40±0.10

(.016±.004)

+0.40

1.27±0.13

(.050±.005)

0.30(.012)TYP

7.62(.300)TYP

9.48(.373)TYP

11.68(.460)TYP

0.40±0.10

(.016±.004)

1.20^–0.20

1.50(.059)

TYP

+.016

.047 ^–.008

1.00(.040)

TYP

0.15±0.05 8.70(.343)

(.006±.002) MAX

Dimensions in mm (inches)

C

1994 FUJITSU LIMITED M80001SC-4-2

42


型号：	MB89821
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontroller 8位微控制器专有微控制器
文件：	总43页 (文件大小：531K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89821 [FUJITSU]

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