MB89899PF_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12524-3E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89890 Series

MB89898/899/P899/PV890

■ OUTLINE

The MB89890 series is a line of single-chip microcontrollers containing a great variety of peripheral functions

such as dual clock control systems, 4-stage operating speed controller, DTMF signal generator, timer, PWM timer,

serial interface, modem, A/D converter and external interrupt, as well as compact instruction set.

■ FEATURES

• F²MC-8L family CPU core

• Dual clock control system

• Maximum memory size: 64 Kbytes

• Minimum execution time: 0.5 µs at 8 MHz

• Interrupt processing time: 4.5 µs at 8 MHz

• I/O ports: max. 85 ports

• 21-bit time-base counter

• 8-bit PWM timer

• DTMF generator

• 8/16-bit timer

• 8-bit serial I/O

• Serial I/O with 1-byte buffer

• A/D converter

• Modem timer (pulse-width counter)

• Modem signal output

(Continued)

■ PACKAGE

100-pin Plastic QFP

100-pin Ceramic MQFP

(FPT-100P-M06)

(MQP-100C-P01)

MB89890 Series

(Continued)

• External interrupt: 16 channels

• Power-on reset function

• Low-power consumption modes (subclock mode, watch mode, sleep mode, stop mode)

• CMOS technology

■ PRODUCT LINEUP

Part number

MB89898

MB89899

MB89P899

MB89PV890

Item

Classification

Piggyback/

evaluation product

(for development)

Mass-produced products

(mask ROM products)

One-time product

OTPROM product

ROM size

RAM size

48 K × 8 bits

60 K × 8 bits

(external ROM)

(internal mask ROM) (internal mask ROM) (internal OTPROM)

1.5 K × 8 bits 2.0 K × 8 bits

Instruction bit

length

8 bits

Instruction length

Data bit length

1 to 3 bytes

1, 8, 16 bits

The number of

instructions

136

Clock generator

Internal

Minimum

execution time

0.5 µs at 8 MHz to 8 µs at 8 MHz, 61 µs at 32.768 kHz

4.5 µs at 8 MHz to 72 µs at 8 MHz, 549.3 µs at 32.768 kHz

Interrupt

processing time

Ports

General-purpose output ports (N-ch open-drain):

General-purpose output ports (CMOS):

General-purpose I/O ports (N-ch open-drain):

General-purpose I/O ports (CMOS):

Total:

21 (8)

8 (0)

8 (6)

48 (29)

85 (43)

( ) indicate

shared function

ports.

PWM timer

8 bits × 1 channel

Timer/counter

Serial I/O

8 bits × 2 channels or 16 bits × 1 channel

8-bit serial I/O (with 1-byte buffer) × 1

8 bits × 8 channels

A/D converter

DTMF generator

CCITT all-tone output capable (1 to 0⁽¹⁰⁾, *, #, A to D)

Single-tone output capable

Soft modem

receiving timer

5-bit noise reduction circuit + pulse-width measurement timer

(Continued)

2

MB89890 Series

(Continued)

Part number

MB89899

MB89P899

MB89PV890

MB89898

Item

Soft modem

transmitting

circuit

approximately 1208 bps, approximately 2415 bps modem output

External interrupt

Time-base timer

Watch prescaler

Standby mode

Process

16

21 bits

15 bits

Watch mode, subclock mode, sleep mode, stop mode

CMOS

Operating

voltage*

2.2 V to 6.0 V

2.7 V to 6.0 V

MBM27C512-20TV

EPROM for use

* : Varies with conditions such as operating frequencies.

■ PACKAGE AND CORRESPONDING MODELS

MB89898

Package

MB89899

MB89PV890

MB89P899

FPT-100P-M06

MQP-100C-P01

×

: Available

× : Not available

Note: For more information about each package, see “■ External Dimensions”.

■ DIFFERENCES AMONG MODELS

1. Memory Size

Before evaluating using the piggyback model, verify its difference from the model that will actually be used.

2. Current Consumption

• In the case of the MB89PV890, added is the current consumed by the EPROM which is connected to the top

socket.

• When operated at low speed the product with an OTPROM (EPROM) will consume more current than the

product with a mask ROM. However, the same is current consumption in sleep/stop mode.

3. Mask Options

Functions that can be selected as options and how to designate these options vary with product. Before using

options, check “■ Mask Options”. Take particular care on the following points:

• Options are fixed on the MB89PV890.

• Pull-up resistor options on the MB89P899 are in 2-bit units for P00 to P07, P10 to P17, P60 to P67, P90 to

P97, and PA0 to PA7. Options are in 1-bit units for P40 to P44, P70 to P77, P80 to P87.

3

MB89890 Series

■ PIN ASSIGNMENT

(Top view)

V^CC

X1A

X0A

MOD0

MOD1

X0

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P97/INT27

P96/INT26

P95/INT25

P94/INT24

P93/INT23

P92/INT22

P91/INT21

P90/INT20

P87

P86

P85

P84

P83

X1

VSS

RST

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

P20

P21

P22

P23

P24

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

P82

P81

P80

P77

P76

P75/BSO2

P74/BSI2

P73/BSK2

V^SS

P72/SO2

P71/SI2

P70/SK2

P67/BSO1

P66/BSI1

P65/BSK1

P64

P63/MSKO

(FPT-100P-M06)

4

MB89890 Series

(Top view)

VCC

X1A

X0A

MOD0

MOD1

X0

P97/INT27

P96/INT26

P95/INT25

P94/INT24

P93/INT23

P92/INT22

P91/INT21

P90/INT20

P87

P86

P85

P84

P83

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

X1

V^SS

O7

O8

01

N.C.

A0

RST

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

P20

P21

P22

P23

P24

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

CE

A10

OE

N.C.

A11

A9

A1

P82

P81

P80

P77

A2

A3

P76

P75/BSO2

P74/BSI2

P73/BSK2

V^SS

P72/SO2

P71/SI2

P70/SK2

P67/BSO1

P66/BSI1

P65/BSK1

P64

A4

A5

A8

A6

P63/MSKO

(MQP-100C-P01)

• Pin assignment on package top (MB89PV890 only)

Pin no.

101

Pin name

N.C.

A15

A12

A7

Pin no.

109

Pin name

A2

Pin no.

117

Pin name

N.C.

O4

Pin no.

125

Pin name

OE

102

110

A1

118

126

N.C.

A11

A9

103

111

A0

119

O5

127

104

112

N.C.

O1

120

O6

128

105

A6

113

121

O7

129

A8

106

A5

114

O2

122

O8

130

A13

A14

VCC

107

A4

115

O3

123

CE

131

108

A3

116

V^SS

124

A10

132

N.C.: Internally connected. Do not use.

5

MB89890 Series

■ PIN DESCRIPTION

Pin no.

Pin name

Circuit type

Function

QFP^*1,MQP^*2

6

X0

A

Crystal oscillator pins (8 MHz)

7

X1

3

X0A

B

C

Crystal oscillator pins (32.768 kHz)

2

X1A

4

5

MOD0

MOD1

RST

Operation mode select pins

Connect to V^SS(GND) when using.

9

D

E

G

F

Reset input pin

10 to 17

18 to 25

26 to 33

39

P00 to P07

P10 to P17

P20 to P27

P30/PWM

General-purpose I/O ports

General-purpose I/O port

Also serves as an 8-bit PWM.

40

41

P31/BUZR

P32/MSKI

F

General-purpose I/O port

Also serves as a buzzer output.

General-purpose I/O port

Also serves as a modem timer.

42,

43

P33,

P34

General-purpose I/O ports

44,

45,

46

P35/SK1,

P36/SI1,

P37/SO1

General-purpose I/O ports

Also serve as an 8-bit serial I/O output 1.

34 to 38

85 to 92

P40 to P44

J

General-purpose I/O ports

P50/AN00 to

P57/AN07

H

General-purpose output ports

Also serve as an analog input.

47,

48,

49

P60/TMO1,

P61/TMO2,

P62/TCLK

F

General-purpose I/O ports

Also serve as an 8/16-bit timer.

51

P63/MSKO

General-purpose I/O port

Also serves as a modem output.

52

P64

F

General-purpose I/O port

53,

54,

55

P65/BSK1,

P66/BSI1,

P67/BSO1

General-purpose I/O ports

Also serve as a serial I/O output 1 with 1-byte buffer.

56,

57,

58

P70/SK2,

P71/SI2,

P72/SO2

I

General-purpose I/O ports

Also serve as an 8-bit serial I/O output 2.

(Continued)

*1: FPT-100P-M06

*2: MQP-100C-P01

6

MB89890 Series

(Continued)

Pin no.

Pin name

Circuit type

Function

QFP^*1,MQP^*2

60,

61,

62

P73/BSK2,

P74/BSI2,

P75/BSO2

I

General-purpose I/O ports

Also serve as a serial I/O output 2 with 1-byte buffer.

63,

64

P76,

P77

I

General-purpose I/O ports

65 to 72

73 to 80

P80 to P87

J

General-purpose output ports

P90/INT20 to

P97/INT27

F

General-purpose I/O ports

External interrupt input is hysteresis input.

81,

82,

83

PA0/INT28,

PA1/INT29,

PA2/INTA

F

General-purpose I/O ports

External interrupt input is hysteresis input.

96,

97 to 100

PA3/INTB,

PA4/INT0 to

PA7/INT3

General-purpose I/O ports

External interrupt input is hysteresis input.

95

1, 50

8, 59

93

DTMF

V^CC

K

–

DTMF signal output pin

Power supply pin

V^SS

Power supply (GND) pin

Power supply pin

V^CC(AVCC)

V^SS(AVSS)

AVR

84

Power supply GND pin

A/D converter reference input pin

94

*1: FPT-100P-M06

*2: MQP-100C-P01

7

MB89890 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

Main clock

• Oscillator feedback resistor: approximately

2 MΩ at 5 V

X1

X0

N-ch

P-ch

N-ch

Main clock control signal

B

Subclock

• Oscillator feedback resistor: approximately

4.5 MΩ at 5 V

X1A

N-ch

X0A

P-ch

N-ch

Subclock control signal

C

D

• Output pull-up resistor (P-ch)

At approximately 50 kΩ/5 V

• Hysteresis input

R

P-ch

N-ch

E

• CMOS output

• CMOS input

• Pull-up resistor optional

R

P-ch

N-ch

(Continued)

8

MB89890 Series

(Continued)

Type

Circuit

Remarks

F

• CMOS output

• Hysteresis input

• Pull-up resistor optional

R

P-ch

N-ch

G

H

• CMOS output

P-ch

N-ch

• N-ch open-drain output

• Analog input

P-ch

N-ch

Analog input

I

• N-ch open-drain output

• Hysteresis input

• Pull-up resistor optional

R

P-ch

N-ch

(Continued)

9

MB89890 Series

(Continued)

Type

Circuit

Remarks

J

• N-ch open-drain output

• Pull-up resistor optional

R

P-ch

N-ch

K

• DTMF analog output

OPAMP

10

MB89890 Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in “■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also take care to prevent the analog power supply (AV^CCand AVR) and analog input from exceeding the digital

power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pull-down

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters

Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although operation is assured within the rated range of VCC power supply voltage, a rapid fluctuation of the

voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC

is therefore important. As stabilization guidelines, it is recommended to control power so that V^CCripple

fluctuations (P-P value) will be less than 10% of the standard V^CCvalue at the commercial frequency (50 to 60

Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as

when power is switched.

6. Precautions when Using an External Clock

When an external clock is used, oscillation stabilization time is required for even power-on reset (optional) and

release from stop mode.

11

MB89890 Series

■ PROGRAMMING TO THE EPROM ON THE MB89P899

The MB89P899 is a one-time PROM version of the MB89890 series.

1. Features

• 60-Kbyte PROM on chip

• Option can be set using the EPROM programmer.

• Equivalency to the MBM27C1001, in EPROM mode (when programmed with the EPROM programmer),

supports 4-byte programming mode.

2. Memory Space

Memory space in each mode such as 60-Kbyte PROM, option area is diagrammed below.

Single chip

EPROM mode

Address

(Corresponding addresses

on the EPROM programmer)

00000H

00080H

00000H

I/O

RAM

2 KB

Not available

Option area

00880H

00FE4H

Not available

Option area

00FE4H

00FFCH

01000H

00FFCH

01000H

PROM

60 KB

PROM

60 KB

0FFFFH

1FFFF^H

0FFFF^H

Not available

3. Programming to the EPROM

In EPROM mode the MB89P899 functions equivalent to the MBM27C1001. This allows the EPROM to be

programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by

using the dedicated socket adapter.

When the operating ROM area for a single chip is 60 Kbytes (01000^Hto 0FFFFH ) the EPROM can be programmed

as follows:

• Programming procedure

(1) Set the EPROM programmer to MBM27C1001.

(2) Load program data into the EPROM programmer at 01000^Hto 0FFFFH.

Load option data into addresses 00FE4H to 00FFCH. (For information about each corresponding options,

see “7. Setting OTPROM Options.”)

(3) Program to 00FE4^Hto 00FFCH, and 01000H to 0FFFFH with the EPROM programmer.

12

MB89890 Series

4. Recommended Screening Conditions

High-Temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

OTPROM microcomputer program.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

5. Programming Yield

Due to its nature, bit programming test can’t be conducted as Fujitsu delivery test. For this reason, a programming

yield of 100% cannot be assured at all times.

6. EPROM Programmer Socket Adapter

Compatible socket adapter

Part number

Package

Sun Hayato Co., Ltd.

QFP-100 ROM-100QF-32DP-8LA

MB89P899

Inquiry: Sun Hayato Co., Ltd.:TEL (81)-3-3986-0403

FAX (81)-3-5396-9106

13

MB89890 Series

7. Setting OTPROM Options

The programming procedure is the same as that for the program data. Options can be set by programming

values at the addresses shown on the memory map. The relationship between bits and options is shown on

the following bit map.

• PROM Option Bitmap

Address

Bit 7

Bit 6

Bit 5

Bit 4

Single/

double clock

1: 2 clock

sytems

Bit 3

Reset

output

1: Yes

0: No

Bit 2

Bit 1

Bit 0

Vacancy

Power-on Oscillation stabilization

reset

1: Yes

0: No

time

11 2¹⁸/FCH 10 2¹⁶/FCH

01 2¹²/FCH 00 2³/FCH

Readable

00FE4^H

and writable and writable and writable

0: 1 clcok

system

P17, P16

Pull-up

1: No

P15, P14

Pull-up

1: No

P13, P12

Pull-up

1: No

P11, P10

Pull-up

1: No

P07, P06 P05, P04 P03, P02

P01, P00

Pull-up

1: No

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

00FE8H

00FEC^H

00FF0^H

00FF4^H

00FF8^H

00FFC^H

1: Yes

0: Yes

P67, P66

Pull-up

1: No

P65, P64

Pull-up

1: No

P63, P62

Pull-up

1: No

P61, P60

Pull-up

1: No

P37, P36 P35, P34 P33, P32

P31, P30

Pull-up

1: No

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

PA7, PA6

Pull-up

1: No

PA5, PA4

Pull-up

1: No

PA3, PA2

Pull-up

1: No

PA1, PA0

Pull-up

1: No

P97, P96 P95, P94 P93, P92

P91, P90

Pull-up

1: No

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Vacancy

P44

P43

P42

P41

P40

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Readable

and writable and writable and writable

P77

P76

P75

P74

P73

P72

P71

P70

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P87

P86

P85

P84

P83

P82

P81

P80

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Notes: • Note that option area address values are equivalent to every fourth address to accommodate 4-byte

programming mode.

• Each bit is set to ‘1’ as the initialized value, therefore the pull-up option is not selected.

14

MB89890 Series

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C512-20TV

2. Programming Socket Adapter

To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato

Co., Ltd.) listed below.

Package

Adapter socket part mumber

LCC-32 (Rectangle) ROM-32LC-28DP-YG

Inquiry: Sun Hayato Co., Ltd.:TEL (81)-3-3986-0403

FAX (81)-3-5396-9106

3. Memory Space

MB89PV890

MBM27C512-20TV

0000H

I/O

0080H

0100H

Register

0200H

RAM

2 KB

0880H

1000^H

FFFFH

1000H

External ROM

60 KB

EPROM

60 KB

FFFF^H

4. Programming Procedure

(1) Set the EPROM programmer to MBM27C512-20TV.

(2) Load program data into the EPROM programmer at 1000H to FFFFH.

(3) Program to 1000H to FFFFH with the EPROM programmer.

15

MB89890 Series

■ BLOCK DIAGRAM

CMOS I/O port 3

Timebase timer

8-bit

PWM timer

P30/PWM

P31/BUZR

Reset circuit

(watchdog)

RST

Buzzer output

Modem timer

P32/MSKI

P33

Oscillator

(max. 8 MHz)

X0

X1

P34

8-bit

serial I/O

P35/SK1

P36/SI1

P37/SO1

Clock control

X0A

X1A

Oscillator

(32.768 kHz)

5

N-ch open-drain output port 4

N-ch open-drain output port 5

P40 to P44

8

P00 to P07

P10 to P17

P20 to P27

CMOS I/O port 0

CMOS I/O port 1

CMOS output port 2

8

8-bit

P50/AN00

to P57/AN07

A/D converter

CMOS I/O port 6

P60/TMO1

P61/TMO2

P62/TCLK

8/16-bit timer

Modem output

P63/MSKO

P64

P65/BSK1

P66/BSI1

P67/BSO1

8-bit serial I/O

with 1-byte buffer

RAM

1.5 Kbytes or 2.0 Kbytes

P70/SK2

P71/SI2

P72/SO2

P73/BSK2

P74/BSI2

P75/BSO2

P76

F²MC-8L

CPU

P77

N-ch open-drain I/O port 7

N-ch open-drain output port 8

CMOS I/O pots 9, A

ROM

48 Kbytes or 60 Kbytes

8

P80 to P87

DTMF

8

4

DTMF generator

P90/INT20

to P97/INT27

PA0/INT28

to PA3/INTB

PA4/INT0

12

External interrupt 2

The other pins

VCC × 2,VSS × 2

MOD0, MOD1

AVCC, AVR, AVSS

to PA7/INT3

4

External interrupt 1

16

MB89890 Series

■ CPU CORE

1. Memory Space

The microcontrollers of the MB89890 series offer 64 Kbytes of memory for storing all of I/O, data, and program

areas. The I/O area is allocated from the lowest address. The data area is allocated immediately above the I/

O area. The data area can be divided into register, stack, and direct areas, according to the application. The

program area is allocated from exactly the opposite end, that is, near the highest address. The tables of interrupt

reset vectors and vector call instructions are allocated from the highest address within the program area. The

memory space of the MB89890 series is structured as illustrated below:

• Memory Space

MB89898

I/O

MB89899

I/O

MB89P899

I/O

MB89PV890

I/O

0000H

007FH

0080H

007FH

0080H

007FH

0080H

007FH

0080H

00FFH

0100H

00FFH

0100H

00FFH

0100H

00FFH

0100H

Register

01FFH

0200H

01FFH

0200H

01FFH

0200H

01FFH

0200H

RAM

1.5 KB

2.0 KB

067FH

0680H

087FH

0880H

087FH

0880H

087FH

0880H

0FFFH

1000H

0FFFH

1000H

0FFFH

1000H

3FFFH

4000H

ROM

48 KB

ROM

60 KB

ROM

60 KB

External ROM

60 KB

FFFFH

17

MB89890 Series

2. Registers

The F²MC-8L family has two types of registers; dedicated hardware registers in the CPU and general-purpose

memory registers. The following dedicated registers are provided:

Program counter (PC):

Accumulator (A):

A 16-bit-long register for indicating the instruction storage positions

A 16-bit-long temporary register for arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit-long register which is used for arithmetic operations with the accumulator

When the instruction is an 8-bit data processing instruction, the lower byte is used.

Index register (IX):

Extra pointer (EP) :

Stack pointer (SP) :

Program status (PS) :

A 16-bit-long register for index modification

A 16-bit-long pointer for indicating a memory address

A 16-bit-long pointer for indicating a stack area

A 16-bit-long register for storing a register pointer, a condition code

Initial value

16 bits

PC

A

: Program counter

: Accumulator

FFFD^H

indeterminate

T

: Temporary accumulator indeterminate

IX

: Index register

: Extra pointer

: Stack pointer

: Program status

indeterminate

EP

SP

PS

I-flag = 0, IL1, 0 = 11

The other bit values are indeterminate.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR) (see the diagram below).

• Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

Vacancy Vacancy Vacancy

PS

RP

H

IL1, 0

N

V

C

RP

CCR

18

MB89890 Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

• Rule for Conversion of Actual Addresses of the General-purpose Register Area

RP

Lower OP codes

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data, and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.

Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared

to ‘0’ at the reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

0

1

2

3

High

0

1

0

1

Low

N-flag: Set to ‘1’ if the highest bit becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ otherwise.

Z-flag: Set to ‘1’ when an arithmetic operation results in ‘0’. Cleared to ‘0’ otherwise.

V-flag: Set to ‘1’ if the complement on ‘2’ overflows as a result of an arithmetic operation. Cleared to ‘0’ if the

overflow does not occur.

C-flag: Set to ‘1’ when a carry or borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to ‘0’

otherwise. Set to the shift-out value in the case of a shift instruction.

19

MB89890 Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit-long register for storing data

The general-purpose registers are of 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 32 banks can be used. The bank currently in use is indicated by the register

bank pointer (RP).

• Register Bank Configuraiton

This address = 0100H + 2 × (RP)

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

32 banks

Memory area

20

MB89890 Series

■ I/O MAP

Address

00^H

01^H

02^H

03H

04^H

05^H

06H

07^H

08H

09^H

0AH

0BH

0C^H

0DH

0EH

0F^H

10H

11^H

12H

13H

14^H

15H

16H

17^H

18^H

19H

1AH

1B^H

1CH

1DH

1E^H

1FH

Write/read

(R/W)

(W)

Register name

PDR0

Register description

Port 0 data register

DDR0

Port 0 data direction register

Port 1 data register

Port 1 data direction register

Port 2 data register

Vacancy

(R/W)

(W)

PDR1

DDR1

(R/W)

PDR2

Vacancy

(R/W)

SCC

SMC

System clock control register

Standby control register

Watchdog control register

Time-base timer control register

Watch prescaler control register

Port 3 data register

Port 3 data direction register

Port 4 data register

Buzzer register

WDTC

TBTC

WPCR

PDR3

DDR3

PDR4

BZCR

PDR5

Port 5 data register

Vacancy

(R/W)

PDR6

DDR6

PDR7

Port 6 data register

Port 6 direction register

Port 7 data register

Vacancy

(R/W)

PDR8

Port 8 data register

Vacancy

(R/W)

(W)

PDR9

DDR9

PDRA

DDRA

SMR

Port 9 data register

Port 9 data direction register

Port A data register

Port A data direction register

Serial mode register

Serial data register

PWM control register

PWM compare register

SDR

CNTR

COMR

(Continued)

21

MB89890 Series

(Continued)

Address

20^H

Write/read

(R/W)

(W)

Register name

DTMC

Register description

DTMF control register

21H

DTMD

DTMF data register

22^H

SBMR

Serial mode register with1-byte buffer

Serial flag register with1-byte buffer

Serial write register with1-byte buffer

Serial read register with1-byte buffer

Serial data register with1-byte buffer

Timer 2 control register

Timer 1 control register

Timer 2 data register

23^H

SBFR

SBUFW

SBUFR

SBDR

24^H

(R)

25^H

26H

27^H

28H

29^H

2AH

2BH

2C^H

2DH

2EH

2F^H

30H

31^H

32H

33H

34^H

35H

36H

37^H

38^H

39H

3AH

3B^H

3CH

3DH

3E^H

3FH

(R)

(R/W)

T2CR

T1CR

T2DR

T1DR

Timer 1 data register

MODC

MODA

Modem output control register

Modem output data register

Vacancy

(R/W)

ADC1

ADC2

ADCD

EIE1

A/D converter control register 1

A/D converter control register 2

A/D converter data register

External interrupt 1 enable register

External interrupt 1 flag register

External interrupt 2 enable register

External interrupt 2 flag register

Modem timer control 1 register

Modem timer control 2 register

Modem timer “H” level data register

Modem timer “L” level data register

Vacancy

EIF1

EIE2

EIF2

MDC1

MDC2

MLDH

MLDL

Vacancy

(R/W)

SSEL

Serial I/O port switching register

Vacancy

(Continued)

22

MB89890 Series

(Continued)

Address

Write/read

Register name

Register description

40^Hto 7BH

7CH

Vacancy

(W)

ILR1

ILR2

ILR3

Interrupt level register 1

Interrupt level register 2

Interrupt level register 3

Vacancy

7D^H

7E^H

7FH

Note: Do not use vacancies.

23

MB89890 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

V^CC

VSS – 0.3

VSS + 7.0

V

AV^CC

Set VCC = AVCC*

Power supply voltage

AVR must not exceed “AV^CC+

0.3 V”.

AVR

V^I

V^SS– 0.3

VSS – 0.3

VSS + 7.0

VCC + 0.3

V

Except P40 to P44, P70 to P77,

P80 to P87

Input voltage

P40 to P44, P70 to P77,

P80 to P87

V^SS– 0.3

VSS – 0.3

VSS + 7.0

VCC + 0.3

20

V

Output voltage

V^O

I^OL

“L” level maximum output

current

mA Peak value

Specified by the average value

of 1 hour.

“L” level average output current

I^OLAV

∑IOL

∑I^OLAV

I^OH

10

mA

“L” level total maximum output

current

120

40

mA Peak value

“L” level total average output

current

Specified by the average value

of 1 hour.

mA

“H” level maximum output

current

–20

–10

–60

–20

mA Peak value

Specified by the average value

of 1 hour.

“H” level average output current

IOHAV

∑I^OH

∑I^OHAV

mA

“H” level total maximum output

current

mA Peak value

“H” level total average output

current

Specified by the average value

of 1 hour.

mA

Power consumption

Operating temperature

Storage temperature

P^D

200

+85

mW

°C

TA

–20

–55

Tstg

+150

°C

* : Use AVCC and VCC set to the same voltage.

Take care so that AVCC does not exceed VCC, such as when power is turned on.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

24

MB89890 Series

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

2.2*

6.0

V

See Figure 1.

V^CC

AVCC

Retains the RAM state in the

stop mode

Power supply voltage

Operating temperature

1.5

6.0

AVR

T^A

2.0

AV^CC

+85

V

–20

°C

* : This value varies with the DTMF generator assurance range.

Figure 1 Operation Assurance Range

6

: Highest gear speed

: Lowest gear speed

5

Operation assurance range

4

3

2

1

2

3

4

5

6

7

8

9

10

Main clock operating frequency (MHz)

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All

the device’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

25

MB89890 Series

3. DC Characteristics

(AVCC = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –20°C to +85°C)

Value

Symbol

Parameter

Condition

Unit Remarks

Min.

Typ.

Max.

P00 to P07, P10 to P17

VCC + 0.3

V^IH

—

0.7 VCC

—

V

P30 to P37, P60 to P67,

P90 to P97, PA0 to PA7,

RST, MOD0, MOD1,

X0, X0A

“H” level input

voltage

V^IHS

—

0.8 VCC

VSS − 0.3

—

VCC + 0.3

0.3 VCC

0.2 VCC

V

P00 to P07, P10 to P17

V^IL

P30 to P37, P60 to P67,

P90 to P97, PA0 to PA7,

RST, MOD0, MOD1,

X0, X0A

“L” level input

voltage

V^ILS

P40 to P47, P70 to P77,

P80 to P87

N-ch open-

drain

VSS − 0.3

VSS + 7.0

VCC + 0.3

—

V

Open-drain

output pin

applied voltage

V^D

N-ch open-

drain

P50 to P57

V

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P60 to P67, P90 to P97,

PA0 to PA7

“H” level output

voltage

V^OH

IOH = –2.0 mA

IOL = 4.0 mA

2.4

—

V

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P60 to P67, P90 to P97,

PA0 to PA7

V^OL1

0.4

“L” level output

voltage

RST

V^OL2

V^OL3

IOL = 4.0 mA

IOL = 8.0 mA

—

0.4

0.6

V

P40 to P44, P70 to P77,

P80 to P87

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P40 to P44, P50 to P57,

Input leakage

current

P60 to P67, P70 to P77, 0.45 V < V^I< VCC

P80 to P87, P90 to P97,

PA0 to PA7, MOD0,

(Hi-z output

leakage

current)

I^LI

—

±5

µA

MOD1

(Continued)

26

MB89890 Series

(Continued)

(AVCC = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –20°C to +85°C)

Value

Symbol

Parameter

Condition

Unit Remarks

Min.

Typ.

Max.

FCH = 4 MHz

V^CC= 5.0 V

in the main

clock

Highest

mA

—

6

9

gear speed

operation

FCH = 4 MHz

V^CC= 3.0 V

in the main

clock

Lowest

mA

—

1.2

13

3

1.8

26

5

gear speed

operation

I^CC

FCH = 8 MHz

V^CC= 5.0 V

in the main

clock

Highest

mA

gear speed

operation

FCH = 8 MHz

V^CC= 3.0 V

in the main

clock

Lowest

mA

gear speed

Power supply

current

operation

VCC

FCH = 4 MHz

V^CC= 5.0 V

in the main

sleep mode

Highest

mA

—

2.5

4

8

gear speed

I^CCS1

FCH = 8 MHz

V^CC= 5.0 V

in the main

sleep mode

Highest

mA

gear speed

FCL =

32.768 kHz

V^CC= 3.0 V

in the

subclock

sleep mode

I^CCS2

—

15

—

2.5

µA

TA = +25°C

V^CC= 3.0 V

in the

I^CCH1

1

µA

subclock

stop mode

(Continued)

27

MB89890 Series

(Continued)

(AVCC = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –20°C to +85°C)

Value

Symbol

Parameter

Condition

Unit Remarks

Min.

Typ.

Max.

TA = +85°C

V^CC= 3.0 V

in the

I^CCH2

—

1

10

µA

subclock

stop mode

FCL =

32.768 kHz

V^CC= 3.0 V

in the

subclock

operation

I^CSB

—

50

75

µA

FCL =

32.768 kHz

V^CC= 3.0 V

in the watch

mode

I^CCT

—

8

15

12

3.4

31

FCH = 4 MHz

V^CC= 5.0 V

in the main

clock

VCC

Highest

mA

gear speed

operation

Power supply

current

FCH = 4 MHz

V^CC= 3.0 V

in the main

clock

Lowest

mA

2.3

17

gear speed

operation

I^CCD

FCH = 8 MHz

V^CC= 5.0 V

in the main

clock

Highest

mA

gear speed

operation

FCH = 8 MHz

V^CC= 3.0 V

in the main

clock

Lowest

mA

—

6

11

gear speed

operation

When A/D

mA conversion

is operating

I^A

1.5

3.5

AVCC

FCH = 8 MHz

When A/D

conversion

is not

operating

IAH

—

1

5

µA

Other than AVCC,

AVSS, VCC, and VSS

Input capacitance C^IN

—

10

—

pF

28

MB89890 Series

4. AC Characteristics

(1) Reset Timing

(VCC = +5.0 V±10%, VSS = 0.0 V, TA = –20°C to +85°C)

Value

Symbol

Condition

Unit

Remarks

Parameter

Min.

Max.

—

RST “L” pulse width

RST “H” pulse width

tZLZH

tZHZL

48 t^XCYL

24 tXCYL

ns

—

Note: tXCYL is the oscillation cycle input to the X0.

tZLZH

tZHZL

RST

0.8 VCC

0.2 VCC

(2) Power-on Reset

(VSS = 0.0 V, TA = –20°C to +85°C)

Value

Min. Max.

Symbol Condition

Unit

Remarks

Parameter

Power supply rising time

Power supply cut-off time

t^R

—

1

50

—

ms

Power-on reset function only

Due to repeated operations

—

t^OFF

Note: Make sure that power supply rises within the selected oscillation stabilization time selected.

If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is

recommended.

tOFF

t^R

2.0 V

0.2 V

V

CC

29

MB89890 Series

(3) Clock Timing

(VCC = +5.0 V±10%, VSS = 0.0 V, TA = –20°C to +85°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Clock frequency

Clock cycle time

Min.

1

Typ.

—

Max.

8

F^CH

X0, X1

MHz Main clock

kHz Subclock

ns Main clock

µs Subclock

FCL

X0A, X1A

X0, X1

—

32.768

—

tHCYL

tLCYL

125

—

1000

—

X0A, X1A

30.5

P^WH

PWL

X0

20

—

15.2

—

ns External clock

—

Input clock pulse width

P^WLH

PWLL

X0A

X0

µs External clock

t^CR1

tCF1

24

ns

Input clock rising/falling

time

External clock

ns

t^CR2

tCF2

X0A

—

200

30

MB89890 Series

• X0 and X1 Timing and Conditions of Applied Voltage

t^HCYL

0.8 VCC

X0

0.2 VCC

P^WH

PWL

tCF1

tCR1

• Main Clock Conditions

When a crystal

or

ceramic resonator is used

When an external clock is used

X0

X1

X0

X1

Open

F^CH

C1

FCH

C0

• X0A and X1A Timing and Conditions of Applied Voltage

tLCYL

0.8 VCC

X0A

0.2 VCC

P^WHL

PWLL

tCF2

tCR2

• Subclock Conditions

When a crystal

or

ceramic resonator is used

When an external clock is used

X0A

X1A

X0A

X1A

Rd

Open

FCL

C0

C1

31

MB89890 Series

(4) Instruction Cycle

Symbol

Value

Unit

Remarks

Parameter

(4/F^CH) tinst = 0.5 µs when

operating at F^CH= 8 MHz

4/FCH, 8/FCH, 16/FCH, 64/FCH

µs

Instruction cycle

(minimum execution time)

t^inst

t^inst= 61.036 µs when operating at

F^CL= 32.768 kHz

2/F^CL

µs

*1: When operating at the main clock, t^instvaries with the execution time (gear) setting, within the following range:

Min. = 4/FCH, Max. = 64/FCH.

*2: When operating at the subclock, tinst = 2/FCL.

(5) Recommended Resonator Manufacturers

• Sample Application of Piezoelectric Resonator (FAR Series)

X0

X1

FAR^*1

C1^*2

C2^*2

*1: Fujitsu Acoustic Resonator

Temperature

characteristics of

FAR frequency

Initial deviation of

FAR frequency

(T^A= +25°C)

Loading

FAR part number

(built-in capacitor type)

Frequency (MHz)

capacitors*²

(T^A= –20°C to +60°C)

3.58

±0.5%

FAR-C4 A-03580- 01

FAR-C4 G-10000- 05

Inquiry: FUJITSU LIMITED

Built-in

10.00

32

MB89890 Series

• Sample Application of Ceramic Resonator

X0

X1

C1

C2

• Mask ROM products

Resonator

manufacturer

Resonator

Frequency (MHz)

C1 (pF)

C2 (pF)

R

CSA8.00MTZ

CST8.00MTW

30

Not required

Murata Mfg. Co., Ltd.

8.00

Built-in

Inquiry: Murata Mfg. Co., Ltd

• Murata Electronics North America. Inc.: TEL 1-404-436-1300

• Murata Europe Mnagement GmbH: TEL 49-911-66870

• Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233

33

MB89890 Series

(6) Serial I/O Timing

(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –20°C to +85°C)

Value

Symbol Pin name

Condition

Unit Remarks

Parameter

Min.

2 t^inst*

–200

200

Max.

—

Serial clock cycle time

SCK ↓ → SO time

t^SCYC

tSLOV

t^IVSH

tSHIX

tSHSL

t^SLSH

tSLOV

t^IVSH

tSHIX

SCK

µs

ns

µs

ns

SCK, SO

SI, SCK

SCK, SI

200

—

Internal shift

clock mode

Valid SI → SCK ↑

SCK ↑ → valid SI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK ↓ → SO time

200

—

1 t^inst*

1 tinst*

0

—

SCK

—

External shift

clock mode

SCK, SO

SI, SCK

SCK, SI

200

—

Valid SI → SCK ↑

200

ns

2 × tXCYL

SCK ↑ → valid SI hold time

200

—

* : For information on tinst, see “(4) Instruction Cycle.”

• Internal Shift Clock Mode

tSCYC

2.4 V

SCK

0.8 V

tSLOV

2.4 V

SO

0.8 V

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

SI

0.2 VCC

• External Shift Clock Mode

tSLSH

tSHSL

0.8 VCC

SCK

0.2 VCC

tSLOV

2.4 V

0.8 V

SO

SI

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

34

MB89890 Series

(7) Peripheral Input Timing

Parameter

(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –20°C to +85°C)

Value

Symbol

Unit Remarks

Min.

Max.

Peripheral input “H” level pulse

width

INT20 to INTA

INT0 to INT3

t^ILIH

t^IHIL

2 t^inst*

—

µs

Peripheral input “L” level pulse

width

INT20 to INTA

INT0 to INT3

2 t^inst*

—

* : For information on tinst, see “(4) Instruction Cycle.”

tILIH

tIHIL

INT20 to INTA

INT0 to INT3

0.8 VCC

0.2 V^CC

0.8 VCC

0.2 VCC

35

MB89890 Series

(8) Electrical Characteristics of DTMF Generator

(AVSS = VSS = 0.0 V, TA = –20°C to +85°C)

Value

Typ.

5.0

Symbol

Condition

Unit

Remarks

Parameter

Min.

Max.

Operating voltage range

—

2.5

6.0

V

Defined when

the DTMF pin

kΩ is connected to

a pull-down

VCC = 2.5 V to 6.0

V

Output load requirements

R^O

20

—

resistor.

DTMF output offset voltage

(at signal output)

V^MOF

VCC = 5.0 V

0.4

V

When the

DTMF pin is

open.

DTMF output amplitude

(ROW single tone)

V^MFOR

–16.3 –14.0 –12.5 dBm

Difference between

COLUMN and ROW levels

R^O= 200 kΩ

R^MF

—

1.6

—

2.0

—

2.4

7

dB

%

Distortion ratio

• Output Level Measurement Circuit

VCC

X0

0.1 µF

Lowpass filter

16.0 kHz

DTMF

Audio analizer

Output level

8 MHz

R^O

X1

–48 dB/oct

V^SS

36

MB89890 Series

5. A/D Converter Electrical Characteristics

(AVCC = VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –20°C to +85°C)

Value

Symbol

Remarks

Parameter

Condition

Unit

name

Min.

—

Typ.

—

Max.

8

Resolution

bit

Total error

—

±1.5

±1.0

LSB

—

Linearity error

—

Differential linearity

error

—

±0.9

LSB

mV

AVR =

AV^CC= 5.0 V

AVSS – 1.5

LSB

AVSS + 0.5

LSB

AVSS + 1.5

LSB

Zero transition

voltage

1 LSB =

AVR/256

V^0T

—

AVR – 1.5

LSB

AVR – 1.5

LSB

AVR + 1.5

LSB

Full-scale transition

voltage

VFST

mV

LSB

µs

Interchannel disparity

—

0.5

—

A/D mode conversion

time

44 t^inst*

—

Sense mode

conversion time

—

12 tinst*

—

µs

—

Analog port input

current

I^AIN

—

10

µA

AN0to

AN7

Analog input voltage

Reference voltage

—

0.0

—

AVR

AV^CC

V

When

starting A/D

conversion

I^R

—

100

—

300

1

µA

AVR

Reference voltage

supply current

AVR =

AV^CC= 5.0 V

When

starting A/D

conversion

IRH

* : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

6. A/D Converter Glossary

• Resolution

Analog changes that are identifiable by the A/D converter

When the number of bits is 8, analog voltage can be divided into 2⁸= 256.

• Linearity error (unit: LSB)

The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the

full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics

• Differential linearity error (unit: LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error (unit: LSB)

The difference between theoretical and actual conversion values

37

MB89890 Series

Digital output

Theoretical conversion value

1111 1111

1111 1110

•

Actual conversion value

•

(1 LSB × N + V^OT)

AVR

256

•

1 LSB =

•

V^NT– (1 LSB × N + VOT)

•

Linearity error =

•

1 LSB

•

V( N + 1 ) T – VNT

•

– 1

Differential linearity error =

Total error =

•

1 LSB

Linearity error

•

VNT – (1 LSB × N + 1 LSB)

•

1 LSB

•

0000 0010

0000 0001

0000 0000

VOT

VNT

V(N + 1)T

VFST

Analog input

7. Notes on Using A/D Converter

• Input impedance of the analog input pins

The A/D converter used for the MB89890 series contains a sample hold circuit as illustrated below to fetch

analog input voltage into the sample hold capacitor for eight instruction cycles after starting A/D conversion.

For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage

might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output

impedance of the external circuit low (below 10 kΩ).

Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of approx.

0.1 µF for the analog input pin.

Analog Input Equivalent Circuit

Sample hold circuit

.

C = 33 pF

.

Analog input pin

Comparator

If the analog input

impedance is higher

than 10 kΩ, it is

recommended to

connect an external

capacitor of approx.

0.1 µF.

.

R = 6 kΩ

.

Close for 8 instruction cycles after starting

A/D conversion.

Analog channel selector

• Error

The smaller the | AVR – AV^SS|, the greater the error would become relatively.

• Order of turning on A/D converter and analog input

Make sure to turn on the digital power supply (VCC) before or at the same time with turning on the A/D converter

power supply (AVCC, AVSS) and application of AN00 to AN07.

To turn off the power, turn off the A/D converter power supply (AV^CC, AVSS) and stop the analog input (AN00

to AN07) before or at the same time with turning off the digital power supply (V^CC).

38

MB89890 Series

■ ELECTRICAL CHARACTERISTICS

(1) “L” Level Output Voltage

(2) “H” Level Output Voltage

VOL vs. IOL

V OL (V)

V ^CC– VOH vs. IOL

V CC = 2.2 V

V CC – V OH (V)

1.1

V CC = 2.2 V

V CC = 2.5 V

1.1

T A = +25°C

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V CC = 3.0 V

V CC = 4.0 V

V CC = 3.0 V

V ^CC= 5.0 V

V ^CC= 6.0 V

V CC = 4.0 V

V ^CC= 5.0 V

V ^CC= 6.0 V

T A = +25°C

10

I ^OL(mA)

0

–.5

–1.0 –1.5 –2.0 –2.5 –3.0

I ^OH(mA)

0

1

2

3

4

5

6

7

8

9

(3) “H” Level Input Voltage/“L” Level Input Voltage (4) “H” Level Input Voltage/“L” Level Input Voltage

(CMOS Input)

(Hysteresis Input)

V ^INvs. V CC

V ^IN(V)

5.0

V ^IN(V)

5.0

T A = +25°C

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

–0

T A = +25°C

4.0

V ^IHS

3.5

3.0

2.5

2.0

1.5

1.0

0.5

–0

V ILS

.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00

V ^CC(V)

.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00

V ^CC(V)

V IHS : “H” level input voltage threshold as

hysteresis input

V ^ILS: “L” level input voltage threshold as

hysteresis input

39

MB89890 Series

(5) Power Supply Current (External Clock)

Characteristics of Current Consumption

in the Main Clock Operation

Characteristics of Current Consumption

in the DTMF and Main Clock Operation

I ^CC(mA)

10

I CC vs. V CC

I CCD vs. V CC

I ^CCD(mA)

12

11

Dividing

-by-4

Dividing

-by-4

T A = +25°C

F CH = 8 MHz

9

8

7

6

5

4

3

2

T A = +25°C

F ^CH= 8 MHz

10

9

8

7

6

5

4

3

2

1

0

Dividing

-by-8

Dividing

-by-8

Dividing

-by-16

Dividing

-by-16

Dividing

-by-64

1

0

2

3

4

5

6

4

2

3

5

6

V ^CC(V)

Characteristics of Current Consumption

in the Main Sleep Mode

Characteristics of Current Consumption

in the Subclock Operation

I CCS vs. V CC

I ^CCS(mA)

10

I ^CCSBvs. V CC

I CCSB (µA)

10

T A = +25°C

F ^CH= 8 MHz

9

8

7

6

5

4

3

9

8

7

6

5

4

3

T A = +25°C

F ^CL= 32.768 KHz

Dividing

-by-4

2

1

2

1

0

2.5

0

2.5

3

3.5

4

4.5

5

5.5

6

3

3.5

4

4.5

5

5.5

6

V ^CC(V)

Characteristics of Current Consumption

in the Watch Mode

Characteristics of Current Consumption

in the Subclock Stop

I ^CCTvs. V CC

I ^CCT(µA)

30

I ^CCHvs. V CC

I ^CCH(A)

2.0

T A = +25°C

F ^CL= 32.768 KHz

T A = +25°C

F ^CL= 32.768 KHz

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

25

20

15

10

5

0.2

0.0

0

2

2.5

3

3.5

4

4.5

5

5.5

6

2

2.5

3

3.5

4

4.5

5

5.5

6

V ^CC(V)

40

MB89890 Series

(6) Pull-up Resistance

R ^PULLvs. VCC

R ^PULL(kΩ)

1000

T A = +25°C

300

100

50

10

0

1

2

3

4

5

6

7

V ^CC(V)

41

MB89890 Series

■ INSTRUCTIONS (136 INSTRUCTIONS)

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

#vct

#d8

#d16

dir: b

rel

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

Register indirect (Example: @A, @IX, @EP)

@

A

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

AH

AL

Lower 8 bits of accumulator A (8 bits)

T

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

TH

TL

IX

EP

PC

SP

PS

dr

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

CCR

RP

Ri

Register bank pointer RP (5 bits)

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × )

(( × ))

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

42

MB89890 Series

Columns indicate the following:

Mnemonic:

~:

Assembler notation of an instruction

The number of instructions

The number of bytes

#:

Operation:

TL, TH, AH:

Operation of an instruction

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH prior to the instruction executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

43

MB89890 Series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

47

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

48 to 4F

04

05

06

60

92

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

07

(A) ← (Ri)

(dir) ← d8

08 to 0F

85

86

87

88 to 8F

D5

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

–

AL

–

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

–

F0

Notes: • During byte transfer to A, T ← A is restricted to low bytes.

• Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

44

MB89890 Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3

C2

C0

D8 to DF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

(TL) − (AL)

(T) − (A)

–

13

03

→

C

A

←

C

A

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

(A) − (Ri)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

45

MB89890 Series

(Continued)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

46

MB89890 Series

■ INSTRUCTION MAP

47

MB89890 Series

■ MASK OPTIONS

Part number

MB89898/9

MB89P899

MB89PV890

No.

Specifying not

possible

Specify when

ordering masking

Specify with EPROM

programmer

Specifying procedure

Pull-up resistors

• P00 to P07

• P10 to P17

• P30 to P37

• P40 to P44

• P60 to P67

• P70 to P77

• P80 to P87

• P90 to P97

• PA0 to PA7

Select by single pin

• P00 to P07

• P10 to P17

• P30 to P37

• P40 to P44

• P60 to P67

• P70 to P77

• P80 to P87

• P90 to P97

• PA0 to PA7

Select by 2-pin pair

• P00 to P07

• P10 to P17

• P30 to P37

• P60 to P67

• P90 to P97

• PA0 to PA7

Select by single pin

• P40 to P44

• P70 to P77

Fixed to no

pull-up resistor

1

• P80 to P87

Set in the above

combinations

Set in the above

combinations

Power-on reset (POR)

• Power-on reset provided

• No power-on reset

Fixed to

power-on reset

optional

2

3

Selectable

WTM1 WTM0

Selectable

WTM1 WTM0

Selection of the oscillation

stabilization time (OSC)

The oscillation stabilization time

initial value can be set with

WTM1 bit and WTM0 bit.

0

1

0:

1:

0:

1:

2³/FCH

2¹²/FCH

2¹⁶/FCH

2¹⁸/FCH

0

1

0:

1:

0:

1:

2³/FCH

2¹²/FCH

2¹⁶/FCH

2¹⁸/FCH

Fixed to oscillator

stabilization 2¹⁸/FCH

Reset pin output (RST)

• Reset output provided

• No reset output

Fixed to reset

output optional

4

5

Selectable

Selection of clock mode (CLK)

• Double clock mode

• Single clock mode

Fixed to double

clock mode

■ ORDERING INFORMATION

Part number

Package

Remarks

MB89898PF

MB89899PF

MB89P899PF

100-pin Plastic QFP

(FPT-100P-M06)

100-pin Ceramic MQFP

(MQP-100C-P01)

MB89PV890CF

48

MB89890 Series

■ PACKAGE DIMENSION

100-pin Plastic QFP

(FPT-100P-M06)

23.90±0.40(.941±.016)

20.00±0.20(.787±.008)

3.35(.132)MAX

(Mounting height)

0.05(.002)MIN

(STAND OFF)

80

51

81

50

12.35(.486)

14.00±0.20 17.90±0.40

(.551±.008) (.705±.016)

16.30±0.40

(.642±.016)

REF

INDEX

31

100

"A"

1

30

LEAD No.

0.65(.0256)TYP

0.30±0.10

(.012±.004)

0.15±0.05(.006±.002)

Details of "B" part

M

0.13(.005)

Details of "A" part

0.25(.010)

0.30(.012)

"B"

0.10(.004)

0

10°

0.18(.007)MAX

0.53(.021)MAX

18.85(.742)REF

0.80±0.20

(.031±.008)

22.30±0.40(.878±.016)

C

Dimensions in mm (inches)

1994 FUJITSU LIMITED F100008-3C-2

49

MB89890 Series

100-pin Ceramic MQFP

(MQP-100C-P01)

17.20±0.40 SQ

(.677±.016)

2.70(.106)MAX

(Mounting height)

12.00 ⁺^–0⁰^.^.¹³⁰⁰SQ

0.05(.002)MIN

(STAND OFF)

.472 –⁺.^.0⁰0¹4²

36

25

Details of "A" part

37

24

0.15(.006)

0.20(.008)

8.80

(.346)

REF

13.60±0.40

(.535±.016)

0.15(.006)MAX

0.50(.020)MAX

INDEX

48

13

"A"

Details of "B" part

1

12

LEAD No.

0.15 –⁺0⁰.^.0⁰1⁵

.006 ⁺^–.^.⁰⁰⁰⁰⁰²⁴

0.80(.0315)TYP

0.30±0.06

(.012±.002)

M

0.16(.006)

0~10°

"B"

1.80±0.30

(.071±.012)

0.15(.006)

Dimensions in mm (inches)

C

1994 FUJITSU LIMITED F48026S-1C-1

50


型号：	MB89899PF
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontroller 8位微控制器专有微控制器和处理器外围集成电路时钟
文件：	总51页 (文件大小：639K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89899PF [FUJITSU]

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