MB89P155PFV-201 [FUJITSU]
8-bit Proprietary Microcontroller; 8位微控制器专有型号: | MB89P155PFV-201 |
厂家: | FUJITSU |
描述: | 8-bit Proprietary Microcontroller |
文件: | 总52页 (文件大小:719K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12506-4E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89150/150A Series
MB89151/151A/152/152A/153/153A/154/154A/155/155A
MB89P155/PV150
■ DESCRIPTION
The MB89150/A series has been developed as general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit, single-chip microcontrollers.
In addition to a compact instruction set, the MB89150 series microcontrollers contain a variety of peripheral
functions such as dual-clock control system, five operating speed control stages, timers, a serial interface, a
remote control transmission output, external interrupts, an LCD controller/driver, an LCD booster, and a watch
prescaler.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-8L family CPU core
• Dual-clock system
• High-speed processing at low voltage
• Minimum execution time: 0.95 µs/2.7 V, 1.33 µs/2.2 V
• I/O ports: max. 43 channels
• 21-bit time-base timer
• 8/16-bit timer/counter: 1 channel (8 bits × 2 channels)
• 8-bit serial I/O: 1 channel
• LCD controller/driver: Max. 36 segments × 4 commons (built-in booster)
• Remote control transmission output
(Continued)
■ PACKAGE
80-pin Ceramic MQFP
80-pin Plastic LQFP
80-pin Plastic QFP
80-pin Plastic LQFP
(FPT-80P-M06)
(FPT-80P-M05)
(FPT-80P-M11)
(MQP-80C-P01)
MB89150/150A Series
(Continued)
• Buzzer output
• Watch prescaler (15 bits)
• External interrupts (wake-up function)
Four independent channels with edge detection function plus eight level-interrupt channels
■ PRODUCT LINEUP
Part number
MB89151/A
MB89152/A MB89153/A MB89154/A MB89155/A MB89P155 MB89PV150
Parameter
Piggyback/
evaluation
product (for
evaluationand
development)
Classification
One-time
PROM
product
Mass production products
(mask ROM products)
ROM size
4 K × 8 bits 6 K × 8 bits 8 K × 8 bits 12K × 8bits 16 K × 8 bits 16 K × 8 bits 32 K × 8 bits
(internal
(internal
(internal
(internal
(internal
(internal
(external
ROM)
PROM,
mask ROM) mask ROM) mask ROM) mask ROM) mask ROM)
programming
with general-
purpose
EPROM
programmer)
RAM size
128 × 8 bits
Number of instructions:
256 × 8 bits
136
512 × 8 bits
CPU functions
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
8 bits
1 to 3 bytes
1, 8, 16 bits
0.95 µs/4.2 MHz
8.57 µs/4.2 MHz
Ports
I/O port (N-ch open-drain):
8 (6 ports also serve as peripherals, 3 ports
are a high-current drive type.)
Output port (N-ch open-drain): 18 (16 ports also serve as segment pins, 2 ports
serve as boost capacitor connection pins.)*1
16 (12 ports also serve as an external interrupt.)
1 (Also serves as a remote control.)
43 (max.)
I/O port (CMOS):
Output port (CMOS):
Total:
Timer/counter
8-bit serial I/O
8-bit timer counter × 2 channel or 16-bit event counter × 1 channel
8 bits
LSB first/MSB first selectability
LCD controller/
driver
Common output:
Segment output:
4
No reference
voltage
32 (max.)*1
Bias power supply pins:
LCD display RAM size:
Booster for LCD driving:
Dividing resistor for LCD driving:
4
generator
and booster
for LCD
36 × 4 bits
Built-in*1
driving
Built-in (an external resistor selectability)
External
interrupts
(wake-up function)
4 (edge selectability)
8 (level interrupt only)
Buzzer output
1 (7 frequencies are selectable by the software.)
(Continued)
2
MB89150/150A Series
(Continued)
Part number
MB89151/A
MB89152/A MB89153/A MB89154/A MB89155/A MB89P155 MB89PV150
Parameter
Remote control
transmission
output
1 (Pulse width and cycle are software selectable.)
Standby modes
Process
Sleep mode, stop mode, and watch mode
CMOS
Operating voltage*2
2.2 V to 6.0 V (single clock)/2.2 V to 4.0 V (dual clock)
2.7 V to 6.0 V
MBM27C256A
EPROM for use
-20TV (LCC
package)
*1: Selected by the mask option. See section “■ Mask Options.”
*2: Varies with conditions such as the operating frequency and the connected ICE. (See section “■ Electrical
Characteristics.”)
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89151/A
MB89152/A
MB89153/A
MB89154/A
MB89155/A
Package
MB89P155
MB89PV150
FPT-80P-M06
FPT-80P-M11
FPT-80P-M05
MQP-80C-P01
×
×
×
×
×
: Available
× : Not available
Note: For more information about each package, see section “■ Package Dimensions.”
3
MB89150/150A Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
• On the MB89151/A, addresses 0140H and later of the register bank cannot be used. On the MB89152/A,
153/A, 154/A, 155/A, and MB89P155, addresses 0180H and later of each register bank cannot be used.
• On the MB89P155, addresses BFF0H to BFF6H comprise the option setting area, option settings can be read
by reading these addresses.
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
• In the case of the MB89PV150, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in sleep/stop modes is the same. (For more information, see sections
“■ Electrical Characteristics” and “■ Example Characteristics.”)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product.
Before using options check section “■ Mask Options.”
Take particular care on the following point:
• On the MB89PV150, options are fixed, except for the segment output selection.
4
MB89150/150A Series
■ PIN ASSIGNMENT
(Top view)
P43/SEG23*4
P44/SEG24*4
P45/SEG25*4
P46/SEG26*4
P47/SEG27*4
P50/SEG28*4
P51/SEG29*4
P52/SEG30*4
P53/SEG31*4
P54/SEG32*4
P55/SEG33*4
P56/SEG34*4
VSS
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG2
SEG1
SEG0
COM3
COM2
COM1
COM0
VCC
V3
V2
V1
V0
9
10
11
12
13
14
15
16
17
18
19
20
P32*2/C0*1
P31*2/C1*1
P30/RCO
X1A
P57/SEG35*4
X1
X0
MOD1
MOD0
RST
X0A
P27/BUZ*3
P26*3
P25/SCK
P00/INT20
(FPT-80P-M05)
*1: For products with a booster circuit
*2: For products without a booster circuit
*3: N-ch open-drain high-current drive type
*4: Selected using the mask option (in units of 4 pins)
5
MB89150/150A Series
(Top view)
P43/SEG23*4
P44/SEG24*4
P45/SEG25*4
P46/SEG26*4
P47/SEG27*4
P50/SEG28*4
P51/SEG29*4
P52/SEG30*4
P53/SEG31*4
P54/SEG32*4
P55/SEG33*4
P56/SEG34*4
VSS
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG2
SEG1
SEG0
COM3
COM2
COM1
COM0
V CC
V3
V2
V1
V0
9
10
11
12
13
14
15
16
17
18
19
20
P32*2/C0*1
P31*2/C*1
P30/RCO
X1A
P57/SEG35*4
X1
X0
MOD1
MOD0
RST
X0A
P27/BUZ*3
P26*3
P25/SCK
P00/INT20
(FPT-80P-M11)
*1: For products with a booster circuit
*2: For products without a booster circuit
*3: N-ch open-drain high-current drive type
*4: Selected using the mask option (in units of 4 pins)
6
MB89150/150A Series
(Top view)
P41/SEG21*4
P42/SEG22*4
P43/SEG23*4
P44/SEG24*4
P45/SEG25*4
P46/SEG26*4
P47/SEG27*4
P50/SEG28*4
P51/SEG29*4
P52/SEG30*4
P53/SEG31*4
P54/SEG32*4
P55/SEG33*4
P56/SEG34*4
VSS
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG4
SEG3
SEG2
SEG1
SEG0
COM3
COM2
COM1
COM0
V CC
V3
V2
V1
V0
P32*2/C0*1
P31*2/C1*1
P30/RCO
X1A
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P57/SEG35*4
X1
X0
MOD1
MOD0
RST
X0A
P27/BUZ*3
P26*3
P00/INT20
P01/INT21
P02/INT22
P25/SCK
P24/SO
P23/SI
(FPT-80P-M06)
*1: For products with a booster circuit
*2: For products without a booster circuit
*3: N-ch open-drain high-current drive type
*4: Selected using the mask option (in units of 4 pins)
7
MB89150/150A Series
(Top view)
P41/SEG21*2
P42/SEG22*2
P43/SEG23*2
P44/SEG24*2
P45/SEG25*2
P46/SEG26*2
P47/SEG27*2
P50/SEG28*2
P51/SEG29*2
P52/SEG30*2
P53/SEG31*2
P54/SEG32*2
P55/SEG33*2
P56/SEG34*2
VSS
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG4
SEG3
SEG2
SEG1
SEG0
COM3
COM2
COM1
COM0
VCC
V3
V2
V1
V0
P32
P31
P30/RCO
X1A
X0A
101
102
103
104
105
106
107
108
109
93
92
91
90
89
88
87
86
85
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P57/SEG35*2
X1
X0
MOD1
MOD0
RST
P27/BUZ*1
P26*1
P25/SCK
P24/SO
P23/SI
P00/INT20
P01/INT21
P02/INT22
(MQP-80C-P01)
*1: N-ch open-drain high-current drive type
*2: Selected using the mask option (in units of 4 pins).
• Pin assignment on package top
Pin no.
81
Pin name
N.C.
VPP
Pin no.
89
Pin name
A2
Pin no.
97
Pin name
N.C.
O4
Pin no.
Pin name
OE
105
106
107
108
109
110
111
112
82
90
A1
98
N.C.
A11
A9
83
A12
A7
91
A0
99
O5
84
92
N.C.
O1
100
101
102
103
104
O6
85
A6
93
O7
A8
86
A5
94
O2
O8
A13
A14
VCC
87
A4
95
O3
CE
88
A3
96
VSS
A10
N.C.: Internally connected. Do not use.
8
MB89150/150A Series
■ PIN DESCRIPTION
Pin no.
Circuit
type
Pin name
Function
MQFP*4
LQFP*1*3
QFP*2
16
15
18
17
19
18
17
20
19
21
X0
X1
A
C
D
Main clock oscillator pins
MOD0
MOD1
RST
Operating mode selection pins
Connect directly to VSS.
Reset I/O pin
This pin is an N-ch open-drain output type with a pull-
up resistor and a hysteresis input type. “L” is output
from this pin by an internal reset source. The internal
circuit is initialized by the input of “L”.
20 to 27
28 to 31
22 to 29
30 to 33
P00/INT20 to
P07/INT27
E
E
General-purpose I/O ports
Also serve as an external interrupt 2 input (wake-up
function).
External interrupt 2 input is hysteresis input.
P10/INT10 to
P13/INT13
General-purpose I/O ports
Also serve as external interrupt 1 input.
External interrupt 1 input is hysteresis input.
32 to 35
36
34 to 37
38
P14 to P17
P20/EC
F
General-purpose I/O ports
H
N-ch open-drain general-purpose I/O port
Also serves as the external clock input for the timer.
The peripheral is a hysteresis input type.
37
38
39
40
P21
I
I
N-ch open-drain general-purpose I/O port
P22/TO
N-ch open-drain general-purpose I/O port
Also serves as a timer output.
39
41
P23/SI
H
N-ch open-drain general-purpose I/O port
Also serves as the data input for the 8-bit serial I/O.
The peripheral is a hysteresis input type.
40
41
42
43
P24/SO
I
N-ch open-drain general-purpose I/O port
Also serves as the data output for the 8-bit serial I/O.
P25/SCK
H
N-ch open-drain general-purpose I/O port
Also serves as the clock I/O for the 8-bit serial I/O.
The peripheral is a hysteresis input type.
42
43
44
45
P26
I
I
N-ch open-drain general-purpose I/O port
P27/BUZ
N-ch open-drain general-purpose I/O port
Also serves as a buzzer output.
(Continued)
*1: FPT-80P-M11
*2: FPT-80P-M06
*3: FPT-80P-M05
*4: MQP-80C-P01
9
MB89150/150A Series
(Continued)
Pin no.
Circuit
type
Pin name
Function
MQFP*4
QFP*2
LQFP*1*3
48
50
49
48
P32
C0
J
Functions as an N-ch open-drain general-purpose
output port only in the products without a booster.
—
J
Functions as a capacitor connection pin in the
products with a booster.
47
46
P31
C1
Functions as an N-ch open-drain general-purpose
output port only in the products without a booster.
—
G
Functions as a capacitor connection pin in the
products with a booster.
P30/RCO
General-purpose output-only port
Also serves as a remote control transmission output.
14
16
P57/SEG35
J/K
N-ch open-drain general-purpose output ports
Also serve as LCD controller/driver segment output.
Switching between port and common output is done by
the mask option.
12 to 6
14 to 8
P56/SEG34 to
P50/SEG28
5 to 1
7 to 3
P47/SEG27 to
P43/SEG23
J/K
80,
79,
78
2,
1,
80
P42/SEG22,
P41/SEG21,
P40/SEG20
77 to 58
79 to 60 SEG19 to
SEG0
K
LCD controller/driver segment output-only pins
57 to 54
52 to 49
44
59 to 56 COM3 to COM0
54 to 51 V3 to V0
K
—
B
LCD controller/driver common output-only pins
LCD driving power supply pins
46
47
55
15
X0A
X1A
VCC
Subclock crystal oscillator pins (32.768 kHz)
45
53
—
—
Power supply pin
13
VSS
Power supply (GND) pin
*1: FPT-80P-M11
*2: FPT-80P-M06
*3: FPT-80P-M05
*4: MQP-80C-P01
10
MB89150/150A Series
• External EPROM pins (MB89PV150 only)
Pin no.
Pin name
VPP
I/O
O
Function
82
“H” level output pin
Address output pins
83
84
85
86
87
88
89
90
91
A12
A7
A6
A5
A4
A3
A2
A1
A0
O
93
94
95
O1
O2
O3
I
Data input pins
96
VSS
O
I
Power supply (GND) pin
Data input pins
98
99
100
101
102
O4
O5
O6
O7
O8
103
CE
O
ROM chip enable pin
Outputs “H” during standby.
104
105
A10
OE
O
O
Address output pin
ROM output enable pin
Outputs “L” at all times.
107
108
109
A11
A9
A8
O
Address output pins
110
111
112
A13
A14
VCC
O
O
O
EPROM power supply pin
81
92
N.C.
—
Internally connected pins
Be sure to leave them open.
97
106
11
MB89150/150A Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
Crystal or ceramic oscillation type (main clock)
• At an oscillation feedback resistor of approximately
1 MΩ/5.0 V
X1
X0
Standby control signal
CR oscillation type (main clock)
(except MB89PV150/P155)
X1
X0
Standby control signal
B
Crystal oscillation type (subclock)
• At an oscillation feedback resistor of approximately
4.5 MΩ/3.0 V
X1A
X0A
Standby control signal
C
D
• At output pull-up resistor (P-ch) of approximately
50 kΩ/5.0 V
R
• Hysteresis input
P-ch
N-ch
E
• CMOS I/O
• The peripheral is a hysteresis input type.
R
P-ch
P-ch
N-ch
Port
• Pull-up resistor optional (except MB89PV150)
Peripheral
(Continued)
12
MB89150/150A Series
(Continued)
Type
Circuit
Remarks
F
• CMOS I/O
R
P-ch
P-ch
N-ch
• Pull-up resistor optional (except MB89PV150)
G
H
• CMOS output
• P-ch output is a high-current drive type.
P-ch
N-ch
• N-ch open-drain I/O
• CMOS input
R
P-ch
• The peripheral is a hysteresis input type.
N-ch
Port
Peripheral
• Pull-up resistor optional (except MB89PV150/P155)
I
• N-ch open-drain I/O
• CMOS input
R
P-ch
• P21, P26, and P27 are a high-current drive type.
N-ch
• Pull-up resistor optional (except MB89PV150/P155)
• N-ch open-drain output
J
R
P-ch
• Pull-up resistor optional (except MB89PV150/P155)
• P31 and P32 are not provided with a pull-up resistor.
N-ch
K
• LCD controller/driver segment output
P-ch
N-ch
P-ch
N-ch
13
MB89150/150A Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
wake-up from stop mode.
14
MB89150/150A Series
■ PROGRAMMING TO THE EPROM ON THE MB89P155
The MB89P155 is an OTPROM version of the MB89150/A series.
1. Features
• 16-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in the EPROM mode is diagrammed below.
EPROM mode
Address
Normal operating mode
(Corresponding addresses on the EPROM programmer)
0000H
0080H
0000H
I/O
RAM
Vacancy
0180H
(Read value FFH)
Not available
Not available
3FF0H
8000H
Option area
3FF6H
Vacancy
(Read value FFH)
C000H
4000H
Program area
(EPROM)
PROM
7FFFH
FFFFH
15
MB89150/150A Series
3. Programming to the EPROM
In EPROM mode, the MB89P155 functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to FFFFH
while operating as a normal operating mode assign to 4000H to 7FFFH in EPROM mode).
Load option data into addresses 3FF0H to 3FF5H of the EPROM programmer. (For information about each
corresponding option, see “7. Setting OTPROM Options.”)
(3) Program with the EPROM programmer.
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Package
Compatible socket adapter
ROM-80SQF-28DP-8L
FPT-80P-M05
FPT-80P-M06
FPT-80P-M11
ROM-80QF-28DP-8L3
ROM-80QF2-28DP-8L2
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
16
MB89150/150A Series
7. Setting OTPROM Options
The programming procedure is the same as that for the PROM. Options can be set by programming values at
the addresses shown on the memory map. The relationship between bits and options is shown on the following
bit map:
• OTPROM option bit map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Oscillation stabilization time
Vacancy
Vacancy
Vacancy
Reset pin
output
1: Yes
Clock mode Power-on
selection
reset
1: Yes
0: No
WTM1
WTM0
3FF0H
3FF1H
3FF2H
3FF3H
3FF4H
3FF5H
1: Dual clock
0: Single clock
Readable
Readable
Readable
See section “■ Mask
Options.”
0: No
P07
P06
P05
P04
P03
P02
P01
P00
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
P17
P16
P15
P14
P13
P12
P11
P10
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Notes: • Set each bit to 1 to erase.
• Do not write 0 to the vacant bit.
The read value of the vacant bit is 1, unless 0 is written to it.
17
MB89150/150A Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
LCC-32(Rectangle) ROM-32LC-28DP-YG
LCC-32(Square) ROM-32LC-28DP-S
Adapter socket part number
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in each mode is diagrammed below.
Address
Normal operating mode
Corresponding addresses on the EPROM programmer
0000H
0000H
0080H
I/O
RAM
0280H
Not available
8000H
EPROM
32 KB
PROM
32 KB
7FFFH
FFFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 4000H to 7FFFH.
(3) Program to 0000H to 7FFFH with the EPROM programmer.
18
MB89150/150A Series
■ BLOCK DIAGRAM
Main clock
oscillator
21-bit time-base
timer
X0
X1
Clock controller
8-bit timer/counter
P22/TO
Subclock oscillator
(32.768 kHz)
X0A
X1A
8-bit timer/counter
8-bit serial I/O
P20/EC
Reset circuit
(WDT)
RST
P25/SCK
P24/SO
P23/SI
8
8
4
External interrupt 2
(wake-up function)
P00/INT20
to P07/INT27
P27/BUZ*4
Buzzer output
CMOS I/O port
2
4
P21*4,P26*4
N-ch open-drain I/O port
4
External interrupt 1
(wake-up function)
P10/INT10
to P13/INT13
P54/SEG32*3
to P57/SEG35*3
N-ch open-drain output port
16
4
4
4
P50/SEG28*3
to P53/SEG31*3
P14 to P17
CMOS I/O port
P44/SEG24*3
to P47/SEG27*3
RAM
(Max. 256 × 8bits)
4
P40/SEG20*3
to P43/SEG23*3
LCD controller/
driver
F2MC-8L
CPU
20
4
SEG0 to SEG19
COM0 to COM3
V0 to V3
ROM
4
(Max. 16 K × 8 bits)
36 × 4 bits
VRAM
P32/C0*2
P31/C1*2
Reference voltage
generator and
booster*1
Other pins
MOD0, MOD1, VCC, VSS
Remote control
output
P30/RCO
N-ch open-drain output port
(Only P30 is a CMOS output type.)
*1: Selected by mask option
*2: Used as ports without a reference voltage generator and booster
*3: Functions selected by mask option
*4: N-ch open-drain high-current drive type
19
MB89150/150A Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89150/A series offer a memory space of 64 Kbytes for storing all of I/O, data,
and program areas. The I/O area is located at the lowest address. The data area is provided immediately above
the I/O area. The data area can be divided into register, stack, and direct areas according to the application.
The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables
of interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89150/A series is structured as illustrated below.
Memory Space
MB89155/A
MB89P155
MB89PV150
I/O
MB89151/A
MB89152/A
I/O
MB89153/A
I/O
MB89154/A
I/O
0000
H
H
0000
H
H
0000
H
H
0000
H
0000
H
H
0000
H
H
I/O
I/O
0080
0080
0080
0080
H
H
0080
0080
Not available
00C0
RAM
512 B
RAM
RAM
256 B
RAM
128 B
RAM
256 B
RAM
256 B
256 B
0100
H
H
0100
H
H
0100
H
H
0100
H
H
0100
H
H
0100
H
H
Register
Register
Register
Register
Register
Register
0140
0180
0180
0180
0180
0200
0280
H
H
Not available
Not available
Not available
Not available
Not available
Not available
8000
External
ROM
C000
H
32 KB
D000
H
E000
H
H
ROM
16 KB
ROM
12 KB
E800
H
H
ROM
8 KB
F000
H
H
ROM
6 KB
ROM
4 KB
FFFF
H
FFFF
H
FFFF
H
FFFF
FFFF
FFFF
20
MB89150/150A Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
Accumulator (A):
A 16-bit register for indicating instruction storage positions
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator
Whenthe instructionisan8-bitdataprocessinginstruction,thelowerbyteisused.
Index register (IX):
Extra pointer (EP):
Stack pointer (SP):
Program status (PS):
A 16-bit register for index modification
A 16-bit pointer for indicating a memory address
A 16-bit register for indicating a stack area
A 16-bit register for storing a register pointer, a condition code
16 bits
PC
Initial value
FFFDH
: Program counter
: Accumulator
A
T
Undefined
Undefined
Undefined
Undefined
Undefined
: Temporary accumulator
: Index register
IX
EP
SP
PS
: Extra pointer
: Stack pointer
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
14
13
12
11
10
9
8
7
6
I
5
4
3
2
Z
1
0
PS
RP
Vacancy Vacancy Vacancy
H
IL1, 0
N
V
C
RP
CCR
21
MB89150/150A Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
Lower OP codes
RP
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
0
IL0
0
Interrupt level
High-low
High
1
0
1
1
0
2
3
1
1
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
22
MB89150/150A Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers. Up to a total of 8 banks can be used on the MB89151 (RAM 128 × 8 bits), and a total of 16 banks
can be used on the MB89152/3/4/5 (RAM 256 × 8 bits). The bank currently in use is indicated by the register
bank pointer (RP).
Note: The number of register banks that can be used varies with the RAM size.
Register Bank Configuration
This address = 0100H + 8 × (RP)
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
8 banks (MB89151)
16 banks (MB89152/3/4/5)
Memory area
23
MB89150/150A Series
■ I/O MAP
Address
00H
Read/write
(R/W)
(W)
Register name
PDR0
Register description
Port 0 data register
01H
DDR0
Port 0 data direction register
Port 1 data register
Port 1 data direction register
Port 2 data register
Port 2 data direction register
Vacancy
02H
(R/W)
(W)
PDR1
03H
DDR1
04H
(R/W)
(W)
PDR2
05H
DDR2
06H
07H
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
SYCC
STBC
WDTC
TBTC
WPCR
PDR3
System clock control register
Standby control register
Watchdog timer control register
Time-base timer control register
Watch prescaler control register
Port 3 data register
Vacancy
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
(R/W)
(R/W)
(R/W)
PDR4
PDR5
BZCR
Port 4 data register
Port 5 data register
Buzzer register
10H
11H
Vacancy
12H
Vacancy
13H
Vacancy
14H
(R/W)
(R/W)
RCR1
RCR2
Remote control transmission register 1
Remote control transmission register 2
Vacancy
15H
16H
17H
Vacancy
18H
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
T2CR
T1CR
T2DR
T1DR
SMR1
SDR1
Timer 2 control register
Timer 1 control register
Timer 2 data register
Timer 1 data register
Serial mode register
Serial data register
Vacancy
19H
1AH
1BH
1CH
1DH
1EH to 2FH
(Continued)
24
MB89150/150A Series
(Continued)
Address
Read/write
(R/W)
Register name
EIE1
Register description
External interrupt 1 enable register
External interrupt 1 flag register
External interrupt 2 enable register
External interrupt 2 flag register
Vacancy
30H
31H
(R/W)
EIF1
32H
(R/W)
EIE2
33H
(R/W)
EIF2
34H to 5FH
60H to 71H
72H
(R/W)
(R/W)
VRAM
LCR1
Display data RAM
LCD controller/driver control register 1
Vacancy
73H to 7BH
7CH
(W)
(W)
(W)
ILR1
ILR2
ILR3
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Vacancy
7DH
7EH
7FH
Note: Do not use vacancies.
25
MB89150/150A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
( VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
Power supply voltage
VCC
VSS – 0.3
VSS – 0.3
VSS + 7.0
V
V
V0 to V3 pins on the product
with booster
VSS + 7.0
VCC + 0.3
LCD power supply voltage
Input voltage
V0 to V3
V0 to V3 pins on the product
without booster
VSS – 0.3
VSS – 0.3
VSS – 0.3
V
V
V
VI1 must not exceed VSS +7.0 V.
All pins except P20 to P27
without a pull-up resistor
VI1
VI2
VCC + 0.3
VSS + 7.0
P20 to P27 without a pull-up
resistor
VO1 must not exceed VSS +7.0 V.
All pins except P20 to P27, P31,
P32, P40 to P47, P50 to P57
without a pull-up resistor
VO1
VSS – 0.3
VSS – 0.3
VCC + 0.3
VSS + 7.0
V
Output voltage
P20 to P27, P31, P32, P40 to
P47, and P50 to P57, without a
pull-up resistor
VO2
V
All pins except P21, P26, P27,
and power supply pins
IOL1
IOL2
—
—
10
20
mA
“L” level maximum output
current
mA P21, P26, and P27
Average value (operating
current × operating rate)
mA
IOLAV1
—
—
4
8
All pins except P21, P26, P27,
and power supply pins.
“L” level average output current
Average value (operating
mA current × operating rate)
P21, P26, and P27
IOLAV2
“L” level total maximum output
current
∑IOL
—
—
80
40
mA
“L” level total average output
current
Average value (operating
mA
∑IOLAV
current × operating rate)
All pins except P30 and power
supply pins
IOH1
IOH2
—
—
–5
mA
“H” level maximum output
current
–10
mA P30
(Continued)
26
MB89150/150A Series
(Continued)
(VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
Average value (operating
current × operating rate)
All pins except P30 and power
supply pins.
IOHAV1
—
–2
mA
“H” level average output current
“H” level total output current
Average value (operating
mA current × operating rate)
IOHAV2
—
–4
P30
∑IOH
—
—
–20
–10
mA
“H” level total average output
current
Average value (operating
mA
∑IOHAV
current × operating rate)
Power consumption
Operating temperature
Storage temperature
PD
—
300
+85
mW
°C
TA
–40
–55
Tstg
+150
°C
Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Func-
tional operation should be restricted to the conditions as detailed in the operational sections of this
data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
2. Recommended Operating Conditions
(VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
Normal operation assurance range
Single clock system of the mask
ROM product.
2.2*1
6.0
V
Normal operation assurance range
Dual-clock system of the mask ROM
product.
2.2*1
Power supply voltage
VCC
4.0
V
2.7*1
1.5
6.0
6.0
V
V
V
MB89P155/PV150
Retains the RAM state in stop mode
V0 to V3 pins
*2
LCD power supply voltage
V0 to V3
VIR
VSS
VCC
LCD reference power supply
input voltage
V1 pin on the products with a booster
Reference power external input
1.3
2.2
V
Operating temperature
TA
–40
+85
°C
*1: The minimum operating power supply voltage varies with the execution time (instruction cycle time) setting for
the operating frequency.
*2: The LCD power supply voltage range and optimum value vary depending on the characteristics of the liquid-
crystal display element.
27
MB89150/150A Series
6
5
Operation assurance range
4
3
2
1
1
2
3
4
5
Main clock operating frequency (at an instruction cycle of 4/Fc) (MHz)
4.0
2.0
1.0
0.8
Minimum execution time (instruction cycle) (µs)
Note: The shaded area is assured only for the MB89151/A, 152/A, 153/A, 154/A,
and MB89155/A.
Figure 1 Operating Voltage vs. Main Clock Operating Frequency (MB89P155/PV150, and single-clock
MB89151/A, 152/A, 153/A, 154/A, and MB89155/A)
6
5
4
Operation assurance range
3
2
1
1
2
3
4
5
Main clock operating frequency (at an instruction cycle of 4/Fc) (MHz)
4.0
2.0
1.0
0.8
Minimum execution time (instruction cycle) (µs)
Figure 2 Operating Voltage vs. Main Clock Operating Frequency (Dual-clock MB89151/A, 152/A, 153/A,
154/A, and MB89155/A)
Figures 1 and 2 indicate the operating frequency of the external oscillator at a minimum execution time of 4/FCH.
Since the operating voltage range is dependent on the minimum execution time, see the minimum execution time
if the operating speed is switched using a gear.
28
MB89150/150A Series
3. DC Characteristics
(VCC = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Unit
Parameter
Pin
Condition
Remarks
Min.
Typ.
Max.
P00 to P07,
P10 to P17,
P20 to P27
VCC + 0.3
VIH
0.7 VCC
V
CMOS input
“H” level input
voltage
RST, MOD0, MOD1,
EC, SI, SCK,
INT10 to INT13,
INT20 to INT27
Hysteresis
input
VSS + 0.3
0.3 VCC
0.2 VCC
VIHS
0.8 VCC
VSS − 0.3
VSS − 0.3
V
V
V
P00 to P07, P10 to P17,
P20 to P27
VIL
—
CMOS input
“L” level input
voltage
RST, MOD0, MOD1,
EC, SI, SCK,
INT10 to INT13,
INT20 to INT27
Hysteresis
input
VILS
Open-drain output
pin application
voltage
P20 to P27, P31, P32,
P40 to P47, P50 to P57
Without
pull-up resistor
VD
VSS − 0.3
VSS + 6.0*1
V
P00 to P07, P10 to P17
P30
VOH1
VOH2
IOH = –2.0 mA
IOH = –6.0 mA
2.4
4.0
V
V
“H” level output
voltage
—
—
P00 to P07, P10 to P17,
P20, P22 to P25,
P30 to P32, P40 to P47,
P50 to P57
VOL1
IOL = 1.8 mA
—
0.4
V
“L” level output
voltage
VOL2
VOL3
P21, P26, P27
RST
IOL = 8.0 mA
IOL = 4.0 mA
—
—
—
—
0.4
0.4
V
V
MOD0, MOD1, P30,
P00 to P07, P10 to P17
Without
pull-up resistor
ILI1
0.0 V < VI < VCC
0.0 V < VI < 6.0 V
—
—
±5
±1
µA
µA
Input leakage current
(Hi-z output
leakage current)
P20 to P27, P31, P32,
P40 to P47, P50 to P57
Without
pull-up resistor
ILI2
—
P00 to P07, P10 to P17,
P20 to P27, P40 to P47,
P50 to P57, RST
With
pull-up resistor
Pull-up resistance RPULL
Common output
VI = 0.0 V
25
50
100
kΩ
RVCOM COM0 to COM3
RVSEG SEG0 to SEG35
V1 to V3 = 5.0 V
V1 to V3 = 5.0 V
—
—
—
—
2.5
15
kΩ
kΩ
impedance
Segment output
impedance
Products
kΩ without a
booster only
LCD divided
resistance
Between
VCC and V0
RLCD
—
300
—
500
—
750
V0 to V3,
COM0 to COM3,
SEG0 to SEG35
LCD leakage
current
ILCDL
—
±1
µA
(Continued)
29
MB89150/150A Series
(VCC = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Unit
Parameter
Pin
Condition
Remarks
Min.
4.3
Typ.
4.5
Max.
4.7
VOV3
VOV2
V3
V2
V
V
Booster for LCD
driving output voltage
V1 = 1.5 V
2.9
3.0
3.1
Products with
a booster only
Reference output
voltage for LCD
driving
VOV1
V1
IIN = 0 µA
1.3
1.5
1.7
V
MB89151/A,
152/A, 153/A,
FCH = 4.2 MHz,
VCC = 5.0 V
tinst*3 = 0.95 µs
Main clock
—
—
—
—
—
—
—
3.0
3.8
4.5
6.0
0.4
1.4
0.1
1.1
1.2
mA 154/A, 155/A,
MB89PV150-
101 to 105
ICC1
operation
MB89P155-101
mA
to 105/201 to 205
MB89151/A,
152/A,153/A,
mA 154/A, 155/A,
MB89PV150-
101 to 105
FCH = 4.2 MHz,
VCC = 3.0 V
tinst*3 = 15.2 µs
Main clock
0.25
0.85
0.05
0.65
0.8
ICC2
operation
MB89P155-101
mA
to 105/201 to 205
MB89151/A,
152/A, 153/A,
mA 154/A, 155/A,
MB89PV150-
101 to 105
FCL = 32.768 kHz,
VCC = 3.0 V
tinst*3 = 61 µs
Subclock
Power supply
current*2
ICCL
VCC
operation
MB89P155-101
mA
to 105/201 to 205
FCH = 4.2 MHz,
VCC = 5.0 V
tinst*3 = 0.95 µs
Main clock
ICCS1
ICCS2
ICCSL
mA
mA
sleep mode
FCH = 4.2 MHz,
VCC = 3.0 V
tinst*3 = 15.2 µs
Main clock
—
—
0.2
25
0.3
50
sleep mode
FCL = 32.768 kHz,
VCC = 3.0 V
tinst*3 = 61 µs
Subclock
µA
sleep mode
(Continued)
30
MB89150/150A Series
(Continued)
(VCC = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Unit
Parameter
Pin
Condition
Remarks
Min.
Typ.
Max.
MB89151/2/3/4/5,
MB89P155-101
to 105,
MB89PV150-101
to 105
FCL = 32.768 kHz,
VCC = 3.0 V
Watch mode
ICCT
—
10
15
µA
FCL = 32.768 kHz,
VCC = 3.0 V
• Watch mode
• During
reference
voltage
MB89151A/2A/
3A/4A/5A,
MB89P155-201
to 205
Power supply
current*2
ICCT2
—
250
400
µA
VCC
generator
and booster
operation
MB89151/2/3/4/5
—
—
—
0.1
0.1
10
1
µA
µA
pF
TA = +25°C,
VCC = 5.0 V
Stop mode
MB89PV150-101
to 105,
MB89P155-101
to 105
ICCH
10
Input capacitance CIN
Other than VCC, VSS f = 1 MHz
*1: P31 and P32 are applicable only for products of the MB89150 series (without the “A” suffix). P40 to P47 and
P50 to P57 are applicable when selected as ports.
*2: The power supply current is measured at the external clock, open output pins, and the external LCD dividing
resistor (or external input for the reference voltage).
In the case of the MB89PV150, the current consumed by the connected EPROM and ICE is not included.
*3: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
Note: For pins which serves as the segment (SEG20 to SEG35) and ports (P40 to P47, P50 to P57), see the port
parameter when these pins are used as ports and the segment parameter when they are used as segments.
P31 and P32 are applicable only for products without a booster (applicable as external capacitor connection
pins for products with a booster).
31
MB89150/150A Series
4. AC Characteristics
(1) Reset Timing
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Condition
Unit
Remarks
Parameter
Min.
48 tHCYL
Max.
RST “L” pulse width
tZLZH
—
—
ns
t
ZLZH
RST
0.2 VCC
(2) Power-on Reset
Parameter
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Min. Max.
Symbol Condition
Unit
Remarks
Power supply rising time
Power supply cut-off time
tR
—
1
50
—
ms
ms
Power-on reset function only
Due to repeated operations
—
tOFF
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is
recommended.
t
OFF
t
R
2.0 V
0.2 V
0.2 V
0.2 V
V
CC
32
MB89150/150A Series
(3) Clock Timing
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Unit
Remarks
Parameter
Clock frequency
Clock cycle time
Min.
1
Typ.
—
Max.
4.2
FCH
X0, X1
MHz Main clock
kHz Subclock
FCL
X0A, X1A
X0, X1
—
32.768
—
—
tHCYL
tLCYL
238
—
1000
—
ns
Main clock
Subclock
X0A, X1A
30.5
µs
PWH
PWL
X0
20
—
—
—
15.2
—
—
—
10
ns
µs
ns
Input clock pulse width
PWHL
PWLL
X0A
External clock
Input clock pulse
rising/falling time
tCR
tCF
X0, X0A
X0 and X1 Timing and Conditions
tHCYL
0.8 VCC
0.2 VCC
X0
PWL
PWH
tCF
tCR
Main Clock Conditions
When a crystal
or
When an external clock
is used
When the CR oscillation
option is used
ceramic resonator is used
X 0
X 1
X 0
X 1
X 0
X 1
FCH
Open
FCH
FCH
R
C1
C2
C
33
MB89150/150A Series
X0A and X1A Timing and Conditions
t
LCYL
0.8 VCC
0.2 VCC
X0A
PWLL
PWHL
t
CF
t
CR
Subclock Conditions
When a crystal
or
When an external clock
is used
When the single clock
option is used
ceramic resonator is used
X0A
X1A
X0A
X1A
X0A
X1A
R
F
CL
Open
Open
F
CL
C1
C2
(4) Instruction Cycle
Parameter
Symbol
Value
Unit
Remarks
(4/FCH) tinst = 0.95 µs when operating
at FCH = 4.2 MHz
4/FCH, 8/FCH, 16/FCH, 64/FCH µs
2/FCL µs
Instruction cycle
(minimum execution time)
tinst
tinst = 61.036 µs when operating at
FCL = 32.768 kHz
34
MB89150/150A Series
(5) Serial I/O Timing
Parameter
(VCC = +5.0 V±10%, VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
SCK
Condition
Unit Remarks
Min.
2 tinst*
–200
Max.
—
Serial clock cycle time
SCK ↓ → SO time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
µs
ns
µs
µs
µs
µs
ns
µs
µs
SCK, SO
SI, SCK
SCK, SI
SCK
200
—
Internal shift
clock mode
Valid SI → SCK ↑
0.5 tinst*
0.5 tinst*
1 tinst*
1 tinst*
0
SCK ↑ → valid SI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↓ → SO time
—
—
SCK
—
External shift
clock mode
SCK, SO
SI, SCK
SCK, SI
200
—
Valid SI → SCK ↑
0.5 tinst*
0.5 tinst*
SCK ↑ → valid SI hold time
—
* : For information on tinst, see “(4) Instruction Cycle.”
Internal Shift Clock Mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SO
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
SI
0.2 VCC
External Shift Clock Mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
SCK
0.2 VCC
0.2 VCC
tSLOV
2.4 V
SO
SI
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
35
MB89150/150A Series
(6) Peripheral Input Timing
(VCC = +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Unit Remarks
Parameter
Min.
1 tinst*
1 tinst*
2 tinst*
2 tinst*
Max.
—
Peripheral input “H” pulse width 1
Peripheral input “L” pulse width 1
Peripheral input “H” pulse width 2
Peripheral input “L” pulse width 2
tILIH1
tIHIL1
tILIH2
tIHIL2
µs
µs
µs
µs
INT10 to INT13, EC
INT20 to INT27
—
—
—
* : For information on tinst, see “(4) Instruction Cycle.”
t
IHIL1
t
ILIH1
INT10 to 13,
EC
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
t
IHIL2
t
ILIH2
INT20 to 27
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
36
MB89150/150A Series
■ EXAMPLE CHARACTERISTICS
(1) “L” Level Output Voltage
VOL1 vs. IOL
V
OL2 vs. IOL
= 2.5 V
V
OL1 (V)
0.6
V
OL2 (V)
V
CC = 2.0 V
VCC = 2.5 V VCC = 3.0 V
V
CC = 2.0 V CC
V
V
CC = 3.0 V
1.0
V
CC = 4.0 V
T = +25°C
A
T = +25°C
A
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
V
CC = 5.0 V
CC = 6.0 V
VCC = 4.0 V
V
V
CC = 5.0 V
CC = 6.0 V
V
0
0
1
2
3
4
5
6
7
8
9
10
OL (mA)
0
2
4
6
8
10 12 14 16 18 20
I
IOL (mA)
(2) “H” Level Output Voltage
VCC
–
VOH2 vs. IOH
CC = 2.5 V
VCC – VOH1 vs. IOH
CC = 2.5 V
C1C.0
V
– VOH2 (V)
V
CC – VOH1 (V)
V
VCC = 3.0 V
V
CC = 2.0 V
VCC = 3.0 V
VCC = 2.0 V
V
1.0
TA = +25°C
T
A
= +25°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
CC = 4.0 V
V
CC = 4.0 V
V
V
CC = 5.0 V
CC = 6.0 V
V
V
CC = 5.0 V
CC = 6.0 V
0
–1 –2 –3 –4 –5 –6 –7 –8 –9 –10
0
–1
–2
–3
–4
–5
IOH (mA)
IOH (mA)
(Continued)
37
MB89150/150A Series
(3) “H” Level Input Voltage/“L” level Input Voltage
(CMOS input)
(Hysteresis input)
VIN vs. VCC
V IN (V)
5.0
VIN vs. VCC
V IN (V)
5.0
TA = +25°C
TA = +25°C
4.5
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
VIHS
VILS
1
2
3
4
5
6
7
1
2
3
4
5
6
7
VCC (V)
VCC (V)
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
(4) Power Supply Current (External Clock)
I
ICC1 (mA)
5.0
CC1 vs. VCC (Mask ROM product)
I
CC2 vs. VCC (Mask ROM product)
ICC2 (mA)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
TA = +25°C
TA = +25°C
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
FCH = 4.2 MHz
FCH = 4.2 MHz
FCH = 3 MHz
FCH = 3 MHz
FCH = 1 MHz
FCH = 1 MHz
1
2
3
4
5
6
7
1
2
3
4
5
6
7
VCC (V)
VCC (V)
(Continued)
38
MB89150/150A Series
I
CCS1 vs. VCC
I
CCS2 vs. VCC
ICCS1 (mA)
I
CCS2 (mA)
1.2
1.0
T
A
= +25°C
T
A
= +25°C
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
F
F
CH = 4.2 MHz
CH = 3 MHz
F
F
F
CH = 4.2 MHz
CH = 3 MHz
CH = 1 MHz
F
CH = 1 MHz
0.1
0
0.1
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
V
CC (V)
VCC (V)
ICCL vs. VCC (Mask ROM product)
I
CCT vs. VCC
ICCT (µA)
ICCL (µA)
200
30
25
20
15
10
TA = +25°C
T
A
= +25°C
180
160
140
120
100
80
F
CL = 32.768 kHz
FCL = 32.768 kHz
60
40
5
0
20
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
VCC (V)
VCC (V)
(Continued)
39
MB89150/150A Series
(Continued)
I
CCSL vs. VCC
I
CCT2 vs. VCC
I
CCSL (µA)
I
CCT2 (µA)
200
T
180
1,000
T
A
= +25°C
A
= +25°C
900
800
700
600
500
400
300
200
160
140
120
100
80
F
CL = 32.768 kHz
F
CL = 32.768 kHz
60
40
20
100
0
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
V
CC (V)
VCC (V)
(5) Pull-up Resistance
R
PULL (kΩ)
1,000
500
100
50
TA = +85°C
A = +25°C
T
TA = –40°C
10
1
2
3
4
5
6
7
VCC (V)
40
MB89150/150A Series
■ INSTRUCTIONS
Execution instructions can be divided into the following four groups:
• Transfer
• Arithmetic operation
• Branch
• Others
Table 1 lists symbols used for notation of instructions.
Table 1 Instruction Symbols
Symbol
dir
Meaning
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
Vector table number (3 bits)
Immediate data (8 bits)
Immediate data (16 bits)
Bit direct address (8:3 bits)
Branch relative address (8 bits)
#vct
#d8
#d16
dir: b
rel
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of accumulator A (8 bits)
AH
AL
Lower 8 bits of accumulator A (8 bits)
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the
instruction in use.)
T
TH
TL
IX
Upper 8 bits of temporary accumulator T (8 bits)
Lower 8 bits of temporary accumulator T (8 bits)
Index register IX (16 bits)
(Continued)
41
MB89150/150A Series
(Continued)
Symbol
Meaning
EP
PC
SP
PS
dr
Extra pointer EP (16 bits)
Program counter PC (16 bits)
Stack pointer SP (16 bits)
Program status PS (16 bits)
Accumulator A or index register IX (16 bits)
Condition code register CCR (8 bits)
Register bank pointer RP (5 bits)
CCR
RP
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
×
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
( × )
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic:
~:
Assembler notation of an instruction
Number of instructions
Number of bytes
#:
Operation:
TL, TH, AH:
Operation of an instruction
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction
is executed.
• 00 becomes 00.
N, Z, V, C:
OP code:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
42
MB89150/150A Series
Table 2 Transfer Instructions (48 instructions)
Mnemonic
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
~
#
Operation
TL
TH AH NZVC OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
45
46
61
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
(dir) ← (A)
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
47
48 to 4F
04
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
05
06
60
92
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
07
(A) ← ( (EP) )
08 to 0F
85
86
87
88 to 8F
D5
(A) ← (Ri)
(dir) ← d8
( (IX) +off ) ← d8
( (EP) ) ← d8
–
–
–
–
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
D6
–
–
–
–
dH
dH
dH
D4
D7
E3
E4
C5
C6
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
AL
AL
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
+ + + +
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
A8 to AF
A0 to A7
42
SETB dir: b
CLRB dir: b
XCH A,T
–
AH
–
–
–
43
F7
F6
F5
XCHW A,T
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
–
–
–
F0
–
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
43
MB89150/150A Series
Table 3 Arithmetic Operation Instructions (62 instructions)
Mnemonic
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
~
#
Operation
(A) ← (A) + (Ri) + C
TL
TH AH NZVC OP code
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + –
– – – –
– – – –
+ + – –
+ + + –
– – – –
– – – –
+ + – –
– – – –
– – – –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + – +
28 to 2F
24
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
25
26
–
–
dH
–
27
23
22
–
–
–
38 to 3F
34
35
–
–
36
37
dH
–
33
32
–
–
–
C8 to CF
C3
C2
dH
–
–
C0
D8 to DF
D3
–
D2
D0
01
11
63
73
53
12
dH
dH
00
dH
dH
dH
–
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) (T)
(A) ← (A) (T)
(A) ← (A) (T)
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
(TL) − (AL)
(T) − (A)
–
–
13
03
→
→
C
A
←
←
C
A
02
–
–
–
+ + – +
ROLC A
2
1
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
14
15
17
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
16
18 to 1F
84
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
94
52
54
55
57
56
DAS
XOR A
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
58 to 5F
62
64
65
AND A,#d8
AND A,dir
(A) ← (AL) (dir)
(Continued)
44
MB89150/150A Series
(Continued)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(dir) – d8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + + +
+ + + +
– – – –
– – – –
67
66
68 to 6F
72
74
75
77
76
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
78 to 7F
95
97
96
98 to 9F
C1
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
DECW SP
D1
Table 4 Branch Instructions (17 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V N = 1 then PC ← PC + rel
If V N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– + – –
– + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
Restore
FD
FC
F9
F8
FB
FA
FF
FE
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
BGE rel
B0 to B7
B8 to BF
E0
21
E8 to EF
31
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
F4
20
30
RETI
–
Table 5 Other Instructions (9 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – R
– – – S
– – – –
– – – –
40
50
41
51
00
81
91
80
90
CLRI
SETI
45
MB89150/150A Series
■ INSTRUCTION MAP
46
MB89150/150A Series
■ MASK OPTIONS
MB89151/1A, 2/2A,
3/3A, 4/4A, 5/5A
Part number
Specifying procedure
MB89P155
MB89PV150
No.
Specify when
ordering masking
Set with EPROM
programmer
Setting not
possible
Pull-up resistors
P00 to P07, P10 to P17
1
2
3
4
Selectable per pin
Can be set per pin
Selectable per pin
(Only when segment
output is not selected.)
Pull-up resistors
P40 to P47, P50 to P57
Fixed to without a
pull-up resistor
Fixed to without a
pull-up resistor
Pull-up resistors
Fixed to without a
pull-up resistor
Selectable by pin
Selectable
P20 to P27
Power-on reset
Fixed to with
With power-on reset
Selectable
power-on reset
Without power-on reset
Selectable
Selectable
Selection of oscillation stabilization time
• The initial value of the oscillation
stabilization time for the main clock can
be set by selecting the values of the
WTM1 and WTM0 bits on the right.
WTM1 WTM0
WTM1WTM0
Fixed to oscillation
stabilization time of
216/FCH
0
0
1
1
0:
1:
0:
1:
22/FCH
212/FCH
216/FCH
218/FCH
0
0
1
1
0:
1:
0:
1:
22/FCH
212/FCH
216/FCH
218/FCH
5
Main clock oscillation type
Crystal or ceramic resonator
CR
Fixed to crystal or
ceramic only
Fixed to crystal or
ceramic
6
7
8
Selectable
Selectable
Selectable
Selectable
Reset pin output
With reset output
Without reset output
Fixed to with reset
output
Selectable
Selectable
Clock mode selection
Dual-clock mode
Fixed to dual-clock
mode
Single-clock mode
Segment output selection
36: No ports selection
32: Selection of P57 to P54
28: Selection of P57 to P50
24: Selection of P57 to P50, and P47 to P44.
20: Selection of P57 to P50, and P47 to P40.
-101: 36 segments
-102: 32 segments
-101/201: 36 segments
-102/202: 32 segments
-103/203: 28 segments -103: 28 segments
-104/204: 24 segments
-105/205: 20 segments
Selection of the
number of
segments.
9
-104: 24 segments
-105: 20 segments
Without booster:
-101 to 105
With booster:
-201 to 205
Without booster:
MB89151/2/3/4/5
With booster:
Fixed to without
booster
(-100 to 105 only)
10 Selection of a built-in booster
MB89151A/2A/3A/4A/5A
47
MB89150/150A Series
• Versions
Version
Features
Mass production
product
One-time PROM
product
Number of
segment pins
Piggyback/evaluation
product
Booster
MB8915151A
152A
MB89P155-201
36
32
28
24
20
-202
-203
-204
-205
153A
154A
155A
—
Yes
MB8915151
152
MB89P155-101
MB89PV150-101
36
32
28
24
20
-102
-103
-104
-105
-102
-103
-104
-105
153
154
155
No
■ ORDERING INFORMATION
Part number
Package
Remarks
MB89151PF
MB89152PF
MB89153PF
MB89154PF
MB89155PF
Without booster
MB89P155PF-101
MB89P155PF-102
MB89P155PF-103
MB89P155PF-104
MB89P155PF-105
80-pin Plastic QFP
(FPT-80P-M06)
MB89151APF
MB89152APF
MB89153APF
MB89154APF
MB89155APF
With booster
MB89P155PF-201
MB89P155PF-202
MB89P155PF-203
MB89P155PF-204
MB89P155PF-205
(Continued)
48
MB89150/150A Series
(Continued)
Part number
Package
Remarks
MB89151PFM
MB89152PFM
MB89153PFM
MB89154PFM
MB89155PFM
Without booster
MB89P155PFM-101
MB89P155PFM-102
MB89P155PFM-103
MB89P155PFM-104
MB89P155PFM-105
80-pin Plastic LQFP
(FPT-80P-M11)
MB89151APFM
MB89152APFM
MB89153APFM
MB89154APFM
MB89155APFM
With booster
MB89P155PFM-201
MB89P155PFM-202
MB89P155PFM-203
MB89P155PFM-204
MB89P155PFM-205
MB89151PFV
MB89152PFV
MB89153PFV
MB89154PFV
MB89155PFV
Without booster
MB89P155PFV-101
MB89P155PFV-102
MB89P155PFV-103
MB89P155PFV-104
MB89P155PFV-105
80-pin Plastic LQFP
(FPT-80P-M05)
MB89151APFV
MB89152APFV
MB89153APFV
MB89154APFV
MB89155APFV
With booster
MB89P155PFV-201
MB89P155PFV-202
MB89P155PFV-203
MB89P155PFV-204
MB89P155PFV-205
MB89PV150CF-101
MB89PV150CF-102
MB89PV150CF-103
MB89PV150CF-104
MB89PV150CF-105
80-pin Ceramic MQFP
(MQP-80C-P01)
Without booster
49
MB89150/150A Series
■ PACKAGE DIMENSIONS
80-pin Plastic QFP
(FPT-80P-M06)
23.90±0.40(.941±.016)
3.35(.132)MAX
0.05(.002)MIN
(STAND OFF)
20.00±0.20(.787±.008)
64
41
65
40
12.00(.472)
REF
14.00±0.20 17.90±0.40
(.551±.008) (.705±.016)
16.30±0.40
(.642±.016)
INDEX
80
25
"A"
1
24
LEAD No.
0.80(.0315)TYP
0.35±0.10
(.014±.004)
0.15±0.05(.006±.002)
Details of "B" part
M
0.16(.006)
Details of "A" part
0.25(.010)
0.30(.012)
"B"
0.10(.004)
0
10°
0.18(.007)MAX
18.40(.724)REF
0.80±0.20
(.031±.008)
0.58(.023)MAX
22.30±0.40(.878±.016)
C
1994 FUJITSU LIMITED F80010S-3C-2
Dimensions in mm (inches)
80-pin Plastic LQFP
(FPT-80P-M11)
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
1.50−+00..2100
(Mounting height)
.059 −+..000048
60
61
41
40
15.00
(.591)
NOM
12.35
(.486)
REF
1 PIN INDEX
80
21
1
Details of "A" part
LEAD No.
"A"
0.10±0.10
(.004±.004)
0.127 +−00..0025
.005−+..000012
20
(STAND OFF)
0.65(.0256)TYP
0.30±0.10
(.012±.004)
M
0.13(.005)
0.50±0.20
(.020±.008)
0.10(.004)
0
10˚
Dimensions in mm (inches)
C
1995 FUJITSU LIMITED F80016S-1C-3
50
MB89150/150A Series
80-pin Plastic LQFP
(FPT-80P-M05)
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
1.50−+00..2100
(Mounting height)
.059 −+..000048
60
41
61
40
13.00
(.512)
NOM
9.50
(.374)
REF
INDEX
80
21
1
20
LEAD No.
Details of "A" part
"A"
0.50±0.08
(.0197±.0031)
0.18−+00..0038
.007 −+..000013
0.127 +−00..0025
.005−+..000012
0.10±0.10
(.004±.004)
(STAND OFF)
0.50±0.20(.020±.008)
0.10(.004)
0
10˚
C
Dimensions in mm (inches)
1995 FUJITSU LIMITED F80008S-2C-5
80-pin Ceramic MQFP
(MQP-80C-P01)
18.70(.736)TYP
12.00(.472)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
1.50(.059)TYP
1.00(.040)TYP
0.80±0.25
(.0315±.010)
INDEX AREA
1.20+–00..2400
4.50(.177)
TYP
0.80±0.25
(.0315±.010)
.047 +–..000186
1.27±0.13
(.050±.005)
INDEX AREA
18.12±0.20
(.713±.008)
22.30±0.33
(.878±.013)
12.02(.473)
TYP
18.40(.724)
REF
10.16(.400)
14.22(.560)
TYP
0.30(.012)
24.70(.972)
TYP
TYP
TYP
INDEX
6.00(.236)
TYP
0.40±0.10
(.016±.004)
1.27±0.13
(.050±.005)
0.30(.012)TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
0.40±0.10
(.016±.004)
1.20+–00..2400
.047 +–..000186
1.50(.059)
TYP
1.00(.040)
TYP
0.15±0.05 8.70(.343)
(.006±.002) MAX
C
1994 FUJITSU LIMITED M80001SC-4-2
Dimensions in mm (inches)
51
MB89150/150A Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: (044) 754-3763
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: (044) 754-3329
http://www.fujitsu.co.jp/
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9804
FUJITSU LIMITED Printed in Japan
相关型号:
MB89P165-203-PFS
Microcontroller, 8-Bit, OTPROM, F2MC-8L CPU, 4.2MHz, CMOS, PQFP80, PLASTIC, LQFP-80
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