MB89P955_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12529-1E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89950 Series

MB89951/953/P955/PV950

■ OUTLINE

The MB89950 series of single-chip compact microcontroller using the F²MC*-8L family core which can operate

at high-speeds and low voltages. They contain peripherals such as timers, UART, serial interfaces, external

interrupts and a 168-pixel LCD controller/driver. It is best suited for use in LCD panels.

*: F²MC stands for FUJITSU Flexible Microcontroller.

■ FEATURES

• Minimum instruction execution time: 0.8 µs at 5 MHz

• F²MC-8L family CPU core

Multiplication and division instructions

16-bit arithmetic operation

Instruction test and branch instruction

Bit manipulation instruction, etc.

Instruction system most suited to controllers

(Continued)

■ PACKAGE

64-pin Plastic QFP

64-pin Ceramic MQFP

(MQP-64C-P01)

(FPT-64P-M09)

MB89950 Series

(Continued)

• LCD controller/driver

Maximum 42 segment outputs x 4 common outputs

Build-in LCD driver split resistor

• Three-channel timer unit

8-bit PWM timer: (usable as both reload timer and PWM timer)

8-bit pulse width counter timer: (usable as both reload timer)

20-bit timebased counter

• Two serial interfaces

8-bit synchronous serial interface

UART (5, 7, and 8-bit transfers possible)

• External-interrupt input: 2 channels

2 channels can be used to clear the low-power consumption modes

An edge detection function is provided for each channel

• Low-power consumption modes

Stop mode (Oscillation stops to minimize the current consumption)

Sleep mode (CPU stops to reduce current consumption to about 30%)

• Package: QFP-64 (0.65mm pitch)

2

MB89950 Series

■ PRODUCT LINEUP

Part number

MB89951

MB89953

MB89P955

MB89PV950

Item

Classification

One-time

PROM

products

Piggyback/

evaluation and

development ptoduct

Mass-produced products

(Mask ROM product)

4 K × 8 bits

(internal mask ROM)

ROM size

8 K × 8 bits

16 K × 8 bits

32 K × 8 bits

(external ROM)

(internal mask ROM) (internal PROM, to be

programmed with

general-purpose

EPROM programmer)

RAM size

128 × 8 bits

256 × 8 bits

512 × 8 bits

1024 × 8 bits

CPU functions

The number of basic instructions:

Instruction bit length:

Instruction length:

136

8 bits

1 to 3 bytes

1, 8, 16 bits

Data bit length:

Minimum imstruction execution time: 0.8 µs at 5 MHz (V^CC=5.0 V)

Interrupt processing time:

7.2 µs at 5 MHz (VCC =5.0 V)

22 (also used as segment pin)*¹

4 (two of them are also used as LCD bias pins)

7 (6 used as peripheral)

Ports

I/O port (N-ch open-drain):

I/O port (CMOS):

Total:

33 (max.)

8-bit PWM

timer

8-bit reload timer operation (toggle output possible)

8-bit resolution PWM operation

Operation clock (pulse-width count timer output: 0.8 µs, 12.8 µs, 51.2 µs/5 MHz)

8-bit

pulse-width

counter timer

8-bit reload timer operation

8-bit pulse width measurement (continuous measurement, High- and Low-width measurement,

and one-cycle measurement)

Operation clock (0.8 µs, 3.2 ms, 25.6 µs/5 MHz)

8-bit serial I/O

UART

8-bit length, selectable from least significant bit (LSB) first or most significant bit (MSB) first,

transfer clock (external, 1.6 µs, 6.4 ms, 25.6 µs/5 MHz)

5-, 7-, 8-bit transfers possible, internal baud-rate generator (Max. 78125 bps/5 MHz)

LCD controller/

driver

Common output: 4

Segment output: 42 (max.)

Operation mode: 1/2 bias and 1/2 duty, 1/3 bias and 1/3 duty, 1/3 bias and 1/4 duty

LCD controller display RAM capacity: 42 × 4 bits

LCD driver split resistor: built-in (external resistor selectable)

External

interrupt

2 (edge selectable: one serving as pulse-width count timer input)

Sleep mode, stop mode

Standby mode

Power supply

voltage*²

2.2 V to 6.0 V

2.7 V to 6.0 V

MBM27C256A-20TV

(LCC package)

EPROM

—

*1: Mask Option.

*2: Varies with conditions such as the operating frequency. (See “■ Electrical Characteristics”.)

3

MB89950 Series

■ PACKAGE AND CORRESPONDING PRODUCTS

Package

MB89951

MB89953

MB89P955

MB89PV950

FPT-64P-M09

MQP-64C-P01

×

: Available

×: Not available

Note: For more information about each package, see section “■ Package Dimensions.”

4

MB89950 Series

■ PIN ASSIGNMENT

(Top view)

SEG4

SEG3

SEG2

SEG1

SEG0

COM3

COM2

COM1

COM0

V3

P33/V2

P32/V1

P31

P30

P40

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P00/SEG20

P01/SEG21

P02/SEG22

P03/SEG23

P04/SEG24

P05/SEG25

P06/SEG26

P07/SEG27

P10/SEG28

P11/SEG29

P12/SEG30

P13/SEG31

P14/SEG32

P15/SEG33

P16/SEG34

P17/SEG35

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

P41/PWM

(FPT-64P-M09)

5

MB89950 Series

(Top view)

SEG5

SEG4

SEG3

SEG2

SEG1

SEG0

COM3

COM2

COM1

COM0

V3

P33/V2

P32/V1

P31

P30

P40

1

2

3

4

5

6

7

8

SEG18

SEG19

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P00/SEG20

P01/SEG21

P02/SEG22

P03/SEG23

P04/SEG24

P05/SEG25

P06/SEG26

P07/SEG27

P10/SEG28

P11/SEG29

P12/SEG30

P13/SEG31

P14/SEG32

P15/SEG33

P16/SEG34

P17/SEG35

P20/SEG36

85

86

87

88

89

90

91

92

93

77

76

75

74

73

72

71

70

69

9

10

11

12

13

14

15

16

17

18

19

P41/PWM

P42/INT1/PWC

P43/SI

(MQP-64C-P01)

• Pin assignment on package top (MB89PV950 only)

Pin no.

65

Pin name

N.C.

VPP

Pin no.

73

Pin name

A2

Pin no.

81

Pin name

N.C.

O4

Pin no.

89

Pin name

OE

66

74

A1

82

90

N.C.

A11

A9

67

A12

A7

75

A0

83

O5

91

68

76

N.C.

O1

84

O6

92

69

A6

77

85

O7

93

A8

70

A5

78

O2

86

O8

94

A13

A14

VCC

71

A4

79

O3

87

CE

95

72

A3

80

V^SS

88

A10

96

N.C.:Internally connected. Do not use.

6

MB89950 Series

■ PIN DESCRIPTION

Pin no.

Circuit

type

Pin name

Function

QFP^*1

22

MQFP^*2

23

X0

X1

A

Clock oscillator pins

23

24

21

22

MODA

B

C

Operation-mode select pin

This pin is connected directly to V^SSwith pull down resistor.

19

20

RST

Reset I/O pin

This pin consists of an N-ch open-drain output with a pull-up

resistor and hysteresis input.

A Low level is put out from this pin.

A “LOW” voltage on this port generates a RESET condition

48 to 41 49 to 42 P00/SEG20

D

N-channel open-drain type general-purpose I/O ports

Also serve as LCDC controller segment outputs.

Switching between port output and segment output is

performed by the mask option every 8 bits.

to

P07/SEG27

40 to 33 41 to 34 P10/SEG28

N-channel open-drain type general-purpose I/O ports

Also serve as LCDC controller segment outputs.

Switching between port output and segment output is

performed by the mask option.

to

P17/SEG35

32 to 27 33 to 28 P20/SEG36

N-channel open-drain type general-purpose I/O ports

Also serve as LCDC controller segment outputs.

Switching between port output and segment output is

performed by the mask option.

to

P25/SEG41

14 to 11 15 to 12 P30 to P31

F

N-channel open-drain type general-purpose I/O ports

12 to 11 13 to 12 P32/V1 to

P33/V2

D

N-channel open-drain type general-purpose I/O ports

Also serve as LCDC controller power supply.

15

16

P40

E

General-purpose I/O port

A pull-up resistor option is provided.

16

17

P41/PWM

General-purpose I/O port

Serves as PWM timer toggle output (PWM).

A pull-up resistor option is provided.

17

18

P42/PWC/INT1

E

General-purpose I/O port

Also serves as pulse-width count timer input (PWC) and

external interrupt input (INT1)

The PWC and INT1 inputs are of a hysteresis type.

A pull-up resistor option is provided.

18

20

19

21

P43/SI

E

General-purpose I/O port

Also serves as serial I/O and UART data input (SI) The SI

input is of a hysteresis type.

A pull-up resistor option is provided.

P44/SO

General-purpose I/O port

Also serves as serial I/O and UART data output (SO).

A pull-up resistor option is provided.

(Continued)

*1: FPT-64P-M09

*2: MQP-64C-P01

7

MB89950 Series

(Continued)

Pin no.

Circuit

type

Pin name

Function

QFP^*1

MQFP^*2

25

26

P45/SCK

E

G

General-purpose I/O port

Also serves as serial I/O and UART clock input/output (SCK).

The SCK input is of a hysteresis type.

A pull-up resistor option is provided.

26

27

P46/INT0

General-purpose input port

Also serves as external-interrupt input (INT0).

The input is of a hysteresis type.

A pull-up resistor option is provided.

5 to 1,

6 to 1, SEG0 to SEG4,

64 to 57, 64 to 58, SEG5 to SEG12,

55 to 49 56 to 50 SEG13 to SEG19

For LCDC controller segment ouput

9 to 6

10

7 to 10 COM0 to COM3

G

—

For LCDC controller common output

For LCD driver power supply

Power supply Pin

11

57

25

V3

56

V^CC

V^SS

24

Power supply (GND) Pin

*1: FPT-64P-M09

*2: MQP-64C-P01

8

MB89950 Series

• External EPROM pins (MB89PV950 only)

Pin no.

Pin name

V^PP

I/O

O

Function

66

“H” level output pin

Address output pins

67

68

69

70

71

72

73

74

75

A12

A7

A6

A5

A4

A3

A2

A1

A0

O

77

78

79

O1

O2

O3

I

Data input pins

80

V^SS

O

I

Power supply (GND) pins

Data input pins

82

83

84

85

86

O4

O5

O6

O7

O8

87

CE

O

ROM chip enable pin

Outputs “H” during standby.

88

89

A10

OE

O

Address output pin

ROM output enable pin

Outputs “L” at all times.

91

92

93

94

95

A11

A9

A8

A13

A14

O

Address output pins

96

V^CC

O

EPROM power supply pin

65

76

81

90

N.C.

Internally connected pins

Be sure to leave them open.

—

9

MB89950 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• Crystal oscillator

• Feedback resistor: Approx. 1 MΩ/5.0 V (1 to 5 MHz)

X1

X0

N-ch

P-ch

N-ch

Standby control signal

B

C

• CMOS input

• Pull-down resistor (N-ch)

R

• Output pull-up resistor (P-ch): Approx. 50 kΩ (5.0 V)

• Hysteresis input

R

P-ch

N-ch

D

• N-ch open-drain output

• CMOS input

P-ch

N-ch

P-ch

N-ch

• The segment output is optional.

E

• CMOS output

• CMOS input

• Hysteresis input

(peripheral input)

R

P-ch

N-ch

• The pull-up resistor is optional.

(Continued)

10

MB89950 Series

(Continued)

Type

Circuit

Remarks

F

• N-ch open-drain output

• CMOS input

N-ch

G

• LCDC output

11

MB89950 Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, supply current increases rapidly and might thermally damage elements. When using, take

great care not to exceed the absolute maximum ratings.

Also, take care to prevent the analog power (AV^CCand AVR) and analog input from exceeding the digital power

supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pull-down

resistor.

3. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

4. Power Supply Voltage Fluctuations

Although operation is assured within the rated, rapid of VCC power supply voltage, a rapid fluctuation of the

voltage cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is

therefore important. As stabilization guidelines, it is recommended to control power so that V^CCrippli fluctuations

(P-P value) will be less than 10% of the standard V^CCvalue at the commercial frequency (50 to 60 Hz) and the

transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power

is switched.

5. Precautions when Using an External Clock

When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and

wake-up from stop mode.

12

MB89950 Series

■ PROGRAMMING TO THE EPROM ON THE MB89P955

The MB89P955 is an OTPROM version of the MB89950 series.

1. Features

• 16-Kbyte PROM on chip

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in EPROM mode is diagrammed below.

Address

0000^H

Single chip

EPROM mode

(Corresponding addresses on the EPROM programmer)

I/O

0080^H

0280^H

RAM

Not available

8000^H

0000^H

Vacancy

Not available

Option area

Not available

(Read value FF^H)

BFF0^H

BFF6^H

3FF0^H

Option area

3FF7^H

Vacancy

(Read value FF^H)

C000^H

4000^H

PROM

16 KB

EPROM

16 KB

FFFF^H

7FFF^H

3. Programming to the EPPROM

Functions equivalent to the MBM27C256A can be used in the MB89P955 EPROM mode. Accordingly, the user

can write data with a general-purpose EPROM writer by using a dedicated adapter. Note that the electrical

signature mode is not supported.

• Programming procedure

(1) Set the EPROM writer for the MBM27C256A.

(2) Load program data from 4000^Hto 7FFFH of the EPROM writer (Note that 0C000H to 0FFFFH in the operation

mode are equivalent to 4000H to 7FFFH in the EPROM mode).

Load option data from 3FF0^Hto 3FF6H of the EPROM writer (See Bit Map on the next page for the

correspondence to each option).

(3) Write the data with the EPROM writer.

13

MB89950 Series

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

OTPROM microcomputer program.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

5. Programming Yield

Duetoitsnature, bitprogrammingtestcan’tbeconductedasFujitsudeliverytest. Forthisreason, aprogramming

yield of 100% cannot be assured at all times.

6. EPROM Programmer Socket Adapter

Part number

Package

MB89P955PFM

QFP-64

Compatible socket adapter

Sun Hayato Co., Ltd.

ROM-64QF2-28DP-8L3

Inquiry: Sun Hayato Co., Ltd.: TEL : (81)-3-3986-0403

FAX: (81)-3-5396-9106

14

MB89950 Series

7. Setting OTPROM Options

The programming procedure is the same as that for the PROM. Options can be set by programming values at

the addresses shown on the memory map. The relationship between bits and options is shown on the following

bit map:

• OTPROM option bit map

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Vacancy

Oscillation

stabilization

time

Vacancy

Reset pin Power-on

ouput

reset

3FF0^H

1: 2¹⁸/fC

Readable

and writable and writable

Readable

1: Yes

0: No

1: Yes

0: No

0: 2¹⁴/fC

and writable and writable and writable

Vacancy

P46

P45

P44

P43

P42

P41

P40

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

3FF1H

Readable

and writable

Vacancy

3FF2^H

3FF3H

3FF4H

3FF5H

3FF6H

Readable

and writable and writable and writable and writable and writable and writable and writable and writable

Vacancy

Readable

and Writable and writable and writable and writable and writable and writable and writable and writable

Vacancy

Readable

and writable and writable and writable and writable and writable and writable and writable and writable

Vacancy

Readable

and writable and writable and writable and writable and writable and writable and writable and writable

Vacancy

Readable

and writable and writable and writable and writable and writable and writable and writable and writable

Note: Each bit is set to ‘1’ as the initialized value, therefore the pull-up option is not selected.

15

MB89950 Series

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TV

2. Programming Socket Adapter

To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato

Co., Ltd.) listed below:

Package

Adapter socket part number

LCC-32 (Rectangle)

ROM-32LC-28DP-YG

Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403

FAX: (81)-3-5396-9106

3. Memory Space

Memory space in each mode such as 32-Kbyte PROM, is diagrammed below.

Address

0000H

0080H

Single chip

Corresponding address on the EPROM programmer

I/O

RAM

Not available

0000H

PROM

32 KB

EPROM

32 KB

7FFF^H

FFFF^H

4. Programming to the EPROM

(1) Set the EPROM programmer for the MBM27C256A.

(2) Load program data into the EPROM programmer at 0007^Hto 7FFFH.

(3) Program with the EPROM programmer.

16

MB89950 Series

■ BLOCK DIAGRAM

X0

X1

20-bit

timebase timer

Oscillator

8-bit PWM timer

P41/PWM

P40

Clock control

External interrupt

8-bit

pulse width

counter

timer

Reset circuit

(WDT)

RST

Noise

clear

P42/PWC/

INT1

8

N-ch open-drain I/O port

P00/SEG20 to

P07/SEG27

8

P10/SEG28 to

P17/SEG35

P45/SCK

P44/SO

P43/SI

8-bit serial I/O

UART

20

SEG0 to SEG19

4

COM0 to COM3

P46/INT0

LCD controller/driver

V3

6

P20/SEG36 to

P25/SEG41

P33/V2

CMOS I/O port

P32/V1

P30

N-ch open-drain I/O port

P31

R A M (256 × 8 bits)

Other pins

MODA

V^CC, V^SS

F²MC-8L

CPU

R O M (8 K × 8 bits)

17

MB89950 Series

■ CPU CORE

1. Memory Space

F²MC-8L CPU has 64 Kbytes of memory. All I/O, data program areas are located in this space. The I/O area is

near the lowest address and the data area is immediately above it. The data area can be divided into register,

stack, and direct-address areas according to the applications. The program area is located near the highest

address, and the tables of interrupt and reset vectors and vector-call instructions are at the highest address in

this area. The following figure shows the structure of the memory space for the MB89950 series of

microcontrollers.

• Memory Space

MB89P955

I/O

MB89PV950

I/O

MB89951

MB89953

I/O

0000^H

0080^H

0000^H

0080^H

0000^H

0080^H

0000^H

0080^H

I/O

Reserved

00C0^H

RAM

0100^H

0180^H

0100^H

0140^H

0100^H

0200^H

Register

0200^H

0280^H

0480^H

8000^H

Vacant

C000^H

E000^H

F000^H

FFFF^H

ROM

FFFF^H

18

MB89950 Series

2. Registers

The F²MC-8L family has two types of registers; dedicated hardware registers in the CPU and general-purpose

memory registers. The following registers are provided:

Program counter (PC):

Accumulator (A):

A 16-bit register for indicating the instruction storage positions.

A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which is used for arithmetic operations with the accumulator

Whentheinstructionisan8-bitdataprocessinginstruction, thelowerbyteisused.

Index register (IX):

Extra pointer (EP):

Stack pointer (SP):

Program status (PS):

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit pointer for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

16 bits

PC

Initial value

: Program counter

: Accumulator

FFFD^H

A

T

Indeterminate

: Temporary accumulator

: Index register

IX

EP

SP

PS

: Extra pointer

: Stack pointer

: Program status

I-flag = 0, IL1, 0 = 11

The other bit values are Indeterminate.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

• Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

PS

RP

Vacancy Vacancy Vacancy

H

IL1, 0

N

V

C

RP

CCR

19

MB89950 Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

• Rule for Conversion of Actual Addresses of the General-purpose Register Area

Lower OP codes

RP

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data, and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

to ‘0’ otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared

to ‘0’ at the reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low

N-flag: Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit is

cleared to ‘0’.

Z-flag: Set to ‘1’ when an arithmetic operation results in ‘0’. Cleared to ‘0’ otherwise.

V-flag: Set to ‘1’ if the complement on ‘2’ overflows as a result of an arithmetic operation. Cleared to ‘0’ if the

overflow does not occur.

C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to

‘0’ otherwise.

Set to the shift-out value in the case of a shift instruction.

20

MB89950 Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit resister for storing data

The general-purpose registers are of 8 bits and located in the register banks of the memory. One bank contains

eight registers. Up to a total of 4 banks can be used on the MB89951 and a total of 8 banks can be used on the

MB89953 and a total of 16 banks can be used on the MB89P955 and a total of 32 banks can be used on the

MB89PV950. The bank currently in use is indicated by the register bank pointer (RP).

• Register Bank Configuration

This address = 0100H + 8 × (RP)

R0

R1

R2

R3

R4

R5

R6

4 banks (MB89951)

R7

8 banks (MB89953)

16 banks (MB89P955)

32 banks (MB89PV950)

Memory area

21

MB89950 Series

■ I/O MAP

Address

00^H

Read/write

Register name

Register description

Port 0 data register

Vacancy

Port 1 data register

Vacancy

Port 2 data register

Vacancy

(R/W)

PDR0

01^H

02^H

(R/W)

PDR1

PDR2

03H

04^H

05^Hto 07H

08H

(R/W)

STBC

WDTC

TBCR

Standby control register

09^H

Watchdog timer control register

Timebase timer control register

0AH

0B^H

Vacancy

Port 3 data register

Vacancy

0CH

0DH

0E^H

(R/W)

PDR3

(R/W)

(W)

PDR4

DDR4

Port 4 data register

0FH

Port 4 data direction register

10H

Vacancy

11^H

12H

(R/W)

(W)

CNTR

COMR

PCR1

PCR2

RLBR

NCCR

PWM control register

13^H

PWM compare register

14H

(R/W)

PWC pulse width control register 1

PWC pulse width control register 2

PWC reload buffer register

15H

16^H

17H

PWC noise reduction control register

18H to 1BH

1C^H

1D^H

1EH

Vacancy

(R/W)

SMR

SDR

Serial mode register

Serial data register

Vacancy

1F^H

20H

(R/W)

SMC1

SRC

UART serial mode control register 1

UART serial rate control register

UART serial status/data register

UART serial data register

21H

22H

SSD

23^H

SIDR/SODR

SMC2

24H

UART serial mode control register 2

(Continued)

22

MB89950 Series

(Continued)

Address

25^Hto 2FH

30^H

Read/write

Register name

Vacancy

External interrupt 1 control register 1

Vacancy

Register description

(R/W)

EIC1

31H to 63H

64^Hto 78H

79^H

(R/W)

VRAM

LCDR

SEGR

Display data RAM

LCD control register

7AH

Segment output select register

7B^H

Vacancy

7C^H

(W)

—

ILR1

ILR2

ILR3

ITR

Interrupt level setting register 1

Interrupt level setting register 2

Interrupt level setting register 3

Interrupt test register

7DH

7E^H

7FH

Note: Do not use vacancies.

23

MB89950 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

Power supply voltage

V^CC

V3

VSS – 0.3 VSS + 7.0

V

LCD power supply

voltage

V^SS– 0.3 VSS + 7.0

All the pins must not exceed VSS + 7.0 V,

excluding P00 to P07, P10 to P17,

P20 to P25,P32 to P33 in MB89P955/PV950

V^I1

VSS – 0.3 VCC + 0.3

VSS – 0.3 VSS + 7.0

V

Input voltage

Applicable to P00 to P07, P10 to P17,

P20 to P25 (port select) in MB89951/953

V^I2

V^I3

V

*P00 to P07, P10 to P17, P20 to P25,

P32 to P33

VSS – 0.3

V3

All the pins must not exceed Vss + 7.0 V,

excluding P00 to P07, P10 to P17, P20 to

P25,

V^O1

VSS – 0.3 VCC + 0.3

VSS – 0.3 VSS + 7.0

V

P32 to P33 in MB89P955/PV950

Output voltage

Applicable to P00 to P07, P10 to P17,

P20 to P25 (port select) in MB89951/953

V^O2

V^O3

V

P00 to P07, P10 to P17, P20 to P25,

P32 to P33*

VSS – 0.3

V3

10

Applicable to all pins except power supply

pin.

“L” level output current I^OL

mA

Applicable to all pins excluding power supply

pin.

“L” level average

output current

I^OLAV

4

mA

Specified as the average value in 1 hour.

“L” level total output

current

∑I^OL

40

–5

mA

Applicable to all pins excluding power supply

pin.

“H” level output current I^OH

Applicable to all pins excluding power supply

pin.

“H” level average

output current

I^OHAV

–2

mA

Specified as the average value in 1 hour.

“H” level total output

maximum current

∑I^OH

–10

Power consumption

P^D

300

+85

mW

°C

Operating temperature T^A

Storage temperature Tstg

–40

–55

+150

°C

* : It is only suitable to MB89P955/PV950.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

24

MB89950 Series

2. Recommended Operating Conditions

(VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

2.2*

6.0

V

Usual operation guarantee range

Power supply voltage

V^CC

RAM-data-holding guarantee range at stop

mode

1.5

6.0

V3 pins for MB89953

The voltage range supplied to LCD and its

optimum value depend on the LCD

LCD power supply

voltage

V3

V^SS

6.0

V

Operating temperature

TA

–40

+85

°C

* : This value varies with the operating frequency and analog assurance range. See Figure 1.

• Figure 1 Operating Voltage vs. Main Clock Operating Frequency (MHz)

6

5

Operating assurance range

4

3

2

1

2

3

4

5

Operating frequency (MHz)

4.0

2.0

1.3

1.0

s)

0.8

Minimum instruction cycle (

µ

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All

the device’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

25

MB89950 Series

3. DC Characteristics

(VCC = V3 = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Parameter

Pin name

Condition

Unit

Remarks

Min.

0.7 V^CC

0.7 V_CC

Typ.

Max.

0.3 V^CC

V3

P00 to P07,

P10 to P17,

P20 to P25,

P30 to P31,

P40 to P46

*1

—

V

V^IH

“H” level input

voltage

P32,P33

—

V

RST, INT0, SCK,

SI, PWC/INT1

V^IHS

0.8 V^CC

VCC + 0.3

P00 to P07,

P10 to P17,

P20 to P25,

P30 to P33,

P40 to P46

*1

V^IL

—

V^SS– 0.3

—

0.3 V^CC

V

“L” level input

voltage

RST, MODA,

INT0, SCK, SI,

PWC/INT1

V^ILS

V^SS– 0.3

0.2 VCC

P00 to P07,

P10 to P17,

P20 to P25

(port select) in

MB89951/953

P30 to P31,

P20 to P25,

P10 to P17,

P00 to P07

VSS + 6.0

Open-drain

output pin

Applied voltage

V^D

P32 to P33

(port select)

P32, P33

—

V^SS– 0.3

4.0

—

V3

—

V

“H” level Output

voltage

V^OH

P40 to P46

IOH = –2.0 mA

P00 to P07,

P10 to P17,

P20 to P25,

P30 to P33

V^OL1

I^OL= 4.0 mA

—

0.4

V

“L” level Output

voltage

V^OL2

RST, P40 to P46 IOL = 4.0 mA

—

0.4

MODA,

P30, P31,

P40 to P46

When pull-up

±5

µA option is not

Input leakage

current (Hi-z

output leak

current)

selected

0.45 V < VI <

V^CC

I^LI1

P00 to P07,

P10 to P17,

P20 to P25,

P32, P33

When pull-up

µA option is not

selected

—

±5

When pull-up

kΩ option is

selected

Pull-up

resistance

RST,

P40 to P46

R^PULL

V^I= 0.0 V

25

—

50

—

100

2.5

Common

Output

impedance

V1 to V3 =

+5.0 V

R^VCOM

COM0 to COM3

kΩ

(Continued)

26

MB89950 Series

(Continued)

(VCC = V3 = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Parameter

Pin name

Condition

Unit

Remarks

Min.

Typ.

Max.

Segment

Output

impedance

V1 to V3 =

+5.0 V

R^VSEG

R^LCD

I^LCDL

SEG0 to SEG41

—

15

kΩ

µA

LCD divided

resistance

V1 to V3

30

—

60

—

120

V1 to V3,

COM0 to COM3,

SEG0 to SEG41

LCD leak

current

—

±10

Pull-down

resistance

—

MODA

TBD

—

TBD

3.5

TBD

5.0

kΩ

mA

FC = 5 MHz

Main RUN

mode

I^CC

VCC

t^inst*3= 0.8µs

Power Supply

voltage

FC = 5 MHz

Main SLEEP

mode

I^CCS

I^CCH

C^IN

VCC

—

1.1

0.1

10

1.7

1

t^inst*3= 0.8µs

TA = +25°C

µA STOP mode

Input

capacitance

Except VCC and

V^SS

f = 1 MHz

—

pF

*1: Port input voltage is smaller than V3 for MB89P955/PV950.

*2: TBD = To be determined

*3: For information on t^inst, see “(4) Instruction Cycle” in “4.AC Characteristics.”

Note: For pins for selection of segments (SEG8 to SEG31) and ports (P10 to P17, P40 to P47, P50 to P57), see

the limits values of ports when port output is selected and those for segments when segment output is

selected.

27

MB89950 Series

4. AC Characteristics

(1) Reset Timing

(VCC = 5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit

Remarks

Parameter

Min.

Max.

RST “L” pulse width

tZLZH

—

48 tXCYL*

—

ns

* : tXCYL is the oscillation cycle (1/FC) to input to the XO pin.

t^ZLZH

RST

0.2 V^CC

(2) Specifications for Power-on Reset

(VCC = 5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol Condition

Unit

Remarks

Parameter

Min.

Max.

Power supply rising time

Power supply cut-off time

t^R

—

1

50

ms

Power-on reset function only

—

Min. interval time to the next

power-on reset

t^OFF

—

Note: If power-on reset provided is selected, an abrupt change in the power supply voltage could cause a power-

on reset. When changing the power supply voltage during operation, voltage fluctuations should be two or

less times for smooth start-up.

t^OFF

t^R

2.0 V

0.2 V

V^CC

28

MB89950 Series

(3) Clock Timing

Parameter

(VSS = 0.0 V, TA = –40°C to +85°C)

Value

Typ.

—

Symbol Pin name

Unit

Remarks

Min.

1

Max.

5

Clock frequency

F^C

X0, X1

X0

MHz

ns

Clock cycle time

t^HCYL

duty

400

30

—

2000

70

Input clock duty ratio*

—

%

crystal & ceramic

Input clock rising/falling

time

t^CR

tCF

Applied when external

clock used

X0

—

10

ns

* : duty = PWH/tHCYL

• Timing Conditions

t^HCYL

X0

0.8 V^CC

0.2 V^CC

P^WH

P^WL

t^CF

t^CR

• Clock Configurations

When crystal

or

ceramic resonator is used

When external clock is used

X0

X1

X0

X1

f

CH

Open

F

C

C0

C

1

(4) Instruction Cycle

(VSS = 0.0 V, TA = –40°C to +85°C)

Symbol

Value

4/FC to 64/FC

Unit

Remarks

Parameter

Instruction cycle

(Minimum instruction

executing time)

t^inst= 0.8 µs when operating at

t^inst

µs

FC = 5 MHz

29

MB89950 Series

(5) Serial I/O & UART timing

(VCC = 5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Pin name

SCK

Condition

Unit Remarks

Parameter

Min.

2 t^inst*

200

Max.

—

Serial clock cycle time

SCK1 ↓ → SO time

t^SCYC

t^SLOV

tIVSH

t^SHIX

t^SHSL

tSLSH

t^SLOV

tIVSH

t^SHIX

µs

ns

µs

ns

µs

Internal

clock

operation

SCK, SO

SI, SCK

SCK, SI

SCK

200

—

Valid SI → SCK ↑

0.5 tinst*

1 t^inst*

1 tinst

SCK ↑ → valid SI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK1 ↓ → SO time

—

SCK

—

External

clock

operation

SCK, SO

SI, SCK

SCK, SI

0

200

—

Valid SI → SCK ↑

0.5 tinst*

SCK ↑ → valid SI hold time

—

* : For information on tinst, see “(4) Instruction Cycle.”

30

MB89950 Series

• Internal Shift Clock Mode

t^SCYC

2.4 V

SCK

0.8 V

t^SLOV

2.4 V

0.8 V

SO

SI

t^SHIX

t^IVSH

0.8 V^CC

0.2 V^CC

0.8 V^CC

0.2 V^CC

• External Shift Clock Mode

t^SLSH

t^SHSL

0.7 V^CC

SCK

SO

SI

0.2 V^CC

t^SLOV

2.4 V

0.8 V

t^IVSH

0.8 V^CC

0.2 V^CC

t^SHIX

0.8 V^CC

0.2 V^CC

31

MB89950 Series

(6) Peripheral Input Timing

(VCC = 5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Pin name

Unit Remarks

Parameter

Min.

2 tinst*

Max.

—

Peripheral input “H” level pulse width 1 t^ILIH1

Peripheral input “L” level pulse width 1 t^IHIL1

PWC, INT1, INT0

µs

—

* : For information on tinst, see “(4) Instruction Cycle.”

t^IHIL1

t^ILIH1

PWC, INT, INT0

0.8 V^CC

0.2 V^CC

0.8 V^CC

0.2 V^CC

32

MB89950 Series

■ INSTRUCTIONS (136 INSTRUCTIONS)

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

#vct

#d8

#d16

dir: b

rel

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

Register indirect (Example: @A, @IX, @EP)

@

A

AH

AL

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

Lower 8 bits of accumulator A (8 bits)

T

TH

TL

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

IX

EP

PC

SP

PS

dr

CCR

RP

Ri

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

Register bank pointer RP (5 bits)

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

( × )

(( × ))

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

Columns indicate the following:

Mnemonic: Assembler notation of an instruction

~:

#:

The number of instructions

The number of bytes

Operation: Operation of an instruction

TL, TH, AH:

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH prior to the instruction executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

33

MB89950 Series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

47

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

48 to 4F

04

05

06

60

92

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

07

(A) ← (Ri)

(dir) ← d8

08 to 0F

85

86

87

88 to 8F

D5

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)

(A) ← (EP)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

–

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(EP) ← d16

(IX) ← (A)

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

AL

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

–

F0

Note During byte transfer to A, T ← A is restricted to low bytes.

Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

34

MB89950 Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3

C2

C0

D8 to DF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

(TL) − (AL)

(T) − (A)

–

13

03

→

C

A

←

C

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

(A) − (Ri)

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

35

MB89950 Series

(Continued)

Mnemonic

~

#

Operation

(A) ← (AL) ( (EP) )

TL

TH AH NZVC OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

36

MB89950 Series

■ INSTRUCTION MAP

37

MB89950 Series

■ MASK OPTIONS

MB89951

MB89953

Model

MB89P955

MB89PV950

Fixed

No.

Select when

ordering mask

Specification method

Set by EPROM

Pull-up resistors

P40 to P46

Can be selected for Can be selected for

1

No pull-up resistor

each pin

Port/segment output

Can be selected for

every 8 to 1 pins^*2

Port/segment

output^*3

2

3

P00 to P07,

P20 to P25

P10 to P17,

Port/segment output*3

Power-on reset

available

Power-on reset available

Power-on reset unavailable

Selectable

Selection of main clock oscillation

stabilization time

(at 5 MHz)^*1

2¹⁸/FC

4

5

Approx. 2¹⁸/FC (Approx. 52.4 ms)

Approx. 2¹⁴/FC (Approx. 3.28 ms)

Reset pin output

Reset output available

Reset output unavailable

Reset output available

*1: The main clock oscillation stabilization time is generated by dividing the main clock oscillation. Since the

oscillation cycle is unstable immedeately after oscillation starts, the time in this table is only a guide.

*2: Port/segment output switching should be specified in the same manner as the port allocation set by the segment

output select register in the LCD controller/driver.

*3: When those pins are used as ports, applied voltage should never be jogjer than V3.

■ ORDERING INFORMATION

Part Number

MB89951PFM

MB89953PFM

MB89P955PFM

Package

Remarks

64-pin Plastic QFP

(FPT-64P-M09)

64-pin Ceramic MQFP

(MQP-64C-M01)

MB89PV950CF

38

MB89950 Series

■ PACKAGE DIMENSIONS

64-pin Plastic QFP

(FPT-64P-M09)

14.00±0.20(.551±.008)SQ

12.00±0.10(.472±.004)SQ

1.50^–⁺⁰⁰^.^.¹²⁰⁰

.059⁺^–.^.⁰⁰⁰⁰⁴⁸

48

49

33

32

(Mounting height)

9.75

(.384)

REF

13.00

(.512)

NOM

1 PIN INDEX

64

17

M

1

16

Details of "A" part

0.10±0.10

LEAD No.

0.65(.0256)TYP

0.30±0.10

(.012±.004)

0.127^–⁺⁰⁰^.^.⁰⁰²⁵

.005^–⁺^.^.⁰⁰⁰⁰¹²

"A"

0.13(.005)

(STAND OFF)

(.004±.004)

0.50±0.20

(.020±.008)

0.10(.004)

0

10°

C

1994 FUJITSU LIMITED F64018S-1C-2

Dimensions in mm (inches)

64-pin Ceramic MQFP

(MQP-64C-P01)

18.70(.736)TYP

16.30±0.33

(.642±.013)

15.58±0.20

(.613±.008)

12.00(.472)TYP

INDEX AREA

1.00±0.25

(.039±.010)

1.20⁺^–0⁰^.^.²⁴⁰⁰

.047 ⁺^–.^.⁰⁰⁰¹⁸⁶

1.00±0.25

(.039±.010)

1.27±0.13

(.050±.005)

18.12±0.20

(.713±.008)

22.30±0.33

(.878±.013)

12.02(.473)

TYP

18.00(.709)

TYP

10.16(.400)

14.22(.560)

TYP

0.30(.012)

TYP

24.70(.972)

TYP

0.40±0.10

(.016±.004)

1.27±0.13

(.050±.005)

0.30(.012)TYP

7.62(.300)TYP

9.48(.373)TYP

11.68(.460)TYP

0.40±0.10

(.016±.004)

1.20^–⁺⁰⁰^.^.²⁴⁰⁰

.047^–⁺^.^.⁰⁰⁰¹⁸⁶

10.82(.426)

MAX

0.15±0.05

(.006±.002)

0.50(.020)TYP

C

1994 FUJITSU LIMITED M64004SC-1-3

Dimensions in mm (inches)

39

MB89950 Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

The contents of this document are subject to change without

notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

KAWASAKI PLANT, 4-1-1, Kamikodanaka,

Nakahara-ku, Kawasaki-shi,

Kanagawa 211-8588, Japan

Tel: +81-44-754-3763

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications,

and are not intended to be incorporated in devices for actual use.

Also, FUJITSU is unable to assume responsibility for

Fax: +81-44-754-3329

http://www.fujitsu.co.jp/

infringement of any patent rights or other rights of third parties

arising from the use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, USA

Tel: +1-408-922-9000

The contents of this document may not be reproduced or copied

without the permission of FUJITSU LIMITED.

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipments, industrial, communications, and

measurement equipments, personal or household devices, etc.).

CAUTION:

Fax: +1-408-922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded

(such as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

Fax: +1-408-922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

Any semiconductor devices have inherently a certain rate of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan,

New Tech Park,

Singapore 556741

Tel: +65-281-0770

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required

for export of those products from Japan.

Fax: +65-281-0220

http://www.fmap.com.sg/

F9609

FUJITSU LIMITED Printed in Japan


型号：	MB89P955
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontroller 8位微控制器专有微控制器
文件：	总40页 (文件大小：562K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89P955 [FUJITSU]

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