MB89W857C-SH [FUJITSU]
8-bit Proprietary Microcontroller; 8位微控制器专有型号: | MB89W857C-SH |
厂家: | FUJITSU |
描述: | 8-bit Proprietary Microcontroller |
文件: | 总48页 (文件大小:637K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12535-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89850R Series
MB89855R/P857/W857
■ DESCRIPTION
The MB89850R series has been developed as a general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit, single-chip microcontrollers.
In addition to the F2MC-8L CPU core which can operate at low voltage but at high speed, the microcontrollers
contain a variety of peripheral functions such as a timer unit, PWM timers, a UART, a serial interface, a 10-bit
A/D converter, and an external interrupt.
The MB89850R series is applicable to a wide range of applications from consumer products to industrial
equipment, including portable devices.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• Various package options
SDIP package (64 pins)/QFP package (64 pins)
• High-speed processing at low voltage
Minimum execution time: 0.4 µs/3.5 V, 0.8 µs/2.7 V
(Continued)
■ PACKAGE
64-pin Plastic SH-DIP
64-pin Plastic QFP
64-pin Ceramic SH-DIP
64-pin Ceramic QFP
(DIP-64P-M01)
(FPT-64P-M06)
(DIP-64C-A06)
(FPT-64C-A02)
MB89850R Series
(Continued)
• F2MC-8L family CPU core
Multiplication and division instructions
16-bit arithmetic operations
Test and branch instructions
Instruction set optimized for controllers
Bit manipulation instructions, etc.
• 8-bit PWM timers: 2 channels
Also usable as a reload timer
• UART
Full-duplex double buffer
Synchronous and asynchronous data transfer
• 8-bit serial I/O
Switchable transfer direction allows communication with various equipment.
• 10-bit A/D converter
Conversion time: 13.2 µs
Activation by an external input or a timer unit capable
• External interrupt: 4 channels
Four channels are independent and capable of wake-up from low-power consumption modes (with an edge
detection function).
• Low-power consumption modes
Stop mode (Oscillation stops to minimize the current consumption.)
Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)
• Bus interface functions
Including hold and ready functions
• Timer unit
Outputs non-overlap three-phase waveforms to control an AC inverter motor.
Also usable as a PWM timer (4 channels)
2
MB89850R Series
■ PRODUCT LINEUP
Part number
Parameter
MB89P857
MB89W857
MB89855R
Classification
Mass production products
(mask ROM products)
One-time PROM pruducts/EPROM
products, also used for evaluation
ROM size
16 K × 8 bits
(internal mask ROM)
32 K × 8 bits
(internal PROM, programming with
general-purpose EPROM programmer)
RAM size
512 × 8 bits
1 K × 8 bits
CPU functions
Number of instructions:
Instruction bit length:
Instruction length:
136
8 bits
1 to 3 bytes
Data bit length:
Minimum execution time:
Interrupt processing time:
1, 8, 16 bits
0.4 µs/10 MHz
3.6 µs/10 MHz
Ports
Input ports:
5 (All also serve as peripherals)
Output ports (N-ch open drain): 8 (All also serve as peripherals)
Output ports (CMOS):
I/O ports (CMOS):
Total:
8 (All also serve as bus control pins)
32 (All also serve as bus pins or peripherals)
53
Timer unit
10-bit up/down count timer × 1
Compare registers with buffer × 4
Compare timer unit clear register with buffer × 1
Zero detection pin control
4 output channels
Non-overlap three-phase waveform output
Independent three-phase dead-time timer
8-bit PWM timer 1,
8-bit PWM timer 2
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to 25.6 µs)
8-bit resolution PWM operation (conversion cycle: 102 µs to 6.528 ms)
UART
8 bits
Clock synchronous/asynchronous data transfer capable
8-bit serial I/O
8 bits
LSB first/MSB first selectability
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)
10-bit A/D converter
External interrupt
10-bit resolution × 8 channels
A/D conversion time: 13.2 µs
Continous activation by a compare channel 0 in timer unit or an external activation capable
4 independent channels (edge selection, interrupt vector, source flag)
Rising edge/falling edge selectability.
Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)
Standby modes
Process
Sleep mode, stop mode
CMOS
Operating voltage*
2.7 V to 6.0 V
2.7 V to 5.5 V
* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
3
MB89850R Series
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
DIP-64P-M01
DIP-64C-A06
FPT-64P-M06
FPT-64C-A02
MB89855R
MB89P857
MB89W857
×
×
×
×
×
×
: Available
× : Not available
Note: For more information about each package, see section “■ Package Dimensions.”
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the OTPROM (one-time PROM) products (also used for evaluation), verify its differences
from the product that will actually be used.
Take particular care on the following point:
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
When operated at low speed, the product with an OTPROM or an EPROM will consume more current than the
product with a mask ROM.
However, the current consumption in sleep/stop modes is the same.
3. Mask Options
In the MB89P857/W857, no option can be set.
Before using options check section “■ Mask Options.”
Take particular care on the following point:
• A pull-up resistor can be set for P00 to P07, P10 to P17 and P20 to P27 only at single-chip mode.
4
MB89850R Series
■ PIN ASSIGNMENT
(Top view)
P31/SO1
P30/SCK1
P47/TRGI
P46/Z
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
P32/SI1
P33/SCK2
P34/SO2
P35/SI2
P36/PTO1
P37/PTO2
VSS
P45/Y
P44/X
P43/RTO3/W
P42/RTO2/V
P41/RTO1/U
P40/RTO0
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
9
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/A08
P11/A09
P12/A10
P13/A11
P14/A12
P15/A13
P16/A14
P17/A15
P20/BUFC
P21/HAK
P22/HRQ
P23/RDY
P24/CLK
P25/WR
P26/RD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVR
AVSS
P64/DTTI
P63/INT3/ADST
P62/INT2
P61/INT1
P60/INT0
RST
MOD0
MOD1
X0
X1
VSS
P27/ALE
(DIP-64P-M01)
(DIP-64C-A06)
5
MB89850R Series
(Top view)
P42/RTO2/V
P41/RTO1/U
P40/RTO0
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
1
2
3
4
5
6
7
8
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P37/PTO2
VSS
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/A08
P11/A09
P12/A10
P13/A11
P14/A12
P15/A13
P16/A14
P17/A15
P20/BUFC
9
10
11
12
13
14
15
16
17
18
19
AVR
AVSS
P64/DTTI
P63/INT3/ADST
P62/INT2
P61/INT1
P60/INT0
(FPT-64P-M06)
(FPT-64C-A02)
6
MB89850R Series
■ PIN DESCRIPTION
Pin no.
Circuit
type
Pin name
X0
Function
SH-DIP*1
QFP*2
23
30
31
28
29
27
A
B
C
Crystal oscillator pins (10 MHz)
24
X1
21
MOD0
MOD1
RST
Operating mode selection pins
Connect directly to VCC or VSS.
22
20
Reset I/O pin
This pin is an N-ch open-drain output type with a pull-up
resistor, and a hysteresis input type. “L” is output from this
pin by an internal reset source. The internal circuit is
initialized by the input of “L”.
56 to 49
48 to 41
40
49 to 42 P00/AD0 to
P07/AD7
D
D
F
F
General-purpose I/O ports
When an external bus is used, these ports function as
multiplex pins of lower address output and data I/O.
41 to 34 P10/A08 to
P17/A15
General-purpose I/O ports
When an external bus is used, these ports function as
upper address output.
33
32
P20/BUFC
P21/HAK
General-purpose output port
When an external bus is used, this port can also be used
as a buffer control output.
39
General-purpose output port
When an external bus is used, this port can also be used
as a hold acknowledge output.
38
37
36
35
34
33
2
31
30
29
28
27
26
59
P22/HRQ
P23/RDY
P24/CLK
P25/WR
P26/RD
D
D
F
F
F
F
E
General-purpose output port
When an external bus is used, this port can also be used
as a hold request input.
General-purpose output port
When an external bus is used, this port functions as a
ready input.
General-purpose output port
When an external bus is used, this port functions as a
clock output.
General-purpose output port
When an external bus is used, this port functions as a
write signal output.
General-purpose output port
When an external bus is used, this port functions as a
read signal output.
P27/ALE
P30/SCK1
General-purpose output port
When an external bus is used, this port functions as an
address latch signal output.
General-purpose I/O port
Also serves as the clock I/O for the UART.
This port is a hysteresis input type.
(Continued)
*1: DIP-64P-M01, DIP-64C-A06
*2: FPT-64P-M06, FPT-64C-A02
7
MB89850R Series
(Continued)
Pin no.
Circuit
type
Pin name
Function
General-purpose I/O port
Also serves as the data output for the UART.
This port is a hysteresis input type.
SH-DIP*1
QFP*2
1
58
P31/SO1
P32/SI1
E
E
E
E
E
E
E
E
E
63
62
61
60
59
58
10
56
55
54
53
52
51
3
General-purpose I/O port
Also serves as the data input for the UART.
This port is a hysteresis input type.
P33/SCK2
P34/SO2
P35/SI2
General-purpose I/O port
Also serves as the clock I/O for the 8-bit serial I/O.
This port is a hysteresis input type.
General-purpose I/O port
Also serves as the data output for the 8-bit serial I/O.
This port is a hysteresis input type.
General-purpose I/O port
Also serves as the data input for the 8-bit serial I/O.
This port is a hysteresis input type.
P36/PTO1
P37/PTO2
P40/RTO0
General-purpose I/O port
Also serves as the pulse output for the 8-bit PWM timer 1.
This port is a hysteresis input type.
General-purpose I/O port
Also serves as the pulse output for the 8-bit PWM timer 2.
This port is a hysteresis input type.
General-purpose I/O port
Also serves as the pulse output for the timer unit.
This port is a hystereisis input type.
9,
8,
7
2,
1,
64
P41/RTO1/U,
P42/RTO2/V,
P43/RTO3/W
General-purpose I/O ports
Also serve as the pulse output or non-overlap three-
phase waveform output for the timer unit.
These ports are a hysteresis input type.
6,
5,
4
63,
62,
61
P44/X,
P45/Y,
P46/Z
E
E
General-purpose I/O ports
Also serve as a non-overlap three-phase waveform
output.
These ports are a hysteresis input type.
3
60
P47/TRGI
General-purpose I/O port
Also serves as the trigger input for the timer unit.
This port is a hysteresis input type.
11 to 18
26 to 24
4 to 11
P50/AN0 to
P57/AN7
G
H
N-ch open-drain output ports
Also serve as the analog input for the A/D converter.
19 to 17 P60/INT0 to
P62/INT2
General-purpose input ports
Also serve as an external interrupt input.
These ports are a hysteresis input type.
23
16
P63/INT3/
ADST
H
General-purpose input port
Also serves as an external interrupt input and as the
activation trigger input for the A/D converter.
This port is a hysteresis input type.
(Continued)
*1: DIP-64P-M01, DIP-64C-A06
*2: FPT-64P-M06, FPT-64C-A02
8
MB89850R Series
(Continued)
Pin no.
Circuit
type
Pin name
Function
SH-DIP*1
QFP*2
22
15
P64/DTTI
H
General-purpose input port
Also serves as a dead-time timer disable input.
This port is a hysteresis input type.
DTTI input is with a noise canceller.
64
32, 57
19
57
25, 50
12
VCC
—
—
—
—
—
Power supply pin
VSS
Power supply (GND) pins
AVCC
AVR
AVSS
A/D converter power supply pin
A/D converter reference voltage input pin
20
13
21
14
A/D converter power supply (GND) pin
Use this pin at the same voltage as VSS.
*1: DIP-64P-M01, DIP-64C-A06
*2: FPT-64P-M06, FPT-64C-A02
9
MB89850R Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• At an oscillation feedback resistor of approximately
1 MΩ/5.0 V
X1
X0
Standby control signal
B
C
• At an output pull-up resistor (P-ch) of approximately
50 kΩ/5.0 V
R
• Hysteresis input
P-ch
N-ch
D
• CMOS output
• CMOS input
R
• Pull-up resistor optional (Mask ROM products)
• At a pull-up resistor of approximately 50 kΩ/5.0 V
P-ch
P-ch
N-ch
E
• CMOS output
• Hysteresis input
R
• Pull-up resistor optional (Mask ROM products)
• At a pull-up resistor of approximately 50 kΩ/5.0 V
P-ch
P-ch
N-ch
(Continued)
10
MB89850R Series
(Continued)
Type
Circuit
Remarks
F
• CMOS output
• Pull-up resistor optional (Mask ROM products)
• At a pull-up resistor of approximately 50 kΩ/5.0 V
R
P-ch
P-ch
N-ch
G
H
• N-ch open-drain output
• Analog input
N-ch
Analog input
• Hysteresis input
• Pull-up resistor optional (Mask ROM products)
• At a pull-up resistor of approximately 50 kΩ/5.0 V
R
11
MB89850R Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pin
Be sure to leave (internally connected) N.C. pin open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
wake-up from stop mode.
12
MB89850R Series
■ PROGRAMMING TO THE EPROM ON THE MB89P857/W857
The MB89P857/W857 are an OTPROM version of the MB89850R series.
1. Features
• 32-Kbyte PROM on chip
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in EPROM mode is diagrammed below.
Address
0000H
Single chip
I/O
EPROM mode
( Corresponding addresses on the EPROM programmer)
0080H
0480H
RAM
Not available
8000H
0000H
PROM
32 KB
EPROM
32 KB
FFFFH
7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P857/W857 functions equivalent to the MBM27C256A. This allows the PROM to
be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used)
by using the dedicated socket adapter.
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0000H to 7FFFH (note that addresses 8000H to FFFFH
while operating as a single chip assign to addresses 0000H to 7FFFH in EPROM mode.)
(3) Program to 0000H to 7FFFH with the EPROM programmer.
13
MB89850R Series
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. Erasure
In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an
ultraviolet light source. A dosage of 10 W-seconds/cm2 is required to completely erase an internal EPROM. This
dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensity
of 12000 µW/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all
filters should be removed from the UV light source prior to erasure.
It is important to note that the internal EPROM and similar devices, will erase with light sources having
wavelengths shorter than 4000 Å. Although erasure time will be much longer than with UV source at 2537 Å,
nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and
exposure to them should be prevented to realize maximum system reliability. If used in such an environment,
the package windows should be covered by an opaque label or substance.
7. EPROM Programmer Socket Adapter
Package
DIP-64P-M01
FPT-64P-M06
FPT-64P-A02
Compatible socket adapter
ROM-64SD-28DP-8L*
ROM-64QF-28DP-8L
ROM-64QF-28DP-8L5
* : Connect the adapter jumper pin to VSS when using.
Inquiry: Sun Hayato Co., Ltd.: Fax 81-3-5396-9106
14
MB89850R Series
■ BLOCK DIAGRAM
X0
X1
Timebase timer
Oscillator
Clock controller
P37/PTO2
P36/PTO1
8-bit PWM timer 2
8-bit PWM timer 1
Reset circuit
(WDT)
RST
P35/SI2
P34/SO2
P33/SCK2
8-bit serial I/O
UART
CMOS I/O port
8
8
P00/AD0
to P07/AD7
P32/SI1
P31/SO1
P30/SCK1
P10/A08
to P17/A15
MOD0
MOD1
External bus
interface
CMOS I/O port
CMOS I/O port
P27/ALE
P26/RD
P47/TRGI
P46/Z
P45/Y
P25/WR
P24/CLK
P23/RDY
P22/HRQ
P21/HAK
P20/BUFC
P44/X
P43/RTO3/W
P42/RTO2/V
P41/RTO1/U
P40/RTO0
6
Timer unit
CMOS output port
(Dead-time timer)
P64/DTTI
4
3
RAM
External interrupt
Input port
P60/INT0
to P62/INT2
F2MC-8L
CPU
P63/INT3/ADST
AVR
AVCC
AVSS
ROM
8
8
Other pins
VCC , VSS × 2
P50/AN0
to P57/AN7
10-bit A/D converter
N-ch open-drain output port
Part number
RAM size
ROM size
MB89855R
MB89W857/P857
512 bytes
16 Kbytes
32 Kbytes
(EPROM)
1 Kbyte
15
MB89850R Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89850R series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located at the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89860/850 series is structured as illustrated below.
• Memory Space
MB89W857/P857
MB89855R
I/O
0000H
0080H
0000H
0080H
I/O
RAM
512 B
RAM
1 KB
0100H
0100H
Register
Register
0200H
0280H
0200H
0480H
External area
External area
8000H
C000H
FFFFH
ROM*
32 KB
ROM*
16 KB
FFFF H
*: The ROM area is an external area depending on the mode.
16
MB89850R Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
Accumulator (A):
A 16-bit register for indicating instruction storage positions
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator
When the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX):
Extra pointer (EP):
Stack pointer (SP):
Program status (PS):
A 16-bit register for index modification
A 16-bit pointer for indicating a memory address
A 16-bit register for indicating a stack area
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bits
PC
: Program counter
: Accumulator
FFFDH
A
T
Indeterminate
: Temporary accumulator Indeterminate
IX
: Index register
: Extra pointer
: Stack pointer
: Program status
Indeterminate
Indeterminate
Indeterminate
EP
SP
PS
I-flag = 0, IL1, 0 = 11
Other bits are indeterminate.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
• Structure of the Program Status Register
15
14
13
12
11
10
9
8
7
6
I
5
4
3
2
Z
1
0
PS
RP
Vacancy Vacancy Vacancy
H
IL1, 0
N
V
C
RP
CCR
17
MB89850R Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
• Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
0
IL0
0
Interrupt level
High-low
High
1
0
1
1
0
2
3
1
1
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
18
MB89850R Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to a total of 32 banks can be used on the MB89850R series. The bank currently in use
is indicated by the register bank pointer (RP).
Note: The number of register banks that can be used varies with the RAM size.
• Register Bank Configuration
This address = 0100H + 8 × (RP)
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
32 banks
Memory area
19
MB89850R Series
■ I/O MAP
Address
00H
Read/write
(R/W)
(W)
Register name
PDR0
Register description
Port 0 data register
01H
DDR0
Port 0 data direction register
Port 1 data register
02H
(R/W)
(W)
PDR1
03H
DDR1
Port 1 data direction register
Port 2 data register
04H
(R/W)
(W)
PDR2
05H
BCTR
External bus pin control register
Vacancy
06H
07H
Vacancy
08H
(R/W)
(W)
STBC
WDTC
TBTC
Standby control register
Watchdog timer control register
Timebase timer control register
Vacancy
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
(R/W)
(R/W)
(W)
PDR3
DDR3
PDR4
DDR4
PDR5
Port 3 data register
Port 3 data direction register
Port 4 data register
(R/W)
(W)
Port 4 data direction register
Port 5 data register
(R/W)
11H
Vacancy
12H
(R)
PDR6
PDR7
PDR8
Port 6 data register
13H
Vacancy
14H
(R/W)
(R/W)
Port 7 data register
15H
Vacancy
16H
Port 8 data register
17H to 1BH
1CH
1DH
1EH
1FH
20H
Vacancy
(R/W)
(W)
CTR1
CMR1
CTR2
CMR2
SMC
PWM control register 1
PWM compare register 1
PWM control register 2
PWM compare register 2
UART serial mode control register
UART serial rate control register
UART serial status/data register
UART serial data register
Serial mode register
Serial data register
(R/W)
(W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
21H
SRC
22H
SSD
23H
SIDR/SODR
SMR
24H
25H
SDR
(Continued)
20
MB89850R Series
(Continued)
Address
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R)
Register name
EIC1
Register description
26H
27H
External interrupt control register 1
EIC2
External interrupt control register 2
A/D converter control register 1
A/D converter control register 2
A/D converter data register (H)
A/D converter data register (L)
Vacancy
28H
ADC1
29H
ADC2
2AH
2BH
2CH
2DH
2EH
2FH
30H
ADDH
(R)
ADDL
(W)
(W)
ZOCTR
CLRBRH
CLRBRL
TCSR
Zero detection output control register
Compare clear buffer register (H)
Compare clear buffer register (L)
Timer control status register
Compare interrupt control register
Timer mode control register
(W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(W)
31H
CICR
32H
TMCR
33H
COER
Compare/port selection register
Compare buffer mode control register
Dead-time timer control register
Dead-time setting register
34H
CMCR
35H
DTCR
36H
DTSR
37H
(R/W)
(W)
OCTBR
OCPBR0H
OCPBR0L
OCPBR1H
OCPBR1L
OCPBR2H
OCPBR2L
OCPBR3H
OCPBR3L
Output control buffer register
Output compare buffer register 0 (H)
Output compare buffer register 0 (L)
Output compare buffer register 1 (H)
Output compare buffer register 1 (L)
Output compare buffer register 2 (H)
Output compare buffer register 2 (L)
Output compare buffer register 3 (H)
Output compare buffer register 3 (L)
Vacancy
38H
39H
(W)
3AH
3BH
3CH
3DH
3EH
3FH
40H to 7BH
7CH
7DH
7EH
7FH
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
ILR1
ILR2
ILR3
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Vacancy
Notes: • Do not use vacancies.
• When a read-modify-write instruction (such as bit set) is used to access a write-only register or a register
containing a write-only bit, a bit designated by the instruction will have a predetermined value. However,
a write-only bit included, if any, in bits not defined by the instruction will cause a malfunction. So no access
to the register should be tried with any read-modefy-write instruction.
21
MB89850R Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Value
Parameter
Symbol
VCC
Unit
Remarks
Min.
Max.
Power supply voltage
VSS – 0.3
VSS – 0.3
VSS – 0.3
VSS + 7.0
V
V
V
*
AVCC
AVR must not exceed
AVCC + 0.3 V.
A/D converter reference input voltage AVR
VSS + 7.0
13.0
MOD1 pins of MB89P857/
W857
Program voltage
VPP
Input voltage
VI
VSS – 0.3
VSS – 0.3
—
VCC + 0.3
VSS + 0.3
20
V
V
Output voltage
VO
IOL
“L” level maximum output current
mA
P00 to P07, P10 to P17,
mA P20 to P27, P30 to P37,
P50 to P57
IOLAV1
IOLAV2
ΣIOLAV1
—
—
—
4
“L” level average output current
15
30
mA P40 to P47
P00 to P07, P10 to P17,
mA P20 to P27, P30 to P37,
P50 to P57
“L” level total average output current
ΣIOLAV2
IOH
—
—
—
50
–20
–4
mA P40 to P47
“H” level maximum output current
“H” level average output current
mA
mA
IOHAV
“H” level total maximum output
current
ΣIOH
—
–20
mA
Power consumption
Operating temperature
Storage temperature
PD
—
300
+85
mW
°C
TA
–40
–55
Tstg
+150
°C
*: Use AVCC and VCC set at the same voltage.
Take care so that AVCC does not exceed VCC, such as when power is turned on.
WARNING: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
22
MB89850R Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Parameter
Symbol
Unit
Remarks
Min.
Max.
Normal operation assurance range*
MB89855R
2.7*
6.0*
V
VCC
AVCC
Power supply voltage
Normal operation assurance range*
MB89P857/W855
2.7*
1.5
5.5*
6.0
V
V
Retains the RAM state in stop mode
A/D converter reference input
voltage
AVR
TA
0.0
AVCC
+85
V
Operating temperature
–40
°C
*: These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1
and “5. A/D Converter Electrical Characteristics.”
Note: Connect the MOD0 and MOD1 pins to VCC or VSS.
6
5.5
Analog accuracy assured in the
VCC = AVCC = 3.5 V to 6.0 V range
5
Operation assurance range
4
3
2
1
1
2
3
4
5
6
7
8
9
10
Clock operating frequency (MHz)
(µs)
4.0 2.0
0.8
0.4
Minimum execution time (instruction cycle)
Note: The shaded area is assured only for the MB89855R.
Figure 1 Operating Voltage vs. Clock Operating Frequency
23
MB89850R Series
3. DC Characteristics
(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
VIH
Pin name
Condition
Unit Remarks
Min.
Typ.
Max.
P00 to P07,
P10 to P17,
P22, P23
0.7 VCC
VCC + 0.3
—
—
—
—
—
V
V
V
V
“H” level input voltage
RST, P30 to P37,
P40 to P47,
P60 to P64
0.8 VCC
VSS – 0.3
VSS – 0.3
VCC + 0.3
0.3 VCC
0.2 VCC
VIHS
—
—
—
P00 to P07,
P10 to P17,
P22, P23
VIL
“L” level input voltage
RST, P30 to P37,
P40 to P47,
P60 to P64
VILS
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47
“H” level output voltage VOH
IOH = –2.0 mA
2.4
—
—
V
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P50 to P57
VOL
IOL = +1.8 mA
IOL = +1.5 mA
—
—
—
—
0.4
1.5
V
V
“L” level output voltage
P40 to P47
VOL2
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P60 to P64,
MOD0, MOD1
Input leackage current
Pull-up resistance
0.0 V < VI < VCC
VI = 0.0 V
ILI1
—
—
±5
µA
Withpull-up
kΩ
RST
RPULL
ICC
25
—
50
15
100
18
resistor
FC = 10 MHz
Normal
operation mode
(External clock)
mA
FC = 10 MHz
Sleep mode
VCC
ICCS
ICCH
—
—
6
8
mA
(External clock)
Power supply current
Stop mode
TA = +25°C
—
10
µA
FC = 10 MHz,
when A/D
AVCC
IA
—
—
6
—
—
µA
conversion is
activated
Other than AVCC,
AVSS, VCC, and VSS
Input capacitance
CIN
f = 1 MHz
10
pF
24
MB89850R Series
4. AC Characteristics
(1) Reset Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
Condition
Unit
Remarks
Min.
Max.
RST “L” pulse width
tZLZH
—
16 tXCYL*
—
ns
* : tXCYL is the oscillation cycle (1/FC) to input to the X0 pin.
t ZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Max.
Parameter
Symbol
tR
Condition
Unit
Remarks
Min.
—
Power supply rising time
Power supply cut-off time
50
—
ms Power-on reset function only
ms Due to repeated operations
—
tOFF
1
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tOFF
tR
2.0 V
0.2 V
0.2 V
0.2 V
V
CC
25
MB89850R Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Clock frequency
Symbol
FC
Pin name
Condition
Unit
Remarks
Min.
1
Max.
10
MHz
ns
X0, X1
Clock cycle time
tXCYL
100
1000
PWH
PWL
—
Input clock pulse width
20
—
—
ns External clock
ns External clock
X0
tCR
tCF
Input clock rising/falling time
10
• X0 and X1 Timing Conditions
tXCYL
PWH
PWL
tCR
tCF
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Clock Conditions
When a crystal
or
When an external clock is used
ceramic resonator is used
X0
X1
X0
X1
Open
(4) Instruction Cycle
Parameter
Symbol
tinst
Value (typical)
Unit
Remarks
Instruction cycle
(minimum execution time)
tinst = 0.4 µs when operating at
FC = 10 MHz
4/FC
µs
26
MB89850R Series
(5) Clock Output Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Cycle time
CLK ↑ → CLK ↓
Symbol
tCYC
tCHCL
Pin name
Condition
Unit
Remarks
Min.
Max.
tXCYL × 2 at 10 MHz
oscillation
200
—
ns
ns
Load
condition:
50 pF
CLK
Approx. tCYC/2 at
10 MHz oscillation
30
100
t CYC
t CHCL
2.4 V
2.4 V
CLK
0.8 V
27
MB89850R Series
(6) Bus Read Timing
(VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value (10 MHz)
Parameter
Symbol
Pin name
Condition
Unit Remarks
Min.
1/4 tinst * – 64 ns
1/2 tinst * – 20 ns
—
Max.
—
Valid address → RD ↓
RD, A15 to A08,
AD7 to AD0
tAVRL
tRLRH
tAVDV
ns
time
RD pulse width
RD
—
ns
Valid address → data
read time
AD7 to AD0, A15
to A08
1/2 tinst*
ns No wait
RD, AD7 to AD0
AD7 to AD0, RD
RD, ALE
1/2 tinst * – 80 ns
RD ↓ → data read time tRLDV
RD ↑ → data hold time tRHDX
—
ns No wait
0
—
—
ns
ns
Load
condition:
50 pF
RD ↑ → ALE ↑ time
tRHLH
1/4 tinst * – 40 ns
RD ↑ → address invalid
time
RD, A15 to A08
1/4 tinst * – 40 ns
tRHAX
—
ns
1/4 tinst * – 60 ns
RD ↓ → CLK ↑ time
CLK ↓ → RD ↑ time
RD ↓ → BUFC ↓ time
tRLCH
tCLRH
tRLBL
—
—
—
ns
ns
ns
RD, CLK
0
RD, BUFC
–5
BUFC ↑ → valid
address time
A15 to A08, AD7
to AD0, BUFC
tBHAV
5
—
ns
* : For information on tinst, see “(4) Instruction Cycle.”
2.4 V
CLK
0.8 V
tRHLH
ALE
0.8 V
0.7 VCC
2.4 V
0.7 VCC
0.3 VCC
2.4 V
0.8 V
AD
0.8 V
0.3 VCC
tAVDV
tRHDX
2.4 V
2.4 V
tCLRH
0.8 V
2.4 V
0.8 V
A
tRLCH
0.8 V
tAVRL
tRLDV
tRHAX
tRLRH
2.4 V
RD
0.8 V
tRLBL
tBHAV
2.4 V
BUFC
0.8 V
28
MB89850R Series
(7) Bus Write Timing
Parameter
(VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value (10 MHz)
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
Valid address → ALE ↓ time tAVLL
1/4 tinst *1 – 64 ns
—
ns
ns
AD7 to AD0,
ALE, A15 to A08
ALE ↓ time → address
tLLAX
5
—
invalid time
Valid address → WR ↓ time
WR pulse width
tAVWL
tWLWH
tDVWH
WR, ALE
1/4 tinst *1 – 60 ns
1/2 tinst *1 – 20 ns
1/2 tinst *1 – 60 ns
1/4 tinst *1 – 40 ns
1/4 tinst *1 – 40 ns
1/4 tinst *1 – 40 ns
1/4 tinst *1 – 60 ns
0
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WR
AD7 to AD0, WR
WR, A15 to A08
AD7 to AD0, WR
WR, ALE
Write data → WR ↑ time
Load
condition:
50 pF
WR ↑ → address invalid time tWHAX
WR ↑ → data hold time
WR ↑ → ALE ↑ time
WR ↓ → CLK ↑ time
CLK ↓ → WR ↑ time
ALE pulse width
tWHDX
tWHLH
tWLCH
tCLWH
tLHLL
WR, CLK
tXCYL – 35 ns*2
tXCYL – 35 ns*2
ALE
ALE ↓ → CLK ↑ time
tLLCH
ALE, CLK
*1: For information on tinst, see “(4) Instruction Cycle.”
*2: These characteristics are also applicable to the bus read timing.
2.4 V
CLK
0.8 V
tLHLL
tLLCH
t WHLH
2.4 V
ALE
AD
A
0.8 V
0.8 V
tAVLL
tLLAX
2.4 V
2.4 V 2.4 V
0.8 V 0.8 V
2.4 V
0.8 V
0.8 V
tDVWH
tWHDX
2.4 V
tCLWH
2.4 V
0.8 V
tWLCH
0.8 V
tAVWL
tWHAX
tWLWH
2.4 V
WR
0.8 V
29
MB89850R Series
(8) Ready Input Timing
(VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
Pin name
Condition
Unit Remarks
Min.
60
0
Max.
—
RDY valid → CLK ↑ time
CLK ↑ → RDY invalid time
tYVCH
tCHYX
ns
ns
*
*
RDY,
CLK
Load condition:
50 pF
—
* : These characteristics are also applicable to the read cycle.
2.4 V
2.4 V
CLK
ALE
AD
A
Address
Data
WR
t YVCH t CHYX
0.7 VCC
0.7 VCC
RDY
0.3 VCC
0.3 VCC
t YVCH t CHYX
Note: The bus cycle is also extended in the read cycle in the same manner.
30
MB89850R Series
(9) UART and Serial I/O Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol Pin name
Condition
Unit Remarks
Min.
Max.
Serial clock cycle time
tSCYC
tSLOV
SCK1,SCK2
2 tinst*
—
µs
SCK1 ↓ → SO1 time
SCK2 ↓ → SO2 time
SCK1, SO1
SCK2, SO2
Internal shift
clock mode
Load
condition:
50 pF
–200
200
—
ns
Valid SI1 → SCK1 ↑ Valid
SI2 → SCK2 ↑
SI1, SCK1
SI2, SCK2
tIVSH
1/2 tinst*
1/2 tinst*
µs
µs
SCK1 ↑ → valid SI1 hold time
SCK2 ↑ → valid SI2 hold time
SCK1, SI1
SCK2, SI2
tSHIX
—
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
1 tinst*
1 tinst*
—
—
µs
µs
SCK1,
SCK2
Externalshift
clock mode
Load
condition:
50 pF
SCK1 ↓ → SO1 time
SCK2 ↓ → SO2 time
SCK1, SO1
SCK2, SO2
tSLOV
tIVSH
tSHIX
0
200
—
ns
µs
µs
Valid SI1 → SCK1 ↑ Valid
SI2 → SCK2 ↑
SI1, SCK1
SI2, SCK2
1/2 tinst*
1/2 tinst*
SCK1 ↑ → valid SI1 hold time
SCK2 ↑ → valid SI2 hold time
SCK1, SI1
SCK2, SI2
—
* : For information on tinst, see “(4) Instruction Cycle.”
31
MB89850R Series
• Internal Shift Clock Mode
tSCYC
SCK1
SCK2
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
SO1
SO2
tIVSH
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.2 VCC
SI1
SI2
• External Shift Clock Mode
t SLSH
t SHSL
SCK1
SCK2
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
t SLOV
2.4 V
SO1
SO2
0.8 V
tIVSH
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.2 VCC
SI1
SI2
32
MB89850R Series
(10) Peripheral Input Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
Peripheral input “H”
pulse width 1
tILIH1
tIHIL1
2 tinst*
—
µs
µs
TRGI, DTTI,
ADST,
INT0 to INT3
Load
condition:
50 pF
Peripheral input “L”
pulse width 1
2 tinst*
—
* : For information on tinst, see “(4) Instruction Cycle.”
TRGI
DTTI
tIHIL1
tILIH1
ADST
INT0 to INT3
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +3.5 V to +6.0 V, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Remark
Parameter
Resolution
Symbol Pin name Condition
Unit
s
Min.
—
Typ.
—
Max.
10
bit
Linearity error
—
—
±2.0
±1.5
±3.0
LSB
LSB
LSB
LSB
—
Differential linearity error
Total error
—
—
AVCC = VCC
—
—
Zero transition voltage
Full-scale transition voltage
Interchannel disparity
A/D mode conversion time
Analog port input current
Analog input voltage
Reference voltage
AVSS – 1.5 AVSS + 0.5 AVSS + 2.5
VOT
AN0 to
AN7
VFST
AVR – 3.5 AVR – 1.5 AVR + 0.5 LSB
—
—
—
0
—
33 tinst*
—
4
LSB
µs
µA
V
—
—
—
—
—
—
—
—
IAIN
10
AN0 to
AN7
—
AVR
AVCC
0
—
V
AVR
Reference voltage supply
current
AVR = 5.0 V
IR
—
200
—
µA
* : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
33
MB89850R Series
6. A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter
• Linearity error
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1111” ↔´“11 1111 1110”) from actual conversion characteristics
• Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error
The total error indicates the difference between the actual value and theoretical value. This error is caused by
the zero transition error, full-scale transition error, linearity error, quantization, and noise.
Theoretical I/O value
VFST
Total error
3FF
3FE
3FD
3FF
3FE
3FD
Actual conversion
value
1.5 LSB
(1 LSB × N + 0.5 LSB)
004
003
002
001
004
003
002
001
VNT
VOT
Actual conversion
value
1 LSB
Theoretical value
0.5 LSB
AVSS
AVR
AVSS
AVR
Analog input
Analog input
VFST – VOT
VNT – (1 LSB × N + 0.5 LSB)
1 LSB =
(V)
Total error of digital output “N” =
1022
1 LSB
(Continued)
34
MB89850R Series
(Continued)
Zero transition error
Full-scale transition error
Theoretical value
004
003
002
001
Actual conversion
value
3FF
3FE
3FD
3FC
Actual conversion
value
VFST
(Measured value)
Actual conversion
value
Actual conversion
value
VOT (Measured value)
Analog input
AVSS
AVR
Analog input
Linearity error
Differential linearity error
Theoretical value
3FF
3FE
3FD
Actual conversion
value
N+1
N
(1 LSB
× N + VOT)
Actual conversion
value
V(N + 1)T
VFST
(Measured
value)
VNT
004
003
002
001
N – 1
N – 2
VNT
Actual conversion
value
Actual conversion
value
Theoretical value
VOT (Measured value)
Analog input
AVSS
AVR
Analog input
VNT – (1 LSB × N + VOT)
V(N + 1)T – VNT
Linearity error of digital output “N” =
Differential linearity error of digital output “N” =
– 1
1 LSB
1 LSB
35
MB89850R Series
7. Notes on Using A/D Converter
• Input impedance of the analog input pins
The A/D converter used for the MB89860/850 series contains a sample hold circuit as illustrated below to
fetch analog input voltage into the sample hold capacitor for fifteen instruction cycles after activation A/D
conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low (below 10 kΩ).
Note that if the impedance connot be kept low, it is recommended to connect an external capacitor of about
0.1 µF for the analog input pin.
• Analog Input Equivalent Circuit
Sample hold circuit
.
C = 64 pF
.
Anlog input pin
Comparator
If the analog input
impedance is higher
than 10 kΩ, it is
recommended to
connect an external
capacitor of approx.
0.1 µF.
.
R = 3 kΩ
.
Close for 15 instruction cycles
after activating A/D conversion.
Analog channel selector
• Error
The smaller the | AVR – AVSS |, the greater the error would become relatively.
36
MB89850R Series
■ EXAMPLE CHARACTERISTICS
(1) “L” Level Output Voltage (P00 to P07, P10 to
P17, P20 to P27, P30 to P37, and P50 to P57)
(2) “L” Level Output Voltage (P40 to P47)
VOL vs. IOL
VOL vs. IOL
VOL (V)
VCC = 3.0 V
VOL (mV)
600
VCC = 4.0 V
TA = +25°C
TA = +25°C
0.5
0.4
0.3
0.2
0.1
500
VCC = 5.0 V
VCC = 6.0 V
VCC = 3.0 V
400
VCC = 4.0 V
300
200
100
0
VCC = 5.0 V
VCC = 6.0 V
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
0 1 2 3 4 5 6 7 8 9 1011121314151617181920
IOL (mA)
(4) Pull-up Resistance
(3) “H” Level Output Voltage (P00 to P07, P10 to
P17, P20 to P27, P30 to P37, and P40 to P47)
RPULL vs. VCC
RPULL (kΩ)
1000
VCC – VOH vs. IOH
VCC – VOH (V)
1.0
TA = +25°C
TA = +25°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VCC = 2.5 V
VCC = 3.0 V
100
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.0
–0.5 –1.0 –1.5 –2.0 –2.5 –3.0
IOH (mA)
10
1
2
3
4
5
6
VCC (V)
37
MB89850R Series
(5) “H” Level Input Voltage/“L” Level Input
Voltage (CMOS Input)
(6) “H” Level Input Voltage/“L” level Input
Voltage (Hysteresis Input)
VIN vs. VCC
VIN (V)
5.0
VIN vs. VCC
TA = +25°C
VIN (V)
5.0
4.5
TA = +25°C
4.0
4.5
3.5
VIHS
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
2.5
VILS
2.0
1.5
1.0
0.5
0
1
2
3
4
5
6
7
VCC (V)
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
1
2
3
4
5
6
7
VCC (V)
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
(7) Operating Supply Current vs. Frequency
(8) Operating Supply Current vs. VCC
ICC vs. FC
ICC vs. VCC
ICC (mA)
10
ICC (mA)
25
TA = +25°C
TA = +25°C
8
20
VCC = 5.0 V
6
15
FC = 10 MHz
FC = 8 MHz
FC = 6 MHz
FC = 4 MHz
VCC = 3.5 V
VCC = 3.0 V
4
10
5
2
0
0
2
4
6
8
10
FC (MHz)
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VCC (V)
38
MB89850R Series
(9) Sleep Power Supply Current vs. Frequency
(10) Sleep Power Supply Current vs. VCC
ICCS vs. FC
ICCS vs. VCC
ICCS (mA)
10
ICCS (mA)
10
TA = +25°C
TA = +25°C
8
8
6
4
2
0
6
FC = 10 MHz
VCC = 5.0 V
FC = 8 MHz
FC = 6 MHz
4
FC = 4 MHz
VCC = 3.5 V
2
VCC = 3.0 V
0
2
4
6
8
10
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VCC (V)
FC (MHz)
39
MB89850R Series
■ INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups:
• Transfer
• Arithmetic operation
• Branch
• Others
Table 1 lists symbols used for notation of instructions.
Table 1 Instruction Symbols
Symbol
dir
Meaning
Direct address (8 bits)
off
Offset (8 bits)
ext
#vct
#d8
#d16
dir: b
rel
Extended address (16 bits)
Vector table number (3 bits)
Immediate data (8 bits)
Immediate data (16 bits)
Bit direct address (8:3 bits)
Branch relative address (8 bits)
Register indirect (Example: @A, @IX, @EP)
@
A
AH
AL
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of accumulator A (8 bits)
Lower 8 bits of accumulator A (8 bits)
T
TH
TL
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of temporary accumulator T (8 bits)
Lower 8 bits of temporary accumulator T (8 bits)
Index register IX (16 bits)
IX
EP
PC
SP
PS
dr
CCR
RP
Ri
Extra pointer EP (16 bits)
Program counter PC (16 bits)
Stack pointer SP (16 bits)
Program status PS (16 bits)
Accumulator A or index register IX (16 bits)
Condition code register CCR (8 bits)
Register bank pointer RP (5 bits)
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
×
Indicates that the contents of × is the target of accessing.
( × )
(( × ))
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic: Assembler notation of an instruction
~:
#:
The number of instructions
The number of bytes
Operation: Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH prior to the instruction executed.
• 00 becomes 00.
N, Z, V, C:
OP code:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
40
MB89850R Series
Table 2 Transfer Instructions (48 instructions)
Mnemonic
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
~
#
Operation
TL
TH AH NZVC OP code
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
(dir) ← (A)
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
45
46
61
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
47
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
48 to 4F
04
05
06
60
92
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
07
(A) ← (Ri)
(dir) ← d8
08 to 0F
85
86
87
88 to 8F
D5
( (IX) +off ) ← d8
( (EP) ) ← d8
–
–
–
–
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
–
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
D4
D7
E3
E4
C5
C6
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
+ + + +
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
SETB dir: b
CLRB dir: b
XCH A,T
A8 to AF
A0 to A7
42
AL
AL
–
–
–
–
AH
–
–
–
XCHW A,T
43
F7
F6
F5
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
–
–
F0
Note During byte transfer to A, T ← A is restricted to low bytes.
Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
41
MB89850R Series
Table 3 Arithmetic Operation Instructions (62 instructions)
Mnemonic
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
~
#
Operation
(A) ← (A) + (Ri) + C
TL
TH AH NZVC OP code
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + –
– – – –
– – – –
+ + – –
+ + + –
– – – –
– – – –
+ + – –
– – – –
– – – –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + – +
28 to 2F
24
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
–
D2
D0
01
11
63
73
53
12
dH
dH
00
dH
dH
dH
–
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) (T)
(A) ← (A) (T)
(A) ← (A) (T)
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
(TL) − (AL)
(T) − (A)
–
–
13
03
→
→
C
A
A
←
←
C
ROLC A
2
1
–
–
–
+ + – +
02
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
14
15
17
16
(A) − (Ri)
18 to 1F
84
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
DAS
XOR A
94
52
54
55
57
56
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
58 to 5F
62
AND A,#d8
AND A,dir
64
65
(A) ← (AL) (dir)
(Continued)
42
MB89850R Series
(Continued)
Mnemonic
~
#
Operation
(A) ← (AL) ( (EP) )
TL
TH AH NZVC OP code
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + + +
+ + + +
– – – –
– – – –
67
66
68 to 6F
72
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(dir) – d8
74
75
77
76
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
78 to 7F
95
97
96
98 to 9F
C1
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
DECW SP
D1
Table 4 Branch Instructions (17 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V N = 1 then PC ← PC + rel
If V N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– + – –
– + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
Restore
FD
FC
F9
F8
FB
FA
FF
FE
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
RETI
–
Table 5 Other Instructions (9 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – R
– – – S
– – – –
– – – –
40
50
41
51
00
81
91
80
90
CLRI
SETI
43
MB89850R Series
■ INSTRUCTION MAP
44
MB89850R Series
■ MASK OPTIONS (MB89855R)
Option type
Option selection
Remarks
0: Without power-on reset
1: With power-on reset
Power-on reset
—
Selects the initial value of the OSCS bit
in the STBC register during power-on
reset.
Initial value of oscillation
stabilization delay time
0: 218/FC (s) (Crystal oscillator)
1: 214/FC (s) (Ceramic oscillator)
0: Without reset output
1: With reset output
Reset pin output
—
• Can be set per pin.
Pull-up resistor at port pin
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P64
• P00 to P07, P10 to P17, and P20 to
P27 with a pull-up resistor can be set
only for single-chip mode.
1: Without pull-up resistor
0: With pull-up resistor
■ STANDARD OPTION LIST
Part number
Parameter
MB89P857/W857
Available
Power-on reset
Initial value of oscillation
stabilization delay time
218/FC (s)
Output at reset pin
Available
Pull-up resistor at port pin
Not available
■ ORDERING INFORMATION
Part number
Package
Remarks
MB89855RP-SH
MB89P857P-SH
64-pin Plastic SH-DIP
(DIP-64P-M01)
64-pin Ceramic SH-DIP
(DIP-64C-A06)
MB89W857C-SH
ES level only
ES level only
64-pin Ceramic QFP
(FPT-64C-A02)
MB89W857CF-ES-BND
45
MB89850R Series
■ PACKAGE DIMENSIONS
64-pin Plastic SH-DIP
(DIP-64P-M01)
58.00+–00..5252
+.008
2.283–.022
INDEX-1
INDEX-2
17.00±0.25
(.669±.010)
5.65(.222)MAX
3.00(.118)MIN
0.25±0.05
(.010±.002)
1.00+–00.50
.039+–0.020
0.45±0.10
(.018±.004)
0.51(.020)MIN
19.05(.750)
TYP
15°MAX
1.778±0.18
(.070±.007)
1.778(.070)
MAX
55.118(2.170)REF
Dimensions in mm (inches)
C
1994 FUJITSU LIMITED D64001S-3C-4
64-pin Ceramic SH-DIP
(DIP-64C-A06)
56.90±0.56
(2.240±.022)
8.89(.350) DIA
TYP
R1.27(.050)
REF
18.75±0.25
(.738±.010)
INDEX AREA
1.27±0.25
(.050±.010)
5.84(.230)MAX
3.40±0.36
0.25±0.05
(.010±.004)
+0.13
(.134±.014)
1.778±0.180
(.070±.007)
0.90±0.10
(.0355±.0040)
0.46–0.08
19.05±0.25
(.750±.010)
.018+–..000035
0°~9°
1.45(.057)
MAX
55.118(2.170)REF
Dimensions in mm (inches)
C
1994 FUJITSU LIMITED D64006SC-1-2
46
MB89850R Series
64-pin Plastic QFP
(FPT-64P-M06)
24.70±0.40(.972±.016)
20.00±0.20(.787±.008)
3.35(.132)MAX
51
33
0.05(.002)MIN
(STAND OFF)
52
32
14.00±0.20 18.70±0.40
(.551±.008) (.736±.016)
12.00(.472)
REF
16.30±0.40
(.642±.016)
INDEX
64
20
"A"
1
19
LEAD No.
0.15±0.05(.006±.002)
Details of "B" part
1.00(.0394)
TYP
0.40±0.10
(.016±.004)
M
0.20(.008)
Details of "A" part
0.25(.010)
"B"
0.30(.012)
0.18(.007)MAX
0.10(.004)
18.00(.709)REF
22.30±0.40(.878±.016)
0
10°
1.20±0.20
(.047±.008)
0.63(.025)MAX
Dimensions in mm (inches)
C
1994 FUJITSU LIMITED F64013S-3C-2
64-pin Ceramic QFP
(FPT-64C-A02)
0.51(.020) TYP
17.91(.705)
TYP
12.01(.473)
REF
16.31(.642)
TYP
9.40(.370)TYP
16.00(.630)
14.00±0.25
(.551±.010)
TYP
INDEX AREA
1.00±0.10
(.0394±.0040)
0.40±0.08
(.016±.003)
1.00±0.10
(.0394±.0040)
0.15±0.05
(.006±.002)
18.00(.709) REF
1.60(.063) TYP
20.00±0.25
(.787±.010)
4.70(.185)MAX
23.90(.941) TYP
22.00(.866) TYP
22.30(.878) TYP
0.80(.0315) TYP
Dimensions in mm (inches)
C
1994 FUJITSU LIMITED F64012SC-2-2
47
MB89850R Series
FUJITSU LIMITED
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FUJITSU LIMITED
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Electronic Devices
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F9609
FUJITSU LIMITED Printed in Japan
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