MB90233PFV-XXX [FUJITSU]
Microcontroller, 16-Bit, MROM, F2MC-16F CPU, 16MHz, CMOS, PQFP100, PLASTIC, LQFP-100;
| 型号： | MB90233PFV-XXX |
| 厂家： | 
FUJITSU |
| 描述： | Microcontroller, 16-Bit, MROM, F2MC-16F CPU, 16MHz, CMOS, PQFP100, PLASTIC, LQFP-100 微控制器 |
| 文件： | 总83页 (文件大小：1396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13504-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16F MB90230 Series
MB90233/234/P234/W234
■ DESCRIPTION
The MB90230 series is a member of general-purpose, 16-bit microcontrollers designed for those applications which
require high-speed realtimeprocessing, proving to be suitable for various industrial machines, camera and video
devices, OA equipment, and for process control. The CPU used in this series is the F2MC*-16F. The instruction
set for the F2MC-16F CPU core is designed to be optimized for controller applications while inheriting the AT
architecture of the F2MC-16/16H series, allowing a wide range of control tasks to be processed efficiently at high
speed.
The peripheral resources integrated in the MB90230 series include: the UART (clock asynchronous/synchronous
transfer) × 1 channel, the extended serial I/O interface × 1 channel, the A/D converter (8/10-bit precision) × 8
channels, the D/A converter (8-bit precision) × 2 channels, the level comparator × 1 channel, the external interrupt
input × 4 lines, the 8-bit PPG timer (PWM/single-shot function) × 1 channel, the 8-bit PWM controller × 6 channels,
the 16-bit free run timer × 1 channel, the input capture unit × 4 channels, the output compare unit × 6 channels,
and the serial E2PROM interface.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
F2MC-16F CPU block
• Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz)
• Instruction set optimized for controllers
Various data types supported (bit, byte, word, and long-word)
Extended addressing modes: 23 types
High coding efficiency
Higher-precision operation enhanced by a 32-bit accumulator
Signed multiplication and division instructions
(Continued)
■ PACKAGE
100-pin Plastic LQFP
100-pin Ceramic LQFP
(FPT-100P-M05)
(FPT-100C-C01)
MB90230 Series
(Continued)
• Enhanced instructions applicable to high-level language (C) and multitasking
System stack pointer
Enhanced pointer-indirect instructions
Barrel shift instructions
• Increased execution speed: 8-byte instruction queue
• 8-level, 32-factor powerful interrupt service functions
• Automatic transfer function independent of the CPU (EI2OS)
• General-purpose ports: Up to 84 lines
Ports with input pull-up resistor available: 24 lines
Ports with output open-drain available: 9 lines
Peripheral blocks
• ROM:48 Kbytes (MB90233)
96 Kbytes (MB90234)
EPROM: 96 Kbytes (MB90W234)
One-time PROM: 96 Kbytes (MB90P234)
• RAM: 2 Kbytes (MB90233)
3 Kbytes (MB90234/W234/P234)
• PWM control circuit: (simple 8 bits): 6 channels
• Serial interface
UART: 1 channel
Extended serial I/O interface
Switchable I/O port: 1 channel
Communication prescaler (Source clock generator for the UART, serial I/O interface, CKOT, and level
comparator): 1 channel
• Serial E2PROM interface: 1 channel
• A/D converter with 8/10-bit resolution: input 8 channels
• Level comparator: 1 channel
4-bit D/A converter integrated
• D/A converter with 8-bit resolution: 2 channels
8-bit PPG timer: 1 channel
• Input/output timer
16-bit free run timer: 1 channel
16-bit output compare unit: 6 channels
16-bit input capture unit: 4 channels
• 18-bit timebase timer
• Watchdog timer function
• Standby modes
Sleep mode
Stop mode
2
MB90230 Series
■ PRODUCT LINEUP
Part number
MB90233
NB90234
MB90P234
MB90W234
MB90V230
Parameter
Classification
One-time PROM
model
Evaluation
model
Mask ROM products
EPROM model
ROM size
48 Kbytes
2 Kbytes
96 Kbytes
3 Kbytes
96 Kbytes
3 Kbytes
96 Kbytes
3 Kbytes
—
RAM size
4 Kbytes
CPU functions
Number of instructions: 420
Instruction bit length: 8 or 16 bits
Instruction length: 1 to 7 bytes
Data bit length: 1, 4, 8, 16, or 32 bits
Minimum execution time: 62.5 ns at 16 MHz (internal)
Ports
Up to 84 lines
I/O ports (CMOS): 51
I/O ports (CMOS) with pull-up resistor available: 24
I/O ports (open-drain): 9
UART
Number of channels: 1 (switchable I/O)
Clock synchronous communication (2404 to 38460 bps, full-duplex double buffering)
Clock asynchronous communication (500K to 5M bps, full-duplex double buffering)
Serial interface
A/D converter
Number of channels: 1
Internal or external clock mode
Clock synchronous transfer (62.5 kHz to 1 MHz, “LSB first” or “MSB first” transfer)
Resolution: 10 or 8 bits, Number of input lines: 4
Single conversion mode (conversion for a specified input channel)
Scan conversion mode (continuous conversion for specified consecutive channels)
Continuous conversion mode (repeated conversion for a specified channel)
Stop conversion mode (periodical conversion)
D/A converter
Resolution: 8 bits, Number of output pins: 2
Level
comparator
Comparison to internal D/A converter (4-bit resolution)
PWM
Number of channels: 6
8-bit PWM control circuit (operation of 1×φ, 2×φ, 16×φ, 32×φ)
PPG timer
Number of channels: 1 channel with 8-bit resolution
PWM function: Continuous output of pulse synchronous to trigger
Single-shot function: Output of single pulse by trigger
Serial E2PROM
interface
Number of channels: 1
Instruction code (NS type)
Variable address length: 8 to 11 bits (with address increment function)
Variable data length: 8 or 16 bits
Timer
Number of channels: 6
16-bit reload timer operation (operation clock cycle of 0.25 µs to 1.05 s)
Free run timer
Number of channels: 1
16-bit input capture unit: 4 channels
16-bit output compare unit: 6 channels
Externalinterrupt
input
Number of input pins: 4
Standby mode
Package
Stop mode and sleep mode
FPT-100P-M05
FPT-100C-C01
PGA256-A02
3
MB90230 Series
■ PIN ASSIGNMENT
(TOP VIEW)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RST
P22/A02
P23/A03
P24/A04
P25/A05
P26/A06
P27/A07
P30/A08
P31/A09
VSS
P32/A10
P33/A11
P34/A12
P35/A13
P36/A14
P37/A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P54/WRH
P53/HRQ
P52/HAK
P51/RDY
P50/CLK
PA5/SCK2
PA4/SOT2
PA3/SIN2
PA2/SCK1
PA1/SOT1
PA0/SIN1
P96/SCK0
P95/SOT0
P94/SIN0
P93/IN3/CKOT
P92/IN2
PWM0/P40/A16
PWM1/P41/A17
PWM2/P42/A18
PWM3/P43/A19
PWM4/P44/A20
VCC
PWM5/P45/A21
TRG/P46/A22
PPG/P47/A23
ATG/P70
P91/IN1
P90/IN0
P87/OUT5
P86/OUT4
P85/OUT3
P84/OUT2
P83/OUT1/INT3
P82/OUT0/INT2
(FPT-100P-M05)
(FPT-100C-C01)
4
MB90230 Series
■ PIN DESCRIPTION
Circuit
type
Pin no.
Pin name
Function
80
81
X0
X1
VCC
A
Oscillator pins
82
—
G
Power supply pin
83 to 90
P00 to P07
General-purpose I/O port
An input pull-up resistor can be added to the port by setting the
pull-up resistor setting register.
These pins serve as D00 to D07 pins in bus modes other than the
single-chip mode.
D00 to D07
P10 to P17
I/O pins for the lower eight bits of the external data bus.
These pins are enabled in an external-bus enabled mode.
91 to 98
G
General-purpose I/O port
An input pull-up resistor can be added to the port by setting the pull-up
resistor setting register.
These pins are enabled in the single-chip mode with the external-bus
enabled and the 8-bit data bus specified.
D08 to D15
P20 to P27
I/O pins for the upper eight bits of the external data bus
These pins are enabled in an external-bus enabled mode with the 16-
bit data bus specified.
99, 100
1 to 6
G
E
General-purpose I/O port
An input pull-up resistor can be added to the port by setting the
pull-up resistor setting register.
These pins are enabled in the single-chip mode.
A00 to A07
P30, P31
I/O pins for the lower eight bits of the external data bus
These pins are enabled in an external-bus enabled mode.
7, 8
General-purpose I/O port
This port is enabled in the single-chip mode or when the middle
address control register setting is “port.”
A08, A09
I/O pins for the middle eight bits of the external data bus
These pins are enabled in an external-bus enabled mode when the
middle address control register setting is “address.”
9
VSS
—
E
Power supply pin
10 to 15
P32 to P37
General-purpose I/O port
This port is enabled in the single-chip mode or when the middle
address control register setting is “port.”
A10 to A15
I/O pins for the middle eight bits of the external data bus
These pins are enabled in an external-bus enabled mode when the
middle address control register setting is “address.”
(Continued)
5
MB90230 Series
Circuit
type
Pin no.
Pin name
P40
Function
16
E
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A16
Output pin for external address A16
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM0
P41
This pin serves as the output pin for 8-bit PWM0
The pin is enabled for output by the control status register.
17
18
19
20
21
E
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A17
Output pin for external address A17
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM1
P42
This pin serves as the output pin for 8-bit PWM1.
The pin is enabled for output by the control status register.
E
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A18
Output pin for external address A18
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM2
P43
This pin serves as the output pin for 8-bit PWM2.
This pin is enabled for output by the control status register.
E
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A19
Output pin for external address A19
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM3
P44
This pin serves as the output pin for 8-bit PWM3.
This pin is enabled for output by the control status register.
E
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A20
Output pin for external address A20
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM4
VCC
This pin serves as the output pin for 8-bit PWM4.
The pin is enabled for output by the control status register.
—
Power supply pin
(Continued)
6
MB90230 Series
Circuit
type
Pin no.
Pin name
P45
Function
22
E
L*1
E
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A21
Output pin for external address A21
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM5
P46
This pin serves as the output pin for 8-bit PWM5.
The pin is enabled for output by the control status register.
23
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A22
Output pin for external address A22
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
TRG
P47
This pin serves as the external trigger pin for the 8-bit PPG timer
The pin is enabled for triggering by the control status register.
24
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A23
Output pin for external address A23
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PPG
This pin serves as the output pin for the 8-bit PPG timer.
The pin is enabled for output by the control status register.
L*1
F
25
26
27
28
29
P70
ATG
General-purpose I/O port
External trigger input pin for the A/D converter
This pin functions when enabled by the control status register.
P71
EDI
General-purpose I/O port
Data input pin for the serial EEPROM interface
This pin functions when enabled by the control status register.
P72
E
General-purpose I/O port
EDO
Data output pin for the serial EEPROM interface
This pin functions when enabled by the control status register.
P73
E
General-purpose I/O port
ESK
Clock output pin for the serial EEPROM interface
This pin functions when enabled by the control status register.
P74
E
General-purpose I/O port
ECS
Chip select signal output pin for the serial EEPROM interface
This pin functions when enabled by the control status register.
(Continued)
7
MB90230 Series
Circuit
type
Pin no.
Pin name
P75, P76
Function
30, 31
K
General-purpose I/O port
DA0
DA1
This pin serves as the D/A converter output pin.
The pin functions when enabled by the control status register.
32
33
AVCC
—
—
—
—
J
A/D converter power supply pin
AVRH
“H” reference power supply pin for the A/D converter
“L” reference power supply pin for the A/D converter
A/D converter power pin (GND)
34
AVRL
35
AVSS
36 to 39
P60 to P63
General-purpose I/O port
This port is enabled when the analog input enable register setting is
“port.”
AN0 to AN3
A/D converter analog input pins
These pins are enabled when the analog input enable register setting
is “analog input.”
40
VSS
—
J
Power pin (GND)
41 to 43
P64 to P66
General-purpose I/O port
This port is enabled when the analog input enable register setting is
“port.”
AN4 to AN6
P67
A/D converter analog input pins
These pins are enabled when the analog input enable register setting
is “analog input.”
44
J
General-purpose I/O port
This port is enabled when the analog input enable register setting is
“port.”
AN7
A/D converter analog input pin
This pin is enabled when the analog input enable register setting is
“analog input.”
CMP
P80
Comparator input pin
L*2
45
46
General-purpose I/O port
This port is always enabled.
INT0
External interrupt request input 0
Since this pin serves for interrupt request as required when external
interrupt is enabled, other outputs must be off unless used
intentionally.
L*2
P81
General-purpose I/O port
This port is always enabled.
INT1
External interrupt request input 1
Since this pin serves for interrupt request as required when external
interrupt is enabled, other outputs must be off unless used
intentionally.
47
48
MD0
MD1
C
C
Mode pin
This pin must be fixed to VCC or VSS.
Mode pin
This pin must be fixed to VCC or VSS.
(Continued)
8
MB90230 Series
Circuit
type
Pin no.
Pin name
MD2
Function
49
C
Mode pin
This pin must be fixed to VSS.
50
HST
D
L*2
Hardware standby input pin
General-purpose I/O port
Output compare output pins
51, 52
P82, P83
OUT0,
OUT1
These pins function when enabled by the control status register.
INT2,
INT3
External interrupt request inputs 2 and 3.
Since these pins serve for interrupt request as required when external
interrupt is enabled, other outputs must be off unless used
intentionally.
53 to 56
57 to 59
60
P84 to P87
OUT2 to OUT5
P90 to P92
IN0 to IN2
P93
E
General-purpose I/O port
This pin is always enabled.
Output compare output pins
These pins function when enabled by the control status register.
L*1
L*1
General-purpose I/O port
This port is always enabled.
Input capture edge input pins
These pins function when enabled by the control status register.
General-purpose I/O port
This port is always enabled.
IN3
Input capture edge input pin
This pin functions when enabled by the control status register.
CKOT
Prescaler output pin
This pin functions when enabled by the control status register.
61
62
63
P94
I
H
I
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
SIN0
P95
Serial data input pin for the UART
This pin functions when enabled by the control status register.
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
SOT0
P96
Serial data output pin for the UART
This pin functions when enabled by the control status register.
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
SCK0
UART clock output pin
This pin functions when enabled by the control status register.
(Continued)
9
MB90230 Series
Circuit
type
Pin no.
Pin name
PA0
Function
64
I
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
SIN1
PA1
Serial data input pin for the extended serial I/O interface
This pin functions when enabled by the control status register and by
the serial port switching register.
65
H
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
SOT1
PA2
Serial data output pin for the extended serial I/O interface
This pin functions when enabled by the control status register and by
the serial port switching register.
66
67
68
I
I
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
SCK1
PA3
Clock output pin for the extended serial I/O interface
This pin functions when enabled by the control status register and by
the serial port switching register.
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
SIN2
PA4
Serial data input pin for the extended serial I/O interface
This pin functions when enabled by the control status register and by
the serial port switching register.
H
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
SOT2
PA5
Serial data output pin for the extended serial I/O interface
This pin functions when enabled by the control status register and by
the serial port switching register.
69
I
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
SCK2
Clock output pin for the extended serial I/O interface
This pin functions when enabled by the control status register and by
the serial port switching register.
The pin is a general-purpose I/O port.
(Continued)
10
MB90230 Series
(Continued)
Circuit
type
Pin no.
Pin name
P50
Function
70
H
This pin is enabled in the single-chip mode and when the CLK output
is disabled.
CLK
CLK output pin
This pin is enabled in an external-bus enabled mode with the CLK
output enabled.
71
72
P51
RDY
P52
F
E
General-purpose I/O port
This port is enabled in the single-chip mode.
Ready signal input pin
This pin is enabled in an external-bus enabled mode.
General-purpose I/O port
This port is enabled in the single-chip mode or when the hold function
is disabled.
HAK
P53
Hold acknowledge signal output pin
This pin is enabled in the single-chip mode or when the hold function
is enabled.
73
74
E
E
General-purpose I/O port
This port is enabled in the single-chip mode or when the hold function
is disabled.
HRQ
Hold acknowledge signal output pin
This pin is enabled in the single-chip mode or when the hold function
is enabled.
P54
General-purpose I/O port
This port is enabled in the single-chip mode, in external-bus 8-bit
mode, or when the WR pin output is disabled.
WRH
Write strobe output pin for the upper eight bits of the data bus
This pin is enabled in an external-bus enabled mode and in external
bus 16-bit mode with the WR pin output enabled.
75
76
RST
P55
B
E
Reset signal input pin
This port is enabled in the single-chip mode, in external-bus 8-bit
mode, or when the WR pin output is disabled
WRL
Write strobe output pin for the lower eight bits of the data bus
This pin is enabled in an external-bus enabled mode and in external
bus 16-bit mode with the WR pin output enabled.
The pin is a general-purpose I/O port.
77
P56
RD
E
This pin is enabled in the single-chip mode.
Read strobe output pin for the data bus
This pin is enabled in an external-bus enabled mode.
78
79
P57
VSS
E
General-purpose I/O port
Power pin (GND)
—
*1: Enabled in any standby mode
*2: Enabled only in the hardware standby mode
11
MB90230 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• Oscillation feedback resistor:
Approx. 1 MΩ
X1
X0
Standby control
B
C
D
E
• Hysteresis input with pull-up
resistor
• CMOS input port
• Hysteresis input port
• CMOS level output
CMOS
Standby control
(Continued)
12
MB90230 Series
Type
Circuit
Remarks
F
• CMOS level output
• Hysteresis input
Standby control
G
• Input pull-up resistor control
provided
Pull-up control
• CMOS level input/output
CMOS
Standby control
H
• CMOS level input/output
• Open-drain control provided
Open-drain control signal
CMOS
Standby control
(Continued)
13
MB90230 Series
(Continued)
Type
Circuit
Remarks
I
• CMOS level output
• Hysteresis input
• Open-drain control provided
Open-drain control signal
CMOS
Standby control
J
• CMOS level input/output
• Analog input
Analog input
CMOS
Standby control
K
• CMOS level input/output
• Analog output
• Also serving for D/A output
DA output
CMOS
Standby control
L
• CMOS level output
• Hysteresis input
• Open-drain control provided
Open-drain control signal
Standby control
14
MB90230 Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage wihich shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. External Reset Input
To reset the internal circuit by the Low-level input to the RST pin, the Low-level input to the RST pin must be
maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input.
4. VCC and VSS Pins
Apply equal potential to the VCC and VSS pins.
5. Notes on Using an External Clock
When using an external clock, drive the X0 pin as illustrated below:
Use of External Clock
MB90234
X0
X1
6. Power-on Sequence for A/D Converter Power Supplies and Analog Inputs
Be sure to turn on the digital power supply (VCC) before applying voltage to the A/D converter power supplies
(AVCC, AVRH, and AVRL) and analog inputs (AN0 to AN15).
When turning power supplies off, turn off the A/D converter power supplies (AVCC, AVRH, and AVRL) and analog
inputs (AN0 to AN15) first, then the digital power supply (AVCC).
When turning AVRH on or off, be careful not to let it exceed AVCC.
7. Pin set when turning on power supplies
When turning on power supplies, set the hardware standby input pin (HST) to “H”.
15
MB90230 Series
8. Program Mode
When shipped from Fujitsu, and after each erasure, all bits (96K × 8 bits) in the MB90W234 and MB90P234 are
in the “1” state. Data is introduced by selectively programming “0’s” into the desired bit locations. Bits cannot
be set to 1 electrically.
9. Erasure Procedure
Data written in the MB90W234 is erased (from 0 to 1) by exposing the chip to ultraviolet rays with a wavelength
of 2,537Å through the translucent cover.
Recommended irradiation dosage for exposure is 10 Wsec/cm2. This amount is reached in 15 to 20 minutes
with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface
illuminance is 1200 µW/cm2).
If the ultraviolet lamp has a filter, remove the filter before exposure. Attaching a mirrored plate to the lamp
increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. If the translucent
part of the package is stained with oil or adhesive, transmission of ultraviolet rays is degraded, resulting in a
longer erasure time. In that case, clean the translucent part using alcohol (or other solvent not affecting the
package).
The above recommended dosage is a value which takes the guard band into consideration and is a multiple of
the time in which all bits can be evaluated to have been erased. Observe the recommended dosage for erasure;
the purpose of the guard band is to ensure erasure in all temperature and supply voltage ranges. In addition,
check the lifespan of the lamp and control the illuminance appropriately.
Data in the MB90W234 is erased by exposure to light with a wavelength of 4000Å or less.
Data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure
results in a much lower erasure rate than exposure to 2537Å ultraviolet rays. Note that exposure to such lights
for an extended period will therefore affect system reliability. If the chip is used where it is exposed to any light
with a wavelength of 4000Å or less, cover the translucent part, for example, with a protective seal to prevent
the chip from being exposed to the light.
Exposure to light with a wavelength of 4,000 to 5,000Å or more will not erase data in the device. If the light
applied to the chip has a very high illuminance, however, the device may cause malfunction in the circuit for
reasons of general semiconductor characteristics. Although the circuit will recover normal operation when
exposure is stopped, the device requires proper countermeasures for use in a place exposed continuously to
such light even though the wavelength is 4,000Å or more.
16
MB90230 Series
10. Recommended Screening Conditions
High-temperature aging is recommended for screening before packaging.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
11. Write Yield
OTPROM products cannot be write-tested for all bits due to their nature. Therefore the write yield cannot always
be guaranteed to be 100%.
17
MB90230 Series
■ BLOCK DIAGRAM
X0, X1
4
CPU
F2MC-16F
RST
HST
Clock controller
Interrupt controller
External interrupt
RAM
ROM
INT0
to
INT3
4
SIN0
SOT0
SCK0
UART
PWM0
to
8-bit PWM
PWM5
6 ch
CKOT
Communication prescaler
TRG
PPG
8-bit PPG timer
SIN1, 2
SOT1, 2
SCK1, 2
I/O timer
Extended serial
I/O interface
IN0, 1
IN2, 3
16-bit input capture × 4
16-bit free run timer
16-bit output compare × 6
OUT0, 1
OUT2, 3
OUT4, 5
AVcc
AVRH, AVRL
AVss
ATG
AN0 to AN7
2
10-bit A/D converter
D/A converter
ECS, ESK
EDO
EDI
Serial E2PROM interface
Level comparator
DA0
DA1
CMP
I/O ports (84 lines)
8
8
8
8
8
8
8
7
8
7
6
P00 P10 P20 P30 P40 P50 P60 P70 P80 P90 PA0
to to to to to to to to to to to
P07 P17 P27 P37 P47 P57 P67 P76 P87 P96 PA5
P00 to P27 (24 lines): Provided with input pull-up resistor setting registers
P94 to P96, PA0 to PA5 (9 lines): Provided with open-drain setting registers
18
MB90230 Series
■ MEMORY MAP
Internal ROM and
external bus
External ROM and
external bus
Single-chip mode
ROM area
FFFFFFH
ROM area
Address1#
00FFFFH
ROM area
ROM area
(FF bank image)
(FF bank image)
Address#2
Address#3
RAM
RAM
RAM
Registers
Registers
Registers
000100H
0000C0H
Peripherals
Peripherals
Peripherals
000000H
Internal
External
Inhibited area
000000H to 000005H and 000010H to 000015H are allocated for external use
when the external bus is enabled.
Note:
Product type
MB90233
Address#1
FF4000H
Address#2
004000H
Address#3
000900H
MB90234
FE8000H
FE8000H
004000H
004000H
000D00H
000D00H
MB90P234
MB90W234
(FE0000H)
(004000H)
(001100H)
MB90V230
The MB90230 series can access the 00 bank to read ROM data written to the upper 48-KB locations in the FF
bank. An advantage of reading written to data addresses FFFFFFH-FF4000H from addresses 00FFFFH-004000H is
that you can use the small model of a C compiler.
Note, however, that the products with more than 48KB ROM space (MB90V230, MB90P/W234, MB90234) cannot
read data in addresses other than FFFFFFH to FF4000H from the 00 bank.
19
MB90230 Series
■ I/O MAP
Register
name
Resouce
name
Address
Register
Port 0 data register
Access
Initial value
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
DDRA
RDR0
RDR1
RDR2
ODR9
ODRA
UMC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
– X X X X X X X
X X X X X X X X
– X X X X X X X
– – X X X X X X
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
– 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
– 0 0 0 0 0 0 0
– – 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
– 0 0 0 – – – –
– – 0 0 0 0 0 0
0 0 0 0 0 1 0 0
0 0 0 1 0 0 0 0
X X X X X X X X
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
Port 5 data register
Port 6 data register
Port 7 data register
Port 8 data register
Port 9 data register
Port A data register
Port 0 direction register
Port 1 direction register
Port 2 direction register
Port 3 direction register
Port 4 direction register
Port 5 direction register
Port 6 direction register
Port 7 direction register
Port 8 direction register
Port 9 direction register
Port A direction register
Port 0 resistor register
Port 1 resistor register
Port 2 resistor register
Port 9 pin register
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port 0
Port 1
Port 2
Port 9
Port A
UART
Port A pin register
Mode control register
Status register
USR
Serial input register
/Serial output register
UIDR
/UODR
R/W
23H
24H
25H
Rate and data register
URD
R/W
R/W
0 0 0 0 – – 0 0
– – – 0 0 0 0 0
0 0 0 0 0 0 1 0
Serial mode control status register
SMCS
Extended serial
I/O interface
(Continued)
20
MB90230 Series
Register
name
Resouce
Initial value
name
Address
Register
Serial data register
Access
26H
SDR
R/W
Extendedserial X X X X X X X X
I/O interface
27H
28H
29H
2AH
2BH
2CH
2DH
Reserved area
—
—
W
—
—
Cycle setting register
Duty factor setting register
Control status register
PCSR
PDUT
PCNTL
PCNTH
—
8-bit
PPG timer
X X X X X X X X
X X X X X X X X
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 –
—
W
R/W
Reserved area
—
—
Communication prescaler
CDCR
R/W
UART, CKOT,
I/O, serial IF
0 – – – 1 1 1 1
2EH
2FH
Clock control register
Level comparator
CLKR
LVLC
R/W
R/W
CKOT output
– – – – – 0 0 0
X X X X 0 0 0 0
Level
comparator
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
Interrupt/DTP enable register
Interrupt/DTP factor register
Request level setting register
Reserved area
ENIR
EIRR
ELVR
—
R/W
R/W
R/W
—
DTP/external
interrupt
– – – – 0 0 0 0
– – – – 0 0 0 0
0 0 0 0 0 0 0 0
—
—
Analog input enable register
Reserved area
ADER
—
R/W
—
10-bit A/D
converter
1 1 1 1 1 1 1 1
—
Control status data register
ADCS0
ADCS1
ADCR0
ADCR1
—
R/W
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
X X X X X X X X
0 0 0 0 0 0 X X
—
Data register
R
Reserved area
—
—
—
Reserved area
—
—
—
D/A converter data register 0
D/A converter data register 1
D/A control register
Reserved area
DAT0
DAT1
DACR
—
R/W
R/W
R/W
—
8-bit D/A
converter
X X X X X X X X
0 0 0 0 0 0 0 0
– – – – – – 0 0
—
—
PWM data register 0
PWM data register 1
Control status data register 0, 1
Reserved area
PWD0
PWD1
PWC01
—
R/W
R/W
R/W
—
8-bit
PWM0, 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
—
—
PWM data register 2
PWM data register 3
Control status register 2, 3
PWD2
PWD3
PWC23
R/W
R/W
R/W
8-bit
PWM2, 3
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
(Continued)
21
MB90230 Series
Register
name
Resouce
name
Address
Register
Reserved area
Access
Initial value
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
62H
63H
64H
65H
66H
—
—
R/W
R/W
R/W
—
—
—
PWM data register 4
PWM data register 5
Control status register 4, 5
Reserved area
PWD4
PWD5
PWC45
—
8-bit
PWM4, 5
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
—
—
Data register
TCDT
R
16-bit free
run timer
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
—
Control status register
Reserved area
TCCS
—
R/W
—
—
Compare register 0
OCP0
R/W
Output
compare 0, 1
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
0 0 0 0 – – 0 0
– – – 0 0 0 0 0
—
Compare register 1
OCP1
R/W
R/W
Control status register 0, 1
CS00
CS01
—
Reserved area
—
—
—
—
Reserved area
—
—
Compare register 2
OCP2
R/W
Output
compare 2, 3
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
0 0 0 0 – – 0 0
– – – 0 0 0 0 0
—
Compare register 3
OCP3
R/W
R/W
Control status register 2, 3
CS10
CS11
—
Reserved area
—
—
—
—
Reserved area
—
—
Compare register 4
OCP4
R/W
Output
compare 4, 5
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
0 0 0 0 – – 0 0
– – – 0 0 0 0 0
—
Compare register 5
OCP5
R/W
R/W
CS20
CS21
—
Control status register 4, 5
Reserved area
Reserved area
—
—
—
—
67H to
6FH
—
—
(Continued)
22
MB90230 Series
Register
name
Resouce
Initial value
name
Address
Register
Capture register 0
Access
70H
71H
72H
73H
74H
ICP0
R/W
Input capture 0,
1
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
0 0 0 0 0 0 0 0
—
Capture register 1
ICP1
R/W
Control status register 0, 1
Reserved area
ICS0
—
R/W
—
75H to
77H
—
78H
79H
7AH
7BH
7CH
Capture register 2
Capture register 3
ICP2
ICP3
R/W
R/W
Input capture 2,
3
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
0 0 0 0 0 0 0 0
—
Control status register 2, 3
Reserved area
ICS1
—
R/W
—
7DH to
7FH
—
Serial E2PROM
interface
80H
81H
82H
83H
84H
85H
OP code register
Format status register
Data register
EOPC
ECTS
EDAT
R/W
R/W
R/W
– – – – 0 0 0 0
0 0 0 0 0 0 0 0
X X X X X X X X
X X X X X X X X
0 0 0 0 0 0 0 0
0 0 – – – 0 0 0
—
Address register
EADR
R/W
86H to
8FH
Reserved area
—
—
—
*1
—
—
90H to
9EH
System reserved area
—
9FH
Delayed interrupt source generate/
release register
DIRR
STBYC
R/W
R/W
Delayed interrupt
generation module
– – – – – – – 0
0 0 0 1 X X X X
A0H
Standby control register
Low-power
consumption
mode
A1H
A2H
A3H
A4H
A5H
A6H
A7H
A8H
Reserved area
—
—
—
—
—
—
—
Reserved area
—
Middle address control register
Upper address control register
External pin control register
Reserved area
MACR
HACR
EPCR
—
W
External pin
External pin
External pin
—
*2
W
*2
W
*2
—
—
—
Reserved area
—
—
—
Watchdog timer control register
TWC
R/W
Watchdog timer/
reset
X X X X X X X X
(Continued)
23
MB90230 Series
Register
name
Resouce
name
Address
Register
Access
Initial value
A9H
Timebase timer control register
TBTC
R/W
Timebase
timer
– – – 0 0 0 0 0
AAH to
AFH
Reserved area
—
—
—
—
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
Interrupt control register 00
Interrupt control register 01
Interrupt control register 02
Interrupt control register 03
Interrupt control register 04
Interrupt control register 05
Interrupt control register 06
Interrupt control register 07
Interrupt control register 08
Interrupt control register 09
Interrupt control register 10
Interrupt control register 11
Interrupt control register 12
Interrupt control register 13
Interrupt control register 14
Interrupt control register 15
External area
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Interrupt
controller
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
*3
C0H to
FFH
—
Initial values
0: The initial value for the bit is “0.”
1: The initial value for the bit is “1.”
X: The initial value for the bit is undefined.
–: The bit is not used; the initial value is undefined.
*1: Access inhibited
*2: The initial value depends on each bus mode.
*3: Only this area can be used as the external access area in the area that follows address 0000FFH. Access to
any address in reserved areas specified in the I/O map table is handled as access to an internal area. An
access signal to the external bus is not generated.
24
MB90230 Series
■ INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS FOR INTERRUPT
SOURCES
Interrupt control
Interrupt vector
I2OS
register
Interrupt source
support
No.
Address
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFB8H
FFFFB0H
FFFFA8H
FFFFA0H
FFFF9CH
ICR
—
Address
Reset
×
×
×
#08
#09
#10
#11
#12
#13
#14
#15
#17
#19
#21
#23
#24
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
—
—
INT9 instruction
—
Exceptional
—
—
ICR00
0000B0H
External interrupt (INT0) 0 ch
External interrupt (INT1) 1 ch
External interrupt (INT2) 2 ch
External interrupt (INT3) 3 ch
Extended serial I/O interface
Serial E2PROM interface
Input capture channel 0
Input capture channel 1
Input capture channel 2
Input capture channel 3
Output compare channel 0
Output compare channel 1
Output compare channel 2
Output compare channel 3
Output compare channel 4
Output compare channel 5
16-bit free run timer overflow
Timebase timer overflow
8-bit PPG timer
ICR01
0000B1H
ICR02
ICR03
ICR04
ICR05
ICR06
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
11H
13H
15H
17H
18H
ICR07
ICR08
ICR09
ICR10
ICR11
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#37
#39
#42
#256
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
25H
27H
2AH
FFH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF68H
FFFF60H
FFFF54H
FFFC00H
Level comparator
0000BCH
0000BDH
0000BEH
0000BFH
—
UART reception
ICR12
ICR13
UART transmission
End of A/D conversion
Delayed interrupt
ICR14
ICR15
—
×
×
Stack fault
: The request flag is cleared by the EI2OS interrupt clear signal.
: The request flag is cleared by the EI2OS interrupt clear signal. The stop request is available.
: The request flag is not cleared by the EI2OS interrupt clear signal.
25
MB90230 Series
■ PERIPHERAL RESOURCES
1. I/O Ports
Each pin in each port can be specified for input or output by setting the direction register when the corresponding
peripheral resource is not set to use that pin. When the data register is read, the value depending on the pin
level is read whenever the pin serves for input. When the data register is read with the pin serving for output,
the latch value of the data register is read. This also applies to read operation by the read modify write instruction.
• General-purpose I/O port
Data register read
Pin
Data register
Data register write
Direction register
Direction register write
Direction register read
• Port with pull-up resistor setting register
Pull-up resistor (Approx. 50 kΩ)
Port input/output
Data register
Direction register read
Resistor register
26
MB90230 Series
• Port with open-drain setting register
Port input/output
Data register
Direction register
Pin register
27
MB90230 Series
(1) Register Configuration
15/7 14/6 13/5 12/4 11/3 10/2 9/1
8/0
bit
P00
P10
P20
P30
P40
P50
P60
P70
P80
P90
PA0
P07 P06 P05 P04 P03 P02 P01
P17 P16 P15 P14 P13 P12 P11
P27 P26 P25 P24 P23 P22 P21
P37 P36 P35 P34 P33 P32 P31
P47 P46 P45 P44 P43 P42 P41
P57 P56 P55 P54 P53 P52 P51
P67 P66 P65 P64 P63 P62 P61
Port 0 data register (PDR0)
Port 1 data register (PDR1)
Port 2 data register (PDR2)
Port 3 data register (PDR3)
Port 4 data register (PDR4)
Port 5 data register (PDR5)
Port 6 data register (PDR6)
Port 7 data register (PDR7)
Port 8 data register (PDR8)
Port 9 data register (PDR9)
Port A data register (PDRA)
Address: 000000H
Address: 000001H
Address: 000002H
Address: 000003H
Address: 000004H
Address: 000005H
Address: 000006H
Address: 000007H
Address: 000008H
Address: 000009H
Address: 00000AH
—
P76 P75 P74 P73 P72 P71
P87 P86 P85 P84 P83 P82 P81
—
—
P96 P95 P94 P93 P92 P91
PA5 PA4 PA3 PA2 PA1
—
15/7 14/6 13/5 12/4 11/3 10/2 9/1
8/0
bit
P00
P10
P20
P30
P40
P50
P60
P70
P80
P90
PA0
P07 P06 P05 P04 P03 P02 P01
P17 P16 P15 P14 P13 P12 P11
P27 P26 P25 P24 P23 P22 P21
P37 P36 P35 P34 P33 P32 P31
P47 P46 P45 P44 P43 P42 P41
P57 P56 P55 P54 P53 P52 P51
P67 P66 P65 P64 P63 P62 P61
Port 0 direction register (DDR0)
Port 1 direction register (DDR1)
Port 2 direction register (DDR2)
Port 3 direction register (DDR3)
Port 4 direction register (DDR4)
Port 5 direction register (DDR5)
Port 6 direction register (DDR6)
Port 7 direction register (DDR7)
Port 8 direction register (DDR8)
Port 9 direction register (DDR9)
Port A direction register (DDRA)
Address: 000010H
Address: 000011H
Address: 000012H
Address: 000013H
Address: 000014H
Address: 000015H
Address: 000016H
Address: 000017H
Address: 000018H
Address: 000019H
Address: 00001AH
—
P76 P75 P74 P73 P72 P71
P87 P86 P85 P84 P83 P82 P81
—
—
P96 P95 P94 P93 P92 P91
—
PA5 PA4 PA3 PA2 PA1
15
14
13
12
11
10
9
8
bit
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1
ADE0 Analog input enable register (ADER)
Address: 000034H
15/7 14/6 13/5 12/4 11/3 10/2 9/1
8/0
bit
P00
P07 P06 P05 P04 P03 P02 P01
P17 P16 P15 P14 P13 P12 P11
P27 P26 P25 P24 P23 P22 P21
Port 0 resistor register (RDR0)
Address: 00001BH
Address: 00001CH
Address: 00001DH
P10
Port 1 resistor register (RDR1)
P20
Port 2 resistor register (RDR2)
15/7 14/6 13/5 12/4 11/3 10/2 9/1
8/0
bit
—
—
—
P96 P95 P94
—
—
—
Port 9 pin register (ODR9)
Address: 00001EH
Address: 00001FH
—
PA5 PA4 PA3 PA2 PA1
PA0
Port A pin register (ODRA)
28
MB90230 Series
Ports 0 to 5 in the MB90230 series share the external bus and pins. Each pin function is selected depending on
the bus mode and register settings.
Function
Pin name
External bus extended mode
Single-chip mode
EPROM write
8 bits
16 bits
P07 to P00
P17 to P10
P27 to P20
P37 to P30
P47 to P45
P44
D07 to D00
A07 to A00
D07 to D00
D15 to D08
A07 to A00
A15 to A08
Port
D15 to D08
A15 to A08*1
A23 to A16*1
A23 to A16
P43 to P40
P50
CLK*2
RDY*2
HAK*2
HRQ*2
Port
P51
Not used
P52
P53
WRH*2
WRL*2
P54
Port
WR
CE
OE
P55
P56
RD
PGM
“0”
P57
Port
*1: The pin can be used as an I/O port by setting the upper and middle address control registers.
*2: The pin can be used as an I/O port by setting the external pin control register.
29
MB90230 Series
2. 8-bit PWM (with 6 channels in this series)
The PWM module consists of a pair of 8-bit PWM output circuits. The MB90230 series incorporates a set of
three PWM modules. They can output a waveform continuously from the port at an arbitrary duty factor according
to the register settings.
• 8-bit down counter
• 8-bit data registers
• Compare circuit
• Control registers
(1) Register Configuration
bit
15
8 7
0
0
000041, 40H
000045, 44H
000049, 48H
PWM data registers 0 to 5
Control registers 0 to 5
PWDx
PWDx
7
000042H
000046H
00004AH
PWCxx
(2) Block Diagram
8-bit down counter
PWM output
Comparator, PWM output section
8-bit data registers
Control registers
30
MB90230 Series
3. UART
The UART is a serial I/O port for synchronous or asynchronous communication with external resources. It has
the following features:
• Full-duplex double buffering
• Data transfer synchronous or asynchronous with clock pulses
• Multiprocessor mode support (Mode 2)
• Internal dedicated baud-rate generator
• Arbitrary baud-rate setting from external clock input or internal timer
• Variable data length (7 to 9 bits (without parity bit); 6 to 8 bits (with parity bit))
• Error detection function (Framing, overrun, parity)
• Interrupt function (Two sources for transmission and reception)
• Transfer in NRZ format
(1) Register Configuration
15
8
7
0
(R/W)
(R/W)
USR
URD
8 bits
UMC
UIDR (R)/UODR (W)
8 bits
7
6
5
4
3
2
1
0
bit
Mode control register
(UMC)
Address: 000020H
PEN
SBL
14
MC1
MC0 SMDE RFC SCKE SOE
15
13
12
11
10
9
8
bit
Status register
(USR)
Address: 000021H
RDRF ORFE
PE
TDRE
RIE
TIE
RBF
TBF
7
6
5
4
3
2
1
0
bit
Serial input data register
Serial output data register
(UIDR/UODR)
Address: 000022H
D7
D6
D5
D4
D3
D2
D1
D0
15
—
14
13
12
11
—
10
—
9
8
bit
Rate and data register
(URD)
Address: 000023H
RC2
RC1
RC0
P
D8
15
14
—
13
—
12
—
11
10
9
8
bit
Communication prescaler
(CDCR)
Address: 00002DH
MD
DIV3
DIV2
DIV1
DIV0
31
MB90230 Series
(2) Block Diagram
CONTROL BUS
Reception interrupt
(To CPU)
Dedicated baud-rate clock
SCK0
Transmission interrupt
(To CPU)
Transmitting clock
Internal timer
Clock selector
Receiving clock
circuit
External clock
Reception control circuit
Transmission control circuit
SIN0
Start bit detector
Transmission start circuit
Transmission bit counter
Transmission parity counter
Received bit counter
Received parity counter
SOT0
Reception status
detection circuit
Reception shifter
Transmission shifter
End of reception
UIDR
Start of transmission
UODR
Reception error
occurrence signal for EI2OS
(To CPU)
Data bus
PEN
SBL
MC1
MC0
SMDE
RFC
RDRF
ORFE
PE
BCH
RC2
RC1
RC0
UMC
register
USR
URD
register
TDRE
register
RIE
TIE
SCKE
SOE
RBF
TBF
P
D8
CONTROL BUS
32
MB90230 Series
4. Extended Serial I/O Interface
This block is a serial I/O interface implemented on a single 8-bit channel that can transfer data in synchronization
with clock pulses. It allows the “LSB first” or “MSB first” option to be selected for data transfer. The serial I/O
port to be used can also be selected.
There are two serial I/O operation modes available:
• Internal shift clock mode: Transfers data in synchronization with internal clock pulses.
• External shift clock mode: Transfers data in synchronization with clock pulses entered from an external pin
(SCKx). In this mode, data can be transferred by instructions from the CPU by
operating the general-purpose port that shares the external pin (SCKx).
(1) Register Configuration
15
14
13
12
11
10
9
8
bit
Address: 000025H
SMD2 SMD1 SMD0
SIE
SIR
BUSY STOP STRT
7
6
5
4
3
2
1
0
bit
Serial mode control status
register (SMCS)
Address: 000024H
—
—
—
OUTC MODE BDS
SOE SCOE
7
6
5
4
3
2
1
0
bit
Serial data register
(SDR)
Address: 000026H
D7
D6
D5
D4
D3
D2
D1
D0
(2) Block Diagram
Internal data bus
(MSB first) D0 to D7
SIN1, 2
D7 to D0 (LSB first)
Selecting transfer direction
Read
Write
SDR (Serial data register)
SOT1, 2
SCK1, 2
Shift clock counter
Control circuit
Internal clock
2
1
0
SMD2 SMD1 SMD0 SIE
SIR BUSY STOP STRT MODE BDS SOE SCOE
Interrupt
request
Internal data bus
33
MB90230 Series
5. A/D Converter
The A/D converter converts the analog input voltage to a digital value. It has the following features:
• Conversion time: 5 µs min. per channel (at 16 MHz machine clock)
• RC-type successive approximation with sample-and-hold circuit
• 8-bit or 10-bit resolution
• Eight analog input channels programmable for selection
• A/D conversion mode selectable from the following three:
One-shot conversion mode: Converts a specified channel once.
Consecutive conversion mode: Converts a specified channel repeatedly.
Stopconversionmode: Convertsonechannelandsuspendsitsownoperationuntilthenextactivation(allowing
synchronized conversion start).
• Conversion mode:
Single conversion mode: Converts one channel (when the start and stop channels are the same).
Scan conversion mode: Converts multiple consecutive channels (when the start and stop channels are
different).
• On completion of A/D conversion, the converter can generate an interrupt request for termination of A/D
conversion to the CPU. This interrupt generation can activate the EI2OS to transfer the A/D conversion result
to memory, making the converter suitable for continuous operation.
• Conversion can be activated by software, external trigger (falling edge), and/or timer (rising edge) as selected.
(1) Register Configuration
bit
8
7
0
15
Control status register
Data register
000037, 36H
ADCS1
ADCR1
ADER
ADCS0
ADCR0
000039, 38H
000034H
Analog input enable register
34
MB90230 Series
(2) Block Diagram
AVCC
AVRH,
AVRL
AVSS
D/A converter
MPX
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Successive
approximation register
Comparator
Sample-and-hold circuit
Data register
ADCR1, 0
A/D control register 0
A/D control register 1
ADCS1, 0
Activation trigger
Activation by timer
ATG
Timer
Operation clock
Interlocked with PPG timer
φ
Prescaler
35
MB90230 Series
6. 16-bit I/O Timer
The 16-bit I/O timer consists of 16-bit free run timer, 6-line output compare, and 4-line input capture modules.
The 16-bit I/O timer can output six independent waveforms based on the 16-bit free run timer, allowing the input
pulse width and external clock cycle to be measured.
(1) Outline of Functions
16-bit free run timer (× 1)
The 16-bit free run timer consists of a 16-bit up-count timer, a control register, and a prescaler. The value output
from this timer/counter is used as the base time by the input capture and output compare modules.
• The counter operation clock cycle can be selected from the following four:
Four internal clock cycles (φ/4, φ/16, φ/32, φ/64)
• The interrupt counter value can be generated by compare/match operation with the overflow register and
compare register 0 (compare/match operation requires the mode setting).
• The counter value can be initialized to “0000H” by compare/match operation with the reset register, software
clear register, and compare register 0.
Output compare module (× 6)
The output compare module consists of six 16-bit compare registers, compare output latches, and control
registers. When the compare value matches the 16-bit free run timer value, this module can generates an
interrupt while inverting the output level.
• Six compare registers can operate independently, and have each output pin and interrupt flag.
• Two compare resisters can be used to control the same output pin.
• The initial value for each output pin can be set.
• The interrupt can be generated by compare/match operation.
Input capture module (× 4)
The input capture module consists of four external input pins and associated capture and control registers. This
module can detect an arbitrary edge of the signal input from each external input pin to generate an interrupt
while holding the 16-bit free run timer value in the capture register.
• The external input signal edge can be selected from the rising edge, failing edge or both edges.
• Four input capture lines can operate independently.
• The interrupts can be generated by a valid edge of external input signals. The extended intelligent I/O service
(EI2OS) can be activated.
36
MB90230 Series
(2) Register Configuration
• 16-bit free run timer
bit
0
15
Timer data register
00004CH
TCDT
Control status register
00004EH
TCCS
• 16-bit output compare module
bit
0
15
000050, 52, 58, 5AH
000060, 62H
Compare register 0 to 5
OCP0 to 5
000054, 55H
00005C, 5DH
000064, 65H
Control status register 0 to 5
CS × 1
CS × 0
• 16-bit input capture module
bit
0
15
Compare register 0 to 3
IPCP0 to 3
000070, 72, 78, 7AH
000074, 7CH
Control status register 0 to 3
ICS0 to 3
37
MB90230 Series
(3) Block Diagram
Control logic
16-bit timer
16-bit free run timer
Clear
Output compare 0
OUT 0
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
Compare register 0
TQ
TQ
TQ
TQ
Compare register 1
Output compare 1
Compare register 2
Compare register 3
Output compare 2
TQ
TQ
Compare register 4
Compare register 5
Input capture 0
Input capture 1
IN 0
IN 1
Capture register 0
Capture register 1
Edge selection
Edge selection
IN 2
IN 3
Capture register 2
Capture register 3
Edge selection
Edge selection
Interrupt
10
38
MB90230 Series
7. PPG Timer (Programmable Pulse Generator)
This module can output the pulse synchronized with an external or software trigger. The cycle and duty factor
of the output pulse can be changed arbitrarily by changing the values in two 8-bit registers.
PWM function: Outputs a pulse in programmable mode while changing the values in the two registers in
synchronization with the input trigger.
This module can also be used as a D/A converter using an external circuit.
Single-shot function: Detects the trigger input edge to output a single pulse.
(1) Module Configuration
This module consists of an 8-bit down counter, prescaler, 8-bit cycle setting register, 8-bit duty factor setting
register, 16-bit control register, external trigger input pin, and PPG output pin.
(2) Register Configuration
bit
Address: 000028H
000029H
15
8
7
0
Cycle setting register
Duty factor setting register
Control status register
PCSR
PDUT
00002BH, 2AH
PCNTH
PCNTL
39
MB90230 Series
(3) Block Diagram
P C S R
P D U T
Prescaler
1 / φ
cmp
4 / φ
ck
Load
8-bit
16 / φ
64 / φ
down counter
Start
Borrow
PPG mask
S
Q
PPG output
R
Inverted bit
Enable
IRQ
TRG input
Edge detection
Software trigger
40
MB90230 Series
8. Serial E2PROM Interface
This module is the interface circuit dedicated to external bit-serial E2PROM.
(1) Features
• Instruction code support (compatible with the MB8557).
• Selectable address length: 8 to 11 bits
• Selectable data length: 8 or 16 bits
• Automatic address increment function
• Transmit/receive data transfer enabled by EI2OS
• Up to 2048-by-16 bit access enabled (at an address length of 11 bits and a data length of 16 bits)
(2) Register Configuration
15
8
7
0
bit
Status format register
Data register
Address register
15
14
13
12
11
10
9
8
bit
Format status register
(ECTS)
Address: 000081H
IFEN
INT
INTE BUSY ADL1 ADL0
DTL
CON
7
6
5
4
3
2
1
0
bit
Op code register
(EOPC)
Address: 000080H
—
—
—
—
OP3
OP2
OP1
OP0
15
14
13
12
11
10
9
8
bit
Data register
(EDAT)
Address: 000083H
D15
D14
D13
D12
D11
D10
D9
D8
7
6
5
4
3
2
1
0
bit
Data register
(EDAT)
Address: 000082H
D7
D6
D5
D4
D3
D2
D1
D0
15
14
13
—
12
—
11
—
10
9
8
bit
Address register
(EADR)
Address: 000085H
CLK
FRQ
A10
A9
A8
7
6
5
4
3
2
1
0
bit
Address register
(EADR)
Address: 000084H
A7
A6
A5
A4
A3
A2
A1
A0
41
MB90230 Series
(3) Block Diagram
Op code register
Address register
EDI
Data register
Data register
EDO
ECS
Format register
Status register
Operation clock
Prescaler
ESK
φ
Machine cycle
42
MB90230 Series
9. DTP/External Interrupt
The data transfer peripheral (DTP) is located between external peripherals and the F2MC-16F CPU. It receives
a DMA request or interrupt request generated by the external peripherals and reports it to the F2MC-16F CPU
to activate the extended intelligent I/O service or interrupt handler. The user can select two request levels of
“H” and “L” for extended intelligent I/O service (EI2OS) or, four request levels of “H,” “L,” rising edge, and falling
edge for external interrupt requests.
(1) Register Configuration
bit
15
8
7
0
Interrupt/DTP enable register
Request level setting register
Address: 000031H, 30H
EIRR
ENIR
ELVR
000032H
(2) Block Diagram
4
Interrupt DTP source register
4
4
3
Gate
Source F/F
Edge detection circuit
Request input
Interrupt DTP source register
8
Request level setting register
43
MB90230 Series
10. D/A Converter
This block is an R-2R type D/A converter with 8-bit resolution.
The D/A converter incorporates two channels, each of which can be controlled for output independently by the
D/A control register.
(1) Register Configuration
bit
15
14
13
12
11
10
9
8
DAT1
DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10
D/A converter data register 1
D/A converter data register 2
D/A control register
Address: 00003DH
7
6
5
4
3
2
1
0
DAT0
Address: 00003CH
DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00
7
6
5
4
3
2
1
0
DACR
Address: 00003EH
—
—
—
—
—
—
DAE1 DAE0
(2) Block Diagram
F2MC-16 bus
DA DA DA DA DA DA DA DA
17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA
07 06 05 04 03 02 01 00
AVCC
AVCC
DA17
DA07
2R
2R
R
R
DA16
DA06
2R
R
2R
R
DA15
DA11
DA05
DA01
2R
R
2R
R
DA10
DA00
2R
2R
2R
2R
DAE1
Standby control
DAE0
Standby control
DA output
ch. 1
DA output
ch. 0
44
MB90230 Series
11. Level Comparator
This module compares the input level (by checking whether it is high or low).
The module consists of a comparator, 4-bit resistor ladder, and control register.
• The external input can be compared to the internal 4-bit resistor ladder.
(1) Register Configuration
bit
8
0
Level comparator
Address: 00002FH
LVLC
(2) Block Diagram
4-bit D/A
AVRH
RD3
RD2
RD1
RD0
4
CPLV
INT
INTE CPEN
AVRL
Analog input
CMP
S/H
Interrupt
Comparator
45
MB90230 Series
12.Watchdog Timer and Timebase Timer
The watchdog timer consists of a 2-bit watchdog counter using carry signals from an 18-bit timebase counter
as the clock source, a control register, and a watchdog reset control section. The timebase timer consists of
an 18-bit timer and an interval interrupt control circuit.
(1) Register Configuration
15
8
7
0
bit
Timebase timer control register
0000A9H, A8H
TBTC
WTC
Address:
(2) Block Diagram
Oscillation clock
TBTC
TBC1
Clock input
212
214
216
218
Selector
Timebase timer
TBC0
TBR
TBTRES
214 216 217 218
S
R
TBIE
Q
AND
TBOF
Timebase
interrupt
WTC
WT1
2-bit counter
OF
Watchdog reset
generator
WDGRST
Selector
To internal reset generator
WT0
WTE
CLR
CLR
PONR
STBR
WRST
ERST
SRST
From power-on occurrence
From hardware standby
control circuit
RST pin
From RST bit in STBYC register
46
MB90230 Series
13. Delay Interruupt Generation Module
The delayed interrupt generation module is used to generate an interrupt for task switching. Using this module
allows an interrupt request to the F2MC-16F CPU to be generated or canceled by software.
(1) Register Configuration
15
—
14
—
13
—
12
—
11
—
10
—
9
8
bit
Delayed interrupt source
generate/release register
DIRR
—
R0
Address: 00009FH
(—)
(X)
(—)
(X)
(—)
(X)
(—)
(X)
(—)
(X)
(—)
(X)
(—)
(X)
(R/W)
(0)
Read/write →
Initial value →
(2) Block Diagram
Delayed interrupt source generate/release decoder
Interrupt source latch
14. Clock Output Control Register
The clock output control register outputs the output from the communication prescaler to the pin.
(1) Register Configuration
bit
15
—
14
—
13
—
12
—
11
—
10
9
8
Clock control register
CLKR
Address: 00002EH
CKEN FRQ1 FRQ0
(R/W) (R/W) (R/W)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
Read/write →
Initial value →
(0)
(0)
(0)
47
MB90230 Series
15.Low-power Consumption Control Circuit
Thelow-powerconsumptioncontrolcircuitconsistsofalow-powerconsumptioncontrolregister, clockgenerator,
standby status control circuit, and gear divider circuit. These internal circuits implements the sleep, stop, and
hardware standby modes as well as the clock gear function. The gear function allows the machine clock cycle
to be selected as a division of the frequency of crystal oscillation or external clock input by 1, 2, 4, or 16.
(1) Register Configuration
bit
15
8
7
0
Standby control register
Address: 0000A0H
STBYC
(2) Block Diagram
Oscillation clock
CPU clock
Gear divider circuit
1/1 1/2 1/4 1/16
CPU clock
generator
STBYC
CLK1
Selector
CLK0
Resource clock
Resource clock
generator
SLP
STP
Standby control circuit
RST Clear HST start
HST pin
Interrupt request or RST
Clock input
20
216
217
218
OSC1
OSC0
Time-base timer
214 216 217 218
Selector
SPL
RST
Pin HI-Z
Pin high-impedance control circuit
Internal reset generator
RST pin
Internal RST
To watchdog timer
WDGRST
48
MB90230 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = 0.0 V)
Value
Symbol
VCC
Unit
Remarks
Parameter
Min.
Max.
VSS – 0.3
VSS + 7.0
V
V
Power supply voltage
AVCC, AVSS
AVRH, AVRL
VCC – 0.3*1
VSS + 7.0
VI*2
VO*2
IOL
Input voltage
VSS – 0.3
VSS – 0.3
VCC + 0.3
VCC + 0.3
20
V
Output voltage
V
“L” level output current
mA
mA
mA
mA
mA
mA
mW
°C
“L” level average output current IOLAV
—
4
“L” level total output current
“H” level output current
ΣIOL
50
IOH
–10
“H” level average output current IOHAV
—
—
–4
“H” level total output current
Power consumption
ΣIOH
PD
–50
—
400
Operating temperature
Storage temperature
TA
–40
–55
+70
TSTG
+150
°C
*1: AVRH, AVRL, or AVCC must not exceed VCC.
AVSS and AVRH must not exceed AVRH and AVCC, respectively.
VCC ≥ AVCC ≥ AVRH > AVRL ≥ AVSS ≥ VSS
*2: VI or VO must not exceed “VCC + 0.3 V.”
WARNING: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for externded periods may affect
device reliability.
2. Recommended Operating Conditions
(VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
4.75
3.0
Max.
5.25
5.5
V
V
During normal operation
In stop mode
Power supply voltage
VCC
Operating temperature TA
–40
+70
°C
49
MB90230 Series
3. DC Characteristics
(VCC = 5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
Parameter
Symbol
Condition
Unit
Remarks
name
Min.
Typ.
—
Max.
VIH
*1
*2
*3
*1
*2
*3
0.7 VCC
0.8 VCC
VCC – 0.3
VSS – 0.3
VSS – 0.3
VSS – 0.3
2.4
VCC + 0.3
VCC + 0.3
VCC + 0.3
0.3 VCC
V
V
V
V
V
V
“H” level input
voltage
VIHS
VIHM
VIL
VCC = 5.0 V±5%
—
Hysteresis input
MD0 to 2
—
—
“L” level input
voltage
VILS
VILM
VCC = 5.0 V±5%
—
0.2 VCC
Hysteresis input
MD0 to 2
—
VSS + 0.3
“H” level output
voltage
VCC = 4.75 V
IOH = –2.0 mA
VOH
VOL
IIH
*1, *2
*1, *2
—
—
—
—
0.4
10
V
V
“L” level output
voltage
VCC = 4.75 V
IOL = 1.8 mA
—
*1, *2,
*3
Input leakage
current
VSS + 4.75 V
<VI <VCC
–10
µA
ICC
—
—
—
48
15
10
80
25
—
mA
Power supply
current
VCC = 5.0 V±5%
fc = 16 MHz
ICCS
ICCH
VCC
mA In sleep mode
µA In stop mode
Other
Input capacity
CIN
thanVCC
and VSS
—
—
10
—
pF
Open-drain
output leakage
current
(N-channel Tr
OFF)
ILEAK
*4
*5
—
—
—
0.1
—
10
µA
µA
Pull-up current
IPULL
–250
–50
*1: CMOS I/O pin (Other than hysteresis pins)
*2: Hysteresis input pins: P46/TRG, P70/ATG, P71/ESI, P80/INT0, P81/INT1, P82/OUT0/INT2, P83/OUT1/INT3,
P90/IN0, P91/IN1, P92/IN2, P93/IN3/CKOT, P94/SIN0, P96/SCK0, PA0/SIN1,
PA2/SCK1, PA3/SIN2, PA5/SCK2
*3: Mode pins MD2 to MD0
*4: Open-drain pins P94 to P96 and PA0 to PA5: Set by registers
*5: Pins with pull-up resistor RST and P00 to P27: Set by registers
50
MB90230 Series
4. AC Characteristics
(1) Clock Timing Standards
(VCC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Symbol Pin name
Condition
Unit
Remarks
Parameter
Min.
Max.
X0
X1
Clock frequency
fC
VCC = 5.0 V ±5%
VCC = 5.0 V ±5%
VCC = 5.0 V ±5%
—
1
16
MHz
ns
X0
X1
Clock cycle time
tC
62.5
25.0
5
—
—
10
PWH
PWL
Input clock pulse width
X0
X0
ns
Duty = 60%
Input clock rising/falling
time
tcr
tcf
ns
tc
0.8 VCC
0.2 VCC
PWH
PWL
tcf
tcr
51
MB90230 Series
(2) Reset, Hardware Standby, and Trigger Input Standards
(VCC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
Symbol
Condition
Unit
Remarks
Parameter
Reset input time
name
Min.
Max.
—
tRSTL
RST
HST
ATG
TRG
—
—
—
—
5
5
5
5
Machine cycle*
Machine cycle*
Machine cycle*
Machine cycle*
Hardware standby input time tHSTL
—
A/D start trigger input time
PPG start trigger input time
tATGX
—
tPPGL
—
IN0 to
IN3
Input capture input trigger
tINP
—
5
—
Machine cycle*
*Machine cycle: tCYC = 1/machine clock = 1/(fC ÷ N)
fC: Oscillation frequency
N: Gear divide ratio (1, 2, 4, 16)
Note: Clock input is required during reset.
The machine cycle at hardware standby input is set to 1/32 divided oscillation.
tRSTL, tHSTL, tINP
tATGX, tPPGT
RST
HST
ATG
TRG
IN0 to IN3
52
MB90230 Series
(3) Power-on Reset
Parameter
(VCC = +5.0 V ±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Symbol Pin name Condition
Unit
Remarks
Min.
—
Max.
50
Power supply riseing time
Power-off time
tR
ms
ms
Vcc
—
tOFF
1
—
tR
Vcc
4.5 V
0.2 V
tOFF
Keep in mind that abrupt changes in supply voltage may cause a power-on reset.
Vcc 5 V
It is recommended to keep the
3 V
rising speed of the supply voltage
at 50 mV/ms or slower.
RAM data refined
Vss
53
MB90230 Series
(4) UART Timing
(VCC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
name
Symbol
Condition
Unit Remarks
Parameter
Min. Max.
Serial clock cycle time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
—
—
—
—
—
—
—
—
—
8 tCYC
–80
100
60
—
80
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output
pin: CL = 80 pF
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
SCK ↑ → Valid SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
—
4 tCYC
4 tCYC
—
—
—
External clock
operation output
pin: CL = 80 pF
150
—
60
SCK ↑ → Valid SIN hold time
60
—
Notes: • These AC characteristics assume the CLK synchronous mode.
• CL is the value for load capacity applied to the pin under testing.
• tCYC is the machine cycle (in nanoseconds).
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
tSHIX
2.4 V
0.8 V
2.4 V
0.8 V
SIN
• External shift clock mode
tSLSH
tSHSL
2.4 V
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
SOT
SIN
tIVSH
tSHIX
2.4 V
0.8 V
2.4 V
0.8 V
54
MB90230 Series
(5) Extended Serial I/O Timing
Parameter
(VCC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
name
Symbol
Condition
Unit
Remarks
Min. Max.
Serial clock cycle time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
—
—
—
—
—
—
—
—
—
8 tCYC
50
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
Internal clock
operationoutput
pin: CL = 80 pF
1 tCYC
1 tCYC
250
SCK ↑ → Valid SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
Externalclock:
2 MHz max.
250
External clock
operationoutput 2 tCYC
pin: CL = 80 pF
1 tCYC
SCK ↑ → Valid SIN hold time
2 tCYC
Notes: • CL is the value for load capacity applied to the pin under testing.
• tCYC is the machine cycle (in nanoseconds).
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
tSHIX
2.4 V
0.8 V
2.4 V
0.8 V
SIN
• External shift clock mode
tSLSH
tSHSL
2.4 V
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
SOT
SIN
tIVSH
tSHIX
2.4 V
0.8 V
2.4 V
0.8 V
55
MB90230 Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +5.0 V ± 5%, AVSS = VSS = 0.0 V, +3.0 V ≤ AVRH – AVRL, TA = –40°C to +70°C)
Value
Symbol
Pin name
Unit
Parameter
Min.
Typ.
Max.
10
Resolution
—
10
bit
LSB
LSB
LSB
LSB
LSB
µs
Total error
—
—
±3.0
±2.0
±1.5
+2.5
AVRH +0.5
—
—
—
Linearity error
—
—
Differential linearity error
Zero transition voltage
Full-scale transition voltage
Conversion time
—
—
VOT
VFST
—
–1.5
+0.5
AN0 to AN7
fC = 16 MHz
AN0 to AN7
AVRH –4.5
AVRH –1.5
5.00
—
—
—
—
—
—
5
Analog port input current
Analog input voltage
IAIN
10
µA
AVRL
AVRL
0
AVRH
AVCC
AVRH
—
V
—
AVRH
AVRL
V
Reference voltage
V
IA
IAS
IR
—
mA
µA
Power supply current
AVCC
—
—
200
—
—
5*
—
—
µA
Reference voltage supply
current
AVRH
IRS
—
—
5*
µA
Variation between channels
AN0 to AN7
—
4
LSB
* : Current applied in CPU stop mode with the A/D converter inactive (VCC = AVCC = AVRH = 5.5 V).
Notes: • The error becomes larger as |AVRH–AVRL| becomes smaller.
• Use the output impedance of the external circuit for analog input under the following conditions: External
circuit output impedance < Approx. 7 kΩ
• If the output impedance the external circuit is too high, the analog voltage sampling time may be insufficient.
(Sampling time = 3.0 µs at a machine clock frequency of 16 MHz)
• Analog Input Circuit Mode
C0
Analog input
Comparator
RON2
RON1
C1
RON2 + RON2 = Approx. 3 kΩ
C0 = Approx. 60 pF
C1 = Approx. 4 pF
Note: The values shown here are reference values.
56
MB90230 Series
6. A/D Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024
• Total error
Difference between actual and logical values. This error is caused by a zero transition error, full-scale transition
error, linearity error, differential linearity error, or by noise.
• Linearity error
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics
• Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
Digital output
11 1111 1111
11 1111 1110
•
•
•
(1LSB × N + VOT)
•
•
•
•
•
•
•
Linearity error
•
00 0000 0010
00 0000 0001
00 0000 0000
Analog input
VOT
VNT V(N+1)T
VFST
VFST − VOT
1LSB
=
=
1022
VNT − (1LSB × N + VOT )
(LSB)
(LSB)
Linearity error
1LSB
V( N+1)T − VNT
− 1
Differential linearity error =
1LSB
57
MB90230 Series
7. D/A Converter Electrical Characteristics
(AVCC = VCC = +5.0 V±5%, AVSS = VSS = 0.0 V, TA = –40°C to +70°C)
Value
Typ.
8
Symbol
Pin name
Unit
Parameter
Resolution
Min.
—
Max.
8
—
—
—
—
—
—
—
—
bit
LSB
µs
Differential linearity error
Conversion time
—
—
±0.9
20*
—
—
10*
28
Analog output impedance
—
KΩ
*: A load capacity of 20 pF is assumed.
58
MB90230 Series
8. Serial E2PROM Interface Timing
(1) E2PROM interface at an operation clock frequency of 1 MHz
(VCC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Typ.
—
Parameter
Operation cycle
Symbol
Unit
Remarks
Min.
1.0
0.4
0.4
0.3
0.0
0.3
0.5
0.0
0.4
0.4
0.8
Max.
—
tSK
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Clock “H” time
tSKH
tSKL
tCSS
tCSH
tPD
0.5
0.5
—
—
Clock “L” time
—
ECS setup time
ECS hold time
—
—
—
EDO data decision time
EDO output hold time
EDI setup time
—
—
tOH
—
—
tDIS
tDIH
tRCSH
tCSL
—
—
EDI hold time
—
—
READY ↑ → ECS ↓
ECS “L” time
—
—
1.0
—
(2) E2PROM interface at an operation clock frequency of 2 MHz
(VCC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Typ.
—
Parameter
Symbol
Unit
Remarks
Min.
0.5
Max.
—
Operation cycle
tSK
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Clock “H” time
tSKH
tSKL
tCSS
tCSH
tPD
0.2
0.25
0.25
—
—
Clock “L” time
0.2
—
ECS setup time
ECS hold time
0.15
0.0
—
—
—
EDO data decision time
EDO output hold time
EDI setup time
0.15
0.25
0.0
—
—
tOH
—
—
tDIS
tDIH
tRCSH
tCSL
—
—
EDI hold time
0.2
—
—
READY ↑ → ECS ↓
ECS “L” time
0.2
—
—
0.4
0.5
—
59
MB90230 Series
tSK
tSKH
tSKL
ESK
tPD
tOH
EDO
Determined data
Determined data
tCSH
tCSS
ECS
EDI
tDIS
tDIH
Input data
Input data
tCSL
ECS
tST
DO
Hi-z
BUSY
READY
(E2PROM output)
MB90230 series
E2PROM
ECS
ESK
EDO
EDI
ECS
ESK
EDI
EDO
60
MB90230 Series
■ INSTRUCTIONS (412 INSTRUCTIONS)
Table 1 Description of Instruction Table
Description
Item
Mnemonic
Upper-case letters and symbols: Described directry in assembly code
Lower-case letters: Replaced when described in assembly code
Numbers after lower-case letters: Indicates the bit width within the code
#
~
Indicates the number of bytes
Indicates the number of cycles
See Table 4 for details about meanings of letters in items.
B
Indicates the compensation value for calculating the number of actual cycles during
execution of instruction.
The number of actual cycles during execution of instruction is summed with the value in
the “cycles” column.
Operation
LH
Indicates operation of instruction.
Indicates special operations involving the bits 15 through 08 of the accumulator.
Z: Transfers “0”
X: Extends before transferring
—: No transfer
AH
Indicates special operations involving the high-order 16 bits in the accumulator.
*: Transfers from AL to AH
—: No transfer
Z: Transfers 00H to AH.
X: Transfers 00H or FFH to AH by extending AL
I
S
Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky
bit), N (negative), Z (zero), V (overflow), and C (carry).
*: Changes due to execution of instruction.
—: No change.
T
S: Set by execution of instruction.
R: Reset by execution of instruction.
N
Z
V
C
RMW
Indicates whether the instruction is a read-modify-write instruction (a single instruction
that reads data from memory, etc., processes the data, and then writes the result to
memory.).
*: Instruction is a read-modify-write instruction
—: Instruction is not a read-modify-write instruction
Note: Cannot be used for addresses that have different meanings depending on
whether they are read or written.
61
MB90230 Series
Table 2 Explanation of Symbols in Table of Instructions
Description
Symbol
A
32-bit accumulator
The number of bits used varies according to the instruction.
Byte: Low order 8 bits of AL
Word: 16 bits of AL
Long: 32 bits of AL, AH
AH
AL
High-order 16 bits of A
Low-order 16 bits of A
SP
Stack pointer (USP or SSP)
Program counter
PC
SPCU
SPCL
PCB
DTB
ADB
SSB
USB
SPB
DPR
brg1
brg2
Ri
Stack pointer upper limit register
Stack pointer lower limit register
Program bank register
Data bank register
Additional data bank register
System stack bank register
User stack bank register
Current stack bank register (SSB or USB)
Direct page register
DTB, ADB, SSB, USB, DPR, PCB, SPB
DTB, ADB, SSB, USB, DPR, SPB
R0, R1, R2, R3, R4, R5, R6, R7
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RW0, RW1, RW2, RW3
RWi
RWj
RLi
RL0, RL1, RL2, RL3
dir
addr16
Compact direct addressing
Direct addressing
addr24
addr24 0 to 15
addr24 16 to 23
Physical direct addressing
Bits 0 to 15 of addr24
Bits 16 to 23 of addr24
io
I/O area (000000H to 0000FFH)
#imm4
#imm8
#imm16
#imm32
ext (imm8)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data
disp8
disp16
8-bit displacement
16-bit displacement
bp
Bit offset value
vct4
vct8
Vector number (0 to 15)
Vector number (0 to 255)
( )b
Bit address
rel
ear
eam
Branch specification relative to PC
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
rlst
Register list
62
MB90230 Series
Table 3 Effective Address Fields
Address format
Number of bytes in
address extemsion*
Code
Notation
00
01
02
03
04
05
06
07
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
RL0 Register direct
(RL0) “ea” corresponds to byte, word, and
RL1 long-word types, starting from the
(RL1) left
RL2
(RL2)
RL3
(RL3)
—
08
09
0A
0B
@RW0
Register indirect
0
0
1
@RW1
@RW2
@RW3
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacemen
2
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + dip16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
0
0
2
2
* : The number of bytes for address extension is indicated by the “+” symbol in the “#” (number of bytes) column in
the Table of Instructions.
63
MB90230 Series
Table 4 Number of Execution Cycles for Each Form of Addressing
(a)*
Code
Operand
Number of execution cycles for each from of addressing
Listed in Table of Instructions
00 to 07
Ri
RWi
RLi
08 to 0B
0C to 0F
10 to 17
18 to 1B
@RWj
1
4
1
1
@RWj +
@RWi + disp8
@RWj + disp16
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + dip16
@addr16
2
2
2
1
* : “(a)” is used in the “cycles” (number of cycles) column and column B (correction value) in the Table of Instructions.
Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles
(b)*
(c)*
(d)*
Operand
byte
word
long
Internal register
+
+
+
+
+
+
0
0
0
1
1
1
+
+
+
+
+
+
0
0
1
1
3
3
+
+
+
+
+
+
0
0
2
2
6
6
Internal RAM even address
Internal RAM odd address
Even address not in internal RAM
Odd address not in internal RAM
External data bus (8 bits)
* : “(b)”, “(c)”, and “(d)” are used in the “cycles” (number of cycles) column and column B (correction value) in the
Table of Instructions.
64
MB90230 Series
Table 6 Transfer Instructions (Byte) [50 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
A, dir
2
3
1
2
2
2
1
1
(b) byte (A) ← (dir)
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
*
*
*
*
*
*
*
–
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A, addr16
A, Ri
(b) byte (A) ← (addr16)
0
0
byte (A) ← (Ri)
byte (A) ← (ear)
A, ear
A, eam
2+ 2+ (a) (b) byte (A) ← (eam)
A, io
2
2
2
3
3
5
2
1
2
2
2
6
3
3
2
1
(b) byte (A) ← (io)
A, #imm8
A, @A
0
byte (A) ← imm8
(b) byte (A) ← ((A))
A, @RLi+disp8
A, @SP+disp8
(b) byte (A) ← ((RLi))+disp8)
(b) byte (A) ← ((SP)+disp8)
(b) byte (A) ←(addr24)
(b) byte (A) ← ((A))
MOVP A, addr24
MOVP A, @A
MOVN A, #imm4
0
byte (A) ← imm4
MOVX A, dir
2
3
2
2
2
2
1
1
(b) byte (A) ← (dir)
X
X
X
X
X
X
X
X
*
*
*
*
*
*
*
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVX A, addr16
MOVX A, Ri
(b) byte (A) ← (addr16)
0
0
byte (A) ← (Ri)
byte (A) ← (ear)
MOVX A, ear
MOVX A, eam
2+ 2+ (a) (b) byte (A) ← (eam)
MOVX A, io
2
2
2
2
3
3
5
2
2
2
2
3
6
3
3
2
(b) byte (A) ← (io)
byte (A) ← imm8
(b) byte (A) ← ((A))
MOVX A, #imm8
MOVX A, @A
0
MOVX A,@RWi+disp8
MOVX A, @RLi+disp8
MOVX A, @SP+disp8
MOVPX A, addr24
MOVPX A, @A
(b) byte (A) ← ((RWi))+disp8) X
(b) byte (A) ← ((RLi))+disp8)
(b) byte (A) ← ((SP)+disp8)
(b) byte (A) ←(addr24)
(b) byte (A) ← ((A))
X
X
X
X
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
dir, A
2
3
1
2
2
2
1
2
(b) byte (dir) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
addr16, A
Ri, A
(b) byte (addr16) ← (A)
0
0
byte (Ri) ← (A)
byte (ear) ← (A)
ear, A
eam, A
2+ 2+ (a) (b) byte (eam) ← (A)
io, A
2
3
3
5
2
6
3
3
(b) byte (io) ← (A)
@RLi+disp8, A
@SP+disp8, A
(b) byte ((RLi)) +disp8) ← (A)
(b) byte ((SP)+disp8) ← (A)
(b) byte (addr24) ← (A)
MOVP addr24, A
MOV
MOV
Ri, ear
2
2
0
byte (Ri) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Ri, eam
2+ 3+ (a) (b) byte (Ri) ← (eam)
MOVP @A, Ri
2
2
3
3
(b) byte ((A)) ← (Ri)
byte (ear) ← (Ri)
*
*
MOV
MOV
MOV
MOV
MOV
MOV
MOV
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
0
*
*
2+ 3+ (a) (b) byte (eam) ← (Ri)
*
*
2
3
3
3
2
3
3
2
0
byte (Ri) ← imm8
*
*
(b) byte (io) ← imm8
(b) byte (dir) ← imm8
–
–
*
–
–
*
0
byte (ear) ← imm8
3+ 2+ (a) (b) byte (eam) ← imm8
–
–
MOV
@AL, AH
2
2
2
3
(b) byte ((A)) ← (AH)
byte (A) ↔ (ear)
–
–
–
–
–
*
*
–
–
–
XCH
XCH
XCH
XCH
A, ear
0
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A, eam
Ri, ear
Ri, eam
2+ 3+ (a) 2× (b) byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
2+ 5+ (a) 2× (b) byte (Ri) ↔ (eam)
2
4
0
For an explanation of “(a)” and “(b)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
65
MB90230 Series
Table 7 Transfer Instructions (Word) [40 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
MOVW A, dir
MOVW A, addr16
MOVW A, SP
MOVW A, RWi
MOVW A, ear
MOVW A, eam
MOVW A, io
MOVW A, @A
MOVW A, #imm16
MOVW A, @RWi+disp8
MOVW A, @RLi+disp8
MOVW A, @SP+disp8
MOVPWA, addr24
MOVPWA, @A
#
~
B
Operation
2
3
1
1
2
2
2
2
1
1
(c) word (A) ← (dir)
(c) word (A) ← (addr16)
0
0
0
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
–
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
2+ 2+ (a) (c) word (A) ← (eam)
2
2
3
2
3
3
5
2
2
2
2
3
6
3
3
2
(c) word (A) ← (io)
(c) word (A) ← ((A))
0
word (A) ← imm16
(c) word (A) ← ((RWi) +disp8) –
(c) word (A) ← ((RLi) +disp8)
(c) word (A) ← ((SP) +disp8
(c) word (A) ← (addr24)
(c) word (A) ← ((A))
–
–
–
–
MOVW dir, A
2
3
4
1
1
2
2
2
2
2
1
2
(c) word (dir) ← (A)
(c) word (addr16) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVW addr16, A
MOVW SP, # imm16
MOVW SP, A
MOVW RWi, A
MOVW ear, A
MOVW eam, A
MOVW io, A
MOVW @RWi+disp8, A
MOVW @RLi+disp8, A
MOVW @SP+disp8, A
MOVPWaddr24, A
MOVPW@A, RWi
MOVW RWi, ear
MOVW RWi, eam
MOVW ear, RWi
MOVW eam, RWi
MOVW RWi, #imm16
MOVW io, #imm16
MOVW ear, #imm16
MOVW eam, #imm16
0
0
0
0
word (SP) ← imm16
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
2+ 2+ (a) (c) word (eam) ← (A)
2
2
3
3
5
2
2
2
3
6
3
3
3
2
(c) word (io) ← (A)
(c) word ((RWi) +disp8) ← (A) –
(c) word ((RLi) +disp8) ← (A)
(c) word ((SP) +disp8) ← (A)
(c) word (addr24) ← (A)
(c) word ((A)) ← (RWi)
–
–
–
–
–
–
–
–
–
–
–
–
0
word (RWi) ← (ear)
2+ 3+ (a) (c) word (RWi) ← (eam)
word (ear) ← (RWi)
2+ 3+ (a) (c) word (eam) ← (RWi)
2
3
0
3
4
4
2
3
2
0
word (RWi) ← imm16
(c) word (io) ← imm16
word (ear) ← imm16
0
4+ 2+ (a) (c) word (eam) ← imm16
MOVW @AL, AH
2
2
(c) word ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
XCHW A, ear
2
3
0
word (A) ↔ (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
XCHW A, eam
XCHW RWi, ear
XCHW RWi, eam
2+ 3+ (a) 2× (c) word (A) ↔ (eam)
word (RWi) ↔ (ear)
2+ 5+ (a) 2× (c) word (RWi) ↔ (eam)
2
4
0
Note: For an explanation of “(a)” and “(c)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual
Cycles.”
66
MB90230 Series
Table 8 Transfer Instructions (Long Word) [11 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
MOVL A, ear
#
~
B
Operation
2
1
0
long (A) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVL A, eam
2+ 3+ (a) (d) long (A) ← (eam)
MOVL A, # imm32
MOVL A, @SP + disp8
MOVPL A, addr24
MOVPL A, @A
5
3
5
2
3
4
4
3
0
long (A) ← imm32
(d) long (A) ← ((SP) +disp8)
(d) long (A) ← (addr24)
(d) long (A) ← ((A))
MOVPL@A, RLi
2
5
(d) long ((A)) ← (RLi)
–
–
–
–
–
*
*
–
–
–
MOVL @SP + disp8, A
MOVPL addr24, A
MOVL ear, A
3
5
2
4
4
2
(d) long ((SP) + disp8) ← (A)
(d) long (addr24) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
0
long (ear) ← (A)
MOVL eam, A
2+ 3+ (a) (d) long (eam) ← (A)
For an explanation of “(a)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
67
MB90230 Series
Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
ADD A, #imm8
#
~
B
Operation
2
2
2
2
3
2
0
byte (A) ← (A) + imm8
Z
Z
Z
Z
–
Z
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
ADD
ADD
ADD
ADD
ADD
ADDC
A, dir
A, ear
A, eam
ear, A
eam, A
A
(b) byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
0
2+ 3+ (a) (b) byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
2+ 3+ (a) 2× (b) byte (eam) ← (eam) + (A)
2
2
0
*
1
2
2
2
0
0
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear) + (C)
–
–
–
–
ADDC A, ear
ADDC A, eam
ADDDC A
2+ 3+ (a) (b) byte (A) ← (A) + (eam) + (C)
1
3
0
byte (A) ←(AH) + (AL) + (C) (Decimal) Z
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC A, ear
SUBC A, eam
SUBDC A
A, #imm8
2
2
2
2
3
2
0
byte (A) ← (A) – imm8
Z
Z
Z
Z
–
–
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
A, dir
A, ear
A, eam
ear, A
eam, A
A
(b) byte (A) ← (A) – (dir)
byte (A) ← (A) – (ear)
0
2+ 3+ (a) (b) byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
2+ 3+ (a) 2× (b) byte (eam) ← (eam) – (A)
2
2
0
*
1
2
2
2
0
0
byte (A) ← (AH) – (AL) – (C)
byte (A) ← (A) – (ear) – (C)
–
–
–
–
2+ 3+ (a) (b) byte (A) ← (A) – (eam) – (C)
1
3
0
byte (A) ←(AH) – (AL) – (C) (Decimal) Z
ADDW A
1
2
2
2
0
0
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
*
–
–
ADDW A, ear
ADDW A, eam
ADDW A, #imm16
ADDW ear, A
ADDW eam, A
ADDCW A, ear
ADDCW A, eam
2+ 3+ (a) (c) word (A) ← (A) + (eam)
3
2
2
2
0
0
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
2+ 3+ (a) 2× (c) word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
2+ 3+ (a) (c) word (A) ← (A) + (eam) + (C)
2
2
0
SUBW A
1
2
2
2
0
0
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
*
–
–
SUBW A, ear
SUBW A, eam
SUBW A, #imm16
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam
2+ 3+ (a) (c) word (A) ← (A) – (eam)
3
2
2
2
0
0
word (A) ← (A) – imm16
word (ear) ← (ear) – (A)
2+ 3+ (a) 2× (c) word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
2+ 3+ (a) (c) word (A) ← (A) – (eam) – (C)
2
2
0
ADDL A, ear
ADDL A, eam
ADDL A, #imm32
2
5
0
long (A) ← (A) + (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
2+ 6+ (a) (d) long (A) ← (A) + (eam)
5
2
4
5
0
0
long (A) ← (A) + imm32
long (A) ← (A) – (ear)
SUBL A, ear
SUBL A, eam
SUBL A, #imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
2+ 6+ (a) (d) long (A) ← (A) – (eam)
long (A) ← (A) – imm32
5
4
0
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
68
MB90230 Series
Table 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
INC
INC
ear
eam
2
2
0
byte (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
2+ 3+ (a) 2× (b) byte (eam) ← (eam) +1
DEC
DEC
ear
eam
2
2
0
byte (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
2+ 3+ (a) 2× (b) byte (eam) ← (eam) –1
INCW ear
INCW eam
2
2
0
word (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
2+ 3+ (a) 2× (c) word (eam) ← (eam) +1
DECW ear
DECW eam
2
2
0
word (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
2+ 3+ (a) 2× (c) word (eam) ← (eam) –1
INCL ear
INCL eam
2
4
0
long (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
2+ 5+ (a) 2× (d) long (eam) ← (eam) +1
DECL ear
DECL eam
2
4
0
long (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
2+ 5+ (a) 2× (d) long (eam) ← (eam) –1
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 11 Compare Instructions (Byte/Word/Long Word) [11 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
byte (AH) – (AL)
CMP
A
1
2
2
2
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMP A, ear
CMP A, eam
CMP A, #imm8
byte (A) – (ear)
2+ 2+ (a) (b) byte (A) – (eam)
2
2
0
byte (A) – imm8
CMPW A
1
2
2
2
0
0
word (AH) – (AL)
word (A) – (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW A, ear
CMPW A, eam
CMPW A, #imm16
2+ 2+ (a) (c) word (A) – (eam)
3
2
0
word (A) – imm16
CMPL A, ear
CMPL A, eam
CMPL A, #imm32
2
3
0
long (A) – (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
2+ 4+ (a) (d) long (A) – (eam)
long (A) – imm32
5
3
0
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
69
MB90230 Series
Table 12 Unsigned Multiplication and Division Instructions (Word/Long Word) [11 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
1
DIVU
A
1
0 word (AH) /byte (AL)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
Quotient → byte (AL) Remainder → byte (AH)
word (A)/byte (ear)
2
0
DIVU
DIVU
A, ear
A, eam
2
2+
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
Quotient → byte (A) Remainder → byte (ear)
word (A)/byte (eam)
6
3
*
*
Quotient → byte (A) Remainder → byte (eam)
long (A)/word (ear)
4
DIVUW A, ear
DIVUW A, eam
0
*
Quotient → word (A) Remainder → word (ear)
long (A)/word (eam)
Quotient → word (A) Remainder → word (eam)
5
7
2+
*
*
8
byte (AH) × byte (AL) → word (A)
byte (A) × byte (ear) → word (A)
byte (A) × byte (eam) → word (A)
word (AH) × word (AL) → long (A)
word (A) × word (ear) → long (A)
word (A) × word (eam) → long (A)
MULU
A
1
2
2+
1
2
2+
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
(b)
0
0
(c)
*
*
*
*
*
*
MULU A, ear
MULU A, eam
MULUW A
MULUW A, ear
MULUW A, eam
9
10
11
12
13
For an explanation of “(b)” and “(c), refer to Table 5, “Correction Values for Number of Cycle Used to Calculate
Number of Actual Cycles.”
*1: 3 when dividing into zero, 6 when an overflow occurs, and 14 normally.
*2: 3 when dividing into zero, 5 when an overflow occurs, and 13 normally.
*3: 5 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 17 + (a) normally.
*4: 3 when dividing into zero, 5 when an overflow occurs, and 21 normally.
*5: 4 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 25 + (a) normally.
*6: (b) when dividing into zero or when an overflow occurs, and 2 × (b) normally.
*7: (c) when dividing into zero or when an overflow occurs, and 2 × (c) normally.
*8: 3 when byte (AH) is zero, and 7 when byte (AH) is not 0.
*9: 3 when byte (ear) is zero, and 7 when byte (ear) is not 0.
*10: 4 + (a) when byte (eam) is zero, and 8 + (a) when byte (eam) is not 0.
*11: 3 when word (AH) is zero, and 11 when word (AH) is not 0.
*12: 3 when word (ear) is zero, and 11 when word (ear) is not 0.
*13: 4 + (a) when word (eam) is zero, and 12 + (a) when word (eam) is not 0.
70
MB90230 Series
Table 13 Signed Multiplication and Division Instructions (Word/Long Word) [11 Insturctions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
1
DIV
A
2
0 word (AH) /byte (AL)
Quotient → byte (AL) Remainder → byte (AH)
0 word (A)/byte (ear)
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
2
DIV
DIV
A, ear
A, eam
2
2+
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
Quotient → byte (A) Remainder → byte (ear)
word (A)/byte (eam)
3
6
*
*
Quotient → byte (A) Remainder → byte (eam)
4
DIVW A, ear
DIVW A, eam
0 long (A)/word (ear)
*
Quotient → word (A) Remainder → word (ear)
long (A)/word (eam)
7
5
*
*
2+
Quotient →word (A) Remainder →word (eam)
8
MUL
MUL A, ear
MUL A, eam
MULW A
MULW A, ear
MULW A, eam
A
2
2
2+
2
2
2+
0 byte (AH) × byte (AL) → word (A)
0 byte (A) × byte (ear) → word (A)
(b) byte (A) × byte (eam) → word (A)
0 word (AH) × word (AL) → long (A)
0 word (A) × word (ear) → long (A)
(b) word (A) × word (eam) → long (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
9
*
10
*
*
*
*
11
12
13
For an explanation of “(b)” and “(c)”, refer to Table 5, “Correction Values for Number of Cycles Used to Calculate
Number of Actual Cycles.”
*1: 3 when dividing into zero, 8 or 18 when an overflow occurs, and 18 normally.
*2: 3 when dividing into zero, 10 or 21 when an overflow occurs, and 22 normally.
*3: 4 + (a) when dividing into zero, 11 + (a) or 22 + (a) when an overflow occurs, and 23 + (a) normally.
*4: When the dividend is positive: 4 when dividing into zero, 10 or 29 when an overflow occurs, and 30 normally.
When the dividend is negative: 4 when dividing into zero, 11 or 30 when an overflow occurs, and 31 normally.
*5: When the dividend is positive: 4 + (a) when dividing into zero, 11 + (a) or 30 + (a) when an overflow occurs,
and 31 + (a) normally.
When the dividend is negative: 4 + (a) when dividing into zero, 12 + (a) or 31 + (a) when an overflow occurs,
and 32 + (a) normally.
*6: (b) when dividing into zero or when an overflow occurs, and 2 × (b) normally.
*7: (c) when dividing into zero or when an overflow occurs, and 2 × (c) normally.
*8: 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*9: 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
*10: 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative.
*11: 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*12: 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
*13: 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative.
Note: Which of the two values given for the number of execution cycles applies when an overflow error occurs in
a DIV or DIVW instruction depends on whether the overflow was detected before or after the operation.
71
MB90230 Series
Table 14 Logical 1 Instructions (Byte, Word) [39 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
AND
A, #imm8
A, ear
A, eam
ear, A
2
2
2
2
0
0
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
*
AND
AND
AND
AND
2+ 3+ (a) (b) byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
2+ 3+ (a) 2× (b) byte (eam) ← (eam) and (A)
2
3
0
eam, A
*
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
2
2
2
2
0
0
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
*
2+ 3+ (a) (b) byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
2+ 3+ (a) 2× (b) byte (eam) ← (eam) or (A)
2
3
0
eam, A
*
XOR A, #imm8
XOR A, ear
XOR A, eam
XOR ear, A
XOR eam, A
2
2
2
2
0
0
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
2+ 3+ (a) (b) byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
2+ 3+ (a) 2× (b) byte (eam) ← (eam) xor (A)
2
3
0
NOT
NOT
NOT
A
ear
eam
1
2
2
2
0
0
byte (A) ← not (A)
byte (ear) ← not (ear)
2+ 3+ (a) 2× (b) byte (eam) ← not (eam)
*
ANDW A
1
3
2
2
2
2
0
0
0
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
*
ANDW A, #imm16
ANDW A, ear
ANDW A, eam
ANDW ear, A
ANDW eam, A
2+ 3+ (a) (c) word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
2+ 3+ (a) 2× (c) word (eam) ← (eam) and (A)
2
3
0
*
ORW
A
1
3
2
2
2
2
0
0
0
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
*
ORW A, #imm16
ORW A, ear
ORW A, eam
ORW ear, A
2+ 3+ (a) (c) word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
2+ 3+ (a) 2× (c) word (eam) ← (eam) or (A)
2
3
0
ORW eam, A
*
XORW A
1
3
2
2
2
2
0
0
0
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
XORW A, #imm16
XORW A, ear
XORW A, eam
XORW ear, A
XORW eam, A
NOTW A
2+ 3+ (a) (c) word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
2+ 3+ (a) 2× (c) word (eam) ← (eam) xor (A)
2
3
0
1
2
2
2
0
0
word (A) ← not (A)
word (ear) ← not (ear)
NOTW ear
NOTW eam
2+ 3+ (a) 2× (c) word (eam) ← not (eam)
*
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
72
MB90230 Series
Table 15 Logical 2 Instructions (Long Word) [6 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
ANDL A, ear
ANDL A, eam
2
5
0
long (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 6+ (a) (d) long (A) ← (A) and (eam)
ORL
ORL
A, ear
A, eam
2
5
0
long (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 6+ (a) (d) long (A) ← (A) or (eam)
XORL A, ear
XORL A, eam
2
5
0
long (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 6+ (a) (d) long (A) ← (A) xor (eam)
For an explanation of “(a)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 16 Sign Inversion Instructions (Byte/Word) [6 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
NEG
A
1
2
0
byte (A) ← 0 – (A)
X
–
–
–
–
*
*
*
*
–
NEG ear
NEG eam
2
2
0
byte (ear) ← 0 – (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
2+ 3+ (a) 2× (b) byte (eam) ← 0 – (eam)
NEGW A
1
2
0
word (A) ← 0 – (A)
–
–
–
–
–
*
*
*
*
–
NEGW ear
NEGW eam
2
2
0
word (ear) ← 0 – (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
2+ 3+ (a) 2× (c) word (eam) ← 0 – (eam)
For an explanation of “(a)”, “(b)” and “(c)” and refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 17 Absolute Value Instructions (Byte/Word/Long Word) [3 Insturctions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
ABS
ABSW A
ABSL
A
2
2
2
2
2
4
0
0
0
byte (A) ← absolute value (A)
word (A) ← absolute value (A)
long (A) ← absolute value (A)
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
A
Table 18 Normalize Instructions (Long Word) [1 Instruction]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
NRML A, R0
2
*
0
long (A) ← Shifts to the position at
which “1” was set first
–
–
–
–
*
–
–
–
–
–
byte (R0) ← current shift count
* : 5 when the contents of the accumulator are all zeroes, 5 + (R0) in all other cases.
73
MB90230 Series
Table 19 Shift Instructions (Byte/Word/Long Word) [27 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
RORC A
#
~
B
Operation
2
2
2
2
0
0
byte (A) ← Right rotation with carry
byte (A) ← Left rotation with carry
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
*
*
–
–
ROLC A
RORC ear
RORC eam
ROLC ear
ROLC eam
2
2
0
byte (ear) ← Right rotation with carry
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
*
*
*
*
2+ 3+ (a) 2× (b) byte (eam) ← Right rotation with carry
byte (ear) ← Left rotation with carry
2
2
0
2+ 3+ (a) 2× (b) byte (eam) ← Left rotation with carry
1
byte (A) ← Arithmetic right barrel shift (A, R0)
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
ASR A, R0
LSR A, R0
LSL A, R0
2
2
2
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*
*
*
1
1
3
3
3
byte (A) ← Arithmetic right barrel shift (A, imm8)
byte (A) ← Logical right barrel shift (A, imm8)
byte (A) ← Logical left barrel shift (A, imm8)
ASR
LSR
LSL
A, #imm8
A, #imm8
A, #imm8
3
3
3
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*
*
*
ASRW A
LSRW A/SHRW A
LSLW A/SHLW A
1
1
1
2
2
2
0
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
R
*
*
*
*
–
–
–
*
*
*
–
–
–
1
ASRW A, R0
LSRW A, R0
LSLW A, R0
2
2
2
0
0
0
word (A) ← Arithmetic right barrel shift (A, R0) –
word (A) ← Logical right barrel shift (A, R0) –
word (A) ← Logical left barrel shift (A, R0) –
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*
*
*
1
1
3
3
3
ASRW A, #imm8
LSRW A, #imm8
LSLW A, #imm8
3
3
3
0
0
0
word (A) ← Arithmetic right barrel shift (A, imm8)
word (A) ← Logical right barrel shift (A, imm8)
word (A) ← Logical left barrel shift (A, imm8)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*
*
*
2
2
2
ASRL A, R0
LSRL A, R0
LSLL A, R0
2
2
2
0
0
0
long (A) ← Arithmetic right shift (A, R0)
long (A) ← Logical right barrel shift (A, R0)
long (A) ← Logical left barrel shift (A, R0) –
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*
*
*
4
4
4
ASRL A, #imm8
LSRL A, #imm8
LSLL A, #imm8
3
3
3
0
0
0
long (A) ← Arithmetic right shift (A, imm8)
long (A) ← Logical right barrel shift (A, imm8) –
long (A) ← Logical left barrel shift (A, imm8)
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*
*
*
–
For an explanation of “(a)” and “(b)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
*1: 3 when R0 is 0, 3 + (R0) in all other cases.
*2: 3 when R0 is 0, 4 + (R0) in all other cases.
*3: 3 when imm8 is 0, 3 + (imm8) in all other cases.
*4: 3 when imm8 is 0, 4 + (imm8) in all other cases.
74
MB90230 Series
Table 20 Branch 1 Instructions [31 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
1
BZ/BEQ
BNZ/BNE rel
BC/BLO
BNC/BHS rel
rel
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Branch when (Z) = 1
Branch when (Z) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
1
*
1
rel
*
*
*
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
1
1
BN
BP
BV
BNV
BT
BNT
BLT
BGE
BLE
BGT
BLS
BHI
BRA
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
1
*
1
*
1
*
1
*
*
*
*
*
*
*
*
1
Branch when (T) = 0
1
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
( (V) xor (N) ) or (Z) = 1
( (V) xor (N) ) or (Z) = 0
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally
1
1
1
1
1
1
*
2
2
JMP
JMP
JMP
JMP
@A
1
3
2
2+
2
2+
4
0
0
0
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
addr16
@ear
@eam
3
4+ (a)
3
4+ (a)
3
(c) word (PC) ← (eam)
word (PC) ←(ear), (PCB) ←(ear +2)
JMPP @ear *3
JMPP @eam *3
JMPP addr24
0
(d) word(PC)←(eam), (PCB)←(eam+2) –
0
word (PC) ← ad24 0 to 15
(PCB) ← ad24 16 to 23
–
CALL @ear *4
CALL @eam *4
CALL addr16 *5
CALLV #vct4 *5
CALLP @ear *6
2
2+
3
1
2
(c) word (PC) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
4
5+ (a)
2× (c) word (PC) ← (eam)
(c) word (PC) ← addr16
2× (c) Vector call linstruction
2× (c) word (PC) ← (ear) 0 to 15,
5
5
7
(PCB) ← (ear) 16 to 23
2
CALLP @eam *6
CALLP addr24 *7
8+ (a)
7
2+
4
word (PC) ← (eam) 0 to 15,
(PCB) ← (eam) 16 to 23
word (PC) ← addr 0 to 15,
(PCB) ← addr 16 to 23
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
2× (c)
Foranexplanationof“(a)”, “(c)”and“(d)”, refertoTable4, “NumberofExecutionCyclesforEachFormofAddressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
*1: 3 when branching, 2 when not branching.
*2: 3 × (c) + (b)
*3: Read (word) branch address.
*4: W: Save (word) to stack; R: Read (word) branch address.
*5: Save (word) to stack.
*6: W: Save (long word) to W stack; R: Read (long word) branch address.
*7: Save (long word) to stack.
75
MB90230 Series
Table 21 Branch 2 Instructions [20 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
1
Branch when byte (A) ≠ imm8
Branch when byte (A) ≠ imm16
CBNE A, #imm8, rel
CWBNE A, #imm16, rel
3
4
0
0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
*
*
1
1
*
CBNE
CBNE
ear, #imm8, rel
eam, #imm8, rel
Branch when byte (ear) ≠ imm8
Branch when byte (eam) ≠ imm8
Branch when word (ear) ≠ imm16
Branch when word (eam) ≠ imm16
4
4+
5
0
(b)
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
3
*
1
*
*
3
CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel
5+
(c)
2
*
DBNZ ear, rel
DBNZ eam, rel
DWBNZ ear, rel
DWBNZ eam, rel
3
3+
3
0
Branch when byte (ear) =
(ear) – 1, and (ear) ≠ 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
4
*
2
2× (b) Branch when byte (ear) =
(eam) – 1, and (eam) ≠ 0
*
4
0
Branch when word (ear) =
(ear) – 1, and (ear) ≠ 0
–
*
*
3+
2× (c) Branch when word (eam) =
(eam) – 1, and (eam) ≠ 0
14
12
13
14
9
INT
INT
INTP
INT9
RETI
#vct8
addr16
addr24
2
3
4
1
1
2
8× (c) Software interrupt
6× (c) Software interrupt
6× (c) Software interrupt
8× (c) Software interrupt
–
–
–
–
–
–
–
–
–
–
–
–
R
R
R
R
*
S
S
S
S
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
–
–
11
6× (c) Return from interrupt
RETIQ *6
*
5
6
Return from interrupt
*
*
*
*
*
*
*
(c)
2
At constant entry, save old
frame pointer to stack, set
new frame pointer, and
–
–
–
–
–
–
–
–
–
–
LINK
#imm8
5
allocate local pointer area
At constant entry, retrieve old
frame pointer from stack.
(c)
1
–
–
–
–
–
–
–
–
–
–
UNLINK
4
5
RET *7
(c)
(d)
1
1
Return from subroutine
Return from subroutine
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
RETP *8
For an explanation of “(b)”, “(c)” and “(d)”, refer to Table 5, “Correction Values for Number of Cycles Used to Calculate
Number of Actual Cycles.”
*1: 4 when branching, 3 when not branching
*2: 5 when branching, 4 when not branching
*3: 5 + (a) when branching, 4 + (a) when not branching
*4: 6 + (a) when branching, 5 + (a) when not branching
*5: 3 × (b) + 2 × (c) when an interrupt request is generated, 6 × (c) when returning from the interrupt.
*6: High-speed interrupt return instruction. When an interrupt request is detected during this instruction, the
instruction branches to the interrupt vector without performing stack operations when the interrupt is generated.
*7: Return from stack (word)
*8: Return from stack (long word)
76
MB90230 Series
Table 22 Other Control Instructions (Byte/Word/Long Word) [36 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
#
~
B
Operation
word (SP) ← (SP) –2, ((SP)) ← (A)
word (SP) ← (SP) –2, ((SP)) ← (AH)
word (SP) ← (SP) –2, ((SP)) ← (PS)
(SP) ← (SP) –2n, ((SP)) ← (rlst)
1
1
1
2
3
3
3
(c)
(c)
(c)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
4
*
*
word (A) ← ((SP)), (SP) ← (SP) +2
word (AH) ← ((SP)), (SP) ← (SP) +2
word (PS) ← ((SP)), (SP) ← (SP) +2
(rlst) ← ((SP)) , (SP) ← (SP)
POPW A
1
1
1
2
–
–
–
–
*
–
–
*
–
–
*
–
–
*
–
–
*
–
–
*
–
–
*
–
–
*
–
–
–
–
3
3
3
(c)
(c)
(c)
POPW AH
POPW PS
POPW rlst
–
–
–
2
4
–
–
–
–
–
–
–
*
*
JCTX @A
1
Context switch instruction
–
–
*
*
*
*
*
*
*
–
9
6× (c)
AND
OR
CCR, #imm8 2
CCR, #imm8 2
byte (CCR) ← (CCR) and imm8 –
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
3
3
0
0
byte (CCR) ← (CCR) or imm8
–
MOV RP, #imm8
MOV ILM, #imm8
2
2
byte (RP) ← imm8
byte (ILM) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
0
0
MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
2
2+
2
word (RWi) ← ear
word (RWi) ← eam
word(A) ← ear
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
0
0
0
0
2+ (a)
2
1+ (a)
MOVEA A, eam
2+
word (A) ← eam
*
ADDSP #imm8
ADDSP #imm16
2
3
word (SP) ← ext (imm8)
word (SP) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
3
0
0
1
MOV
MOV
MOV
A, brgl
brg2, A
brg2, #imm8
2
2
3
byte (A) ← (brgl)
byte (brg2) ← (A)
byte (brg2) ← imm8
Z
–
–
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
0
0
0
*
1
2
NOP
ADB
DTB
PCB
SPB
NCC
CMR
1
1
1
1
1
1
1
No operation
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Prefix code for AD space access
Prefix code for DT space access
Prefix code for PC space access
Prefix code for SP space access
–
–
–
–
–
–
Prefix code for no flag change
Prefix code for the common register bank
MOVW SPCU, #imm16
MOVW SPCL, #imm16
SETSPC
4
4
2
2
word (SPCU) ← (imm16)
word (SPCL) ← (imm16)
Stack check operation enable
Stack check operation disable
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
2
2
2
2
CLRSPC
5
byte (A) ← position of “1” bit in word (A)
byte (A) ← position of “1” bit in word (A) × 2
byte (A) ← position of “1” bit in word (A) × 4
BTSCN A
BTSCNSA
BTSCNDA
2
2
2
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
0
0
0
*
6
*
7
*
For an explanation of “(a)” and “(c)”, refer to Tables 4 and 5.
*1: PCB, ADB, SSB, USB, and SPB: 1 cycle
DTB: 2 cycles
DPR: 3 cycles
*2: 3 + 4 × (pop count)
*3: 3 + 4 × (push count)
*4: Pop count × (c), or push count × (c)
*5: 3 when AL is 0, 5 when AL is not 0.
*6: 4 when AL is 0, 6 when AL is not 0.
*7: 5 when AL is 0, 7 when AL is not 0.
77
MB90230 Series
Table 23 Bit Manipulation Instructions [21 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp
3
4
3
3
3
3
(b) byte (A) ← (dir:bp) b
(b) byte (A) ← (addr16:bp) b
(b) byte (A) ← (io:bp) b
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A
3
4
3
4
4
4
2× (b) bit (dir:bp) b ← (A)
2× (b) bit (addr16:bp) b ← (A)
2× (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
SETB dir:bp
SETB addr16:bp
SETB io:bp
3
4
3
4
4
4
2× (b) bit (dir:bp) b ← 1
2× (b) bit (addr16:bp) b ← 1
2× (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
CLRB dir:bp
CLRB addr16:bp
CLRB io:bp
3
4
3
4
4
4
2× (b) bit (dir:bp) b ← 0
2× (b) bit (addr16:bp) b ← 0
2× (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
1
BBC
BBC
BBC
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
(b) Branch when (dir:bp) b = 0
(b) Branch when (addr16:bp) b = 0
(b) Branch when (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
*
1
*
1
*
1
BBS
BBS
BBS
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
(b) Branch when (dir:bp) b = 1
(b) Branch when (addr16:bp) b = 1
(b) Branch when (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
*
1
*
1
*
2
Branch when (addr16:bp) b = 1, bit = 1
SBBS addr16:bp, rel
WBTS io:bp
5
3
3
2× (b)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
*
*
4
3
Wait until (io:bp) b = 1
Wait until (io:bp) b = 0
–
–
–
–
*
*
*
3
4
WBTC io:bp
*
For an explanation of “(b)”, refer to Table 5, “Correction Values for Number of Cycles Used to Calculate Number of
Actual Cycles.”
*1: 5 when branching, 4 when not branching
*2: 7 when condition is satisfied, 6 when not satisfied
*3: Undefined count
*4: Until condition is satisfied
78
MB90230 Series
Table 24 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
SWAP
SWAPW
EXT
EXTW
ZEXT
ZEXTW
#
~
B
Operation
1
1
1
1
1
1
3
2
1
2
1
2
0 byte (A) 0 to 7 ← → (A) 8 to 15
0 word (AH) ← → (AL)
0 Byte code extension
0 Word code extension
0 Byte zero extension
–
–
X
–
Z
–
–
*
–
X
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0 Word zero extension
*
Table 25 String Instructions [10 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
2
2
3
MOVS/MOVSI
MOVSD
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Byte transfer @AH+ ← @AL+, counter = RW0
Byte transfer @AH– ← @AL–, counter = RW0
*
*
*
*
3
1
1
4
SCEQ/SCEQI
SCEQD
2
2
*
*
*
*
Byte retrieval @AH+ – AL, counter = RW0
Byte retrieval @AH– – AL, counter = RW0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
4
5
5m +3
FILS/FILSI
2
Byte filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
*
2
6
MOVSW/MOVSWI
MOVSWD
2
2
Word transfer @AH+ ← @AL+, counter = RW0
Word transfer @AH– ← @AL–, counter = RW0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
2
6
1
7
SCWEQ/SCWEQI
SCWEQD
2
2
*
*
*
*
Word retrieval @AH+ – AL, counter = RW0
Word retrieval @AH– – AL, counter = RW0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
1
7
8
5m +3
2
Word filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
FILSW/FILSWI
*
m: RW0 value (counter value)
*1: 3 when RW0 is 0, 2 + 6 × (RW0) for count out, and 6n + 4 when match occurs
*2: 4 when RW0 is 0, 2 + 6 × (RW0) in any other case
*3: (b) × (RW0)
*4: (b) × n
*5: (b) × (RW0)
*6: (c) × (RW0)
*7: (c) × n
*8: (c) × (RW0)
79
MB90230 Series
Table 26 Multiple Data Transfer Instructions [18 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
1
3
MOVM @A, @RLi, #imm8
MOVM @A, eam, #imm8
MOVM addr16, @RLi, #imm8
MOVM addr16, eam, #imm8
MOVMW @A, @RLi, #imm8
MOVMW @A, eam, #imm8
MOVMW addr16, @RLi, #imm8
MOVMW addr16, eam, #imm8
MOVM @RLi, @A, #imm8
MOVM eam, @A, #imm8
MOVM @RLi, addr16, #imm8
MOVM eam, addr16, #imm8
MOVMW @RLi, @A, #imm8
MOVMW eam, @A, #imm8
MOVMW @RLi, addr16, #imm8
MOVMW eam, addr16, #imm8
MOVM bnk : addr16, *5
Multiple data trasfer byte ((A)) ← ((RLi))
Multiple data trasfer byte ((A)) ← (eam)
Multiple data trasfer byte (addr16) ← ((RLi))
Multiple data trasfer byte (addr16) ← (eam)
Multiple data trasfer word ((A)) ← ((RLi))
Multiple data trasfer word ((A)) ← (eam)
Multiple data trasfer word (addr16) ← ((RLi))
Multiple data trasfer word (addr16) ← (eam)
Multiple data trasfer byte ((RLi)) ← ((A))
Multiple data trasfer byte (eam) ← ((A))
Multiple data transfer byte ((RLi)) ← (addr16)
Multiple data transfer byte (eam) ← (addr16)
3
3+
5
5+
3
3+
5
5+
3
3+
5
5+
3
3+
5
5+
7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
2
3
*
*
1
3
*
*
3
2
*
*
4
1
*
*
4
2
*
*
4
1
*
*
4
2
*
*
3
1
*
*
3
2
*
*
3
1
*
*
3
2
*
*
4
1
Multiple data trasfer word ((RLi)) ← ((A))
Multiple data trasfer word (eam) ← ((A))
Multiple data transfer word ((RLi)) ← (addr16)
Multiple data transfer word (eam) ← (addr16)
*
*
4
2
*
*
4
1
*
*
4
2
*
*
3
1
Multiple data transfer
byte (bnk:addr16) ← (bnk:addr16)
Multiple data transfer
*
*
bnk : addr16, #imm8
MOVMW bnk : addr16, *5
4
1
7
*
–
–
–
–
–
–
–
–
–
–
*
bnk : addr16, #imm8
word (bnk:addr16) ← (bnk:addr16)
*1: 5 + imm8 × 5, 256 times when imm8 is zero.
*2: 5 + imm8 × 5 + (a), 256 times when imm8 is zero.
*3: Number of transfers × (b) × 2
*4: Number of transfers × (c) × 2
*5:The bank register specified by “bnk” is the same as for the MOVS instruction.
80
MB90230 Series
■ ORDERING INFORMATION
Model
Package
Remarks
MB90233PFV-XXX
MB90234PFV-XXX
100-pin Plastic LQFP
(FPT-100P-M05)
100-pin Plastic LQFP
(FPT-100P-M05)
MB90234PFV
Only ES
Only ES
100-pin Ceramic SQFP
(FPT-100C-C01)
MB90W234ZFV
81
MB90230 Series
■ PACKAGE DIMENSIONS
100-pin Plastic LQFP
(FPT-100P-M05)
1.50−+00..2100
.059 −+..000048
16.00±0.20(.630±.008)SQ
(Mounting height)
75
51
14.00±0.10(.551±.004)SQ
76
50
12.00
(.472)
REF
15.00
(.591)
NOM
Details of "A" part
0.15(.006)
INDEX
0.15(.006)
100
26
0.15(.006)MAX
0.40(.016)MAX
"B"
1
25
LEAD No.
"A"
0.50(.0197)TYP
0.18−+00..0038
0.127 +−00..0025
.005−+..000012
M
Details of "B" part
0.08(.003)
.007 −+..000013
0.10±0.10
(.004±.004)
(STAND OFF)
0.50±0.20(.020±.008)
0.10(.004)
0~10˚
C
1995 FUJITSU LIMITED F100007S-2C-3
Dimensions in mm (inches)
100-pin Ceramic LQFP
(FPT-100C-C01)
16.00±0.20 SQ
(.630±.008)
13.60+−0.125 SQ
.535−+..001060
12.00(.472)REF
0.50(.0197)TYP
1.70(.067)MAX
(Mounting height)
0.90(.035)REF
0.20±0.05
(.008±.002)
Details of "A" part
15.00±0.25 SQ
(.591±0.10)
0(0)MIN
STAND OFF
0.125±0.05
(.005±.002)
INDEX AREA
0.50±0.20
(.020±.008)
"A"
C
1995 FUJITSU LIMITED F100015SC-1-3
Dimensions in mm (inches)
82
MB90230 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
measurement equipment, personal or household devices, etc.).
CAUTION:
Fax: (408) 922-9179
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
http://www.fmap.com.sg/
F9901
FUJITSU LIMITED Printed in Japan
83
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