MB90246_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13505-5E

16-bit Proprietary Microcontroller

CMOS

F²MC-16F MB90246A Series

MB90246A

■ DESCRIPTION

The MB90246A series is a 16-bit microcontroller optimum to control mechatronics such as a hard disk drive unit.

The instruction set of F²MC-16F CPU core inherits AT architecture of F²MC*-16/16H family with additional

instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division

instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for

processing long word data (32-bit).

The MB90246A series contains a production addition unit as peripheral resources for enabling easy

implementation of functions supported by IIR and FIR digital filters. It also supports a wealth of peripheral functions

including:

- an 8/10-bit A/D converter having eight channels;

- an 8-bit D/A converter having three channels;

- UART;

- an 8-bit PWM timer having four channels;

- a timer having three plus one channels;

- an input capture (ICU) having two channels; and

- a DTP/external interrupt circuit having four channels.

* : F²MC stands for FUJITSU Flexible Microcontroller.

■ PACKAGE

100-pin Plastic LQFP

(FPT-100P-M05)

MB90246A Series

■ FEATURES

• Clock

Operating clock can be selected from divided-by-2, 4, 8 or 32 of oscillation (at oscillation of 32 MHz, 1 MHz

to 16 MHz).

Minimum instruction execution time of 62.5 ns (at machine clock of 16 MHz)

• CPU addressing space of 16 Mbytes

Internal addressing of 24-bit

External accessing can be performed by selecting 8/16-bit bus width (external bus mode)

• Instruction set optimized for controller applications

Rich data types (bit, byte, word, long word)

Rich addressing mode (23 types)

High code efficiency

Enhanced precision calculation realized by the 32-bit accumulator

Signed multiplication/division instruction

• Instruction set designed for high level language (C) and multi-task operations

Adoption of system stack pointer

Enhanced pointer indirect instructions

Barrel shift instructions

• Enhanced execution speed

8-byte instruction queue

• Enhanced interrupt function

Priority levels: 8 levels

External interrupt input ports: 4 ports

• Automatic data transmission function independent of CPU operation

Extended intelligent I/O service function (EI²OS)

• Low-power consumption (stand-by) mode

Sleep mode (mode in which CPU operating clock is stopped)

Stop mode (mode in which oscillation is stopped)

Hardware stand-by mode

Gear function

• Process

CMOS technology

• I/O port

General-purpose I/O ports (CMOS): 38

General-purpose I/O ports (TTL): 11

General-purpose I/O ports (N-ch open-drain): 8

Total: 57

• Timer

Timebase timer/watchdog timer: 1 channel

8-bit PWM timer: 4 channels

16-bit re-load timer: 3 channels

• 16-bit I/O timer

16-bit free-run timer: 1 channel

Input capture (ICU): 2 channels

• I/O simple serial interface

Clock synchronized transmission can be used.

• UART: 1 channel

Clock asynchronized or clock synchronized serial transmission can be selectively used.

• DTP/external interrupt circuit: 4 channels

A module for starting extended intelligent I/O service (EI²OS) and generating an external interrupt triggered

by an external input.

(Continued)

2

MB90246A Series

(Continued)

• Delayed interrupt generation module

Generates an interrupt request for switching tasks.

• 8/10-bit A/D converter: 8 channels

8-bit or 10-bit resolution can be selectively used.

Starting by an external trigger input.

• 8-bit D/A converter

Resolution: 8 bits × 3 channels

• DSP interface for the IIR filter

Function dedicated to IIR calculation

Up to eight items of results of signed multiplication of 16 × 16 bits are added.

N

M

Execution time of Yk = Σ bn Yk – n + Σ am Xk – m: 0.625 µs (When oscillation is 32 MHz and when N = M =3)

n = 0 m = 0

Up to three N and M values can be set at your disposal.

3

MB90246A Series

■ PRODUCT LINEUP

Part number

Item

MB90246A

MB90V246

Classification

ROM size

Mass-produced product

Evaluation product

None

RAM size

4 k × 8 bits

6 k × 8 bits

The number of instructions: 412

Instruction bit length: 8 bits, 16 bits

Instruction length: 1 byte to 7 bytes

Data bit length: 1 bit, 4 bits, 8 bits, 16 bits, 32 bits

Minimum execution time: 62.5 ns (at machine clock of 16 MHz)

Interrupt processing time: 1.0 µs (at machine clock of 16 MHz, minimum

value)

CPU functions

General-purpose I/O ports (CMOS output): 38

General-purpose I/O ports (TTL input): 11

General-purpose I/O ports (N-ch open-drain output): 8

Total: 57

Ports

18-bit counter

Interrupt interval: 0.256 ms, 1.024 ms, 4.096 ms, 16.384 ms

(at oscillation of 32 MHz)

Timebase timer

Reset generation interval: 3.58 ms, 14.33 ms, 28.67 ms, 57.34 ms

(at oscillation of 32 MHz, minimum value)

Watchdog timer

Number of channels: 4

Pulse interval: 0.25 µs to 32.77 ms (at oscillation of 32 MHz)

8/16-bit PWM timer

Number of channels: 3

16-bit re-load timer operation

Interval: 125 ns to 131 ms (at machine clock of 16 MHz)

External event count can be performed.

16-bit re-load timer

16-bit free-run

Number of channel: 1

timer

Overflow interrupts or intermediate bit interrupts may be generated.

16-bit

I/O timer

Input capture

Number of channel: 2

(ICU)

Rewriting a register value upon a pin input (rising, falling, or both edges)

Number of channels: 2

Clock synchronized transmission (62.5 kbps to 8 Mbps)

I/O simple serial interface

Clock asynchronized transmission (2404 bps to 500 kbps)

Clock synchronized transmission (250 kbps to 2 Mbps)

Transmission can be performed by bi-directional serial transmission or by

master/slave connection.

UART

Number of inputs: 4

DTP/external interrupt circuit Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.

External interrupt circuit or extended intelligent I/O service (EI²OS) can be used.

Delayed interrupt generation

module

An interrupt generation module for switching tasks

used in real-time operating systems.

(Continued)

4

MB90246A Series

(Continued)

Part number

MB90246A

MB90V246

Item

Conversion precision: 10-bit or 8-bit can be selectively used.

Number of inputs: 8

One-shot conversion mode (converts selected channel only once)

Continuous conversion mode (converts selected channel continuously)

Stop conversion mode (converts selected channel and stop operation repeatedly)

8/10-bit A/D converter

8-bit D/A converter

Number of channels: 3

Resolution: 8 bits

Based on the R-2R system

Function dedicated to IIR calculation

Up to 8 items of results of signed

multiplication of 16 × 16 bits are added.

DSP interface for the IIR

filter

N

M

Execution time of Yk = Σ bn Yk – n + Σ am Xk – m: 0.625 µs

n = 0 m = 0

(When oscillation is 32 MHz and when N = M = 3)

Up to three N and M values can be set at your disposal.

Low-power consumption

(stand-by) mode

Sleep/stop/hardware stand-by/gear function

Process

CMOS

Power supply voltage for

operation*

4.5 V to 5.5 V

* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”) Assurance

for the MB90V246 is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an operating

temperature of 0 to 70 degrees centigrade, and an clock frequency of 1.6 MHz to 32 MHz.

Note: A 64-word RAM for product addition is supported in addition to the above RAMs.

■ PACKAGE AND CORRESPONDING PRODUCTS

Package

FPT-100P-M05

MB90246A

MB90V246

×

PGA-256C-A02

×

: Available × : Not available

Note: For more information about each package, see section “■ Package Dimensions.”

■ DIFFERENCES AMONG PRODUCTS

Memory Size

In evaluation with an evaluation chips, note the difference between the evaluation chip and the chip actually used.

The RAM size is 4 Kbytes for the MB90246A, and 6 Kbytes for the MB90V246.

5

MB90246A Series

■ PIN ASSIGNMENT

(Top view)

1

2

3

4

5

6

7

8

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A02

A03

A04

A05

A06

A07

A08

A09

V^SS

A10

A11

A12

A13

A14

A15

P40/A16

P41/A17

P42/A18

P43/A19

P44/A20

V^CC

P45/A21

P46/A22

P47/A23

P70/ASR0

RST

P54/WRH

P53/HRQ

P52/HAK

P51/RDY

P50/CLK

PA5/SCK2

PA4/SOD2

PA3/SID2

PA2/SCK1

PA1/SOD1

PA0/SID1

P96/SCK0

P95/SOD0

P94/SID0

P93/INT3/PWM3

P92/INT2/ATG

P91/INT1

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P90/INT0

P87/PWM2

P86/PWM1

P85/PWM0

P84/DAO2

P83/DAO1

P82/DAO0

(FPT-100P-M05)

6

MB90246A Series

■ PIN DESCRIPTION

Pin no.

Pin name

LQFP*

Circuit

type

Function

80

81

X0

X1

A

This is a crystal oscillator pin.

47 to 49 MD0 to MD2

C

This is an input pin for selecting operation modes.

Connect directly to V^CCor VSS.

75

50

RST

HST

B

C

D

This is external reset request signal.

This is a hardware stand-by input pin.

91 to 98 P10 to P17

This is a general-purpose I/O port.

This function is valid in the 8-bit mode where the external bus is

valid.

D08 to D15

This is an I/O pin for the upper 8-bit of the external address data

bus.

This function is valid in the 16-bit mode where the external bus is

valid.

16 to 20, P40 to P44,

22 to 24 P45 to P47

E

This is a general-purpose I/O port.

This function becomes valid in the bit where the upper address

control register is set to select a port.

A16 to A20,

A21 to A23

This is an output pin for the upper 8-bit of the external address bus.

This function is valid in the mode where the external bus is valid

and the upper address control register is set to select an address.

70

71

P50

CLK

P51

E

D

This is a general-purpose I/O port.

This function becomes valid when the CLK output is disabled.

This is a CLK output pin.

This function becomes valid when CLK output is enabled.

This is a general-purpose I/O port.

This function becomes valid when the external ready function are

disabled.

RDY

This is a ready input pin.

This function becomes valid when the external ready function is

enabled.

72

73

74

P52

HAK

P53

HRQ

P54

D

E

This is a general-purpose I/O port.

This function becomes valid when the hold function are disabled.

This is a hold acknowledge output pin.

This function becomes valid when the hold function is enabled.

This is a general-purpose I/O port.

This function becomes valid when the hold function are disabled.

This is a hold request input pin.

This function becomes valid when the hold function is enabled.

This is a general-purpose I/O port.

This function becomes valid, in the external bus 8-bit mode, or

WRH pin output is disabled.

WRH

This is a write strobe output pin for the upper 8-bit of the data bus.

This function becomes valid when the external bus 16-bit mode is

selected, and WRH output pin is enabled.

* : FPT-100P-M05

(Continued)

7

MB90246A Series

Pin no.

Circuit

Pin name

Function

This is a general-purpose I/O port.

type

LQFP*

76

P55

WR

E

This function becomes valid when WRL/WR pin output is disabled.

This is a write strobe output pin for the lower 8-bit of data bus.

This function becomes valid when WRL/WR pin output is enabled.

WRL is used for holding the lower 8-bit for write strobe in 16-bit

access operations, while WR is used for holding 8-bit data for write

strobe in 8-bit access operations.

WRL

77

P56

RD

E

This pin cannot be used as a general-purpose port.

This is a read strobe output pin for the data bus.

This function is valid in the mode where the external bus is valid.

78,28,27 P57,P73,P72

E

This is a general-purpose I/O port.

36 to 39, P60 to P63,

41 to 44 P64 to P67

G

This is an I/O port of an N-ch open-drain type.

When the data register is read by a read instruction other than the

modify write instruction with the corresponding bit in ADER set at

“0”, the pin level is acquired. The value set in the data register is

output to the pin as is.

AN0 to AN3,

AN4 to AN7

This is an analog input pin of the 8/10-bit A/D converter.

When using this input pin, set the corresponding bit in ADER at “1”.

Also, set the corresponding bit in the data register at “1”.

25

26

P70

E

This is a general-purpose I/O port.

ASR0

This is a data input pin for input capture 0.

Because this input is used as required when the input capture 0 is

performing input operations, and it is necessary to stop outputs

from other functions unless such outputs are made intentionally.

P71

This is a general-purpose I/O port.

ASR1

This is a data input pin of input capture 1.

Because this input is used as required when input capture 1 is

performing input operations, and it is necessary to stop outputs by

other functions unless such outputs are made intentionally.

29 to 31 P74 to P76

TIN0 to TIN 2

This is a general-purpose I/O port.

This function becomes valid when outputs from 16-bit re-load timer

0 – 2 are disabled.

This is an input pin of 16-bit timer.

Because this input is used as required whin 16-bit timer 0 - 2 is

performing input operations,and it is necessary to stop outputs by

other functions unless such outputs are made intentionally.

TOT0 to TOT2

51 to 53 P82 to P84

DAO0 to DAO2

These are output pins for 16-bit re-load timer 0 and 1.

This function becomes valid when output from 16-bit re-load timer

0 – 2 are enabled.

H

This is a general-purpose I/O port.

This function becomes valid when data output from 8-bit D/A

converter 0 – 2 are disabled.

This is an output pin of 8-bit D/A converter.

This function becomes valid when data output from 8-bit D/A

converter 0 – 2 are enabled.

* : FPT-100P-M05

(Continued)

8

MB90246A Series

Pin no.

LQFP*

Circuit

type

Pin name

Function

54 to 56 P85 to P87

E

This is a general-purpose I/O port.

This function becomes valid when output from PWM0 – PWM2 are

disabled.

PWM0 to PWM2

This is an output pin of 8-bit PWM timer.

This function becomes valid when output from PWM0 – PWM2 are

enabled.

57,

58

P90,

P91

F

This is a general-purpose I/O port.

INT0,

INT1

This is a request input pin of the DTP/external interrupt circuit ch.0

and 1.

Because this input is used as required when the DTP/external

interrupt circuit is performing input operations, and it is necessary

to stop outputs from other functions unless such outputs are made

intentionally.

59

60

61

P92

E

This is a general-purpose I/O port.

INT2

This is an input pin of the DTP/external interrupt circuit ch.2.

Because this input is used as required when the DTP/external

interrupt circuit is performing input operations, and it is necessary

to stop outputs from other functions unless such outputs are made

intentionally.

ATG

This is a trigger input pin of the 8/10-bit A/D converter.

Because this input is used as requited when the 8/10-bit A/D

converter is performing input operations, and it is necessary to

stop outputs by other functions unless such outputs are made

intentionally.

P93

This is a general-purpose I/O port.

This function is always valid.

This function becomes valid when output from PWM3 is disabled.

INT3

This is a request input of the DTP/external interrupt circuit

ch. 3.

Because this input is used as required when the DTP/external

interrupt circuit is performing input operations, and it is necessary

to stop outputs from other functions unless such output are made

intentionally.

PWM3

P94

This is an output pin of 8-bit PWM timer.

This function becomes valid when output from PWM3 is enabled.

This is a general-purpose I/O port.

This function becomes valid when serial data output from UART is

disabled.

SID0

This is a serial data I/O pin of UART.

This function becomes valid when serial data output from UART is

enabled.

Because this input is used as required when UART is performing

input operations, and it is necessary to stop outputs by other

functions unless such outputs are made intentionally.

* : FPT-100P-M05

(Continued)

9

MB90246A Series

Pin no.

Circuit

Pin name

Function

This is a general-purpose I/O port.

type

LQFP*

62

P95

E

This function becomes valid when data output from UART is

disabled.

SOD0

P96

This is a data output pin of UART.

This function becomes valid when data output from UART is

enabled.

63

E

This is a general-purpose I/O port.

This function becomes valid when clock output from UART is

disabled.

SCK0

This is a clock I/O pin of UART.

This function becomes valid when clock output from UART is

enabled.

Because this input is used as required when UART is performing

input operations, and it is necessary to stop outputs by other

functions unless such outputs are made intentionally.

1 to 6,

100,

99

A02 to A07,

A01,

A00

E

This is an output pin for the lower 8-bit of the external address bus.

7,

8,

A08,

A09,

This is an output pin for the middle 8-bit of the external address

bus.

10 to 15 A10 to A15

This function is valid in the mode where the external bus is valid

and the middle address control refister is set to select an address.

64

65

66

PA0

E

This is a general-purpose I/O port.

SID1

This is a data input pin of I/O simple serial interface 1.

Because this input is used as required when I/O simple serial

interface 1 is performing input operations, and it is necessarey to

stop outputs by other functions unless such outputs are made

intentionally.

PA1

This is a general-purpose I/O port.

This function becomes valid when data output from I/O simple

serial interface 1 is disabled.

SOD1

PA2

This is a data output pin of I/O simple serial interface 1.

This function becomes valid when data output from I/O simple

serial interface 1 is enabled.

This is a general-purpose I/O port.

This function becomes valid when clock output from I/O simple

serial interface 1 is disabled.

SCK1

This is a clock output pin of I/O simple serial interface 1.

This function becomes valid when clock output from I/O simple

serial interface 1 is enabled.

* : FPT-100P-M05

(Continued)

10

MB90246A Series

(Continued)

Pin no.

Circuit

type

Pin name

PA3

Function

LQFP*

67

E

D

This is a general-purpose I/O port.

SID2

This is a data input pin of I/O simple serial interface 2.

Because this input is used as required when is performing input

operations, and it is I/O simple serial interface 2 necessarey to stop

outputs by other functions unless such outputs are made

intentionally.

68

69

PA4

This is a general-purpose I/O port.

This function becomes valid when data output from I/O simple

serial interface 2 is disabled.

SOD2

PA5

This is a data output pin of I/O simple serial interface 2.

This function becomes valid when data output from I/O simple

serial interface 2 is enabled.

This is a general-purpose I/O port.

This function becomes valid when clock output from I/O simple

serial interface 2 is disabled.

SCK2

This is clock output pin of I/O simple serial interface 2.

This function becomes valid when clock output from I/O simple

serial interface 2 is enabled.

83 to 90 D00 to D07

This is an I/O pin for the lower 8-bit of the external data bus.

This is power supply to the digital circuit.

21,

82

V^CC

Power

supply

9,

40,

79

V^SS

Power

supply

This is a ground level of the digital circuit.

32

AV^CC

Power

supply

This is power supply to the analog circuit.

Make sure to turn on/turn off this power supply with a voltage

exceeding AV^CCapplied to VCC.

33

AVRH

Power

supply

This is a reference voltage input to the A/D converter.

Make sure to turn on/turn off this power supply with a voltage

exceeding AVRH applied to AV^CC.

34

35

45

46

AVRL

AV^SS

Power

supply

This is a reference voltage input to the A/D converter.

Power

supply

This is a ground level of the analog circuit.

DVRH

DVRL

Power

supply

This is an external reference power supply pin for the D/A

converter.

Power

supply

This is an external reference power supply pin for the D/A

converter.

* : FPT-100P-M05

11

MB90246A Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• For oscillation of 32 MHz

• Oscillation feedback resistor approx.

1 MΩ

Clock

suspension

X1

X0

N-ch

Clock input

B

• CMOS level hysteresis input

(without stand-by control)

• Pull-up resistor approx. 50 kΩ

V^CC

P-ch type trigger

R

N-ch type trigger

V^SS

Digital input

CMOS

C

• CMOS level hysteresis input

(without stand-by control)

V^CC

P-ch type trigger

R

N-ch type trigger

V^SS

Digital input

CMOS

D

• CMOS level output

• TTL level input

(with stand-by control)

Digital output

P-ch

R

Digital output

N-ch

Digital input

TTL

Standby control signal

(Continued)

12

MB90246A Series

(Continued)

Type

Circuit

Remarks

E

• CMOS level output

• CMOS level hysteresis input

(with stand-by control)

P-ch

Digital output

R

N-ch

Digital input

CMOS

Standby control signal

F

• CMOS level input

• CMOS level hysteresis input

(with stand-by control (during interrupt

disable))

P-ch

N-ch

Digital output

R

Digital input

Standby control signal

(during interrupt disable)

G

• N-ch open-drain

• CMOS level output

• CMOS level hysteresis input

• Analog input

R

Digital output

Analog input

(with analog control)

Digital input

ADER

CMOS

H

• CMOS level output

• Analog output

• CMOS level hysteresis input

(with stand-by control)

P-ch

N-ch

Digital output

R

Analog input

Digital input

Standby control signal CMOS

13

MB90246A Series

■ HANDLING DEVICES

1. Make Sure that the Voltage not Exceed the Maximum Rating (to Avoid a Latch-up)

In CMOS ICs, a latch-up phenomenon is caused when an voltage exceeding VCC or an voltage below VSS is

applied to input or output pins or a voltage exceeding the rating is applied across VCC and VSS.

When a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal

break-down of devices. To avoid the latch-up, make sure that the voltage not exceed the maximum rating.

In turning on/turning off the analog power supply, make sure the analog power voltage (AV^CC, AVRH) and analog

input voltages not exceed the digital voltage (VCC).

2. Connection of Unused Pins

Leaving unused pins open may result in abnormal operations. Clamp the pin level by connecting it to a pull-up

or a pull-down resistor.

3. Notes on Using External Clock

In using the external clock, drive X0 pin only and leave X1 pin unconnected.

• Using external clock

X0

Open

X1

MB90246A series

4. Power Supply Pins

In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to

avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to

lower the electro-magnetic emission level and abnormal operation of strobe signals caused by the rise in the

ground level, and to conform to the total current rating.

Make sure to connect V^CCand VSS pins via lowest impedance to power lines.

It is recommended to provide a bypass capacitor of around 0.1 µF between V^CCand VSS pin near the device.

5. Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass

capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and

make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand

area for stabilizing the operation.

14

MB90246A Series

6. Turning-on Sequence of Power Supply to A/D Converter, D/A Converter and Analog Inputs

Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL), D/A converter power supply and

analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC).

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure

that the voltage not exceed AVRH or AV^CC(turning on/off the analog and digital supplies simultaneously is

acceptable).

7. Connection of Unused Pins of A/D Converter

Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.

8. “MOV @AL, AH”, “MOVW @AL, AH” Instructions

When the above instruction is performed to I/O space, an unnecessary writing operation may be performed

(#FF, #FFFF) in the internal bus.

Use the compiler function for inserting an NOP instruction before the above instructions to avoid the writing

operation.

Accessing RAM space with the above instruction does not cause any problem.

9. Initialization

In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers

turning on the power again.

10.External Reset Input

To reset the internal securely, “L” level input to the RST pin must be at least 5 machine cycle.

11.HST Pin

Make sure HST pin is set to “H” level when turn on the power supply. Also make sure HST pin is never set to

“L” level, when RST pin is set to “L” level.

12.CLK Pin

X1

a case 32 MHz

STOP

To the inside

X0

2 deviding circuit

P50/CLK*

CLK output

P50 output

P50 input

*: At P50/CLK pin in the external bus mode, CLK output is selected as an initial value.

15

MB90246A Series

■ BLOCK DIAGRAM

F²MC–16F.

CPU

Interrupt controller

X0

X1

RST

HST

Clock control block

(including timebase timer)

DVRH

DVRL

8-bit

D/A converter

3

8

Port 1

8

3

P82/DAO0 to

P84/DAO2

P10/D08 to

P17/D15

16

8

Port 8

A00 to A15

D00 to D07

P85/PWM0 to

P87/PWM2

3

8-bit

P40/A16 to

P47/A23

P50/CLK

P51/RDY

P52/HAK

P53/HRQ

P54/WRH

P55/WR/WRL

P56/RD

8

External bus

PWM timer

× 4 channels

interface

2

13

P93/INT3/PWM3

DTP/external

interrupt

circuit 3

Port 4, 5

Port 7

P57

Port 9

P94/SID0

P95/SOD0

P96/SCK0

2

P72

P73

UATR

3

16-bit

re-load timer

PA0/SID1

PA1/SOD1

PA2/SCK1

PA3/SID2

PA4/SOD2

PA5/SCK2

3

P74/TIN0/TOT0 to

P76/TIN2/TOT2

4

I/O

simple serial

2

16-bit I/O timer

P70/ASR0

P71/ASR1

3

interface

Input compare

(ICU)

2

Port A

16-bit

free-run timer

DTP/external

interrupt circuit

0, 1, 2

DSP interface for

the IIR filter

3

P90/INT0

P91/INT1

Port 9

P92/INT2/ATG

RAM

AVRH

AVRL

AV^CC

8/10-bit

A/D converter

AV^SS

8

P60/AN0 to

P67/AN7

Port 6

Other pins

MD0 to MD2,

V^CC,V^SS

16

MB90246A Series

MEMORY MAP

External ROM

external bus mode

FFFFFF^H

External area

001980^H

001900^H

001100^H

I/O

External area

RAM

Register

000100^H

0000C0^H

External area

I/O

000000^H

: Internal access memory

: Enternal access memory

The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler

small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address,

enabling reference of the table on the ROM without stating “far”.

17

MB90246A Series

■ F²MC-16F CPU PROGRAMMING MODEL

(1) Dedicated Registers

: Accumlator (A)

AH

AL

Dual 16-bit register used for storing results of calculation etc. The two 16-bit

registers can be combined to be used as a 32-bit register.

: User stack pointer (USP)

The 16-bit pointer for containing a user stack address.

USP

SSP

PS

: System stack pointer (SSP)

The 16-bit pointer for displaying the status of the system stack address.

: Processor status (PS)

The 16-bit register for displaying the system status.

: Program counter (PC)

The 16-bit register for displaying storing location of the current instruction code.

PC

: User stack upper limit register (USPCU)

The 16-bit register for specifying the upper limit of the user stack.

USPCU

SSCPU

USPCL

: System stack upper limit register (SSPCU)

The 16-bit register for specifying the upper limit of the system stack.

: User stack lower limit register (USPCL)

The 16-bit register for specifying the lower limit of the user stack.

: System stack lower limit register (SSPCL)

The 16-bit register for specifying the lower limit of the system stack.

SSPCL

DPR

: Direct page register (DPR)

The 8-bit register for specifying bit 8 through 15 of the operand address in the

short direct addressing mode.

: Program bank register (PCB)

The 8-bit register for displaying the program space.

PCB

DTB

USB

SSB

: Data bank register (DTB)

The 8-bit register for displaying the data space.

: User stack bank register (USB)

The 8-bit register for displaying the user stack space.

: System stack bank register (SSB)

The 8-bit register for displaying the system stack space.

ADB

8-bit

: Additional data bank register (ADB)

The 8-bit register for displaying the additional data.

16-bit

32-bit

18

MB90246A Series

(2) General-purpose Registers

Maximum of 32 banks

RW7

R7

R6

RL3

RL2

RL1

RL0

RW6

RW5

RW4

R5

R3

R4

R2

R1

R0

RW3

RW2

RW1

RW0

000180 ^H+ (RP × 10 ^H)

16-bit

(3) Processor Status (PS)

ILM

RP

CCR

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

—

PS

ILM2 ILM1 ILM0 B4

B3

0

B2

0

B1

0

B0

0

I

S

1

T

X

N

X

Z

X

V

X

C

X

Initial value

0

— : Unused

X : Indeterminate

19

MB90246A Series

■ I/O MAP

Abbreviated

Address

Read/

write

Resource

name

Register name

Initial value

register name

(System reservation area)*¹

R/W!

000000^H

000001H

000002H

000003H

000004H

000005H

000006H

000007H

000008H

000009H

00000AH

PDR1

Port 1 data register

Port 1

X X X X X X X X B

(System reservation area)*¹

PDR4

PDR5

PDR6

PDR7

PDR8

PDR9

PDRA

Port 4 data register

Port 5 data register

Port 6 data register

Port 7 data register

Port 8 data register

Port 9 data register

Port A data register

R/W!

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

X X X X X X X X B

1 1 1 1 1 1 1 1 B

– X X X X X X X B

X X X X X X – – B

– X X X X X X X B

– – X X X X X X B

00000BH

to

(Vacancy)

00000F^H

(System reservation area)*¹

000010^H

000011H

000012H

000013H

000014H

000015H

DDR1

Port 1 direction register

R/W

Port 1

0 0 0 0 0 0 0 0 B

(System reservation area)*¹

DDR4

DDR5

Port 4 direction register

R/W

Port 4

Port 5

0 0 0 0 0 0 0 0 B

Port 5 direction register

Port 6,

8/10-bit A/D

converter

000016H

ADER

Analog input enable register

R/W

1 1 1 1 1 1 1 1 B

000017H

000018H

000019H

00001AH

DDR7

DDR8

DDR9

DDRA

Port 7 direction register

Port 8 direction register

Port 9 direction register

Port A direction register

R/W

Port 7

Port 8

Port 9

Port A

– 0 0 0 0 0 0 0 B

0 0 0 0 0 0 – – B

– X X X X X X X B

– – 0 0 0 0 0 0 B

00001BH

to

(Vacancy)

00001FH

000020H

000021H

000022H

000023H

SCR1

SSR1

Serial control status register 1

Serial status register 1

R/W

R

1 0 0 0 0 0 0 0 B

– – – – – – – 1 B

X X X X X X X X B

I/O simple serial

interface 1

SDR1L

SDR1H

Serial data register 1 (L)

Serial data register 1 (H)

R/W

(Continued)

20

MB90246A Series

Abbreviated

register name

Read/

write

Resource

Initial value

name

Address

Register name

000024^H

000025H

000026H

000027H

000028H

000029H

SCR2

SSR2

SDR2L

SDR2H

UMC

Serial control status register 2

Serial status register 2

Serial data register 2 (L)

Serial data register 2 (H)

Mode control register

Status register

R/W

R

1 0 0 0 0 0 0 0 ^B

– – – – – – – 1 B

I/O simple serial

interface 2

R/W

X X X X X X X X B

0 0 0 0 0 1 0 0 B

0 0 0 1 0 0 0 0 B

USR

UART

UIDR/

UODR

Input data register/

output data register

00002AH

00002BH

00002CH

R/W

X X X X X X X X ^B

URD

Rate and data register

0 0 0 0 0 0 0 0 B

PWM3 operating mode control

register

8-bit PWM

0 0 0 0 0 X X 1 ^B

timer 3

PWMC3

00002DH

00002E^H

00002FH

000030H

000031H

000032H

000033H

(Vacancy)

PRLL3

PRLH3

ENIR

PWM3 re-road register (L)

PWM3 re-road register (H)

DTP/interrupt enable register

DTP/interrupt factor register

Request level setting register

R/W

X X X X X X X X B

8-bit PWM

timer 3

X X X X X X X X B

– – – – 0 0 0 0 B

DTP/external

– – – – 0 0 0 0 B

interrupt circuit

EIRR

ELVR

0 0 0 0 0 0 0 0 B

(Vacancy)

PWM0 operating mode control

register

8-bit PWM

0 0 0 0 0 X X 1 B

timer 0

000034^H

PWMC0

R/W

000035H

000036H

000037H

(Vacancy)

PRLL0

PRLH0

PWM0 re-road register (L)

PWM0 re-road register (H)

R/W

X X X X X X X X B

8-bit PWM

timer 0

X X X X X X X X B

PWM1 operating mode control

register

8-bit PWM

0 0 0 0 0 X X 1 ^B

timer 1

000038H

PWMC1

R/W

000039H

00003AH

00003BH

(Vacancy)

PRLL1

PRLH1

PWM1 re-road register (L)

PWM1 re-road register (H)

R/W

X X X X X X X X B

8-bit PWM

timer 1

X X X X X X X X B

PWM2 operating mode control

register

8-bit PWM

0 0 0 0 0 X X 1 B

timer 2

00003CH

PWMC2

R/W

00003DH

00003E^H

00003FH

(Vacancy)

PRLL2

PRLH2

PWM2 re-road register (L)

PWM2 re-road register (H)

R/W

X X X X X X X X B

8-bit PWM

timer 2

X X X X X X X X B

Timer control status register 0

lower digits

000040H

000041H

R/W

0 0 0 0 0 0 0 0 ^B

16-bit re-load

TMCSR0

timer 0

Timer control status register 0

upper digits

– – – – 0 0 0 0 ^B

(Continued)

21

MB90246A Series

Abbreviated

Address

Read/

write

Resource

name

Register name

Initial value

register name

000042^H

X X X X X X X X ^B

X X X X X X X X B

X X X X X X X X ^B

X X X X X X X X B

TMR0

16-bit timer register 0

16-bit re-load register 0

R

000043H

000044H

000045H

000046H

000047^H

16-bit re-load

timer 0

TMRLR0

R/W

(Vacancy)

Timer control status register 1

lower digits

000048H

000049H

R/W

0 0 0 0 0 0 0 0 ^B

– – – – 0 0 0 0 ^B

TMCSR1

Timer control status register 1

upper digits

16-bit re-load

timer 1

00004AH

00004BH

00004CH

00004DH

00004EH

00004F^H

X X X X X X X X ^B

X X X X X X X X B

X X X X X X X X ^B

X X X X X X X X B

TMR1

16-bit timer register 1

16-bit re-load register 1

R

TMRLR1

R/W

(Vacancy)

Timer control status register 2

lower digits

000050H

000051H

R/W

0 0 0 0 0 0 0 0 ^B

– – – – 1 1 1 1 ^B

TMCSR2

Timer control status register 2

upper digits

16-bit re-load

timer 2

000052H

000053H

000054H

000055H

X X X X X X X X ^B

X X X X X X X X B

X X X X X X X X ^B

X X X X X X X X B

TMR2

16-bit timer register 2

16-bit re-load register 2

R

TMRLR2

R/W

000056H

to

(Vacancy)

000059^H

00005A^H

00005BH

00005CH

00005DH

00005EH

00005FH

000060H

000061H

000062H

000063H

000064H

DADR0

DACR0

DADR1

DACR1

DADR2

DACR2

D/A data register 0

D/A control register 0

D/A data register 1

D/A control register 1

D/A data register 2

D/A control register 2

R/W

X X X X X X X X B

– – – – – – – 0 B

X X X X X X X X B

– – – – – – – 0 B

X X X X X X X X B

– – – – – – – 0 B

X X X X X X X X ^B

X X X X X X X X B

X X X X X X X X ^B

X X X X X X X X B

0 0 0 0 0 0 0 0 B

8-bit D/A

converter 0

8-bit D/A

converter 1

8-bit D/A

converter 2

IPCP0

Input capture register 0

R

16-bit I/O timer

(input

capture 0, 1)

IPCP1

ICS0

Input capture register 1

R

Input capture control register

R/W

22

(Continued)

MB90246A Series

Abbreviated

register name

Read/

write

Resource

Initial value

name

Address

Register name

000065^H

to

(Vacancy)

00006B^H

00006CH

00006DH

00006EH

00006FH

0 0 0 0 0 0 0 0 ^B

16-bit I/O timer

TCDT

TCCS

Timer data register

R/W

(16-bit free-run

timer)

0 0 0 0 0 0 0 0 B

Timer control status register

(Vacancy)

0 0 0 0 0 0 0 0 B

A/D control status register lower

digits

000070^H

000071H

ADCSL

ADCSH

R/W

0 0 0 – 0 0 0 0 ^B

– 0 0 0 – – 0 0 B

A/D control status register upper

digits

000072H

000073H

000074H

000075H

000076H

000077H

000078H

000079H

00007AH

00007BH

X X X X X X X X ^B

X X X X X X X X B

– – – – – – * * B

X X X X X X X X B

– – – – – – * * B

X X X X X X X X B

– – – – – – * * B

X X X X X X X X B

– – – – – – * * B

ADCT

Conversion time setting register

A/D data register 0

R/W

ADTL0

ADTH0

ADTL1

ADTH1

ADTL2

ADTH2

ADTL3

ADTH3

R

8/10-bit A/D

converter

A/D data register 1

A/D data register 2

A/D data register 3

00007CH

to

(Vacancy)

00007FH

Product addition control status

register lower digits

000080^H

000081H

000082H

000083H

R/W

X X X 0 X X X 0 B

– X X X X X X X ^B

0 0 0 0 0 0 0 0 B

– – – – – – 0 0 B

MCSR

Product addition control status

register digits

Product addition continuation

control register lower digits

MCCRL

MCCRH

Product addition continuation

control register upper digits

DSP interface

for the IIR filter

000084H

000085H

000086H

000087H

000088H

X X X X X X X X ^B

X X X X X X X X B

X X X X X X X X ^B

X X X X X X X X B

MDORL

MDORM

MDORH

R

Production addition output

register

(Continued)

23

MB90246A Series

(Continued)

Abbreviated

Address

Read/

write

Resource

name

Register name

Initial value

register name

000089^H

to

(Vacancy)

00008F^H

000090^H

to

(System reservation area)*¹

00009E^H

Delayed

interrupt

generation

module

Delayed interrupt factor

generation/

cancellation register

00009FH

DIRR

R/W

– – – – – – – 0 ^B

0 0 0 1 X X X X B

Low-power

consumption

0000A0H

STBYC

Standby control register

(stand-by) mode

0000A1H

to

(System reservation area)*¹

0000A3^H

0000A4H

0000A5^H

0000A8^H

0000A9H

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

0000BDH

0000BEH

0000BFH

HACR

EPCR

WDTC

TBTC

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

Upper address control register

W

*2

External bus pin

External pin control register

Watchdog timer control register

Timebase timer control register

Interrupt control register 00

Interrupt control register 01

Interrupt control register 02

Interrupt control register 03

Interrupt control register 04

Interrupt control register 05

Interrupt control register 06

Interrupt control register 07

Interrupt control register 08

Interrupt control register 09

Interrupt control register 10

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

Interrupt control register 14

Interrupt control register 15

W

*2

X X X X X X X X B

R/W

Watchdog timer

Timebase timer

– X X 0 0 1 0 0 B

0 0 0 0 0 1 1 1 B

Interrupt

controller

0000C0H

to

(External area)*³

0000FFH

24

MB90246A Series

Descriptions for read/write

R/W: Readable and writable

R: Read only

W: Write only

R/W!: Bits for reading operation only or writing operation only are included. Refer to the register lists for specific

resource for detailed information.

Descriptions for initial value

0 : The initial value of this bit is “0”.

1 : The initial value of this bit is “1”.

X : The initial value of this bit is indeterminate.

– : This bit is not used. The initial value is indeterminate.

* : The storage type varies with the value of the ADCSH CREG bit.

*1: Access prohibited.

*2: The initial value varies with bus mode.

*3: Thisareaistheonlyexternalaccessareahavinganaddressof0000FF^Horlower. Accesstoanyoftheaddresses

specified as reserved areas in the table is handled as if an internal area were accessed. A signal for accessing

an external bus is not generated.

*4: When a register described as R/W! or W in the read/write column is accessed by a bit setting instruction or

other read modify write instructions, the bit pointed to by the instruction becomes a set value. If a bit is writable

byotherbits, however, malfunctionoccurs. Youmustnot, therefore, accessthatregisterusingtheseinstructions.

Note: For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial

value. Note that the values are different from reading results.

25

MB90246A Series

■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

Interrupt vector

Number Address

Interrupt control register

EI²OS

Priority*²

Interrupt source

support

ICR

—

Address

Reset

×

# 08

# 09

# 10

08^H

09^H

0AH

FFFFDCH

FFFFD8H

FFFFD4H

—

High

INT9 instruction

Exception

—

DTP/external interrupt circuit

Channel 0

# 11

# 13

0B^H

0D^H

FFFFD0H

FFFFC8H

ICR00

0000B0H

DTP/external interrupt circuit

Channel 1

ICR01

ICR02

0000B1H

0000B2H

Input capture (ICU) Channel 0

Input capture (ICU) Channel 1

# 15

# 17

0FH

11H

FFFFC0H

FFFFB8H

ICR03

0000B3H

I/O simple serial interface

Channel 2

# 18

# 19

# 21

12^H

13^H

15^H

FFFFB4H

FFFFB0H

FFFFA8H

DTP/external interrupt circuit

Channel 2

ICR04

ICR05

0000B4H

0000B5H

DTP/external interrupt circuit

Channel 3

16-bit free-run timer Overflow

Timebase timer Interval interrupt

16-bit re-load timer Channel 0

8-bit PWM timer Channel 0

16-bit re-load timer Channel 1

8-bit PWM timer Channel 1

16-bit re-load timer Channel 2

8-bit PWM timer Channel 2

# 23

# 25

# 27

# 28

# 29

# 30

# 31

# 32

17H

19H

1BH

1CH

1DH

1EH

1FH

20H

FFFFA0H

FFFF98H

FFFF90H

FFFF8CH

FFFF88H

FFFF84H

FFFF80H

FFFF7CH

ICR06

ICR07

0000B6H

0000B7H

ICR08*¹

ICR09*¹

ICR10*¹

0000B8H

0000B9H

0000BAH

×

8/10-bit A/D converter

measurement complete

# 33

# 34

# 35

21^H

22H

23^H

FFFF78H

FFFF74H

FFFF70H

ICR11*¹

ICR12

0000BBH

0000BCH

8-bit PWM timer Channel 3

×

I/O simple serial interface

Channel 1

UART transmission complete

UART reception complete

# 37

# 39

25H

27H

FFFF68H

FFFF60H

ICR13

ICR14

0000BDH

0000BEH

Delayed interrupt generation

module

×

# 42

2A^H

FFFF54H

FFFC00H

ICR15

—

0000BFH

—

Stack fault

# 255 FFH

Low

: Can be used

×

: Can not be used

: Can be used. With Extended intelligent I/O service (EI²OS) stop function at abnormal operation.

: Can be used if interrupt request using ICR are not commonly used.

26

MB90246A Series

*1: • Interrupt levels for peripherals that commonly use the ICR register are in the same level.

• When the extended intelligent I/O service (EI²OS) is specified in a peripheral device commonly using the ICR

register, only one of the functions can be used.

• When the extended intelligent I/O service (EI²OS) is specified for one of the peripheral functions, interrupts

can not be used on the other function.

*2: The level shows priority of same level of interrupt invoked simultaneously.

27

MB90246A Series

■ PERIPHERALS

1. I/O Port

(1) Input/output Port

Ports 1, 4, 5, 7 to 9, A are general-purpose I/O ports having a combined function as an external bus pin and a

resource input. The input output ports function as general-purpose I/O port only in the single-chip mode. In the

external bus mode, the ports are configured as external bus pins, and part of pins for port 4 can be configured

as general-purpose I/O port by setting the bus control signal select register (ECSR).

• Operation as output port

The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.

Writing data to PDR register when the port is configured as output, the data is retained in the output latch in

the PDR and directly output to the pin.

The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR

register.

Note: When a read-modify-write type instruction (e.g. bit set instruction) is performed to the port data register,

the destination bit of the operation is set to the specified value, not affecting the bits configured by the

DDR register for output, however, values of bits configured by the DDR register as inputs are changed

because input values to the pins are written into the output latch. To avoid this situation, configure the

pins by the DDR register as output after writing output data to the PDR register when configuring the bit

used as input as outputs.

• Operation as input port

The pin is configured as an input by setting the corresponding bit of the DDR register to “0”.

When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance

status.

When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs

are unaffected.

Reading the PDR register reads out the pin level (“0” or “1”).

• Block diagram

PDR (port data register)

PDR read

Output latch

P-ch

PDR write

DDR (port direction register)

N-ch

Direction latch

DDR write

Standby control (SPL=1)

DDR read

Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode

28

MB90246A Series

(2) N-ch Open-drain Port

Port6isgeneral-purposeI/Oporthavingacombinedfunctionasresourceinput/output. Eachpincanbeswitched

between resource and port bitwise.

• Operation as output port

When a data is written into the PDR register, the data is latched to the output latch of PDR. When the output

latch value is set to “0”, the output transistor is turned on and the pin status is put into an “L” level output, while

writing “1” turns off the transistor and put the pin in a high-impedance status.

If the output pin is pulled-up, setting output latch value to “1” puts the pin in the pull-up status.

Reading the PDR register returns the pin value (same as the output latch value in the PDR).

Note: Execution of a read-modify-write instruction (e.g. bit set instruction) reads out the output latch value rather

than the pin value, leaving output latch that is not manipulated unchanged.

• Operation as input port

Setting corresponding bit of the PDR register to “1” turns off the output transistor and the pin is put into a high-

impedance status.

Reading the PDR register returns the pin value (“0” or “1”).

• Block diagram

ADER (analog input enable register)

To analog input

ADER read

ADER latch

ADER write

PDR (port data register)

RMW

(read-modify-write

type instruction)

PDRread

Output trigger

Output latch

PDR write

Standby control (SPL=1)

Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode

29

MB90246A Series

(3) Register Configuration

. . . . . . . . . . . . .

bit 7

bit 0

Address

000001^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

Port 1 data register

(PDR1)

P17

R/W

P16

R/W

P15

R/W

bit 8

P14

R/W

P13

R/W

P12

R/W

P11

R/W

P10 (System reservation area)

R/W

. . . . . . . . . . . .

Address bit 15

000004^H

bit 7

bit 6

bit 5

bit 4

bit 3

P43

R/W

bit 2

P42

R/W

bit 1

P41

R/W

bit 0

P40

R/W

Port 4 data register

(PDR4)

(PDR5)

P47

R/W

P46

R/W

P45

R/W

P44

R/W

. . . . . . . . . . . . .

(PDR4)

Address

000005^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

P50

bit 0

Port 5 data register

(PDR5)

P57

R/W

P56

R/W

P55

R/W

P54

R/W

P53

R/W

P52

R/W

P51

R/W

. . . . . . . . . . . .

Address

000006^H

bit 15

bit 8 bit 7

P67

bit 6

bit 5

bit 4

bit 3

bit 2

P62

R/W

bit 1

P61

R/W

bit 0

P60

R/W

Port 6 data register

(PDR6)

(PDR7)

P66

R/W

P65

R/W

P64

R/W

P63

R/W

. . . . . . . . . . . . .

(PDR6)

Address

000007^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

P70

bit 0

Port 7 data register

(PDR7)

—

P76

R/W

P75

R/W

P74

R/W

P73

R/W

P72

R/W

P71

R/W

. . . . . . . . . . . .

Address

000008^H

bit 15

bit 8 bit 7

P87

bit 6

bit 5

bit 4

bit 3

bit 2

P82

R/W

bit 1

—

bit 0

Port 8 data register

(PDR8)

(PDR9)

P86

R/W

P85

R/W

P84

R/W

P83

R/W

—

R/W

—

. . . . . . . . . . . . .

(PDR8)

Address

000009^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

P90

bit 0

Port 9 data register

(PDR9)

—

P96

R/W

P95

R/W

P94

R/W

P93

R/W

P92

R/W

P91

R/W

. . . . . . . . . . . .

Address

00000A^H

bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

PA2

bit 1

PA1

R/W

bit 0

PA0

R/W

Port A data register

(PDRA)

(Vacancy)

—

PA5

R/W

PA4

R/W

PA3

R/W

bit 7

. . . . . . . . . . . . .

bit 0

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

Address

000011^H

Port 1 direction register

(DDR1)

(System reservation area)

P17

R/W

P16

R/W

P15

R/W

P14

R/W

P13

R/W

P12

R/W

P11

R/W

P10

R/W

. . . . . . . . . . . .

Address

000014^H

bit 15

bit 8 bit 7

P47

bit 6

bit 5

bit 4

bit 3

bit 2

P42

R/W

bit 1

P41

R/W

bit 0

P40

R/W

Port 4 direction register

(DDR4)

(DDR5)

P46

R/W

P45

R/W

P44

R/W

P43

R/W

. . . . . . . . . . . . .

(DDR4)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

P50

bit 0

Address

000015^H

Port 5 direction register

(DDR5)

P57

R/W

P56

R/W

P55

R/W

P54

R/W

P53

R/W

P52

R/W

P51

R/W

. . . . . . . . . . . .

(DDR7)

Address

000016^H

bit 15

bit 8 bit 7

P67

bit 6

bit 5

bit 4

bit 3

bit 2

P62

bit 1

P61

bit 0

P60

R/W

Analog input enable register

(ADER)

P66

R/W

P65

R/W

P64

R/W

P63

R/W

(Continued)

30

MB90246A Series

(Continued)

. . . . . . . . . . . . .

Address

000017^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

bit 7

bit 0

Port 7 direction register

(DDR7)

—

P76

P75

R/W

bit 8

P74

R/W

P73

R/W

P72

R/W

P71

R/W

P70

R/W

(ADER)

R/W

. . . . . . . . . . . .

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

P82

R/W

bit 1

—

bit 0

Address bit 15

000018^H

Port 8 direction register

(DDR8)

(DDR9)

P87

R/W

P86

R/W

P85

R/W

P84

R/W

P83

R/W

—

. . . . . . . . . . . . .

(DDR8)

Address

000019^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

P90

bit 0

Port 9 direction register

(DDR9)

—

P96

P95

P94

P93

R/W

P92

R/W

P91

R/W

. . . . . . . . . . . .

R/W

R/W R/W

R/W

. . . . . . . . . . . .

Address

00001A^H

bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

PA2

R/W

bit 1

PA1

R/W

bit 0

PA0

R/W

Port A direction register

(DDRA)

(Vacancy)

—

PA5

R/W

PA4

R/W

PA3

R/W

R/W : Readble and writable

— : Unused

31

MB90246A Series

2. Timebase Timer

The timebase timer is a 18-bit free-run counter (timebase counter) for counting up in synchronization to the

internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from

four types of 2¹³/HCLK, 2¹⁵/HCLK, 2¹⁷/HCLK, and 2¹⁹/HCLK.

The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation

stabilization time or the watchdog timer etc.

(1) Register Configuration

• Timebase timer control register (TBTC)

. . . . . . . . . . . . .

(WDTC)

bit 7

bit 0

Address

0000A9^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

Initial value

B

0XX00000

—

RESV

R/W

TBIE TBOF TBR TBC1 TBC0

R/W

W

R/W

R/W: Readable and writable

R : Read only

W : Write only

— : Unused

X : Indeterminate

RESV: Reserved bit

(2) Block Diagram

To 8-bit

PWM timer

To watchdog timer

Timebase timer

counter

× 2¹× 2²× 2³

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

. . . . . .

Divided-by-2

of HCLK

OF

To oscillation stabilization

time selector of clock control block

Power-on reset

Counter

clear circuit

Interval

timer selector

Start stop mode

CKSCR : MCS = 1→0*¹

Set TBOF

Clear TBOF

Timebase timer control register

(TBTC)

—

RESV

TBIE TBOF TBR TBC1 TBC0

Timebase timer

interrupt signal

#25(19^H)*²

OF : Overflow

HCLK: Oscillation clock

*1

*2

: Switch machine clock from oscillation clock to PLL clock

: Interrupt signal

32

MB90246A Series

3. Watchdog Timer

The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when

the counter is not cleared for a preset period of time.

(1) Register Configuration

• Watchdog timer control register (WDTC)

. . . . . . . . . . . .

(TBTC)

Address bit 15

0000A8^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

WT1

W

bit 0

WT0

W

Initial value

B

PONR STBR WRST ERST SRST WTE

XXXXXXXX

R

W

R : Read only

W: Write only

X : Indeterminate

(2) Block Diagram

Watchdog timer control register (WDTC)

PONR STBR WRST ERST SRST WTE WT1 WT0

2

Watchdog timer

CLR and start

Overflow

CLR

Start sleep mode

Start hold status

Start stop mode

Counter clear

control circuit

Count clock

selector

2-bit

counter

Watchdog reset

generation circuit

To internal reset

generation circuit

CLR

4

Clear

(Timebase timer counter)

Divided-by-2

of HCLK

× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

× 2⁸

× 2¹× 2²

. . .

HCLK: Oscillation clock

33

MB90246A Series

4. 8-bit PWM Timer

The 8-bit PWM timer is a re-load timer module that can generate a pulse wave with any period/duty ratio. It uses

pulse output control according to timer operation for PWM (Pulse Width Modulation) output.

An appropriate external circuit allows the 8-bit PWM timer to operate as a D/A converter.

The 8-bit PWM timer module consists of two 8-bit re-load registers used to specify “H” width and “L” width and

of a down counter that is loaded alternately with those values and counts down.

• A pulse waveform with any period and duty ratio is generated.

• An output pulse’s duty ratio of 0.4 to 99.6 percent can be set.

• An appropriate external circuit allows this PWM timer to operate as a D/A converter.

• An interrupt request can be generated by counter underflow.

• The count clock can be selected from two types of timebase timer output.

(1) Register Configuration

• PWM0 to 3 operating mode control register (PWM)

Address

. . . . . . . . . . . .

Initial value

bit 15

bit 8 bit 7

PEN PCKS POE

R/W R/W R/W

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PWMC0 : 000034^H

PWMC1 : 000038^H

PWMC2 : 00003C^H

PWMC3 : 00002C^H

B

00000XX1

(Vacancy)

PIE

PUF

R/W

—

RESV

R/W

B

R/W

• PWM0 to 3 re-load register (PRLL, PRLH)

Address

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Initial value

PRLH0 : 000037^H

PRLH1 : 00003B^H

PRLH2 : 00003F^H

PRLH3 : 00002F^H

PRLL0 : 000036^H

PRLL1 : 00003A^H

PRLL2 : 00003E^H

PRLL3 : 00002E^H

B

XXXXXXX1

B

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

R/W : Readable and writable

—

X

: Unused

: Indeterminate

RESV: Reserved bit

34

MB90246A Series

(2) Block Diagram

Timerbase timer output (2²/HCLK)

Timerbase timer output (2¹¹/HCLK)

P85/PWM0

P86/PWM1

P87/PWM2

Count clock

selector

PWM

output latch

Output enable

P93/INT3/PWM3

Reverse

Clear

Interrupt request

Down counter clear

#28(1C^H)

#30(1E^H)

#32(20^H)

#34(22^H)

Re-load

Re-load register

L/H selector

PWM re-load register

(PRLL)

Temporary buffer

PWM re-load register

(PRLH)

PCKS

PEN

POE PIE PUF

—

RESV

PWM operationg mode

control register

(PWMC)

Internal data bus

HCLK : Oscillation clock

35

MB90246A Series

5. 16-bit Re-load Timer

The 16-bit re-load timer has an internal clock mode for counting down in synchronization to three types of internal

clocks and an event count mode for counting down detecting a given edge of the pulse input to the external bus

pin, and either of the two functions can be selectively used.

For this timer, an “underflow” is defined as the timing of transition from the counter value of “0000^H” to “FFFFH”.

According to this definition, an underflow occurs after [re-load register setting value + 1] counts.

In operating the counter, the re-load mode for repeating counting operation after re-loading a counter value after

anunderflowortheone-shotmodeforstoppingthecountingoperationafteranunderflowcanbeselectivelyused.

Because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent

I/O service (EI²OS).

The MB90246A series has 3 channels of 16-bit re-load timers.

(1) Register Configuration

• Timer control status register 0, 1, 2 upper digits (TMCSR0, TMCSR1, TMCSR2: H)

. . . . . . . . . . . . .

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

CSL1 CSL0 MOD2 MOD1

R/W R/W R/W R/W

bit 0

Initial value

Address

TMCSR0 : 000041^H

TMCSR1 : 000049^H

TMCSR2 : 000051^H

B

- - - -0000

—

(TMCSR : L)

• Timer control status register 0, 1, 2 lower digits (TMCSR0, TMCSR1, TMCSR2: L)

. . . . . . . . . . . . .

bit 15 bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

CNTE TRG

R/W R/W

bit 0

Initial value

Address

TMCSR0 : 000040^H

TMCSR1 : 000048^H

TMCSR2 : 000050^H

B

00000000

(TMCSR : H)

MOD0 OUTE OUTL RELD INTE

R/W R/W R/W R/W R/W

UF

R/W

• 16-bit timer register 0, 1 (TMR0, TMR1, TMR2)

bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Initial value

XXXXXXXX^B

Address

TMR0 : 000042^H

TMR1 : 00004A^H

TMR2 : 000052^H

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

R

• 16-bit re-load register 0, 1 (TMRL0,TMRL1)

bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Initial value

XXXXXXXX^B

Address

TMRLR0 : 000044^H

TMRLR1 : 00004C^H

TMRLR2 : 000054^H

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

W

R/W : Readable and writable

R

: Read only

W : Write only

— : Unused

X

: Indeterminate

36

MB90246A Series

(2) Block Diagram

Internal data bus

TMRLR0*¹

<<TMRLR2>>

16-bit re-load register

Re-load signal

TMR0*¹

Re-load

control circuit

<TMR1>

<<TMR2>>

16-bit timer register (down counter) UF

CLK

Count clock generation circuit

Gate input

Wait signal

3

Valid clock

decision

circuit

φ

Prescaler

To UART (ch.1)*¹

To 8/10-bit A/D converter

(ch. 2)

Clear

CLK

Internal

clock

Output control circuit

Output

Input

control

circuit

generation circuit

Clock

selecter

Revers

EN

P74/TIN0/TOT0

<<P76/TIN2/TOT2>>

External

clock

3

2

Select

signal

P74/TIN0/TOT0

<<P76/TIN2/TOT2>>

Operation

control circuit

Function select

—

— CSL1CSL0MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG

Timer control status register (TMCSR0)*¹

Interrupt request signal

#27 (1B^H)

<<TMCSR2>>

<#29 (1D^H)>*²

<<#31 (1F^H)>>

*1: The timer has ch.0, ch.1 and ch.2, and listed in the parenthesis <> are for ch.1 and << >> for ch.2.

*2: Interrupt number

φ: Machine clock frequency

37

MB90246A Series

6. 16-bit I/O Timer

The 16-bit I/O timer module consists of one 16-bit free-run timer, two input capture (ICU) circuits, and four output

comparators.

This complex module allows two independent waveforms to be output on the basis of the 16-bit free-run timer.

Input pulse width and external clock periods can, therfore, be measured.

The 16-bit I/O timer consists of:

• a 16-bit free-run timer; and

• two input captures (ICU).

• Block diagram

Internal data bus

16-bit

free-run timer

Input capture

(ICU)

Dedicated bus

38

MB90246A Series

(1) 16-bit Free-run Timer

The 16-bit free-run timer consists of a 16-bit up counter, a prescaler, and a control register. The value output

from the timer counter is used as basic timer (base timer) for input capture (ICU).

• A counter operation clock can be selected from four internal clocks.

• An interrupt request can be issued to the CPU by counter overflow.

• The extended intelligent I/O service (EI²OS) can be activated.

• The 16-bit free-run timer counter is cleared to “0000^H” by a reset or by clearing the timer (TCCS: CLK = 0).

• Register configuration

• Timer control status register (TCCS)

. . . . . . . . . . . . .

Initial value

Address

bit 15

bit 8 bit 7

bit 6

IVF

bit 5

IVFE STOP RESV CLR CLK1 CLK0

R/W R/W R/W R/W R/W R/W

bit 4

bit 3

bit 2

bit 1

bit 0

00006E^H

(Vacancy)

RESV

B

00000000

R/W

• Timer data register (TCDT)

Initial value

Address

bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

T15 T14 T13 T12 T11 T10 T09 T08 T07 T06 T05 T04 T03 T02 T01 T00

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

B

00000000

00006D^H

00006C^H

B

R/W : Readable and writable

RESV: Reserved bit

• Block diagram

Count value output

to input capture

(ICU)

Timer data register (TCDT)

OF

16-bit free-run timer

STOP

CLK

CLR

φ

Prescaler

2

Timer control

status register

(TCCS)

RESV IVF IVFE STOP RESV CLR CLK1 CLK0

Free-run timer

interrupt request

#23 (17^H)*

: Machine clock frequency

: Overflow

: Interrupt number

φ

OF

*

39

MB90246A Series

(2) Input Capture (ICU)

The input capture (ICU) consists of a capture register corresponding to two 16-bit external input pins, a control

register, and an edge detector. Upon input of a trigger edge through an external input pin, the counter value of

the 16-bit free-run timer is stored into the input capture register, and an interrupt request can be generated

concurrently.

• A capture interrupt can be generated independently for each capture unit.

• The extended intelligent I/O service (EI²OS) can be activated.

• A trigger edge direction can be selected from rising/falling/both edges.

• Since two input capture units can be operated independent of each other, up to two events can be measured

independently.

• The input capture function is suited for measurements of intervals (frequencies) and pulse-widths.

• Register configuration

• Input capture control status register (ICS)

. . . . . . . . . . . . .

Initial value

Address

bit 15

bit 8 bit 7

bit 6

ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00

R/W R/W R/W R/W R/W R/W R/W

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

ICS0 : 000064^H

(Vacancy)

ICP1

B

00000000

R/W

• Input capture register (IPCP0, IPCP1)

Initial value

Address bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

B

XXXXXXXX

IPCP0 : 000061^H

CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

B

IPCP1 : 000063^H

IPCP0 : 000060^H

IPCP1 : 000062^H

R/W : Readable and writable

R

X

: Read only

: Indeterminate

• Block diagram

16-bit free-run timer

Edge detection circuit

P71/ASR1

Input capture register 1 (IPCP1)

Input capture register 0 (IPCP0)

P70/ASR0

Input capture

controlstatus

register(ICS)

EG11 EG10 EG01 EG00

#17 (11^H)

ICE0

ICP1 ICP0 ICE1

Input capture

interrupt request

(ICU)

#15 (OF^H)

*: Interrupt number

40

MB90246A Series

7. Simple I/O Serial Interface

The 8/16-bit simple I/O serial interface transfers data synchronously with a clock.

• Communications direction: Concurrent processing of transmission (Whether data is to be sent or received

must be judged by the user.)

• Transfer mode: Clock synchronization function (Only data are transferred.)

• Transfer rate:DC to φ/2 (φ: Machine clock. Frequencies of up to 8 MHz are available when the machine clock

is rated at 16 MHz.)

• Shift clock: A machine clock division clock is used as the shift clock. (One of four division ratios can be

selected.). A shift clock is output only during data transfer.

• Data transfer format: MSB first can be selected. 8 or 16 bits can be selected as data length. Only data are

transferred.

• Interrupt request: An interrupt request is issued upon termination of transfer.

• Inter-CPU connection: Only 1:1 (bidirectional communication)

(1) Register Configuration

• Serial control status register 1, 2 (SCR)

. . . . . . . . . . . . .

Initial value

Address

bit 15

bit 8 bit 7

STOP OCKE SOE

R/W R/W R/W

bit 6

bit 5

bit 4

bit 3

bit 2

WBS SMD1 SMD0

R/W R/W R/W

bit 1

bit 0

SCR0 : 000020^H

SCR1 : 000024^H

B

10000000

(SSR)

SIE

SIR

R/W

• Serial status register 1, 2 (SSR)

. . . . . . . . . . . . .

(SCR)

Initial value

Address

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

BUSY

bit 0

SSR1 : 000021^H

SSR2 : 000025^H

—

B

- - - - - - -1

R

• Serial data register 1, 2 (SDR)

Initial value

Address bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

B

XXXXXXXX

SDR1H : 000023^H

D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

B

SDR2H : 000027^H

SDR1L : 000022^H

SDR2L : 000026^H

R/W : Readable and writable

: Read only

— : Unused

: Indeterminate

R

X

41

MB90246A Series

(2) Block Diagram

Serial data register (SDR)

SDRH

SDRL

PA0/SID1

PA3/SID2

PA1/SOD1

PA4/SOD2

Control circuit

PA2/SCK1

PA5/SCK2

Shift clock counter

2

STOP OCKE

SMD1 SMD0

SOE SIE SIR WBS

Serial control

status register (SCR)

Serial I/O

interrupt request

#35 (23^H)*

#18 (12^H)*

—

BUSY

Serial status register (SSR)

: Machine clock frequency

: Interrupt number

φ

*

42

MB90246A Series

8. UART

UART0 is a general-purpose serial data communication interface for performing synchronous or asynchronous

communication (start-stop synchronization system). In addition to the normal duplex communication function

(normal mode), UART0 has a master-slave type communication function (multi-processor mode).

• Data buffer: Full-duplex double buffer

• Transfer mode:Clock synchronized (with start and stop bit)

Clock asynchronized (start-stop synchronization system)

• Baud rate: With dedicated baud rate generator, selectable from 12 types

External clock input possible

Internal clock (A clock supplied from 16-bit re-load timer 2 can be used.)

• Data length: 7 bit to 9 bit selective (with a parity bit)

6 bit to 8 bit selective (without a parity bit)

• Signal format: NRZ (Non Return to Zero) system

• Reception error detection: Framing error

Overrun error

Parity error (not available in multi-processor mode)

• Interrupt request: Receive interrupt (receive complete, receive error detection)

Receive interrupt (transmit complete)

Transmit/receive conforms to extended intelligent I/O service (EI²OS)

• Master/slave type communication function: 1 (master) to n (slave) communication possible

(multi-processor mode)

(1) Register Configuration

• Status register (USR)

. . . . . . . . . . . . .

(UMC)

Address

000029^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

BCH0 RBF

R/W

bit 8 bit 7

bit 0

Initial value

00010000^B

RDRF OREF

PE

R

TDRE RIE

R/W

TBF

R

• Mode control register (UMC)

. . . . . . . . . . . .

Address

000028^H

bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

00000100^B

(USR)

PEN

R/W

SBL

R/W

MC1

R/W

MC0 SMDE RFC SCKE SOE

R/W R/W R/W R/W

W

• Rate and data register (URD)

. . . . . . . . . . . . .

Address

00002B^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

bit 0

Initial value

00000000^B

BCH

R/W

RC3

R/W

RC2

R/W

RC1

R/W

RC0 BCH0

R/W R/W

P

D8

(UIDR/UODR)

R/W

• Input data register (UIDR)

. . . . .

Address

00002A^H

bit 15

bit 9 bit 8

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

D2

bit 1

D1

bit 0

D0

Initial value

XXXXXXXX^B

(URD)

D8

R

D7

R

D6

R

D5

R

D4

R

D3

R

• Output data register (UODR)

. . . . .

bit 15

bit 9 bit 8

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Address

Initial value

00002A^H

XXXXXXXX^B

(URD)

D8

W

D7

W

D6

W

D5

W

D4

W

D3

W

D2

W

D1

W

D0

W

R/W : Readable and writable

: Read only

W : Write only

: Indeterminate

R

X

43

MB90246A Series

(2) Block Diagram

Control bus

Receive

interrupt signal

#39 (27^H)*

Dedicated baud

rate generator

Transmit

clock

Transmit

interrupt signal

#37 (25^H)*

Clock

16-bit re-load

selector

timer 2

Receive

clock

Transmit

control circuit

Receive

control circuit

P96/SCK0

Start bit

detection circuit

Transmit start

circuit

Receive bit

counter

Transmit bit

counter

Receive parity

counter

Transmit parity

counter

P95/SOD0

Shift register for

reception

Shift register for

transmission

P94/SID0

Reception

complete

Start transmission

UIDR

UODR

Receive condition

decision circuit

To EI²OS reception

error generation

signal (to CPU)

Internal data bus

PEN

SBL

BCH

RDRF

ORFE

PE

RC3

RC2

RC1

RC0

BCH0

P

MC1

MC0

SMDE

RFC

SCKE

SOE

UMC

register

USR

register

URD

register

TDRE

RIE

TIE

RBF

TBF

D8

* : Interrupt number

44

MB90246A Series

9. DTP/External Interrupt Circuit

TheDTP(DataTransferPeripheral)/externalinterruptcircuitislocatedbetweenperipheralequipmentconnected

externally and the F²MC-16F CPU and transmit interrupt requests or data transfer requests generated by

peripheral equipment to the CPU, generates external interrupt request and starts the extended intelligent I/O

service (EI²OS).

(1) Register Configuration

• DTP/interrupt factor register (EIRR)

. . . . . . . . . . . .

(ENIR)

Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

000031^H

bit 9

bit 8 bit 7

bit 0

Initial value

B

RESV RESV RESV RESV ER3

ER2

R/W

ER1

R/W

ER0

R/W

- - - - 0000

—

R/W

• DTP/interrupt enable register (ENIR)

. . . . . . . . . . . .

Address bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

EN0

Initial value

000030^H

B

(EIRR)

RESV RESV RESV RESV EN3

EN2

R/W

EN1

R/W

- - - - 0000

—

R/W

• Request level setting register (ELVR)

. . . . . . . . . . . .

Address bit 15

000032^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

B

(Vacancy)

LB3

R/W

LA3

R/W

LB2

R/W

LA2

R/W

LB1

R/W

LA1

R/W

LB0

R/W

LA0

R/W

00000000

R/W: Readable and writable

— : Unused

RESV : Reserved bit

45

MB90246A Series

(2) Block Diagram

Request level setting register (ELVR)

LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

2

P93/INT3/

PWM3

Level edge

selector 3

Level edge

selector 1

Level edge

selector 2

Level edge

selector 0

P92/INT2/ATG

DTP/external interrupt input

detection circuit

P91/INT1

P90/INT0

DTP/interrupt factor register

(EIRR)

RESV RESV RESV RESV ER3 ER2 ER1 ER0

Interrupt request signal

#21 (15^H)*

#19 (13^H)*

#13 (0D^H)*

#11 (0B^H)*

DTP/interrupt enable register

(ENIR)

RESV RESV RESV RESV EN3 EN2 EN1 EN0

*: Interrupt signal

46

MB90246A Series

10. Delayed Interrupt Generation Module

The delayed interrupt generation module generates interrupts for switching tasks for development on a real-

timeoperatingsystem(REALOSseries). Themodulecanbeusedtogeneratesoftwarewisegenerateshardware

interrupt requests to the CPU and cancel the interrupts.

This module does not conform to the extended intelligent I/O service (EI²OS).

(1) Register Configuration

• Delayed interrupt factor generation/cancellation register (DIRR)

. . . . . . . . . . . .

bit 0

Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

Initial value

(System reservation area)

00009F^H

—

R0

B

- - - - - - - 0

—

R/W

R/W: Readable and writable

— : Unused

(2) Block Diagram

Internal data bus

—

R0

S factor

R latch

Interrupt request signal

#42 (2A^H)*

Delayed interrupt factor generation/

cancellation register (DIRR)

*: Interrupt signal

47

MB90246A Series

11. 8/10-bit A/D Converter

The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input

voltage) to digital values (A/D conversion) and has the following features.

• Minimum conversion time: 6.13 µs (at machine clock of 16 MHz, including sampling time)

• Minimum sampling time: 3.75 µs (at machine clock of 16 MHz)

• Conversion time: The sampling time can be set arbitrarily.

Serial to parallel converter with a sample hold circuit

• Conversion method

• Resolution: 10-bit or 8-bit selective

• Analog input pins: Selectable from eight channels by software

Single conversion mode: Single conversion for the specified channel

Scan conversion mode: Scan conversions for maximum of four channel

• Interrupt requests can be generated and the extended intelligent I/O service (EI²OS) can be started after the

end of A/D conversion.

• Starting factors for conversion: Selected from software activation, 16-bit re-load timer 1 output (rising edge),

and external trigger (falling edge).

• A data buffer that covers four channels is supported. The results of conversion are stored into the data buffer.

48

MB90246A Series

(1) Register Configuration

• A/D control status register upper digits (ADCSH)

. . . . . . . . . . . .

(ADCSL)

Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

bit 0

Initial value

000071^H

B

—

ACS2 ACS1 ACS0

R/W R/W R/W

—

CREG SCAN

R/W R/W

- 000 - - 00

• A/D control status register lower digits (ADCSL)

. . . . . . . . . . . .

Address bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

STS1 STS0 STAR RESV

R/W R/W R/W R/W

bit 2

bit 1

bit 0

Initial value

000070^H

(ADCSH)

BUSY

INT

INTE

R/W

—

B

000 - 0000

R/W

• A/D data register 0 to 3 (ADTH, ADTL)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9 bit 8 bit 7 bit 6 bit 5

bit 3 bit 2 bit 1 bit 0

bit 4

Address

Initial value

ADTH0 : 000075^H

ADTH1 : 000077^H

ADTH2 : 000079^H

ADTH3 : 00007B^H

ADTL0 : 000074^H

ADTL1 : 000076^H

ADTL2 : 000078^H

ADTL3 : 00007A^H

B

- - - - - -

XXXXXXXX

—

R

—

R

—

R

—

R

—

R

—

R

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

* *

B

R

*

• Conversion time setting register (ADCT)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

Address

000073^H

000072^H

bit 9 bit 8 bit 7 bit 6 bit 5

bit 3 bit 2 bit 1 bit 0

bit 4

Initial value

B

XXXXXXXX

SMP3 SMP2 SMP1 SMP0 CV03 CV02 CV01 CV00 CV13 CV12 CV11 CV10 CV23 CV22 CV21 CV20

B

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W

R/W

• Analog input enable register (ADER)

. . . . . . . . . . . .

Address bit 15

bit 8 bit 7

ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

R/W R/W R/W R/W R/W R/W R/W R/W

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

000016^H

(DDR7)

B

11111111

R/W: Readable and writable

R : Read only

— : Unused

X : Indeterminate

*

: The CREG bit value of ADCSH makes different storage styles.

RESV : Reserved bit

49

MB90246A Series

(2) Block Diagram

Conversion time setting register (ADCT)

SMP3 SMP2 SMP1 SMP0 CV03 CV02 CV01 CV00 CV13 CV12 CV11 CV10 CV23 CV22 CV21 CV20

4

A/D data register 0 to 3

4

ADTH0 to ADTH3, ADTL0 to ADTL3

AVRH

AVRL

AV^CC

AV^SS

P67/AN7

P66/AN6

P65/AN5

P64/AN4

P63/AN3

P62/AN2

P61/AN1

P60/AN0

Analog

channel

selector

Sample

hold

A/D converter

circuit

φ

TO

Control circuit

Clock

selector

P92/INT2/ATG

2

3

—

ACS2 ACS1 ACS0

—

CREG SCAN BUSY INT INTE

—

STS1 STS0 STAR RESV

A/D control status register (ADCS)

Interrupt request #33 (21^H)

φ : Machine clock frequency

TO : 16-bit re-load timer channel 1 output

50

MB90246A Series

12. 8-bit D/A Converter

The 8-bit D/A converter, which is based on the R-2R system, supports 8-bit resolution mode. It contains two

channels each of which can be controlled in terms of output by the D/A control register.

(1) Register Configuration

• D/A control register 0 (DACR0)

. . . . . . . . . . . . .

(DADR0)

bit 7

bit 2

bit 0

Address

00005B^H

bit 15 bit 14 bit 13

bit 11 bit 10 bit 9

bit 8

bit 12

Initial value

B

- - - - - - - 0

—

DAE0

R/W

—

• D/A control register 1 (DACR1)

. . . . . . . . . . . . .

(DADR1)

Address

00005D^H

bit 15 bit 14 bit 13

bit 11 bit 10 bit 9

bit 8

DAE1

R/W

bit 12

—

Initial value

B

- - - - - - - 0

—

• D/A control register 2 (DACR2)

. . . . . . . . . . . . .

(DADR2)

bit 15 bit 14 bit 13

bit 11 bit 10 bit 9

bit 8

bit 12

Address

00005F^H

Initial value

B

- - - - - - - 0

—

DAE2

R/W

—

• D/A data register 0 (DADR0)

. . . . . . . . . . . .

bit 15

bit 8

Address

00005A^H

bit 7

bit 6

bit 5

bit 3

bit 1

bit 0

bit 4

Initial value

B

XXXXXXXX

(DACR0)

DA07 DA06 DA05

DA03 DA02 DA01 DA00

DA04

R/W

bit 7

R/W

bit 3

R/W

• D/A data register 1 (DADR1)

. . . . . . . . . . . .

bit 15

bit 8

Address

00005C^H

bit 6

bit 5

bit 2

bit 1

bit 0

bit 4

DA14

R/W

Initial value

B

XXXXXXXX

(DACR1)

DA17 DA16 DA15

DA13 DA12 DA11 DA10

R/W

• D/A data register 2 (DADR2)

. . . . . . . . . . . .

bit 15

bit 8

bit 7

bit 6

bit 5

bit 3

bit 2

bit 1

bit 0

bit 4

DA24

R/W

Address

00005E^H

Initial value

B

XXXXXXXX

(DACR2)

DA27 DA26 DA25

R/W R/W R/W

DA23 DA22 DA21 DA20

R/W R/W R/W R/W

R/W : Readable and writable

— : Unused

X

: Indeterminate

51

MB90246A Series

(2) Block Diagram

Internal data bus

D/A data register (DADR0)

DA×7 DA×6 DA×5 DA×4 DA×3 DA×2 DA×1 DA×0

D/A converter

DVRH

DA×7

2R

R

P82/DAO0

DA×6

2R

R

DA×5

2R

R

DA×4

2R

R

DA×3

2R

R

DA×2

2R

R

DA×1

2R

R

DA×0

2R

R

DVRL

Standby control

D/A control register (DACR0)

—

DAE

Internal data bus

Note: The 8-bit D/A converter supports channels 0 to 2. A value enclosed by < and >

is for channels 1 and 2.

52

MB90246A Series

13. DSP Interface for the IIR Filter

The DSP interface for the IIR filter is a unit which covers product addition (ΣBi × Yj + ΣAm × Xn) by hardware.

This interface allows IIR filter calculation to be performed readily and in a high speed.

The DSP interface for the IIR filter has the following features.

• Coefficients A and B, and variables X and Y have 16-bit length, and four banks are supported.

• (1 to 4) + (1 to 4) product terms can be selected.

• Data can be rounded and clipped in units of 10 or 12 bits.

• With two or more concatenated banks used, the results of an operation can be transferred to the subsequent

bank register.

• Operation time: ((M + N + 1) × B + 1)/φ µs(M, N = number of product terms, B = number of banks, φ: machine

clock)

(1) Register Configuration

• Product addition control status register upper digits (MCSR:H)

. . . . . . . . . . . . .

(MCSR:L)

bit 7

bit 0

Address

000081^H

bit 15 bit 14 bit 13

bit 11 bit 10 bit 9

bit 8

bit 12

Initial value

B

- XXXXXXX

—

WEY WENY

N1

N0

M1

M0

WENX

R/W

• Product addition control status register lower digits (MCSR:L)

. . . . . . . . . . . .

bit 15

bit 8

bit 7

bit 6

bit 5

bit 3

bit 2

bit 1

bit 0

MAE

R/W

Address

bit 4

Initial value

B

XXX0XXX0

000080^H

(MCSR:H)

RND

R/W

CLP

R/W

DIV

BNK1 BNK0 TRG

BF

R

R/W

bit 7

W

• Product addition control register upper digits (MCCR:H)

. . . . . . . . . . . . .

(MCCR:L)

bit 0

Address

000083^H

bit 15 bit 14 bit 13

bit 11 bit 10 bit 9

bit 8

RESV RESV

R/W R/W

bit 12

—

Initial value

B

- - - - - - 00

—

• Product addition control register lower digits (MCCR:L)

. . . . . . . . . . . .

bit 15

bit 8

bit 7

bit 6

bit 5

bit 3

bit 2

bit 1

bit 0

Address

bit 4

Initial value

B

00000000

000082^H

(MCCR:H)

OVF CNTD CNTC

CDRD CDRC CDRB CDRA

CNTB

R/W

• Product addition output register (MDORL, M, H)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

Address

bit 9 bit 8 bit 7 bit 6 bit 5

bit 3 bit 2 bit 1 bit 0

bit 4

Initial value

B

XXXXXXXX

MDORH : 000088^H

S

R

S

R

S

R

S

R

D34 D33 D32

S

R

B

XXXXXXXX XXXXXXXX

MDORM : 000086^HD31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21

D19 D18 D17 D16

D20

R

MDORL : 000084^HD15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5

D3 D2 D1 D0

D4

R

R/W: Readable and writable

R : Read only

W : Write only

— : Unused

X : Indeterminate

RESV : Reserved bit

53

MB90246A Series

(2) Block Diagram

Internal data bus

Transfer data

selector

Transfer data

selector

Coefficient register

A0 to A3

Coefficient register

B0 to B3

Input data register

X0 to X3

Input data register

Y0 to Y3

Coefficient register

selector

Register selection

Register

selection

Bank/register

selector

Input data selector

Product addition unit

Product adder

3

4

Right shift and clip

OVF CNTD CNTC

CDRD CDRC CDRB CDRA

CNTB

Product addition control register (MCCR)

Product addition output register L

(MDORL)

Product addition output register M

(MDORM)

Product addition

output register H

(MDORH)

2

4

3

—

WEY WENY

N1

N0

M1

M0

RND CLP

DIV

BF BNK1 BNK0 TRG MAE

WENX

Product addition control status register (MCSR)

54

MB90246A Series

14. Low-power Consumption (Stand-by) Mode

The F²MC-16F has the following CPU operating mode configured by selection of an clock operation control.

• Stand-by mode

The hardware stand-by mode is a mode for reducing power consumption by stopping clock supply to the CPU

by the low-power consumption control circuit, and stopping oscillation clock (stop mode, hardware standby

mode).

Gear function contributes to the low-power dissipation by providing options of divide-by-2, 4, or 16 external

clock frequencies, whichiare usually derived from non-divided frequencies.

(1) Register Configuration

• Standby control register (STBYC)

. . . . . . . . . . . .

(Vacancy)

Address bit 15

0000A0^H

bit 8 bit 7

STP

bit 6

SLP

W

bit 5

SPL

R/W

bit 4

RST OSC1 OSC0 CLK1 CLK0

R/W R/W R/W R/W R/W

bit 3

bit 2

bit 1

bit 0

Initial value

B

0001XXXX

W

R/W : Readable and writable

W : Write only

X

: Indeterminate

55

MB90246A Series

(2) Block Diagram

Low-power consumption mode control register (STBYC)

STP SLP SPL RST OSC1 OSC0 CLK1 CLK0

Pin Hi-z control

Internal reset

high-impedance

control circuit

Internal reset

generation

circuit

RST Pin

CPU clock

control circuit

CPU clock

Cancellation of reset

RST

2

Stop and sleep signal

Standby control

circuit

Cancellation of interrupt

HST Pin

Stop signal

Machine clock

Cancellation of

oscillation

stabilization time

Peripheral clock

control circuit

Peripheral clock

Clock

generation

block

Clock selector

2

Oscillation

stabilization

time selector

2

Divided

-by-2

Divided

-by-2

Divided

-by-4

System clock

generation

circuit

Main clock

Divided

-by-2¹⁴

Divided

-by-2

Divided

-by-2

Divided

-by-2

DDC

X0

Oscillation

clock

Timebase timer

DDC: Direct duty control

56

MB90246A Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

V^CC

VSS – 0.3

VSS + 7.0

V

AVCC

*1

AVRH,

AVRL

Power supply voltage

V^SS– 0.3

VSS + 7.0

V

DVRH,

DVRL

*1

Input voltage

V^I

VSS – 0.3

VCC + 0.3

10

V

*2

*3

*4

*5

*3

*4

*5

Output voltage

VO

V

“L” level maximum output current

“L” level average output current

“L” level total average output current

“H” level maximum output current

“H” level average output current

“H” level total average output current

Power consumption

IOL

mA

mW

°C

IOLAV

ΣI^OLAV

IOH

4

50

–10

IOHAV

ΣI^OHAV

PD

–4

–48

600

Operating temperature

T^A

–30

–55

+70

Storage temperature

Tstg

+150

°C

*1: AV^CC, AVRH, AVRL, DVRH and DVRL shall never exceed VCC.

DVRL shall never exceed DVRH. AVRL shall never exceed AVRH.

*2: VI and VO shall never exceed VCC + 0.3 V.

*3: The maximum output current is a peak value for a corresponding pin.

*4: Average output current is an average current value observed for a 100 ms period for a corresponding pin.

*5: Total average current is an average current value observed for a 100 ms period for all corresponding pins.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

57

MB90246A Series

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

V^CC

4.5

5.5

V

Normal operation

Power supply voltage

Retains RAM data at the time of

operation stop

2.0

5.5

Operating temperature T^A

–30

+70

°C

External bus mode

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

58

MB90246A Series

3. DC Characteristics

Parameter Symbol

(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)

Value

Pin name

Condition

Unit Remarks

Min.

0.7 VCC

2.2

Typ.

—

Max.

V^IH

CMOS input pin

TTL input pin

—

VCC + 0.3

V

V^IH2

VCC = 5.0 V ±10%

—

“H” level

input

voltage

Hysteresis input

V^IH1S

0.8 V^CC

—

VCC + 0.3

V

—

V^IHM

VIL1

V^IL2

MD0 to MD2

CMOS input pin

TTL input pin

VCC – 0.3

—

VCC + 0.3

0.3 VCC

0.8

V

VCC = 5.0 V ±10% VCC – 0.3

“L” level

input

voltage

Hysteresis input

V^IL1S

V^ILM

V^CC– 0.3

—

0.2 VCC

V

MD0 to MD2

VCC – 0.3

VCC + 0.3

“H” level

output

voltage

All ports other

than P60 to P67 I^OH= –4.0 mA

VCC = 4.5 V

V^CC– 0.5

V^OH

—

V

“L” level

output

voltage

V^CC= 4.5 V

All output pins

V^OL

—

0.4

IOL = 4.0 mA

Open-drain

output

leakage

current

I^LEAK

P60 to P67

—

0.1

—

10

µA

CMOS input

pins other than

RST

VCC = 5.5 V

VIH = 0.7 VCC

I^IH1

–10

“H” level

input

current

V^CC= 5.5 V

VIH = 2.2 VCC

I^IH2

I^IH3

TTL input pin

—

–10

µA

Hysteresis input VCC = 5.5 V

VIH = 0.8 VCC

CMOS input

pins other than

RST

VCC = 5.5 V

VIL = 0.3 VCC

I^IL1

—

10

µA

“L” level

input

current

V^CC= 5.5 V

VIL = 0.8 V

I^IL2

I^IL3

R

TTL input pin

—

22

—

10

µA

Hysteresis input VCC = 5.5 V

VIL = 0.2 VCC

Pull-up

resistance

RST

—

110

kΩ

(Continued)

59

MB90246A Series

(Continued)

(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)

Value

Parameter Symbol

Pin name

Condition

Unit Remarks

Min.

Typ.

Max.

Internal operation

at 16 MHz

V^CC= 5.0 V ±10%

Normal operation

I^CC

VCC

—

80

100

mA

Internal operation

at 16 MHz

V^CC= 5.0 V ±10%

In sleep mode

Power

I^CCS

—

30

50

mA

supply

current

T^A= +25°C

VCC = 4.5 V to 5.5 V

In stop mode and

hardware standby

mode

I^CCH

—

0.1

10

—

µA

Input

capacitance

Other than AVCC,

AV^SS, VCC, VSS

C^IN

—

pF

60

MB90246A Series

4. AC Characteristics

(1) Reset, Hardware Standby Input Timing

(AV^CC= VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Min.

Max.

—

Reset input time

t^RSTL

RST

HST

5 t^CYC*

5 tCYC*

ns

—

Hardware standby input time t^HSTL

—

* : For t^CYC(cycle time (machine cycle)), see paragraph (4), "Clock output timing."

Note: Upon hardware standby input, divide-by-32 is selected as the machine cycle.

tRSTL, tHSTL

RST

HST

0.2 V^CC

• Measurement conditions for AC ratings

C^L

C^Lis a load capacitance connected to a pin under test.

Capacitors of C^L= 30 pF should be connected to CLK pin, while C^Lof 80 pF is connected

to address bus (A23 to A00) and data bus (D15 to D00), RD, WRH and WRL pins.

61

MB90246A Series

(2) Specification for Power-on Reset

(AV^SS= VSS = 0.0 V, TA = –30°C to +70°C)

Value

Symbol Pin name Condition

Unit

ms

Remarks

Parameter

Min.

Max.

Power supply rising time

Power supply cut-off time

t^R

VCC

—

30

*

—

Due to repeated

operations

t^OFF

1

—

ms

* : V^CCmust be kept lower than 0.2 V before power-on.

Notes: • The above ratings are values for causing a power-on reset.

• When HST is set to “L”, apply power according to this table to cause a power-on reset irrespective of

whether or not a power-on reset is required.

• For built-in resources in the device, re-apply power to the resources to cause a power-on reset.

tR

4.5 V

0.2 V

V^CC

0.2 V

tOFF

Sudden changes in the power supply voltage may cause a power-on reset.

To change the power supply voltage while the device is in operation, it is recommended to raise the voltage

smoothly to suppress fluctuations as shown below.

Main power

supply voltage

V^CC

It is recommended to keep the rising

speed of the supply voltage at 50 mV/ms.

Sub power supply voltage

V^SS

RAM data retained

62

MB90246A Series

(3) Clock Timings

• Operation at 5.0 V ±10%

(AV^SS= VSS = 0.0 V, TA = –30°C to +70°C)

Value

Symbol Pin name

Condition

Unit

Remarks

Parameter

Min. Typ. Max.

Clock frequency

Clock cycle time

F^C

t^C

X0, X1

VCC = 5.0 V ±10%

16

—

32

—

MHz

ns

1/Fc

Recommended

ns duty ratio of

30% to 70%

—

Input clock pulse

width

P^WH,

P^WL

X0

10

—

Input clock rising/

falling time

t^CR,

t^CF

Maximum value

= t^CR+ tCF

VCC = 5.0 V ±10%

11

ns

• Clock timings

tC

0.7 V^CC

0.3 V^CC

P^WH

PWL

t^CF

t^CR

• Relationship between clock frequency and power supply voltage

(V)

5.5

Normal operation range

(T^A= –30°C to +70°C)

4.5

0

16

32

(MHz)

Clock frequency F^C

63

MB90246A Series

(4) Clock Output Timing

(AV^CC= VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)

Value

Symbol Pin name

Condition

Unit Remarks

Parameter

Cycle time

Min.

Max.

2 t^C*¹

32tC*¹*²

t^CYC

CLK

—

ns

(machine cycle)

CLK ↑ → CLK ↓

t^CHCL

VCC = 5.0 V ±10% 1 tCYC/2 – 20 1 tCYC/2 + 20 ns

*1: For t^C(clock cycle time), refer to “(3) Clock Timings.”

*2: This case is applied when the lowest speed (1/16) is selected by the clock gear function with the clock frequency

(FC) set at 16 MHz.

t^CYC

t^CHCL

2.4 V

CLK

0.8 V

64

MB90246A Series

(3) Bus Read Timing

(AV^CC= VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Unit

Remarks

Symbol

Pin name

Condition

Parameter

Min.

Max.

Effective address →

RD ↓ time

t^AVRL

t^AVDV

tRLRH

t^RLDV

A00 to A23

D15 to D00

RD

1 t^CYC*/2 – 20

—

ns

V^CC= 5.0 V ±10%

Effective address →

effective data input

(N + 1.5) ×

1 t^CYC* – 40

—

(N + 1) ×

1 t^CYC* – 25

RD pulse width

—

RD ↓ → effective data

input

(N + 1) ×

1 t^CYC** – 30

D15 to D00

A00 to A23

VCC = 5.0 V ±10%

—

ns

RD ↑ → data hold time tRHDX

0

—

RD ↑ → address

t^RHAX

1 tCYC*/2 – 20

—

effective time

—

Effective address →

t^AVCH

CLK,

A00 to A23

1 t^CYC*/2 – 25

1 tCYC*/2 – 25

—

ns

CLK ↑ time

RD ↓ → CLK ↑ time

tRLCL

RD, CLK

N: Stands for the number of wait cycles. With no wait, N is set at “0”. (The number of wait cycles depends on an

automatic wait and external RDY.)

* : For t^CYC(cycle time (machine cycle)), see paragraph (4), “Clock output timing.”

t^AVCH

0.8 V

t^RLCL

2.4 V

CLK

RD

0.8 V

t^AVRL

t^RLRH

2.4 V

0.8 V

tRHAX

2.4 V

0.8 V

2.4 V

0.8 V

A00 to A23

D00 to D15

t^RLDV

t^RHDX

t^AVDV

2.2 V

0.8 V

2.2 V

0.8 V

65

MB90246A Series

(4) Bus Write Timing

(AV^CC= VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)

Value

Unit

Remarks

Symbol

Pin name

Condition

Parameter

Min.

Max.

Effective address →

WRL, WRH ↓ time

1 tCYC*/

t^AVWL

A00 to A23

WRL, WRH

D15 to D00

A00 to A23

WRL, CLK

VCC = 5.0 V ±10%

—

ns

2 – 20

(N + 1) ×

1 t^CYC** – 25

WRL, WRH pulse width tWLWH

—

Write data → WRL,

t^DVWH

(N + 1) ×

1 t^CYC* – 40

WRH ↑ time

WRL, WRH ↑ → data

t^WHDX

1 t^CYC*/

2 – 20

VCC = 5.0 V ±10%

hold time

WRL, WRH ↑ →

t^WHAX

1 t^CYC*/

2 – 20

address effective time

—

WRL, WRH ↓ → CLK ↓

time

1 t^CYC*/

2 – 25

t^WLCL

N: Stands for the number of wait cycles. With no wait, N is set at “0”. (The number of wait cycles depends on an

automatic wait and external RDY.)

* : For t^CYC(cycle time (machine cycle)), see paragraph (4), “Clock output timing.”

t^WLCL

0.8 V

CLK

t^AVWL

t^WLWH

2.4 V

WRL, WRH

0.8 V

t^WHAX

2.4 V

0.8 V

A00 to A23

D00 to D15

0.8 V

tDVWH

tWHDX

2.4 V

0.2 V

2.4 V

0.2 V

Write data

66

MB90246A Series

(5) Ready Input Timing

• CLK signal standards

(AV^CC= VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min.

Max.

RD/WRH/

WRL,

RDY

RD/WRH/WRL ↓ →

RDY ↓ time

N ×1 t^CYC*

t^RYHS

0

ns

+ 15

RDY setup time

(in diallocating)

t^RHDV

RDY

VCC = 5.0 V ±10%

30

0

—

ns

RDY hold time

tRYHH

—

N: Stands for the number of wait cycles. With no wait, N is set at “0”. (The number of wait cycles depends on an

automatic wait and external RDY.)

* : For t^CYC(cycle time (machine cycle)), see paragraph (4), “Clock output timing.”

Note: Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient.

• Ready input timing (CLK signal standards)

CLK

A00 to A23

RD/WRH/WRL

0.8 V

t^RYHH

t^RYH

RDY

(wait not inserted)

2.2 V

0.8 V

2.2 V

RDY

(wait inserted)

2.2 V

0.8 V

t^RHDV

t^RYHH

67

MB90246A Series

• RD/WRH/WRL signal standards

(AV^CC= VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min.

Max.

RD/WRH/

WRL,

RDY

RD/WRH/WRL ↓ →

RDY ↓ time

N ×1 t^CYC*³

t^RYHS

t^RYPW

tRHDV

—

VCC = 5.0 V ±10%

—

0

ns

+ 15*¹

1/2 t^CYC*³

+ 20

(m + 1) × 1

RDY pulse width

RDY

tCYC*^2,*³

RD/WRH/

WRL,

RDY

1 t^CYC*³

– 15

2 t^CYC*³

– 25

RDY ↑ → RD ↑

N: Stands for the number of wait cycles. With no wait, N is set at “0”. (The number of wait cycles depends on an

automatic wait and external RDY.)

m: Stands for the number of RDY wait cycles. With no wait, m is set at “0”.

*1: Use the automatic ready function when the setup time is not sufficient.

*2: If the pulse width has exceeded the maximum value, the wait period may be extended beyond the specified

number of cycles by one cycle.

*3: For tCYC (cycle time (machine cycle)), see paragraph (4), “Clock output timing.”

• Ready input timing (RD/WRH/WRL signal standards)

A00 to A23

RD/WRH/WRL

0.8 V

2.4 V

t^RYHS

2.2 V

t^RYPW

RDY

(wait not inserted)

2.2 V

0.8 V

RDY

(wait inserted)

2.2 V

0.8 V

t^RHDV

68

MB90246A Series

(8) Hold Timing

Parameter

(AV^CC= VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Min.

30

Max.

1 tCYC*

2 tCYC*

Pins in floating status →

HAK ↓ time

t^XHAL

HAK

VCC = 5.0 V ±10%

ns

HAK ↑ → pin valid time tHAHV

—

1 tCYC*

* : For t^CYC(cycle time (machine cycle)), see paragraph (4), “Clock output timing.”

Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.

HRQ

HAK

2.4 V

0.8 V

t^XHAL

t^HAHV

Pins

High impedance

(9) UART Timing

(AV^CC= VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)

Value

Symbol Pin name

Condition

Unit

Remarks

Parameter

Min.

Max.

Serial clock cycle time

t^SCYC

t^SLOV

SCK0

—

8 tCYC*

—

ns

SCK ↓ → SOD delay

time

SCK0,

SOD0

–80

100

80

—

Internal shift

clock mode

C^L= 80 pF for

an output pin

SCK0,

SID0

Valid SID → SCK ↑

tIVSH

t^SHIX

tSHSL

t^SLSH

V^CC= 5.0 V ±10%

ns

SCK ↑ → valid SID hold

time

SCK0,

SID0

60

Serial clock “H” pulse

width

SCK0

4 tCYC*

—

Serial clock “L” pulse

width

External shift

clock mode

ns C^L= 80 pF for

an output pin

ns

SCK ↓ → SOD delay

time

SCK0,

SID0

t^SLOV

tIVSH

t^SHIX

—

60

150

—

Valid SID → SCK ↑

—

V^CC= 5.0 V ±10%

SCK ↑ → valid SID hold

time

SCK0,

SID0

—

ns

* : For t^CYC(cycle time (machine cycle)), see paragraph (4), “Clock output timing.”

Notes: • These are AC ratings in the CLK synchronous mode.

• C^Lis the load capacitor value connected to pins while testing.

69

MB90246A Series

• Internal shift clock mode

tSCYC

SCK0

2.4 V

0.8 V

tSLOV

2.4 V

0.8 V

SOD0

SID0

tIVSH

tSHIX

0.8 V^CC

0.2 V^CC

0.8 V^CC

0.2 V^CC

• External shift clock mode

tSLSH

tSHSL

SCK0

0.8 V^CC

0.2 V^CC

tSLOV

2.4 V

0.8 V

SOD0

SID0

tIVSH

tSHIX

0.8 V^CC

0.2 V^CC

0.8 V^CC

0.2 V^CC

70

MB90246A Series

(10) Timer Input Timing

(AV^CC= VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min.

Max.

t^TIWH,

t^TIWL

ASR0, ASR1,

TIN0 to TIN2

Input pulse width

—

4 t^CYC*

—

ns

* : For tCYC (cycle time (machine cycle)), see paragraph (4), “Clock output timing.”

0.8 V^CC

0.2 V^CC

ASR0, ASR1

TIN0 to TIN2

tTIWH

tTIWL

(11) Timer Output Timing

(AV^CC= VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min.

Max.

TOT0 to TOT2,

PWM0 to

PWM3

CLK ↑ → TOT

transition time

t^TO

V^CC= 5.0 V ±10%

—

40

ns

2.4 V

CLK

TOT

2.4 V

0.8 V

t^TO

71

MB90246A Series

(12) I/O Simple Serial Timing

(AV^CC= VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)

Value

Symbol

Pin name

Condition

Unit

Remarks

Parameter

Min.

Max.

Serial clock cycle time

t^SCYC

t^SLOV

SCK1, SCK2

2 tCYC*

—

ns

SCK ↓ → SOD delay

time

SCK1, SOD1,

SCK2, SOD2,

—

1 t^CYC*/2

Internal shift

clock mode

C^L= 80 pF for

an output pin

—

SCK1, SID1,

SCK2, SID2,

Valid SID → SCK ↑

t^IVSH

1 t^CYC*

—

ns

SCK ↑ → valid SID hold

time

SCK1, SID1,

SCK2, SID2,

t^SHIX

* : For t^CYC(cycle time (machine cycle)), see paragraph (4), “Clock output timing.”

Note: C^Lis the load capacitor value connected to pins while testing.

• Internal shift clock mode

tSCYC

2.4 V

SCK1, SCK2

0.8 V

tSLOV

2.4 V

SOD1, SOD2

0.8 V

tIVSH

tSHIX

0.8 V^CC

0.2 V^CC

0.8 V^CC

0.2 V^CC

SID1, SID2

72

MB90246A Series

(13) Trigger input timing

(AV^CC= VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)

Value

Symbol

Pin name

Condition

Unit

Remarks

Parameter

Min.

Max.

t^TRGH,

tTRGL

ATG,

INT0 to INT3

Input pulse width

—

5 t^CYC*

—

ns

* : For t^CYC(cycle time (machine cycle)), see paragraph (4), “Clock output timing.”

0.8 V^CC

0.2 V^CC

0.8 V^CC

0.2 V^CC

ATG

INT0 to INT3

tTRGH

tTRGL

73

MB90246A Series

5. A/D Converter Electrical Characteristics

(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)

Value

Typ.

8, 10

—

Symbol

Pin name

Condition

Unit

Parameter

Resolution

Min.

—

Max.

10

—

bit

Total error

—

±3.0

±2.0

±1.9

AVRL

LSB

Linearity error

—

Differential linearity error

—

AVRL

—

AVRL

—

Zero transition voltage

V^OT

V^FST

AN0 to AN7

mV

– 1.0 LSB + 1.0 LSB + 3.0 LSB

Full-scale transition

voltage

Conversion time*¹

AVRH

AN0 to AN7

mV

µs

– 4.0 LSB – 1.0 LSB + 1.0 LSB

—

1.25

560

—

Sampling

period

—

ns

Use the A/D data

register for setup.

V^CC= 5.0 V ±10%

Conversion

period a

—

125

250

—

ns

Conversion

period b

Conversion

period c

Analog port input current I^AIN

AN0 to AN7

—

0.1

—

3

µA

—

Analog input voltage

V^AIN

AVRL

AVRH

V

AVRL

+ 2.7

—

AVRH

—

AV^CC

V

≥

Reference voltage

AVRH – AVRL 2.7

AVRH

– 2.7

AVRL

0

—

V

I^A

I^AS*²

I^R

AVCC

—

15

20

mA

Supply current when

the CPU stops

(AVCC = 5.5 V)

Power supply current

AVCC

—

0.7

—

5

µA

AVRH

—

2

Reference voltage

supply current

Supply current when

the CPU stops

(AV^CC= 5.5 V)

I^RS*²

AVRH

5

µA

Offset between channels

—

AN0 to AN7

—

4

LSB

*1: Glossary for conversion time

Conversion time

Conversion period a Conversion period b Conversion period c

1 t^CYC* Sampling period

2 t^CYC*

A/D activation

End of conversion

ADCS bit 6: INT “H”

ADCS bit 1: Sets STAR

(Interrupt occurred to CPU)

* : For tCYC, see ■ Electrical Characteristics, 4, “AC Characteristics,” Cycle time (machine cycle) in

paragraph (4), “Clock output timing.”

*2: IAS and IRS signify currents when the A/D converter does not operate and when the CPU is out of service,

respectively.

74

MB90246A Series

6. A/D Converter Glossary

Resolution: Analog changes that are identifiable with the A/D converter

With 10 bits supported, an analog voltage can be divided into 2¹⁰parts.

Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00

0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual

conversion characteristics

Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the

theoretical value

Total error: The total error is defined as a difference between the actual value and the theoretical value, which

includes zero-transition error/full-scale transition error, linearity error, differential linearity error and

error caused by noise.

Digital output

11 1111 1111

11 1111 1110

•

(1 LSB × N + V^OT)

•

Linearity error

•

00 0000 0010

00 0000 0001

00 0000 0000

V^OT

V^NTV^{(N + 1)T}

V^FST

V^FST– V^OT

1022

1 LSB =

V^NT– (1 LSB × N + V^OT)

Linearity error

=

[LSB]

1 LSB

^{V( N+1 )T – VNT}– 1 LSB [LSB]

1 LSB

Differential linearity error

=

75

MB90246A Series

7. Notes on Using A/D Converter

Select the output impedance value for the external circuit of analog input according to the following conditions.

Output impedance values of the external circuit of 300 Ω or lower are recommended.

Whencapacitorsareconnectedtoexternalpins, thecapacitanceofseveralthousandtimestheinternalcapacitor

value is recommended to minimized the effect of voltage distribution between the external capacitor and internal

capacitor.

When the output impedance of the external circuit is too high, the sampling time for analog voltages may not

be sufficient (sampling time = 0.56 µs @machine clock of 16 MHz).

• Block diagram of analog input circuit model

Analog input pin

C⁰

Comparator

R^ON1

R^ON2

Comparator

R^ON1: Approx. 300 Ω

R^ON2: Approx. 150 Ω

C⁰: Approx. 60 pF

C¹: Approx. 4 pF

C¹

Comparator

Note: Listed values must be considered as standards.

• Error

The smaller the | AVRH – AVRL |, the greater the error would become relatively.

8. 8-bit D/A Converter Electrical Characteristics

(AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –30°C to +70°C)

Value

Typ.

8

Symbol Pin name

Condition

Unit

Parameter

Resolution

Min.

—

Max.

8

—

bit

—

Differential linearity error

Absolute accuracy

Conversion time

—

±0.9

LSB

V^CC= DVRH = 5.0 V,

DVRL = 0.0 V

—

1.2

%

—

DVRH

DVRL

DVRH

—

V^SS+ 2.0

V^SS

10

—

20

VCC

µs

V

Load capacitance:

20 pF

Analog power supply

voltage

≥

—

VCC – 2.0

1.5

V

DVRH – DVRL 2.0 V

I^D

During conversion

—

1.0

mA

Reference voltage

supply current

When the CPU is

stopped

I^DH

DVRH

—

10

—

µA

kΩ

Analog output

impedance

—

28

76

MB90246A Series

■ EXAMPLE CHARACTERISTICS

(1) “H” Level Output Voltage

(2) “L” Level Output Voltage

V^CC– V^OH

V^OH– I^OH

V^OL(V)

1.0

V^OL– I^OL

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

T^A= +25°C

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

V^CC= 5.0 V

0

–2

–4

–6

–8

0

2

4

6

8

I^OH(mA)

I^OL(mA)

(3) Power Supply Current

I^CC– V^CC

I^CCS– V^CC

I^CC(mA)

80

I^CCS(mA)

25

Internal operating frequency

16 MHz

Internal operating frequency

16 MHz

70

60

50

40

30

20

10

20

15

10

5

13 MHz

10 MHz

8 MHz

10 MHz

8 MHz

4 MHz

2 MHz

4 MHz

2 MHz

0

4.0

0

4.0

4.5

5.0

5.5

6.0

4.5

5.0

5.5

6.0

V^CC(V)

77

MB90246A Series

■ INSTRUCTIONS (421 INSTRUCTIONS)

Table 1 Description of Items in Instruction List

Item

Description

Mnemonic

English upper case and symbol: Described directly in assembler code.

English lower case: Converted in assembler code.

Number of letters after English lower case: Describes bit width in code.

#

~

Describes number of bytes.

Describes number of cycles.

For other letters in other items, refer to table 4.

B

Describes correction value for calculating number of actual states.

Number of actual states is calculated by adding value in the ~section.

Operation

LH

Describes operation of instructions.

Describes a special operation to 15 bits to 08 bits of the accumulator.

Z : Transfer 0.

X : Sign-extend and transfer.

– : No transmission

AH

Describes a special operation to the upper 16-bit of the accumulator.

* : Transmit from AL to AH.

– : No transfer.

Z : Transfer 00^Hto AH.

X : Sign-extend AL and transfer 00H or FFH to AH.

I

S

Describes status of I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero),

V (overflow), and C (carry) flags.

* : Changes after execution of instruction.

– : No changes.

S : Set after execution of instruction.

R: Reset after execution of instruction.

T

N

Z

V

C

RMW

Describes whether or not the instruction is a read-modify-write type (a data is read out from

memory etc. in single cycle, and the result is written into memory etc.).

* : Read-modify-write instruction

– : Not read-modify-write instruction

Note: Not used to addresses having different functions for reading and writing operations.

78

MB90246A Series

Table 2 Description of Symbols in Instruction Table

Description

Item

A

32-bit accumlator

The bit length is dependent on the instructions to be used.

Byte : Lower 8-bit of AL

Word:16-bit of AL

Long : AL: 32-bit of AH

AH

AL

Upper 16-bit of A

Lower 16-bit of A

SP

Stack pointer (USP or SSP)

Program counter

PC

SPCU

SPCL

PCB

DTB

ADB

SSB

USB

SPB

DPR

brg1

brg2

Ri

Stack pointer upper limited register

Stack pointer lower limited register

Program bank register

Data bank register

Additional data bank register

System stack bank register

User stack bank register

Current stack bank register (SSB or USB)

Direct page register

DTB, ADB, SSB, USB, DPR, PCB

DTB, ADB, SSB, USB, DPR

R0, R1, R2, R3, R4, R5, R6, R7

RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

RW0, RW1, RW2, RW3

RWi

RWj

RLi

RL0, RL1, RL2, RL3

dir

addr16

Specify shortened direct address.

Specify direct address.

addr24

ad24 0 to 15

ad24 16 to 23

Specify physical direct address.

bit0 to bit15 of addr24

bit16 to bit 23 of addr24

io

I/O area (000000^Hto 0000FFH)

#imm4

#imm8

#imm16

#imm32

ext (imm8)

4-bit immediate data

8-bit immediate data

16-bit immediate data

32-bit immediate data

16-bit data calculated by sign-extending an 8-bit immediate data

disp8

disp16

8-bit displacement

16-bit displacement

bp

Bit offset value

vct4

vct8

Vector number (0 to 15)

Vector number (0 to 255)

(Continued)

79

MB90246A Series

(Continued)

Item

Description

( )b

Bit address

rel

ear

eam

Specify PC relative branch.

Specify effective address (code 00 to 07).

Specify effective address (code 08 to 1F).

rlst

Register allocation

Table 3 Effective Address Field

Number of bytes in address

extension block*

Code

Symbol

Address type

RL0 Register direct

(RL0) "ea" corresponds to byte, word, and

RL1 long word from left respectively.

(RL1)

RL2

(RL2)

RL3

00

01

02

03

04

05

06

07

R0

RW0

RW1

RW2

RW3

RW4

RW5

RW6

RW7

R1

R2

R3

R4

R5

R6

R7

—

(RL3)

08

09

0A

0B

@RW0

@RW1

@RW2

@RW3

Register indirect

0

0C

0D

0E

0F

@RW0 +

@RW1 +

@RW2 +

@RW3 +

Register indirect with post increment

10

11

12

13

14

15

16

17

@RW0 + disp8

@RW1 + disp8

@RW2 + disp8

@RW3 + disp8

@RW4 + disp8

@RW5 + disp8

@RW6 + disp8

@RW7 + disp8

Register indirect with 8-bit

displacement

1

18

19

1A

1B

@RW0 + disp16

@RW1 + disp16

@RW2 + disp16

@RW3 + disp16

Register indirect with 16-bit

displacement

2

1C

1D

1E

1F

@RW0 + RW7

@RW1 + RW7

@PC + disp16

addr16

Register indirect with index

PC indirect with 16-bit displacement

Direct address

0

2

Note: Number of bytes for address extension corresponds to “+” in the # (number of bytes) part in the instruction

table.

80

MB90246A Series

Table 4 Number of Execution Cycles in Addressing Modes

(a)*

Code

Operand

Number of execution cycles for addressing modes

Ri

RWi

RLi

00 to 07

Listed in instruction table

08 to 0B

0C to 0F

10 to 17

18 to 1B

@RWj

1

4

1

@RWj +

@RWi + disp8

@RWj + disp16

1C

1D

1E

1F

@RW0 + RW7

@RW1 + RW7

@PC + disp16

addr16

2

1

Note: (a) is used for ~ (number of cycles) and B (correction value) in instruction table.

Table 5 Correction Value for Number of Cycles for Calculating Actual Number of Cycles

(b)*

byte

+0

(c)*

word

+0

(d)*

long

+0

Operand

Internal register

Internal RAM even address

Internal RAM odd address

+0

+1

+0

+2

Other than internal RAM even address

Other than internal RAM odd address

+1

+3

+2

+6

External data bus 8-bit

+1

+3

+6

Notes: • (b), (c), (d) is used for ~ (number of cycles) and B (correction value) in instruction table.

81

MB90246A Series

Table 6 Transmission Instruction (Byte) [50 Instructions]

LH AH

Mnemonic

MOV A, dir

MOV A, addr16

MOV A, Ri

MOV A, ear

MOV A, eam

MOV A, io

MOV A, #imm8

MOV A, @A

MOV A, @RLi + disp8

MOV A, @SP + disp8

MOVP A, addr24

MOVP A, @A

#

~

B

Operation

I

S

T

N

Z

V

C RMW

2

3

1

2

1

(b) byte (A) ← (dir)

(b) byte (A) ← (addr16)

0

Z

*

–

*

–

*

–

*

R

*

–

byte (A) ← (Ri)

byte (A) ← (ear)

2 + 2 + (a) (b) byte (A) ← (eam)

2

3

5

2

1

2

6

3

2

1

(b) byte (A) ← (io)

byte (A) ← imm8

(b) byte (A) ← ((A))

0

byte (A) ← ((RLi) + disp8)

byte (A) ← ((SP) + disp8)

(b)

(b) byte (A) ← (addr24)

(b) byte (A) ← ((A))

0

MOVN A, #imm4

byte (A) ← imm4

MOVX A, dir

MOVX A, addr16

MOVX A, Ri

MOVX A, ear

MOVX A, eam

MOVX A, io

MOVX A, #imm8

MOVX A, @A

MOVX A, @RWi + disp8

MOVX A, @RLi + disp8

MOVX A, @SP + disp8

MOVPX A, addr24

MOVPX A, @A

2

3

2

1

(b) byte (A) ← (dir)

(b) byte (A) ← (addr16)

X

*

–

*

–

*

–

0

byte (A) ← (Ri)

byte (A) ← (ear)

2 + 2 + (a) (b) byte (A) ← (eam)

2

3

5

2

3

6

3

2

(b) byte (A) ← (io)

byte (A) ← imm8

(b) byte (A) ← ((A))

byte (A) ← ((RWi) + disp8)

(b)

0

(b) byte (A) ← ((RLi) + disp8) X

byte (A) ← ((SP) + disp8)

(b)

X

(b) byte (A) ← (addr24)

(b) byte (A) ← ((A))

MOV dir, A

MOV addr16, A

MOV Ri, A

MOV ear, A

MOV eam, A

2

3

1

2

1

2

(b) byte (dir) ← (A)

(b) byte (addr16) ← (A)

–

*

–

0

byte (Ri) ← (A)

byte (ear) ← (A)

2 + 2 + (a) (b) byte (eam) ← (A)

MOV io, A

2

3

5

2

6

3

(b) byte (io) ← (A)

byte ((RLi) + disp8) ← (A)

byte ((SP) + disp8) ← (A)

MOV @RLi + disp8, A

MOV @SP + disp8, A

MOVP addr24, A

(b)

(b) byte (addr24) ← (A)

MOV Ri, ear

MOV Ri, eam

MOVP @A, Ri

2

0

byte (Ri) ← (ear)

–

*

–

2 + 3 + (a) (b) byte (Ri) ← (eam)

2

3

(b) byte ((A)) ← (Ri)

byte (ear) ← (Ri)

MOV ear, Ri

0

MOV eam, Ri

MOV Ri, #imm8

MOV io, #imm8

MOV dir, #imm8

MOV ear, #imm8

MOV eam, #imm8

2 + 3 + (a) (b) byte (eam) ← (Ri)

2

3

2

3

2

0

byte (Ri) ← imm8

*

(b) byte (io) ← imm8

(b) byte (dir) ← imm8

0

–

*

–

*

byte (ear) ← imm8

3 + 2 + (a) (b) byte (eam) ← imm8

–

MOV @AL, AH

2

3

(b) byte ((A)) ← (AH)

byte (A) ↔ (ear)

–

*

–

XCH A, ear

XCH A, eam

XCH Ri, ear

XCH Ri, eam

0

Z

–

2 + 3 + (a) 2 × (b) byte (A) ↔ (eam)

byte (Ri) ↔ (ear)

2 + 5 + (a) 2 × (b) byte (Ri) ↔ (eam)

2

4

0

Note: For (a) and (b), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

82

MB90246A Series

Table 7 Transmission Instruction (Word) [40 Instructions]

LH AH

Mnemonic

MOVW A, dir

MOVW A, addr16

MOVW A, SP

MOVW A, RWi

MOVW A, ear

MOVW A, eam

MOVW A, io

MOVW A, @A

MOVW A, #imm16

MOVW A, @RWi + disp8

MOVW A, @RLi + disp8

MOVW A, @SP + disp8

MOVPW A, addr24

MOVPW A, @A

#

~

B

Operation

I

S

T

N

Z

V

C RMW

2

3

1

2

1

(c) word (A) ← (dir)

(c) word (A) ← (addr16)

0

–

*

–

*

–

*

–

word (A) ← (SP)

word (A) ← (RWi)

word (A) ← (ear)

2 + 2 + (a) (c) word (A) ← (eam)

2

3

2

3

5

2

3

6

3

2

(c) word (A) ← (io)

(c) word (A) ← ((A))

0

(c)

(c) word (A) ← (addr24)

word (A) ← ((A))

(c)

word (A) ← imm16

word (A) ← ((RWi)

+disp8)

word (A) ← ((RLi) +disp8)

word (A) ← ((SP) + disp8)

MOVW dir, A

2

3

4

1

2

1

2

–

*

–

*

–

*

–

*

–

MOVW addr16, A

MOVW SP, #imm16

MOVW SP, A

MOVW RWi, A

MOVW ear, A

MOVW eam, A

MOVW io, A

MOVW @RWi + disp8, A

MOVW @RLi + disp8, A

MOVW @SP + disp8, A

MOVPW addr24, A

MOVPW @A, RWi

MOVW RWi, ear

MOVW RWi, eam

MOVW ear, RWi

MOVW eam, RWi

MOVW RWi, #imm16

MOVW io, #imm16

MOVW ear, #imm16

MOVW eam, #imm16

(c) word (dir) ← (A)

0

word (addr16) ← (A)

word (SP) ← imm16

word (SP) ← (A)

word (RWi) ← (A)

2 + 2 + (a) (c) word (ear) ← (A)

2

3

5

2

3

6

3

2

(c) word (eam) ← (A)

(c) word (io) ← (A)

(c)

0

word ((RWi) +disp8) ←

(A)

word ((RLi) +disp8) ← (A)

word ((SP) + disp8) ← (A)

word (addr24) ← (A)

2 + 3 + (a) (c) word ((A)) ← (RWi)

word (RWi) ← (ear)

2 + 3 + (a) (c) word (RWi) ← (eam)

2

3

0

3

4

2

3

2

0

word (ear) ← (RWi)

(c) word (eam) ← (RWi)

word (RWi) ← imm16

0

4 + 2 + (a) (c) word (io) ← imm16

word (ear) ← imm16

MOVW @AL, AH

2

(c) word (eam) ← imm16

–

*

–

XCHW A, ear

2

3

0

word ((A)) ← (AH)

word (A) ↔ (ear)

–

XCHW A, eam

XCHW RWi, ear

XCHW RWi, eam

2 + 3 + (a) 2 × (c)

2

2 + 5 + (a) 2 × (c) word (A) ↔ (eam)

word (RWi) ↔ (ear)

4

0

word (RWi) ↔ (eam)

Note: For (a) and (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

83

MB90246A Series

Table 8 Transmission Instruction (Long) [11 Instructions]

LH AH

Mnemonic

MOVL A, ear

MOVL A, eam

MOVL A, #imm32

MOVL A, @SP + disp8

MOVPL A, addr24

MOVPL A, @A

#

2

2 +

5

3

5

~

2

B

0

Operation

long (A) ← (ear)

I

S

–

T

–

N

*

Z

*

V

–

C RMW

–

3 + (a)

(d) long (A) ← (eam)

long (A) ← imm32

3

4

3

0

(d) long (A) ← ((SP) + disp8)

(d) long (A) ← (addr24)

(d) long (A) ← ((A))

*

2

MOVPL @A, RLi

2

5

(d) long ((A)) ← (RLi)

–

*

–

long ((SP) + disp8) ← (A)

(d) long (addr24) ← (A)

long (ear) ← (A)

(d) long (eam) ← (A)

MOVL @SP + disp8, A

MOVPL addr24, A

MOVL ear, A

3

5

2

4

2

(d)

–

*

–

0

3 + (a)

MOVL eam, A

2 +

Note: For (a) and (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

84

MB90246A Series

Table 9 Add/Subtract (Byte, Word, Long) [42 Instructions]

LH AH

Mnemonic

ADD A,#imm8

#

~

B

Operation

I

S

T

N

Z

V

C RMW

2

3

2

0

byte (A) ← (A) +imm8

Z

–

Z

–

Z

–

*

–

*

ADD

ADDC

A, dir

A, ear

A, eam

ear, A

eam, A

A

(b) byte (A) ← (A) +(dir)

byte (A) ← (A) +(ear)

0

2 + 3 + (a) (b) byte (A) ← (A) +(eam)

byte (ear) ← (ear) + (A)

2 + 3 + (a) 2 × (b) byte (eam) ← (eam) + (A)

2

0

*

1

2

0

byte (A) ← (AH) + (AL) + (C)

byte (A) ← (A) + (ear) + (C)

–

*

ADDC A, ear

ADDC A, eam

ADDDC A

2 + 3 + (a) (b) byte (A) ← (A) + (eam) + (C)

byte (A) ← (AH) + (AL) + (C) (decimal)

1

2

3

2

3

2

0

SUB

SUBC

A, #imm8

A, dir

A, ear

A, eam

ear, A

eam, A

A

byte (A) ← (A) – imm8

(b) byte (A) ← (A) – (dir)

byte (A) ← (A) – (ear)

0

2 + 3 + (a) (b) byte (A) ← (A) – (eam)

byte (ear) ← (ear) – (A)

2 + 3 + (a) 2 × (b) byte (eam) ← (eam) – (A)

2

0

*

1

2

0

byte (A) ← (AH) – (AL) – (C)

byte (A) ← (A) – (ear) – (C)

–

SUBC A, ear

SUBC A, eam

SUBDC A

2 + 3 + (a) (b) byte (A) ← (A) – (eam) – (C)

1

byte (A) ← (AH) – (AL) – (C) (decimal)

3

0

ADDW

A

1

2

0

word (A) ← (AH) + (AL)

word (A) ← (A) + (ear)

–

*

–

*

ADDW A, ear

ADDW A, eam

ADDW A, #imm16

ADDW ear, A

ADDW eam, A

ADDCW A, ear

ADDCW A, eam

2 + 3 + (a) (c) word (A) ← (A) + (eam)

3

2

0

word (A) ← (A) + imm16

word (ear) – (ear) + (A)

2 + 3 + (a) 2 × (c) word (eam) – (eam) + (A)

word (A) ← (A) + (ear) + (C)

2 + 3 + (a) (c) word (A) ← (A) + (eam) + (C)

*

2

0

–

*

–

1

2

0

word (A) ← (AH) – (AL)

word (A) ← (A) – (ear)

SUBW

A

SUBW A, ear

SUBW A, eam

SUBW A, #imm16

SUBW ear, A

SUBW eam, A

SUBCW A, ear

SUBCW A, eam

2 + 3 + (a) (c) word (A) ← (A) – (eam)

3

2

0

word (A) ← (A) – imm16

word (ear) ← (ear) – (A)

2 + 3 + (a) 2 × (c) word (eam) ← (eam) – (A)

word (A) ← (A) – (ear) – (C)

2 + 3 + (a) (c) word (A) ← (A) – (eam) – (C)

2

0

ADDL A, ear

ADDL A, eam

ADDL A, #imm32

SUBL A, ear

SUBL A, eam

SUBL A, #imm32

2

5

0

long (A) ← (A) + (ear)

–

*

–

2 + 6 + (a) (d) long (A) ← (A) + (eam)

5

2

4

5

0

long (A) ← (A) + imm32

long (A) ← (A) – (ear)

2 + 6 + (a) (d) long (A) ← (A) – (eam)

long (A) ← (A) – imm32

5

4

0

Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

85

MB90246A Series

Table 10 Increment/Decrement (Byte, Word, Long) [12 Instructions]

LH AH

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C RMW

INC

ear

eam

2

0

byte (ear) ← (ear) +1

–

*

–

*

2 + 3 + (a) 2 × (b) byte (eam) ← (eam) +1

DEC

ear

eam

2

0

byte (ear) ← (ear) –1

–

*

–

*

2 + 3 + (a) 2 × (b) byte (eam) ← (eam) –1

INCW ear

INCW eam

2

0

word (ear) ← (ear) +1

–

*

–

*

2 + 3 + (a) 2 × (c) word (eam) ← (eam) +1

DECW ear

DECW eam

2

0

word (ear) ← (ear) –1

–

*

–

*

2 + 3 + (a) 2 × (c) word (eam) ← (eam) –1

long (ear) ← (ear) +1

INCL

ear

eam

2

4

0

–

*

–

*

2 + 5 + (a) 2 × (d) long (eam) ← (eam) +1

DECL ear

DECL eam

2

4

0

long (ear) ← (ear) –1

–

*

–

*

2 + 5 + (a) 2 × (d) long (eam) ← (eam) –1

Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

Table 11 Compare (Byte, Word, Long) [11 Instructions]

LH AH

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C RMW

CMP

A

1

2

1

2

0

byte (AH) – (AL)

byte (A) – (ear)

–

*

–

A, ear

A, eam

A, #imm8

2 + 3 + (a) (b) byte (A) – (eam)

2

0

byte (A) – imm8

CMPW A

1

2

1

2

0

word (AH) – (AL)

word (A) – (ear)

–

*

–

CMPW A, ear

CMPW A, eam

CMPW A, #imm16

2 + 3 + (a) (c) word (A) – (eam)

3

2

0

word (A) – imm16

CMPL A, ear

CMPL A, eam

CMPL A, #imm32

2

6

0

word (A) – (ear)

–

*

–

2 + 7 + (a) (d) word (A) – (eam)

word (A) – imm32

5

3

0

Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

86

MB90246A Series

Table 12 Unsigned Multiply/Division (Word, Long) [11 Instructions]

LH AH

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C RMW

DIVU

A

1

*1

0

word (AH) /byte (AL)

Quotient → byte (AL)

Remainder → byte (AH)

word (A)/byte (ear)

–

*

–

DIVU

A, ear

A, eam

2

*2

0

–

*

Quotient → byte (A)

Remainder → byte (ear)

2 + *3 *6 word (A)/byte (eam)

Quotient → byte (A)

Remainder → byte (eam)

long (A)/word (ear)

DIVUW A, ear

DIVUW A, eam

2

*4

0

Quotient → word (A)

Remainder → word (ear)

2+ *5 *7 long (A)/word (eam)

Quotient → word (A)

Remainder → word (eam)

MULU

MULUW A

MULUW A, ear

MULUW A, eam

A

1

2

*8

*9

0

byte (AH) byte (AL) → word (A)

byte (A) byte (ear) → word (A)

–

A, ear

A, eam

2 + *10 (b) byte (A) byte (eam) → word (A)

1

2

*11

*12

0

word (AH) word (AL) → long (A)

word (A) word (ear) → long (A)

2 + *13 (c) word (A) word (eam) → long (A)

Note: For (b) and (c), refer to “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of

Cycles.”

*1: Set to 3 when the division-by-0, 6 for an overflow, and 14 for normal operation.

*2: Set to 3 when the division-by-0, 6 for an overflow, and 13 for normal operation.

*3: Set to 5 + (a) when the division-by-0, 7 + (a) for an overflow, and 17 + (a) for normal operation.

*4: Set to 3 when the division-by-0, 5 for an overflow, and 21 for normal operation.

*5: Set to 4 + (a) when the division-by-0, 7 + (a) for an overflow, and 25 + (a) for normal operation.

*6: When the division-by-0, (b) for an overflow, and 2 × (b) for normal operation.

*7: When the division-by-0, (c) for an overflow, and 2 × (c) for normal operation.

*8: Set to 3 when byte (AH) is zero, 7 when byte (AH) is not zero.

*9: Set to 3 when byte (ear) is zero, 7 when byte (ear) is not zero.

*10:Set to 4 + (a) when byte (eam) is zero, 8 + (a) when byte (eam) is not zero.

*11:Set to 3 when word (AH) is zero, 11 when word (AH) is not zero.

*12:Set to 4 when word (ear) is zero, 11 when word (ear) is not zero.

*13:Set to 4 + (a) when word (eam) is zero, 12 + (a) when word (eam) is not zero.

87

MB90246A Series

Table 0 Signed multiplication/division (Word, Long) [11 Instructions]

LH AH

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C RMW

DIV

A

2

*1

0

word (AH)/byte (AL)

Z

–

*

–

Quotient → byte (AL)

Remainder → byte (AH)

word (A)/byte (ear)

A, ear

2

*2

0

–

*

Quotient → byte (A)

Remainder → byte (ear)

A, eam

2 + *3 *6 word (A)/byte (eam)

Quotient → byte (A)

Remainder → byte (eam)

long (A)/word (ear)

DIVW A, ear

DIVW A, eam

2

*4

0

Quotient → word (A)

Remainder → word (ear)

2 + *5 *7 long (A)/word (eam)

Quotient → word (A)

Remainder → word (eam)

MUL

MULW A

MULW A, ear

MULW A, eam

A

2

*8

*9

0

byte (AH) × byte (AL) → word (A) –

–

A, ear

A, eam

byte (A) × byte (ear) → word (A)

byte (A) × byte (eam) → word (A)

word (AH) × word (AL) → long (A)

word (A) × word (ear) → long (A)

–

2 + *10 (b)

2

*11

*12

0

2 + *13 (b) word (A) × word (eam) → long (A)

For (b) and (c), refer to “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”

*1: Set to 3 for divide-by-0, 8 or 18 for an overflow, and 18 for normal operation.

*2: Set to 3 for divide-by-0, 10 or 21 for an overflow, and 22 for normal operation.

*3: Set to 4 + (a) for divide-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation.

*4: Positive divided: Set to 4 for divide-by-0, 10 or 29 for an overflow, and 30 for normal operation.

Negative divided: Set to 4 for divide-by-0, 11 or 30 for an overflow, and 31 for normal operation.

*5: Positivedivided: Setto4+(a)fordivide-by-0, 11+(a)or30+(a)foranoverflow, and31+(a)fornormaloperation.

Negative divided: Set to 4 + (a) for divide-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal

operation.

*6: Set to (b) when the division-by-0 or an overflow, and 2 × (b) for normal operation.

*7: Set to (c) when the division-by-0 or an overflow, and 2 × (c) for normal operation.

*8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.

*9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.

*10:Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative.

*11:Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.

*12:Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.

*13:Setto4+(a)whenword(eam)iszero, 17+(a)whentheresultispositive, and20+(a)whentheresultisnegative.

Note: When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two

values because of detection before and after an operation.

When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed.

88

MB90246A Series

Table 14 Logic 1 (Byte, Word) [39 Instructions]

LH AH

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C RMW

AND

A, #imm8

A, ear

A, eam

ear, A

2

0

byte (A) ← (A) and imm8

byte (A) ← (A) and (ear)

–

*

R

–

*

2 + 3 + (a) (b) byte (A) ← (A) and (eam)

byte (ear) ← (ear) and (A)

2

3

0

eam, A

2 + 3 + (a) 2 × (b) byte (eam) ← (eam) and (A) –

*

OR

A, #imm8

A, ear

A, eam

ear, A

2

0

byte (A) ← (A) or imm8

byte (A) ← (A) or (ear)

–

*

R

–

*

2 + 3 + (a) (b) byte (A) ← (A) or (eam)

byte (ear) ← (ear) or (A)

2 + 3 + (a) 2 × (b) byte (eam) ← (eam) or (A)

2

3

0

eam, A

*

XOR A, #imm8

XOR A, ear

XOR A, eam

XOR ear, A

XOR eam, A

2

0

byte (A) ← (A) xor imm8

byte (A) ← (A) xor (ear)

–

*

R

–

*

–

*

2 + 3 + (a) (b) byte (A) ← (A) xor (eam)

byte (ear) ← (ear) xor (A)

2

3

0

2 + 3 + (a) 2 × (b) byte (eam) ← (eam) xor (A) –

1

2

NOT

A

ear

eam

2

0

byte (A) ← not (A)

byte (ear) ← not (ear)

–

2 + 3 + (a) 2 × (b) byte (eam) ← not (eam)

*

ANDW A

1

3

2

0

word (A) ← (AH) and (A)

word (A) ← (A) and imm16

word (A) ← (A) and (ear)

–

*

R

–

*

ANDW A, #imm16

ANDW A, ear

ANDW A, eam

ANDW ear, A

ANDW eam, A

2 + 3 + (a) (c) word (A) ← (A) and (eam)

word (ear) ← (ear) and (A)

2

3

0

2 + 3 + (a) 2 × (c) word (eam) ← (eam) and (A) –

*

ORW

A

1

3

2

0

word (A) ← (AH) or (A)

word (A) ← (A) or imm16

word (A) ← (A) or (ear)

–

*

R

–

*

ORW A, #imm16

ORW A, ear

ORW A, eam

ORW ear, A

ORW eam, A

2 + 3 + (a) (c) word (A) ← (A) or (eam)

word (ear) ← (ear) or (A)

2

3

0

2 + 3 + (a) 2 × (c) word (eam) ← (eam) or (A) –

*

XORW A

1

3

2

0

word (A) ← (AH) xor (A)

word (A) ← (A) xor imm16

word (A) ← (A) xor (ear)

–

*

R

–

*

–

*

XORW A, #imm16

XORW A, ear

XORW A, eam

XORW ear, A

XORW eam, A

NOTW A

2 + 3 + (a) (c) word (A) ← (A) xor (eam)

word (ear) ← (ear) xor (A)

2

3

0

2 + 3 + (a) 2 × (c) word (eam) ← (eam) xor (A) –

1

2

3

0

word (A) ← not (A)

word (ear) ← not (ear)

–

NOTW ear

NOTW eam

2 + 3 + (a) 2 × (c) word (eam) ← not (eam)

*

Note: For (a) to (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

89

MB90246A Series

Table 15 Logic 2 (Long) [6 Instructions]

LH AH

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C RMW

ANDL A, ear

ANDL A, eam

2

5

0

long (A) ← (A) and (ear)

–

*

R

–

2 + 6 + (a) (d) long (A) ← (A) and (eam)

ORL

A, ear

A, eam

2

5

0

long (A) ← (A) or (ear)

–

*

R

–

2 + 6 + (a) (d) long (A) ← (A) or (eam)

XORL A, ear

XORL A, eam

2

5

0

long (A) ← (A) xor (ear)

–

*

R

–

2 + 6 + (a) (d) long (A) ← (A) xor (eam)

Note: For (a) and (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

Table 16 Sign Reverse (Byte, Word) [6 Instructions]

RG

LH AH

RMW

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C

NEG

A

1

2

0

byte (A) ← 0 – (A)

X

–

*

–

NEG

ear

eam

2

3

2

0

byte (ear) ← 0 – (ear)

–

*

–

*

2 + 5 + (a) 0 2 × (b) byte (eam) ← 0 – (eam)

NEGW A

1

2

0

word (A) ← 0 – (A)

–

*

–

NEGW ear

NEGW eam

2

3

2

0

word (ear) ← 0 – (ear)

–

*

–

*

2 + 5 + (a) 0 2 × (c) word (eam) ← 0 – (eam)

Note: For (a) and (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

Table 17 Absolute Values (Byte, Word, Long) [3 Instructions]

LH AH

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C RMW

ABS

ABSW A

ABSL

A

2

4

0

byte (A) ← Absolute value (A)

word (A) ← Absolute value (A)

long (A) ← Absolute value (A)

Z

–

*

–

A

Table 18 Normalize Instruction (Long) [1 Instruction]

LH AH

RMW

C

Mnemonic

#

~

RG

B

Operation

I

S

T

N

Z

V

NRML A, R0

2

*1

1

0

long (A) ← Shift to where “1”

is originally located

–

*

–

byte (R0) ← Number of shifts

in the operation

* : Set to 5 when the accumulator is all “0”, otherwise set to 5 + (R0).

90

MB90246A Series

Table 19 Shift Type Instruction (Byte, Word, Long) [27 Instructions]

LH AH

RMW

S T N Z V C

Mnemonic

RORC A

#

~

B

Operation

I

2

0

byte (A) ← With right-rotate carry

byte (A) ← With left-rotate carry

–

*

–

*

–

ROLC A

RORC ear

RORC eam

ROLC ear

ROLC eam

2

2 +

2

0

byte (ear) ← With right-rotate carry

–

*

–

*

3 + (a)

2 × (b) byte (eam) ← With right-rotate carry

byte (ear) ← With left-rotate carry

2

3 + (a)

0

2 +

2 × (b) byte (eam) ← With left-rotate carry

byte (A) ← Arithmetic right barrel shift (A, R0)

ASR A, R0

LSR A, R0

2

*1

0

–

*

–

*

–

*

–

byte (A) ← Logical right barrel shift (A, R0)

byte (A) ← Logical left barrel shift (A, R0)

LSL

A, R0

byte (A) ← Arithmetic right barrel shift (A, imm8)

ASR A, #imm8

3

*3

0

–

*

–

*

–

*

–

byte (A) ← Logical right barrel shift (A, imm8)

LSR

LSL

A, #imm8

byte (A) ← Logical left barrel shift (A, imm8)

word (A) ← Arithmetic right shift (A, 1 bit)

ASRW A

LSRW A/SHRW

A

1

2

0

–

*

–

*

R

*

–

*

–

word (A) ← Logical right shift (A, 1 bit)

word (A) ← Logical left shift (A, 1 bit)

LSLW A/SHLW A

word (A) ← Arithmetic right barrel shift (A, R0)

2

*1

0

–

*

–

*

–

*

–

ASRW A, R0

LSRW A, R0

LSLW A, R0

word (A) ← Logical right barrel shift (A, R0)

word (A) ← Logical left barrel shift (A, R0)

word (A) ← Arithmetic right barrel shift (A, imm8)

3

*3

0

–

*

–

*

–

*

–

ASRW A, #imm8

LSRW A, #imm8

LSLW A, #imm8

word (A) ← Logical right barrel shift (A, imm8)

word (A) ← Logical left barrel shift (A, imm8)

long (A) ← Arithmetic right barrel shift (A, R0)

ASRL A, R0

LSRL A, R0

LSLL A, R0

2

*2

0

–

*

–

*

–

*

–

long (A) ← Logical right barrel shift (A, R0)

long (A) ← Logical left barrel shift (A, R0)

long (A) ← Arithmetic right barrel shift (A, imm8)

ASRL A, #imm8

LSRL A, #imm8

LSLL A, #imm8

3

*4

0

–

*

–

*

–

*

–

long (A) ← Logical right barrel shift (A, imm8)

long (A) ← Logical left barrel shift (A, imm8)

Note: For (a) and (b), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

*1: Set to 3 when R0 is 0, otherwise 3 + (R0).

*2: Set to 3 when R0 is 0, otherwise 4 + (R0).

*3: Set to 3 when imm8 is 0, otherwise 3 + imm8.

*4: Set to 3 when imm8 is 0, otherwise 4 + imm8.

91

MB90246A Series

Table 20 Branch 1 [31 Instructions]

LH AH

Mnemonic

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

#

~

B

Operation

Branch if (Z) = 1

I

S

T N Z V C RMW

2

*1

0

–

Branch if (Z) = 0

Branch if (C) = 1

Branch if (C) = 0

Branch if (N) = 1

Branch if (N) = 0

Branch if (V) = 1

Branch if (V) = 0

Branch if (T) = 1

Branch if (T) = 0

Branch if (V) xor (N) = 1

Branch if (V) xor (N) = 0

Branch if ((V) xor (N)) or (Z) = 1

Branch if ((V) xor (N)) or (Z) = 0

Branch if (C) or (Z) = 1

Branch if (C) or (Z) = 0

Branch unconditionally

BN

BP

BV

BNV

BT

BNT

BLT

BGE

BLE

BGT

BLS

BHI

BRA

rel

JMP

JMPP

@A

addr16

@ear

@eam

@ear *³

@eam *³

addr24

1

3

2

3

0

word (PC) ← (A)

word (PC) ← addr16

word (PC) ← (ear)

–

2 + 4 + (a) (c) word (PC) ← (eam)

2

2 + 4 + (a) (d)

4

2

word (PC) ← (ear), (PCB) ← (ear + 2)

word (PC) ← (eam), (PCB) ← (eam + 2)

3

0

3

4

0

word (PC) ← ad24 0 – 15,

(PCB) ← ad24 16 – 23

CALL

@ear *⁴

(c) word (PC) ← (ear)

–

@eam *⁴

addr16 *⁵

2 + 5 + (a) 2 × (c) word (PC) ← (eam)

3

1

2

5

7

(c) word (PC) ← addr16

2 × (c) Vector call instruction

2 × (c) word (PC) ← (ear) 0 – 15

(PCB) ← (ear) 16 – 23

CALLV #vct4 *⁵

CALLP @ear *⁶

CALLP @eam *⁶

CALLP addr24 *⁷

2 + 8 + (a) *2 word (PC) ← (eam) 0 – 15

(PCB) ← (eam) 16 – 23

4

–

7

2 × (c) word (PC) ← addr0 – 15,

(PCB) ← addr16 – 23

Note: For (a), (c) and (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5

Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”

*1: Set to 3 when branch is executed, and 2 when branch is not executed.

*2: 3 × (c) + (b)

*3: Reads (word) of the branch destination address.

*4: W pushes to stack (word), and R reads (word) of the branch destination address.

*5: Pushes to stack (word).

*6: W pushes to stack (long), and R reads (long) of the branch destination address.

*7: Pushes to stack (long).

92

MB90246A Series

Table 21 Branch 2 [20 Instructions]

LH AH

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C RMW

CBNE A, #imm8, rel

CWBNE A, #imm16, rel

3 *1

4 *1

0

Branch if byte (A) ≠ imm8

Branch if word (A) ≠ imm16

–

*

–

Branch if byte (ear) ≠ imm8

Branch if byte (eam) ≠ imm8

Branch if word (ear) ≠ imm16

Branch if word (eam) ≠ imm16

CBNE ear, #imm8, rel

CBNE eam, #imm8, rel

CWBNE ear, #imm16, rel

4 *1

4 + *3 (b)

5 *1

0

–

*

–

0

CWBNE eam, #imm16, rel 5 + *3 (c)

DBNZ ear, rel

DBNZ eam, rel

3 *2

0

byte (ear) = (ear) – 1,

Branch if (ear) ≠ 0

–

*

–

*

3 + *4 2 × (b) byte (eam) = (eam) – 1,

Branch if (eam) ≠ 0

DWBNZ ear, rel

DWBNZ eam, rel

3 *2

0

word (ear) = (ear) – 1,

Branch if (ear) ≠ 0

–

*

–

*

3 + *4 2 × (c) word (eam) = (eam) – 1,

Branch if (eam) ≠ 0

INT

INTP

INT9

RETI

RETIQ *⁶

#vct8

addr16

addr24

2 14 8 × (c) Software interrupt

3 12 6 × (c) Software interrupt

4 13 6 × (c) Software interrupt

1 14 8 × (c) Software interrupt

–

R

*

S

*

–

*

–

*

–

*

–

*

–

*

–

1

9 6 × (c) Return from interrupt

2 11 *5 Return from interrupt

*

2

1

6

5

(c) Stores old frame pointer in

the beginning of the

–

LINK

#imm8

function, set new frame

pointer, and reserves local

pointer area

(c) Restore old frame pointer

from stack in the end of

the function

–

UNLINK

RET *⁷

1

4

5

(c) Return from subroutine

(d) Return from subroutine

–

RETP *⁸

Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

*1: Set to 4 when branch is executed, and 3 when branch is not executed.

*2: Set to 5 when branch is executed, and 4 when branch is not executed.

*3: Set to 5 + (a) when branch is executed, and 4 + (a) when branch is not executed.

*4: Set to 6 + (a) when branch is executed, and 5 + (a) when branch is not executed.

*5: Set to 3 × (b) + 2 × (c) when an interrupt request is issued, and 6 × (c) for return.

*6: This is a high-speed interrupt return instruction. In the instruction, an interrupt request is detected. When an

interrupt occurs, stack operation is not performed, with this instruction branching to the interrupt vector.

*7: Return from stack (word).

*8: Return from stack (long).

93

MB90246A Series

Table 22 Miscellaneous Control Types (Byte, Word, Long) [36 Instructions]

LH AH

Mnemonic

PUSHW A

PUSHW AH

PUSHW PS

PUSHW rlst

#

~

B

Operation

I

S

T N Z V C RMW

1

2

3

(c) word (SP) ← (SP) – 2, ((SP)) ← (A) –

–

word (SP) ← (SP) – 2, ((SP)) ← (AH)

word (SP) ← (SP) – 2, ((SP)) ← (PS)

(PS) ← (PS) – 2n, ((SP)) ← (rlst)

(c)

*4

–

*3

word (A) ← ((SP)), (SP) ← (SP) + 2

word (AH) ← ((SP)), (SP) ← (SP) + 2

word (PS) ← ((SP)), (SP) ← (SP) + 2

(rlst) ← ((SP)), (SP) ← (SP) + 2n

POPW

A

1

2

3

(c)

*4

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

POPW AH

POPW PS

POPW rlst

–

*2

–

JCTX

@A

1

9

6 × (c) Context switch instruction

–

*

–

AND

OR

CCR, #imm8

2

3

0

byte (CCR) ← (CCR) and imm8 –

–

*

–

byte (CCR) ← (CCR) or imm8

–

MOV

RP, #imm8

ILM, #imm8

2

0

byte (RP) ← imm8

byte (ILM) ← imm8

–

MOVEA RWi, ear

MOVEA RWi, eam

MOVEA A, ear

2

3

0

word (RWi) ← ear

word (RWi) ← eam

word(A) ← ear

–

*

–

2 + 2 + (a)

2

2 + 1 + (a)

2

MOVEA A, eam

word (A) ← eam

*

ADDSP #imm8

ADDSP #imm16

2

3

0

word (SP) ← (SP) + ext (imm8) –

–

word (SP) ← (SP) + imm16

–

MOV

A, brgl

brg2, A

brg2, #imm8

2

3

*1

1

2

0

byte (A) ← (brgl)

byte (brg2) ← (A)

byte (brg2) ← imm8

Z

–

*

–

*

–

NOP

ADB

DTB

PCB

SPB

NCC

CMR

1

0

No operation

–

Prefix code for accessing AD space

Prefix code for accessing DT space

Prefix code for accessing PC space

Prefix code for accessing SP space

Prefix code for no change in flag

Prefix for common register bank

MOVW SPCU, #imm16

MOVW SPCL, #imm16

SETSPC

4

2

0

word (SPCU) ← (imm16)

word (SPCL) ← (imm16)

Enables stack check operation. –

Disables stack check operation. –

–

CLRSPC

BTSCN A

BTSCNS A

BTSCND A

Bit position of 1 in byte (A) from word (A)

2

*5

*6

*7

0

Z

–

*

–

Bit position (× 2) of 1 in byte (A) from word

(A)

Bit position (× 4) of 1 in byte (A) from word

(A)

Note: For (a) and (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

*1: PCB, ADB, SSB, USB, and SPB : 1 state

DTB

DPR

: 2 states

: 3 states

*2: 3 + 4 × (number of POPs)

94

MB90246A Series

*3: 3 + 4 × (number of PUSHes)

*4: (Number of POPs) × (c), or (number of PUSHes) × (c)

*5: Set to 3 when AL is 0, 5 when AL is not 0.

*6: Set to 4 when AL is 0, 6 when AL is not 0.

*7: Set to 5 when AL is 0, 7 when AL is not 0.

Table 23 Bit Manipulation Instruction [21 Instructions]

LH AH

Mnemonic

#

~

B

Operation

I

S

T N Z V C RMW

MOVB A, dir:bp

MOVB A, addr16:bp

MOVB A, io:bp

3

4

3

(b) byte (A) ← (dir:bp) b

(b) byte (A) ← (addr16:bp) b

(b) byte (A) ← (io:bp) b

Z

*

–

*

–

MOVB dir:bp, A

MOVB addr16:bp, A

MOVB io:bp, A

3

4

3

4

2 × (b) bit (dir:bp) b ← (A)

2 × (b) bit (addr16:bp) b ← (A)

2 × (b) bit (io:bp) b ← (A)

–

*

–

*

SETB dir:bp

SETB addr16:bp

SETB io:bp

3

4

3

4

2 × (b) bit (dir:bp) b ← 1

2 × (b) bit (addr16:bp) b ← 1

2 × (b) bit (io:bp) b ← 1

–

*

CLRB dir:bp

CLRB addr16:bp

CLRB io:bp

3

4

3

4

2 × (b) bit (dir:bp) b ← 0

2 × (b) bit (addr16:bp) b ← 0

2 × (b) bit (io:bp) b ← 0

–

*

BBC dir:bp, rel

BBC addr16:bp, rel

BBC io:bp, rel

4

5

4

*1

(b) Branch if (dir:bp) b = 0

(b) Branch if (addr16:bp) b = 0

(b) Branch if (io:bp) b = 0

–

*

–

BBS

dir:bp, rel

addr16:bp, rel

io:bp, rel

4

5

4

*1

(b) Branch if (dir:bp) b = 1

(b) Branch if (addr16:bp) b = 1

(b) Branch if (io:bp) b = 1

–

*

–

Branch if (addr16:bp) b = 1, bit = 1

SBBS addr16:bp, rel

WBTS io:bp

5

3

*2 2 × (b)

–

*

–

*

*3

*4 Wait until (io:bp) b = 1

*4 Wait until (io:bp) b = 0

–

WBTC io:bp

Note: For (b), refer to “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”

*1: Set to 5 when branch is executed, and 4 when branch is not executed.

*2: 7 if conditions are met, 6 when conditions are not met.

*3: Indeterminate times

*4: Until conditions are met

95

MB90246A Series

Table 24 Accumulator Manipulation Instruction (Byte, Word) [6 Instructions]

LH AH

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C RMW

SWAP

SWAPW/XCHW AL, AH

EXT

EXTW

ZEXT

ZEXTW

1

3

2

1

2

1

0 byte (A) 0 – 7 ↔ (A) 8 – 15

0 word (AH) ↔ (AL)

0 byte sign-extension

0 word sign-extension

0 byte zero-extension

0 word zero-extension

–

X

–

Z

–

*

–

X

–

Z

–

*

R

–

*

–

*

Table 25 String Instruction [10 Instructions]

LH AH

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C RMW

MOVS/MOVSI

2

*2 *3 byte transfer @AH + ← @AL +,

Counter = RW0

*2 *3 byte transfer @AH – ← @AL –,

Counter = RW0

–

MOVSD

–

SCEQ/SCEQI

SCEQD

2

*1 *4 byte search (@AH +) – AL,

Counter = RW0

*1 *4 byte search (@AH –) – AL,

Counter = RW0

–

*

–

FISL/FILSI

2 5m + 6 *5 byte fill @AH + ← AL,

–

*

–

Counter = RW0

MOVSW/MOVSWI

MOVSWD

2

*2 *6 word transfer @AH + ← @AL +,

Counter = RW0

*2 *6 word transfer @AH – ← @AL –,

Counter = RW0

–

SCWEQ/SCWEQI

SCWEQD

2

*1 *7 word search (@AH +) – AL,

Counter = RW0

*1 *7 word search (@AH –) – AL,

Counter = RW0

–

*

–

FILSW/FILSWI

2 5m + 6 *8 word fill @AH + ← AL,

–

*

–

Counter = RW0

m: RW0 value (counter value)

*1: 3 when RW0 is 0, 2 + 6 × (RW0) when count out, and 6n + 4 when matched

*2: 4 when RW0 is 0, otherwise 2 + 6 × (RW0)

*3: (b) × (RW0)

*4: (b) × n

*5: (b) × (RW0)

*6: (c) × (RW0)

*7: (c) × n

*8: (c) × (RW0)

96

MB90246A Series

Table 26 Multiple Data Transfer Instructions [18 Instruction]

LH AH

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C RMW

MOVM @A, @RLi, #imm8

3

*1 *3 Multiple data transfer

–

byte ((A)) ← ((RLi))

MOVM @A, eam, #imm8

MOVM addr16, @RLi, #imm8

3 + *2 *3 Multiple data transfer

–

byte ((A)) ← (eam)

*1 *3 Multiple data transfer

5

byte (addr16) ← ((RLi))

MOVM addr16, @eam, #imm8 5 + *2 *3 Multiple data transfer

byte (addr16) ← (eam)

*1 *4 Multiple data transfer

MOVMW@A, @RLi, #imm8

MOVMW@A, eam, #imm8

MOVMWaddr16, @RLi, #imm8

3

word ((A)) ← ((RLi))

3 + *2 *4 Multiple data transfer

word ((A)) ← (eam)

5

*1 *4 Multiple data transfer

word (addr16) ←

((RLi))

MOVMWaddr16, @eam, #imm8 5 + *2 *4 Multiple data transfer

–

word (addr16) ← (eam)

MOVM @RLi, @A, #imm8

MOVM @eam, A, #imm8

MOVM @RLi, addr16, #imm8

3

*1 *3 Multiple data transfer

byte ((RLi)) ← ((A))

3 + *2 *3 Multiple data transfer

byte (eam) ← ((A))

*1 *3 Multiple data transfer

5

byte ((RLi)) ← (addr16)

MOVM @eam, addr16, #imm8 5 + *2 *3 Multiple data transfer

byte (eam) ← (addr16)

MOVMW@RLi, @A, #imm8

MOVMW@eam, A, #imm8

MOVMW@RLi, addr16, #imm8

3

*1 *4 Multiple data transfer

word ((RLi)) ← ((A))

3 + *2 *4 Multiple data transfer

word (eam) ← ((A))

*1 *4 Multiple data transfer

word ((RLi)) ←

5

(addr16)

MOVMW@eam, addr16, #imm8 5 + *2 *4 Multiple data transfer

–

word (eam) ← (addr16)

MOVM bnk: addr16,

bnk: addr16, #imm8*⁵

7

*1 *3 Multiple data transfer

byte (bnk: addr16) ←

(bnk: addr16)

*1 *4 Multiple data transfer

word (bnk: addr16) ←

(bnk: addr16)

MOVMWbnk: addr16,

bnk: addr16, #imm8*⁵

–

*1: 256 when 5 + imm8 × 5, imm8 is 0.

*2: 256 when 5 + imm8 × 5 + (a), imm8 is 0.

*3: (Number of transfer cycles) × (b) × 2

*4: (Number of transfer cycles) × (c) × 2

*5: The bank register specified by bnk is the same as that for the MOVS instruction.

97

MB90246A Series

■ ORDERING INFORMATION

Part number

Package

100-pin Plastic LQFP

Remarks

MB90246APFV

(FPT-100P-M05)

98

MB90246A Series

■ PACKAGE DIMENSIONS

100-pin Plastic LQFP

(FPT-100P-M05)

1.50−⁺0⁰.^.210⁰

.059 −⁺.^.0⁰⁰04⁸

16.00±0.20(.630±.008)SQ

(Mounting height)

75

51

14.00±0.10(.551±.004)SQ

76

50

12.00

(.472)

REF

15.00

(.591)

NOM

Details of "A" part

0.15(.006)

INDEX

100

26

0.15(.006)MAX

0.40(.016)MAX

"B"

1

25

LEAD No.

"A"

0.50(.0197)TYP

0.18−⁺0⁰.^.003⁸

0.127 ⁺−0⁰.^.002⁵

.005−⁺.^.0⁰⁰01²

M

Details of "B" part

0.08(.003)

.007 −⁺.^.0⁰⁰01³

0.10±0.10

(STAND OFF)

(.004±.004)

0.50±0.20(.020±.008)

0~10˚

0.10(.004)

C

1995 FUJITSU LIMITED F100007S-2C-3

Dimensions in mm (inches)

99

MB90246A Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: 81(44) 754-3763

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

Fax: 81(44) 754-3329

http://www.fujitsu.co.jp/

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications,

and are not intended to be incorporated in devices for actual use.

Also, FUJITSU is unable to assume responsibility for

infringement of any patent rights or other rights of third parties

arising from the use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

Fax: (408) 922-9179

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and measurement

equipment, personal or household devices, etc.).

CAUTION:

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded (such

as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608

Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Any semiconductor devices have an inherent chance of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for

export of those products from Japan.

Fax: (65) 281-0220

http://www.fmap.com.sg/

F98010

FUJITSU LIMITED Printed in Japan


型号：	MB90246
厂家：	FUJITSU
描述：	16-bit Proprietary Microcontroller 16位微控制器专有微控制器
文件：	总100页 (文件大小：1793K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90246 [FUJITSU]

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