MB90523APFV_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13707-3E

16-bit Proprietary Microcontroller

CMOS

F²MC-16LX MB90520A/520B Series

MB90522A/523A/522B/523B/F523B/V520A

■ DESCRIPTION

The MB90520A/520B series is a general-purpose 16-bit microcontroller designed for process control applications

in consumer products that require high-speed real-time processing.

*

2

The microcontroller instruction set is based on the AT architecture of the F MC family with additional instructions

for high-level languages, extended addressing modes, enhanced multiplication and division instructions, and a

complete range of bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long

word (32-bit) data.

The MB90520A/520B series peripheral resources include an 8/10-bit A/D converter, 8-bit D/A converter, UART

(SCI) , extended I/O serial interfaces 0 and 1, 8/16-bit up/down counter/timers 0 and 1, 8/16-bit PPG timers 0 and

1, a range of I/O timers (16-bit free-run timers 1 and 2, input capture (ICU) 0 and 1, and output compare (OCU)

0 and 1) , an LCD controller/driver, 8 external interrupt inputs, and 8 wakeup interrupts.

2

* : F MC stands for FUJITSU Flexible MicroController, a registered trademark of FUJITSU LIMITED.

■ FEATURES

• Clock

• Internal PLL clock multiplication circuit

• Selectable machine clock (PLL clock) : Base oscillation divided by two or multiplied by one to four

(For a 4 MHz base oscillation, the machine clock range is 4 MHz to 16 MHz) .

(Continued)

■ PACKAGES

120-pin, Plastic, LQFP

120-pin, Plastic, QFP

(FPT-120P-M05)

(FPT-120P-M13)

MB90520A/520B Series

(Continued)

• Sub-clock (32.768 KHz) operation available

Minimum instruction execution time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = ×4, VCC = 5.0 V)

• 16MB CPU memory space

Internal 24-bit addressing

• Instruction set optimized for controller applications

Rich data types (bit, byte, word, long-word)

Extended addressing modes (23 types)

Enhanced signed multiplication and division instructions and RETI instruction

Enhanced calculation precision using a 32-bit accumulator

• Instruction set designed for high-level language (C) and multi-tasking

System stack pointer

Enhanced pointer-indirect instructions and barrel shift instructions

• Faster execution speed

4-byte instruction queue

ROM mirror function (48 Kbytes of bank FF is mirrored in bank 00)

• Program patch function : An address match detection function (2 × addresses)

• Interrupt function

32 programmable interrupts with 8 levels

• Automatic data transmission function independent of CPU operation

2

Extended intelligent I/O service function (EI OS) : Up to 16 channels

• Low-power consumption (stand-by) modes

Sleep mode (CPU operating clock stops, peripherals continue to operate.)

Pseudo-clock mode (Only oscillation clock and timebase timer continue to operate.)

Clock mode (Main oscillation clock stops, sub-clock and clock timer continue to operate.)

Stop mode (Main oscillation and sub-clock both stop.)

CPU intermittent operation mode

Hardware stand-by mode (Change to stop mpde by operating hardware stand-by pins.)

• Process

CMOS technology

• I/O ports

General-purpose I/O ports (CMOS input/output) : 53 ports

General-purpose I/O ports (inputs with pull-up resistors) : 24 ports

General-purpose I/O ports (Nch open-drain outputs) : 8 ports

• Timers

Timebase timer, clock timer, watchdog timer : 1 channel each

8/16-bit PPG timers 0 and 1 : 8-bit × 2 channels or 16-bit × 1 channel

16-bit reload timers 0 and 1 : 2 channels

16-bit I/O timers :

16-bit free-run timers 0 and 1 : 2 channels

16-bit input capture 0 : 2 channels (2 channels per unit)

16-bit output compare 0 and 1 : 8 channels (4 channels per unit)

8/16-bit up/down counter/timers 0 and 1 : 8-bit × 2 channels or 16-bit × 1 channel

Clock output function : 1 channel

• Communications macro (communication interface)

Extended I/O serial interfaces 0 and 1 : 2 channels

UART (full-duplex, double-buffered, SCI : Can also be used for synchronous serial transfer) : 1 channel

2

MB90520A/520B Series

• External event interrupt control function

DTP/external interrupts : 8 channels (Can be set to detect rising edges, falling edges, “H” levels, or “L” levels)

Wake-up interrupts : 8 channels (Detects “L” levels only)

Delayed interrupt generation module : 1 channel (for task switching)

• Analog/digital conversion

8/10-bit A/D converter : 8 channels (Can be initiated by an external trigger. Minimum conversion time = 10.2

µs for a 16 MHz machine clock)

8-bit D/A converter : 2 channels (R-2R type. Settling time = 12.5 µs for a 16 MHz machine clock)

• Display function

LCD controller/driver : 32 × segment drivers + 4 × common drivers

• Other

Supports serial writing to flash memory. (Only on versions with on-board flash memory.)

Note : The MB90520A and 520B series cannot be used in external bus mode. Always set these devices to single-

chip mode.

3

MB90520A/520B Series

■ PRODUCT LINEUP

Part

Number MB90522A MB90523A MB90522B MB90523B MB90F523B MB90V520A

Parameter

Evaluation

product

Classification

Mask ROM

Flash ROM

ROM size

RAM size

64 Kbytes

128 Kbytes

64 Kbytes

4 Kbytes

128 Kbytes 128 Kbytes

6 Kbytes

No

Separate emulator

power supply^*1

Process

CMOS

2.7 V to 5.5 V

Operating power

supply voltage^*2

3.0 V to 5.5 V

mounted

Internal regulator circuit

not mounted

Number of instructions : 340

Instruction sizes : 8-bit, 16-bit

Instruction length : 1 byte to 7 bytes

Data sizes : 1-bit, 8-bit, 16-bit

CPU functions

Minimum instruction execution time : 62.5 ns (for a 16 MHz machine clock)

Interrupt processing time : 1.5 µs min. (for a 16 MHz machine clock)

Low power operation

(standby modes)

Sleep mode, clock mode, pseudo-clock mode, stop mode, hardware standby mode,

and CPU intermittent operation mode

General-purpose I/O ports (CMOS outputs) : 53

General-purpose I/O ports (inputs with pull-up resistors) : 24

General-purpose I/O ports (Nch open drain outputs) : 8

Total : 85

I/O ports

18-bit counter

Timebase timer

Watchdog timer

Interrupt interval : 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms

(for a 4 MHz base oscillation)

Reset trigger period

• For a 4 MHz base oscillation : 3.58, 14.33, 57.23, 458.75 ms

• For 32.768 sub-clock operation : 0.438, 3.500, 7.000, 14.000 s

16-bit

freerun

timer

Number of channels : 2

Generates an interrupt on overflow

16-bit

I/O

timers

16-bit

output

compare

Number of channels : 8

Pin change timing : Free run timer register value equals output compare register value.

16-bit

input

capture

Number of channels : 2

Saves the value of the freerun timer register when a pin input occurs (rising edge, falling

edge, either edge) .

Number of channels : 2

16-bit reload timer

Count clock frequency : 0.125, 0.5, or 2.0 µs for a 16 MHz machine clock

Can be used to count an external event clock.

(Continued)

4

MB90520A/520B Series

(Continued)

Part

Number MB90522A MB90523A MB90522B MB90523B MB90F523B MB90V520A

Parameter

15-bit timer

Clock timer

Interrupt interval : 0.438, 0.5, or 2.0 µs for sub-clock frequency = 32.768 kHz

Number of channels : 1 (Can be used in 2 × 8-bit channel mode)

Can generate a pulse waveform output with specified period and 0 to 100% duty ratio.

8/16-bit PPG timer

Number of channels : 1 (Can be used in 2 × 8-bit channel mode)

External event inputs : 6 channels

Reload/compare function : 8-bit × 2 channels

8/16 -bit up/down

counter/timers

Clock monitor

Clock output frequency : Machine clock/2¹to machine clock/2⁸

Delayed interrupt

generation module

Interrupt generation module for task switching. (Used by REALOS.)

Input channels : 8

DTP/External

interrupts

Generates interrupts to the CPU on rising edges, falling edges with input “H” level, or “L”

level.

Can be used for external event interrupts and to activate EI OS.

2

Input channels : 8

Triggered by “L” level.

Wakeup interrupts

Number of channels : 8

Resolution : 8-bit or 10-bit selectable

8/10-bit A/D converter

(successive

approximation type)

Conversion can be performed sequentially for multiple consecutive channels.

• Single-shot conversion mode : Converts specified channel once only.

• Continuous conversion mode : Repeatedly converts specified channel.

• Intermittent conversion mode : Converts specified channel then halts temporarily.

8-bit D/A converter

(R-2R type)

Number of channels : 2

Resolution : 8-bit

Number of channels : 1

Clock synchronous transfer : 62.5 Kbps to 1 Mbps

Clock asynchronous transfer : 1202 bps to 31250 bps

Supports bi-directional and master-slave communications.

UART (SCI)

Number of channels : 2

Clock synchronous transfer : 31.25 Kbps to 1 Mbps (Using internal shift clock)

Transmission format : Selectable LSB-first or MSB-first

Extended I/O serial

interface

Number of common outputs : 4

Number of segment outputs : 32

LCD controller/driver

Number of power supply pins for LCD drive : 4

LCD display memory : 16 bytes

Divider resistor for LCD drive : Internal

*1 : As for the necessity of a DIP switch setting (S2) when using the emulation pod (MB2145-507) .

Refer to the hardware manual for the emulation pod (MB2145-507) fomr details.

*2 : Take note of the maximum operating frequency and A/D converter precision restrictions when operating at 3.0 V

to 3.6 V. See the “Electrical Characteristics” section for details.

5

MB90520A/520B Series

■ PACKAGES AND CORRESPONDING PRODUCTS

Package

MB90522A

MB90523A

MB90522B

MB90523B

MB90F523B MB90V520A

FPT-120P-M05

(LQFP)

×

FPT-120P-M13

(QFP)

×

PGA-256C-A01

(PGA)

×

: Available,

: Not available

Note : See the “■ PACKAGE DIMENSIONS” section for more details.

6

MB90520A/520B Series

■ PIN ASSIGNMENT

(TOP VIEW)

P31/CKOT

P32/OUT0

P33/OUT1

P34/OUT2

P35/OUT3

P36/PG00

P37/PG01

VCC

P40/PG10

P41/PG11

P42/SIN0

P43/SOT0

P44/SCK0

P45/SIN1

P46/SOT1

P47/SCK1

SEG0

1

2

3

4

5

6

7

8

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

RST

MD0

MD1

MD2

HST

V3

V2

V1

V0

9

P97/SEG31

P96/SEG30

P95/SEG29

P94/SEG28

P93/SEG27

P92/SEG26

P91/SEG25

X0A

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

X1A

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

P90/SEG24

P87/SEG23

P86/SEG22

P85/SEG21

P84/SEG20

P83/SEG19

P82/SEG18

P81/SEG17

P80/SEG16

VSS

PA0/SEG8

PA1/SEG9

PA2/SEG10

PA3/SEG11

PA4/SEG12

PA5/SEG13

P77/COM3

P76/COM2

(FPT-120P-M05)

(FPT-120P-M13)

7

MB90520A/520B Series

■ PIN DESCRIPTIONS

Pin No.

Circuit

LQFP-120^*1

QFP-120^*2

Pin Name

Function

Type

92, 93

74, 73

X0, X1

A

B

Oscillator pin

X0A, X1A

Sub-oscillator pin

MD0 to

MD2

Input pins for setting the operation mode.

Connect directly to V^CCor VSS.

89 to 87

C

90

86

RST

HST

C

External reset input pin

Hardware standby input pin

General-purpose I/O ports

P00 to

P06

The settings in the pull-up resistor setup register (RDR0) are enabled

when ports are set as inputs.

The RDR0 settings are ignored when ports are set as outputs.

95 to 101

D

INT0 to

INT6

Event input pins for ch.0 to ch.6 of the DTP/external interrupt circuit

General-purpose I/O port

The settings in the pull-up resistor setup register (RDR0) are enabled when

ports are set as inputs.

102

P07

The RDR0 settings are ignored when ports are set as outputs.

General-purpose I/O ports

The settings in the pull-up resistor setup register (RDR1) are enabled when

ports are set as inputs.

P10 to

P17

103 to 110

The RDR1 settings are ignored when ports are set as outputs.

WI0 to

WI7

Event input pins for the wakeup interrupts.

General-purpose I/O ports

P20, P21,

P22, P23

111, 112,

113, 114

Trigger input pins for input capture units (ICU) 0 and 1.

E

IC00, IC01,

IC10, IC11

Input operates continuously when channels 0 and 1 of input capture units

(ICU) 0 and 1 are operating. Accordingly, output to the pins from other func-

tions that share this pin must be suspended unless performed intentionally.

P24

AIN0

P25

General-purpose I/O port

115

116

E

Also can be used as the count clock A input to 8/16-bit up/down counter/

timer 0.

General-purpose I/O port

Also can be used as the count clock B input to 8/16-bit up/down counter/

timer 0.

BIN0

P26

General-purpose I/O port

Also can be used as the control clock Z input to 8/16-bit up/down counter/

timer 0.

117

ZIN0

INT7

E

Event input pin for ch.7 of the DTP/external interrupt circuit

*1 : FPT-120P-M05

*2 : FPT-120P-M13

(Continued)

8

MB90520A/520B Series

Pin No.

Circuit

Type

LQFP-120^*1

QFP-120^*2

Pin Name

Function

P27

General-purpose I/O port

External trigger input to the 8/10-bit A/D converter

118

E

Input operates continuously when the 8/10-bit A/D converter is performing

input. Accordingly, output to the pin from other functions that share this

pin must be suspended unless performed intentionally.

ADTG

120

1

P30

P31

E

General-purpose I/O port

Output pin for clock monitor function

The clock monitor is output when clock monitor output is enabled.

CKOT

P32

General-purpose I/O port

Only available when waveform output from output compare 0 is disabled.

2

3

4

5

6

7

E

Event output pin for ch.0 of output compare unit 0 (OCU)

Only available when event output is enabled for output compare unit 0.

OUT0

P33

General-purpose I/O port

Only available when waveform output from output compare 1 is disabled.

Event output pin for ch.1 of output compare unit 0 (OCU)

Only available when event output is enabled for output compare unit 0.

OUT1

P34

General-purpose I/O port

Only available when waveform output from output compare 2 is disabled.

Event output pin for ch.2 of output compare unit 0 (OCU)

Only available when event output is enabled for output compare unit 0.

OUT2

P35

General-purpose I/O port

Only available when waveform output from output compare 3 is disabled.

Event output pin for ch.3 of output compare unit 0 (OCU)

Only available when event output is enabled for output compare unit 0.

OUT3

P36

General-purpose I/O port

Only available when waveform output from PG00 is disabled.

Output pin for 8/16-bit PPG timer 0

Only available when waveform output is enabled for PG00.

PG00

P37

General-purpose I/O port

Only available when waveform output from PG01 is disabled.

Output pin for 8/16-bit PPG timer 0

Only available when waveform output is enabled for PG01.

PG01

*1 : FPT-120P-M05

*2 : FPT-120P-M13

(Continued)

9

MB90520A/520B Series

Pin No.

Circuit

LQFP-120^*1

QFP-120^*2

Pin Name

Function

Type

General-purpose I/O ports

Only available when waveform outputs from PG10 and PG11 are disabled.

The settings in the pull-up resistor setup register (RDR4) are enabled

when ports are set as inputs. The RDR4 settings are ignored when ports

are set as outputs.

P40, P41

D

9, 10

PG10,

PG11

Output pins for 8/16-bit PPG timer 1

Only available when waveform output is enabled for PG10 and PG11.

General-purpose I/O port

The settings in the pull-up resistor setup register (RDR4) are enabled

when ports are set as inputs. The RDR4 settings are ignored when ports

are set as outputs.

P42

11

D

UART (SCI) serial data input pin

Input operates continuously when the UART is performing input.

Accordingly, output to the pin from other functions that share this pin must

be suspended unless performed intentionally.

SIN0

General-purpose I/O port

The settings in the pull-up resistor setup register (RDR4) are enabled

when ports are set as inputs. The RDR4 settings are ignored when ports

are set as outputs.

P43

SOT0

P44

12

13

D

UART (SCI) serial data output pin

Only available when serial data output is enabled for the UART (SCI) .

General-purpose I/O port

The settings in the pull-up resistor setup register (RDR4) are enabled

when ports are set as inputs. The RDR4 settings are ignored when ports

are set as outputs.

UART (SCI) serial clock input/output pin

Only available when serial clock output is enabled for the UART (SCI) .

SCK0

P45

General-purpose I/O port

The settings in the pull-up resistor setup register (RDR4) are enabled

when ports set as inputs. The RDR4 settings are ignored when ports set

are as outputs.

14

D

Data input pin for extended I/O serial interface 1

Input operates continuously when the performing serial input. Accordingly,

output to the pin from other functions that share this pin must be

suspended unless performed intentionally.

SIN1

General-purpose I/O port

The settings in the pull-up resistor setup register (RDR4) are enabled

when ports set as inputs. The RDR4 settings are ignored when ports are

set as outputs.

P46

15

Data output pin for extended I/O serial interface 1

Only available when serial data output is enabled for SOT1.

SOT1

*1 : FPT-120P-M05

*2 : FPT-120P-M13

(Continued)

10

MB90520A/520B Series

Pin No.

Circuit

Type

LQFP-120^*1

QFP-120^*2

Pin Name

Function

General-purpose I/O port

The settings in the pull-up resistor setup register (RDR4) are enabled

when ports are set as inputs. The RDR4 settings are ignored when ports

are set as outputs.

P47

16

D

Serial clock input/output pin for extended I/O serial interface 1

Only available when serial clock output is enabled for SCK1.

SCK1

P50

General-purpose I/O port

Data input pin for extended I/O serial interface 2

Input operates continuously when the performing serial input.

Accordingly, output to the pin from other functions that share this pin must

be suspended unless performed intentionally.

SIN2

35

36

E

Also can be used as the count clock A input to 8/16-bit up/down counter/

timer 1.

AIN1

P51

General-purpose I/O port

Data output pin for extended I/O serial interface 2

Only available when serial data output is enabled for SOT2.

SOT2

Also can be used as the count clock B input to 8/16-bit up/down counter/

timer 1.

BIN1

P52

General-purpose I/O port

Serial clock input/output pin for extended I/O serial interface 2

Only available when serial clock output is enabled for SCK2.

SCK2

37

E

I

Also can be used as the control clock Z input to 8/16-bit up/down counter/

timer 1.

ZIN1

P53, P54

DA0, DA1

General-purpose I/O ports

40, 41

Analog output pins for ch.0 and ch.1 of the 8-bit D/A converter

General-purpose I/O ports

P60 to P67

Port input is enabled when the analog input enable register (ADER) is set

to the ports.

46 to 53

K

E

Analog inputs for the 8/10-bit A/D converter

Analog input is enabled when the analog input enable register (ADER) is

set.

AN0 to

AN7

P70, P72

General-purpose I/O ports

Event input pins for 16-bit reload timers 0 and 1

Input operates continuously when 16-bit reload timers 0 and 1 input an

external clock. Accordingly, output to these pins from other functions that

share the pins must be suspended unless performed intentionally.

TI0, TI1

55, 57

OUT4,

OUT6

Event output pins for ch. 4 and ch. 6 of output compare unit 1 (OCU)

Only available when event output from output compare 1 is enabled.

*1 : FPT-120P-M05

*2 : FPT-120P-M13

(Continued)

11

MB90520A/520B Series

Pin No.

Circuit

LQFP-120^*1

QFP-120^*2

Pin Name

Function

Type

General-purpose I/O ports

P71, P73

TO0, TO1

Only available when event outputs from 16-bit reload timers 0 and 1 are

disabled.

56, 58

E

Output pins for 16-bit reload timers 0 and 1.

Only available when output is enabled for 16-bit reload timers 0 and 1.

OUT5,

OUT7

Event output pins for ch. 5 and ch. 7 of output compare unit 1 (OCU)

Only available when event output from output compare 1 is enabled.

General-purpose I/O ports

P74 to P77

Only available when the LCD controller/driver control register is set to the

ports.

59 to 62

64 to 71

L

Common pins for the LCD controller/driver

Only available when the LCD controller/driver control register is set to the

common outputs.

COM0 to

COM3

General-purpose I/O ports

Only available when the LCD controller/driver control register is set to the

ports.

P80 to P87

LCD segment output pins for the LCD controller/driver

Only available when the LCD controller/driver control register is set to the

segment outputs.

SEG16 to

SEG23

General-purpose I/O ports (Support up to IOL = 10 mA)

Only available when the LCD controller/driver control register is set to the

ports.

P90,

P91 to P97

72,

75 to 81

M

F

L

SEG24,

SEG25 to

SEG31

LCD segment output pins for the LCD controller/driver

Only available when the LCD controller/driver control register is set to the

segment outputs.

SEG0 to

SEG7

17 to 24

25 to 32

LCD segment 00 to 07 pins for the LCD controller/driver

General-purpose I/O ports

Only available when the LCD controller/driver control register is set up to

the ports.

PA0 to PA7

LCD segment 08 to 15 pins for the LCD controller/driver

Only available when the LCD controller/driver control register is set to the

segment outputs.

SEG8 to

SEG15

*1 : FPT-120P-M05

*2 : FPT-120P-M13

(Continued)

12

MB90520A/520B Series

(Continued)

Pin No.

Circuit

Type

Pin Name

Function

LQFP-120^*1

QFP-120^*2

Capacitor connection pin for stabilizing power supply

34

C

G

N

Connect an external ceramic capacitor of approximately 0.1 µF. If operat-

ing at 3.3 V or lower, connect to VCC.

82 to 85

8, 54, 94

V0 to V3

Power supply input pins for the LCD controller/driver

Power supply input pins for the digital circuit

Power

supply

VCC

Power

supply

33, 63, 91, 119

42

VSS

GND level power supply input pins for the digital circuit

Power supply input for the analog circuit

Ensure that a voltage greater than AVCC is applied to VCC before turning

the analog power supply on or off.

AV^CC

H

J

“H” reference voltage for the A/D converter

Ensure that a voltage greater than AVRH is applied to AV^CCbefore turning

the power supply to this pin on or off.

43

AVRH

44

45

AVRL

AV^SS

H

“L” reference voltage for the A/D converter

GND level power supply input pin for the analog circuit

“H” reference voltage for the D/A converter

Ensure that this voltage does not exceed VCC.

38

39

DV^CC

DV^SS

H

“L” reference voltage for the D/A converter

Apply the same voltage level as VSS.

*1 : FPT-120P-M05

*2 : FPT-120P-M13

13

MB90520A/520B Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• High-speed oscillation feedback

resistor

Approx. 1 MΩ

X0

X1

Clock input

Nch Pch

Pch

Nch

A

Standby control signal

• Low-speed oscillation feedback

resistor

Approx. 10 MΩ

X0A

X1A

Clock input

Nch Pch

Pch

Nch

B

C

Standby control signal

Hysteresis input

• Hysteresis input

R

• Selectable pull-up option

• CMOS hysteresis input

• CMOS level output

Pull-up connect/

disconnect selection

signal

VCC

• With standby control

Pch

Digital output

D

Digital output

Nch

VSS

R

Hysteresis input

IOL = 4 mA

Standby control

• CMOS hysteresis input

• CMOS level output

• With standby control

VCC

Pch

Digital output

E

Nch

VSS

R

Hysteresis input

Standby control

IOL = 4 mA

(Continued)

14

MB90520A/520B Series

Type

Circuit

Remarks

• Segment output pins

VCC

R

F

Nch

VSS

• Capacitor connection pin

(This is an N.C. pin on the

MB90522A and MB90523A.)

VCC

Pch

G

Nch

VSS

• Analog power supply input

protection circuit

VCC

Pch

AVP

H

Nch

VSS

• CMOS hysteresis input

• CMOS level output

VCC

Pch

(CMOS output is not available when

analog output is operating.)

• Also used as analog output

(Analog output has priority)

• With standby control

Digital output

Nch

VSS

I

R

IOL = 4 mA

Hysteresis input

Standby control

Analog output

• A/D converter ref+ power supply

input pin

(Incorporates power supply

protection circuit.)

VCC

Pch

ANE

AVP

ANE

J

Nch

VSS

(Continued)

15

MB90520A/520B Series

(Continued)

Type

Circuit

Remarks

• CMOS hysteresis input

• CMOS level output

• Also used as analog input.

• With standby control

VCC

Pch

Digital output

Hysteresis input

Nch

VSS

K

R

IOL = 4 mA

Standby control

Analog input

• CMOS hysteresis input

• CMOS level output

• Also used as segment output pin.

• With standby control

VCC

Pch

Digital output

(only available when segment

output is not operating.)

Digital output

Nch

VSS

L

R

IOL = 4 mA

Hysteresis input

Standby control

Segment output/common output

• CMOS hysteresis input

• N-ch open-drain output

• Also used as segment output pin.

• With standby control

VCC

Pch

(only available when segment

output is not operaing.)

Open drain

Nch

VSS

M

R

Hysteresis input

IOL = 10 mA

Standby control

Segment output

• Reference voltage pin for LCD

controller

VCC

Pch

R

N

Nch

VSS

IOL = 10 mA

16

MB90520A/520B Series

■ HANDLING DEVICES

Take note of the following points when handling devices :

• Do not exceed maximum rated voltage (to prevent latch-up)

• Supply voltage stability

• Power-on precautions

• Power supply pins

• Crystal oscillator circuit

• Notes on using an external clock

• Precautions when not using sub-clock mode

• Treatment of unused pins

• Treatment of N.C. pins

• Treatment of pins when A/D converter is not used

• Sequence for connecting and disconnecting the A/D converter power supply and analog input pins

• Shared use of general-purpose I/O ports and LCD controller/driver SEG/COM pins

• Conditions when output from ports 0 and 1 is undefined

• Initialization

• Notes on using the DIV A, Ri and DIVW A, RWi instructions

• Notes on using REALOS

Device Handling Precautions

• Do not exceed maximum rated voltage (to prevent latch-up)

Latch-up occurs in CMOS ICs if a voltage greater than V^CCor less than VSS is applied to an input or output pin

(other than a high or medium withstand voltage pin) or if the voltage applied between VCC and VSS exceeds

the rating. If latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit

elements. Therefore, ensure that maximum ratings are not exceeded in circuit operation.

Similarly, when turning the analog power supply on or off, ensure the analog power supply voltages (AV^CC,

AVRH, DVCC) and analog input voltages do not exceed the digital voltage (VCC) .

Also ensure that the voltages applied to the LCD power supply pins (V3 to V0) do not exceed the power supply

voltage (V^CC) .

• Supply voltage stability

Rapid changes in supply voltage may cause the device to misoperate, even if the voltage remains within the

allowed operating range. Accordingly, ensure that the V^CCsupply is stable.

The standard for power supply voltage stability is a peak-to-peak VCC ripple voltage at the mains supply

frequency (50 to 60 Hz) of 10% or less of VCC and a transient voltage change rate of 0.1 V/ms or less when

turning the power supply on or off.

• Power-on precautions

To prevent misoperation of the internal regulator circuit at power-on, ensure that the power supply rising time

(0.2 V to 2.7 V) is at least 50 µs.

• Power supply pins

When multiple V^CCand VSS pins are provided, connect all VCC and VSS pins to power supply or ground externally.

Although pins at the same potential are connected together in the internal device design so as to prevent

misoperation such as latch-up, connecting all V^CCand VSS pins appropriately minimizes unwanted radiation,

prevents misoperation of strobe signals due to increases in the ground level, and keeps the overall output

current rating.

Also, ensure that the impedance of the VCC and VSS connections to the power supply are as low as possible.

17

MB90520A/520B Series

Connection of a bypass capacitor of approximately 0.1 µF between V^CCand VSS is recommended to prevent

power supply noise. Connect the capacitor close to the VCC and VSS pins.

• Crystal oscillator circuit

Noise on the X0 and X1 pins can be a cause of device misoperation. Place the X0 and X1 pins, crystal oscillator

(or ceramic oscillator) , and bypass capacitor to ground as close together as possible. Also, design the circuit

board so that the X0 and X1 pin wiring does not cross other wiring.

Surrounding the X0/X1 and X0A/X1A pins with ground in the printed circuit board design is recommended to

ensure stable operation.

• Notes on using an external clock

When using an external clock, drive the X0 pin only and leave the X1 pin open.

The figure below shows an example of how to use an external clock.

Example of how to use an external clock

X0

Open circuit

X1

MB90520A/520B series

• Precautions when not using sub-clock mode

Connect an oscillator to X0A and X1A, even if not using sub-clock mode.

• Treatment of unused pins

Leaving unused input pins unconnected can cause misoperation or permanent damage to the device due to

latchup. Always pull-up or pull-down unused pins using a 2 kΩ or larger resistor.

If some I/O pins are unused, either set as outputs and leave open circuit or set as inputs and treat in the same

way as input pins.

• Treatment of N.C. pins

Always leave N.C. (non connect) pins open circuit.

• Treatment of pins when A/D converter not used

When not using the A/D converter and D/A converter, always connect AV^CC= DVCC = AVRH = VCC and AVSS =

AVRL = V^SS.

• Sequence for connecting and disconnecting the A/D converter power supply and analog input pins

Do not apply voltage to the A/D and D/A converter power supply (AVCC, AVRH, AVRL, DVCC, DVSS) or analog

inputs (AN0 to AN7) until the digital power supply (V^CC) is turned on.

When turning the device off, turn off the digital power supply after disconnecting the A/D converter power

supply and analog inputs. When turning the power on or off, ensure that AVRH and DVCC do not exceed AVCC

(turning the analog and digital power supplies on and off simultaneously is OK) .

• Shared use of general-purpose I/O ports and LCD controller/driver SEG/COM pins

The SEG08 to SEG31 and COM0 to COM3 pins are shared with general-purpose I/O ports. The electrical

ratings for SEG08 to SEG23 and COM0 to COM3 are the same as for CMOS outputs and the electrical ratings

for SEG24 to SEG31 are the same as for N-ch open-drain ports.

18

MB90520A/520B Series

• Conditions when output from ports 0 and 1 is undefined

After turning on the power supply, the outputs from ports 0 and 1 are undefined during the oscillation stabili-

zation delay time controlled by the regulator circuit (during the power-on reset) . The figure below shows the

timing.

Note that this undefined output period does not occur on products without an internal regulator circuit as these

products do not have an oscillation stabilization delay time.

Timing chart for undefined output from ports 0 and 1

Oscillation stabilization delay time^*2

Regulator circuit stabilization

delay time^*1

VCC (Power supply pin)

PONR (Power-on reset) signal

RST (External asynchronous reset) signal

RST (Internal reset) signal

Oscillation clock signal

KA (Internal operating clock A) signal

KB (Internal operating clock B) signal

Undefined output time

PORT (port output) signal

*1 : Regulator circuit oscillation stabilization delay time : 2¹⁷/Oscillation clock frequency

(approx. 8.19 ms for a 16 MHz oscillation clock frequency)

*2 : Oscillation stabilization delay time : 2¹⁸/Oscillation clock frequency

(approx. 16.38 ms for a 16 MHz oscillation clock frequency)

Note : Seethe“■PRODUCTLINEUP”sectionfordetailsofwhichMB90520A/520Bseriesproductshaveaninternal

regulator circuit.

• Initialization

The device contains internal registers that are only initialized by a power-on reset. To initialize these registers,

restart the power supply.

• Notes on using the DIV A, Ri and DIVW A, RWi instructions

Set the corresponding bank registers (DTB, ADB, USB, SSB) to “00^H” when using the signed division instruc-

tions “DIV A, Ri” and “DIVW A, RWi”.

If the corresponding bank registers (DTB, ADB, USB, SSB) are set to other than “00H”, the remainder value

produced by the instruction is not stored in the instruction operand register.

• Notes on using REALOS

The extended intelligent I/O service (EI OS) cannot be used when using REALOS.

2

Caution on Operations during PLL Clock Mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even

when there is no external oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed.

19

MB90520A/520B Series

• BLOCK DIAGRAM

8

4

Ports 8, 9^*3, A

24

P80/SEG16 to P87/SEG23

F²MC-16LX

CPU

P90/SEG24 to P97/SEG31

PA0/SEG08 to PA7/SEG15

LCD

controller/

driver

4

Main clock

X0, X1

SEG00 to SEG07

V0 to V3

Clock controller^*1

Sub-clock

X0A, X1A

(Includes

P74/COM0 to P77/COM3

RST

HST

timebase timer)

Port 0^*2

Port 7

16-bit

reload

timer 0

P07

7

DTP/

P00/INT0 to P06/INT6

16-bit

reload

timer 1

external

interrupt

circuit

P70/TI0/OUT4

P71/TO0/OUT5

P72/TI1/OUT6

P73/TO1/OUT7

16-bit

I/O timer 2

Port 2

Output

4

compare 1

(OCU)

P24/AIN0

P25/BIN0

P26/ZIN0/INT7

8/16-bit

3

up/down

16-bit

freerun

timer 1

counter/

timer 0, 1

16-bit

I/O timer 1

Input

2

P20/IC00

P21/IC01

P22/IC10

P23/IC11

capture 0

(ICU)

16-bit

freerun

timer 0

Port 6

8

P32/OUT0

P33/OUT1

P34/OUT2

P35/OUT3

P60/AN0 to P67/AN7

Output

4

compare 0

(OCU)

AVCC

AVSS

AVRH

AVRL

8/10-bit

A/D

converter

Clock

P31/CKOT

output

P30

P36/PG00

P37/PG01

Port 3

P27/ADTG

2

8/16-bit

PPG

2

P40/PG10

P41/PG11

timer 0, 1

Port 2

P42/SIN0

P43/SOT0

P44/SCK0

Interrupt controller

Port 5

UART

(SCI)

P45/SIN1

P46/SOT1

P47/SCK1

P50/SIN2/AIN1

P51/SOT2/BIN1

P52/SCK2/ZIN1

SIO ch.1

SIO ch.2

Port 4^*2

Port 1^*2

P53/DA0

P54/DA1

2

8-bit

D/A

converter

× 2 ch

8

Wakeup

interrupts

P10/WI0 to P17/WI7

DVCC

DVSS

Other pins

MD0 to MD2, C,

VCC, VSS

RAM

ROM

*1 : The clock control circuit includes the watchdog timer and timebase timer low power consumption control

circuits.

*2 : Incorporates a pull-up register setting register. CMOS level input and output.

*3 : As this port shares pins with the LCD output, the port uses N-ch open-drain circuits.

20

MB90520A/520B Series

■ MEMORY MAP

Single chip mode with mirror function

FFFFFFH

ROM area

Address #1

FE0000H

010000H

ROM area

(image of

FF bank)

Address #2

004000H

002000H

Address #3

Registers

RAM

000100H

0000C0H

000000H

Peripherals

Address #1^*

FF0000H

Address #2^*

004000H

Address #3^*

001100H

001900H

Part No.

MB90522A/B

MB90523A/B

MB90F523B

MB90V520A

FE0000H

004000H

FE0000H

004000H

: Internal memory access

: Access prohibited

* : The values of addresses #1, #2, and #3 vary by product.

Note : The upper part of 00 bank contains a mirror of the ROM data in FF bank. This is called the mirror ROM

function and enables use of the C compiler’s small memory model. As the lower 16 bits of the FF bank and

00 bank addresses are the same, tables located in ROM can be referenced without needing to declare far

pointers.

For example, accessing 00C000^Hactually accesses the contents of ROM at FFC000H. Note that, as the FF

bank ROM area exceeds 48 KBytes, the entire ROM image cannot be mirrored in 00 bank. Accordingly, as

ROM data from FF4000^Hto FFFFFFH is mirrored in 004000H to 00FFFFH, always locate ROM data tables in

the range FF4000^Hto FFFFFFH.

21

MB90520A/520B Series

■ I/O MAP

Abbreviated

Register

Name

Address

Register Name

Port 0 data register

Peripheral Name

Initial Value

000000^H

000001H

000002H

000003H

000004H

000005H

000006H

000007H

000008H

000009H

00000AH

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

PDR7

PDR8

PDR9

PDRA

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

XXXXXXXXB

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

Port 5 data register

Port 6 data register

Port 7 data register

Port 8 data register

Port 9 data register

Port A data register

Port 7,

LCD controller/driver

00000BH

LCDCMR

OCP4

Port 7/COM pin selection register

OCU compare register ch.4

XXXX 0 00 0B

00000CH

00000DH

00000EH

00000F^H

000010H

000011H

000012H

000013H

000014H

000015H

000016H

000017H

000018H

000019H

00001AH

00001BH

00001CH

00001DH

00001EH

00001FH

XXXXXXXX^B

XXXXXXXXB

16-bit I/O timer

(Access prohibited)

EIFR

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

DDR7

DDR8

DDR9

DDRA

ADER

Wakeup interrupt flag register

Port 0 direction register

Port 1 direction register

Port 2 direction register

Port 3 direction register

Port 4 direction register

Port 5 direction register

Port 6 direction register

Port 7 direction register

Port 8 direction register

Port 9 direction register

Port A direction register

Analog input enable register

Wakeup interrupts

Port 0

XXXXXXX0B

0 00 0 0 0 0 0B

XXX0 0 0 00B

0 00 0 0 0 0 0B

1 11 1 1 1 1 1B

XXXXXXXX^B

XXXXXXXXB

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port 6, A/D converter

OCP5

OCU compare register ch.5

16-bit I/O timer

(Access prohibited)

Wakeup interrupt enable register

EICR

Wakeup interrupts

0 00 0 0 0 0 0B

(Continued)

22

MB90520A/520B Series

Abbreviated

Register

Name

Address

Register Name

Serial mode register

Peripheral Name

Initial Value

000020^H

000021H

SMR

SCR

0 00 0 0 0 0 0B

0 00 0 0 1 0 0B

Serial control register

UART

(SCI)

SIDR/

SODR

Serial input data register/

Serial output data register

000022H

XXXXXXXXB

000023H

000024H

000025H

000026H

SSR

Serial status register

0 0 0 0 1X 0 0B

XXXX 0 00 0B

0 00 0 0 0 1 0B

XXXXXXXXB

SMCS1

Serial mode control status register 1

Serial data register 1

Extended I/O serial

interface 1

SDR1

CDCR

Communication prescaler control

register

Communicationprescaler

register

000027H

0 XXX 1 1 11B

000028H

000029H

00002AH

00002BH

00002C^H

00002DH

00002EH

00002FH

000030H

000031H

000032H

000033H

000034H

000035H

000036H

000037H

000038H

000039H

00003AH

00003BH

00003CH

00003DH

00003EH

XXXX 0 00 0B

0 00 0 0 0 1 0B

XXXXXXXXB

SMCS2

SDR2

Serial mode control status register 2

Serial data register 2

Extended I/O serial

interface 2

(Access prohibited)

00 0 0 XX 0 0B

XXX0 0 0 00B

00 0 0 XX 0 0B

XXX0 0 0 00B

0 00 0 0 0 0 0B

XXXXXXXXB

0 00 0 0 0 0 0B

XXXXXXXX^B

XXXXXXXXB

0 00 0 0 0 0 0B

XXXXXXXX^B

0 0 00 1 XXXB

XXXXXXXXB

XXXXXXX0B

OCS45

OCS67

OCU control status register ch.45

OCU control status register ch.67

16-bit I/O timer

ENIR

EIRR

DTP/interrupt enable register

DTP/interrupt request register

DTP /external interrupt

circuit

ELVR

OCP6

ADCS

ADCR

Request level setting register

OCU compare register ch.6

A/D control status register

A/D data register

16-bit I/O timer

8/10-bit A/D converter

DADR0

DADR1

DACR0

DACR1

CLKR

D/A converter data register ch.0

D/A converter data register ch.1

D/A control register 0

8-bit D/A converter

D/A control register 1

Clock output enable register

Clock monitor function

XXXX 0 00 0B

(Continued)

23

MB90520A/520B Series

Abbreviated

Register

Name

Address

Register Name

(Access prohibited)

Peripheral Name

Initial Value

00003F^H

000040^H

000041H

000042H

000043H

000044H

000045H

000046H

000047H

000048^H

000049H

00004AH

00004BH

00004CH

00004DH

00004EH

00004FH

000050H

000051H

000052H

000053H

000054H

000055H

000056^H

000057H

000058H

000059H

00005A^H

00005BH

00005CH

00005DH

00005EH

00005FH

PRLL0

PRLH0

PRLL1

PRLH1

PPGC0

PPGC1

PPGOE

PPG0 reload register L

XXXXXXXXB

0 X 0 00 XX1B

0 X 0 0 00 0 1B

0 00 0 0 0 0 0B

PPG0 reload register H

PPG1 reload register L

PPG1 reload register H

8/16-bit PPG timer 0, 1

PPG0 operation mode control register

PPG1 operation mode control register

PPG0, 1 output control register

(Access prohibited)

0 00 0 0 0 0 0B

XXXX 00 0 0B

XXXXXXXX^B

XXXXXXXXB

0 00 0 0 0 0 0B

XXXX 00 0 0B

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

000 0 0 0 0 0B

TMCSR0

Timer control status register ch.0

16-bit reload timer 0

16-bit reload timer 1

TMR0/

TMRLR0

16-bit timer register ch.0/

16-bit reload register ch.0

TMCSR1

Timer control status register ch.1

TMR1/

TMRLR1

16-bit timer register ch.1/

16-bit reload register ch.1

IPCP0

ICU data register ch.0

16-bit I/O timer

IPCP1

ICS01

ICU data register ch.1

ICU control status register

(Access prohibited)

0 00 0 0 0 0 0B

000 0 0 0 0 0B

TCDT0

TCCS0

Freerun timer data register 0

Freerun timer control status register 0

(Access prohibited)

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

OCP0

OCP1

OCP2

OCU compare register ch.0

OCU compare register ch.1

OCU compare register ch.2

16-bit I/O timer

XXXXXXXXB

(Continued)

24

MB90520A/520B Series

Abbreviated

Register

Name

Address

Register Name

Peripheral Name

Initial Value

000060^H

000061H

000062H

000063H

000064H

000065H

000066H

000067H

000068H

000069H

00006AH

00006BH

00006CH

00006DH

00006EH

XXXXXXXX^B

XXXXXXXXB

00 0 0 XX 0 0B

XXX0 0 0 00B

00 0 0 XX 0 0B

XXX0 0 0 00B

0 00 0 0 0 0 0B

000 0 0 0 0 0B

OCP3

OCS01

OCS23

OCU compare register ch.3

OCU control status register ch.0, ch.1

OCU control status register ch.2, ch.3

16-bit I/O timer

TCDT1

TCCS1

Freerun timer data register 1

16-bit I/O timer

Freerun timer control status register 1

(Access prohibited)

LCR0

LCR1

LCDC control register 0

LCDC control register 1

0 00 1 0 0 0 0B

0 00 0 0 0 0 0B

XXXXXXXX^B

XXXXXXXXB

LCD controller/driver

16-bit I/O timer

OCP7

OCU compare register ch.7

(Access prohibited)

ROM mirror function

selection module

00006F^H

ROMM

VRAM

ROM mirror function selection register

XXXXXXX1B

XXXXXXXXB

000070H

to

Data memory for LCD display

LCD controller/driver

00007FH

000080H

000081H

000082H

000083H

000084H

000085H

000086H

000087H

000088H

000089H

00008AH

00008BH

UDCR0

UDCR1

RCR0

Up/down count register 0

Up/down count register 1

Reload compare register 0

Reload compare register 1

Counter status register 0

(Reserved) ^*3

0 00 0 0 0 0 0B

000 0 0 0 0 0B

8/16-bit up/down

counter/timer 0, 1

RCR1

CSR0

X 0 0 0 00 0 0B

0 00 0 0 0 0 0B

000 0 0 0 0 0B

CCR0

CSR1

Counter control register 0

8/16-bit up/down

counter/timer 0, 1

Counter status register 1

(Reserved) ^*3

X 0 0 0 00 0 0B

8/16-bit up/down

counter/timer 0, 1

CCR1

Counter control register 1

Port 0

00008CH

00008DH

RDR0

RDR1

Port 0

Port 1

0 00 0 0 0 0 0B

input pull-up resistor setup register

Port 1

0 00 0 0 0 0 0B

(Continued)

input pull-up resistor setup register

25

MB90520A/520B Series

Abbreviated

Register

Name

Address

Register Name

Peripheral Name

Initial Value

Port 4

input pull-up resistor setup register

00008E^H

RDR4

Port 4

0 0 0 00 0 0 0B

00008FH

to

00009DH

(Access prohibited)

(Area reserved for system use) ^*4

Address match detection

00009EH

00009FH

PACSR

DIRR

Address detection control register

0 0 0 00 0 0 0B

XXXXXXX 0B

function

Delayed interrupt request output/clear

register

Delayed interrupt

generation module

Low power consumption mode control

register

0000A0H

0000A1H

LPMCR

CKSCR

0 0 0 11 0 0 0B

11 1 11 1 0 0B

Low power consumption

(standby) mode

Clock selection register

0000A2H

to

(Access prohibited)

0000A7H

0000A8^H

0000A9H

0000AAH

WDTC

TBTC

WTC

Watchdog timer control register

Timebase timer control register

Clock timer control register

Watchdog timer

Timebase timer

Clock timer

XXXXXXXXB

1 XX 0 00 0 0B

1 X0 0 1 0 00B

0000ABH

to

(Access prohibited)

0000ADH

0000AE^H

0000AFH

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

0000BDH

FMCS

Flash memory control status register

1 Mbit flash memory

0 00 X 0 0 00B

(Access prohibited)

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

Interrupt control register 00

Interrupt control register 01

Interrupt control register 02

Interrupt control register 03

Interrupt control register 04

Interrupt control register 05

Interrupt control register 06

Interrupt control register 07

Interrupt control register 08

Interrupt control register 09

Interrupt control register 10

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

0 0 0 00 1 1 1B

Interrupt controller

0 0 0 00 1 1 1B

(Continued)

26

MB90520A/520B Series

(Continued)

Abbreviated

Register

Name

Address

Register Name

Peripheral Name

Initial Value

0000BEH

0000BFH

ICR14

ICR15

Interrupt control register 14

Interrupt control register 15

0 0 0 00 1 1 1B

Interrupt controller

0000C0H

to

(Access prohibited) ^*1

0000FFH

000100H

to

(RAM area) ^*2

00####H

to

(Reserved area) ^*3

001FEFH

Detection address setting register 0

(low byte)

001FF0H

001FF1H

001FF2H

001FF3H

001FF4H

001FF5H

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

Detection address setting register 0

(middle byte)

PADR0

PADR1

Detection address setting register 0

(high byte)

Address match

detection function

Detection address setting register 1

(low byte)

Detection address setting register 1

(middle byte)

Detection address setting register 1

(high byte)

001FF6H

to

(Reserved area) ^*3

001FFFH

Initial value notation

0

: Initial value of bit is “0”.

: Initial value of bit is “1”.

: Initial value of bit is undefined.

1

X

*1 : Access is prohibited to the address range 0000C0^Hto 0000FFH. See the “■ MEMORY MAP” section.

*2 : See the “■ MEMORY MAP” section for details of the “ (RAM area) ”.

*3 : “ (Reserved areas) ” are addresses used internally by the system and may not be used.

*4 : The “ (Area reserved for system use) ” contains setting registers used by the evaluation tools.

Notes : • LPMCR, CKSCR, and WDTC are initialized by some types of reset and not by others. The initial values

listed are for the case when the registers are initialized.

• The boundary address “####^H” between the “ (RAM area) ” and “ (Reserved area) ” differs depending on

the product. See the “■ MEMORY MAP” section for details.

• OCU compare registers ch.0 to ch.3 use 16-bit freerun timer 0 and OCU compare registers ch.4 to ch.7

use 16-bit freerun timer 1. Note that 16-bit freerun timer 0 is also used by input capture 0 and 1 (ICU) .

27

MB90520A/520B Series

■ INTERRUPTS, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

Interrupt Vector Interrupt Control Register

2

EI OS

Interrupt

Priority

Support

No.

Address

ICR

Address

×

Reset

#08 FFFFDC^H

High

INT 9 instruction

Exception

#09

#10

#11

FFFFD8^H

FFFFD4^H

FFFFD0H

8/10-bit A/D converter

Timebase timer

ICR00

ICR01

ICR02

ICR03

0000B0H

0000B1H

0000B2H

0000B3H

×

#12 FFFFCCH

DTP0/DTP1

(external interrupt 0/external interrupt 1)

#13

FFFFC8H

×

16-bit freerun timer 0 overflow

Extended I/O serial interface 1

Wakeup interrupt

#14

#15

FFFFC4H

FFFFC0H

#16 FFFFBCH

Extended I/O serial interface 2

#17

#18

#19

FFFFB8H

FFFFB4H

FFFFB0H

DTP2/DTP3

(external interrupt 2/external interrupt 3)

×

8/16-bit PPG timer 0 counter borrow

ICR04

ICR05

ICR06

0000B4H

0000B5H

0000B6H

DTP4/DTP5

(external interrupt 4/external interrupt 5)

#20 FFFFACH

8/16-bit up/down counter/timer 0

compare match

#21

FFFFA8H

8/16-bit up/down counter/timer 0

overflow, up/down direction change

#22

#23

#24

FFFFA4H

FFFFA0H

FFFF9CH

×

8/16-bit PPG timer 1 counter borrow

DTP6/DTP7

(external interrupt 6/external interrupt 7)

Output compare 1 (OCU) ch.4, ch.5 match

Clock timer

#25

#26

#27

#28

FFFF98H

FFFF94H

FFFF90H

FFFF8CH

ICR07

ICR08

0000B7H

0000B8H

×

Output compare 1 (OCU) ch.6, ch.7 match

16-bit freerun timer 1 overflow

8/16-bit up/down counter/timer 1

compare match

#29

#30

FFFF88H

FFFF84H

ICR09

0000B9H

8/16-bit up/down counter/timer 1

overflow, up/down direction change

Input capture 0 (ICU) capture

#31

#32

#33

#34

FFFF80H

FFFF7CH

FFFF78H

FFFF74H

ICR10

ICR11

0000BAH

0000BBH

Input capture 1 (ICU) capture

Output compare 0 (OCU) ch.0 match

Output compare 0 (OCU) ch.1 match

(Continued)

28

MB90520A/520B Series

(Continued)

Interrupt Vector Interrupt Control Register

Priority

2

EI OS

Interrupt

Support

No.

#35

#36

#37

#38

#39

#40

#41

#42

Address

FFFF70^H

FFFF6CH

FFFF68H

FFFF64H

FFFF60H

FFFF5CH

FFFF58H

FFFF54H

ICR

Address

Output compare 0 (OCU) ch.2 match

Output compare 0 (OCU) ch.3 match

UART (SCI) receive complete

16-bit reload timer 0

ICR12

0000BCH

ICR13

ICR14

ICR15

0000BDH

0000BEH

0000BFH

UART (SCI) send complete

16-bit reload timer 1

×

Flash memory

Delayed interrupt generation module

Low

: Supported

×

: Not supported

: Supported, includes EI OS stop function

2

29

MB90520A/520B Series

■ PERIPHERAL RESOURCES

1. I/O Ports

• The I/O ports can be used as general-purpose I/O ports (parallel I/O ports) . The MB90520A and 520B series

have 11 ports (85 pins) . The ports share pins with the inputs and outputs of the peripheral functions.

• The port data registers (PDR) are used to output data to the I/O pins and capture the input signals from the

I/O ports.

Similarly, the port direction registers (DDR) set the I/O direction (input or output) for each individual port bit.

• The following tables list the I/O ports and peripheral functions with which they share pins.

Pin Name

Pin Name (Peripheral)

Peripheral Function that Shares Pin

External interrupts

(Port)

P00 − P06

P07

INT0 − INT6

Port 0

Port 1

Not shared

P10 − P17

P20 − P23

P24, P25

P26

WI0 − WI7

IN00 − IN11

AIN0, BIN0

ZIN0/INT7

Wakeup interrupts

Input capture (unit 0)

8/16-bit up/down counter/timer 0

8/16-bit up/down counter/timer 0, external interrupt

Not shared

Port 2

Port 3

Port 4

P30

P31

CKOT

Clock monitor function

Output compare (unit 0)

8/16-bit PPG timer 0

P32 − P35

P36, P37

P40, P41

P42 − P44

P45 − P47

OUT0 − OUT3

PPG00, PPG01

PPG10, PPG11

SIN0, SOT0, SCK0

SIN1, SOT1, SCK1

8/16-bit PPG timer 1

UART (SCI)

Extended I/O serial interface 0

SIN2/AIN1,

SOT1/BIN1,

SCK1/ZIN1

8/16-bit up/down counter/timer 0

Extended I/O serial interface 1

P50 − P52

Port 5

Port 6

P53, P54

DA0, DA1

8-bit D/A converter

P60 − P67

AN0 − AN7

8/16-bit A/D converter

TIN0/OUT4,

TOT0/OUT5,

TIN1/OUT6,

TOT1/OUT7

16-bit reload timers 0, 1

Output compare (unit 1)

P70 − P73

Port 7

P74 − P77

P80 − P87

P90 − P97

PA0 − PA7

COM0 − COM3

SEG16 − SEG23

SEG24 − SEG31

SEG8 − SEG15

LCD control driver common output

LCD control driver segment output

Port 8

Port 9

Port A

Notes

• Port 9 contains general-purpose I/O ports with N-ch open-drain output circuits.

• Connect an external pull-up resistor when using port 9 pins as outputs.

• Port 6 shares pins with the analog inputs. When using port 6 as a general-purpose port, ensure that the

corresponding analog input enable register (ADER) bits are set to “0”. ADER is initialized to “FF^H” after a reset.

30

MB90520A/520B Series

• Block diagrams

P00 to P07, P10 to P17

Pull-up resistor

option connect/

disconnect setting

Peripheral function input

PDR (Port data register)

Pch

PDR read

PDR write

Output latch

Pch

DDR (Port direction register)

Nch

Direction latch

DDR write

Standby control (SPL = 1)

DDR read

Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,

and hardware standby mode

P20 to P27

Peripheral function input

PDR (Port data register)

PDR read

Output latch

Pch

PDR write

DDR (Port direction register)

Nch

Direction latch

DDR write

DDR read

Standby control (SPL = 1)

Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,

and hardware standby mode

31

MB90520A/520B Series

P40 to P47

Pull-up resistor

option connect/

disconnect setting

Peripheral function input*

PDR (Port data register)

Peripheral function output*

Peripheral function

output approval*

Pch

PDR read

Pch

Nch

Output latch

PDR write

DDR (Port direction register)

Direction latch

DDR write

Standby control (SPL = 1)

DDR read

Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,

and hardware standby mode

* : Peripheral function I/O is equivalent to I/O of peripheral function.

P30 to P37, P50 to P52, P70 to P73

Peripheral function input*

PDR (Port data register)

Peripheral function output*

Peripheral function

output approval*

PDR read

Pch

Output latch

PDR write

DDR (Port direction register)

Nch

Direction latch

DDR write

Standby control (SPL = 1)

DDR read

Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,

and hardware standby mode

* : Peripheral function I/O is equivalent to I/O of peripheral function.

32

MB90520A/520B Series

P53, P54

D/A analog pin

output approval

D/A analog output

PDR (Port data register)

PDR read

Output latch

Pch

PDR write

DDR (Port direction register)

Nch

Direction latch

DDR write

Standby control (SPL = 1)

DDR read

Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,

and hardware standby mode

P74 to P77

Common pin

output approval

LCD common output

PDR (Port data register)

PDR read

Output latch

Pch

PDR write

DDR (Port direction register)

Nch

Direction latch

DDR write

Standby control (SPL = 1)

DDR read

Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,

and hardware standby mode

33

MB90520A/520B Series

P60 to P67

Analog input

PDR (Port data register)

PDR read

Output latch

Pch

Nch

PDR write

DDR (Port direction register)

Direction latch

DDR write

Standby control (SPL = 1)

DDR read

Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,

and hardware standby mode

P80 to P87, PA0 to PA7

Segment pin

output approval

LCD Segment output

PDR (Port data register)

PDR read

Output latch

Pch

PDR write

DDR (Port direction register)

Nch

Direction latch

DDR write

Standby control (SPL = 1)

DDR read

Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,

and hardware standby mode

34

MB90520A/520B Series

P90 to P97

Segment pin

output approval

LCD Segment output

PDR (Port data register)

PDR read

Output latch

PDR write

DDR (Port direction register)

Nch

Direction latch

DDR write

Standby control (SPL = 1)

DDR read

Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,

and hardware standby mode

35

MB90520A/520B Series

2. Timebase Timer

• The timebase timer is an 18-bit freerun timer (timebase timer/counter) that counts up synchronized with the

main clock (oscillation clock : HCLK divided by 2) .

• The timer can generate interrupt requests at a specified interval, with four different interval time settings

available.

• The timer supplies the operating clock for peripheral functions including the oscillation stabilization delay timer

and watchdog timer.

• Timebase timer interval settings

Internal Count Clock Period

Interval Time

2¹²/HCLK (approx. 1.024 ms)

2¹⁴/HCLK (approx. 4.096 ms)

2¹⁶/HCLK (approx. 16.384 ms)

2/HCLK (0.5 µs)

2¹⁹/HCLK (approx. 131.072 ms)

• HCLK : Oscillation clock frequency

• The values enclosed in ( ) indicate the times for a clock frequency of 4 MHz.

• Period of clocks supplied from timebase timer

Peripheral Function

Clock Period

2¹⁰/HCLK (approx. 0.256 ms)

2¹³/HCLK (approx. 2.048 ms)

2¹⁵/HCLK (approx. 8.192 ms)

2¹⁷/HCLK (approx. 32.768 ms)

2¹²/HCLK (approx. 1.024 ms)

2¹⁴/HCLK (approx. 4.096 ms)

2¹⁶/HCLK (approx. 16.384 ms)

2¹⁹/HCLK (approx. 131.072 ms)

2⁹/HCLK (approx. 0.128 ms)

Oscillation stabilization delay

for the main clock

Watchdog timer

PPG timer

• HCLK : Oscillation clock frequency

• The values enclosed in ( ) indicate the times for a clock frequency of 4 MHz.

36

MB90520A/520B Series

• Block diagram

To PPG timer

To watchdog timer

Timebase timer/counter

HCLK divided

by 2

× 2¹× 2²× 2³

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

OF

To oscillation

stabilization delay

time selector

in clock controller

Reset^*1

Clear stop mode, etc.^*2

Switch clock mode^*3

Counter clear

circuit

Interval timer

selector

TBOF clear

TBOF set

Timebase timer control register

(TBTC)

TBIE TBOF TBR TBC1 TBC0

Timebase timer interrupt signal

OF : Overflow

HCLK : Oscillation clock frequency

*1

*2

*3

: Power-on reset, release of hardware standby mode, watchdog reset

: Clear stop mode, main clock mode, PLL clock mode, and pseudo-clock mode

: Main → PLL clock, Sub → main clock, Sub → PLL clock

The actual interrupt request number for the timebase timer is :

Interrupt request number : #12 (0C^H)

37

MB90520A/520B Series

3. Watchdog Timer

• The watchdog timer is a timer/counter used to detect faults such as program runaway.

• The watchdog timer is a 2-bit counter that counts the clock signal from the timebase timer or clock timer.

• Once started, the watchdog timer must be cleared before the 2-bit counter overflows. If an overflow occurs,

the CPU is reset.

• Interval time for the watchdog timer

HCLK : Oscillation Clock (4 MHz)

SCLK : Sub-Clock (8.192 kHz)

Min Max Clock Period

Min

Approx. 3.58 ms

Max

Clock Period

Approx. 4.61 ms

2

¹⁴± 2¹¹/ HCLK Approx. 0.438 s Approx. 0.563 s 2¹²± 2⁹/ SCLK

¹⁶± 2¹³/ HCLK Approx. 3.500 s Approx. 4.500 s 2¹⁵± 2¹²/ SCLK

¹⁸± 2¹⁵/ HCLK Approx. 7.000 s Approx. 9.000 s 2¹⁶± 2¹³/ SCLK

Approx. 14.33 ms Approx. 18.30 ms

Approx. 57.23 ms Approx. 73.73 ms

Approx. 458.75 ms Approx. 589.82 ms 2²¹± 2¹⁸/ HCLK Approx. 14.00 s Approx. 18.00 s 2¹⁷± 2¹⁴/ SCLK

* : The difference between the maximum and minimum watchdog timer interval times is due to the timing when the

counter is cleared.

* : As the watchdog timer is a 2-bit counter that counts the carry-up signal from the timebase timer or clock timer,

clearing the timebase timer (when operating on HCLK) or the clock timer (when operating on SCLK) lengthens

the time until the watchdog timer reset is generated.

• Watchdog timer count clock

HCLK : Oscillation clock

WTC : WDCS

SCLK : Sub-clock

PCLK : PLL clock

“0”

“1”

Count the clock timer output.

Count the timebase timer output.

Count the clock timer output.

• Events that stop the watchdog timer

1 : Stop due to a power-on reset

2 : Reset due to recovery from hardware standby mode

3 : Watchdog reset

• Events that clear the watchdog timer

1 : External reset input from the RST pin.

2 : Writing “0” to the software reset bit.

3 : Writing “0” to the watchdog control bit (second and subsequent times) .

4 : Changing to sleep mode (clears the watchdog timer and temporarily halts the count) .

5 : Changing to pseudo-clock mode (clears the watchdog timer and temporarily halts the count) .

6 : Changing to clock mode (clears the watchdog timer and temporarily halts the count) .

7 : Changing to stop mode (clears the watchdog timer and temporarily halts the count) .

38

MB90520A/520B Series

• Block diagram

Watchdog timer control register (WDTC)

PONR STBR WRST ERST SRST WTE WT1 WT0

2

Watchdog timer

Start

Reset

To

Change to sleep mode

Change to pseudo-clock mode

Change to clock mode

Counter

clear

control circuit

Counter

clock

selector

Watchdog timer

reset

generation circuit

2-bit

counter

internal

reset

circuit

Change to stop mode

Clear

4

(Timebase timer/counter)

Main clock

(HCLK divided by 2)

× 2¹× 2²

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

(Clock counter)

× 2¹× 2²

× 2⁵× 2⁶× 2⁷× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵

Sub-clock

HCLK : Oscillation clock frequency

39

MB90520A/520B Series

4. 8/16-bit PPG (Programmable Pulse Generator) Timers 0 and 1

The 8/16-bit PPG timer is a two-channel reload timer module (PPG0 and PPG1) that can generate pulse outputs

with the periods specified in the table below and with duty ratios between 0 and 100%. Note that the pulse

periods are different depending on the operation mode.

PPG00, PPG01 (PPG ch0)

PPG10, PPG11 (PPG ch1)

Operation

Mode

Count Clock^*2

Output Pulse

Interval Time

Output Pulse

Interval Time

Width

φ/1 (62.5 ns)

φ/2 (125 ns)

φ/4 (250 ns)

φ/8 (500 ns)

φ/16 (1000 ns)

1/φ to 2⁸/φ

2/φ to 2⁹/φ

1/φ to 2⁹/φ

2²/φ to 2¹⁰/φ

2³/φ to 2¹¹/φ

2⁴/φ to 2¹²/φ

2⁵/φ to 2¹³/φ

1/φ to 2⁸/φ

2/φ to 2⁹/φ

1/φ to 2⁹/φ

2²/φ to 2¹⁰/φ

2³/φ to 2¹¹/φ

2⁴/φ to 2¹²/φ

2⁵/φ to 2¹³/φ

8-bit

2²/φ to 2¹⁰/φ

2³/φ to 2¹¹/φ

2⁴/φ to 2¹²/φ

2²/φ to 2¹⁰/φ

2³/φ to 2¹¹/φ

2⁴/φ to 2¹²/φ

PPG output

Independent

2ch operation

mode

2⁹/HCLK to

2¹⁷/HCLK

2¹⁰/HCLK to

2¹⁸/HCLK

2⁹/HCLK to

2¹⁷/HCLK

2¹⁰/HCLK to

2¹⁸/HCLK

HCLK/512 (128 µs)

φ/1 (62.5 ns)

φ/2 (125 ns)

φ/4 (250 ns)

φ/8 (500 ns)

φ/16 (1000 ns)

1/φ to 2¹⁶/φ

2/φ to 2¹⁷/φ

2²/φ to 2¹⁸/φ

2³/φ to 2¹⁹/φ

2⁴/φ to 2²⁰/φ

1/φ to 2¹⁷/φ

2²/φ to 2¹⁸/φ

2³/φ to 2¹⁹/φ

2⁴/φ to 2²⁰/φ

2⁵/φ to 2²¹/φ

1/φ to 2¹⁶/φ

2/φ to 2¹⁷/φ

2²/φ to 2¹⁸/φ

2³/φ to 2¹⁹/φ

2⁴/φ to 2²⁰/φ

1/φ to 2¹⁷/φ

2²/φ to 2¹⁸/φ

2³/φ to 2¹⁹/φ

2⁴/φ to 2²⁰/φ

2⁵/φ to 2²¹/φ

16-bit

PPG output

operation

mode

2⁹/HCLK to

2²⁵/HCLK

2¹⁰/HCLK to

2²⁶/HCLK

2⁹/HCLK to

2²⁵/HCLK

2¹⁰/HCLK to

2²⁶/HCLK

HCLK/512 (128 µs)

φ/1 (62.5 ns)

φ/2 (125 ns)

φ/4 (250 ns)

φ/8 (500 ns)

φ/16 (1000 ns)

1/φ to 2⁶/φ

2/φ to 2⁹/φ

1/φ to 2⁹/φ

2²/φ to 2¹⁰/φ

2³/φ to 2¹¹/φ

2⁴/φ to 2¹²/φ

2⁵/φ to 2¹³/φ

1/φ to 2¹⁶/φ

2/φ to 2¹⁷/φ

2²/φ to 2¹⁸/φ

2³/φ to 2¹⁹/φ

2⁴/φ to 2²⁰/φ

1/φ to 2¹⁷/φ

2²/φ to 2¹⁸/φ

2³/φ to 2¹⁹/φ

2⁴/φ to 2²⁰/φ

2⁵/φ to 2²¹/φ

8 + 8-bit

PPG output

operation

mode^*1

2²/φ to 2¹⁰/φ

2³/φ to 2¹¹/φ

2⁴/φ to 2¹²/φ

2⁹/HCLK to

2¹⁷/HCLK

2¹⁰/HCLK to

2¹⁸/HCLK

2⁹/HCLK to

2²⁵/HCLK

2¹⁰/HCLK to

2²⁶/HCLK

HCLK/512 (128 µs)

*1 : 8 + 8-bit PPG output operation mode consists of using the lower 8 bits as a prescaler for the PPG timer.

*2 : The values enclosed in ( ) indicate the times for a machine clock frequency of 16 MHz.

40

MB90520A/520B Series

• PPG timer channels and PPG pins

The figure below shows the relationship between the 8/16-bit PPG channels and PPG pins on the MB90520A/

520B series.

PPG0

PPG00 output pin

PPG01 output pin

PPG1

PPG10 output pin

PPG11 output pin

41

MB90520A/520B Series

• Block diagram

8/16-bit PPG timer 0

"H" level data bus

"L" level data bus

PPG0 reload

register

PPG0 operation mode control register

(PPGC0)

PEN0

PE00 PIE0 PUF0

Reserved

PRLH0

PRLL0

("H" level register) ("L" level register)

Interrupt

request output

R

S

PPG0 temporary

buffer (PRLBH0)

Q

2

Operation mode control signal

Reload register

"L" level/"H" level

selector

Select signal

PPG1 underflow

PPG0 underflow

(to PPG1)

Count start value

Reload

Underflow

Clear

Pulse selector

PPG0 down counter

(PCNT0)

CLK

PPG0

output latch

Invert

PPG00

PPG output control circuit

Timebase timer output

(HCLK/512)

Peripheral clock (φ/1)

Peripheral clock (φ/2)

Peripheral clock (φ/4)

Peripheral clock (φ/8)

Peripheral clock (φ/16)

Count

clock

selector

PPG01

3

Select signal

PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01

PPG01 output control register (PPGOE)

: Undefined

Reserved : Reserved bit

HCLK

: Oscillation clock frequency

: Machine clock frequency

φ

42

MB90520A/520B Series

8/16-bit PPG timer 1

"H" level data bus

"L" level data bus

PPG1 operation mode control register

(PPGC1)

PPG1

reload

PRLH1

PRLL1

PEN1

PE10 PIE1 PUF1 MD1 MD0 Reserved

2

("H" level register) ("L" level register)

register

Operation

mode control signal

Interrupt

R

PPG1 temporary

buffer (PRLBH1)

request output

S

Q

Reload selector

"L" level/"H"

level selector

Select signal

Clear

Count start value

Reload

Underflow

PPG1

output latch

PPG1 down counter

(PCNT1)

Invert

PPG10

CLK

PPG output control circuit

MD0

PPG1 underflow

(to PPG0)

PPG11

PPG0 underflow

(from PPG0)

Timebase timer output

(HCLK/512)

Peripheral clock (φ/1)

Peripheral clock (φ/2)

Peripheral clock (φ/4)

Peripheral clock (φ/8)

Peripheral clock (φ/16)

Count

clock

3

Select signal

selector

PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01

PPG01 output control register (PPGOE)

: Undefined

Reserved : Reserved bit

HCLK

: Oscillation clock frequency

: Machine clock frequency

φ

43

MB90520A/520B Series

5. 16-bit Reload Timers 0 and 1 (With Event Count Function)

The 16-bit reload timers have the following functions.

• The count clock can be selected from three internal clock and the external event clock.

• Either software trigger or external trigger can be selected as the start signals for 16-bit reload timers 0 and 1.

• An interrupt to the CPU can be generated when an underflow occurs on 16-bit reload timer 0 and 1. This

interrupt allows the timers to be used as interval timers.

• Two different operation modes can be selected when an underflow occurs on 16-bit reload timer 0 and 1 : one-

shot mode in which timer operation halts when an underflow occurs or reload mode in which the reload register

value is loaded into the timer and counting continues.

2

• Extended intelligent I/O service (EI OS) is supported.

• The MB90520A/520B series contains two 16-bit reload timer channels.

• 16-bit reload timer operation modes

Count Clock

Start Trigger

Operation when an Underflow Occurs

One-shot mode

Software trigger

Reload mode

Internal clock

(3 clocks available)

One-shot mode

External trigger

Software trigger

External trigger

Reload mode

One-shot mode

Reload mode

Event clock

One-shot mode

Reload mode

• Interval times for the 16-bit reload timers

Count Clock

Internal clock

Event clock

Count Clock Period

Example Interval Times

0.125 µs to 8.192 ms

0.5 µs to 32.768 ms

2.0 µs to 131.1 ms

0.5 µs or longer

2¹T (0.125 µs)

2³T (0.5 µs)

2⁵T (2.0 µs)

2³T or longer

Note : The values enclosed in ( ) and the example interval times are for a machine clock frequency of 16 MHz.

“T” is the machine cycle and is 1/ (machine clock frequency) .

44

MB90520A/520B Series

• Block diagram

Internal data bus

TMRLR

16-bit reload register

Reload signal

Reload

control circuit

TMR

UF

16-bit timer register

CLK

Count clock generation circuit

Gate

input

Clock

pulse

detection

circuit

Machine

clock

3

Wait signal

Prescaler

φ

Output to internal

peripheral functions

Clear

trigger

Output control circuit

Internal

clock

CLK

Output signal

generation

circuit

Input

control

circuit

Clock

selector

EN

TOT

TIN

External clock

Select

signal

3

2

Operation

control

Function selection

circuit

CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG

Timer control status register (TMCSR)

Interrupt

request output

45

MB90520A/520B Series

6. 16-bit I/O Timers

The 16-bit I/O timers consist of a two-channel 16-bit freerun timer, two-channel input capture, and eight-channel

output compare. The output compare channels can be used to generate eight independent waveform outputs

based on the 16-bit freerun timer. The input capture channels can be used to measure input pulse widths and

external clock periods.

•Structure of I/O timers in the MB90520A/520B series

16-bit Freerun Timer

Output Compare

Input Capture

16-bit I/O timer

(unit 0)

Output compare 0 to 3

(unit 0)

Input capture 0 and 1

(unit 0)

16-bit freerun timer 0

16-bit I/O timer

(unit 1)

Output compare 4 to 8

(unit 1)

16-bit freerun timer 1

• 16-bit freerun timer functions

• The count value for the 16-bit freerun timer sets the base time for the input capture and output compare

functions.

• An interrupt can be generated when the 16-bit freerun timer overflows.

2

• Extended intelligent I/O service (EI OS) can be generated.

• 16-bit freerun timers 0 and 1 can be cleared to “0000H” when an external reset is input, on setting the timer

clear bit (TCCS : CLR = 1) , and when a compare match occurs on output compare 0 to 4.

• The count clock frequency can be selected from the following four clocks :

4/φ (250 ns) , 16/φ (1.0 µs) , 64/φ (4.0 µs) , 256/φ (16.0 µs)

Note : φ is the machine clock frequency. The values in ( ) are for 16 MHz machine clock.

• Input capture functions

• The input capture saves the value of the 16-bit freerun timer and generates an interrupt request when the

specified edge is detected on the trigger input from the external trigger input pin (IC00 or IC01/IC10 or IC11) .

• Input capture channels 0 and 1 can perform input capture and generate interrupt request independently.

2

• Extended intelligent I/O service (EI OS) can be generated.

• Detection of rising edges, falling edges, or either edge can be selected as the trigger edge.

• When using input capture 0, either the IC00 or IC01 pin can be used. Note, however, that masking one pin

only is not possible.

• When using input capture 1, either the IC10 or IC11 pin can be used. Note, however, that masking one pin

only is not possible.

• Output compare functions

• The output compare channels compare the values set in output compare registers 0 to 7 with the 16-bit freerun

timers 0 and 1 count values and invert the level of the corresponding output compare pin and clear the 16-bit

freerun timer to “0000^H” when a match is detected.

2

• Extended intelligent I/O service (EI OS) can be generated.

• The initial output levels at the output compare pins can be set after the microcontroller boots.

• The output levels from the eight output compare channels are controlled independently. Similarly, interrupt

requests are also generated independently by each channel.

46

MB90520A/520B Series

•

Block diagram

16-bit freerun timer

Counter value output

to input capture

and output compare

Timer data registers

(TCDT0, TCDT1* )

OF

16-bit counter

CLK STOP

CLR

φ

Prescaler

2

Output compare register 0

(Output compare register 4* )

match signal

Timer control

status registers

(TCCS0,TCCS1 *)

Reserved IVF IVFE STOP MODE CLR CLK1 CLK0

Freerun timer

overflow interrupt request

φ

: Machine clock frequency

OF : Overflow

*

: Name for 16-bit freerun timer channel 1

Input capture

16-bit freerun timer 0

Edge detection circuit

IN00

Input capture register 1 (IPCP0)

IN01

IN10

Input capture register 0 (IPCP1)

IN11

2

Input capture

control status register

(ICS01)

ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00

Input capture

interrupt request

47

MB90520A/520B Series

Output compare

interrupt request

Output compare control

status registers

(OSC23, OSC67*)

CMOD OTE1 OTE0 OTD1 OTD0 IOP1 IOP0 IOE1 IOE0

CST1 CST0

2

Timer data registers

(TCDT0, TCDT1* )

2

16-bit freerun timer 0 (1*)

Compare control circuit 3 (7*)

OCP3 (OCP7*)

Output compare register 3 (7*)

OUT3 (OUT7*)

Compare control circuit 2 (6*)

Output control

circuit 3 (7*)

OCP2 (OCP6*)

Output compare register 2 (6*)

OUT2 (OUT6*)

Output control

circuit 2 (6*)

Compare control circuit 1 (5*)

OUT1 (OUT5*)

OCP1 (OCP5*)

Output control

circuit 1 (5*)

Output compare register 1 (5*)

OUT0 (OUT4*)

Output control

circuit 0 (4*)

Compare control circuit 0 (4*)

OCP0 (OCP4*)

Output compare register 0 (4*)

2

Output compare control

2

status registers

(OSC01, OSC45*)

CMOD OTE1 OTE0 OTD1 OTD0 IOP1 IOP0 IOE1 IOE0

CST1 CST0

Output compare

interrupt request

* : Name for output compare unit 1

48

MB90520A/520B Series

7. 8/16-bit Up/Down Counter/Timers 0 and 1

• The 8/16-bit up/down counter/timers can operate in timer mode, up/down count mode, and phase difference

count mode.

• The unit can be used as either a 2-channel × 8-bit or 1-channel × 16-bit up/down counter/timer.

• 8/16-bit up/down counter/timer functions

Operation

Mode

Count Clock

(Count Edge)

Function of

ZIN Pin

Count Mode

Other Functions

2/φ, 4/φ

(φ : Machine clock frequency)

Timer mode

Counts up on detecting speci-

Up/down count fied edge on the AIN pin.

Counter clear

function

mode

Counts down on detecting spec-

ified edge on the BIN pin.

Gate function

Phase

Reads the AIN pin input level on Counter clear

difference count detecting a rising or falling edge

function

8-bit

× 2-channel

mode

on the BIN pin and counts up or

Gate function

(multiply by 2) counts down.

Reads the AIN pin input level on Counter clear

• Compare function

• Reload function

• Compare/reload function

• Compare/reload prohibit

detecting a rising or falling edge

on the BIN pin and counts up or

function

Phase

difference count counts down. Similarly, reads

mode the BIN pin input level on detect-

(multiply by 4) ing a rising or falling edge on the

AIN pin and counts up or counts

down.

Gate function • The direction of the

previous count can be

determined from the up/

down flag.

• Interrupt requests can be

generated on the following

2/φ, 4/φ

Timer mode

(φ : Machine clock frequency)

conditions :

Counts up on detecting speci-

Up/down count fied edge on the AIN pin.

Counter clear

function

1 : Compare match

2 : Underflow or overflow

3 : Count direction

change

mode

Counts down on detecting spec-

ified edge on the BIN pin.

Gate function

Phase

Reads the AIN pin input level on Counter clear

difference count detecting a rising or falling edge

function

16-bit

× 1-channel

mode

on the BIN pin and counts up or

Gate function

(multiply by 2) counts down.

Reads the AIN pin input level on Counter clear

detecting a rising or falling edge

on the BIN pin and counts up or

function

Phase

difference count counts down. Similarly, reads

mode the BIN pin input level on detect-

(multiply by 4) ing a rising or falling edge on the

AIN pin and counts up or counts

down.

Gate function

49

MB90520A/520B Series

• Block diagram

8/16-bit up/down counter/timer 0

Internal data bus

RCR0

Reload compare register 0

Reload

control circuit

Carry/

Borrow

(to

UDCR0

Up/down count register 0

channel

1)

Counter control

register 0 (CCR0: L)

CTUTUCRERLDE UDCC CGSC CGE1CGE0

Compare

control circuit

Counter

clear circuit

ZIN0

Edge/level

detection

circuit

Count clock

Counter status

Machine clock

AIN0

register 0 (CSR0)

Pre-

scaler

Up/down

count

CSTR CITE UDIE CMPFOVFF UDFF UDF1 UDF0

selector

Edge

detection

circuit

BIN0

Interrupt

request

Interrupt

request

M16ECDCF CFIE CLKS CMS1CMS0CES1 CES0

Counter control register 0 (CCR0: H)

M16E

(to channel 1)

50

MB90520A/520B Series

8/16-bit up/down counter/timer 1

Internal data bus

RCR1

Reload compare register 1

Reload

control circuit

UDCR1

Up/down count register 1

Counter control

register 1 (CCR1: L)

CTUTUCRERLDE UDCC CGSC CGE1CGE0

Compare

control circuit

Counter

clear circuit

ZIN1

Edge/level

detection

circuit

Carry/Borrow

(from channel 0)

Count clock

Counter status

register 1 (CSR1)

Machine clock

AIN1

Pre-

scaler

Up/down

count clock

selector

CSTR CITE UDIE CMPFOVFF UDFF UDF1 UDF0

Edge

detection

circuit

BIN1

Interrupt

M16E

request

(from

channel 1)

Interrupt

request

CDCF CFIE CLKS CMS1CMS0CES1 CES0

Counter control register 1 (CCR1: H)

• Pins and interrupt numbers

8/16-bit up/down counter/timer 0

AIN0 pin : P24/AIN0

BIN0 pin : P25/BIN0

ZIN0 pin : P26/ZIN0

Compare match interrupt number : #21 (15^H)

Interrupt number for underflow/overflow interrupt, count direction change interrupt : #2 (16H)

8/16-bit up/down counter/timer 1

AIN1 pin : P50/AIN1

BIN1 pin : P51/BIN1

ZIN1 pin : P52/ZIN1

Compare match interrupt number : #29 (1D^H)

Interrupt number for underflow/overflow interrupt, count direction change interrupt : #3 (1EH)

51

MB90520A/520B Series

8. Extended I/O Serial Interfaces 0 and 1

• The extended I/O serial interfaces are serial I/O interfaces that perform clock-synchronized data transfer.

• The MB90520A/520B series contain two internal extended I/O serial interface channels.

• Either LSB-first or MSB-first data transmission format can be selected.

• Extended I/O serial interface functions

Function

• Transmit and receive can be handled simultaneously. (A setting is required to select

Transmission direction

transmit or receive.)

Transmission mode

• Clock synchronous (data transfer only)

• Internal shift clock mode (Uses the communications prescaler output clock.)

• External shift clock mode (Inputs the clock signal from SCK1 and SCK2.)

Transmission clock

• When using internal shift clock :

Up to 1 MHz operation can be achieved (for a 16 MHz machine clock with the divisor

setting for the communication prescaler set to 8) . Speeds faster than 1 MHz are not

possible.

Transmission speed

• When using an external shift clock :

As a minimum of 5 machine cycles are required, when the machine clock is 16 MHz

the maximum input frequency for the external shift clock is 16 MHz / 5 = 3.2 MHz.

• LSB-first or MSB-first, selectable

• Data transfer only

• Number of data bits = 8 (fixed)

Data transmission

format

Interrupt request

generation

• Interrupt generated when transfer completes

2

EI OS support

• Supports use of the extended intelligent I/O service.

52

MB90520A/520B Series

• Block diagram

Internal data bus

(MSB-first)

D7 to D0

D7 to D0 (LSB-first)

Transmission direction selection

Read

Write

Serial data register

(SDR)

SIN

SOT

Control circuit

Shift clock counter

SCK

Machine clock

Communications

prescaler

SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT

MODE BDS SOE SCOE

Interrupt request

Serial mode control

status register (SMCS)

MD

DIV3 DIV2 DIV1 DIV0

Communications prescaler

register (CDCR)

53

MB90520A/520B Series

9. UART (SCI : Serial Communication Interface)

• The UART (SCI) is a general-purpose serial communications interface for performing synchronous or asyn-

chronous communications with external devices.

• The interface provides bi-directional communications in both clock synchronous and clock asynchronous

modes.

• Includes a master-slave communication function (multi-processor mode) .

• Can generate interrupt requests at receive complete, receive error detected, and transmit complete timings.

2

Also supports EI OS.

• UART (SCI) functions

Function

Data buffer

• Full-duplex double-buffered

• Clock synchronous (with no start/stop bit, no parity bit)

• Clock asynchronous (start-stop sync)

Transmission modes

• Can use dedicated baud rate generator.

• Can use external clock input.

• Can use clock supplied by 16-bit reload timer 0.

• For machine clock speeds of 6 MHz, 8 MHz, 10 MHz, 12 MHz, and 16 MHz :

Available speeds for asynchronous communications : 31250 bps, 9615 bps,

4808 bps, 2404 bps, and 1202 bps

Baud rate

Available speeds for synchronous communications : 1 Mbps, 500 Kbps,

250 Kbps, 125 Kbps, and 62.5 Kbps

• 7 bits (when parity is used for asynchronous normal mode)

• 8 bits (when parity is not used)

Number of data bits

Signal format

• Non return to zero (NRZ) format

• Framing errors (not available in clock synchronous mode)

• Overrun errors

Receive error detection

• Parity errors (not available in clock synchronous mode and multi-processor

mode)

• Receive interrupt (Receive complete or receive error detected)

• Transmit interrupt (Transmission complete)

• Both transmit and receive support the extended intelligent I/O service (EI OS) .

Interrupt requests

2

Master/slave communication

function

• Used for 1 (master) to n (slave) communications. (Can only be used as master)

(multi-processor mode)

2

EI OS support

• Supports the extended intelligent I/O service (EI OS)

54

MB90520A/520B Series

•UART (SCI) operation modes

No. of Data Bits

Parity Bit

None Use

No. of Stop Bits

Operation Mode

7 bits

8 bits

1 bit

2 bits

Normal mode

Mode 0 Asynchronous

Mode 1 Asynchronous

(1-to-1)

Multi-processor mode

(1-to-n)

×

(+1)

Clock synchronous

mode

Clock

Mode 2

×

synchronous

(one-to-one)

: Available

×

: Not available

+1 : Address/data bit used for communication control

Notes :

• The number of data bits must be set to eight for multi-processor and clock synchronous modes.

• A parity bit cannot be used in multi-processor and clock synchronous modes.

• Only data can be transferred in clock synchronous mode. Start and stop bits cannot be added to the trans-

mission data.

55

MB90520A/520B Series

• Block diagram

Control bus

Receive

interrupt

request output

Dedicated baud rate

generator

Transmit

clock

Transmit

interrupt

16-bit

Clock

request output

reload timer 0

selector

Receive clock

Receive

control

circuit

Transmission

control circuit

SCK

Start bit

Transmission

detection circuit

start circuit

Receive bit

counter

Transmit

bit counter

Receive parity

counter

Transmit

parity counter

SOT

Receive

shift register

Transmission

shift register

SIN

Transmission start

Serial input

data register

Serial output

data register

Receive status

evaluation circuit

Receive error

detection signal

for EI²OS

Internal data bus

PEN

P

SBL

CL

PE

ORE

FRE

RDRF

MD

MD1

MD0

CS2

CS1

CS0

Communi-

cation

prescaler

register

Serial

mode

register

Serial

control

register

Serial

status

register

A/D

TDRE

DIV3

DIV2

DIV1

DIV0

REC

RXE

TXE

RIE

TIE

SCKE

SOE

56

MB90520A/520B Series

10. DTP (Data Transfer Peripheral) /External Interrupt Circuit

The DTP/external interrupt function detects interrupt requests and data transfer requests input from external

devices and passes these to the CPU as external interrupt requests. This block can also activate the extended

2

intelligent I/O service (EI OS) .

• DTP/external interrupt functions

External Interrupt

DTP Function

Input pins

• 8 channels (INT0 to INT7)

• Can be set independently for each channel (each pin) in the detection level setup register

(ELVR) .

Interrupt

conditions

• “H” level, “L” level,

“H” level or “L” level input

rising edge, or falling edge input

Interrupt control • Interrupts can be enabled or disabled in the DTP/external interrupt enable register (ENIR) .

Interrupt flag

• The DTP/external interrupt request register (EIRR) stores interrupt requests.

Processing

selection

2

• Set EI OS to be disabled (ICR : ISE = 0)

• Set EI OS to be enabled (ICR : ISE = 1)

Interrupt

execution

• Jumps to interrupt handler routine after

automatic data transfer by EI OS completes.

• Jumps to interrupt handler routine

2

EI OS support • Supports the extended intelligent I/O service (EI OS)

57

MB90520A/520B Series

• Block diagram

Detection level setting register (ELVR)

LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4

LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

Level/Edge

selector

Level/Edge

selector

INT7

INT3

Level/Edge

selector

Level/Edge

selector

INT6

INT2

Level/Edge

selector

Level/Edge

selector

INT5

INT1

Level/Edge

selector

Level/Edge

selector

INT4

INT0

DTP/external interrupt input

detection circuit

DTP/external interrupt request

register (EIRR)

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

Interrupt request

signal

Interrupt request

signal

DTP/external interrupt enable

register (ENIR)

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

58

MB90520A/520B Series

11. Wakeup Interrupts

• The wakeup interrupt function detects wakeup interrupt requests from external devices by detecting “L” levels

input to the wakeup interrupt input pins (WI0 to WI7) and passes these to the CPU for interrupt processing.

• Wakeup interrupts can be used to wakeup the microcontroller from standby mode. (However, wakeup interrupts

cannot be used to recover from hardware standby mode.)

2

• Not supported by the extended intelligent I/O service (EI OS) .

•Wakeup interrupt functions

Function and Control

Input pins

• 8 channels (8 pins : WI0 to WI7)

Interrupt trigger

• “L” level inputs. One interrupt flag is shared by all eight channels.

• Interrupt requests can be enabled or disabled in the wakeup interrupt control

register (EICR) .

Interrupt control

Interrupt flag

• Interrupt requests are stored in the wakeup interrupt flag register (EIFR) .

2

EI OS support

• Not supported by the extended intelligent I/O service (EI OS) .

• Block diagram

Internal data bus

Wakeup interrupt

control register (EICR)

flag register (EIFR)

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

WIF

Interrupt request detection circuit

WI0

WI1

WI2

WI3

WI4

WI5

WI6

WI7

Wakeup

interrupt request

: Undefined

59

MB90520A/520B Series

12. Delayed Interrupt Generation Module

The delayed interrupt generation module is used to generate the task switching interrupt. Generation of this

hardware interrupt can be specified by software.

• Delayed interrupt generation module functions

Function and Control

• Writing “1” to bit R0 of the delayed interrupt request generation/clear register

(DIRR : R0 = 1) generates an interrupt request.

• Writing “0” to bit R0 of the delayed interrupt request generation/clear register

Interrupt trigger

(DIRR : R0 = 0) clears the interrupt request.

Interrupt control

Interrupt flag

• No enable/disable register is provided for this interrupt.

• Set in bit R0 of the delayed interrupt request generation/clear register (DIRR : R0) .

2

EI OS support

• Not supported by the extended intelligent I/O service (EI OS) .

• Block diagram

Internal data bus

R0

S

Interrupt

request latch

Interrupt request

signal

Delayed interrupt request generation/clear

register (DIRR)

R

: Undefined

60

MB90520A/520B Series

13. 8/10-bit A/D Converter

• The 8/10-bit A/D converter uses RC successive approximation to convert analog input voltages to an 8-bit or

10-bit digital value.

• The input signals can be selected from the eight analog input pin channels.

• Either a software trigger, internal timer output, or external pin trigger can be selected to trigger the start of A/

D conversion.

• 8/10-bit A/D converter functions

Function

• Sampling time : Can be selected from 64, 128, or 4096 machine cycles.

The minimum is 4 µs.

A/D conversion

time

• Compare time : Can be selected from 44, 99, or 176 machine cycles.

The minimum is 4.4 µs.

• A/D conversion time = sampling time + conversion time.

The minimum A/D conversion time is 10.2 µs.

Conversion method • RC successive approximation with sample & hold circuit

Resolution

Analog input pins

Interrupts

• 8-bit or 10-bit, selectable

• Up to eight channels can be used. However, two or more channels cannot be used

simultaneously.

• An interrupt request can be generated when A/D conversion completes.

A/D conversion

start trigger

• Selectable : software, internal timer output, or falling edge on input from external pin

2

EI OS support

• Supported by the extended intelligent I/O service (EI OS) .

• 8/10-bit A/D converter conversion modes

Description

Performs A/D conversion sequentially from the start channel to the end channel. A/D con-

conversion mode version halts after conversion completes for the end channel.

Continuous Performs A/D conversion sequentially from the start channel to the end channel. A/D con-

Single-shot

conversion mode version starts again from the start channel after conversion completes for the end channel.

A/D conversion is performed for one channel then halts until the next trigger. After conver-

sion is performed for the end channel, the next conversion is performed for the start chan-

nel, and repeated this operation.

Incremental

conversion mode

61

MB90520A/520B Series

• Block diagram

Interrupt request output

A/D control

status register

(ADCS)

Re-

BUSY INT

PAUS STS1 STS0 STAT

2

MD1 MD0

ANS1ANS0 ANE2 ANE1ANE0

6

INTE

ANS2

served

2

ADTG

TO

Trigger

selector

Decoder

φ

Comparator

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

Sample &

hold circuit

Control circuit

Analog

channel

selector

AVRH, AVRL

AVCC

D/A converter

AVSS

2

A/D data

register

(ADCR)

SELB ST1 ST0 CT1 CT0

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

TO

: Internal timer output

: Undefined

Reserved : Always set to “0”.

: Machine clock

φ

62

MB90520A/520B Series

14. 8-bit D/A Converter

• The 8-bit D/A converter performs R-2R D/A conversion with 8-bit resolution.

• Two D/A converter channels with independent analog outputs are provided.

• D/A converter functions

Function

D/A conversion time

Conversion method

Resolution

•The settling time is 12.5 µs. This is independent of the machine clock.

• R-2R conversion

• 8-bit

Analog output pins

Interrupts

• Two output pins are provided. Both pins can be used simultaneously.

• None

• Set the digital value in the D/A data register (DADR) , then enable D/A output in the

D/A control register (DACR) to start analog output from the D/A output pin.

D/A conversion trigger

2

EI OS support

• Not supported by the extended intelligent I/O service (EI OS) .

• D/A converter theoretical output voltage

D/A Data Register Setting

Theoretical Output Voltage Value

0 / 256 × DVCC voltage ( = 0 V)

1 / 256 × DVCC voltage

•••

00^H

00H

•••

FE^H

FF^H

254 / 256 × DVCC voltage

255 / 256 × DVCC voltage

Note : DV^CCvoltage : D/A converter reference voltage. This must not exceed VCC.

Also, always ensure that DVSS is equipotential to VSS.

63

MB90520A/520B Series

• Block diagram

Internal data bus

D/A data register (DADR)

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0

D/A conversion circuit

DVR

DA7

DA

2R

R

DA6

2R

R

DA5

2R

R

DA4

2R

R

DA3

2R

R

DA2

2R

R

DA1

2R

R

DA0

2R

DV^SS

Standby control (SPL = 1)

D/A control register (DACR)

DAE

Internal data bus

Standby control : Controls stop mode (SPL = 1) , pseudo-clock mode (SPL = 1) , clock mode (SPL = 1) ,

and hardware standby mode.

64

MB90520A/520B Series

15. Clock Timer

• The clock timer is a 15-bit freerun timer that counts up synchronized with the sub-clock.

• Seven different interval time settings are available.

• This timer provides the clock for the sub-clock’s oscillation stabilization delay timer and the watchdog timer.

• This timer always counts the sub-clock, regardless of the settings in the clock selection register (CKSC) .

• Clock timer functions

Function

Interval time

Clock timer size

Clock supply

Source clock

Interrupts

• Selectable from the seven settings shown in the table below.

• 15-bit

• Oscillation stabilization delay timer for sub-clock and watchdog timer

• Sub-oscillation clock divided by four. (SCLK : Sub-clock)

• Interval time overflow

2

EI OS support

• Not supported by the extended intelligent I/O service (EI OS) .

• Clock timer interval times

Sub-Clock Period

Interval Time

2⁹/SCLK (approx. 62.5 ms)

2¹⁰/SCLK (approx. 125.0 ms)

2¹¹/SCLK (approx. 250.0 ms)

2¹²/SCLK (approx. 500.0 ms)

2¹³/SCLK (approx. 1.0 s)

SCLK (122 µs)

2¹⁴/SCLK (approx. 2.0 s)

2¹⁶/SCLK (approx. 4.0 s)

SCLK : Sub-clock frequency

The values enclosed in ( ) are the times for a sub-clock frequency of 8.192 kHz.

Note that the sub-oscillation clock is divided by four to generate the sub-clock frequency. The sub-oscillation clock

operates at 32.768 kHz.

• Clock periods generated by clock timer

Clock Supply

Clock Period

Oscillation stabilization delay timer

for sub-clock

2¹⁴/SCLK (approx. 2.0 s)

2¹⁰/SCLK (approx. 125.0 ms)

2¹³/SCLK (approx. 1.0 s)

2¹⁴/SCLK (approx. 2.0 s)

2¹⁶/SCLK (approx. 4.0 s)

Watchdog timer

SCLK : Sub-clock frequency

The values enclosed in ( ) are the times for a sub-clock frequency of 8.192 kHz.

Note that the sub-oscillation clock is divided by four to generate the sub-clock frequency. The sub-oscillation clock

operates at 32.768 kHz.

65

MB90520A/520B Series

• Block diagram

To

watchdog

timer

Clock timer counter

SCLK

× 2¹× 2²× 2³× 2⁴× 2⁵× 2⁶× 2⁷× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵

OF

Power-on reset

Change to hardware standby mode

Change to stop mode

Counter

clear circuit

To oscillation stabilization

delay timer for sub-clock

Interval

timer selector

Clock timer interrupt

WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0

Clock timer control register (WTC)

OF

: Overflow

SCLK : Sub-clock frequency

66

MB90520A/520B Series

16. LCD Controller/Driver

• The LCD controller/driver can drive an LCD (Liquid Crystal Display) directly.

• The LCD is driven by 4 common outputs and 32 segment outputs.

• The output mode can be set to 1/2, 1/3, or 1/4 duty.

• LCD controller/driver functions

Function

Divider resistor for LCD • Either the internal resistor (approx. 100 kΩ) or an externally connected resistor

drive power

can be selected.

• Max 4 outputs (The corresponding pins cannot be used as I/O ports when using

an LCD.)

Common outputs

Segment outputs

Display data memory

Duty

• Max 32 outputs (of these, 24 pins can be used as I/O ports in blocks of 8 pins.)

• 16 bytes of RAM for internal display are provided

• 1/2, 1/3, or 1/4 can be selected.

Bias

• 1/3 only supported

Drive clock

Interrupts

• Either the oscillation clock (HCLK) or sub-clock (SCLK) can be used.

• None

2

EI OS support

• Not supported by the extended intelligent I/O service (EI OS) .

• Bias, duty, and common output combinations

Bias

1/2 Duty Output Mode

1/3 Duty Output Mode

1/4 Duty Output Mode

COM0 and COM1 outputs

used

COM0 to COM2 outputs

used

COM0 to COM3 outputs

used

1/3 bias

67

MB90520A/520B Series

• Block diagram

Common pin selection register

(LCDCMR)

COM3 COM2 COM1 COM0

V0

V1

V2

V3

4

LCDC control

register 0

(LCR0)

Internal

divider

resistor

CSS LCEN VSEL BK MS1 MS0 FP1 FP0

2

COM0

COM1

COM2

COM3

SEG0

Timing

Prescaler

HCLK

SCLK

Common

driver

controller

Display data memory

32

(16 bytes)

SEG1

SEG2

6

Re-

served

Re-

served

Segment

driver

SEG5 SEG4

SEG3 SEG2 SEG1 SEG0

LCDC control register 1

(LCR1)

SEG29

SEG30

SEG31

Controller

: Undefined bit

HCLK : Main clock

SCLK : Sub-clock

Driver

68

MB90520A/520B Series

17. Communications Prescaler

• Supplies the clock to the dedicated baud rate generator used by the UART (SCI) and extended I/O serial

interfaces.

• By dividing the machine clock to produce the clock supply to the dedicated baud rate generator, the baud rate

can be specified independently of the machine clock speed.

• The communications prescaler can divide the machine clock frequency φ by the following seven ratios to

generate the clock supply to the dedicated baud rate generator and extended I/O serial interface :

φ/2, φ/3, φ/4, φ/5, φ/6, φ/7, φ/8

• Communications prescaler functions

Function

• Dedicated baud rate generator for the UART (SCI) and the extended I/O serial

Clock supply

interface. However, the same clock is supplied to both peripherals.

Divided clock frequency • φ/2, φ/3, φ/4, φ/5, φ/6, φ/7, φ/8 (φ : Machine clock frequency)

Interrupts

• None

• Not supported by the extended intelligent I/O service (EI OS) .

2

EI OS support

Note : As the same output from the communications prescaler is supplied to both the UART (SCI) and the extended

I/Oserialinterface, thetransferclockspeedsettingsmustberevisedifthecommunicationsprescalersettings

are changed.

• Block diagram

MD

DIV3 DIV2 DIV1 DIV0

Extended serial I/O

CDCR

SMCS:SMD2 SMD0 = 000B 100B

Communications prescaler

φ/2 φ/3 φ/4 φ/5

UART

φ

φ/6

φ/7

φ/8

SMR:CS2 CS0 = 000B 100B

: Undefined

: Machine clock frequency

φ

69

MB90520A/520B Series

18. Address Match Detection Function

• If the program address during program execution matches the value set in one of the detection address setting

registers (PADR) , the address match detection function replaces the instruction being executed with the INT9

instruction and executes the interrupt handler program.

• The address match detection function provides a simple method of correcting programming errors (patching)

using RAM or similar.

•Address match detection functions

Function

No. of address settings

Interrupts

• Two channels (two addresses can be set)

• An interrupt is generated when the program address matches the detection

address setting register.

2

EI OS support

• Not supported by the extended intelligent I/O service (EI OS) .

•Block diagram

Address latch

PADR0 (24 bit)

INT9 instruction

(generates an INT9 interrupt)

Detection address setting register

PADR1 (24 bit)

Detection address setting register

PACSR

Reserved Reserved Reserved Reserved ADE1

ADD1

ADE0

ADD0

Address detection control register (PACSR)

Reserved : Always set to “0”.

70

MB90520A/520B Series

19. ROM Mirror Function Selection Module

The ROM mirror function selection module enables ROM data in FF bank to be read by accessing 00 bank.

• ROM mirror function selection module functions

Function

• Data in FFFFFF^Hto FF4000H in FF bank can be read from 00FFFFH to 004000H

Mirror setting address

in 00 bank.

Interrupts

• None

• Not supported by the extended intelligent I/O service (EI OS) .

2

EI OS support

• Relationship between addresses in the ROM mirror function

004000H

00 bank mirror area

00FFFFH

FE0000H

ROM area in MB90523A, 523B, and F523B

FEFFFFH

FF0000H

ROM area in MB90522A and 522B

FF4000H

Mirrored ROM data area

in FF bank

FFFFFFH

• Block diagram

ROM mirror function selection register (ROMM)

MI

Address

Address space

00 bank

FF bank

Data

ROM

71

MB90520A/520B Series

20. Low Power Consumption (Standby) Modes

2

The power consumption of F MC-16LX devices can be reduced by various settings relating to the operating

clock selection.

• Functions of each CPU operation mode

CPUOperation Operation

Explanation

Clock

Mode

The CPU and peripheral functions operate using the oscillation clock (HCLK) mul-

tiplied by the PLL circuit.

Normal run

The peripheral functions only operate using the oscillation clock (HCLK) multiplied

by the PLL circuit.

Sleep

PLL clock

Pseudo- The timebase timer only operates using the oscillation clock (HCLK) multiplied by

clock

the PLL circuit.

Stop

The oscillation clock is stopped and the CPU and peripherals halt operation.

The CPU and peripheral functions operate using the oscillation clock (HCLK) di-

vided by 2.

Normal run

Main clock

The peripheral functions only operate using the oscillation clock (HCLK) divided

by 2.

Sleep

Stop

The oscillation clock is stopped and the CPU and peripherals halt operation.

The CPU and peripheral functions operate using the sub-clock (SCLK) . The os-

cillation clock stops.

Normal run

The peripheral functions only operate using the sub-clock (SCLK) . The oscillation

clock stops.

Sleep

Clock

Stop

Sub-clock

The clock timer only operates using the sub-clock (SCLK) . The oscillation clock

stops.

The oscillation clock and sub-clock are stopped and the CPU and peripherals halt

operation.

CPU

intermittent

operation

The oscillation clock (HCLK) divided by 2 operates intermittently for fixed time in-

tervals.

Normal run

Stop

Hardware

standby

The oscillation clock and sub-clock are stopped and the CPU and peripherals halt

operation.

72

MB90520A/520B Series

21. Clock Monitor Function

The clock monitor function outputs the machine clock divided by a specified amount to the clock monitor pin

(CKOT) .

• Clock monitor functions

Function

Output frequency

Interrupts

• Machine clock divided by 2 to 32 (8 settings available)

• None

2

EI OS support

• Not supported by the extended intelligent I/O service (EI OS) .

• Output frequency of the clock monitor function

When φ = 16 MHz

When φ = 8 MHz

When φ = 4 MHz

FRQ2 - 0

Bits

Machine Clock

Divide Ratio

Period

125 ns

250 ns

500 ns

1.0 µs

2.0 µs

4.0 µs

8.0 µs

16.0 µs

Frequency

8 MHz

Period

250 ns

500 ns

1.0 µs

2.0 µs

4.0 µs

8.0 µs

16.0 µs

32.0 µs

Frequency

Period

500 ns

1.0 µs

2.0 µs

4.0 µs

8.0 µs

16.0 µs

32.0 µs

64.0 µs

Frequency

000^B

001B

010^B

011B

100B

101^B

110B

111^B

φ/2¹

φ/2²

φ/2³

φ/2⁴

φ/2⁵

φ/2⁶

φ/2⁷

φ/2⁸

4 MHz

2 MHz

1 MHz

4 MHz

2 MHz

1 MHz

500 kHz

250 kHz

125 kHz

62.5 kHz

31.25 kHz

15.625 kHz

1 MHz

500 kHz

250 kHz

125 kHz

62.5 kHz

31.25 kHz

500 kHz

250 kHz

125 kHz

62.5 kHz

• Block diagram

Count

clock

selector

φ

Prescaler

CKOT

Output enable

3

Clock output enable

register (CLKR)

CKEN FRQ2 FRQ1 FRQ0

: Undefined

φ

: Machine clock frequency

73

MB90520A/520B Series

22. 1 Mbit Flash Memory

• This section describes the flash memory on the MB90F523B and does not apply to evaluation products and

MASK ROM versions.

• The flash memory is located in banks FE to FF in the CPU memory map.

• Flash memory functions

Function

Memory size

• 1 Mbit (128 KBytes)

Memory configuration

Sector configuration

Sector protect function

• 128 KWords × 8 bits or 64 KWords × 16 bits

• 16 KBytes + 8 KBytes + 8 KBytes + 32 KBytes + 64 KBytes

• Selectable for each sector

• Automatic programming algorithm (Embedded Algorithm^*: Equivalent to

MBM29F400TA)

Programming algorithm

• Compatible with JEDEC standard commands

• Includes an erase pause and restart function

• Data polling and toggle bit write/erase completion

• Erasing by sector available (sectors can be combined in any combination)

Operation commands

No. of write/erase cycles • Min 10,000 guaranteed

• Can be written and erased using a parallel writer

(Minato Electronics model 1890A, Ando Denki AF9704, AF9705, AF9706,

AF9708, and AF9709)

• Can be written and erased using a dedicated serial writer

(YDC AF200, AF210, AF120, and AF110)

Memory write/erase

method

• Can be written and erased by the program

Interrupts

• Write and erase completion interrupts

2

EI OS support

• Not supported by the extended intelligent I/O service (EI OS) .

* : Embedded Algorithm is a trademark of Advanced Micro Devices.

• Sector configuration of flash memory

Flash memory

CPU address

Writer address*

FE0000H

FEFFFH

60000H

6FFFFH

70000H

77FFFH

78000H

79FFFH

7A000H

7BFFFH

7C000H

7FFFFH

SA0 (64 Kbyte)

SA1 (32 Kbyte)

SA2 (8 Kbyte)

SA3 (8 Kbyte)

FF0000H

FF7FFFH

FF8000H

FF9FFFH

FFA000H

FFBFFFH

FFC000H

FEFFFFH

SA4 (16 Kbyte)

* : The writer address is the address to use instead of the CPU address when writing data from a parallel

flash memory writer. Use the writer address when programming or erasing using a general-purpose

parallel writer.

74

MB90520A/520B Series

• Pins used for Fujitsu standard serial on-board programming

Function

Explanation

MD2,MD1,

MD0

Setting MD2 = MD1 = 1, MD0 = 0 selects flash memory serial program-

ming mode.

Mode pins

Flash memory serial programming mode uses the PLL clock with the

multiplier set to 1 as the machine clock. Set the oscillation frequency

used for serial programming to between 3 MHz and 16 MHz.

X0, X1

Oscillation input pin

Write program activation

pins

P00, P01

Input P00 = 0 (“L” level) and P01 = 1 (“H” level)

RST

Reset pin

HST

Hardware standby pin

Serial data input pin

Serial data output pin

Serial clock input pin

Input an “H” level during flash memory serial programming mode.

Uses the UART (SCI) in clock synchronous mode.

SIN0

SOT0

SCK0

Capacitor pin for power supply stabilization. Connect an external capac-

itor of approx. 0.1 µF.

C

C pin

If the user system can provide the programming voltage (5 V ± 10%) ,

do not need to connect to the flash microcontroller writer.

V^CC

Power supply voltage pins

GND pin

VSS

Connect to common GND with the flash microcontroller writer.

• Overall configuration of connection between serial writer and MB90F523A

Fujitsu standard serial on-board programming uses a flash microcontroller writer made by YDC.

Host interface cable (AZ221)

Standard cable (AZ210)

Clock synchronous

serial

Flash microcontroller

RS232C

writer

+

memory card

MB90F523A/B

user system

Can operate standalone

Note : Contact YDC for details of the functions and operation of the flash microcontroller writer (AF220, AF210,

AF120, or AF110) , standard connection cable (AZ210) , and connectors.

75

MB90520A/520B Series

■ Electrical Characteristics\

1. Absolute Maximum Ratings

(VSS = AVSS = 0.0 V)

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

V^CC

VSS − 0.3

VSS + 6.0

V

1

AV^CC

*

Power supply voltage

AVRH,

AVRL

VSS − 0.3

VSS + 6.0

V

2

3

4

5

DVCC

VI

VSS − 0.3

VSS + 6.0

15

V

*

Input voltage

V

Output voltage

VO

V

“L” level maximum output current

“L” level average output current

“L” level total maximum output current

“L” level total average output current

“H” level maximum output current

“H” level average output current

“H” level total maximum output current

“H” level total average output current

IOL

mA

IOLAV

ΣIOL

ΣI^OLAV

IOH

4

100

6

4

5

50

*

−15

IOHAV

ΣIOH

ΣIOHAV

−4

−100

−50

6

*

MB90522A/523A/

F523B

400

mW

Power consumption

Pd

300

+85

mW MB90522B/523B

Operating temperature

Storage temperature

Ta

−40

−55

°C

Tstg

+150

*1 : AV^CC, AVRH, AVRL, and DVCC shall never exceed VCC . AVRH and AVRL shall never exceed AVCC.

Also, AVRL shall never exceed AVRH.

*2 : V^CC≥ AVCC ≥ DVCC ≥ 3.0 V.

*3 : VI and VO shall never exceed VCC + 0.3 V.

*4 : The maximum output current is the peak value for a single pin.

*5 : The average output current is the average current value for a single pin during a 100 ms period.

*6 : The total average current is the average current for all pins during a 100 ms period.

Note : Average output current = operating current × operating ratio

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

76

MB90520A/520B Series

2. Recommended Operating Conditions

(VSS = AVSS = 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

3.0

Max

5.5

Power supply voltage

Smoothing capacitor

Operating temperature

V^CC

C^S

V

0.1

1.0

µF

°C

Ta

−40

+85

Note : Use a ceramic capacitor or other capacitor with equivalent frequency characteristics. The capacitance of

the smoothing capacitor connected to the V^CCpin must be greater than CS.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

C pin diagram

C

C^S

77

MB90520A/520B Series

3. DC Characteristics

(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Typ

Sym-

bol

Parameter

Pin Name

Condition

Unit

Remarks

Min

Max

P20 to P27,

P30 to P37,

P53, P54,

P70 to P77,

P80 to P87,

PA0 to PA7

VCC +

0.3

V^IHS

0.8 V^CC

V

“H” level input

voltage

VCC −

0.3

VCC +

0.3

V^IHMMD0 to MD2

V^CC= 3.0 V to 5.5 V

P20 to P27,

P30 to P37,

P53, P54,

VSS −

0.3

V^ILS

0.2 VCC

P70 to P77,

“L” level input

voltage

P80 to P87,

PA0 to PA7

VSS −

0.3

VSS +

0.3

V^ILMMD0 to MD2

V

All output pins

V^OHotherthanP90

to P97

“H” level

output voltage

V^CC= 4.5 V

IOH = −2.0 mA

VCC −

0.5

“L”leveloutput

voltage

VCC = 4.5 V

IOL = 2.0 mA

V^OL

All output pins

0.4

5

V

All output pins

otherthanP90

to P97

Input leak

current

V^CC= 5.5 V

VSS < VI < VCC

I^IL

− 5

µA

Open-drain

output leak

current

P90 to P97

output pins

I^leak

0.1

5

µA

kΩ

P00 to P07,

P10 to P17

P40 to P47,

MD0, MD1

Pull-up

resistor

RUP

50

100

200

Pull-down

resistor

R^DOWNMD2

kΩ

MB90522A/

523A

40

30

65

60

40

mA

For VCC = 5 V,

internal frequency

= 16 MHz,

Power supply

current^*

ICC

VCC

mA MB90F523B

MB90522B/

523B

normal operation

mA

(Continued)

78

MB90520A/520B Series

(AV^CC= VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Sym-

bol

Parameter

Pin Name

Condition

Unit

Remarks

Min

Typ

Max

25

MB90522A/

523A

20

mA

For VCC = 5 V,

internalfrequency

= 8 MHz,

15

20

mA MB90F523B

MB90522B/

523B

normal operation

15

20

mA

MB90522A/

523A

For V^CC= 5 V,

internalfrequency

= 16 MHz,

A/D operation in

progress

50

45

35

70

65

45

mA

mA MB90F523B

MB90522B/

523B

mA

MB90522A/

523A

For V^CC= 5 V,

internalfrequency

= 8 MHz,

A/D operation in

progress

25

20

30

25

mA

mA MB90F523B

ICC

MB90522B/

523B

mA

MB90522A/

523A

For VCC = 5 V,

internalfrequency

= 16 MHz,

D/A operation in

progress

55

50

40

70

50

mA

mA MB90F523B

MB90522B/

523B

mA

Power supply

current^*

VCC

MB90522A/

523A

For V^CC= 5 V,

internalfrequency

= 8 MHz,

D/A operation in

progress

30

25

20

35

30

25

mA

mA MB90F523B

MB90522B/

523B

mA

Writing or erasing

flash memory

50

8

75

15

20

10

18

mA MB90F523B

MB90522A/

523A

For VCC = 5 V,

internalfrequency

= 16 MHz,

mA

MB90F523B

mA

15

7

sleep mode

/522B/523B

I^CCS

MB90522A/

523A

For V^CC= 5 V,

internalfrequency

= 8 MHz,

mA

MB90F523B

mA

12

sleep mode

/522B/523B

For VCC = 5 V,

internalfrequency

= 8 kHz,

sub-clock mode,

Ta = 25 °C

MB90522A/

mA 523A/522B/

523B

0.1

4

1.0

7

I^CCL

mA MB90F523B

(Continued)

79

MB90520A/520B Series

(Continued)

(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Typ

Sym-

bol

Parameter

Pin Name

Condition

Unit

Remarks

Min

Max

For VCC = 5 V,

internalfrequency

= 8 kHz,

sub-sleep mode,

Ta = 25 °C

ICCLS

30

15

50

µA

Power supply

current^*

For VCC = 5 V,

internalfrequency

= 8 kHz,

VCC

ICCT

30

µA

clock mode,

Ta = 25 °C

Sleep mode,

Ta = 25 °C

I^CCH

5

20

80

µA

Other than

AVCC, AVSS, C,

VCC, and VSS

Input

capacitance

C^IN

10

pF

V0 − V1,

R^LCDV1 − V2,

V2 − V3

LCD divider

resistor

50

100

200

2.5

kΩ

Output

impedance for

COM0 to

COM3

RVCOM COM0 to COM3

V1 to V3 = 5.0 V

Output

impedance for

SEG00 to

SEG31

SEG00 to

R^VSEG

15

kΩ

µA

SEG31

V0 to V3,

COM0 to

ILCDC COM3,

SEG00 to

LCDC leak

current

±5

SEG31

* : Current values are provisional and are subject to change without notice to allow for improvements to the char-

acteristics. The power supply current is measured with an external clock.

80

MB90520A/520B Series

4. AC Characteristics

(1) Reset and Hardware Standby Input Timings

(AV^CC= VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Parameter

Symbol

Condition

Unit

Remarks

Name

Min

4 t^CP

4 tCP

Typ

*

Reset input time

Hardware standby input time

t^RSTL

RST

HST

ns

tHSTL

* : See “ (3) Clock Timings” for more information about t^CP(internal operating clock cycle time) .

tRSTL, tHSTL

RST

HST

0.2 VCC

Measurement conditions for AC ratings

CL is the load capacitance for the pin during testing.

CL

81

MB90520A/520B Series

(2) Power-On Reset

(AV^CC= VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Name

Condi-

tion

Parameter

Symbol

Unit

Remarks

Min

0.05

4

Typ

Power supply rise time

Power supply cutoff time

t^R

VCC

30

ms

*

t^OFF

ms For repeated operation

* : V^CCmust be less than 0.2 V before power-on.

Notes : • The above rating values are for generating a power-on reset.

• WhenHST= “L”, alwaysapplythepowersupplyinaccordancewiththeaboveratingsregardlessofwhether

a power-on reset is required.

• Some internal registers are only initialized by a power-on reset. Always apply the power supply in cordance

with the above ratings if you wish to initialize these registers.

tR

2.7 V

0.2 V

VCC

tOFF

Sudden changes in the power supply voltage may cause a power-on reset.

The recommended practice if you wish to change the power supply voltage while the device is operating is

to raise the voltage smoothly as shown below. Also, changes to the supply voltage should be performed when

the PLL clock is not in use. The PLL clock may be used, however, if the rate of voltage change is 1 V/s or less.

VCC

Recommended rate of voltage

rise is 50 mV/ms or less.

3.0 V

Maintain RAM data

VSS

82

MB90520A/520B Series

(3) Clock Timings

(AV^CC= VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Sym-

bol

Name

Condi-

tion

Parameter

Clock frequency

Clock cycle time

Unit

Remarks

Min

Typ

32.768

30.5

Max

F^C

FCL

X0, X1

X0A, X1A

X0, X1

3

16

MHz

kHz

ns

t^HCYL

62.5

10

333

t^LCYLX0A, X1A

µs

P^WH

X0

ns

µs

ns

PWL

Recommended duty

ratio = 30% to 70%

Input clock pulse width

P^WLH

X0A

PWLL

15.2

Input clock rise/fall

time

t^CR

X0

tCF

When using an

external clock

5

f^CP

fLCP

tCP

1.5

16

MHz When using main clock

kHz When using sub-clock

ns When using main clock

µs When using sub-clock

Internal operating

clock frequency

8.192

122.1

62.5

666

Internal operating

clock cycle time

t^LCP

X0 and X1 clock timing

tHCYL

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

X0

PWH

PWL

tCR

tCF

X0A and X1A clock timing

tLCYL

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

X0A

PWLH

PWLL

tCR

tCF

83

MB90520A/520B Series

PLL guaranteed operation range

Relationship between internal operating clock frequency and power supply voltage

Guaranteed operation range for MB90V520A

5.5

4.5

PLL guaranteed

operation range

A/D, D/A guaranteed

voltage range

3.0

2.7

Guaranteed operation

range for MB90522A, 523A,

MB90522B, 523B, and F523B

1.5

3

8

10

16

Internal Clock fCP (MHz)

Relationship between oscillation frequency and internal operating clock frequency

×4 ×3

×2

×1

16

12

9

8

Divided by 2

6

4

3

2

3

4

6

8

12

16

Source Oscillation Clock fCP (MHz)

The AC ratings are measured at the following reference voltages.

Input signal waveform

Output signal waveform

Hysteresis input pin

Output pin

0.8 VCC

2.4 V

0.8 V

0.2 VCC

Pins other than hysteresis input or MD input pins

0.7 VCC

0.3 VCC

84

MB90520A/520B Series

(4) Clock Output Timings

(AV^CC= VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Name

Parameter

Symbol

Condition

Unit

Remarks

Min

62.5

20

Typ

Cycle time

CLK ↑ → CLK ↓

t^CYC

ns

CLK

VCC = 5.0 V ± 10%

t^CHCL

tCYC

tCHCL

2.4 V

CLK

0.8 V

85

MB90520A/520B Series

(5) UART (SCI) Timings

(AV^CC= VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Sym-

bol

Re-

marks

Parameter

Pin Name

Condition

Unit

Min

Typ

*

Serial clock cycle time

t^SCYC

SCK0 to SCK2

8 t^CP

ns

SCK0 to SCK2

SOT0 to SOT2

SCK ↓ → SOT delay time

tSLOV

−80

100

60

80

Internal shift clock

mode, output pin

load is

SCK0 to SCK2

SIN0 to SIN2

Valid SIN → SCK ↑

t^IVSH

ns

C^L= 80 pF + 1 TTL

SCK0 to SCK2

SIN0 to SIN2

SCK ↑ → valid SIN hold time t^SHIX

*

Serial clock “H” pulse width

Serial clock “L” pulse width

tSHSL

SCK0 to SCK2

4 t^CP

ns

t^SLSH

4 tCP

SCK0 to SCK2 External shift clock

SOT0 to SOT2 mode, output pin

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SLOV

t^IVSH

150

ns

load is

C^L= 80 pF + 1 TTL

SCK0 to SCK2

SIN0 to SIN2

60

SCK0 to SCK2

SIN0 to SIN2

SCK ↑ → valid SIN hold time t^SHIX

* : See “ (3) Clock Timings” for more information about t^CP(internal operating clock cycle time) .

Notes : • These are the AC ratings for CLK synchronous mode.

• C^Lis the load capacitor connected to the pin for testing.

86

MB90520A/520B Series

Internal shift clock mode

SCK0 to SCK2

tSCYC

2.4 V

0.8 V

tSLOV

2.4 V

0.8 V

SOT0 to SOT2

SIN0 to SIN2

tSHIX

tIVSH

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

External shift clock mode

tSLSH

tSHSL

SCK0 to SCK2

SOT0 to SOT2

SIN0 to SIN2

0.8 VCC

0.2 VCC

tSLOV

0.2 VCC

2.4 V

0.8 V

tSHIX

tIVSH

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

87

MB90520A/520B Series

(6) Timer Input Timings

(AV^CC= VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin Name

Condition

Unit

Remarks

Min

Typ

IC00/01,

IC10/11

TI0, TI1

t^TIWH

tTIWL

*

Input pulse width

4 tCP

ns

* : See “ (3) Clock Timings” for more information about t^CP(internal operating clock cycle time) .

0.8 VCC

0.2 VCC

IC00/01

IC10/11

TI0, TI1

0.2 VCC

tTIWL

tTIWH

(7) Timer Output Timings

Parameter

(AV^CC= VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Symbol

Pin Name

Condition

Unit

Remarks

Min

Typ

OUT0 to OUT7

PG00/01

CLK ↑ → T^OUTchange time

tTO

30

ns

PG10/11

TO0, TO1

2.4 V

CLK

tTO

2.4 V

0.8 V

TOUT

(TOUT : OUT0 to OUT7, PG00/01, PG10/11, TO0, TO1)

88

MB90520A/520B Series

5. Electrical Characteristics for the A/D Converter

(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, 3.0 V ≤ AVRH − AVRL, Ta = −40 °C to +85 °C)

Value

Sym-

Parameter

Resolution

Pin Name

Unit

Remarks

bol

Min

Typ

Max

8/10

bit

Total error

±5.0

±2.5

±1.9

LSB

Linearity error

Differential linearity error

AVSS

+ 4.5 LSB

Zero transition voltage

V^OT

AN0 to AN7

mV

− 3.5 LSB + 0.5 LSB

AVRH AVRH

− 6.5 LSB − 1.5 LSB

AVRH

+ 1.5 LSB

Full-scale transition voltage

VFST

At machine

A/D conversion time

Compare time

163 tcp

ns clock = 16

MHz

At machine

ns clock = 16

MHz

99 tcp

Analog port input current

Analog input voltage

I^AIN

AN0 to AN7

AVRH

10

AVRH

µA

V

VAIN

AVRL

AVRL + 3.0

AV^CC

V

Reference voltage

AVRL

0

AVRH − 3.0

V

I^A

I^AH

IR

AVCC

5

mA

Power supply current

AVCC

5

µA

*

AVRH

400

Reference voltage supply

current

IRH

AVRH

5

4

µA

Variation between channels

AN0 to AN7

LSB

* : Current when 8/10-bit A/D converter not used and CPU in stop mode (V^CC= AVCC = AVRH = 5.0 V)

Note : See “ (3) Clock Timings” in “4. AC Ratings” for more information about tCP (internal operating clock cycle time) .

89

MB90520A/520B Series

6. A/D Converter Glossary

Resolution

: The change in analog voltage that can be recognized by the A/D converter.

Linearity error

: The deviation between the actual conversion characteristics and the line linking the

zero transition point (“00 0000 0000^B” ←→ “00 0000 0001B”) and the full scale transi-

tion point (“11 1111 1110B” ←→ “11 1111 1111B”) .

Differential linearity error : The variation from the ideal input voltage required to change the output code by 1 LSB.

Total error

:

The total error is the difference between the actual value and the theoretical value.

This includes the zero-transition error, full-scale transition error, and linearity error.

Total Error

3FFH

0.5 LSB

3FEH

3FDH

Actual conversion

characteristic

{1 LSB × (N − 1) + 0.5 LSB}

004H

003H

002H

001H

VNT

(Measured value)

Actual conversion

characteristic

Theoretical characteristic

0.5 LSB

Analog Input

AVRL

AVRH

AVRH − AVRL

1 LSB = (Theoretical value)

[V]

1024^*

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

Total error for digital output N =

[LSB]

1 LSB

V^OT(Theoretical value) = AVRL + 0.5 LSB [V]

V^FST(Theoretical value) = AVRH − 1.5 LSB [V]

VNT : Voltage at which digital output changes from (N − 1) to N

* : For 10-bit resolution, this value is 1024 (2¹⁰) . For 8-bit resolution, this value is 256 (2⁸) .

(Continued)

90

MB90520A/520B Series

(Continued)

Linearity Error

Differential Linearity Error

Theoretical characteristic

3FFH

Actual conversion characteristic

{1 LSB × (N − 1)

+ VOT}

3FEH

3FDH

N + 1

Actual conversion

characteristic

VFST

(Measured

value)

N

N − 1

N − 2

VNT

(Measured value)

004H

003H

002H

001H

V (N + 1)T

(Measured value)

Actual conversion

VNT

characteristic

(Measured value)

Actual conversion

characteristic

Theoretical characteristic

VOT (Measured value)

Analog Input

AVRL

AVRH

AVRL

AVRH

Analog Input

VNT − {1 LSB × (N − 1) + VOT}

[LSB]

Linearity error for digital output N =

1 LSB

V (N + 1) T − VNT

Differential linearity error for digital output N =

− 1 LSB [LSB]

1 LSB

VFST − VOT

1 LSB =

[V]

1022^*

VOT : Voltage at which digital output changes from “000H” to “001H”

VFST : Voltage at which digital output changes from “3FEH” to “3FFH”

* : For 10-bit resolution, this value is 1022 (2¹⁰− 2) . For 8-bit resolution, this value is 254 (2⁸− 2) .

91

MB90520A/520B Series

7. Notes for A/D Conversion

The recommended external circuit impedance of analog inputs for MB90V520 is approximately 5 kΩ or less,

that for MB90F523B is approximately 15.5 kΩ or less, and that for MB90522A/523A/522B/523B is approximately

10 kΩ or less.

If using an external capacitor, the capacitance should be several thousand times the level of the chip’s internal

capacitor to allow for the partial potential between the external and internal capacitance.

If the impedance of the external circuit is too high, the analog voltage sampling interval may be too short. (for

sampling time = 4 µs, machine clock frequency = 16 MHz) .

• Block diagram of analog input circuit model

RON

C

Analog input

Comparator

MB90522A/523A/522B/523B

RON = 2.2 kΩ approx.

C = 45 pF approx.

MB90F523B

RON = 2.6 kΩ approx.

C = 28 pF approx.

Note : The values listed are an indication only.

• Error

The relative error increases as |AVRH − AVRL| becomes smaller.

92

MB90520A/520B Series

8. Electrical Characteristics for the D/A Converter

(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Parameter

Resolution

Symbol

Unit

Remarks

Name

Min

Typ

Max

8

bit

LSB

%

Differential linearity error

Absolute accuracy

Linearity error

±0.9

±1.2

±1.5

LSB

For load capacitance

= 20 pF

Conversion time

10

20

µs

Analog reference voltage

DV^CC

VSS + 3.0

AVCC

300

10

V

I^DVR

120

20

µA

Current consumption for

reference voltage

DVCC

IDVRS

µA Stop mode

kΩ

Analog output impedance

9. Flash Memory Program/Erase

Value

Typ

Parameter

Condition

Unit

Remarks

Min

Max

Excludes 00H programming

prior erasure

Sector erase time

Chip erase time

1

5

15

s

Ta = + 25 °C

V^CC= 5.0 V

Excludes 00H programming

prior erasure

Word (16-bit width)

programming time

16

3,600

µs

Excludes system-level overhead

Program/Erase cycle

Data hold time

10,000

100 K

cycle

h

93

MB90520A/520B Series

■ EXAMPLE CHARACTERISTICS

Power supply current (MB90523A)

ICC − VCC

I^CCS− VCC

Ta = +25 °C, External clock input

60

20

15

10

5

f = 16 MHz

50

f = 12 MHz

f = 10 MHz

f = 8 MHz

f = 12 MHz

40

f = 10 MHz

30

f = 8 MHz

f = 4 MHz

f = 2 MHz

20

f = 4 MHz

10

f = 2 MHz

0

2

3

4

5

6

VCC (V)

0

2

3

4

5

6

VCC (V)

I^CCL− VCC

ICCLS − VCC

Ta = +25 °C, External clock input

70

20

60

50

40

30

20

10

0

15

10

5

f = 8 kHz

0

2

3

4

5

6

VCC (V)

2

3

5

6

4

VCC (V)

(Continued)

94

MB90520A/520B Series

(Continued)

ICCT − VCC

Ta = +25 °C, External clock input

10

8

6

4

f = 8 kHz

2

0

2

3

4

5

6

VCC (V)

Example MB90523A V^OH− IOH Characteristics

Ta = +25 °C, VCC = 4.5 V

Example MB90523A VOL − IOL Characteristics

Ta = +25 °C, VCC = 4.5 V

1000

900

800

700

600

500

400

300

200

100

0

900

800

700

600

500

400

300

200

100

0

1

2

3

4

5

6

7

8

9

10 11 12

0

1

2

3

4

5

6

7

8

9

10 11 12

IOH (mA)

IOL (mA)

95

MB90520A/520B Series

■ ORDERING INFORMATION

Part No.

Package

Remarks

MB90522APFF

MB90523APFF

MB90522BPFF

MB90F523BPFF

120-pin, Plastic LQFP

(FPT-120P-M05)

MB90522APFV

MB90523APFV

MB90522BPFV

MB90F523BPFV

120-pin, Plastic QFP

(FPT-120P-M13)

96

MB90520A/520B Series

■ PACKAGE DIMENSIONS

120-pin Plastic LQFP

(FPT-120P-M05)

* : Pins width and pins thickness include plating thickness.

16.00±0.20(.630±.008)SQ

14.00±0.10(.551±.004)SQ

90

61

91

60

0.08(.003)

Details of "A" part

1.50 ⁺^–0⁰^.^.¹²⁰⁰

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

(Mounting height)

INDEX

120

31

"A"

0~8°

1

30

LEAD No.

0.10±0.10

(.004±.004)

(Stand off)

0.16±0.03

(.006±.001)

0.145±0.055

(.006±.002)

0.50±0.20

(.020±.008)

M

0.07(.003)

0.40(.016)

0.45/0.75

(.018/.030)

0.25(.010)

C

1998 FUJITSU LIMITED F120006S-3C-4

Dimensions in mm (inches)

(Continued)

97

MB90520A/520B Series

(Continued)

120-pin Plastic QFP

(FPT-120P-M13)

* : Pins width and pins thickness include plating thickness.

22.60±0.20(.890±.008)SQ

20.00±0.10(.787±.004)SQ

0.145±0.055

(.006±.002)

90

61

91

60

0.08(.003)

Details of "A" part

3.53 –⁺0⁰.^.2³0²

(Mouting height)

.139 –⁺.^.0⁰0¹8³

0.20 –⁺0⁰.^.1¹5⁰

.008 –⁺.^.0⁰0⁰6⁴

(Stand off)

0°~8°

INDEX

120

31

0.25(.010)

0.50±0.20

(.020±.008)

"A"

0.60±0.15

(.024±.006)

1

30

LEAD No.

0.50(.020)

0.22±0.05

(.009±.002)

M

0.08(.003)

C

2000 FUJITSU LIMITED F120013S-c-3-5

Dimensions in mm (inches)

98

MB90520A/520B Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0203

FUJITSU LIMITED Printed in Japan


型号：	MB90523APFV
厂家：	FUJITSU
描述：	16-bit Proprietary Microcontroller 16位微控制器专有微控制器和处理器外围集成电路时钟
文件：	总99页 (文件大小：929K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90523APFV [FUJITSU]

相关型号：

MB90523B

MB90523BPFV

MB90523BPFV

MB90523BPMC1

MB90523BPMC1

MB90523BPMC1

MB90523PFF

MB90523PFF-G

MB90523PFV

MB90523PFV-G

MB90540

MB90540G