MB90634A_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13601-5E

16-bit Proprietary Microcontroller

CMOS

F²MC-16L MB90630A Series

MB90632A/634A/P634A

■ DESCRIPTION

The MB90630A series are 16-bit microcontrollers designed for high speed real-time processing in consumer

product applications such as controlling video cameras, VCRs, or copiers. The series uses the F²MC*-16L CPU.

The chips incorporate an eight channels 10-bit A/D converter, two channels 8-bit D/A converter, UART two

channels, two channels serial interface, 8/16-bit up/down counter, 16-bit I/O timer (two channels input capture,

four channels output compare, and one channel 16-bit free-run timer).

*: F²MC stands for FUJITSU Flexible Microcontroller.

■ FEATURES

F²MC-16L CPU

• Minimum execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication), maximum multiplier = 4

• Instruction set optimized for controller applications

Object code compatibility with F²MC-16(H)

Wide range of data types (bit, byte, word, and long word)

Improved instruction cycles provide increased speed

Additional addressing modes: 23 modes

High code efficiency

Access mothods (bank access, linear pointer)

(Continued)

■ PACKAGE

100-pin Plastic LQFP

100-pin Plastic QFP

(FPT-100P-M05)

(FPT-100P-M06)

MB90630A Series

(Continued)

High precision operations are enhanced by use of a 32-bit accumulator

Extended intelligent I/O service (access area extended to 64 KB)

Maximum memory space: 16 MB

• Enhanced high level language (C) and multitasking support insturctions

Use of a system stack pointer

Enhanced pointer indirect instructions

Barrel shift instructions

• Improved execution speed: Four byte instruction queue

• Powerful interrupt function

• Automatic data transfer function that does not use insturction (IIOS)

Internal peripherals

• ROM:

32 Kbytes (MB90632A)

64 Kbytes (MB90634A)

One-time PROM: 64 Kbytes (MB90P634A)

• RAM:

1 Kbytes (MB90632A)

2 Kbytes (MB90634A)

3 Kbytes (MB90P634A)

• General-purpose ports: 82 ports max.

• 10-bit A/D converter (RC successive approximation): eight channels (10-bit resolution, conversion time =

5.2 µs at 4 MHz with a × 4 multiplier)

• 8-bit D/A converter two channels (8-bit resolution)

• UART (can also be used as a serial port) two channels

• I/O expansion serial interface two channels

• 8/16-bit PPG (can be set to either 8-bit × two channels or 16-bit × one channel) one channel

• 16-bit I/O timer one channel

(two channels input capture, four channels output compare, and one channel free-run timer)

• Clock output generator

• Timebase counter/watchdog timer (18-bit)

• Low-power consumption modes

• The device types are classified by the initial value of the oscillation stabilization delay time.

Oscillation stabilization delay time initial value = 2.05 ms: MB90630A series (MB90632A/634A/P634A)

• Package: LQFP-100 (QFP-100 planned)

• CMOS technology

2

MB90630A Series

■ PRODUCT LINEUP

Part number

MB90P634A

MB90632A

MB90634A

Parameter

Classification

ROM size

OTPROM

64 Kbyte

3 Kbyte

Mask ROM

64 Kbyte

2 Kbyte

32 Kbyte

1 Kbyte

: 340

RAM size

CPU functions

Number of instructions

Instruction bit length

Instruction length

: 8/16 bits

: 1/7 bytes

Data bit length

Minimum execution time

Interrupt processing time

: 1/4/8/16/32 bits

: 62.5 ns/4 MHz (PLL multiplier = 4)

: 1000 ns/16 MHz (minimum)

Ports

I/O ports (CMOS/TTL)

Input pull-up resistors available

Can be set as open-drain outputs : 8 ports

: 82 ports

: 24 ports

(

)

Package

FPT-100P-M05

FPT-100P-M06

A/D converter

D/A converter

10-bit resolution, 5.2 µs conversion time (at 4 MHz with a ×4 multiplier)

RC successive approximation, 8 channels (multiplexed inputs)

8-bit resolution

R-2R type, 2 channels (independent)

UART

Full-duplex, double-buffered (8-bit), internal baud rate correction circuit that uses the

operating clock

NRZ-type transfer, supports MIDI frequencies, 2 channels

Serial interface

8/16-bit PPG

8-bit data register. LSB-first or MSB-first operation can be selected.

The transfer shift clock can be input externally.

The internal shift clock includes a built-in operating clock correction circuit. 1 channel

Can operate as two independent channels in 8-bit mode.

Can also be used as a single-channel 16-bit PPG. 1 channel

8/16-bit up/down

counter

6 event inputs. Can operate as two independent 8-bit up/down counter channels. Can

also be used as a single-channel 16-bit counter. Includes reload and compare functions.

1 channel

16-bit I/O timer

Timer functions

Consists of 2 × input capture, 4 × output compare, and 1 × free-run timer. 1 channel

Timebase timer/watchdog timer (18-bit)

Low-power

consumption modes

Includes sleep, stop, and hardware standby functions

Oscillation

stabilization delay

time

The initial value of the oscillation stabilization delay time is 64 ms.

The oscillation stabilization delay time can also be set to 0 ms, 2.05 ms, 8.19 ms, or

64 ms (for an crystal oscillator).

The MB90630A series are for FAR oscillators.

External interrupt

8 inputs

External interrupt mode

(Interrupts can be generated from four different types of request signal)

PLL function

Other

Selectable multiplier: 1/2/3/4

(Set a multiplier that does not exceed the assured operation frequency range.)

VPP is shared with the MD2 pin

(for EPROM programming)

—

3

MB90630A Series

■ PIN ASSIGNMENT

(TOP VIEW)

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

RST

P22/A18

P23/A19

P24/A20

P25/A21

P26/A22

P27/A23

P30/ALE

P31/RD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

PA1/OUT1

PA0/OUT0

P97/IN1

P96/IN0

P95/ZIN1

P94/BIN1

P93/AIN1/IRQ7

P92/ZIN0

P91/BIN0

P90/AIN0/IRQ6

P67/PPG11

P66/PPG10

P65/CKOT

P64/PPG01

P63/PPG00

P62/SCK2

P61/SOT2

P60/SIN2

P87

V^SS

P32/WRL

P33/WRH

P34/HRQ

P35/HAK

P36/RDY

P37/CLK

P40/SIN0

P41/SOT0

P42/SCK0

P43/SIN1

P44/SOT1

V^CC

P86

P85/IRQ5

P84/IRQ4

P83/IRQ3

P82/IRQ2

P45/SCK1

P46/ADTG

P47

P70/SIN3

(FPT-100P-M05)

4

MB90630A Series

■ PIN DESCRIPTION

Pin no.

Circuit

type

Pin name

Function

LQFP*¹

80

QFP*²

82

X0

A

C

B

D

Oscillator pin

81

83

X1

50

52

HST

RST

Hardware standby input pin

Reset input pin

75

77

83 to 90 85 to 92 P00 to P07

General-purpose I/O ports

(STBC) Pull-up resistors can be set (RD07 to RD00 = “1”) using the

pull-up resistor setting register (RDR0). The setting does not

apply for ports set as outputs (D07 to D00 = “1”: invalid at the

output setting).

AD00 to AD07

In external bus mode, the pins function as the lower data I/O or

lower address outputs (AD00 to AD07).

91 to 98 93 to 100 P10 to P17

D

General-purpose I/O ports

(STBC) Pull-up resistors can be set (RD17 to RD10 = “1”) using the

pull-up resistor setting register (RDR1). The setting does not

apply for ports set as outputs (D17 to D10 = “1”: invalid at the

output setting).

AD08 to AD15

In 16-bit external bus mode, the pins function as the upper data

I/O or middle address outputs (AD08 to AD15).

99, 100,

1 to 6

1 to 8

P20 to P27

A16 to A23

P30

H

General-purpose I/O ports

(STBC) In external bus mode, pins for which the corresponding bit in

the HACR register is “0” function as the P20 to P27 pins.

In external bus mode, pins for which the corresponding bit in

the HACR register is “1” function as the upper address output

pins (A16 to A23).

7

8

9

H

General-purpose I/O port

(STBC) Functions as the ALE pin in external bus mode.

ALE

P31

Functions as the address latch enable signal.

10

12

H

General-purpose I/O port

(STBC) Functions as the RD pin in external bus mode.

RD

Functions as the read strobe output (RD).

10

P32

H

General-purpose I/O port

(STBC) Functions as the WR pin in external bus mode if the WRE bit in

the EPCR register is “1”.

WRL

P33

Functions as the lower data write strobe output (WRL).

11

13

H

General-purpose I/O port

(STBC) Functions as the WRH pin in 16-bit external bus mode if the

WRE bit in the EPCR register is “1”.

WRH

Functions as the upper data write strobe output (WRH).

(Continued)

STBC: Incorporates standby control

*1: LQFP (FPT-100P-M05)

*2: QFP (FPT-100P-M06)

6

MB90630A Series

Pin no.

Circuit

type

Pin name

P34

Function

LQFP*¹

QFP*²

12

13

14

15

16

14

H

General-purpose I/O port

(STBC) Functions as the HRQ pin in external bus mode if the HDE bit

in the EPCR register is “1”.

HRQ

P35

Functions as the hold request input pin (HRQ).

15

16

17

18

H

General-purpose I/O port

(STBC) Functions as the HAK pin in external bus mode if the HDE bit in

the EPCR register is “1”.

HAK

P36

Functions as the hold acknowledge output (HAK) pin.

H

General-purpose I/O port

(STBC) Functions as the RDY pin in external bus mode if the RYE bit in

the EPCR register is “1”.

RDY

P37

Functions as the external ready input (RDY) pin.

H

General-purpose I/O port

(STBC) Functions as the CLK pin in external bus mode if the CKE bit in

the EPCR register is “1”.

CLK

P40

Functions as the machine cycle clock output (CLK) pin.

G

General-purpose I/O port

(STBC) When UART0 is operating, the data at the pin is used as the

serial input (SIN0).

Can be set as an open-drain output port (OD40 = “1”) by the

open-drain control register (ODR4). The setting does not apply

for ports set as inputs (D40 = “0”: invalid at the input setting).

SIN0

P41

Functions as the UART0 serial input (SIN0).

17

18

19

20

F

General-purpose I/O port

(STBC) Functions as the SOT0 pin if the SOE bit in the UMC register is

“1”.

Can be set as an open-drain output port (OD41 = “1”) by the

open-drain control register (ODR4). The setting does not apply

for ports set as inputs (D41 = “0”: invalid at the input setting).

SOT0

P42

Functions as the UART0 serial data output pin (SOT0).

G

General-purpose I/O port

(STBC) When UART0 is operating in external shift clock mode, the

data at the pin is used as the clock input (SCK0). Also,

functions as the SCK0 pin if the SOE bit in the UMC register is

“1”.

Can be set as an open-drain output port (OD42 = “1”) by the

open-drain control register (ODR4). The setting does not apply

for ports set as inputs (D42 = “0”: invalid at the input setting).

SCK0

Functions as the UART0 serial clock I/O pin (SCK0).

(Continued)

STBC: Incorporates standby control

*1: LQFP (FPT-100P-M05)

*2: QFP (FPT-100P-M06)

7

MB90630A Series

Pin no.

Circuit

type

Pin name

Function

LQFP*¹

QFP*²

19

21

P43

G

General-purpose I/O port

(STBC) When I/O expansion serial is operating, the data at the pin is

used as the serial input (SIN1).

Can be set as an open-drain output port (OD43 = “1”) by the

open-drain control register (ODR4). The setting does not apply

for ports set as inputs (D43 = “0”: invalid at the input setting).

SIN1

P44

Functions as the serial input for I/O expansion serial data.

20

22

24

F

General-purpose I/O port

(STBC) Functions as the SOT1 pin if the SOE bit in the UMC register is

“1”.

Can be set as an open-drain output port (OD44 = “1”) by the

open-drain control register (ODR4). The setting does not apply

for ports set as inputs (D44 = “0”: invalid at the input setting).

SOT1

P45

Functions as the output pin (SOT1) for I/O expansion serial

data.

G

General-purpose I/O port

(STBC) When I/O expansion serial is operating in external shift clock

mode, the data at the pin is used as the clock input (SCK1).

Also, functions as the SCK1 pin if the SOE bit in the UMC

register is “1”.

Can be set as an open-drain output port (OD45 = “1”) by the

open-drain control register (ODR4). The setting does not apply

for ports set as inputs (D45 = “0”: invalid at the input setting).

SCK1

P46

Functions as the I/O expansion serial clock I/O pin (SCK1).

23

24

25

26

F

General-purpose I/O port

(STBC) Can be set as an open-drain output port (OD46 = “1”) by the

open-drain control register (ODR4). The setting does not apply

for ports set as inputs (D46 = “0”: invalid at the input setting).

ADTG

P47

Functions as the external trigger input pin for the A/D

converter.

F

General-purpose I/O port

(STBC) Can be set as an open-drain output port (OD47 = “1”) by the

open-drain control register (ODR4). The setting does not apply

for ports set as inputs (D47 = “0”: invalid at the input setting).

36 to 39, 38 to 41, P50 to P57

K

General-purpose I/O ports

41 to 44 43 to 46

(STBC)

AN0 to AN7

The pins are used as analog inputs (AN0 to AN7) when the A/D

converter is operating.

25

26

27

28

29

P70

I

General-purpose I/O port

(STBC)

SIN3

P71

Functions as the UART1 serial input (SIN3).

General-purpose I/O port

H

(STBC)

SOT3

P72

Functions as the UART1 serial data output pin (SOT3).

General-purpose I/O port

I

(STBC)

SCK3

Functions as the UART1 serial clock I/O pin (SCK0).

(Continued)

STBC: Incorporates standby control

*1: LQFP (FPT-100P-M05)

*2: QFP (FPT-100P-M06)

8

MB90630A Series

Pin no.

Circuit

type

Pin name

P73

Function

LQFP*¹

QFP*²

30

32

L

General-purpose I/O port

(STBC) Functions as a D/A output pin when DAE0 = “1” in the D/A

control register (DACR).

DAO0

P74

Functions as D/A output 0 when the D/A converter is operating.

31

33

L

General-purpose I/O port

(STBC) Functions as a D/A output pin when DAE1 = “1” in the D/A

control register (DACR).

DAO1

P80

Functions as D/A output 1 when the D/A converter is operating.

45

46

51

52

53

54

47

48

53

54

55

56

General-purpose I/O port

I

IRQ0

P81

Functions as external interrupt request I/O 0.

I

General-purpose I/O port

IRQ1

P82

Functions as external interrupt request I/O 1.

General-purpose I/O port

IRQ2

P83

Functions as external interrupt request I/O 2.

General-purpose I/O port

I

IRQ3

P84

Functions as external interrupt request I/O 3.

General-purpose I/O port

I

IRQ4

P85

Functions as external interrupt request I/O 4.

General-purpose I/O port

I

IRQ5

P86

Functions as external interrupt request I/O 5.

General-purpose I/O port

55

56

57

58

59

H

(STBC) This applies in all cases.

P87

P60

H

General-purpose I/O port

(STBC) This applies in all cases.

E

General-purpose I/O port

(STBC) A pull-up resistor can be set (RD60 = “1”) using the pull-up

resistor setting register (RDR6). The setting does not apply for

ports set as outputs (D60 = “1”: invalid at the output setting).

SIN2

P61

Functions as a data input pin (SIN2) for I/O expansion serial.

58

60

D

General-purpose I/O port

(STBC) Functions as the SOT2 pin if the SOE bit in the UMC register is

“1”.

A pull-up resistor can be set (RD61 = “1”) using the pull-up

resistor setting register (RDR6). The setting does not apply for

ports set as outputs (D61 = “1”: invalid at the output setting).

SOT2

Functions as an output pin (SOT2) for I/O expansion serial

data.

(Continued)

STBC: Incorporates standby control

*1: LQFP (FPT-100P-M05)

*2: QFP (FPT-100P-M06)

9

MB90630A Series

Pin no.

Circuit

type

Pin name

Function

LQFP*¹

QFP*²

59

61

P62

E

General-purpose I/O port

(STBC) When I/O expansion serial is operating in external shift clock

mode, the data at the pin is used as the clock input (SCK2).

Also, functions as the SCK2 pin if the SOE bit in the UMC

register is “1”. A pull-up resistor can be set (RD62 = “1”) using

the pull-up resistor setting register (RDR6). The setting does

not apply for ports set as outputs (D62 = “1”: invalid at the

output setting).

SCK2

P63

Functions as the I/O expansion serial clock I/O pin (SCK2).

60

61

62

63

64

62

63

64

65

66

D

General-purpose I/O port

(STBC) A pull-up resistor can be set (RD63 = “1”) using the pull-up

resistor setting register (RDR6). The setting does not apply for

ports set as outputs (D63 = “1”: invalid at the output setting).

PPG00

P64

Functions as the PPG00 output when PPG output is enabled.

D

General-purpose I/O port

(STBC) A pull-up resistor can be set (RD64 = “1”) using the pull-up

resistor setting register (RDR6). The setting does not apply for

ports set as outputs (D64 = “1”: invalid at the output setting).

PPG01

P65

Functions as the PPG01 output when PPG output is enabled.

D

General-purpose I/O port

(STBC) A pull-up resistor can be set (RD65 = “1”) using the pull-up

resistor setting register (RDR6). The setting does not apply for

ports set as outputs (D65 = “1”: invalid at the output setting).

CKOT

P66

Functions as the CKOT output when CKOT is operating.

D

General-purpose I/O port

(STBC) A pull-up resistor can be set (RD66 = “1”) using the pull-up

resistor setting register (RDR6). The setting does not apply for

ports set as outputs (D66 = “1”: invalid at the output setting).

PPG10

P67

Functions as the PPG10 output when PPG output is enabled.

D

General-purpose I/O port

(STBC) A pull-up resistor can be set (RD67 = “1”) using the pull-up

resistor setting register (RDR6). The setting does not apply for

ports set as outputs (D67 = “1”: invalid at the output setting).

PPG11

P90

Functions as the PPG11 output when PPG output is enabled.

65

66

67

68

I

General-purpose I/O port

AIN0

IRQ6

P91

Input to channel 0 of the 8/16-bit up/down timer.

Functions as an interrupt request input.

General-purpose I/O port

I

(STBC)

BIN0

Input to channel 0 of the 8/16-bit up/down timer.

(Continued)

STBC: Incorporates standby control

*1: LQFP (FPT-100P-M05)

*2: QFP (FPT-100P-M06)

10

MB90630A Series

(Continued)

Pin no.

Circuit

type

Pin name

P92

Function

LQFP*¹

QFP*²

67

69

I

General-purpose I/O port

(STBC)

ZIN0

P93

Input to channel 0 of the 8/16-bit up/down timer.

General-purpose I/O port

68

70

I

AIN1

IRQ7

P94

Input to channel 1 of the 8/16-bit up/down timer.

Functions as an interrupt request input.

General-purpose I/O port

69

70

71

72

73

74

76

77

78

71

72

73

74

75

76

78

79

80

I

(STBC)

BIN1

P95

Input to channel 1 of the 8/16-bit up/down timer.

General-purpose I/O port

I

(STBC)

ZIN1

P96

Input to channel 1 of the 8/16-bit up/down timer.

General-purpose I/O port

I

(STBC)

IN0

Trigger input for channel 0 of the input capture.

General-purpose I/O port

P97

I

(STBC)

IN1

Trigger input for channel 1 of the input capture.

General-purpose I/O port

PA0

OUT0

PA1

OUT1

PA2

OUT2

PA3

OUT3

PA4

H

(STBC)

Event output for channel 0 of the output compare.

General-purpose I/O port

H

(STBC)

Event output for channel 1 of the output compare.

General-purpose I/O port

H

(STBC)

Event output for channel 2 of the output compare.

General-purpose I/O port

H

(STBC)

Event output for channel 3 of the output compare.

General-purpose I/O port

H

(STBC)

32

35

33

34

28

29

34

37

35

36

30

31

AV^CC

—

A/D converter power supply pin

AVSS

A/D converter power supply pin

AVRH

AVRL

DVRH

DV^SS

A/D converter external reference power supply pin

D/A converter external reference power supply pin

D/A converter power supply pin

47 to 49 49 to 51 MD0 to MD2

Operating mode selection pins.

Connect directly to VCC or VSS.

C

21, 82 23, 84 V^CC

—

Power supply (5.0 V) input pin

Power supply (0.0 V) input pin

9, 40, 79 11, 42, 81 VSS

STBC: Incorporates standby control

*1: LQFP (FPT-100P-M05)

*2: QFP (FPT-100P-M06)

11

MB90630A Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Oscillator feedback

A

X1

X0

Registance 1 MΩ (approx.)

Standby control signal

B

• Hysteresis input with pull-up

Registance 50 kΩ (approx.)

HYS

C

D

• Hysteresis input port

HYS

• Incorporates pull-up resistor control

(for input)

CTL

Registance 50 kΩ (approx.)

• CMOS level I/O

CMOS

E

• Incorporates pull-up resistor control

(for input)

CTL

Registance 50 kΩ (approx.)

• CMOS level output

• Hysteresis input

HYS

F

• CMOS level I/O

• Open-drain control signal

Open-drain control

signal

CMOS

(Continued)

12

MB90630A Series

(Continued)

Type

Circuit

Remarks

G

• CMOS level output

• Hysteresis input

• Incorporates open-drain control

Open-drain control

signal

HYS

H

• CMOS level I/O

CMOS

I

• CMOS level output

• Hysteresis input

HYS

K

• CMOS level I/O

• Analog input

CMOS

Analog input

L

• CMOS level I/O

• Analog output

• Shared with D/A outputs

D/A output

CMOS

M

• Incorporates pull-up resistor control

(for input)

CTL

Registance 50 kΩ (approx.)

• CMOS level output

• Hysteresis input

HYS

13

MB90630A Series

■ HANDLING DEVICES

1. Preventing Latch-up

Latch-up occurs in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin

or if the voltage applied between VCC and VSS exceeds the rating. If latch-up occurs, the power supply current

increases rapidly resulting in thermal damage to circuit elements. Therefore, ensure that maximum ratings are

not exceeded in circuit operation.

For the same reason, also ensure that the analog supply voltage does not exceed the digital supply voltage.

2. Treatment of Unused Pins

Leaving unused input pins unconnected can cause misoperation. Always pull-up or pull-down unused pins.

3. External Reset Input

To reliably reset the controller by inputting an “L” level to the RST pin, ensure that the “L” level is applied for at

least five machine cycles. Take particular note when using an external clock input.

4. V^CCand V^SSPins

Ensure that all VCC pins are at the same voltage. The same applies for the VSS pins.

5. Precautions when Using an External Clock

Drive the X0 pin only when using an external clock.

• Using an external clock

MB90630A

X0

X1

6. A/D Converter Power Supply and the Turn-on Sequence for Analog Inputs

Always turn off the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) before

turning off the digital power supply (VCC).

When turning the power on or off, ensure that AVRH does not exceed AVCC.

Also, when using the analog input pins as input ports, ensure that the input voltage does not exceed AVCC.

7. Program Mode

All bits (64 K × 16 bits) in the MB90P634A are “1” on delivery from Fujitsu or after erasing. To write data,

selectively program the desired bits to “0”. The value “1” cannot be written electrically.

14

MB90630A Series

8. Recommended Screening Conditions

High temperature aging is recommended as the pre-assembly screening procedure.

9. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

10. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is

therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations

(P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the

transient fluctuation rate will be less than 0.1 V/ms at the time of 2 momentary fluctuation such as when power

is switched.

15

MB90630A Series

■ PROGRAMMING THE EPROM IN THE MB90P634A

In EPROM mode, the MB90P634A function as MBM27C1000 equivalents. By using a dedicated adapter socket,

the devices can be programmed using a standard EPROM programmer.

1. Pin Assignment in EPROM Mode

• Pins compatible with the MBM27C1000

MBM27C1000

MB90P634A

Pin number

Pin name

V^PP

Pin number

Pin name

MD2 (VPP)

P32

P17

P14

P27

P26

P25

P24

P23

P22

P21

P20

P00

P01

P02

—

1

49

10

98

95

6

2

OE

3

A15

A12

A07

A06

A05

A04

A03

A02

A01

A00

D00

D01

D02

GND

V^CC

4

5

6

5

7

4

8

3

9

2

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

1

100

99

83

84

85

—

11

—

97

96

91

92

94

7

—

PGM

NC

P33

—

A14

A13

A08

A09

A11

A16

A10

CE

P16

P15

P10

P11

P13

P30

P12

P31

P07

93

8

D07

90

(Continued)

16

MB90630A Series

(Continued)

MBM27C1000

MB90P634A

Pin number

Pin name

D06

Pin number

Pin name

P06

20

19

18

17

89

88

87

86

D05

P05

D04

P04

D03

P03

• Power supply and GND connection pins

Type

Pin number

Pin name

Power supply (V^CC)

28

50

21, 82

DVRH

HST

VCC

GND

9

V^SS

34

35

40

29

75

79

12

13

14

AVRL

AVSS

VSS

DVSS

RST

VSS

P34

P35

P36

17

MB90630A Series

• Pins other than MBM27C1000-compatible pins

Pin number

Pin name

Treatment

Pull-up (4.7 kΩ)

47

48

80

MD0

MD1

X0

81

X1

OPEN

15

P37

16 to 20

22 to 24

25 to 27

30

P40 to P44

P45 to P47

P70 to P72

P73

31

P74

36 to 39

41 to 44

45

P50 to P53

P54 to P57

P80

Connect pull-up resistors of

approximately 1 MΩ to each pin

46

P81

51 to 56

57 to 64

65 to 72

73

P82 to P87

P60 to P67

P90 to P97

PA0

74

PA1

76

77

PA2

PA3

78

PA4

2. EPROM Programmer Socket Adapter

Compatible socket adapter

Sun Hayato Co., Ltd.

Part no.

Package

MB90P634APFV SQFP-100

ROM-100SQF-32DP-16L

Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403

FAX: (81)-3-5396-9106

18

MB90630A Series

3. Programming Procedure

(1) Set the EPROM programmer for a MBM27C1000.

(2) Load the program data between 10000^Hand 1FFFFH in the EPROM programmer.

In the MB90P634A, ROM addresses FFFFFFH to FF0000H in operating mode correspond to addresses 1FFFFH

to 10000H in EPROM mode.

FFFFFF H

1FFFF ^H

FF0000 ^H

10000 ^H

Operating mode

EPROM mode

(3) Set the MB90P634A, in the adapter socket and connect the adapter socket to the EPROM programmer.

Take care to correctly align the device with the adapter.

(4) Perform programming.

(5) If programming cannot be performed successfully, connect a 0.1 µF or similar capacitor between V^CCand

GND and between V^PPand GND.

Note: As mask ROM products (MB90632A, 634A) do not support EPROM mode, data cannot be read using an

EPROM programmer. Performing a blank check for other than the above addresses results in either non-

EPROM addresses being read or the blank check being unable to be performed.

19

MB90630A Series

■ BLOCK DIAGRAM

CPU

Clock control

circuit

X0, 1

RST

HST

4

F²MC-16L series core

Interrupt controller

RAM

ROM

2

PPG00, 01

PPG10, 11

8 + 8PPG

(Output switching) × 1 channel

× 2

U/D counter

8 bits × 2

(16 bits × 1)

AIN0, 1

BIN0, 1

ZIN0, 1

Communications prescaler

2

SIN0, 3

SOT0, 3

SCK0, 3

2

UART × 2 channels

CKOT

Prescaler

8

2

IRQ0 to IRQ7

SIN1, 2

SOT1, 2

SCK1, 2

External interrupts

2

I/O expansion serial

2

interface × 2 channels

2

I/O timers

IN0, 1

OUT1 to OUT3

16-bit input capture × 2 channels

16-bit output capture × 4 channels

16-bit free-run timer

AVCC

AVRH, AVRL

AVSS

ADTG

AN0 to AN7

3

2

A/D converter

(10 bits)

8

2

DAO0, 1

DVRH

DV^SS

D/A converter

(8 bits) × 2 channels

I/O ports

8

5

8

5

P00 P10 P20 P30 P40 P50 P60 P70 P80 P90 PA0

to to to to to to to to to to to

P07 P17 P27 P37 P47 P57 P67 P74 P87 P97 PA4

P00 to P07 (8 pins) : Incorporates a pull-up resistor setting register (for input)

P10 to P17 (8 pins) : Incorporates a pull-up resistor setting register (for input)

P60 to P67 (8 pins) : Incorporates a pull-up resistor setting register (for input)

P40 to P47 (8 pins) : Incorporates an open-drain setting register

20

MB90630A Series

■ F²MC-16L CPU PROGRAMMING MODEL

• Dedicated Registers

Accumulator

AH

AL

USP

SSP

User stack pointer

System stack pointer

Processor status

PS

PC

Program counter

USPCU

SSPCU

USPCL

SSPCL

User stack upper register

System stack upper register

User stack lower register

System stack lower register

Direct page register

DPR

Program bank register

Data bank register

PCB

DTB

USB

SSB

ADB

User stack bank register

System stack bank register

Additional data bank register

8 bits

16 bits

32 bits

• General-purpose Registers

Maximum 32 banks

R7

R5

R3

R1

R6

RW7

RW6

RW5

RW4

RL3

RL2

RL1

RL0

R4

R2

R0

RW3

RW2

RW1

RW0

000180

H

+ RP × 10H →

16 bit

• Processor Status (PS)

ILM

RP

−

I

S

T

N

Z

V

C

CCR

21

MB90630A Series

■ MEMORY MAP

Single chip

FFFFFF H

Internal ROM/External bus

ROM area

External ROM/External bus

ROM area

Address 1#

FF0000 ^H

010000 H

ROM area

(FF bank image)

Address 2#

004000 H

002000 H

Address 3#

000380 ^H

RAM

Registers

RAM

Registers

RAM

Registers

000180 ^H

000100 H

0000C0 H

Peripherals

000000 H

: Internal

: External

: No access

Type

MB90632A

MB90634A

Address #1

FF8000H

FF0000H

Address #2

Address #3

000500H

000900H

008000H

004000H

000D00H

MB90P634A

22

MB90630A Series

■ I/O MAP

Register

name

Address

Register

Access

Resource

Initial value

00^H

01^H

Port 0 data register

Port 1 data register

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

PDR7

PDR8

PDR9

PDRA

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

XXXXXXXX

–––XXXXX

XXXXXXXX

–––XXXXX

02^H

Port 2 data register

Port 3 data register

Port 4 data register

Port 5 data register

Port 6 data register

Port 7 data register

Port 8 data register

Port 9 data register

Port A data register

03H

04^H

05^H

06H

07^H

08H

09^H

0AH

0B to 0FH

10^H

Reserved area

DDR0

Port 0 direction register

Port 1 direction register

Port 2 direction register

Port 3 direction register

Port 4 direction register

Port 5 direction register

Port 6 direction register

Port 7 direction register

Port 8 direction register

Port 9 direction register

Port A direction register

Port 4 pin register

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port 4

Port 0

Port 1

Port 6

Port 5, A/D

00000000

–––00000

00000000

–––00000

00000000

11111111

00000000

00000100

11H

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

DDR7

DDR8

DDR9

DDRA

ODR4

RDR0

RDR1

RDR6

ADER

SMR0

SCR0

12H

13^H

14H

15^H

16H

17H

18^H

19H

1AH

1B^H

1C^H

1DH

1EH

1F^H

20H

Port 0 resistance register

Port 1 resistance register

Port 6 resistance register

Analog input enable register

Serial mode register 0

Serial control register 0

21H

UART0

Serial input register/

Serial output register 0

SIDR/

SODR0

22^H

R/W

XXXXXXXX

(Continued)

23

MB90630A Series

Register

name

Address

Register

Access

Resource

Initial value

23^H

24H

25^H

26^H

Serial status register 0

SSR0

SMCS0

SDR0

R/W

UART0

00001–00

––––0000

00000010

XXXXXXXX

Serial mode control status register 0

Serial data register 0

I/O expansion serial

interface 0

Communications

prescaler

27^H

Clock division control register

CDCR

R/W

0–––1111

Serial mode control status register 1

Serial data register 1

28^H

29^H

SMCS1

SDR1

R/W

––––0000

00000010

XXXXXXXX

I/O expansion serial

interface 1

2A^H

2B to 2FH

30H

Reserved area

Interrupt/DTP enable register

Interrupt/DTP source register

ENIR

R/W

00000000

XXXXXXXX

00000000

31H

EIRR

DTP/External interrupts

32^H

Request level setting register

ELVR

R/W

33^H

34 to 35H

36^H

Reserved area

ADCS1

00000000

XXXXXXXX

–––––––0

–––––000

Control status register

Data register

R/W

R

37^H

ADCS2

ADCR1

ADCR2

DAT0

A/D converter

38^H

39^H

3AH

D/A converter data register 0

D/A converter data register 1

D/A control register 0

R/W

3B^H

DAT1

D/A converter

CKOT output

3CH

DACR0

DACR1

CLKR

3DH

D/A control register 1

3E^H

Clock control register

3F^H

Reserved area

40H

Reload register L (channel 0)

Reload register H (channel 0)

Reload register L (channel 1)

Reload register H (channel 1)

PPG0 operation mode control register

PPG1 operation mode control register

PPG0, 1 output control register

PRLL0

R/W

XXXXXXXX

0X000XX1

0X000001

00000000

41H

PRLH0

PRLL1

PRLH1

PPGC0

PPGC1

PPGOE

42^H

43H

8/16 bit PPG

44H

45^H

46H

47 to 4FH

Reserved area

OCCP0 R/W

16-bit I/O timer output

compare (channel 0 to 3)

50^H

Lower compare register channel 0

XXXXXXXX

(Continued)

24

MB90630A Series

Register

name

Address

Register

Access

Resource

Initial value

51^H

52H

Upper compare register channel 0

Lower compare register channel 1

Upper compare register channel 1

Lower compare register channel 2

Upper compare register channel 2

Lower compare register channel 3

Upper compare register channel 3

Compare control status register channel 0

Compare control status register channel 1

Compare control status register channel 2

Compare control status register channel 3

OCCP0

R/W

XXXXXXXX

–––00000

0000––00

–––00000

0000––00

OCCP1

R/W

53^H

54^H

OCCP2

OCCP3

55H

16-bit I/O timer

Output compare

(channel 0 to 3)

56^H

57^H

58H

OCS0

OCS1

OCS2

OCS3

R/W

59^H

5AH

5B^H

5C to 5FH

60H

Reserved area

R

Lower input capture register channel 0

Upper input capture register channel 0

Lower input capture register channel 1

Upper input capture register channel 1

Input capture control status register

Reserved area

XXXXXXXX

00000000

––––––––

00000000

IPCP0

61^H

R

16-bit I/O timer

Input capture

(channel 0, 1)

62H

IPCP1

63^H

R

64^H

ICS

—

R/W

—

65H

66^H

Lower timer data register

TCDTL

TCDTH

TCCS

R/W

16-bit I/O timer

Free-run timer

(channel 0, 1)

67H

Upper timer data register

68H

Timer control status register

69 to 6F^H

70H

Reserved area

Up/down count register channel 0

Up/down count register channel 1

Reload compare register channel 0

Reload compare register channel 1

Counter status register channel 0

Reserved area

UDCR0

00000000

––––––––

–0000000

00000000

––––––––

–0000000

(Continued)

R

71^H

UDCR1

RCR0

RCR1

CSR0

—

72^H

W

73^H

74H

R/W

—

8/16-bit up/down

timer/counter

75H

76^H

CCRL0

CCRH0

CSR1

—

Counter control register channel 0

R/W

77^H

78H

Counter status register channel 1

Reserved area

R/W

—

79^H

7AH

Counter control register channel 1

CCRL1

R/W

25

MB90630A Series

Register

name

Address

Register

Access

Resource

Initial value

Counter control register

channel 1

8/16-bit up/down

timer/counter

7B^H

CCRH1

R/W

–0000000

7C to 87^H

88H

Reserved area

Serial mode register 1

Serial control register 1

SMR1

R/W

00000000

00000100

89H

SCR1

UART1

Serial input register 1/serial

output register 1

SIDR1/

SODR1

8A^H

R/W

XXXXXXXX

00001–00

8BH

Serial status register 1

SSR1

8C to 9EH

Reserved area (Accessing 90H to 9EH is prohibited.)

Delayed interrupt generation/

clear register

Delayed interrupt

generation module

9F^H

A0^H

DIRR

R/W

–––––––0

Low-power consumption mode

register

LPMCR

CKSCR

R/W

Low-power consumption 00011000

Low-power consumption 11001100

A1^H

Clock selection register

A2 to A4^H

Reserved area

Auto-ready function selection

register

A5^H

A6^H

A7^H

ARSR

W

External pins

0011––00

––––0000

0000*00–

External address output control

register

HACR

ECSR

Bus control signal selection

register

A8^H

A9^H

Watchdog timer control register

Timebase timer control register

WDTC

TBTC

R/W

Watchdog timer

Timebase timer

XXXXX111

1––00100

AA to AF^H

B0H

Reserved area

Interrupt control register 00

Interrupt control register 01

Interrupt control register 02

Interrupt control register 03

Interrupt control register 04

Interrupt control register 05

Interrupt control register 06

Interrupt control register 07

Interrupt control register 08

Interrupt control register 09

Interrupt control register 10

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

ICR00

R/W

00000111

(Continued)

B1^H

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

B2^H

B3H

B4H

B5^H

B6H

Interrupt controller

B7H

B8^H

B9H

BAH

BB^H

BCH

BD^H

26

MB90630A Series

(Continued)

Register

name

Address

Register

Access

Resource

Initial value

BE^H

BFH

Interrupt control register 14

Interrupt control register 15

Reserved area

ICR14

ICR15

—

R/W

—

00000111

—

Interrupt controller

—

C0 to FF^H

Initial values

0: The initial value of this bit is “0”.

1: The initial value of this bit is “1”.

* : The initial value of this bit is “0” or “1”.

X: The initial value of this bit is undefined.

–: This bit is not used. The initial value is undefined.

Note: Areas below address 0000FF^Hnot listed in the table are reserved areas. These addresses are accessed by

internal access. No access signals are output on the external bus.

27

MB90630A Series

■ INTERRUPT VECTOR AND INTERRUPT CONTROL REGISTER ASSIGNMENTS TO

INTERRUPT SOURCES

Interrupt vector

Number

Interrupt control register

I²OS

Interrupt source

support

Address

FFFFDC^H

FFFFD8^H

FFFFD4^H

FFFFD0^H

FFFFC8H

FFFFC4H

FFFFC0H

FFFFBCH

FFFFB8H

FFFFB4H

FFFFB0H

FFFFACH

FFFFA8H

ICR

—

Address

Reset

×

#08

#09

#10

#11

#13

#14

#15

#16

#17

#18

#19

#20

#21

—

INT 9 instruction

—

Exception

—

A/D converter

ICR00

0000B0H

DTP 0 (External interrupt 0)

16-bit free-run timer (I/O timer) overflow

I/O expansion serial 1

ICR01

ICR02

ICR03

ICR04

0000B1H

0000B2H

0000B3H

0000B4H

DTP 1 (External interrupt 1)

I/O expansion serial 2

DTP 2 (External interrupt 2)

DTP 3 (External interrupt 3)

8/16-bit PPG 0 counter borrow

8/16-bit U/D counter 0 compare

ICR05

ICR06

0000B5H

0000B6H

8/16-bit U/D counter 0 underflow/

overflow, up/down invert

#22

FFFFA4^H

8/16-bit PPG 1 counter borrow

DTP 4/5 (External interrupt 4/5)

Output compare (channel 2) match (I/O timer)

Output compare (channel 3) match (I/O timer)

DTP 6 (External interrupt 6)

#23

#24

#25

#26

#28

#29

FFFFA0H

FFFF9CH

FFFF98H

FFFF94H

FFFF8CH

FFFF88H

ICR07

ICR08

0000B7H

0000B8H

8/16-bit U/D counter 1 compare

ICR09

ICR10

0000B9H

0000BAH

8/16-bit U/D counter 1 underflow/

overflow, up/down invert

#30

FFFF84^H

Input capture (channel 0) read (I/O timer)

Input capture (channel 1) read (I/O timer)

Output compare (channel 0) match (I/O timer)

Output compare (channel 1) match (I/O timer)

DTP 7 (External interrupt 7)

UART0 receive complete

UART1 receive complete

UART0 transmit complete

UART1 transmit complete

Reserved

#31

#32

#33

#34

#36

#37

#38

#39

#40

#41

#42

FFFF80H

FFFF7CH

FFFF78H

FFFF74H

FFFF6CH

FFFF68H

FFFF64H

FFFF60H

FFFF5CH

FFFF58H

FFFF54H

ICR11

ICR12

ICR13

0000BBH

0000BCH

0000BDH

ICR14

ICR15

0000BEH

0000BFH

×

Delayed interrupt

: Indicates that the interrupt request flag is cleared by the I²OS interrupt clear signal (no stop request).

: Indicates that the interrupt request flag is cleared by the I²OS interrupt clear signal (stop request present).

: Indicates that the interrupt request flag is not cleared by the I²OS interrupt clear signal.

Note: For resources in which two interrupt sources share the same interrupt number, the I²OS interrupt clear signal

clears both interrupt request flags.

28

MB90630A Series

■ PERIPHERAL RESOURCES

1. Parallel Ports

(1) I/O Ports

Each port pin can be specified as either an input or output by its corresponding direction register when the pin

is not set for use by a peripheral. When a port is set as an input, reading the data register always reads the

value corresponding to the pin level. When a port is set as an output, reading the data register reads the data

register latch value. The same applies when reading using a read-modify-write instruction.

When used as control outputs, reading the data register reads the control output value, irrespective of the

direction register value.

Note that if a read-modify-write instruction (set bit or similar instruction) is used to set output data in the data

register before switching a pin from input to output, the instruction reads the input level at the pin and not the

data register latch value.

• Block Diagram

↑

Data register read

Data register

↑

Data register write

Direction register

↑

Direction register write

↑

Direction register read

29

MB90630A Series

(2) Register Configuration

15/7 14/6 13/5 12/4 11/3 10/2 9/1

8/0

bit

P00

P10

P20

P30

P40

P50

P60

P70

P80

P90

PA0

P07 P06 P05 P04 P03 P02 P01

P17 P16 P15 P14 P13 P12 P11

P27 P26 P25 P24 P23 P22 P21

P37 P36 P35 P34 P33 P32 P31

P47 P46 P45 P44 P43 P42 P41

P57 P56 P55 P54 P53 P52 P51

P67 P66 P65 P64 P63 P62 P61

Port 0 data register (PDR0)

Port 1 data register (PDR1)

Port 2 data register (PDR2)

Port 3 data register (PDR3)

Port 4 data register (PDR4)

Port 5 data register (PDR5)

Port 6 data register (PDR6)

Port 7 data register (PDR7)

Port 8 data register (PDR8)

Port 9 data register (PDR9)

Port A data register (PDRA)

Address: 000000^H

Address: 000001H

Address: 000002H

Address: 000003H

Address: 000004H

Address: 000005H

Address: 000006H

Address: 000007H

Address: 000008H

Address: 000009H

Address: 00000AH

—

P74 P73 P72 P71

P87 P86 P85 P84 P83 P82 P81

P97 P96 P95 P94 P93 P92 P91

—

PA4 PA3 PA2 PA1

15/7 14/6 13/5 12/4 11/3 10/2 9/1

8/0

bit

D00

D10

D20

D30

D40

D50

D60

D70

D80

D90

DA0

D07 D06 D05 D04 D03 D02 D01

D17 D16 D15 D14 D13 D12 D11

D27 D26 D25 D24 D23 D22 D21

D37 D36 D35 D34 D33 D32 D31

D47 D46 D45 D44 D43 D42 D41

D57 D56 D55 D54 D53 D52 D51

D67 D66 D65 D64 D63 D62 D61

Port 0 direction register (DDR0)

Port 1 direction register (DDR1)

Port 2 direction register (DDR2)

Port 3 direction register (DDR3)

Port 4 direction register (DDR4)

Port 5 direction register (DDR5)

Port 6 direction register (DDR6)

Port 7 direction register (DDR7)

Port 8 direction register (DDR8)

Port 9 direction register (DDR9)

Port A direction register (DDRA)

Address: 000010^H

Address: 000011H

Address: 000012H

Address: 000013H

Address: 000014H

Address: 000015H

Address: 000016H

Address: 000017H

Address: 000018H

Address: 000019H

Address: 00001AH

—

D74 D73 D72 D71

D87 D86 D85 D84 D83 D82 D81

D97 D96 D95 D94 D93 D92 D91

—

DA4 DA3 DA2 DA1

15

14

13

12

11

10

9

8

bit

OD47 OD46 OD45 OD44 OD43 OD42 OD41

OD40 Port 4 pin register (ODR4)

Address: 00001B^H

15/7 14/6 13/5 12/4 11/3 10/2 9/1

8/0

bit

RD00

RD07 RD06 RD05 RD04 RD03 RD02 RD01

RD17 RD16 RD15 RD14 RD13 RD12 RD11

RD67 RD66 RD65 RD64 RD63 RD62 RD61

Port 0 resistor register (RDR0)

Address: 00001C^H

Address: 00001DH

Address: 00001EH

RD10

Port 1 resistor register (RDR1)

RD60

Port 6 resistor register (RDR6)

15

14

13

12

11

10

9

8

bit

ADE0

ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1

Port 5 analog input enable register

Address: 00001F^H

(ADER)

30

MB90630A Series

(3) Register Details

• Port Data Registers

7

6

5

4

3

2

1

0

bit

Initial value

Undefined

Access

R/W*

PDR0

P07

P06

P05

P04

P03

P02

P01

P00

Address: 000000^H

15

14

13

12

11

10

9

8

bit

PDR1

Address: 000001H

P17

P16

P15

P14

P13

P12

P11

P10

Undefined

R/W*

7

6

5

4

3

2

1

0

bit

PDR2

Address: 000002H

P27

P26

P25

P24

P23

P22

P21

P20

15

14

13

12

11

10

9

8

bit

PDR3

Address: 000003^H

P37

P36

P35

P34

P33

P32

P31

P30

Undefined

7

6

5

4

3

2

1

0

bit

PDR4

Address: 000004^H

P47

P46

P45

P44

P43

P42

P41

P40

15

14

13

12

11

10

9

8

bit

PDR5

Address: 000005^H

P57

P56

P55

P54

P53

P52

P51

P50

7

6

5

4

3

2

1

0

bit

PDR6

Address: 000006^H

P67

P66

P65

P64

P63

P62

P61

P60

Undefined

15

—

14

—

13

—

12

11

10

9

8

bit

PDR7

Address: 000007H

P74

P73

P72

P71

P70

7

6

5

4

3

2

1

0

bit

PDR8

Address: 000008^H

P87

P86

P85

P84

P83

P82

P81

P80

Undefined

15

14

13

12

11

10

9

8

bit

PDR9

Address: 000009^H

P97

P96

P95

P94

P93

P92

P91

P90

7

6

5

4

3

2

1

0

bit

PDRA

Address: 00000A^H

—

PA4

PA3

PA2

PA1

PA0

Undefined

* : The operation of reading or writing to I/O ports is slightly different from reading or writing to memory, as follows.

• Input mode

Read: Reads the corresponding pin level.

Write: Writes to the output latch.

• Output mode

Read: Reads the value of the data register latch.

Write: The value is output from the corresponding pin.

31

MB90630A Series

• Port Direction Registers

7

6

5

4

3

2

1

0

bit

Initial value

00000000^B

Access

R/W

DDR0

D07

D06

D05

D04

D03

D02

D01

D00

Address: 000010^H

15

14

13

12

11

10

9

8

bit

DDR1

Address: 000011H

D17

D16

D15

D14

D13

D12

D11

D10

00000000B

R/W

7

6

5

4

3

2

1

0

bit

DDR2

Address: 000012H

D27

D26

D25

D24

D23

D22

D21

D20

15

14

13

12

11

10

9

8

bit

DDR3

Address: 000013^H

D37

D36

D35

D34

D33

D32

D31

D30

00000000^B

00000000B

00000000^B

7

6

5

4

3

2

1

0

bit

DDR4

Address: 000014^H

D47

D46

D45

D44

D43

D42

D41

D40

15

14

13

12

11

10

9

8

bit

DDR5

Address: 000015^H

D57

D56

D55

D54

D53

D52

D51

D50

7

6

5

4

3

2

1

0

bit

DDR6

Address: 000016^H

D67

D66

D65

D64

D63

D62

D61

D60

00000000^B

-----000B

15

—

14

—

13

—

12

11

10

9

8

bit

DDR7

Address: 000017H

D74

D73

D72

D71

D70

7

6

5

4

3

2

1

0

bit

DDR8

Address: 000018^H

D87

D86

D85

D84

D83

D82

D81

D80

00000000^B

00000000B

15

14

13

12

11

10

9

8

bit

DDR9

Address: 000019^H

D97

D96

D95

D94

D93

D92

D91

D90

7

6

5

4

3

2

1

0

bit

DDRA

Address: 00001A^H

—

DA4

DA3

DA2

DA1

DA0

---00000^B

When pins are used as ports, the register bits control the corresponding pins as follows.

0: Input mode

1: Output mode

Bits are set to “0” by a reset.

32

MB90630A Series

• Port Resistance Registers

7

6

5

4

3

2

1

0

bit

Initial value

00000000^B

RDR0

Address: 00001C^H

RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00

15

14

13

12

11

10

9

8

bit

RDR1

Address: 00001D^H

RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10

00000000^B

7

6

5

4

3

2

1

0

bit

RDR6

Address: 00001E^H

RD67 RD66 RD65 RD64 RD63 RD62 RD61 RD60

• Block Diagram

Pull-up resistor (approx. 50 kΩ)

Port I/O

Data register

Direction register

Resistance register

Notes: • Input resistance register R/W

Controls the pull-up resistor in input mode.

0: Pull-up resistor disconnected in input mode.

1: Pull-up resistor connected in input mode.

The setting has no meaning in output mode (pull-up resistor disconnected).

The direction register (DDR) sets input or output mode.

• The pull-up resistor is disconnected in hardware standby or stop mode (SPL = 1) (high impedance).

• This function is disabled when using an external bus. In this case, do not write to this register.

33

MB90630A Series

• Port Pin Register

7

6

5

4

3

2

1

0

bit

Initial value

00000000^B

ODR4

Address: 00001B^H

OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40

• Block Diagram

Port I/O

Data register

Direction register

Pin register

Notes: • Pin register R/W

Performs open-drain control in output mode.

0: Operate as a standard output port in output mode.

1: Operate as an open-drain output port in output mode.

The setting has no meaning in input mode (output Hi-z).

The direction register (DDR) sets input or output mode

• The pull-up resistor is disconnected in hardware standby or stop mode (SPL = 1) (high impedance).

• This function is disabled when using an external bus. In this case, do not write to this register.

• Analog Input Enable Register

15

14

13

12

11

10

9

8

bit

Initial value

11111111^B

ADER

Address: 00001F^H

ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Controls each port 5 pin as follows.

0: Port input mode

1: Analog input mode

Set to “1” by a reset.

34

MB90630A Series

2. UART

The UART is a serial I/O port that can be used for CLK asynchronous (start-stop synchronization) or CLK

synchronous communications. The UART has the following features.

• Full duplex, double buffered

• Supports asynchronous (start-stop synchronization) and CLK synchronous data transfer

• Supports multi-processor mode

• Built-in dedicated baud rate generator

Asynchronous: 9615, 31250, 4808, 2404, 1202 bps

For a 6, 8, 10, 12, or 16 MHz clock.

CLK synchronous: 1 Mbps, 500 Kbps, 250 Kbps, 125 Kbps, and 62.5

• Supports flexible baud rate setting using an external clock

• Error detect function (parity, framing, and overrun)

• NRZ type transmission signal

• Intelligent I/O service support

(1) Register Configuration

15

8

7

0

(R/W)

—

SMR

CDCR

SCR

SIDR (R)/SODR (W)

8 bits

SSR

8 bits

7

6

5

4

3

2

1

0

bit

Serial mode register 0, 1

(SMR0, 1)

Address: 000020H

000088H

MD1

MD0

CS2

CS1

CS0 Reserved SCKE SOE

15

14

P

13

12

11

10

9

8

bit

Serial control register 0, 1

(SCR0, 1)

Address: 000021H

000089H

PEN

SBL

CL

A/D

REC

RXE

TXE

7

6

5

4

3

2

1

0

bit

Serial input register/

Serial output register 0, 1

(SIDR/SODR0, 1)

Address: 000022H

00008AH

D7

D6

D5

D4

D3

D2

D1

D0

15

14

13

12

11

10

—

9

8

bit

Serial status register 0, 1

(SSR0, 1)

Address: 000023H

00008BH

PE

ORE

FRE RDRF TDRE

RIE

TIE

15

14

—

13

—

12

—

11

10

9

8

bit

Clock division control register

(CDCR)

Address: 000027H

MD

DIV3

DIV2

DIV1

DIV0

35

MB90630A Series

(2) Block Diagram

Control signals

Reception interrupt

(to CPU)

SCK0, 1

Dedicated baud rate generator

Upper 8/16-bit PPG timer

Transmission clock

pulses

Transmission interrupt

(to CPU)

(Connected internally)

Clock select

circuit

Reception clock

pulses

External clock

Transmission control

Reception control

circuit

Transmission start

circuit

SIN0, 1

Start bit counter

Reception bit

counter

Transmission bit

counter

Transmission parity

counter

Reception parity

counter

SOT0, 1

Reception status

detection circuit

Reception shifter

End of

Transmission shifter

Start of

transmission

Reception error

reception

occurrence signal

for I²OS

SODR

SIDR

(to CPU)

F²MC-16 bus

MD1

MD0

CS2

CS1

CS0

PEN

PE

P

ORE

FRE

SBL

CL

SMR

register

SCR

register

SSR

register

RDRF

TDRE

A/D

REC

RXE

TXE

SCKE

SOE

RIE

TIE

Control signals

36

MB90630A Series

3. I/O Expansion Serial Interface

This block consists of an 8-bit serial I/O interface that can perform clock synchronous data transfer. Either LSB-

first or MSB-first data transfer can be selected.

The following two serial I/O operation modes are available.

• Internal shift clock mode: Data transfer is synchronized with the internal clock.

• External shift clock mode: Data transfer is synchronized with the clock input from the external pin (SCK). By

manipulating the general-purpose port that shares the external pin (SCK), this

mode also enables the data transfer operation to be driven by CPU instructions.

(1) Register Configuration

15

14

13

12

11

10

9

8

bit

Address: 000025^H

000029H

SMD2 SMD1 SMD0

SIE

SIR

BUSY STOP STRT

7

6

5

4

3

2

1

0

bit

Serial mode control status

registers 0, 1 (SMCS0, 1)

Address: 000024H

000028H

—

MODE BDS

SOE SCOE

7

6

5

4

3

2

1

0

bit

Serial data registers 0, 1

(SDR0, 1)

Address: 000026H

00002AH

D7

D6

D5

D4

D3

D2

D1

D0

(2) Register Details

• Serial Mode Control Status Register (SMCS)

15

SMD2 SMD1 SMD0

(R/W) (R/W) (R/W) (R/W) (R/W*¹) (R)

14

13

12

11

10

9

8

bit

SMCS

Initial value

00000010^B

SIE

SIR

BUSY STOP STRT

(R/W) (R/W*²)

Address: 000025H

000029H

7

6

5

4

3

2

1

0

bit

SMCS

Initial value

----0000B

—

MODE BDS

SOE SCOE

Address: 000024H

000028H

(R/W) (R/W) (R/W) (R/W)

*1: Only “0” can be written.

*2: Only “1” can be written. Reading always returns “0”.

This register controls the transfer operation mode of the serial I/O. The following describes the function of each

bit.

(a) [bit 3] Serial mode selection bit (MODE)

Thisbitselectstheconditionsforstartingoperationfromthehaltedstate. Changingthemodeduringoperation

is prohibited.

MODE

Operation

Start when STRT is set to “1”. [Initial value]

Start on reading from or writing to the serial data register.

0

1

The bit is initialized to “0” by a reset. The bit is readable and writable. Set to “1” when using the intelligent I/O

service.

37

MB90630A Series

(b) [bit 2] Transfer direction selection bit (BDS: Bit Direction Select)

Selects as follows at the time of serial data input and output whether the data are to be transferred in the

order from LSB to MSB or vice versa.

MODE

Operation

0

1

LSB-first [Initial value]

MSB-first

(3) Block Diagram

Internal data bus

(MSB-first) D0 to D7

SIN1, 2

D7 to D0 (LSB-first)

Transfer direction selection

Read

Write

SDR (Serial data register)

SOT1, 2

SCK1, 2

Control circuit

Shift clock counter

Internal clock

2

1

0

SMD2 SMD1 SMD0 SIE

SIR BUSY STOP STRT MODE BDS SOE SCOE

Interrupt

request

Internal data bus

38

MB90630A Series

4. A/D Converter

The A/D converter converts analog input voltages to digital values. The A/D converter has the following features.

• Conversion time: Minimum of 5.2 µs per channel (for a 16 MHz machine clock)

• Uses RC-type successive approximation conversion with a sample and hold circuit.

• 10-bit resolution

• Eight program-selectable analog input channels

Single conversion mode

Scan conversion mode

: Selectively convert a one channel.

: Continuously convert multiple channels. Maximum of 8 program-

selectable channels.

Continuous conversion mode : Repeatedly convert specified channels.

Stop conversion mode : Convert one channel then halt until the next activation. (Enables

synchronization of the conversion start timing.)

• An A/D conversion completion interrupt request to the CPU can be generated on the completion of A/D

conversion. This interrupt can activate I²OS to transfer the result of A/D conversion to memory and is suitable

for continuous operation.

• Activation by software, external trigger (falling edge), or timer (rising edge) can be selected.

(1) Register Configuration

The A/D converter has the following registers.

15

8

7

0

ADCS2

ADCR2

8 bits

ADCS1

ADCR1

8 bits

7

6

5

4

3

2

1

0

bit

Address: 000036H

MD1

MD0

ANS2 ANS1 ANS0 ANE2 ANE1 ANE0

Control status register

(ADCS1, ADCS2)

15

14

13

12

11

10

9

8

bit

Address: 000037H

BUSY

INT

INTE PAUS STS1 STS0 STRT

DA

7

6

5

4

3

2

1

0

bit

Address: 000038H

Data register

(ADCR1, ADCR2)

15

—

14

—

13

—

12

—

11

—

10

—

9

8

bit

Address: 000039H

39

MB90630A Series

(2) Block Diagram

AV CC

AVRH

AVRL

AV SS

D/A converter

MPX

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

Successive

approximation register

Comparator

Sample and

hold circuit

Data register

ADCR1, 2

A/D control register 1

A/D control register 2

ADCS1, 2

Trigger activation

ADTG

Timer activation

PPG01

Operating clock

Prescaler

φ

40

MB90630A Series

5. D/A Converter

This block is an R-2R type D/A converter with 8-bit resolution. The device contains two D/A converters. The

D/A control register controls the output of the two D/A converters independently.

(1) Register Configuration

7

6

5

4

3

2

1

0

bit

D/A converter data register 0

(DAT0)

Address: 00003A^H

DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00

15

14

13

12

11

10

9

8

bit

D/A converter data register 0

(DAT1)

Address: 00003BH

DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10

7

6

5

4

3

2

1

0

bit

D/A control register 0

(DACR0)

Address: 00003CH

—

DAE0

15

—

14

—

13

—

12

—

11

—

10

—

9

8

bit

D/A control register 1

(DACR1)

Address: 00003DH

—

DAE1

(2) Block Diagram

F²MC-16 bus

DA DA DA DA DA DA DA DA

17 16 15 14 13 12 11 10

DA DA DA DA DA DA DA DA

07 06 05 04 03 02 01 00

DVR

DA17

DA07

2R

R

DA16

DA06

2R

R

2R

R

DA15

DA11

DA05

DA01

2R

R

2R

R

DA10

DA00

2R

DAE1

Standby control

DAE0

Standby control

DA output

channel 1

DA output

channel 0

41

MB90630A Series

6. 8/16-bit PPG

This block is an 8-bit reload timer module. The block performs PPG output in which the pulse output is controlled

by the operation of the timer.

The hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two

external pulse output pins, and two interrupt outputs. The PPG has the following functions.

• 8-bit PPG output in two channels independent operation mode:

Two independent PPG output channels are available.

• 16-bit PPG output operation mode

• 8+8-bit PPG output operation mode

: One 16-bit PPG output channel is available.

: Variable-period 8-bit PPG output operation is available by using the

output of channel 0 as the clock input to channel 1.

• PPG output operation

: Outputs pulse waveforms with variable period and duty ratio. Can be

used as a D/A converter in conjunction with an external circuit.

(1) Register Configuration

PPG0 operation mode control

7

6

5

4

3

2

1

0

Address: channel 0 000044^H

PEN0

—

PE00

PIE0

PUF0

—

Reserved

PPGC0

PPGC1

PPGOE

PRLH0, 1

(R/W)

(0)

(—)

(X)

(R/W) (R/W) (R/W)

(0) (0) (0)

(—)

(X)

(—)

(X)

(—)

(1)

Read/write

Initial value

PPG1 operation mode control

15

14

13

PE10

(R/W) (R/W) (R/W)

12

11

10

MD1

(R/W) (R/W)

9

8

Address:

channel 1 000045H

PEN1

—

PIE1

PUF1

MD0

Reserved

Read/write

Initial value

(R/W)

(0)

(—)

(X)

(—)

(1)

(0)

PPG0, 1 output control register

Address: channel 0,1 000046H

7

6

5

4

3

2

1

0

PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11

(R/W) (R/W) (R/W) (R/W) (R/W)

(0) (0) (0) (0) (0)

PE01

(R/W) (R/W) (R/W)

(0) (0) (0)

Read/write

Initial value

15

14

13

12

11

10

9

8

Reload register H

Address:

channel 0 000041H

channel 1 000043H

Read/write

(R/W) (R/W) (R/W) (R/W) (R/W)

(X) (X) (X) (X) (X)

(R/W) (R/W) (R/W)

(X) (X) (X)

Initial value

7

6

5

4

3

2

1

0

Reload register L

Address:

PRLL0, 1

channel 0 000040H

channel 1 000042^H

Read/write

(R/W) (R/W) (R/W) (R/W) (R/W)

(X) (X) (X) (X) (X)

(R/W) (R/W) (R/W)

(X) (X) (X)

Initial value

42

MB90630A Series

(2) Block Diagram

• 8/16-bit PPG (channel 0)

PPG00 output enable

PPG01 output enable

PPG00

PPG01

Peripheral clock divided by 16

Peripheral clock divided by 8

Peripheral clock divided by 4

Peripheral clock divided by 2

Peripheral clock

A/D converter

PPG0

output latch

Invert

Clear

PEN0

S

Q

R

PCNT (Down-counter)

Reload

IRQ

Count clock

selection

channel 1-borrow

Timebase counter output

Main clock divided by 512

L/H selector

L/H select

PRLL0

PRLH0

PRLBH0

PIE 0

PUF0

L-side data bus

H-side data bus

PPGC0

(Operation mode control)

43

MB90630A Series

• 8/16-bit PPG (channel 1)

PPG10 output enable

PPG10

PPG11

Peripheral clock divided by 16

Peripheral clock divided by 8

Peripheral clock divided by 4

Peripheral clock divided by 2

Peripheral clock

PPG11 output enable

UART

PPG1

output latch

Invert

Clear

Count clock

selection

PEN1

S

R

Q

PCNT (Down-counter)

Reload

IRQ

channel 0-borrow

Timebase counter output

Main clock divided by 512

L/H selector

L/H select

PRLL1

PRLH1

PRLBH1

PIE

PUF

L-side data bus

H-side data bus

PPGC1

(Operation mode control)

44

MB90630A Series

7. 8/16-bit Up/Down Counter/Timer

This block is an up/down counter/timer and consists of six event input pins, two 8-bit up/down counters, two 8-

bit reload/compare registers, and their control circuits.

(1) Main Functions

• The 8-bit count register can count in the range 0 to 256D

(or 0 to 65535D in 1 × 16-bit operation mode).

• The count clock selection can select between four different count modes.

Count modes

Timer mode

Up/down counter mode

Phase difference count mode (× 2)

Phase difference count mode (× 8)

• Two different internal count clocks are available in timer mode.

Count clock (at 16 MHz operation)

125 ns (8 MHz: Divide by 2)

1.0 µs (1 MHz: Divide by 8)

• In up/down count mode, you can select which edge to detect on the external pin input signal.

Detected edge

Detect falling edges

Detect rising edges

Detect both rising and falling edges

Edge detection disabled

• Phase difference count mode is suitable for motor encoder counting. By inputting the A, B, and Z phase outputs

from the encoder, a high-precision rotational angle, speed, or similar count can be implemented simply.

• Two different functions can be selected for the ZIN pin.

ZIN pin

Counter clear function

Gate function

• Compare and reload functions are available and can be used either independently or together. A variable-

width up/down count can be performed by activating both functions.

Compare/reload function

Compare function (Output an interrupt when a compare

occurs.)

Compare function (Output an interrupt and clear the

counter when a compare occurs.)

Reload function (Output an interrupt and reload when

an underflow occurs.)

Compare/reload function

(Output an interrupt and clear the counter when a

compare occurs. Output an interrupt and reload when

an underflow occurs.)

Compare/reload disabled

• Whether or not to generate an interrupt when a compare, reload (underflow), or overflow occurs can be set

independently.

• The previous count direction can be determined from the count direction flag.

• An interrupt can be generated when the count direction changes.

45

MB90630A Series

(2) Register Configuration

The 8/16-bit up/down counter/timer has the following registers.

15

8

7

0

UDCR1

RCR1

UDCR0

RCR0

Reversed area

CCRH0

CSR0

CCRL0

Reversed area

CCRH1

CSR1

CCRL1

8 bits

7

6

5

4

3

2

1

0

bit

Up/down count register channel 0

(UDCR0)

Address: 000070H

D07

D06

D05

D04

D03

D02

D01

D00

15

14

13

12

11

10

9

8

bit

Up/down count register channel 1

(UDCR1)

Address: 000071H

D17

D16

D15

D14

D13

D12

D11

D10

7

6

5

4

3

2

1

0

bit

Reload compare register channel 0

(RCR1)

Address: 000072H

D07

D06

D05

D04

D03

D02

D01

D00

15

14

13

12

11

10

9

8

bit

Reload compare register channel 1

(RCR1)

Address: 000073H

D17

D16

D15

D14

D13

D12

D11

D10

7

6

5

4

3

2

1

0

bit

Counter status register channel 0, 1

(CSR0, 1)

Address: 000074H

000078H

CSTR CITE

UDIE CMPF OVFF UDFF UDF1 UDF0

7

6

5

4

3

2

1

0

bit

Address: 000076^H

00007AH

Counter status register channel 0, 1

(CCRL0, 1)

—

CTUT UCRE RLDE UDCC CGSC CGE1 CGE0

14 13 12 11 10

15

9

8

bit

Counter control register channel 0

(CCRH0)

Address: 000077H

M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0

7

6

5

4

3

2

1

0

bit

Counter control register channel 1

(CCRH1)

Address: 00007BH

—

CDCF CFIE CLKS CMS1 CMS0 CES1 CES0

46

MB90630A Series

(3) Block Diagram

• 8/16-bit Up/Down Counter/Timer (channel 0)

Data bus

8 bits

RCR0 (reload/compare regiater 0)

CGE1 CGE0 C/GS

Edge or level detection

CTUT

Reload control

ZIN0

UCRE

RLDE

UDCC

Counter clear

8 bits

UDCR0 (Up/down count regiater 0)

Carry

CMPF

CES1 CES0

CMS1 CMS0

UDFF OVFF

CITE UDIE

Count clock

UDF1 UDF0 CDCF CFIE

AIN0

BIN0

Up/down count

clock selection

Interrupt output

Prescaler

CLKS

CSTR

47

MB90630A Series

• 8/16-bit Up/Down Counter/Timer (channel 1)

Data bus

8 bits

CGE1 CGE0 C/GS

Edge or level detection

RCR1 (reload/compare register 1)

CTUT

UCRE

Reload control

ZIN1

RLDE

UDCC

Counter clear

8 bits

UDCR1 (Up/down count register 1)

CMPF

UDFF OVFF

CMS1 CMS0 CES1 CES0 EN16

Carry

CITE UDIE

Count clock

UDF1 UDF0 CDCF CFIE

Interrupt output

AIN1

BIN1

Up/down count

clock selection

Prescaler

CSTR

CLKS

48

MB90630A Series

8. Clock Output Control Register

The clock output outputs the divided machine clock.

(1) Register Configuration

bit

7

6

5

4

3

2

1

0

Clock control register

Address:

0003EH

—

CKEN FRQ2 FRQ1 FRQ0

CLKR

(R/W)

(0)

(R/W) (R/W) (R/W)

(0) (0) (0)

Read/write

Initial value

(—)

(a) [bit 3] CKEN

CKOT output enable bit

MODE

Operation

0

1

Operate as a standard port.

Operate as the CKOT output.

(b) [bits 2, 1, 0] FRQ2, FRQ1, FRQ0

These bits select the output frequency of the clock.

FRQ2

FRQ1

FRQ0

Output clock

φ/2¹

φ = 16 MHz

125 ns

250 ns

500 ns

1 µs

φ = 8 MHz

250 ns

500 ns

1 µs

φ = 4 MHz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

500 ns

1 µs

φ/2²

φ/2³

2 µs

φ/2⁴

2 µs

4 µs

φ/2⁵

2 µs

4 µs

8 µs

φ/2⁶

4 µs

8 µs

16 µs

32 µs

64 µs

φ/2⁷

8 µs

16 µs

32 µs

φ/2⁸

16 µs

49

MB90630A Series

9. DTP/External Interrupts

The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F²MC-16L

CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the

requests to the F²MC-16L CPU to activate the intelligent I/O service or interrupt processing. Two request levels

(“H” and “L”) are provided for the intelligent I/O service. For external interrupt requests, generation of interrupts

on a rising or falling edge as well as on “H” and “L” levels can be selected, giving a total of four types.

(1) Register Configuration

7

6

5

4

3

2

1

0

bit

Interrupt/DTP enable register

(ENIR)

Address: 000030^H

EN7

EN6

EN5

EN4

EN3

EN2

EN1

EN0

15

14

13

12

11

10

9

8

bit

Interrupt/DTP source register

(EIRR)

Address: 000031H

ER7

ER6

ER5

ER4

ER3

ER2

ER1

ER0

7

6

5

4

3

2

1

0

bit

Request level setting register

(ELVR)

Address: 000032H

LB3

LA3

LB2

LA2

LB1

LA1

LB0

LA0

15

14

13

12

11

10

9

8

bit

Request level setting register

(ELVR)

Address: 000033H

LB7

LA7

LB6

LA6

LB5

LA5

LB4

LA4

(2) Block Diagram

4

8

Interrupt/DTP enable register

Request F/F

4

Gate

Edge detect circuit

Request input

Interrupt/DTP source register

Request level setting register

50

MB90630A Series

10. 16-bit I/O Timer

The 16-bit I/O timer consists of one 16-bit free-run timer, four output compare, and two input capture modules.

Based on the 16-bit free-run timer, these functions can be used to generate two independent waveform outputs

and to measure input pulse widths and external clock periods.

(1) A Summary of Each Function

• 16-bit free-run timer (× 1)

The 16-bit free-run timer consists of a 16-bit up-counter, a control register, and a prescaler. The output of the

timer/counter is used as the base time for the input capture and output compare.

(a) The operating clock for the counter can be selected from four different clocks.

Four internal clocks (φ/4, φ/16, φ/32, φ/64)

(b) Interrupts can be generated when a counter value overflow or compare match with compare register 0 occurs

(the appropriate mode must be set for a compare match).

(c) The counter can be initialized to 0000^Hby a reset, software clear, or compare match with compare register 0.

• Output compare (× 4)

The output compare consists of two 16-bit compare registers, compare output latches, and control registers.

The modules can invert the output level and generate an interrupt when the 16-bit free-run timer value matches

the compare register value.

(a) The four compare registers can be operated independently.

Each compare register has a corresponding output pin and interrupt flag.

(b) The four compare registers can be paired to control the output pins.

Invert the output pins using the four compare registers.

(c) Initial values can be set for the output pins.

(d) An interrupt can be generated when a compare match occurs.

• Input capture (× 2)

The input capture consists of two independent external input pins, their corresponding capture registers, and a

control register. The value of the 16-bit free-run timer can be stored in the capture register and an interrupt

generated when the specified edge is detected on the signal from the external input pin.

(a) The edge to detect on the external input signal is selectable.

Detection of rising edges, falling edges, or either edge can be specified.

(b) The two input capture channels can operate independently.

(c) An interrupt can be generated on detection of the specified edge on the external input signal.

The input capture interrupt can activate the intelligent I/O service.

51

MB90630A Series

(2) Register Configuration for the Entire 16-bit I/O Timer

• 16-bit free-run timer

bit

0

15

Timer data register

000066^H

000068^H

TCDT

Timer control status register

TCCS

OCS0/2

ICS

• 16-bit output compare

bit

15

Compare register channel 0 to 3

000050, 52, 54, 56^H

OCCP0 to 3

Compare control status register

channel 0, 2

000058, 5AH

OCS1/3

• 16-bit input capture

bit

15

Input capture register channel 0, 2

Input capture control status register

000060, 62^H

000064^H

IPCP0 to 1

• Overall Block Diagram of the 16-bit I/O timer

Control logic

Interrupt

16-bit free-run timer

16-bit timer

Clear

Output compare 0

OUT 0

OUT 1

OUT 2

OUT 3

Compare register 0

Output compare 1

Compare register 1

Output compare 2

Compare register 2

Output compare 3

TQ

Compare register 3

Input capture 0

IN 0

IN 1

Capture register 0

Capture register 1

Edge selection

52

MB90630A Series

(3) 16-bit Free-run Timer

The 16-bit free-run timer consists of a 16-bit up-counter and a control status register. The count value of the

timer is used as the base time for the input capture and output compare.

(a) The count clock can be selected from four different clocks.

(b) Interrupts can be generated when a counter value overflow occurs.

(c) Depending on the mode setting, the counter can be initialized when a match occurs with compare register

0 of the output compare.

• Register Configuration

bit

0

15

Timer data register

000066^H

TCDT

Timer/counter control status register

000068^H

TCCS

• Block Diagram

φ

Interrupt request

IVF IVFE STOP MODE CLR CLK1 CLK0

Divider

Comparator 0

Clock

16-bit up-counter

Count value output T15 to T00

53

MB90630A Series

• Register Details

Data Register

bit

15

14

13

12

11

10

9

8

Address: 000067H

T15

T14

T13

T12

T11

T10

T09

T08

Read/write

Initial value

(R/W) (R/W) (R/W) (R/W) (R/W)

(R/W) (R/W) (R/W)

(0)

bit

7

6

5

4

3

2

1

0

Address: 000066H

T06

T05

T04

T03

T02

T01

T00

T07

Read/write

Initial value

(R/W) (R/W) (R/W) (R/W) (R/W)

(0) (0) (0) (0) (0)

(R/W) (R/W) (R/W)

(0) (0) (0)

The count value of the 16-bit free-run timer can be read from this register. The count is cleared to “0000^H” by a

reset. Writing to this register sets the timer value. However, only write to the register when the timer is halted

(STOP = “1”). Always use word access.

The 16-bit free-run timer is initialized by the following.

(a) Reset

(b) The clear bit (CLR) of the control status register

(c) A match between the timer/counter value and compare register 0 of the output compare (if the appropriate

mode is set)

54

MB90630A Series

(4) Output Compare

The output compare consists of 16-bit compare registers, compare output pins, and a control register. The

module can invert the output level and generate an interrupt when the 16-bit free-run timer value matches a

compare register value.

(a) The two compare registers can be operated independently.

The output compare can also be set to control pin output using two compare registers.

(b) The initial value of the output pins can be set.

(c) An interrupt can be generated when a compare match occurs.

• Register Configuration

bit

15

0

Compare registers channel 0 to 3

000050, 52, 54, 56H

OCCP0 to 3

bit

15

0

Compare control status registers

channel 0 to 3

X = 0 to 3

000058, 59, 5A, 5B^H

OCSX

• Block Diagram

16-bit timer/counter value (T15 to T00)

Compare control

OUT0

(OUT2)

TQ

CMOD

TQ

OTEO

Compare regiater 0 (2)

16-bit timer/counter value (T15 to T00)

OUT1

(OUT3)

OTE1

Compare control

Compare regiater 1 (3)

ICP1 ICP0 ICE1 ICE0

Compare 1 interrupt (3)

Compare 0 interrupt (2)

Controller

Control blocks

55

MB90630A Series

(5) Input Capture

The function of this module is to store the value of the 16-bit free-run timer in a register when the specified edge

(rising, falling, or either edge) is detected on the external input signal. The module can also generate an interrupt

on detection of the edge. The input capture contains input capture data registers and a control register. Each

input capture has a corresponding external input pin.

(a) Three different types of edge detection can be selected.

Rising edges (↑), falling edges (↓), or either edge (↑ ↓).

(b) An interrupt can be generated on detection of the specified edge on the external input.

• Register Configuration (for the entire input capture)

bit

15

0

Input capture data register

X = 0 to 1

000060, 62H

IPCX

bit

7

0

Input capture control status register

X = 0 to 1

000064^H

ICSX

• Block Diagram

IN 0

Capture data register 0

Edge detection

EG11 EG10 EG01 EG00

16-bit timer/counter value (T15 to T00)

Capture data register 1

IN 1

Edge detection

ICP1 ICP0 ICE1 ICE0

Interrupt

56

MB90630A Series

• Register Details

Input capture data register

bit

15

14

13

12

11

10

9

8

000060, 62H

CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08

Read/write

Initial value

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

bit

7

6

5

4

3

2

1

0

CP06 CP05 CP04 CP03 CP02 CP01

CP00

CP07

Read/write

Initial value

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

The 16-bit free-run timer value is stored in these registers when the specified edge is detected on the input

waveform from the corresponding external pin. (Always use word access. Writing is prohibited.)

57

MB90630A Series

11. Watchdog Timer

The watchdog timer consists of a 2-bit watchdog counter that uses the carry signal from the 18-bit timebase

counter as its clock source, a control register, and a watchdog reset controller. The following block diagram

shows the structure of both the watchdog timer and timebase timer (see “12. Timebase Timer”).

(1) Block Diagram

WTE

Output enable

WT1

WT0

Reset

control

Selector

2-bit counter

Timebase counter

1

2

1

2¹²

1

2¹³

1

2¹⁴

1

2¹⁵

1

2¹⁶

1

2¹⁷

1

2¹⁸

f/2

.........

Clear

Power-on reset

STOP mode

Clear

control

TBIE

IRQ

TBOF

Selectror

TBR

Clear

I²OS

TBC1

TBC0

1/2 ¹⁶to 1/2 ¹⁸(Timebase division output)

OSC1

OSC0

Oscillation stabilization delay completion signal

Selectror

(2) Register Configuration

bit

7

6

5

4

3

2

1

0

Watchdog timer control register

(WDTC)

Address: 0000A8^H

PONR STBR WRST ERST SRST

WTE

WT1

WT0

58

MB90630A Series

12. Timebase Timer

The timebase timer consists of an 18-bit timebase counter (which divides the system clock) and a control register.

The carry signal of the timebase counter can generate a fixed period interrupt.

All bits of the timebase counter are cleared to zero at power-on, when stop mode is set, or by software (by

writing “0” to the TBR bit). The timebase counter continuously increments while an oscillation is input.

The timebase counter is also used as the clock source for the watchdog timer and as a timer for the oscillation

stabilization delay time.

(1) Block Diagram

See “(1) Block diagram” in “11. Watchdog Timer” for the block diagram of the timebase timer.

(2) Register Configuration

bit

15

14

—

13

—

12

11

10

9

8

Timebase timer control register

(TBTC)

Address: 0000A9^H

Reserved

TBIE

TBCF

TBR

TBC1 TBC0

(3) Register Details

• TBTC (Timebase timer control register)

bit

15

14

—

13

—

12

11

10

9

8

Initial value

X--00000^B

Address: 0000A9^H

Reserved

TBIE

TBCF

TBR

TBC1 TBC0

(R/W) (R/W)

(W)

(R/W) (R/W)

(W)

(a) [bit 15] Reserved

A reserved bit. Always set to “1” when writing data to the register.

(b) [bit 12] TBIE

Interval interrupt enable bit for the timebase timer. The interrupt is enabled when TBIE is “1” and disabled

when TBIE is “0”. Initialized to “0” by a reset. The bit is readable and writable.

(c) [bit 11] TBOF

Interrupt request flag for the timebase timer. An interrupt request is generated if TBCF goes to “1” when

TBIE is “1”. The bit is set to “1” at fixed intervals set by the TBC1 and 0 bits. Clear by writing “0”, transition

to stop or hardware standby mode, or a reset. Writing “1” has no meaning.

Read as “1” by read-modify-write instructions.

(d) [bit 10] TBR

Clears all bits of the timebase counter to “0”. Writing “0” to the TBR bit clears the timebase counter. Writing

“1” to the TBR bit is meaningless. Reading from the TBR bit results in “1”.

(e) [bit 9, 8] TBC1, 0

Set a timebase timer interval. The bits are initialized to “00” by resetting. These bits are readable and writable.

Setting of timebase timer interval

Interval time when base

TBC1

TBC0

frequency is 4 MHz

0

1

0

1

0

1

1.024 ms

4.096 ms

16.384 ms

131.072 ms

59

MB90630A Series

13. External Bus Pin Control Circuit

The external bus pin control circuit controls the external bus pins required to extend the CPU’s address/data

bus outside the device.

(1) Register Configuration

bit

15

14

13

12

11

—

10

—

9

8

Auto-ready function selection register

Address:

0000A5H

ICR1

ICR0 HMR1 HMR0

LMR1 LMR0

ARSR

HACR

EPCR

Read/write

Initial value

(W)

(0)

(W)

(0)

(W)

(1)

(W)

(1)

(—)

(W)

(0)

(W)

(0)

bit

7

6

5

4

3

2

1

0

External address output control register

Address:

0000A6H

E23

E22

E21

E20

E19

E18

E17

E16

(W)

(0)

(W)

(0)

(W)

(0)

(W)

(0)

(W)

(0)

(W)

(0)

(W)

(0)

(W)

(0)

Read/write

Initial value

bit

15

14

13

12

11

10

9

8

Bus control signal selection register

Address:

0000A7H

CKE

RYE

HDE

ICBS HMBS WRE

LMBS

—

Read/write

Initial value

(W)

(0)

(W)

(0)

(W)

(0)

(W)

(0)

(W)

(0)

(W)

(0)

(—)

(1/0)

(2) Block Diagram

P3

P2

P1

P3

P0

P0 data

P0 direction

RB

Data control

Address control

Access control

60

MB90630A Series

4. Low-Power Control Circuits (CPU Intermittent Operation Function, Oscillation Stabilization

Delay Time, and Clock Multiplier Function)

The following operation modes are available: PLL clock mode, PLL sleep mode, timer mode, main clock mode,

main sleep mode, stop mode, and hardware standby mode. Operation modes other than PLL clock mode are

classified as low power consumption modes.

In main clock mode and main sleep mode, the device operates on the main clock only (OSC oscillator clock).

The PLL clock (VCO oscillator clock) is stopped in these modes and the main clock divided by 2 is used as the

operating clock.

In PLL sleep mode and main sleep mode, the CPU’s operating clock only is stopped and other elements continue

to operate.

In timer mode, only the timebase timer operates.

Stop mode and hardware standby mode stop the oscillator. These modes maintain existing data with minimum

power consumption.

The CPU intermittent operation function provides an intermittent clock to the CPU when register, internal

memory, internal resource, or external bus access is performed. This function reduces power consumption by

lowering the CPU execution speed while still providing a high-speed clock to internal resources.

The PLL clock multiplier ratio can be set to 1, 2, 3, or 4 by the CS1, 0 bits.

The WS1, 0 bits set the delay time to wait for the main clock oscillation to stabilize when recovering from stop

mode or hardware standby mode.

(1) Register Configuration

bit

7

6

5

4

3

2

1

0

Low-power consumption mode register

Address:

0000A0H

Reserved

STP

SLP

SPL

RST

CG1

CG0

LPMCR

CKSCR

(W)

(0)

(W)

(0)

(R/W)

(0)

(W)

(1)

(—)

(1)

(R/W) (R/W)

(—)

(0)

Read/write

Initial value

(0)

bit

15

14

13

12

11

10

9

8

Clock select register

Address:

0000A1H

Reserved

MCM

WS1

WS0

MCS

CS1

CS0

Read/write

Initial value

(—)

(1)

(R)

(1)

(R/W) (R/W)

(1) (1)

(—)

(1)

(R/W) (R/W) (R/W)

(1) (0) (0)

61

MB90630A Series

(2) Block Diagram

• Low-Power Consumption Control Circuit and Clock Generator

CKSCR

Main clock

PLL multiplier

MCM

(OSC oscillator)

circuit

CPU clock

MCS

1

2

3

4 1/2

CPU clock

generator

CKSCR

CS1

CPU

clock selector

0/9/17/33

intermittent cycle selection

CS0

LPMCR

CG1

Cycle selection

circuit for the CPU

intermittent

CG0

operation function

Peripheral clock

HST pin

LPMCR

SLP

Peripheral

clock

generator

Standby control

circuit

RST release HSTactivate

STP

Interrupt request

or RST

CKSCR

OSC1

2⁴

Clock input

Timebase timer

2¹²2¹⁴2¹⁶2¹⁹

Oscillation

stabilization

delay time

selector

2¹³

2¹⁵

2¹⁸

Timebase clock

Pin HI-Z

OSC0

LPMCR

SPL

Pin high impedance control circuit

RST pin

LPMCR

RST

Internal reset

generator

Internal RST

To watchdog timer

WDGRST

62

MB90630A Series

• State Transition Diagram for Clock Selection

Power-on

Main→PLLX

MCS=0

MCM=1

CS1/0=XX

Main

(1)

(2)

MCS=1

MCM=1

CS1/0=XX

(6)

(7)

(3)

PLL 1

PLL1→Main

MCS=1

MCM=0

multiplier

MCS=0

MCM=0

CS1/0=00

(4)

(6)

CS1/0=00

(7)

PLL 2

PLL2→Main

MCS=1

MCM=0

CS1/0=01

multiplier

MCS=0

MCM=0

CS1/0=01

(6)

PLL 3

PLL3→Main

MCS=1

MCM=0

CS1/0=10

(5)

multiplier

MCS=0

MCM=0

CS1/0=10

(7)

(6)

PLL 4

PLL4→Main

multiplier

MCS=0

MCM=0

CS1/0=11

MCS=1

MCM=0

CS1/0=11

(6)

(1) MCS bit cleared

(2) PLL clock oscillation stabilization delay complete and CS1/0=“00”

(3) PLL clock oscillation stabilization delay complete and CS1/0=“01”

(4) PLL clock oscillation stabilization delay complete and CS1/0=“10”

(5) PLL clock oscillation stabilization delay complete and CS1/0=“11”

(6) MCS bit set (including a hardware standby or watchdog reset)

(7) PLL clock and main clock synchronized timing

63

MB90630A Series

5. Delayed Interrupt Generation Module

The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to

the F²MC-16L CPU can be generated and cleared by software using this module.

(1) Register Configuration

bit

15

—

14

—

13

—

12

—

11

—

10

—

9

8

Delayed interrupt request register

(DIRR)

Address: 00009FH

—

R0

(2) Register Details

Delayed interrupt request register (DIRR)

15

—

14

—

13

12

11

10

9

8

bit

Initial value

R0

Address: 00009FH

—

- - - - - - - 0 ^B

(R/W)

The DIRR register controls generation and clearing of delayed interrupt requests. Writing “1” to the register

generates a delayed interrupt request. Writing “0” to the register clears the delayed interrupt request. The register

is set to the interrupt cleared state by a reset. Either “0” or “1” can be written to the reserved bits. However,

considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for

register access.

(3) Block Diagram

Delayed interrupt generate/clear decoder

Interrupt latch

64

MB90630A Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = AVSS = 0.0 V)

Value

Symbol

Unit Remarks

Max.

Parameter

Min.

VSS – 0.3

—

V^CC

VSS + 7.0

—

V

Power supply voltage

AVCC*¹

AVRH, AVRL*¹

V

Program voltage

V^PP

VI

V

Input voltage*²

VCC + 0.3

15

V

Output voltage*²

VO

V

“L” level (maximum) output current*³

“L” level (average) output current*⁴

IOL

mA

mW

°C

IOLAV

—

50

“L” level total (maximum) output current ΣI^OL

“L” level total (average) output current*⁵ΣIOLAV

—

100

—

50

“H” level (maximum) output current*³

“H” level (average) output current*⁴

IOH

—

–15

IOHAV

—

–50

“H” level total (maximum) output current ΣI^OH

—

–100

–50

“H” level total (average) output current*⁵

Power consumption

ΣIOHAV

—

P^d

—

+400

+85

Operating temperature

T^A

–40

Storage temperature

T^stg

–55

+150

*1: AV^CC, AVRH, and AVRL must not exceed VCC. Similarly, it must not exceed AVRH and AVRL.

*2: VI and VO must not exceed VCC + 0.3 V.

*3: The maximum output current must not be exceeded at any individual pin.

*4: The average output current is the rating for the current from an individual pin averaged over 100 ms.

*5: The average total output current is the rating for the current from all pins averaged over 100 ms.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

65

MB90630A Series

2. Recommended Operating Conditions

(VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

2.7

Max.

5.5

V

For normal operation

Power supply voltage

V^CC

2.7

5.5

To maintain statuses in stop mode

Other than VIHS

V^IH

0.7 VCC

0.8 VCC

VCC – 0.3

VSS – 0.3

–40

VCC + 0.3

0.3 VCC

0.2 VCC

VSS + 0.3

+85

V

“H” level input voltage

VIHS

V^IHM

VIL

V

Hysteresis inputs

V

Other than VILS

“L” level input voltage

Operating temperature

VILS

V^ILM

TA

V

Hysteresis inputs

V

°C

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the

device’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

66

MB90630A Series

3. DC Characteristics

Parameter

(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit Remarks

name

Min.

Typ.

—

Max.

V^IH

0.7 VCC

0.8 VCC

VCC – 0.3

0.7 VCC

0.8 VCC

VSS – 0.3

VCC + 0.3

VSS + 0.3

V

VCC = +5.0

V±10%

“H” level input voltage

V^IHS

V^IHM

V^IL

—

V

*1

—

VCC = +5.0

V±10%

“L” level input voltage

V^ILS

V^ILM

—

V^CC= +4.5

V±10%

I^OH= –4.0 mA

V^CC– 0.5

V^CC– 0.3

—

V

“H” level output voltage V^OH

“L” level output voltage V^OL

—

V^CC= +2.7 V

I^OH= –1.6 mA

V^CC= +4.5

V±10%

I^OH= –4.0 mA

0.4

VCC = +2.7 V

I^OH= –2.0 mA

—

Pull-up resistor

R^pull

RST

—

22

—

110

80

kΩ

ICC

VCC = +5.0

V±10%

F^C= 16 MHz

60

mA

VCC

I^CCS

I^CC

—

20

15

10

35

40

15

mA

VCC = +3.0

V±10%

F^C= 10 MHz

Power supply current*²

I^CCS

VCC

VCC = +5.0

V±10%

ICCH

—

20

—

µA

Other

than V^CC

and VSS

Input pin capacitance

Input leak current

C^IN

—

10

pF

VCC = 5.5 V

VSS < VI < VCC

P73, 74

P86, 87

I^IL

–10

—

10

µA

Leak current for

open-drain outputs

P50 to

P57

I^leak

—

0.1

*1: Hysteresis input pins: RST, HST

*2: Current values are provisional and are subject to change without notice to allow for improvements to the

characteristics and similar.

67

MB90630A Series

4. AC Characteristics

(1) Clock Timing

• When V^CC= 5.0 V±10%

(V^CC= 4.5 V to +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit

Remarks

name

Min.

3

Max.

16

Clock frequency

Clock cycle time

F^C

t^C

X0, X1

—

MHz

ns

62.5

333

The duty ratio should

ns be in the range 30 to

70%

Input clock pulse width

PWH, PWL

X0

—

10

—

Input clock rise time and

fall time

t^cr, tcf

X0

—

1.5

5

ns

MHz

ns

Internal operating clock

frequency

f^CP

16

Internal operating clock

cycle time

tCP

62.5

333

• When V^CC= 2.7 V (min.)

(V^CC= 4.5 V to +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit

Remarks

name

Min.

3

Max.

10

Clock frequency

Clock cycle time

F^C

X0, X1

—

MHz

ns

tC

100

333

The duty ratio should

ns be in the range 30 to

70%

Input clock pulse width

P^WH, PWL

X0

—

20

—

Input clock rise time and

fall time

t^cr, tcf

X0

—

1.5

100

5

8

ns

MHz

ns

Internal operating clock

frequency

f^CP

Internal operating clock

cycle time

t^CP

333

• Clock Timing

t C

0.8 V CC

0.2 V CC

P WL

P WH

t cf

t cr

68

MB90630A Series

• PLL Operation Assurance Range

Relationship between the internal operating clock frequency and suply voltage

Normal operation range

5.5

4.5

3.3

2.7

PLL operation assurance range

1.5

3

8

16

Internal clock FCP (MHz)

Relationship between the oscillation frequency and internal operating clock frequency

Multiply Multiply

by 4

by 3

16

No multiplier

Multiply

by 2

Multiply by 1

12

9

8

4

3 4

8

16

24

32

Oscillation clock F^C(MHz)

Note: Low voltage operation down to 2.7 V is also assured for the evaluation tools.

The AC characteristics are for the following measurement reference voltages.

• Input Signal Waveform

• Output Signal Waveform

Hysteresis input pins

0.8 V ^CC

Output pins

2.4 V

0.2 V CC

0.8 V

Other than hysteresis or MD input pins

0.7 V ^CC

0.3 V CC

69

MB90630A Series

(2) Clock Output Timing

(V^CC= +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit

Remarks

Parameter

name

Min.

62.5

20

Max.

—

Cycle time

CLK ↑ → CLK↓

t^CYC

ns

V^CC= 5.0

V±10%

CLK

t^CHCL

—

tCYC

tCHCL

2.4 V

CLK

0.8 V

(3) Reset and Hardware Standby Inputs

(V^CC= +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit

Remarks

Parameter

Reset input time

name

Min.

Max.

Machine

cycle

t^RSTL

t^HSTL

RST

4

—

Machine

cycle

Hardware standby input time

HST

4

—

t

RSTL, tHSTL

RST

HST

0.2 V CC

0.2 V ^CC

70

MB90630A Series

(4) Power-on Reset

Parameter

(V^CC= +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Min.

—

Max.

30

Power supply rising time

Power supply cut-off time

t^R

VCC

ms

—

t^OFF

1

—

Note: The above values are the values required for a power-on reset.

t ^R

2.25 V

V ^CC

0.2 V

Abrupt changes in the power supply voltage may cause a power-on reset.

When changeing the power supply voltage during operation, suppress variations in the voltage and

ensure that the voltage rises smoothly, as shown in the following figure. Also, do not use the PLL

clock when varying the voltage. However, the supply voltage can be changed when using the PLL

clock if the voltage drops by less than 1 mV/s.

5.0 V

V CC

The gradient should be no

more than 50 mV/ms.

2.7 V

Holding RAM data

V ^SS

71

MB90630A Series

(5) Bus Timing (Read)

(V^CC= +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Pin name

ALE

Condition

Unit Remarks

Parameter

ALE pulse width

Min.

Max.

t^LHLL

t^AVLL

tCP/2 –20

—

ns

Multiplexed

address

Valid address → ALE ↓ time

ALE ↓ → address valid time

Valid address → RD ↓ time

Valid address→ valid data input

t^CP/2 –25

t^CP/2 –15

t^CP–15

—

Multiplexed

address

t^LLAX

tAVRL

tAVDV

ns

Multiplexed

address

—

Multiplexed

address

5 t^CP/2 –60

—

RD pulse width

tRLRH

tRLDV

tRHDX

tAVDV

tRHLH

tRHAX

t^AVCH

tRLCH

RD

3 tCP/2 –20

—

ns

RD ↓ → valid data input

RD ↑ → data hold time

Valid address → valid data input

RD ↑ → ALE ↑ time

3 tCP/2 –60

D15 to D00

0

—

0

RD, ALE

tCP/2 –15

tCP/2 –10

tCP/2 –20

RD ↑ → address valid time

Valid address → CLK ↑ time

RD ↓ → CLK ↑ time

Address, RD

Address, CLK

RD, CLK

t AVCH

t RLCH

2.4 V

CLK

t AVLL

t LHLL

t LLAX

t RHLH

2.4 V

0.8 V

2.4 V

ALE

RD

t AVRL

t RLRH

2.4 V

0.8 V

t RHAX

2.4 V

0.8 V

2.4 V

0.8 V

A19 to

A16

t RLDV

t AVDV

t ^RHDX

2.4 V

0.8 V

0.7 V CC

0.3 V CC

0.7 V ^CC

0.3 V CC

2.4 V

0.8 V

AD15 to

AD00

Address

Read data

72

MB90630A Series

(6) Bus Timing (Write)

Parameter

(V^CC= +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Min.

Max.

—

Valid address → WR ↓ time

Valid address → RD ↓ time

WR pulse width

tAVWL

tAVRL

tWLWH

tRLRH

A19 to A00

A23 to A00

WR

tCP–15

ns

tCP/2 –15

3 tCP/2 –20

—

RD pulse width

RD

—

Valid data output → WR ↑

time

t^DVWH

D15 to D00

3 tCP/2 –20

—

ns

—

WR ↑ → data hold time

WR ↑ → address valid time

WR ↑ → ALE ↑ time

tWHDX

tWHAX

tWHLH

D15 to D00

A19 to A00

WR, ALE

20

—

ns

tCP/2 –10

tCP/2 –15

WRL, WRH,

CLK

WR ↓ → CLK ↑ time

tWLCH

t^CP/2 –20

—

ns

t WLCH

2.4 V

CLK

ALE

t WHLH

2.4 V

t AVWL

t WLWH

2.4 V

WR

(WRL, WRH)

0.8 V

t WHAX

2.4 V

0.8 V

2.4 V

0.8 V

A19 to

A16

t DVWH

t WHDX

2.4 V

0.8 V

2.4 V

0.8 V

AD15 to

AD00

Address

Write data

0.8 V

73

MB90630A Series

(7) Ready Input Timing

(V^CC= +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min.

45

70

0

Max.

—

V^CC= 5.0 V ±10%

V^CC= 3.0 V ±10%

—

ns

RDY setup time

RDY hold time

t^RYHS

t^RYHH

RDY

—

Note: Use the auto-ready function if the RDY setup time is too short.

2.4 V

CLK

ALE

RD/WR

t RYHS

RDY (When one wait

states are inserted)

0.2 VCC

t RYHS

t RYHH

RDY (When wait states

are not inserted)

0.8 V^CC

0.8 VCC

74

MB90630A Series

(8) Hold Timing

Parameter

(V^CC= +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol Pin name

Condition

Unit

Remarks

Min.

30

Max.

tCP

Pin floating → HAK ↓ time

HAK ↑ → pin valid time

tXHAL

tHAHV

HAK

—

ns

tCP

2 tCP

Note: After reading HRQ, more than one cycle is required before changing HAK.

HRQ

HAK

t XHAL

t HAHV

High impedance

75

MB90630A Series

(9) UART Timing

(V^CC= +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

name

Symbol

Condition

Unit

Remarks

Parameter

Min.

Max.

Serial clock cycle time

t^SCYC

—

8 t^CP

—

ns

VCC = +5.0 V ±10% –80

V^CC= +3.0 V ±10% –120

VCC = +5.0 V ±10% 100

V^CC= +3.0 V ±10% 200

80

120

—

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SLOV

t^IVSH

t^SHIX

C^L= 80 pF+1TTL

for the internal

shift clock mode

output pin

—

VCC = +5.0 V ±10%

60

—

SCK ↑ → valid SIN hold time

V^CC= +3.0 V ±10% 120

—

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

t^SLSH

—

4 tCP

—

VCC = +5.0 V ±10%

V^CC= +3.0 V ±10%

VCC = +5.0 V ±10%

150

200

—

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SLOV

t^IVSH

t^SHIX

C^L= 80 pF+1TTL

for the external

shift clock mode

output pin

—

60

V^CC= +3.0 V ±10% 120

VCC = +5.0 V ±10% 60

V^CC= +3.0 V ±10% 120

—

SCK ↑ → valid SIN hold time

—

Notes: • These are the AC characteristics for CLK synchronous mode.

• C^Lis the load capacitance connected to the pin at testing.

• tCP is the machine cycle period (unit: ns).

76

MB90630A Series

• Internal Shift Clock Mode

tSCYC

2.4 V

SCK

0.8 V

tSLOV

2.4 V

0.8 V

SOT

tIVSH

tSHIX

0.8 V ^CC

0.2 V ^CC

0.8 V CC

0.2 V CC

SIN

• External Shift Clock Mode

tSLSH

tSHSL

0.8 V ^CC

0.8 V CC

SCK

SOT

0.2 V CC

tSLOV

2.4 V

0.8 V

tIVSH

tSHIX

0.8 V CC

0.2 V ^CC

0.8 V CC

0.2 V CC

SIN

77

MB90630A Series

(10) I/O Extended Serial Timing

(V^CC= +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

t^SCYC

Condition

Unit

Remarks

Parameter

name

Min.

8 tCP

—

Max.

—

Serial clock cycle time

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

—

ns

V^CC= +5.0 V ±10%

V^CC= +3.0 V ±10%

—

80

CL = 80 pF+1TTL

for the internal

shift clock mode

output pin

t^SLOV

—

160

—

tIVSH

—

tCP

SCK ↑ → valid SIN hold

t^SHIX

—

tCP

—

ns

time

V^CC= +5.0 V ±10%

V^CC= +3.0 V ±10%

V^CC= +5.0 V ±10%

VCC = +3.0 V ±10%

—

230

460

230

460

2 tCP

tCP

—

ns

Serial clock “H” pulse

width

tSHSL

—

C^L= 80 pF+1TTL

for the external

shift clock mode

output pin

Serial clock “L” pulse

width

t^SLSH

SCK ↓ → SOT delay time

Valid SIN →SCK ↑

tSLOV

—

Max. 2 MHz

t^IVSH

—

SCK ↑ → valid SIN hold

time

t^SHIX

—

2 tCP

—

ns

Notes: • These are the AC characteristics for CLK synchronous mode.

• C^Lis the load capacitance connected to the pin at testing.

• tCP is the machine cycle period (unit: ns).

• The values in the table are target values.

78

MB90630A Series

• Internal Shift Clock Mode

tSCYC

2.4 V

SCK

0.8 V

tSLOV

2.4 V

0.8 V

SOT

tIVSH

tSHIX

0.8 V ^CC

0.2 V ^CC

0.8 V CC

0.2 V CC

SIN

• External Shift Clock Mode

tSLSH

tSHSL

0.8 V ^CC

0.8 V CC

SCK

SOT

0.2 V CC

tSLOV

2.4 V

0.8 V

tIVSH

tSHIX

0.8 V CC

0.2 V ^CC

0.8 V CC

0.2 V CC

SIN

79

MB90630A Series

(11) Timer Output Timing

(V^CC= +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min.

30

Max.

—

OUT0 to OUT3

VCC = +5.0 V ±10%

ns

SCK ↑ → T^OUTchange

t^TO

time

PPG00 to PPG11 V^CC= +3.0 V ±10%

80

—

2.4 V

CLK

OUT0 to OUT3

2.4 V

0.8 V

PPG0 to PPG1

t TO

(12) Trigger Input Timing

(V^CC= +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Pin name

ATG,

IRQ0 to IRQ7

IN0, IN1

Condition

Unit Remarks

Parameter

Min.

Max.

t^TRGH

tTRGL

Input pulse width

—

5 t^CP

—

ns

0.8 V CC

0.2 V CC

ATG,

IRQ0 to IRQ7

IN0, IN1

0.2 V CC

t TRGL

t TRGH

80

MB90630A Series

(13) Up/down Counter

(V^CC= +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min.

Max.

AIN input “1” pulse

width

t^AHL

t^ALL

t^BHL

t^BLL

8 t^CYL

—

ns

AIN input “0” pulse

width

8 tCYL

—

BIN input “1” pulse

width

BIN input “0” pulse

width

AIN0, AIN1

BIN0, BIN1

AIN ↑ → BIN ↑ time

BIN ↑ → AIN ↓ time

AIN ↓ → BIN ↓ time

BIN ↓ → AIN ↑ time

BIN ↑ → AIN ↑ time

AIN ↑ → BIN ↓ time

BIN ↓ → AIN ↓ time

AIN ↓ → BIN ↑ time

t^AUBU

tBUAD

t^ADBD

tBDAU

tBUAU

t^AUBD

tBDAD

tADBU

4 tCYL

—

ns

—

ZIN input “1” pulse

width

t^ZHL

t^ZLL

4 tCYL

—

ns

ZIN0, ZIN1

ZIN input “0” pulse

width

81

MB90630A Series

t AHL

t ALL

0.8 V^CC

0.8 VCC

AIN

BIN

0.2 VCC

t AUBU

t BUAD

t ADBD

t BDAU

0.8 VCC

0.2 VCC

t BHL

t BLL

t BHL

t BLL

0.8 VCC

BIN

0.2 VCC

t BUAU

t AUBD

t BDAD

t ADBU

0.8 VCC

0.2 VCC

t AHL

t ALL

0.8 VCC

t ZHL

ZIN

t ZLL

0.2 VCC

82

MB90630A Series

5. A/D Converter Electrical Characteristics

(AVCC = VCC = +2.7 V to +5.5 V, AVSS = VSS = 0.0 V, 2.7 V ≤ AVRH – AVRL, TA = –40°C to +85°C)

Value

Symbol

Pin name

Unit

Parameter

Min.

Typ.

Max.

Resolution

—

10

bit

LSB

µs

Total error

—

±3.0

Linearity error

—

±2.0

Differential linearity error

Zero transition error

Full scale transition error

—

±1.5

V^OT

V^FST

AN0 to AN7

–1.5

+0.5

+2.5

AVRH –3.5

AVRL –1.5

AVRH +0.5

5.12*¹

—

5

—

Conversion time

—

8.12*²

—

µs

Analog port input current

Analog input voltage

I^AIN

V^AIN

—

I^A

AN0 to AN7

AVRH

—

10

µA

AVRL

AVRH

V

AVRL + 2.7

AV^CC

V

Reference voltage

AVRL

0

AVRH – 2.7

V

AVCC

—

5*³

—

5*³

4

mA

µA

Power supply current

I^AH

I^R

AVCC

—

200

—

AVRH

µA

Reference voltage supply

current

I^RH

—

AVRH

µA

Variation between channels

AN0 to AN7

LSB

*1: For V^CC= +5.0 V ±10% and a 16 MHz machine clock

*2: For VCC = +3.0 V ±10% and an 8 MHz machine clock

*3: The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVRH = +5.0 V).

Notes: • The error increases proportionally as |AVRH – AVRL| decreases.

• The output impedance of the external circuits connected to the analog inputs should be in the following

range.

Output impedance of external circuit < approx. 10 kΩ

• If the output impedance of the external circuit is too high, the sampling time for the analog voltage may

be too short. (Sampling time = 3.8 µs (corresponds to 16 MHz internal operation if the multiplier is 4.))

• Model of the Analog Input Circuit

Sample and hold circuit

C0

Analog input

Comparator

R^ON1

RON2

RON3

RON4

C1

RON1 = 1.5 kΩ (approx.) (VCC = 5.0 V)

R^ON2= 0.5 kΩ (approx.) (VCC = 5.0 V)

R^ON3= 0.5 kΩ (approx.) (VCC = 5.0 V)

R^ON4= 0.5 kΩ (approx.) (VCC = 5.0 V)

C⁰= 60 pF (approx.)

C¹= 4 pF (approx.)

Note: The above values are for reference only.

83

MB90630A Series

6. A/D Converter Glossary

• Resolution

The change in analog voltage that can be recognized by the A/D converter.

If the resolution is 10 bits, the analog voltage can be resolved into 2¹⁰= 1024 steps.

• Total error

The deviation between the actual and logic value attributable to offset error, gain error, non-linearity error, and

noise.

• Linearity error

The deviation between the actual conversion characteristic of the device and the line linking the zero transition

point (00 0000 0000 ↔ 00 0000 0001) and the full scale transition point (11 1111 1110 ↔ 11 1111 1111).

• Differential linearity error

The variation from the ideal input voltage required to change the output code by 1 LSB.

Digital output

11 1111 1111

11 1111 1110

•

(1LSB × N + V OT)

Linearity error

00 0000 0010

00 0000 0001

00 0000 0000

Analog input

VOT

VNT V (N+1)T

VFST

V FST – V OT

1LSB =

1022

V NT – (1LSB × N + V OT )

1LSB

Linearity error =

[LSB]

V(N+1)T – V NT

– 1 [LSB]

Differential linearity error =

1LSB

84

MB90630A Series

7. 8-bit D/A Converter Electrical Characteristics

(VCC = 2.7 to 5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

Value

Symbol Pin name

Unit

Remarks

Parameter

Resolution

Min.

—

Typ.

8

Max.

8

—

bit

LSB

%

Differential linearity error

Absolute accuracy

–0.9

—

0.9

1.2

—

The load

Conversion time

—

I^D

—

V^SS+ 1.7

—

10

—

20

VCC

1.5

µS capacitance = 20

pF

Analog reference power

supply voltage

DVRH

V

DVSS = VSS = 0.0 V

Current

mA consumption at

conversion

Reference power supply

current (when operating)

1.0

Current

µA consumption

when stopped

Reference power supply

current (when stopped)

I^DH

—

DVRH

DA0

—

10

—

Analog output impedance

28

kΩ

Note: DV^SSmust be connected at VSS = 0.0 V.

85

MB90630A Series

■ EXAMPLE CHARACTERISTICS

(1) “H” Level Output Voltage

(2) “L” Level Output Voltage

VOL – IOL

V OL (V)

VOH – IOH

VOH (V)

1.0

V^CC= +2.7 V

V^CC= +3.0 V

V^CC= +2.7 V

V^CC= +3.0 V

0.9

TA = +25°C

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V^CC= +3.5 V

V^CC= +4.0 V

V^CC= +4.5 V

V^CC= +5.0 V

V^CC= +3.5 V

V^CC= +4.0 V

V^CC= +4.5 V

V^CC= +5.0 V

2

4

6

8

–2

–4

–6

–8

I^OH(mA)

I^OL(mA)

(3) “H” Level Input Voltage/“L” Level Input Voltage

(CMOS Input)

(4) “H”LevelInputVoltage/“L”LevelInputVoltage

(Hysteresis Input)

V^IN– VCC

V^IN(V)

5.0

TA = +25°C

V^IN– VCC

4.5

V^IN(V)

4.0

5.0

TA = +25°C

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

VIHS

VILS

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2

3

4

5

6

V^CC(V)

VIHS : Threshold when input voltage in hysteresis

characteristics is set to “H” level

2

3

4

5

6

V^CC(V)

V^ILS: Threshold when input voltage in hysteresis

characteristics is set to “L” level

86

MB90630A Series

(5) Power Supply Current (f^CP= Internal Operating Clock Frequency)

ICC (mA)

70

65

60

55

50

45

40

35

30

25

20

15

10

5

ICC–VCC

ICCS (mA)

ICCS–VCC

15

14

13

12

11

10

9

8

7

6

5

TA = +25°C

f^cp= 16 MHz

f^cp= 12.5 MHz

f^cp= 8 MHz

f^cp= 4 MHz

f^cp= 8 MHz

f^cp= 4 MHz

4

3

2

1

0

3.0

4.0

5.0

6.0

V^CC(V)

3.0

4.0

5.0

6.0

V^CC(V)

I^A(mA)

6.0

IA–AVCC

I^R(mA)

0.30

IR–AVR

TA = +25°C

f^CP= 16 MHz

TA = +25°C

fCP = 16 MHz

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

0.20

0.10

0

3.0

4.0

5.0

6.0

AV^CC(V)

3.0

4.0

5.0

6.0

AVR (V)

(5) Pull-up Resistance

R–V^CC

R (kΩ)

1000

TA = +25°C

100

10

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

V^CC(V)

87

MB90630A Series

■ INSTRUCTIONS (340 INSTRUCTIONS)

Table 1 Explanation of Items in Tables of Instructions

Item

Meaning

Mnemonic

Upper-case letters and symbols: Represented as they appear in assembler.

Lower-case letters:

Replaced when described in assembler.

Numbers after lower-case letters:Indicate the bit width within the instruction.

#

~

Indicates the number of bytes.

Indicates the number of cycles.

m: When branching

n : When not branching

See Table 4 for details about meanings of other letters in items.

RG

B

Indicates the number of accesses to the register during execution of the instruction.

It is used calculate a correction value for intermittent operation of CPU.

Indicates the correction value for calculating the number of actual cycles during execution of the

instruction. (Table 5)

The number of actual cycles during execution of the instruction is the correction value summed

with the value in the “~” column.

Operation

LH

Indicates the operation of instruction.

Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.

Z : Transfers “0”.

X : Extends with a sign before transferring.

– : Transfers nothing.

AH

Indicates special operations involving the upper 16 bits in the accumulator.

* : Transfers from AL to AH.

– : No transfer.

Z : Transfers 00^Hto AH.

X : Transfers 00H or FFH to AH by signing and extending AL.

I

S

Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),

N (negative), Z (zero), V (overflow), and C (carry).

* : Changes due to execution of instruction.

– : No change.

S : Set by execution of instruction.

R : Reset by execution of instruction.

T

N

Z

V

C

RMW

Indicates whether the instruction is a read-modify-write instruction. (a single instruction that

reads data from memory, etc., processes the data, and then writes the result to memory.)

* : Instruction is a read-modify-write instruction.

– : Instruction is not a read-modify-write instruction.

Note: A read-modify-write instruction cannot be used on addresses that have different

meanings depending on whether they are read or written.

88

MB90630A Series

Table 2 Explanation of Symbols in Tables of Instructions

Meaning

Symbol

A

32-bit accumulator

The bit length varies according to the instruction.

Byte : Lower 8 bits of AL

Word : 16 bits of AL

Long : 32 bits of AL:AH

AH

AL

Upper 16 bits of A

Lower 16 bits of A

SP

PC

Stack pointer (USP or SSP)

Program counter

PCB

DTB

ADB

SSB

USB

SPB

DPR

brg1

brg2

Ri

Program bank register

Data bank register

Additional data bank register

System stack bank register

User stack bank register

Current stack bank register (SSB or USB)

Direct page register

DTB, ADB, SSB, USB, DPR, PCB, SPB

DTB, ADB, SSB, USB, DPR, SPB

R0, R1, R2, R3, R4, R5, R6, R7

RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

RW0, RW1, RW2, RW3

RWi

RWj

RLi

RL0, RL1, RL2, RL3

dir

Compact direct addressing

addr16

addr24

ad24 0 to 15

ad24 16 to 23

Direct addressing

Physical direct addressing

Bit 0 to bit 15 of addr24

Bit 16 to bit 23 of addr24

io

I/O area (000000^Hto 0000FFH)

imm4

imm8

4-bit immediate data

8-bit immediate data

imm16

imm32

ext (imm8)

16-bit immediate data

32-bit immediate data

16-bit data signed and extended from 8-bit immediate data

disp8

disp16

8-bit displacement

16-bit displacement

bp

Bit offset

vct4

vct8

Vector number (0 to 15)

Vector number (0 to 255)

( )b

Bit address

(Continued)

89

MB90630A Series

(Continued)

Symbol

Meaning

rel

Branch specification relative to PC

ear

eam

Effective addressing (codes 00 to 07)

Effective addressing (codes 08 to 1F)

rlst

Register list

Table 3 Effective Address Fields

Address format

Number of bytes in address

extension *

Code

Notation

00

01

02

03

04

05

06

07

R0

RW0

RW1

RW2

RW3

RW4

RW5

RW6

RW7

RL0 Register direct

(RL0)

RL1 “ea” corresponds to byte, word, and

(RL1) long-word types, starting from the

RL2 left

(RL2)

RL3

R1

R2

R3

R4

R5

R6

R7

—

(RL3)

08

09

0A

0B

@RW0

Register indirect

@RW1

@RW2

@RW3

0

0C

0D

0E

0F

@RW0 +

@RW1 +

@RW2 +

@RW3 +

Register indirect with post-increment

10

11

12

13

14

15

16

17

@RW0 + disp8

@RW1 + disp8

@RW2 + disp8

@RW3 + disp8

@RW4 + disp8

@RW5 + disp8

@RW6 + disp8

@RW7 + disp8

Register indirect with 8-bit

displacement

1

2

18

19

1A

1B

@RW0 + disp16

@RW1 + disp16

@RW2 + disp16

@RW3 + disp16

Register indirect with 16-bit

displacement

1C

1D

1E

1F

@RW0 + RW7

@RW1 + RW7

@PC + disp16

addr16

Register indirect with index

PC indirect with 16-bit displacement

Direct address

0

2

Note: The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)

column in the tables of instructions.

90

MB90630A Series

Table 4 Number of Execution Cycles for Each Type of Addressing

(a)

Number of register

accesses for each type of

addressing

Code

Operand

Number of execution cycles

for each type of addressing

Ri

RWi

RLi

00 to 07

Listed in tables of instructions Listed in tables of instructions

08 to 0B

0C to 0F

10 to 17

18 to 1B

@RWj

2

4

2

1

2

1

@RWj +

@RWi + disp8

@RWj + disp16

1C

1D

1E

1F

@RW0 + RW7

@RW1 + RW7

@PC + disp16

addr16

4

2

1

2

0

Note: “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.

Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles

(b) byte

(c) word

(d) long

Number

Operand

Number

of cycles

Number

of cycles

Number

of cycles

of

access

Internal register

+0

1

+0

1

+0

2

Internal memory even address

Internal memory odd address

+0

1

+0

+2

1

2

+0

+4

2

4

Even address on external data bus (16 bits)

Odd address on external data bus (16 bits)

+1

1

+1

+4

1

2

+2

+8

2

4

External data bus (8 bits)

+1

1

+4

2

+8

4

Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)

in the tables of instructions.

• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready

input and automatic ready.

Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles

Instruction

Internal memory

Byte boundary

Word boundary

—

+3

+2

+3

—

External data bus (16 bits)

External data bus (8 bits)

Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready

input and automatic ready.

• Because instruction execution is not slowed down by all program fetches in actuality, these correction

values should be used for “worst case” calculations.

91

MB90630A Series

Table 7 Transfer Instructions (Byte) [41 Instructions]

R

G

L

A

RM

W

Mnemonic

#

~

B

Operation

I

S

T N Z V C

H H

MOV

A, dir

A, addr16

A, Ri

A, ear

A, eam

A, io

A, #imm8

A, @A

A, @RLi+disp8

2

3

1

2

3

4

2

0

1

(b) byte (A) ← (dir)

(b) byte (A) ← (addr16)

Z

*

–

*

–

*

–

0

byte (A) ← (Ri)

byte (A) ← (ear)

2+ 3+ (a) 0

(b) byte (A) ← (eam)

(b) byte (A) ← (io)

2

3

1

3

2

3

10

1

0

2

0

byte (A) ← imm8

(b) byte (A) ← ((A))

(b) byte (A) ←

MOVN A, #imm4

0

((RLi)+disp8)

R

byte (A) ← imm4

MOVX A, dir

MOVX A, addr16

MOVX A, Ri

MOVX A, ear

MOVX A, eam

MOVX A, io

MOVX A, #imm8

MOVX A, @A

MOVX A,@RWi+disp8

MOVX A, @RLi+disp8

2

3

2

3

4

2

0

1

(b)

X

*

–

*

–

*

–

(b) byte (A) ← (dir)

0

byte (A) ← (addr16)

byte (A) ← (Ri)

(b) byte (A) ← (ear)

(b) byte (A) ← (eam)

2+ 3+ (a) 0

2

3

2

3

5

10

0

1

2

0

byte (A) ← (io)

(b) byte (A) ← imm8

(b) byte (A) ← ((A))

(b) byte (A) ←

((RWi)+disp8)

MOV

dir, A

addr16, A

Ri, A

ear, A

eam, A

io, A

@RLi+disp8, A

Ri, ear

Ri, eam

ear, Ri

eam, Ri

Ri, #imm8

io, #imm8

dir, #imm8

ear, #imm8

eam, #imm8

@AL, AH

2

3

1

2

3

4

2

0

1

(b) byte (A) ←

(b) ((RLi)+disp8)

0

–

*

–

*

–

*

–

*

–

*

–

0

byte (dir) ← (A)

2+ 3+ (a) 0

(b) byte (addr16) ← (A)

(b) byte (Ri) ← (A)

(b) byte (ear) ← (A)

2

3

2

3

10

3

0

2

0

byte (eam) ← (A)

2+ 4+ (a) 1

2

2+ 5+ (a) 1

2

3

(b) byte (io) ← (A)

4

2

0

byte ((RLi) +disp8) ←

(b) (A)

2

5

2

1

0

1

0

byte (Ri) ← (ear)

(b) byte (Ri) ← (eam)

(b) byte (ear) ← (Ri)

0

byte (eam) ← (Ri)

3+ 4+ (a) 0

2

(b) byte (Ri) ← imm8

(b) byte (io) ← imm8

byte (dir) ← imm8

3

0

/MOV @A, T

byte (ear) ← imm8

byte (eam) ← imm8

2+ 5+ (a) 0 2× (b) byte ((A)) ← (AH)

XCH

A, ear

2

4

2

0

Z

–

A, eam

Ri, ear

Ri, eam

2

7

4

0

2+ 9+ (a) 2 2× (b)

byte (A) ↔ (ear)

byte (A) ↔ (eam)

byte (Ri) ↔ (ear)

byte (Ri) ↔ (eam)

Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

92

MB90630A Series

Table 8 Transfer Instructions (Word/Long Word) [38 Instructions]

R

G

L

A

RM

W

Mnemonic

MOVW A, dir

MOVW A, addr16

MOVW A, SP

MOVW A, RWi

MOVW A, ear

MOVW A, eam

MOVW A, io

MOVW A, @A

#

~

B

Operation

I

S

T N Z V C

H H

2

3

1

2

3

4

1

2

0

1

(c) word (A) ← (dir)

(c) word (A) ← (addr16)

0

(c) word (A) ← (eam)

(c) word (A) ← (io)

(c) word (A) ← ((A))

–

*

–

*

–

*

–

word (A) ← (SP)

word (A) ← (RWi)

word (A) ← (ear)

2+ 3+ (a) 0

2

3

2

3

2

5

10

0

1

2

MOVW A, #imm16

MOVW A, @RWi+disp8

MOVW A, @RLi+disp8

0

word (A) ← imm16

(c) word (A) ← ((RWi)

(c) +disp8)

word (A) ← ((RLi)

(c) +disp8)

(c)

0

(c) word (RWi) ← (A)

(c) word (ear) ← (A)

(c) word (eam) ← (A)

(c) word (io) ← (A)

(0) word ((RWi) +disp8) ←

(c) (A)

MOVW dir, A

MOVW addr16, A

MOVW SP, A

MOVW RWi, A

MOVW ear, A

MOVW eam, A

MOVW io, A

MOVW @RWi+disp8, A

MOVW @RLi+disp8, A

MOVW RWi, ear

MOVW RWi, eam

MOVW ear, RWi

MOVW eam, RWi

MOVW RWi, #imm16

MOVW io, #imm16

MOVW ear, #imm16

MOVW eam, #imm16

2

3

1

2

3

4

1

2

0

1

–

*

–

*

–

*

–

*

–

word (dir) ← (A)

word (addr16) ← (A)

word (SP) ← (A)

2+ 3+ (a) 0

2

3

2

3

5

10

3

0

1

2

2+ 4+ (a) 1

2

4

2

0

word ((RLi) +disp8) ←

2+ 5+ (a) 1

(c) (A)

0

(c) word (RWi) ← (eam)

0

(c) word (eam) ← (RWi)

word (RWi) ← imm16

(c) word (io) ← imm16

word (ear) ← imm16

word (eam) ← imm16

0

3

4

2

5

2

1

0

1

word (RWi) ← (ear)

word (ear) ← (RWi)

4+ 4+ (a) 0

MOVW AL, AH

/MOVW @A, T

2

3

0

–

*

–

XCHW A, ear

2

4

2

–

XCHW A, eam

XCHW RWi, ear

XCHW RWi, eam

2+ 5+ (a) 0 2× (c) word ((A)) ← (AH)

2

7

4

0

2+ 9+ (a) 2 2× (c)

word (A) ↔ (ear)

word (A) ↔ (eam)

word (RWi) ↔ (ear)

word (RWi) ↔ (eam)

MOVL A, ear

MOVL A, eam

MOVL A, #imm32

2

4

2

0

long (A) ← (ear)

–

*

–

2+ 5+ (a) 0

5

(d) long (A) ← (eam)

0

3

0

long (A) ← imm32

MOVL ear, A

MOVL eam, A

2

4

2

0

long (ear) ← (A)

–

*

–

2+ 5+ (a) 0

(d) long (eam) ← (A)

Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

93

MB90630A Series

Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]

R

G

L

A

RM

W

Mnemonic

ADD

#

~

B

Operation

I

S

T N Z V C

H H

2

5

3

0

1

0

byte (A) ← (A) +imm8

Z

–

Z

–

Z

–

*

–

*

–

*

A,#imm8

ADD

ADDC

(b) byte (A) ← (A) +(dir)

byte (A) ← (A) +(ear)

(b) byte (A) ← (A) +(eam)

byte (ear) ← (ear) + (A)

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) + (A)

A, dir

A, ear

A, eam

ear, A

eam, A

A

0

2+ 4+ (a) 0

2

3

2

0

1

2

3

0

1

0

byte (A) ← (AH) + (AL) + (C)

byte (A) ← (A) + (ear) + (C)

ADDC A, ear

ADDC A, eam

ADDDC A

2+ 4+ (a) 0

(b) byte (A) ← (A) + (eam) + (C)

0

1

2

3

2

5

3

0

1

byte (A) ← (AH) + (AL) + (C)

(decimal)

SUB

A,

(b) byte (A) ← (A) –imm8

byte (A) ← (A) – (dir)

(b) byte (A) ← (A) – (ear)

byte (A) ← (A) – (eam)

2+ 5+ (a) 0 2× (b) byte (ear) ← (ear) – (A)

#imm8

SUB

SUBC

0

A, dir

A, ear

A, eam

ear, A

eam, A

A

2+ 4+ (a) 0

2

3

2

0

1

2

3

0

1

0

byte (eam) ← (eam) – (A)

byte (A) ← (AH) – (AL) – (C)

–

2+ 4+ (a) 0

(b) byte (A) ← (A) – (ear) – (C)

0

SUBC A, ear

SUBC A, eam

SUBDC A

1

3

0

byte (A) ← (A) – (eam) – (C)

byte (A) ← (AH) – (AL) – (C)

(decimal)

ADDW A

ADDW A, ear

ADDW A, eam

ADDW

#imm16

ADDW ear, A

ADDW eam, A

ADDCWA, ear

ADDCWA, eam

SUBW A

SUBW A, ear

SUBW A, eam

SUBW

#imm16

SUBW ear, A

SUBW eam, A

SUBCW A, ear

SUBCW A, eam

1

2

3

0

1

0

word (A) ← (AH) + (AL)

word (A) ← (A) +(ear)

–

*

–

*

–

*

2+ 4+ (a) 0

3

2

(c) word (A) ← (A) +(eam)

0

A,

2

3

0

2

word (A) ← (A) +imm16

word (ear) ← (ear) + (A)

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) + (A)

word (A) ← (A) + (ear) + (C)

(c) word (A) ← (A) + (eam) + (C)

2

3

1

0

2+ 4+ (a) 0

1

2

3

0

1

0

word (A) ← (AH) – (AL)

word (A) ← (A) – (ear)

2+ 4+ (a) 0

3

2

(c) word (A) ← (A) – (eam)

0

2

3

0

2

word (A) ← (A) –imm16

word (ear) ← (ear) – (A)

A,

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) – (A)

word (A) ← (A) – (ear) – (C)

(c) word (A) ← (A) – (eam) – (C)

2

3

1

0

–

2+ 4+ (a) 0

ADDL A, ear

ADDL A, eam

2

6

2

0

long (A) ← (A) + (ear)

–

*

–

2+ 7+ (a) 0

5

2

2+ 7+ (a) 0

5

(d) long (A) ← (A) + (eam)

0

ADDL

A,

4

6

0

2

long (A) ← (A) +imm32

long (A) ← (A) – (ear)

#imm32

SUBL A, ear

SUBL A, eam

(d) long (A) ← (A) – (eam)

long (A) ← (A) –imm32

4

0

SUBL

A,

#imm32

Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

94

MB90630A Series

Table 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]

R

G

L

H

A

H

RM

W

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C

INC

ear

eam

2

0

byte (ear) ← (ear) +1

–

*

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) +1

DEC

ear

eam

2

3

2

0

byte (ear) ← (ear) –1

–

*

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) –1

INCW ear

INCW eam

2

3

2

0

word (ear) ← (ear) +1

–

*

–

*

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) +1

DECW ear

DECW eam

2

3

2

0

word (ear) ← (ear) –1

–

*

–

*

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) –1

INCL ear

INCL eam

2

7

4

0

long (ear) ← (ear) +1

–

*

–

*

2+ 9+ (a) 0 2× (d) long (eam) ← (eam) +1

DECL ear

DECL eam

2

7

4

0

long (ear) ← (ear) –1

–

*

–

*

2+ 9+ (a) 0 2× (d) long (eam) ← (eam) –1

Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 11 Compare Instructions (Byte/Word/Long Word) [11 Instructions]

R

G

L

H

A

H

RM

W

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C

CMP

A

1

2

1

2

0

1

0

byte (AH) – (AL)

byte (A) ← (ear)

–

*

–

CMP

A, ear

A, eam

A, #imm8

2+ 3+ (a) 0

2

(b) byte (A) ← (eam)

0

2

0

byte (A) ← imm8

CMPW A

1

2

1

2

0

1

0

word (AH) – (AL)

word (A) ← (ear)

–

*

–

CMPW A, ear

CMPW A, eam

CMPW A, #imm16

2+ 3+ (a) 0

3

(c) word (A) ← (eam)

0

2

0

word (A) ← imm16

CMPL A, ear

CMPL A, eam

CMPL A, #imm32

2

6

2

0

word (A) ← (ear)

–

*

–

2+ 7+ (a) 0

5

(d) word (A) ← (eam)

word (A) ← imm32

3

0

Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

95

MB90630A Series

Table 12 Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]

R

G

L

A

H

RM

W

Mnemonic

#

1

~

B

Operation

I

S

–

T

–

N

–

Z

–

V

*

C

*

H

1

DIVU

A

0

1

0

1

0

0 word (AH) /byte (AL)

Quotient → byte (AL) Remainder →

0 byte (AH)

–

*

2

DIVU

ear

A,

2

*

word (A)/byte (ear)

Quotient → byte (A) Remainder →

byte (ear)

word (A)/byte (eam)

Quotient → byte (A) Remainder →

byte (eam)

6

3

2+

2

*

DIVU

eam

A,

4

*

0

*

7

5

*

DIVUW A,

ear

2+

*

long (A)/word (ear)

Quotient → word (A) Remainder →

word (ear)

long (A)/word (eam)

Quotient → word (A) Remainder →

word (eam)

8

0

(b)

DIVUW A,

eam

1

2

2+

*

0

1

0

–

9

10

11

12

13

0

(c)

MULU

A

1

2

2+

0

1

0

–

*

byte (AH) *byte (AL) → word (A)

byte (A) *byte (ear) → word (A)

byte (A) *byte (eam) → word (A)

MULU A,

ear

MULU A,

eam

word (AH) *word (AL) → long (A)

word (A) *word (ear) → long (A)

word (A) *word (eam) → long (A)

MULUW A

MULUW A,

ear

MULUW A,

eam

*1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally.

*2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally.

*3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.

*4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally.

*5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.

*6: (b) when the result is zero or when an overflow occurs, and 2 × (b) normally.

*7: (c) when the result is zero or when an overflow occurs, and 2 × (c) normally.

*8: 3 when byte (AH) is zero, and 7 when byte (AH) is not zero.

*9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero.

*10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.

*11: 3 when word (AH) is zero, and 11 when word (AH) is not zero.

*12: 4 when word (ear) is zero, and 12 when word (ear) is not zero.

*13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.

Note: Foranexplanationof “(a)”to“(d)”, refertoTable4, “Numberof ExecutionCyclesforEachTypeof Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

96

MB90630A Series

Table 13 Logical 1 Instructions (Byte/Word) [39 Instructions]

R

G

L

A

H

RM

W

Mnemonic

AND A, #imm8

#

~

B

Operation

I

S

T

N

Z

V

C

H

2

3

0

1

0

byte (A) ← (A) and imm8

byte (A) ← (A) and (ear)

–

*

R

–

*

AND

A, ear

A, eam

ear, A

eam, A

2+ 4+ (a) 0

(b) byte (A) ← (A) and (eam)

byte (ear) ← (ear) and (A)

2

3

2

0

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) and (A) –

OR

A, #imm8

A, ear

A, eam

ear, A

2

3

0

1

0

byte (A) ← (A) or imm8

byte (A) ← (A) or (ear)

–

*

R

–

*

2+ 4+ (a) 0

(b) byte (A) ← (A) or (eam)

byte (ear) ← (ear) or (A)

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) or (A)

2

3

2

0

eam, A

XOR A, #imm8

XOR A, ear

XOR A, eam

XOR ear, A

XOR eam, A

2

3

0

1

0

byte (A) ← (A) xor imm8

byte (A) ← (A) xor (ear)

–

*

R

–

*

2+ 4+ (a) 0

2

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) xor (A) –

(b) byte (A) ← (A) xor (eam)

byte (ear) ← (ear) xor (A)

3

2

0

NOT

A

ear

eam

1

2

3

0

2

0

byte (A) ← not (A)

byte (ear) ← not (ear)

–

*

R

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← not (eam)

ANDW A

1

3

2

3

0

1

0

word (A) ← (AH) and (A)

word (A) ← (A) and imm16

word (A) ← (A) and (ear)

–

*

R

–

*

ANDW A, #imm16

ANDW A, ear

ANDW A, eam

ANDW ear, A

ANDW eam, A

2+ 4+ (a) 0

2

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) and (A) –

(c) word (A) ← (A) and (eam)

word (ear) ← (ear) and (A)

3

2

0

ORW

A

1

3

2

3

0

1

0

word (A) ← (AH) or (A)

word (A) ← (A) or imm16

word (A) ← (A) or (ear)

–

*

R

–

*

ORW A, #imm16

ORW A, ear

ORW A, eam

ORW ear, A

ORW eam, A

2+ 4+ (a) 0

2

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) or (A) –

(c) word (A) ← (A) or (eam)

word (ear) ← (ear) or (A)

3

2

0

XORW A

1

3

2

3

0

1

0

word (A) ← (AH) xor (A)

word (A) ← (A) xor imm16

word (A) ← (A) xor (ear)

–

*

R

–

*

XORW A, #imm16

XORW A, ear

XORW A, eam

XORW ear, A

XORW eam, A

2+ 4+ (a) 0

(c) word (A) ← (A) xor (eam)

word (ear) ← (ear) xor (A)

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) xor (A)

2

3

2

0

NOTW A

NOTW ear

NOTW eam

1

2

3

0

2

0

word (A) ← not (A)

word (ear) ← not (ear)

–

*

R

–

*

2+ 5+ (a) 0 2× (c) word (eam) ← not (eam)

Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

97

MB90630A Series

Table 14 Logical 2 Instructions (Long Word) [6 Instructions]

R

G

L

H

A

H

RM

W

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C

ANDL A, ear

ANDL A, eam

2

6

2

0

long (A) ← (A) and (ear)

–

*

R

–

2+ 7+ (a) 0

(d) long (A) ← (A) and (eam)

ORL

A, ear

A, eam

2

6

2

0

long (A) ← (A) or (ear)

–

*

R

–

2+ 7+ (a) 0

(d) long (A) ← (A) or (eam)

XORL A, ea

XORL A, eam

2

6

2

0

long (A) ← (A) xor (ear)

–

*

R

–

2+ 7+ (a) 0

(d) long (A) ← (A) xor (eam)

Table 15 Sign Inversion Instructions (Byte/Word) [6 Instructions]

R

G

L

A

H

RM

W

Mnemonic

#

1

2

~

2

3

B

0

Operation

byte (A) ← 0 – (A)

byte (ear) ← 0 – (ear)

I

S

T

N

Z

V

C

H

NEG

A

0

X

–

*

–

NEG ear

NEG eam

2

–

*

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← 0 – (eam)

NEGW A

1

2

0

word (A) ← 0 – (A)

–

*

–

NEGW ear

NEGW eam

2

3

2

0

word (ear) ← 0 – (ear)

–

*

–

*

2+ 5+ (a) 0 2× (c) word (eam) ← 0 – (eam)

Table 16 Normalize Instruction (Long Word) [1 Instruction]

L

H

A

H

RM

W

Mnemonic

#

~

RG

B

Operation

I

S

T

N

Z

V

C

1

NRML A, R0

2

1

0

long (A) ← Shift until first

digit is “1”

–

*

–

*

byte (R0) ← Current shift

count

*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).

Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

98

MB90630A Series

Table 17 Shift Instructions (Byte/Word/Long Word) [18 Instructions]

R

G

L A

H H

RM

W

Mnemonic

#

~

B

Operation

I

S

T N Z V C

RORCA

ROLC A

2

0

byte (A) ← Right rotation with carry

byte (A) ← Left rotation with carry

–

*

–

*

–

RORCear

RORCeam

ROLC ear

ROLC eam

2

3

2

0

byte (ear) ← Right rotation with carry –

–

*

–

*

–

*

–

*

2+ 5+ 0 2× (b) byte (eam) ← Right rotation with

2

2+

–

(a)

3

5+

(a)

2

0

carry

0 2× (b) byte (ear) ← Left rotation with carry

byte (eam) ← Left rotation with carry

ASR A, R0

LSR A, R0

LSL A, R0

2

1

0

–

*

–

*

–

*

–

byte (A) ← Arithmetic right barrel shift (A,

R0)

byte (A) ← Logical right barrel shift

1

*

1

(A, R0)

byte (A) ← Logical left barrel shift (A,

R0)

ASRWA

LSRWA/SHRW 1

A

LSLW A/SHLW

A

1

2

0

word (A) ← Arithmetic right shift (A, 1

bit)

word (A) ← Logical right shift (A, 1

bit)

word (A) ← Logical left shift (A, 1 bit)

–

*

–

*

R

*

–

*

–

1

2

1

0

–

*

–

*

–

*

–

*

1

ASRWA, R0

LSRWA, R0

LSLW A, R0

word (A) ← Arithmetic right barrel shift (A,

R0)

word (A) ← Logical right barrel shift

*

(A, R0)

word (A) ← Logical left barrel shift (A,

R0)

2

ASRL A, R0

LSRL A, R0

LSLL A, R0

2

1

0

long (A) ← Arithmetic right shift (A,

R0)

long (A) ← Logical right barrel shift

(A, R0)

–

*

–

*

–

*

–

*

2

long (A) ← Logical left barrel shift (A,

R0)

*1: 6 when R0 is 0, 5 + (R0) in all other cases.

*2: 6 when R0 is 0, 6 + (R0) in all other cases.

Note: Foranexplanationof “(a)”to“(d)”, refertoTable4, “Numberof ExecutionCyclesforEachTypeof Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

99

MB90630A Series

Table 18 Branch 1 Instructions [31 Instructions]

L

A

RM

W

Mnemonic

#

~

RG

B

Operation

I

S

T N Z V C

H H

1

BZ/BEQ

BNZ/BNE rel

BC/BLO

BNC/BHS rel

rel

2

0

Branch when (Z) = 1

Branch when (Z) = 0

Branch when (C) = 1

Branch when (C) = 0

Branch when (N) = 1

Branch when (N) = 0

Branch when (V) = 1

Branch when (V) = 0

Branch when (T) = 1

Branch when (T) = 0

Branch when (V) xor (N) = 1

Branch when (V) xor (N) = 0

Branch when ((V) xor (N)) or

(Z) = 1

–

*

1

*

1

rel

*

1

BN

BP

BV

BNV

BT

BNT

BLT

BGE

BLE

BGT

BLS

BHI

BRA

rel

1

*

1

*

1

*

1

*

1

Branch when ((V) xor (N)) or

(Z) = 0

Branch when (C) or (Z) = 1

Branch when (C) or (Z) = 0

Branch unconditionally

1

*

2

3

JMP

@A

1

3

2

2+

2

2+

4

0

1

0

2

0

–

addr16

@ear

@eam

3

4+ (a)

5

6+ (a)

4

word (PC) ← (A)

(c) word (PC) ← addr16

word (PC) ← (ear)

(d) word (PC) ← (eam)

JMPP @ear *³

JMPP @eam *³

JMPP addr24

0

word (PC) ← (ear), (PCB) ←

(ear +2)

CALL @ear *⁴

CALL @eam *⁴

CALL addr16 *⁵

CALLV #vct4 *⁵

CALLP @ear *⁶

6

7+ (a)

6

7

10

2

2+

3

1

2

1

(c) word (PC) ← (eam), (PCB) ←

–

0 2× (c) (eam +2)

0

(c) word (PC) ← ad24 0 to 15,

0 2× (c) (PCB) ← ad24 16 to 23

2 2× (c) word (PC) ← (ear)

word (PC) ← (eam)

word (PC) ← addr16

2

CALLP @eam *⁶

CALLP addr24 *⁷

11+ (a)

10

2+

4

0

–

*

Vector call instruction

word (PC) ← (ear) 0 to 15

(PCB) ← (ear) 16 to 23

word (PC) ← (eam) 0 to 15

(PCB) ← (eam) 16 to 23

word (PC) ← addr0 to 15,

(PCB) ← addr16 to 23

2× (c)

*1: 4 when branching, 3 when not branching.

*2: (b) + 3 × (c)

*3: Read (word) branch address.

*4: W: Save (word) to stack; R: read (word) branch address.

*5: Save (word) to stack.

*6: W: Save (long word) to W stack; R: read (long word) R branch address.

*7: Save (long word) to stack.

Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

100

MB90630A Series

Table 19 Branch 2 Instructions [19 Instructions]

L

H

A

H

RM

W

Mnemonic

#

~ RG

B

Operation

I

S

T

N

Z

V

C

1

CBNE A, #imm8, rel

CWBNEA, #imm16, rel

3

4

0

Branch when byte (A) ≠

imm8

–

*

–

*

1

Branch when word (A) ≠

imm16

2

3

4

3

CBNE ear, #imm8, rel

CBNE eam, #imm8,

rel*⁹

CWBNEear, #imm16,

rel

4

4+

5

*

1

0

1

0

(b)

0

–

*

–

Branch when byte (ear) ≠

5+

(c) imm8

Branch when byte (eam) ≠

imm8

Branch when word (ear) ≠

2 2× (b) imm16

Branch when word (eam) ≠

5

6

3

2

0

–

*

–

*

CWBNEeam, #imm16,

*

rel*⁹

3+

DBNZ ear, rel

imm16

5

6

3

*

2

0

–

*

–

*

DBNZ eam, rel

Branch when byte (ear) =

3+

2 2× (c) (ear) – 1, and (ear) ≠ 0

Branch when byte (eam) =

(eam) – 1, and (eam) ≠ 0

DWBNZ ear, rel

DWBNZ eam, rel

8× (c)

6× (c)

8× (c)

6× (c)

2

3

4

1

0

–

R

*

S

*

–

*

–

*

–

*

–

*

–

*

–

20

16

17

20

15

Branch when word (ear) =

(ear) – 1, and (ear) ≠ 0

Branch when word (eam) =

(eam) – 1, and (eam) ≠ 0

INT

INTP

INT9

RETI

#vct8

addr16

addr24

(c)

2

0

Software interrupt

Return from interrupt

–

6

LINK

#local8

(c)

1

0

–

5

At constant entry, save old

frame pointer to stack, set

new frame pointer, and

(c)

(d)

1

0

–

4

6

UNLINK

allocate local pointer area

At constant entry, retrieve

old frame pointer from stack.

RET *⁷

RETP *⁸

Return from subroutine

*1: 5 when branching, 4 when not branching

*2: 13 when branching, 12 when not branching

*3: 7 + (a) when branching, 6 + (a) when not branching

*4: 8 when branching, 7 when not branching

*5: 7 when branching, 6 when not branching

*6: 8 + (a) when branching, 7 + (a) when not branching

*7: Retrieve (word) from stack

*8: Retrieve (long word) from stack

*9: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.

Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

101

MB90630A Series

Table 20 Other Control Instructions (Byte/Word/Long Word) [36 Instructions]

L A

H H

RM

W

Mnemonic

#

~

RG

B

Operation

I

S

T N Z V C

PUSHW A

word (SP) ← (SP) –2, ((SP)) ← (A)

word (SP) ← (SP) –2, ((SP)) ← (AH)

word (SP) ← (SP) –2, ((SP)) ← (PS)

(SP) ← (SP) –2n, ((SP)) ← (rlst)

1

2

4

0

(c)

–

PUSHW AH

PUSHW PS

PUSHW rlst

3

5

4

*

POPW

A

word (A) ← ((SP)), (SP) ← (SP) +2

word (AH) ← ((SP)), (SP) ← (SP) +2

word (PS) ← ((SP)), (SP) ← (SP) +2

(rlst) ← ((SP)), (SP) ← (SP) +2n

1

2

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

3

4

0

(c)

POPW AH

POPW PS

POPW rlst

–

2

5

4

–

*

JCTX

@A

Context switch instruction

1

–

*

–

14

0 6× (c)

AND

OR

CCR, #imm8

byte (CCR) ← (CCR) and imm8

byte (CCR) ← (CCR) or imm8

2

–

*

–

3

0

MOV RP, #imm8

MOV ILM, #imm8

byte (RP) ←imm8

byte (ILM) ←imm8

2

–

2

0

MOVEA RWi, ear

MOVEA RWi, eam

MOVEA A, ear

word (RWi) ←ear

word (RWi) ←eam

word(A) ←ear

2

2+

2

–

*

–

3

1

0

2+ (a) 1

1

0

MOVEA A, eam

word (A) ←eam

2+

*

1+ (a) 0

ADDSP #imm8

ADDSP #imm16

word (SP) ← (SP) +ext (imm8)

word (SP) ← (SP) +imm16

2

3

–

3

0

1

MOV

A, brgl

brg2, A

byte (A) ← (brgl)

byte (brg2) ← (A)

2

Z

–

*

–

*

–

0

*

1

NOP

ADB

DTB

PCB

SPB

NCC

CMR

No operation

1

–

0

1

Prefix code for accessing AD space

Prefix code for accessing DT space

Prefix code for accessing PC space

Prefix code for accessing SP space

Prefix code for no flag change

Prefix code for common register bank

*1: PCB, ADB, SSB, USB, and SPB : 1 state

DTB, DPR : 2 states

*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)

*3: 29 + (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)

*4: Pop count × (c), or push count × (c)

*5: Pop count or push count.

Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

102

MB90630A Series

Table 21 Bit Manipulation Instructions [21 Instructions]

L A

H H

RM

W

Mnemonic

#

~

RG

B

Operation

I

S

T N Z V C

MOVB A, dir:bp

MOVB A,

addr16:bp

3

4

3

5

4

0

(b) byte (A) ← (dir:bp) b

(b) byte (A) ← (addr16:bp) b

(b) byte (A) ← (io:bp) b

Z

*

–

*

–

MOVB A, io:bp

3

4

3

7

6

0 2× (b) bit (dir:bp) b ← (A)

0 2× (b) bit (addr16:bp) b ← (A)

0 2× (b) bit (io:bp) b ← (A)

–

*

–

*

MOVB dir:bp, A

MOVB addr16:bp,

A

MOVB io:bp, A

3

4

3

7

0 2× (b) bit (dir:bp) b ← 1

0 2× (b) bit (addr16:bp) b ← 1

0 2× (b) bit (io:bp) b ← 1

–

*

SETB dir:bp

SETB addr16:bp

SETB io:bp

3

4

3

7

0 2× (b) bit (dir:bp) b ← 0

0 2× (b) bit (addr16:bp) b ← 0

0 2× (b) bit (io:bp) b ← 0

–

*

CLRB dir:bp

CLRB addr16:bp

CLRB io:bp

1

4

5

4

0

(b) Branch when (dir:bp) b = 0

(b) Branch when (addr16:bp) b = 0

(b) Branch when (io:bp) b = 0

–

*

–

*

1

2

BBC dir:bp, rel

BBC addr16:bp,

rel

1

4

5

4

0

(b) Branch when (dir:bp) b = 1

(b) Branch when (addr16:bp) b = 1

(b) Branch when (io:bp) b = 1

–

*

–

*

1

BBC io:bp, rel

2

BBS dir:bp, rel

BBS addr16:bp,

rel

3

5

3

0 2× (b) Branch when (addr16:bp) b = 1, –

–

*

–

*

bit = 1

5

4

BBS io:bp, rel

0

–

*

Wait until (io:bp) b = 1

Wait until (io:bp) b = 0

4

5

SBBS addr16:bp,

rel

*

WBTS io:bp

WBTC io:bp

*1: 8 when branching, 7 when not branching

*2: 7 when branching, 6 when not branching

*3: 10 when condition is satisfied, 9 when not satisfied

*4: Undefined count

*5: Until condition is satisfied

Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

103

MB90630A Series

Table 22 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]

R

G

L

A

H

RM

W

Mnemonic

SWAP

SWAPW/XCHW AL, AH

EXT

EXTW

ZEXT

ZEXTW

#

~

B

Operation

I

S

T

N

Z

V

C

H

1

3

2

1

2

1

0

0 byte (A) 0 to 7 ↔ (A) 8 to 15

0 word (AH) ↔ (AL)

0 byte sign extension

0 word sign extension

0 byte zero extension

0 word zero extension

–

X

–

Z

–

*

–

X

–

Z

–

*

R

–

*

–

*

Table 23 String Instructions [10 Instructions]

R

G

L

H

A

H

RM

W

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C

2

5

3

MOVS/MOVSI

MOVSD

2

Byte transfer @AH+ ← @AL+, counter

= RW0

Byte transfer @AH– ← @AL–, counter

= RW0

–

*

2

5

3

*

1

5

4

SCEQ/SCEQI

SCEQD

2

*

–

*

–

1

5

4

*

Byte retrieval (@AH+) – AL, counter =

RW0

5

3

6m +6

FISL/FILSI

2

–

*

–

*

Byte retrieval (@AH–) – AL, counter =

RW0

Byte filling @AH+ ← AL, counter =

RW0

2

8

6

MOVSW/

MOVSWI

MOVSWD

2

Word transfer @AH+ ←@AL+, counter –

–

*

2

8

6

= RW0

–

*

Word transfer @AH– ←@AL–, counter

= RW0

1

8

7

2

*

–

*

–

1

8

7

SCWEQ/

SCWEQI

SCWEQD

*

Word retrieval (@AH+) – AL, counter =

RW0

8

6

6m +6

2

–

*

–

*

Word retrieval (@AH–) – AL, counter =

RW0

FILSW/FILSWI

Word filling @AH+ ← AL, counter =

RW0

m: RW0 value (counter value)

n: Loop count

*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs

*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case

*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) separately

for each.

*4: (b) × n

*5: 2 × (RW0)

*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c) separately

for each.

*7: (c) × n

*8: 2 × (RW0)

Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

104

MB90630A Series

■ ORDERING INFORMATION

Model

Package

Remarks

MB90632APFV

MB90634APFV

MB90P634APFV

100-pin Plastic LQFP

(FPT-100P-M05)

MB90632APF

MB90634APF

MB90P634APF

100-pin Plastic QFP

(FPT-100P-M06)

MB90P634A supports ES alone.

105

MB90630A Series

■ PACKAGE DIMENSIONS

100-pin Plastic LQFP

(FPT-100P-M05)

1.50 –⁺0⁰.^.1²0⁰

.059 –⁺.^.0⁰0⁰4⁸

16.00±0.20(.630±.008)SQ

(Mounting height)

(Mouting height)

75

51

14.00±0.10(.551±.004)SQ

76

50

12.00

(.472)

REF

15.00

(.591)

NOM

Details of "A" part

0.15(.006)

INDEX

0.15(.006)

100

26

0.15(.006)MAX

0.40(.016)MAX

"B"

1

25

LEAD No.

"A"

0.50(.0197)TYP

0.18 –⁺0⁰.^.0⁰3⁸

0.127 ⁺–0⁰.^.0⁰2⁵

.005 ⁺^–.^.⁰⁰⁰⁰¹²

M

Details of "B" part

0.08(.003)

.007 –⁺.^.0⁰0⁰1³

0.10±0.10

(.004±.004)

(STAND OFF)

0.50±0.20(.020±.008)

0.10(.004)

0~10°

C

1995 FUJITSU LIMITED F100007S-2C-3

Dimensions in mm (inches)

100-pin Plastic QFP

(FPT-100P-M06)

23.90±0.40(.941±.016)

20.00±0.20(.787±.008)

3.35(.132)MAX

(Mounting height)

0.05(.002)MIN

(STAND OFF)

80

51

81

50

12.35(.486)

16.30±0.40

14.00±0.20 17.90±0.40

(.551±.008) (.705±.016)

REF

(.642±.016)

INDEX

31

100

"A"

1

30

LEAD No.

0.65(.0256)TYP

0.30±0.10

(.012±.004)

0.15±0.05(.006±.002)

Details of "B" part

M

0.13(.005)

Details of "A" part

0.25(.010)

"B"

0.10(.004)

0.30(.012)

0.18(.007)MAX

0.53(.021)MAX

0

10°

18.85(.742)REF

0.80±0.20

(.031±.008)

22.30±0.40(.878±.016)

C

1994 FUJITSU LIMITED F100008-3C-2

Dimensions in mm (inches)

106

MB90630A Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

KAWASAKI PLANT, 4-1-1, Kamikodanaka,

Nakahara-ku, Kawasaki-shi,

Kanagawa 211-8588, Japan

Tel: +81-44-754-3763

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

Fax: +81-44-754-3329

http://www.fujitsu.co.jp/

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

Fax: +1-408-922-9179

The contents of this document may not be reproduced or copied

without the permission of FUJITSU LIMITED.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

FUJITSU semiconductor devices are intended for use in standard

applications (computers, office automation and other office

equipments, industrial, communications, and measurement

equipments, personal or household devices, etc.).

Fax: +1-408-922-9179

http://www.fujitsumicro.com/

CAUTION:

Europe

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or

where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters,

vehicle operating controls, medical devices for life support, etc.)

are requested to consult with FUJITSU sales representatives before

such use. The company will not be responsible for damages arising

from such use without prior approval.

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

http://www.fmap.com.sg/

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0004

FUJITSU LIMITED Printed in Japan


型号：	MB90634A
厂家：	FUJITSU
描述：	16-bit Proprietary Microcontroller 16位微控制器专有微控制器
文件：	总107页 (文件大小：1469K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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