MB90653A [FUJITSU]
16-bit Proprietary Microcontroller; 16位微控制器专有
| 型号： | MB90653A |
| 厂家： | 
FUJITSU |
| 描述： | 16-bit Proprietary Microcontroller |
| 文件： | 总120页 (文件大小：1567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13607-3E
16-bit Proprietary Microcontroller
CMOS
F2MC-16L MB90650A Series
MB90652A/653A/P653A/654A/F654A
■ DESCRIPTION
The MB90650A series are 16-bit microcontrollers designed for high speed real-time processing in consumer
product applications such as controlling celluar phones, CD-ROMs, or VTRs. Based on the F2MC*1-16L CPU
core, an F2MC-16L is used as the CPU. This CPU includes high-level language-support instructions and robust
task switching instructions, and additional addressing modes. In order to reduce the consumption current, dual-
clock (main/sub) is used. Furthermore, low consumption power supply is achieved by using stop mode, sleep
mode, watch mode, pseudo-watch mode, CPU intermittent operation mode.
Microcontrollers in this series have built-in peripheral resources including 10-bit A/D converter, 8-bit D/A
converter, UART, 8/16-bit PPG, 8/16-bit up/down counter/timer, I2C interface*2, 8/16-bit I/O timer (input capture,
output compare, and 16-bit free-run timer).
*1:F2MC stands for FUJITSU Flexible Microcontroller.
*2:Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined
by Philips.
■ FEATURES
F2MC-16L CPU
• Minimum execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication) maximum multiplier = 4
• Instruction set optimized for controller applications
Object code compatibility with F2MC-16(H)
(Continued)
■ PACKAGE
100-pin plastic LQFP
100-pin plastic QFP
(FPT-100P-M05)
(FPT-100P-M06)
MB90650A Series
(Continued)
Wide range of data types (bit, byte, word, and long word)
Improved instruction cycles provide increased speed
Additional addressing modes: 23 modes
High code efficiency
Access methods (bank access, linear pointer)
High precision operations are enhanced by use of a 32-bit accumulator
Extended intelligent I/O service (access area extended to 64 Kbytes)
Maximum memory space: 16 Mbytes
• Enhanced high level language (C) and multitasking support instructions
Use of a system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Improved execution speed: Four byte instruction queue
• Powerful interrupt function
• Automatic data transfer function that does not use instruction (extended I2OS)
2
MB90650A Series
■ PRODUCT LINEUP
Part number
MB90652A
MB90P653A
MB90V650A
MB90654A
MB90F654A
MB90653A
Item
Mask ROM
product
Classification
Mask ROM product
64 Kbytes
3 Kbytes
2.2 V to 3.6 V
OTPROM product For evaluation
128 Kbytes
5 Kbytes
2.7 V to 5.5 V
340
FLASH product
ROM size
RAM size
—
256 Kbytes
8 Kbytes
Power supply
voltage
2.2 V to 3.6 V 2.4 V to 3.6 V
CPU functions
The number of instructions:
Instruction bit length:
Instruction length:
8/16 bits
1 to 7 bytes
1/4/8/16/32 bits
Data bit length:
Minimum execution time:
Interrupt processing time:
62.5 ns/4 MHz (PLL multiplier = 4)
1.0 µs/16 MHz (minimum)
Ports
I/O ports (N-channel open-drain):
I/O ports (CMOS):
4
75 (Input pull-up resistors available: 24/
Can be set as N-channel open-drain: 8)
79
Total:
A/D converter
D/A converter
Analog inputs : 8 channels
10-bit resolution
Conversion time : minimum
Analog inputs: 8 channels
10-bit resolution
Conversion time : minimum 12.25
Analog inputs : 8 channels
10-bit resolution
Conversion time : minimum
6.13 µs/16 MHz
6.13 µs/16 MHz
µs/8 MHz
2 channels (independent),
8-bit resolution, R-2R type
8/16-bit up/down
counter/timer
16 bits × 1 channel/8 bits × 2 channels selectable
Includes reload and compare functions.
I2C interface
1 channel
Master mode/slave mode available
UART
1 channel
Clock synchronous communication
Clock asynchronous communication
I/O extended serial
interface
8 bits × 2 channels
LSB-first or MSB-first operation selecable
8/16-bit PPG
8 bits × 2 channels/16 bits × 1 channel selectable
16-bit I/O timer
1 channel
(Input capture × 2 channels, output compare × 4 channels, and free-run timer × 1 channel)
DTP/external
interrupt
8 inputs
Timer functions
DTMF generator
Timebase timer (18-bit)/watchdog timer (18-bit)/watch timer (15-bit)
Supports every ITU-T (CCITT) tone for output (Internal 16 MHz shall be used for
DTMF generator).
Low-power
consumption modes
CPU intermittent operation mode, sub clock mode, stop mode, sleep mode,
watch mode, pseudo-watch mode
PLL function
Selectable multiplier: 1/2/3/4
(Set a multiplier that does not exceed the assured operation frequency range.)
Other
VPP is shared with
the MD2 pin
—
—
(for EPROM
programming)
Package
FPT-100P-M05, FPT-100P-M06
PGA-256C-A02 FPT-100P-M05, FPT-100P-M06
Notes: • MB90V650A device is assured only when operate with the tools, under the condition of power supply
voltage: 2.7 V to 3.3 V, operating temparature: 0°C to 70°C and operating frequency: 1.5 MHz to 8MHz
• For more information about each package, see seciton “PACKAGE DIMENSIONS”.
3
MB90650A Series
■ PIN ASSIGNMENT
(Top view)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RST
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PA1/OUT1
PA0/OUT0
P97/IN1
P96/IN0
P95/ZIN1
P94/BIN1
P93/AIN1/IRQ7
P92/ZIN0
P91/BIN0
P90/AIN0/IRQ6
P67/PPG11
P66/PPG10
P65/CKOT
P64/PPG01
P63/PPG00
P62/SCK2
P61/SOT2
P60/SIN2
DTMF
VSS
P32/WRL
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
VCC2
P86/OUT3
P85/IRQ5
P84/IRQ4
P83/IRQ3
P82/IRQ2
P45/SCK1
P46/ADTG
P47
P70/SDA
(FPT-100P-M05)
4
MB90650A Series
(Top view)
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
/
/
/
/
/
/
/
/
/
/
A16
A17
A18
A19
A20
A21
A22
A23
ALE
RD
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
X0A
X1A
PA2
RST
PA1
/
OUT2
/
OUT1
PA0
/OUT0
IN1
IN0
P97
P96
P95
P94
P93
P92
P91
P90
P67
P66
P65
P64
P63
P62
P61
P60
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
9
ZIN1
BIN1
AIN1
ZIN0
BIN0
AIN0
PPG11
PPG10
CKOT
PPG01
PPG00
SCK2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
/
/
IRQ7
IRQ6
P32
P33
P34
P35
P36
P37
P40
P41
P42
P43
P44
/
/
/
/
/
/
/
/
/
/
/
WRL
WRH
HRQ
HAK
RDY
CLK
SIN0
SOT0
SCK0
SIN1
SOT1
SOT2
SIN2
VCC
2
DTMF
P45
/
SCK1
P86
P85
P84
P83
P82
/
/
/
/
/
OUT3
IRQ5
IRQ4
IRQ3
IRQ2
P46
P47
P70
P71
P72
/
ADTG
/
/
SDA
SCL
TEST
MD2
DVRH
(FPT-100P-M06)
5
MB90650A Series
■ PIN DESCRIPTION
Pin no.
Circuit
type
Pin name
Function
LQFP*1
80
QFP*2
82
X0
A
A
B
B
D
Crystal oscillator pin
Crystal oscillator pin
81
83
X1
77
79
X1A
X0A
Crystal oscillatort pins (32 kHz)
Crystal oscillatort pins (32 kHz)
78
80
47 to 49 49 to 51 MD0 to MD2
Operating mode selection pins
Connect directly to VCC or VSS.
50
75
52
77
TEST
RST
D
Test input pin
This pin must always be fixed to “H”.
C
E
Reset input pin
83 to 90 85 to 92 P00 to P07
General-purpose I/O ports
(STBC) Pull-up resistors can be set (RD07 to RD00 = “1”) using the
pull-up resistor setting register (RDR0).
The setting does not apply for ports set as outputs (D07 to D00
= “1”: invalid at the output setting).
AD00 to AD07
In external bus mode, the pins function as the lower data I/O or
lower address outputs (AD00 to AD07).
91 to 98 93 to 100 P10 to P17
E
General-purpose I/O ports
(STBC) Pull-up resistors can be set (RD17 to RD10 = “1”) using the
pull-up resistor setting register (RDR1).
The setting does not apply for ports set as outputs (D17 to D10
= “1”: invalid at the output setting).
AD08 to AD15
In 16-bit external bus mode, the pins function as the upper data
I/O or middle address outputs (AD08 to AD15).
99,
100,
1 to 6
1,
2,
3 to 8
P20,
P21,
P22 to P27
I
General-purpose I/O ports
(STBC) In external bus mode, pins for which the corresponding bit in
the HACR register is “0” function as the P20 to P27 pins.
A16,
A17,
A18 to A23
In external bus mode, pins for which the corresponding bit in
the HACR register is “1” function as the upper address output
pins (A16 to A23).
7
8
9
P30
I
General-purpose I/O port
(STBC) Functions as the ALE pin in external bus mode.
ALE
P31
Functions as the address latch enable signal.
10
12
I
General-purpose I/O port
(STBC) Functions as the RD pin in external bus mode.
RD
Functions as the read strobe output (RD).
10
P32
I
General-purpose I/O port
(STBC) Functions as the WRL pin in external bus mode if the WRE bit
in the ECSR register is “1”.
WRL
Functions as the lower data write strobe output (WRL).
(Continued)
*1: FPT-100P-M05
*2: FPT-100P-M06
6
MB90650A Series
Pin no.
Circuit
type
Pin name
P33
Function
LQFP*1
QFP*2
11
12
13
14
15
16
13
I
General-purpose I/O port
(STBC) Functions as the WRH pin in 16-bit external bus mode if the
WRE bit in the ECSR register is “1”.
WRH
P34
Functions as the upper data write strobe output (WRH).
14
15
16
17
18
I
General-purpose I/O port
(STBC) Functions as the HRQ pin in external bus mode if the HDE bit
in the ECSR register is “1”.
HRQ
P35
Functions as the hold request input pin (HRQ).
I
General-purpose I/O port
(STBC) Functions as the HAK pin in external bus mode if the HDE bit in
the ECSR register is “1”.
HAK
P36
Functions as the hold acknowledge output (HAK) pin.
I
General-purpose I/O port
(STBC) Functions as the RDY pin in external bus mode if the RYE bit in
the ECSR register is “1”.
RDY
P37
Functions as the external ready input (RDY) pin.
I
General-purpose I/O port
(STBC) Functions as the CLK pin in external bus mode if the CKE bit in
the ECSR register is “1”.
CLK
P40
Functions as the machine cycle clock output (CLK) pin.
H
General-purpose I/O port
(STBC) When UART0 is operating, the data at the pin is used as the
serial input (SIN0).
Can be set as an open-drain output port (OD40 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D40 = “0”:
invalid at the input setting).
SIN0
P41
Functions as the UART0 serial input (SIN0).
17
19
G
General-purpose I/O port
(STBC) Functions as the SOT0 pin if the SOE bit in the UMC register is
“1”.
Can be set as an open-drain output port (OD41 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D41 = “0”:
invalid at the input setting).
SOT0
Functions as the UART0 serial data output pin (SOT0).
(Continued)
*1: FPT-100P-M05
*2: FPT-100P-M06
7
MB90650A Series
Pin no.
Circuit
type
Pin name
Function
LQFP*1
QFP*2
18
20
P42
H
General-purpose I/O port
(STBC) When UART0 is operating in external shift clock mode, the
data at the pin is used as the clock input (SCK0).
Also, functions as the SCK0 pin if the SOE bit in the UMC
register is “1”.
Can be set as an open-drain output port (OD42 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D42 = “0”:
invalid at the input setting).
SCK0
P43
Functions as the UART0 serial clock I/O pin (SCK0).
19
20
21
22
H
General-purpose I/O port
(STBC) When I/O extended serial is operating, the data at the pin is
used as the serial input (SIN1).
Can be set as an open-drain output port (OD43 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D43 = “0”:
invalid at the input setting).
SIN1
P44
Functions as the serial input for I/O extended serial data.
G
General-purpose I/O port
(STBC) Functions as the SOT1 pin if the SOE bit in the UMC register is
“1”.
Can be set as an open-drain output port (OD44 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D44 = “0”:
invalid at the input setting).
SOT1
P45
Functions as the output pin (SOT1) for I/O extended serial
data.
22
24
H
General-purpose I/O port
(STBC) When I/O extended serial is operating in external shift clock
mode, the data at the pin is used as the clock input (SCK1).
Also, functions as the SCK1 pin if the SOE bit in the UMC
register is “1”.
Can be set as an open-drain output port (OD45 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D45 = “0”:
invalid at the input setting).
SCK1
P46
Functions as the I/O extended serial clock I/O pin (SCK1).
23
24
25
26
G
General-purpose I/O port
(STBC) Can be set as an open-drain output port (OD46 = “1”) by the
open-drain control register (ODR4).
The setting does not apply for ports set as inputs (D46 = “0”:
invalid at the input setting).
ADTG
P47
Functions as the external trigger input pin for the A/D
converter.
K
Open-drain type general-purpose I/O port
(NMOS/H)
(STBC)
(Continued)
*1: FPT-100P-M05
*2: FPT-100P-M06
8
MB90650A Series
Pin no.
LQFP*1 QFP*2
Circuit
type
Pin name
Function
36 to 39, 38 to 41, P50 to P53,
41 to 44 43 to 46 P54 to P57
L
General-purpose I/O ports
(STBC)
AN0 to AN3,
AN4 to AN7
The pins are used as analog inputs (AN0 to AN7) when the A/D
converter is operating.
57
58
59
60
P60
F
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD60 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D60 = “1”:
invalid at the output setting).
SIN2
P61
Functions as a data input pin (SIN2) for I/O extended serial.
E
General-purpose I/O port
(STBC) Function as the SOT2 pin if the SOE bit in the UMC register is
“1”.
A pull-up resistor can be set (RD61 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D61 = “1”:
invalid at the output setting).
SOT2
P62
Functions as an output pin (SOT2) for I/O extended serial data.
59
61
F
General-purpose I/O port
(STBC) When I/O extended serial is operating in external shift clock
mode, the data at the pin is used as the clock input (SCK2).
Also, functions as the SCK2 pin if the SOE bit in the UMC
register is “1”.
A pull-up resistor can be set (RD62 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D62 = “1”:
invalid at the output setting).
SCK2
P63
Functions as the I/O extended serial clock I/O pin (SCK2).
60
61
62
63
E
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD63 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D63 = “1”:
invalid at the output setting).
PPG00
P64
Functions as the PPG00 output when PPG output is enabled.
E
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD64 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D64 = “1”:
invalid at the output setting).
PPG01
Functions as the PPG01 output when PPG output is enabled.
(Continued)
*1: FPT-100P-M05
*2: FPT-100P-M06
9
MB90650A Series
Pin no.
Circuit
type
Pin name
Function
LQFP*1
QFP*2
62
64
P65
E
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD65 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D65 = “1”:
invalid at the output setting).
CKOT
P66
Functions as the CKOT output when CKOT is operating.
63
64
25
26
65
66
27
28
E
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD66 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D66 = “1”:
invalid at the output setting).
PPG10
P67
Functions as the PPG10 output when PPG output is enabled.
E
General-purpose I/O port
(STBC) A pull-up resistor can be set (RD67 = “1”) using the pull-up
resistor setting register (RDR6).
The setting does not apply for ports set as outputs (D67 = “1”:
invalid at the output setting).
PPG11
P70
Functions as the PPG11 output when PPG output is enabled.
K
Open-drain type I/O port
(NMOS/H)
(STBC)
I2C interface data I/O pin
SDA
This function is valid when I2C interface operations are
enabled.
Set port output to Hi-Z (PDR = 1) during I2C interface
operations.
P71
SCL
K
Open-drain type I/O port
(NMOS/H)
(STBC)
I2C interface clock I/O pin
This function is valid when I2C interface operations are
enabled.
Set port output to Hi-Z (PDR = 1) during I2C interface
operations.
27
30
29
32
P72
P73
K
Open-drain type I/O port
(STBC)
M
Open-drain type I/O port
(STBC) Functions as a D/A output pin when DAE0 = “1” in the D/A
control register (DACR).
DA00
P74
Functions as D/A output 0 when the D/A converter is operating.
31
45
33
47
M
General-purpose I/O port
(STBC) Functions as a D/A output pin when DAE1 = “1” in the D/A
control register (DACR).
DA01
P80
Functions as D/A output 1 when the D/A converter is operating.
J
General-purpose I/O port
IRQ0
Functions as external interrupt request I/O 0.
(Continued)
*1: FPT-100P-M05
*2: FPT-100P-M06
10
MB90650A Series
Pin no.
Circuit
type
Pin name
P81
Function
LQFP*1
QFP*2
46
51
52
53
54
55
48
J
J
J
J
J
I
General-purpose I/O port
IRQ1
P82
Functions as external interrupt request I/O 1.
General-purpose I/O port
53
54
55
56
57
IRQ2
P83
Functions as external interrupt request I/O 2.
General-purpose I/O port
IRQ3
P84
Functions as external interrupt request I/O 3.
General-purpose I/O port
IRQ4
P85
Functions as external interrupt request I/O 4.
General-purpose I/O port
IRQ5
P86
Functions as external interrupt request I/O 5.
General-purpose I/O port
(STBC) This applies in all cases.
Event output for channel 3 of the output compare
General-purpose I/O port
OUT3
P90
65
67
J
AIN0
IRQ6
P91
Input to channel 0 of the 8/16-bit up/down counter/timer
Functions as an interrupt request input.
General-purpose I/O port
66
67
68
68
69
70
J
(STBC)
BIN0
P92
Input to channel 0 of the 8/16-bit up/down counter/timer
General-purpose I/O port
J
(STBC)
ZIN0
P93
Input to channel 0 of the 8/16-bit up/down counter/timer
General-purpose I/O port
J
AIN1
IRQ7
P94
Input to channel 1 of the 8/16-bit up/down counter/timer
Functions as an interrupt request input.
General-purpose I/O port
69
70
71
72
73
71
72
73
74
75
J
(STBC)
BIN1
P95
Input to channel 1 of the 8/16-bit up/down counter/timer
General-purpose I/O port
J
(STBC)
ZIN1
P96
Input to channel 1 of the 8/16-bit up/down counter/timer
General-purpose I/O port
J
(STBC)
IN0
Trigger input for channel 0 of the input capture
General-purpose I/O port
P97
J
(STBC)
IN1
Trigger input for channel 1 of the input capture
General-purpose I/O port
PA0
I
(STBC)
OUT0
Event output for channel 0 of the output compare
(Continued)
*1: FPT-100P-M05
*2: FPT-100P-M06
11
MB90650A Series
(Continued)
Pin no.
Circuit
type
Pin name
Function
LQFP*1
QFP*2
74
76
PA1
I
General-purpose I/O port
(STBC)
OUT1
PA2
Event output for channel 1 of the output compare
General-purpose I/O port
76
78
I
(STBC)
OUT2
VCC1
VCC2
VSS
Event output for channel 2 of the output compare
Power supply (3.0 V) input pin
82
21
84
23
—
—
Power supply (3.0 V/5.0 V) input pin
Power supply (0.0 V) input pin
9,
40,
79
11,
42,
81
—
32
33
34
35
28
29
56
34
35
36
37
30
31
58
AVCC
—
—
—
—
—
—
N
A/D converter power supply pin
AVRH
AVRL
AVSS
A/D converter external reference power supply pin
A/D converter external reference power supply pin
A/D converter power supply pin
DVRH
DVSS
D/A converter external reference power supply pin
D/A converter power supply pin
DTMF
DTMF output pin
*1: FPT-100P-M05
*2: FPT-100P-M06
Note: STBC = Incorporates standby control
NMOS = N-ch open-drain output
12
MB90650A Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• Oscillation feedback resistance :
Approx. 1 MΩ
X1
X0
Standby control signal
B
• Oscillation feedback resistance :
Approx. 10 MΩ
X1A
X0A
Standby control signal
Hysteresis input
Hysteresis input
CTL
C
• Hysteresis input with pull-up
Resistance approx. 50 kΩ
R
R
R
D
E
• Hysteresis input port
• Incorporates pull-up resistor control
(for input)
• CMOS level I/O
Resistance approx. 50 kΩ
CMOS
R
F
• Incorporates pull-up resistor control
(for input)
CTL
• CMOS level output
• Hysteresis input
Resistance approx. 50 kΩ
Hysteresis input
R
(Continued)
13
MB90650A Series
Type
Circuit
Remarks
• CMOS level I/O
G
• Incorporates open-drain control
Open-drain control
signal
CMOS
R
H
• CMOS level output
• Hysteresis input
• Incorporates open-drain control
Open-drain control
signal
Hysteresis input
R
I
• CMOS level I/O
CMOS
R
J
• CMOS level output
• Hysteresis input
Hysteresis input
R
K
L
• Hysteresis input
• N-ch open-drain output
Digital output
Hysteresis input
R
• CMOS level I/O
• Analog input
CMOS
R
Analog input
(Continued)
14
MB90650A Series
(Continued)
Type
Circuit
Remarks
M
• CMOS level I/O
• Analog output
• Shared with D/A outputs
D/A output
CMOS
R
N
• DTMF analog output
R
R
R
15
MB90650A Series
■ HANDLING DEVICES
1. Preventing Latch-up
Latch-up occurs in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin
or if the voltage applied between VCC and VSS exceeds the rating.
If latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements.
Therefore, ensure that maximum ratings are not exceeded in circuit operation.
For the same reason, also ensure that the analog supply voltage does not exceed the digital supply voltage.
2. Treatment of Unused Pins
Leaving unused input pins unconnected can cause misoperation. Always pull-up or pull-down unused pins.
3. External Reset Input
To reliably reset the controller by inputting an “L” level to the RST pin, ensure that the “L” level is applied for at
least five machine cycles. Take particular note when using an external clock input.
4. VCC and VSS Pins
Ensure that all VCC pins are at the same voltage. The same applies for the VSS pins.
5. Precautions when Using an External Clock
Drive the X0 pin only when using an external clock.
• Using an external clock
MB90650A Series
X0
X1
6. A/D Converter Power Supply and the Turn-on Sequence for Analog Inputs
Always turn off the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) before
turning off the digital power supply (VCC).
When turning the power on or off, ensure that AVRH does not exceed AVCC.
Also, when using the analog input pins as input ports, ensure that the input voltage does not exceed AVCC.
7. Turn-on Sequence for D/A Converter Power Supply
Always turn on the D/A converter power supply (DVR), after turning off the digital power supply (VCC).
And in the turning off the power supply sequence always turn off the digital power supply (VCC) after turning off
the D/A converter power supply (DVR).
16
MB90650A Series
8. Initializing
In this device there are some kinds of inner resisters which are initializid only by power on reset. It is possible
to initialize these resisters by turning on the power supply again.
9. Power Supply Pins
When there are several VCC and VSS pins, those pins that should have the same electric potential are connected
within the device when the device is designed in order to prevent misoperation, such as latchup. However, all
of those pins must be connected to the power supply and ground externally in order to reduce unnecessary
emissions, prevent misoperation of strobe signals due to an increase in the ground level, and to observe the
total output current standards.
In addition, give a due consideration to the connection in that current supply be connected to VCC and VSS with
the lowest possible impedance.
Finally, it is recommended to connect a capacitor of about 0.1 µF between VCC and VSS near this device as a
bypass capacitor.
10.Crystal Oscillation Circuit
Noise in the vicinity of the X0 and X1 pins will cause this device to operate incorrectly. Design the printed circuit
board so that the bypass capacitor connecting X0, X1 and the crystal oscillator (or ceramic oscillator) to ground
is located as close to the device as possible, and that the wiring does not closs the other wirings.
In addition, because printed circuit board artwork in which the area around the X0 and X1 pins is surrounded
by ground provides stable operation, such an arrangement is strongly recommended.
11. About 2 Power Supplies
The MB90650A series usually uses the 3-V power supply as the main power source. With Vcc1 = 3 V and Vcc2
= 5 V, however, it can interface with P20 to P27, P30 to P37, P40 to P47, and P70 to P72 for the 5-V power
supply separately from the 3-V power supply. Note, however, that the analog power supplies such as A/D and
D/A can be used only as 3-V power supplies.
17
MB90650A Series
■ PROGRAMMING FOR MB90P653A
In EPROM mode, the MB90P653A functions equivalent to the MBM27C1000/1000A. This allows the EPROM
to be programmed with a general-purpose EPROM programmer by using the dedicated socket adapter (do not
use the electronic signature mode).
1. Program Mode
When shipped from Fujitsu, and after each erasure, all bits (128 K × 8 bits) in the MB90P653A are in the “1”
state. Data is written to the ROM by selectively programming “0” into the desired bit locations. Bits cannot be
set to “1” electrically.
2. Programming Procedure
(1) Set the EPROM programmer to MBM27C1000/1000A.
(2) Load program data into the EPROM programmer at 00000H to 1FFFFH.
Note that ROM addresses FE0000H to FFFFFFH in the operation mode in the MB90P653A series assign to
00000H to 1FFFFH in the EPROM mode (on the EPROM programmer).
Normal operating mode
EPROM mode
FFFFFF H
1FFFF H
00000 H
PROM
PROM
FE0000 H
010000 H
PROM
Mirror
004000 H
000000 H
The 00 bank PROM mirror is 48 Kbytes. (This is a mirror for FF4000H to FFFFFFH.)
(3) Mount the MB90P653A on the adapter socket, then fit the adapter socket onto the EPROM programmer.
When mounting the device and the adapter socket, pay attention to their mounting orientations.
(4) Start programming the program data to the device.
(5) If programming has not successfully resulted, connect a capacitor of approx. 0.1 µF between VCC and GND,
between VPP and GND.
Note: The mask ROM products (MB90653A, MB90652A) does not support EPROM mode. Data cannot, therefore,
be read by the EPROM programmer.
18
MB90650A Series
3. EPROM Programmer Socket Adapter
MB90652APFV MB90653APFV MB90P653APFV
MB90P653APF
Part no.
Package
MB90652APF MB90653APF
QFP-100
LQFP-100
Compatible
socket
adapter
ROM-100SQF-32DP-16L
ROM-100QF-32DP-16L
Sun Hayato
Co., Ltd.
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
4. Recommended Screening Conditions
High temperature aging is recommended as the pre-assembly screening procedure.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yeild
MB90P653A cannot be write tested for all bits due to their nature. Therefore the write yield cannot always be
guaranteed to be 100%.
19
MB90650A Series
6. EPROM Mode Pin Assignments
• MBM27C1000/1000A compatible pins
MBM27C1000/1000A
MB90P653A
Pin no.
MBM27C1000/1000A
MB90P653A
Pin no. Pin name
Pin no.
Pin name
VPP
Pin name
MD2
P32
P17
P14
P27
P26
P25
P24
P23
P22
P21
P20
P00
P01
P02
VSS
Pin no.
32
Pin name
VCC
1
2
VCC
P33
—
OE
31
PGM
N.C.
A14
3
A15
A12
A07
A06
A05
A04
A03
A02
A01
A00
D00
D01
D02
GND
30
4
29
P16
P15
P10
P11
P13
P30
P12
P31
P07
P06
P05
P04
P03
5
28
A13
6
27
A08
7
26
A09
8
25
A11
9
24
A16
10
11
12
13
14
15
16
23
A10
CE
22
21
D07
D06
D05
D04
D03
20
19
18
17
• Non-MBM27C1000/1000A compatible pins
• Power supply, GND connection pins
Pin no.
Pin name
Treatment
Classification
Pin no.
Pin name
MD0
MD1
X0
HST
VCC
DVRH
See
Connect a pull-up
resistor of 4.7 kΩ.
Power supply
“PIN ASSIGNMENT”
X0A
P34
P35
P36
RST
AVRL
AVSS
DVSS
VV
X1 to X1A
OPEN
AVCC
AVRH
P37
See
GND
See “PIN
ASSIGN-
MENT”
“PIN ASSIGNMENT”
P40 to P47
P50 to P57
P60 to P67
P70 to P74
P80 to P86
P90 to P97
PA0 to PA2
N.C.
Connect a pull-up
resistor of about
1 MΩ to each pin.
TEST
20
MB90650A Series
■ BLOCK DIAGRAM
CPU
Clock control
circuit
X0, X1
RST
X0A, X1A
5
F2MC-16L family core
Interrupt controller
RAM
ROM
2
2
PPG00, PPG01
PPG10, PPG11
8/16-bit PPG
(Output switching) × 1 channel
8/16-bit up/down
counter/timer
8 bits × 2 channels
(16 bits × 1 channel)
2
2
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
2
Communications prescaler
UART
SIN0
SOT0
SCK0
CKOT
Prescaler
6
IRQ0 to IRQ5
IRQ6, IRQ7
2
2
2
SIN1, SIN2
DTP/external interrupt
I/O extended serial
SOT1, SOT2
SCK1, SCK2
interface × 2 channels
2
16-bit I/O timers
2
IN0, IN1
16-bit input capture × 2 channels
AVCC
AVRH, AVRL
AVSS
2
4
16-bit output compare × 4 channels
16-bit free-run timer × 1 channel
OUT1 to OUT3
A/D converter
(10 bits)
ADTG
AN0 to AN7
8
DTMF
DTMF
2
DA00, DA01
DVRH
DVSS
SCL
SDA
D/A converter
(8 bits)
I2C interface
I/O ports
8
8
8
8
8
8
8
5
7
8
3
Other pins
P00 P10 P20 P30 P40 P50 P60 P70 P80 P90 PA0
to to to to to to to to to to to
P07 P17 P27 P37 P47 P57 P67 P74 P86 P97 PA2
TEST, AD00 to AD15,
A16 to A23, ALE, RD,
WRL, WRH, HRQ,
P00 to P07 (8 pins) : Incorporates a pull-up resistor setting register (for input)
P10 to P17 (8 pins) : Incorporates a pull-up resistor setting register (for input)
P60 to P67 (8 pins) : Incorporates a pull-up resistor setting register (for input)
P40 to P46 (7 pins) : Incorporates an open-drain setting register
P47, P70 to P72 (4 pins) : Open-drain
HAK, RDY, CLK, N.C.,
MD0 to MD2, VCC, VSS
21
MB90650A Series
■ MEMORY MAP
• MB90652, MB90653, MB90P653
Single chip mode
FFFFFFH
Internal ROM/external bus mode External ROM/external bus mode
ROM area
ROM area
Address #1
FE0000H
010000H
ROM area
ROM area
(FF bank image)
(FF bank image)
Address #2
004000H
002000H
Address #3
RAM
Registers
RAM
Registers
RAM
Registers
000100H
0000C0H
Peripherals
Peripherals
Peripherals
000000H
*
*
*
Address #3
Type
MB90652
MB90653
Address #2
004000H
004000H
004000H
Address #1
FF0000H
FE0000H
000CFFH
0014FFH
0014FFH
MB90P653
FE0000H
: Internal access memory
: External access memory
: No access
* : Address #1, #2, and #3 are different owing to their devices respectively.
Notes: While the ROM data image of bank FF can be seen in the upper portion of bank 00, this is done only to permit
effective use of the C compiler’s small model. Because the lower 16 bits are the same, it is possible to
reference tables in ROM without declaring the “far” specification in the pointer.
For example, to access to 00C000H is to access to the ROM content of FFC000H in practice.
Because the ROM area of FF bank exceeds 48 Kbytes, all the area can be seen in bank 00.
So, the image for FF4000H to FFFFFFH can be seen in bank 00, while FE0000H to FF3FFFH can only be
seen in bank FF and FE.
22
MB90650A Series
• MB90654A, MB90F654A
FFFFFFH
ROM area
010000H
ROM area
ROM area
(FF bank image)
(FF bank image)
002100H
Registers
Registers
Registers
RAM
RAM
RAM
000100H
0000C0H
Peripherals
Peripherals
Peripherals
000000H
Address #3
0020FFH
Type
MB90654A*
Address #2
004000H
Address #1
FC0000H
MB90F654A*
004000H
FC0000H
0020FFH
: Internal access memory
: External access memory
: No access
* : In the MB90654A and MB90F654A, RAM area 2000H is 2100H.
Notes: While the ROM data image of bank FF can be seen in the upper portion of bank 00, this is done only to permit
effective use of the C compiler’s small model. Because the lower 16 bits are the same, it is possible to
reference tables in ROM without declaring the “far” specification in the pointer.
For example, to access to 00C000H is to access to the ROM content of FFC000H in practice.
Because the ROM area of FF bank exceeds 48 Kbytes, all the area can be seen in bank 00.
So, the image for FF4000H to FFFFFFH can be seen in bank 00, while FE0000H to FF3FFFH can only be
seen in bank FF and FE.
23
MB90650A Series
■ F2MC-16L CPU PROGRAMMING MODEL
• Dedicated registers
Accumulator
AH
AL
USP
SSP
PS
User stack pointer
System stack pointer
Processor status
PC
Program counter
USPCU
SSPCU
USPCL
SSPCL
User stack upper register
System stack upper register
User stack lower register
System stack lower register
Direct page register
DPR
Program bank register
Data bank register
PCB
DTB
USB
SSB
ADB
User stack bank register
System stack bank register
Additional data bank register
8 bits
16 bits
32 bits
• General-purpose registers
Maximum 32 banks
R7
R5
R3
R1
R6
RW7
RW6
RW5
RW4
RL3
RL2
RL1
RL0
R4
R2
R0
RW3
RW2
RW1
RW0
000180H + RP × 10H →
16 bits
• Processor status (PS)
ILM
RP
—
I
S
T
N
Z
V
C
CCR
24
MB90650A Series
■ I/O MAP
Register Read/
Address
Register
Resource name
Initial value
name
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00H
01H
Port 0 data register
Port 1 data register
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
1XXXXXXXB
XXXXXXXXB
XXXXXXXXB
–––XX111B
–XXXXXXXB
XXXXXXXXB
–––––XXXB
02H
Port 2 data register
Port 3 data register
Port 4 data register
Port 5 data register
Port 6 data register
Port 7 data register
Port 8 data register
Port 9 data register
Port A data register
03H
04H
05H
06H
07H
08H
09H
0AH
0BH to 0FH
10H
(Reserved area)
DDR0
Port 0 direction register
Port 1 direction register
Port 2 direction register
Port 3 direction register
Port 4 direction register
Port 5 direction register
Port 6 direction register
Port 7 direction register
Port 8 direction register
Port 9 direction register
Port A direction register
Port 4 pin register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port 4
Port 0
Port 1
Port 6
Port 5, A/D
00000000B
00000000B
00000000B
00000000B
–0000000B
00000000B
00000000B
–––00–––B
–0000000B
00000000B
–––––000B
–0000000B
00000000B
00000000B
00000000B
11111111B
00000000B
00000100B
11H
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
DDRA
ODR4
RDR0
RDR1
RDR6
ADER
SMR0
SCR0
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
Port 0 resistance register
Port 1 resistance register
Port 6 resistance register
Analog input enable register
Serial mode register 0
Serial control register 0
21H
UART0
Serial input register/
serial output register 0
SIDR/
SODR0
22H
R/W
XXXXXXXXB
(Continued)
25
MB90650A Series
Register Read/
Address
Register
Resource name
Initial value
name
write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23H
24H
Serial status register 0
SSR0
UART0
00001–00B
––––0000B
00000010B
XXXXXXXXB
0–––1111B
––––0000B
00000010B
XXXXXXXXB
Serial mode control status register 0
Serial mode control status register 0
Serial data register 0
SMCS0
SMCS0
SDR0
I/O extended serial
interface 0
25H
26H
Communications prescaler
27H
Clock division control register
Serial mode control status register 1
Serial mode control status register 1
Serial data register 1
CDCR
SMCS1
SMCS1
SDR1
28H
I/O extended serial
interface 1
29H
2AH
2BH to 2FH
30H
(Reserved area)
Interrupt/DTP enable register
Interrupt/DTP source register
ENIR
R/W
R/W
00000000B
00000000B
00000000B
00000000B
31H
EIRR
DTP/external interrupts
32H
Request level setting register
ELVR
R/W
33H
34H to 35H
36H
(Reserved area)
Control status register 1
Control status register 2
Data register 1
ADCS1
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
–––––––0B
–––––––0B
R/W
R
37H
ADCS2
ADCR1
ADCR2
DAT0
A/D converter
D/A converter
38H
39H
Data register 2
3AH
D/A converter data register 0
D/A converter data register 1
D/A control register channel 0
D/A control register channel 1
R/W
R/W
R/W
R/W
3BH
DAT1
3CH
DACR0
DACR1
3DH
Clock output control
register
3EH
Clock control register
CLKR
R/W
––––0000B
3FH
40H
41H
42H
43H
(Reserved area)
Reload register lower channel 0
Reload register upper channel 0
Reload register lower channel 1
Reload register upper channel 1
PRLL0
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
PRLH0
PRLL1
PRLH1
PPG0 operation mode control register
channel 0
8/16-bit PPG
44H
45H
PPGC0
PPGC1
PPGOE
R/W
R/W
R/W
0X000XX1B
0X000001B
00000000B
PPG1 operation mode control register
channel 1
PPG0, PPG1 output control register
channel 0, channel 1
46H
47H to 4FH
(Reserved area)
16-bit I/O timer output
compare (channel 0 to
channel 3)
50H
Lower compare register channel 0
OCCP0
R/W
XXXXXXXXB
(Continued)
26
MB90650A Series
Register Read/
Address
Register
Resource name
Initial value
name
write
51H
52H
Upper compare register channel 0
Lower compare register channel 1
Upper compare register channel 1
Lower compare register channel 2
Upper compare register channel 2
Lower compare register channel 3
Upper compare register channel 3
Compare control status register channel 0
Compare control status register channel 1
Compare control status register channel 2
Compare control status register channel 3
OCCP0
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
0000––00B
–––00000B
0000––00B
–––00000B
OCCP1
OCCP2
OCCP3
R/W
R/W
R/W
53H
54H
55H
16-bit I/O timer
Output compare
(channel 0 to channel 3)
56H
57H
58H
OCS0
OCS1
OCS2
OCS3
R/W
R/W
R/W
R/W
59H
5AH
5BH
5CH to 5FH
60H
(Reserved area)
R
Lower input capture register channel 0
Upper input capture register channel 0
Lower input capture register channel 1
Upper input capture register channel 1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
IPCP0
61H
R
R
16-bit I/O timer
Input capture
(channel 0, channel 1)
62H
IPCP1
63H
R
64H
Input capture control status register ICS0, 1
R/W
65H
(Reserved area)
66H
Lower timer data register
Upper timer data register
Timer control status register
TCDTL
R/W
R/W
R/W
00000000B
00000000B
00000000B
16-bit I/O timer
Free-run timer
67H
TCDTH
TCCS
68H
69H to 6FH
70H
(Reserved area)
Up/down count register channel 0
Up/down count register channel 1
Reload compare register channel 0
Reload compare register channel 1
Counter status register channel 0
UDCR0
00000000B
00000000B
00000000B
00000000B
00000000B
R
71H
UDCR1
RCR0
RCR1
CSR0
8/16-bit up/down
counter/timer
72H
W
73H
74H
R/W
75H
(Reserved area)
76H
CCRL0
00001000B
00000000B
00000000B
Counter control register channel 0
Counter status register channel 1
R/W
R/W
8/16-bit up/down
counter/timer
77H
CCRH0
CSR1
78H
79H
(Reserved area)
CCRL1 R/W
8/16-bit up/down
counter/timer
7AH
Counter control register channel 1
00000000B
(Continued)
27
MB90650A Series
Register Read/
Address
Register
Resource name
Initial value
name
write
8/16-bit up/down
counter/timer
7BH
Counter control register channel 1
CCRH1
R/W
X0001000B
7CH to 7FH
80H
(Reserved area)
I2C bus status register
I2C bus control register
I2C bus clock control register
I2C bus address register
I2C bus data register
IBSR
R
00000000B
00000000B
––0XXXXXB
–XXXXXXXB
XXXXXXXXB
81H
IBCR
ICCR
IADR
IDAR
R/W
R/W
R/W
R/W
I2C interface
82H
83H
84H
85H to 87H
88H
(Reserved area)
DTMF control register
DTMF data register
DTMC
DTMD
—
—
—
—
00000000B
000X0000B
89H
8A to 9EH
(Reserved area) (Accessing 90H to 9EH is prohibited)
Delayed interrupt generation/
release register
Delayed interrupt
generation module
9FH
A0H
A1H
DIRR
R/W
R/W
R/W
–––––––0B
00011000B
11111100B
Low-power consumption mode
control register
Low-power consumption
mode
LPMCR
CKSCR
Low-power consumption
mode
Clock selection register
A2H to A4H
A5H
(Reserved area)
Auto-ready function selection register
External bus pin control circuit
ARSR
W
0011––00B
00000000B
External address output control
register
HACR
W
External bus pin control circuit
A6H
A7H
A8H
Bus control signal selection register ECSR
W
External bus pin control circuit 0000*00–B
Watchdog timer control register
Timebase timer control register
Watch timer control register
WDTC
TBTC
WTC
R/W
R/W
R/W
Watchdog timer
Timebase timer
Watch timer
XXXXX111B
1––00000B
1X–00000B
A9H
AAH
ABH to AFH
(Reserved area)
(Continued)
28
MB90650A Series
(Continued)
Register Read/
Address
Register
Resource name
Initial value
name
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
B0H
B1H
Interrupt control register 00
Interrupt control register 01
Interrupt control register 02
Interrupt control register 03
Interrupt control register 04
Interrupt control register 05
Interrupt control register 06
Interrupt control register 07
Interrupt control register 08
Interrupt control register 09
Interrupt control register 10
Interrupt control register 11
Interrupt control register 12
Interrupt control register 13
Interrupt control register 14
Interrupt control register 15
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
B2H
B3H
B4H
B5H
B6H
B7H
Interrupt controller
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
C0H to FFH
(External area)
About Programming
R/W : Readable and writable
R
: Read only
W : Write only
Explanation of initial values
0: The initial value of this bit is “0”.
1: The initial value of this bit is “1”.
* : The initial value of this bit is “0” or “1”.
X: The initial value of this bit is undefined.
–: This bit is not used. The initial value is undefined.
Note: Areas below address 0000FFH not listed in the table are reserved areas. These addresses are accessed by
internal access. No access signals are output on the external bus.
29
MB90650A Series
■ INTERRUPT VECTOR AND INTERRUPT CONTROL REGISTER ASSIGNMENTS TO
INTERRUPT SOURCES
Interrupt vector
Number Address
Interrupt control register
I2OS
support
Interrupt source
Number
Address
Reset
×
×
×
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
#20
#21
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
—
—
—
—
—
—
INT 9 instruction
Exception
A/D converter
ICR00
ICR01
ICR02
ICR03
ICR04
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
Timebase timer interval interrupt
DTP/external interrupt 0 (External interrupt 0)
16-bit free-run timer (I/O timer) overflow
I/O extended serial interface 1
DTP/external interrupt 1 (External interrupt 1)
I/O extended serial interface 2
DTP/external interrupt 2 (External interrupt 2)
DTP/external interrupt 3 (External interrupt 3)
8/16-bit PPG 0 counter borrow
8/16-bit up/down counter/timer 0 compare
×
ICR05
0000B5H
8/16-bit up/down counter/timer 0
underflow/overflow, up/down invert
#22
FFFFA4H
8/16-bit PPG 1 counter borrow
#23
#24
#25
#26
#27
#28
#29
FFFFA0H
FFFF9CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
ICR06
ICR07
ICR08
0000B6H
0000B7H
0000B8H
DTP/external interrupt 4/5 (External interrupt 4/5)
Output compare (channel 2) match (I/O timer)
Output compare (channel 3) match (I/O timer)
Watch prescaler
×
DTP/external interrupt 6 (External interrupt 6)
8/16-bit up/down counter/timer 1 compare
ICR09
0000B9H
8/16-bit up/down counter/timer 1
underflow/overflow, up/down invert
#30
FFFF84H
Input capture (channel 0) read (I/O timer)
Input capture (channel 1) read (I/O timer)
Output compare (channel 0) match (I/O timer)
Output compare (channel 1) match (I/O timer)
Completion of flash memory write/erase
DTP/external interrupt 7 (External interrupt 7)
UART0 receive complete
#31
#32
#33
#34
#35
#36
#37
#39
#41
#42
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
FFFF60H
FFFF58H
FFFF54H
ICR10
ICR11
ICR12
0000BAH
0000BBH
0000BCH
×
ICR13
ICR14
0000BDH
0000BEH
UART0 transmit complete
I2C interface
×
×
ICR15
0000BFH
Delayed interrupt generation module
: Indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal.
: Indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (stop request present).
: Indicates that the interrupt request flag is not cleared by the I2OS interrupt clear signal.
Note: For resources in which two interrupt sources share the same interrupt number, the I2OS interrupt clear signal
clears both interrupt request flags.
30
MB90650A Series
■ PERIPHERAL RESOURCES
1. Parallel Ports
(1) I/O Ports
Each port pin can be specified as either an input or output by its corresponding direction register when the pin
is not set for use by a peripheral. When a port is set as an input, reading the data register always reads the
value corresponding to the pin level. When a port is set as an output, reading the data register reads the data
register latch value. The same applies when reading using a read-modify-write instruction.
When used as control outputs, reading the data register reads the control output value, irrespective of the
direction register value.
Note that if a read-modify-write instruction (set bit or similar instruction) is used to set output data in the data
register before switching a pin from input to output, the instruction reads the input level at the pin and not the
data register latch value.
• Block diagram
↑
Data register read
Pin
Data register
↑
Data register write
Direction register
↑
Direction register write
↑
Direction register read
31
MB90650A Series
(2) Port Direction Registers
• Port 0 data register (PDR0)
bit 7
P07
bit 6
P06
bit 5
P05
bit 4
P04
bit 3
P03
bit 2
P02
bit 1
P01
bit 0
P00
Initial value
Access
R/W*
Address : 000000H
XXXXXXXXB
• Port 1 data register (PDR1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
P10
Initial value
Access
R/W*
Address : 000001H
P17
P16
P15
P14
P13
P12
P11
XXXXXXXXB
• Port 2 data register (PDR2)
Initial value
Access
R/W*
bit 7
P27
bit 6
P26
bit 5
P25
bit 4
P24
bit 3
P23
bit 2
P22
bit 1
P21
bit 0
P20
Address : 000002H
XXXXXXXXB
• Port 3 data register (PDR3)
Initial value
Access
R/W*
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
P30
Address : 000003H
P37
P36
P35
P34
P33
P32
P31
XXXXXXXXB
• Port 4 data register (PDR4)
bit 7
P47
bit 6
P46
bit 5
P45
bit 4
P44
bit 3
P43
bit 2
P42
bit 1
P41
bit 0
P40
Initial value
Access
R/W*
Address : 000004H
1XXXXXXXB
• Port 5 data register (PDR5)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
P50
Initial value
Access
R/W*
Address : 000005H
P57
P56
P55
P54
P53
P52
P51
XXXXXXXXB
• Port 6 data register (PDR6)
bit 7
P67
bit 6
P66
bit 5
P65
bit 4
P64
bit 3
P63
bit 2
P62
bit 1
P61
bit 0
P60
Initial value
Access
R/W*
Address : 000006H
XXXXXXXXB
• Port 7 data register (PDR7)
Initial value
- - - XX111B
Access
R/W*
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
P70
Address : 000007H
—
—
—
P74
P73
P72
P71
• Port 8 data register (PDR8)
Initial value
Access
R/W*
bit 7
—
bit 6
P86
bit 5
P85
bit 4
P84
bit 3
P83
bit 2
P82
bit 1
P81
bit 0
P80
Address : 000008H
- XXXXXXXB
• Port 9 data register (PDR9)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
P90
Initial value
Access
R/W*
Address : 000009H
P97
P96
P95
P94
P93
P92
P91
XXXXXXXXB
• Port A data register (PDRA)
Initial value
- - - - - XXXB
Access
R/W*
bit 7
—
bit 6
—
bit 5
—
bit 4
—
bit 3
—
bit 2
PA2
bit 1
PA1
bit 0
PA0
Address : 00000AH
R/W : Readable and writable
—
X
: Unused
: Indeterminate
* : The operation of reading or writing to I/O ports is slightly different from reading or writing to memory, as follows.
• Input mode
Read: Reads the corresponding pin level.
Write: Writes to the output latch.
• Output mode
Read: Reads the value of the data register latch.
Write: The value is output from the corresponding pin.
32
MB90650A Series
(3) Port Direction Registers
• Port 0 direction register (DDR0)
bit 7
D07
bit 6
D06
bit 5
D05
bit 4
D04
bit 3
D03
bit 2
D02
bit 1
D01
bit 0
D00
Initial value
Access
R/W*
Address : 000010H
00000000B
• Port 1 direction register (DDR1)
Initial value
Access
R/W*
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
D10
D17
D16
D15
D14
D13
D12
D11
00000000B
Address : 000011H
• Port 2 direction register (DDR2)
Initial value
Access
R/W*
bit 7
D27
bit 6
D26
bit 5
D25
bit 4
D24
bit 3
D23
bit 2
D22
bit 1
D21
bit 0
D20
00000000B
Address : 000012H
• Port 3 direction register (DDR3)
Initial value
Access
R/W*
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
D30
Address : 000013H
D37
D36
D35
D34
D33
D32
D31
00000000B
• Port 4 direction register (DDR4)
Initial value
Access
R/W*
bit 7
—
bit 6
D46
bit 5
D45
bit 4
D44
bit 3
D43
bit 2
D42
bit 1
D41
bit 0
D40
Address : 000014H
• Port 5 direction register (DDR5)
-0000000B
Initial value
Access
R/W*
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
D50
D57
D56
D55
D54
D53
D52
D51
00000000B
Address : 000015H
• Port 6 direction register (DDR6)
Initial value
Access
R/W*
bit 7
D67
bit 6
D66
bit 5
D65
bit 4
D64
bit 3
D63
bit 2
D62
bit 1
D61
bit 0
D60
00000000B
Address : 000016H
• Port 7 direction register (DDR7)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
—
Initial value
---00--- B
Access
R/W*
—
—
—
D74
D73
—
—
Address : 000017H
• Port 8 direction register (DDR8)
Initial value
Access
R/W*
bit 7
—
bit 6
D86
bit 5
D85
bit 4
D84
bit 3
D83
bit 2
D82
bit 1
D81
bit 0
D80
-0000000B
Address : 000018H
• Port 9 direction register (DDR9)
Initial value
Access
R/W*
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
D90
Address : 000019H
• Port A direction register (DDRA)
D97
D96
D95
D94
D93
D92
D91
00000000B
Initial value
-----000B
Access
R/W*
bit 7
—
bit 6
—
bit 5
—
bit 4
—
bit 3
—
bit 2
DA2
bit 1
DA1
bit 0
DA0
Address : 00001AH
R/W : Readable and writable
: Unused
—
33
MB90650A Series
(Continued)
* : The operation of reading or writing to I/O ports is slightly different from reading or writing to memory, as follows.
• Input mode
Read: Reads the corresponding pin level.
Write: Writes to the output latch.
• Output mode
Read: Reads the value of the data register latch.
Write: The value is output from the corresponding pin.
When pins are used as ports, the register bits control the corresponding pins as follows.
0: Input mode
1: Output mode
Bits are set to “0” by a reset.
• P47, P70 to P72
No DDR for this port. Data is always available in this port, so when using P70 and P71 as I2C pin, set PDR
value to “1”. (Otherwise when using P70 and P71 by themselves, turn off the I2C.)
As this port is open-drain output style, so when using this port as an input port, in order to turn off the output
transister, set the output data resister value to “1” and add the pull up resister to the external pin.
34
MB90650A Series
(4) Port Resistance Registers
• Register configuration
• Port 0 resistance register (RDR0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value Access
00000000 R/W
Address : 00001C
H
H
H
RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00
B
• Port 1 resistance register (RDR1)
Initial value Access
00000000 R/W
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address : 00001D
• Port 6 resistance register (RDR6)
B
RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value Access
00000000 R/W
Address : 00001E
RD67 RD66 RD65 RD64 RD63 RD62 RD61 RD60
B
R/W : Readable and writable
• Block diagram
Pull-up resistor (approx. 50 kΩ)
Port I/O
Data register
Direction register
Resistance register
Notes: • Input resistance register R/W
Controls the pull-up resistor in input mode.
0: Pull-up resistor disconnected in input mode.
1: Pull-up resistor connected in input mode.
The setting has no meaning in output mode (pull-up resistor disconnected).
The direction register (DDR) sets input or output mode.
• The pull-up resistor is disconnected in hardware standby or stop mode (SPL = 1) (high impedance).
• This function is disabled when using an external bus mode. In this case, do not write to this register.
35
MB90650A Series
(5) Port Pin Register
• Register configuration
• Port 4 pin register (ODR4)
bit 7
—
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value Access
R/W
Address : 00001B
H
OD46 OD45 OD44 OD43 OD42 OD41 OD40 -0000000
B
R/W : Readable and writable
: Unused
—
• Block diagram
Port I/O
Data register
Direction register
Pin register
Notes: • Pin register R/W
Performs open-drain control in output mode.
0: Operate as a standard output port in output mode.
1: Operate as an open-drain output port in output mode.
The setting has no meaning in input mode (output Hi-z).
The direction register (DDR) sets input or output mode.
• This function is disabled when using an external bus mode. In this case, do not write to this register.
(6) Analog Input Enable Register
• Register configuration
• Analog input enable register (ADER)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
R/W R/W R/W R/W R/W
bit 8
Initial value Access
R/W
Address : 00001F
H
11111111
B
R/W
R/W
R/W
R/W : Readable and writable
Controls each port 5 pin as follows.
0: Port input mode
1: Analog input mode
Set to “1” by a reset.
36
MB90650A Series
2. UART
The UART is a serial I/O port that can be used for CLK asynchronous (start-stop synchronization) or CLK
synchronous communications. The UART has the following features.
• Full duplex, double buffered
• Supports asynchronous (start-stop synchronization) and CLK synchronous data transfer
• Supports multi-processor mode
• Built-in dedicated baud rate generator
Asynchronous : 9615 bps, 31250 bps, 4808 bps, 2404 bps and 1202 bps
For a 6, 8, 10, 12, or 16 MHz
CLK synchronous : 1 Mbps, 500 kbps, 250 kbps, 125 kbps, 115.2 kbps and 62.5 kbps
clock.
• Supports flexible baud rate setting using an external clock
• Error detect function (parity, framing, and overrun)
• NRZ type transmission signal
• Intelligent I/O service support
(1) Register Configuration
bit 15
bit 8 bit 7
bit 0
CDCR
SCR
—
SMR
SSR
SIDR (R) /SODR (W)
8 bits
8 bits
• Serial mode register 0 (SMR0)
bit 7
MD1 MD0
R/W R/W
bit 6
bit 5
bit 4
bit 3
CS0 Reserved SCKE SOE
R/W R/W R/W R/W
bit 2
bit 1
bit 0
Initial value
Address : 000020H
• Serial control register 0 (SCR0)
CS2
R/W
CS1
R/W
00000000B
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address : 000021H
PEN
R/W
P
SBL
R/W
CL
A/D
REC RXE
TXE
R/W
00000100B
R/W
R/W
R/W
W
R/W
• Serial input register/serial output register 0 (SIDR/SODR0)
Initial value
bit 7
bit 6
bit 5
bit 4
bit 3
D3
bit 2
D2
bit 1
D1
bit 0
D0
Address : 000022H
• Serial status register 0 (SSR0)
D7
D6
D5
D4
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W R/W
R/W R/W
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Initial value
PE
R
ORE FRE RDRF TDRE
—
—
RIE
TIE
00001-00B
Address : 000023H
• Clock division control register (CDCR)
R
R
R
R
R
/W
R/W
Initial value
0---1111B
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
MD
—
—
—
—
—
—
DIV3 DIV2 DIV1 DIV0
R/W R/W R/W R/W
Address : 000027H
R/W
R/W : Readable and writable
R
W
: Read only
: Write only
— : Unused
: Indeterminate
X
37
MB90650A Series
(2) Block Diagram
Control signals
Reception interrupt
(to CPU)
SCK0, SCK1
Dedicated baud rate generator
16-bit timer 0
Transmission clock
pulses
Transmission interrupt
(to CPU)
(Connected internally)
Clock select
circuit
Reception clock
pulses
External clock
Transmission control
Reception control
circuit
circuit
Start bit detection
circuit
Transmission start
circuit
SIN0
Reception bit
counter
Transmission bit
counter
Transmission parity
counter
Reception parity
counter
SOT0, SOT1
Reception status
determination circuit
Reception shifter
End of
Transmission shifter
Start of
transmission
Reception error
reception
occurrence signal
for I2OS
SODR
SIDR
(to CPU)
Internal data bus
MD1
MD0
CS2
CS1
CS0
PEN
P
PE
ORE
FRE
SBL
SMR
register
SCR
register
SSR
register
CL
RDRF
TDRE
A/D
REC
RXE
TXE
SCKE
SOE
RIE
TIE
Control signals
38
MB90650A Series
3. I/O Extended Serial Interface
I/O extended serial interface consists of an 8-bit serial I/O interface that can perform clock synchronous data
transfer. Either LSB-first or MSB-first data transfer can be selected.
The following two serial I/O operation modes are available.
• Internal shift clock mode: Data transfer is synchronized with the internal clock.
• External shift clock mode: Data transfer is synchronized with the clock input from the external pin (SCK). By
manipulating the general-purpose port that shares the external pin (SCK), this
mode also enables the data transfer operation to be driven by CPU instructions.
(1) Register Details
• Serial mode control status register 0, 1 (SMCS0, SMCS1)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address : 000025H
000029H
SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT
00000010B
R/W
bit 7
—
R/W
bit 6
—
R/W
bit 5
—
R/W R/W*1
R
R/W R/W*2
bit 1 bit 0
Initial value
bit 4
—
bit 3
bit 2
Address : 000024H
000028H
- - - - 0 0 0 0 B
MODE BDS SOE SCOE
—
—
—
R/W
R/W
R/W
R/W
—
• Serial data register 0, 1 (SDR0, SDR1)
Initial value
bit 7
D7
bit 6
D6
bit 5
D5
bit 4
D4
bit 3
D3
bit 2
D2
bit 1
D1
bit 0
D0
Address : 000026H
00002AH
XXXXXXXXB
R/W
R/W
R/W
R/W R/W
R/W
R/W R/W
R/W : Readable and writable
: Read only
— : Unused
R
X
: Indeterminate
*1: Only “0” can be written.
*2: Only “1” can be written. Reading always returns “0”.
This register controls the transfer operation mode of the serial I/O. The following describes the function of each bit.
bit 3: Serial mode selection bit (MODE)
This bit selects the conditions for starting operation from the halted state. Changing the mode during
operation is prohibited
MODE
Operation
Start when STRT is set to “1”. [Initial value]
0
1
Start on reading from or writing to the serial data register.
The bit is initialized to “0” by a reset. The bit is readable and writable. Set to “1” when using the intelligent I/O
service.
bit 2: Transfer direction selection bit (BDS: Bit Direction Select)
Selects as follows at the time of serial data input and output whether the data are to be transferred in
the order from LSB to MSB or vice versa.
MODE
Operation
0
1
LSB-first [Initial value]
MSB-first
39
MB90650A Series
(2) Block Diagram
Internal data bus
(MSB-first) D0 to D7
SIN1, SIN2
D7 to D0 (LSB-first)
Transfer direction selection
Read
Write
SDR (Serial data register)
SOT1, SOT2
SCK1, SCK2
Control circuit
Shift clock counter
Internal clock
2
1
0
SMD2 SMD1 SMD0 SIE
SIR BUSY STOP STRT MODE BDS SOE SCOE
Interrupt
request
Internal data bus
40
MB90650A Series
4. A/D Converter
The A/D converter converts analog input voltages to digital values. The A/D converter has the following features.
• Conversion time: Minimum of 5.2 µs per channel (for a 16 MHz machine clock)
• Uses RC-type successive approximation conversion with a sample and hold circuit.
• 10-bit resolution
• Eight program-selectable analog input channels
Single conversion mode:
Scan conversion mode:
Selectively convert a one channel.
Continuously convert multiple channels. Maximum of 8 program-
selectable channels.
Continuous conversion mode : Repeatedly convert specified channels.
Stop conversion mode: Convert one channel then halt until the next activation. (Enables
synchronization of the conversion start timing.)
• An A/D conversion completion interrupt request to the CPU can be generated on the completion of A/D
conversion. This interrupt can activate I2OS to transfer the result of A/D conversion to memory and is suitable
for continuous operation.
• Activation by software, external trigger (falling edge), or timer (rising edge) can be selected.
(1) Register Configuration
bit 15
bit 8 bit 7
bit 0
ADCS2
ADCS1
ADCR2
8 bits
ADCR1
8 bits
• Control status register 1 (ADCS1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
Address : 000036
H
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
00000000
B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 8
• Control status register 2 (ADCS2)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
BUSY INT INTE PAUS STS1 STS0 STRT
Address : 000037
H
DA
00000000
B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Data register 1 (ADCR1)
• Data register 2 (ADCR2)
Initial value
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address : 000038
H
7
6
5
4
3
2
1
0
XXXXXXXX
B
R
R
R
R
R
R
R
R
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address : 000039
H
—
R
—
R
—
R
—
R
—
R
—
R
9
8
XXXXXXXX
B
R
R
: Readable and writable
: Read only
: Indeterminate
R/W
R
X
41
MB90650A Series
(2) Block Diagram
AVCC
AVRH
AVRL
AVSS
D/A converter
MPX
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Successive
approximation register
Comparator
Sample and
hold circuit
Data register
ADCR1, ADCR2
A/D control register 1
A/D control register 2
ADCS1, ADCS2
Trigger activation
ADTG
Timer activation
PPG01
Operating clock
Prescaler
φ
42
MB90650A Series
5. D/A Converter
D/A converter is an R-2R type D/A converter with 8-bit resolution. The device contains two D/A converters. The
D/A control register controls the output of the two D/A converters independently.
(1) Register Configuration
• D/A converter data register 0 (DAT0)
Initial value
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address : 00003AH
• D/A converter data register 1 (DAT1)
DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00
XXXXXXXXB
R/W
R/W
R/W R/W
R/W
R/W
R/W
R/W
bit 8
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
Address : 00003BH
• D/A control register channel 0 (DACR0)
DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10
XXXXXXXXB
R/W
bit 7
R/W
bit 6
R/W
bit 5
R/W
bit 4
R/W
bit 3
R/W
bit 2
R/W
bit 1
R/W
bit 0
Initial value
-------0 B
Address : 00003CH
• D/A control register channel 1 (DACR1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DAE0
R/W
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Initial value
-------0 B
Address : 00003DH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DAE1
R/W
R/W : Readable and writable
— : Unused
X
: Indeterminate
43
MB90650A Series
(2) Block Diagram
Internal data bus
DA DA DA DA DA DA DA DA
17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA
07 06 05 04 03 02 01 00
DVR
DVR
DA17
DA07
2R
2R
R
R
DA16
DA06
2R
R
2R
R
DA15
DA11
DA05
DA01
2R
R
2R
R
DA10
DA00
2R
2R
2R
2R
DAE1
Standby control
DAE0
Standby control
DA output
channel 1
DA output
channel 0
44
MB90650A Series
6. 8/16-bit PPG
8/16-bit PPG is an 8-bit reload timer module. The block performs PPG output in which the pulse output is
controlled by the operation of the timer.
The hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two
external pulse output pins, and two interrupt outputs. The PPG has the following functions.
• 8-bit PPG output in two channels independent operation mode:
Two independent PPG output channels are available.
• 16-bit PPG output operation mode : One 16-bit PPG output channel is available.
• 8 + 8-bit PPG output operation mode : Variable-period 8-bit PPG output operation is available by using the
output of channel 0 as the clock input to channel 1.
• PPG output operation :
Outputs pulse waveforms with variable period and duty ratio. Can be
used as a D/A converter in conjunction with an external circuit.
(1) Register Configuration
• PPG0 operation mode control register channel 0 (PPGC0)
Initial value
0X000XX1
bit 7
bit 6
—
bit 5
PE00 PIE0 PUF0
R/W R/W R/W
bit 4
bit 3
bit 2
—
bit 1
—
bit 0
Reserved
—
Address : 000044
H
PEN0
R/W
B
B
B
—
—
—
• PPG1 operation mode control register channel 1 (PPGC1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
Initial value
0X000001
bit 8
Address : 000045
H
PEN1
R/W
—
—
PE10 PIE1 PUF1 MD1 MD0 Reserved
R/W
R/W
bit 4
R/W
bit 3
R/W
bit 2
R/W
bit 1
—
• PPG0, PPG1 output control register channel 0, channel 1 (PPGOE)
bit 7 bit 6 bit 5
Initial value
00000000
bit 0
Address : 000046
H
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01
R/W
R/W R/W
R/W
R/W
R/W
R/W
R/W
• Reload register upper channel 0, channel 1 (PRLH0, PRLH1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
Initial value
bit 8
R/W
Address : 000041
H
H
XXXXXXXX
B
000043
R/W
R/W R/W
R/W
R/W
R/W
R/W
• Reload register lower channel 0, channel 1 (PRLL0, PRLL1)
Initial value
XXXXXXXX
bit 7
R/W
bit 6
bit 5
bit 4
R/W
bit 3
R/W
bit 2
R/W
bit 1
R/W
bit 0
R/W
Address : 000040
H
H
B
000042
R/W R/W
R/W : Readable and writable
: Indeterminate
X
45
MB90650A Series
(2) Block Diagram
• 8/16-bit PPG (channel 0)
PPG00 output enable
PPG01 output enable
PPG00
PPG01
Peripheral clock divided by 16
Peripheral clock divided by 8
Peripheral clock divided by 4
Peripheral clock divided by 2
Peripheral clock
A/D converter
PPG0
output latch
Invert
Clear
PEN0
S
R
Q
PCNT (Down-counter)
Reload
IRQ
Count clock
selection
Channel 1-borrow
Timebase counter output
Main clock divided by 512
L/H selector
L/H select
PRLL0
PRLH0
PRLBH0
PIE0
PUF0
L-side data bus
H-side data bus
PPGC0
(Operation mode control)
46
MB90650A Series
• 8/16-bit PPG (channel 1)
PPG10 output enable
PPG10
PPG11
Peripheral clock divided by 16
Peripheral clock divided by 8
Peripheral clock divided by 4
Peripheral clock divided by 2
Peripheral clock
PPG11 output enable
UART
PPG1
output latch
Invert
Clear
Count clock
selection
PEN1
S
Q
R
PCNT (Down-counter)
Reload
IRQ
Channel 0-borrow
Timebase counter output
Main clock divided by 512
L/H selector
L/H select
PRLL1
PRLH1
PRLBH1
PIE
PUF
L-side data bus
H-side data bus
PPGC1
(Operation mode control)
47
MB90650A Series
7. 8/16-bit Up/Down Counter/Timer
8/16-bit up/down counter/timer is an up/down counter/timer and consists of six event input pins, two 8-bit up/
down counters, two 8-bit reload/compare registers, and their control circuits.
(1) Main Functions
• The 8-bit count register can count in the range 0 to 256 (or 0 to 65535 in 1 × 16-bit operation mode).
• The count clock selection can select between four different count modes.
Count modes
Timer mode
Up/down counter mode
Phase difference count mode (× 2)
Phase difference count mode (× 8)
• Two different internal count clocks are available in timer mode.
Count clock (at 16 MHz operation)
125 ns (8 MHz: Divide by 2)
0.5 µs (1 MHz: Divide by 8)
• In up/down count mode, you can select which edge to detect on the external pin input signal.
Detected edge
Detect falling edges
Detect rising edges
Detect both rising and falling edges
Edge detection disabled
• Phase difference count mode is suitable for motor encoder counting. By inputting the A, B, and Z phase outputs
from the encoder, a high-precision rotational angle, speed, or similar count can be implemented simply.
• Two different functions can be selected for the ZIN pin.
ZIN pin
Counter clear function
Gate function
• Compare and reload functions are available and can be used either independently or together. A variable-
width up/down count can be performed by activating both functions.
Compare/reload function
Comparefunction(Outputaninterruptwhenacompare
occurs.)
Compare function (Output an interrupt and clear the
counter when a compare occurs.)
Reload function (Output an interrupt and reload when
an underflow occurs.)
Compare/reload function
(Output an interrupt and clear the counter when a
compare occurs. Output an interrupt and reload when
an underflow occurs.)
Compare/reload disabled
• Whether or not to generate an interrupt when a compare, reload (underflow), or overflow occurs can be set
independently.
• The previous count direction can be determined from the count direction flag.
• An interrupt can be generated when the count direction changes.
48
MB90650A Series
(2) Register Configuration
bit 15
bit 8 bit 7
bit 0
UDCR1
RCR1
UDCR0
RCR0
CSR0
(Reversed area)
CCRH0
CCRL0
CSR1
(Reversed area)
CCRH1
8 bits
CCRL1
8 bits
• Up/down count register channel 0 (UDCR0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
Address : 000070
H
D07
R
D06
R
D05
R
D04
R
D03
R
D02
R
D01
R
D00
R
00000000
B
• Up/down count register channel 1 (UDCR1)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address : 000071
H
H
H
D17
R
D16
R
D15
R
D14
R
D13
R
D12
R
D11
R
D10
R
00000000
B
• Reload compare register channel 0 (RCR0)
Initial value
bit 7
D07
W
bit 6
D06
W
bit 5
D05
W
bit 4
D04
W
bit 3
D03
W
bit 2
D02
W
bit 1
D01
W
bit 0
D00
W
Address : 000072
00000000
B
• Reload compare register channel 1 (RCR1)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address : 000073
D17
W
D16
W
D15
W
D14
W
D13
W
D12
W
D11
W
D10
W
00000000
B
• Counter status register channel 0, channel 1 (CSR0, CSR1)
Initial value
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address : 000074
H
H
00000000
B
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
000078
R/W
R/W
R/W R/W
R/W
R/W
R
R
• Counter control register channel 0, channel 1 (CCRL0, CCRL1)
bit 7
bit 6
bit 5 bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
Address : 000076
00007A
H
H
00001000
00000000
B
–
–
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
B
R/W
R/W R/W
R/W
R/W
R/W
R/W
• Counter control register channel 0 (CCRH0)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address : 000077
H
00000000
B
M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
R/W
R/W
R/W R/W
R/W
R/W
R/W
R/W
• Counter control register channel 1 (CCRH1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Initial value
X0001000
Address : 00007B
H
B
–
–
CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
R/W R/W R/W R/W R/W R/W R/W
: Readable and writable
: Read only
: Write only
R/W
R
W
–
X
: Unused
:
Indeterminate
49
MB90650A Series
(3) Block Diagram
• 8/16-bit up/down counter/timer (channel 0)
Internal data bus
8 bits
RCR0 (Reload/compare register 0)
CGE1 CGE0 C/GS
CTUT
Reload control
ZIN0
Edge or level detection
UCRE
RLDE
UDCC
Counter clear
8 bits
UDCR0 (Up/down count register 0)
Carry
CMPF
CES1 CES0
CMS1 CMS0
UDFF OVFF
CITE UDIE
Count clock
UDF1 UDF0 CDCF CFIE
AIN0
BIN0
Up/down count
clock selection
Interrupt output
Prescaler
CLKS
CSTR
50
MB90650A Series
• 8/16-bit up/down counter/timer (channel 1)
Internal data bus
8 bits
RCR1 (Reload/compare register 1)
CGE1 CGE0 C/GS
Edge or level detection
CTUT
Reload control
ZIN1
UCRE
RLDE
Counter clear
8 bits
UDCR1 (Up/down count register 1)
UDCC
CMPF
UDFF OVFF
CMS1 CMS0 CES1 CES0 EN16
Carry
CITE UDIE
Count clock
UDF1 UDF0 CDCF CFIE
Interrupt output
AIN1
BIN1
Up/down count
clock selection
Prescaler
CSTR
CLKS
51
MB90650A Series
8. Clock Output Control Register
Clock output control register outputs the divided machine clock.
(1) Register Configuration
• Clock control register (CLKR)
Initial value
----0000B
bit 7
—
bit 6
—
bit 5
—
bit 4
—
bit 3
CKEN FRQ2 FRQ1 FRQ0
R/W R/W R/W R/W
bit 2
bit 1
bit 0
Address : 00003EH
R/W : Readable and writable
— : Unused
bit 3: Clock output enable bit (CKEN)
MODE
Operation
0
1
Operate as a standard port.
Operate as the clock output.
bit 2 to bit 0: Clock output frequency select bit (FRQ2 to FRQ0)
FRQ2
FRQ1
FRQ0
Output clock
φ/21
φ = 16 MHz
125 ns
250 ns
500 ns
1 µs
φ = 8 MHz
250 ns
500 ns
1 µs
φ = 4 MHz
500 ns
1 µs
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
φ/22
φ/23
2 µs
φ/24
2 µs
4 µs
φ/25
2 µs
4 µs
8 µs
φ/26
4 µs
8 µs
16 µs
32 µs
64 µs
φ/27
8 µs
16 µs
32 µs
φ/28
16 µs
52
MB90650A Series
9. DTP/External Interrupts
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16L
CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the
requests to the F2MC-16L CPU to activate the intelligent I/O service or interrupt processing. Two request levels
(“H” and “L”) are provided for the intelligent I/O service. For external interrupt requests, generation of interrupts
on a rising or falling edge as well as on “H” and “L” levels can be selected, giving a total of four types.
(1) Register Configuration
• Interrupt/DTP enable register (ENIR)
bit 7
bit 6
bit 5
bit 4
EN4
bit 3
EN3
bit 2
EN2
bit 1
EN1
bit 0
Initial value
Address : 000030H
• Interrupt/DTP source register (EIRR)
EN7
R/W
EN6
R/W
EN5
R/W
EN0
R/W
00000000B
R/W R/W
R/W R/W
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address : 000031H
• Request level setting register (ELVR)
ER7
R/W
ER6
R/W
ER5
R/W
ER4
ER3
ER2
ER1
ER0
R/W
00000000B
R/W R/W
R/W R/W
Initial value
bit 7
bit 6
bit 5
bit 4
LA2
bit 3
LB1
bit 2
LA1
bit 1
LB0
bit 0
00000000B
Address : 000032H
LB3
R/W
LA3
R/W
LB2
R/W
LA0
R/W
R/W R/W
R/W R/W
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address : 000033H
LB7
R/W
LA7
R/W
LB6
R/W
LA6
LB5
LA5
LB4
LA4
R/W
00000000B
R/W R/W
R/W R/W
R/W : Readable and writable
(2) Block Diagram
4
4
4
8
Interrupt/DTP enable register
Request F/F
4
Gate
Edge detect circuit
Request input
Interrupt/DTP source register
Request level setting register
53
MB90650A Series
10. 16-bit I/O Timer
The 16-bit I/O timer consists of one 16-bit free-run timer, two output compare, and two input capture modules.
Based on the 16-bit free-run timer, these functions can be used to generate two independent waveform outputs
and to measure input pulse widths and external clock periods.
• Register configuration
• 16-bit free-run timer
bit 15
bit 0
TCDTL : 000066H
TCDTH : 000067H
TCDT
Timer data register lower, upper (TCDTL, TCDTH)
Timer control status register (TCCS)
TCCS : 000068H
TCCS
• 16-bit output compare
bit 15
bit 0
OCCP0 : 000050H, 51H
OCCP1 : 000052H, 53H
OCCP2 : 000054H, 55H
OCCP3 : 000056H, 57H
Compare register channel 0 to channel 3
lower, upper (OCCP0 to OCCP3)
OCCP
OCS
OCS0 : 000058H
OCS1 : 000059H
OCS2 : 00005AH
OCS3 : 00005BH
Compare control status register
channel 0 to channel 3 (OCS0 to OCS3)
• 16-bit input capture
bit 15
bit 0
IPCP0 : 000060H, 61H
IPCP1 : 000062H, 63H
Input capture register channel 0, channel 1
lower, upper (IPCP0, IPCP1)
IPCP
ICS0, 1 : 000064H
ICS
Input capture control status register (ICS0, 1)
• Block diagram
Control logic
16-bit timer
Interrupt
16-bit free-run timer
Clear
Output compare 0
OUT0
OUT1
OUT2
OUT3
Compare register 0
Output compare 1
Compare register 1
Output compare 2
Compare register 2
Output compare 3
TQ
TQ
TQ
TQ
Compare register 3
Input capture 0
IN0
IN1
Capture register 0
Capture register 1
Edge selection
Edge selection
54
MB90650A Series
(1) 16-bit Free-run Timer
The 16-bit free-run timer consists of a 16-bit up-counter, a control register, and a prescaler. The output of the
timer/counter is used as the base time for the input capture and output compare.
• The operating clock for the counter can be selected from four different clocks.
Four internal clocks (φ/4, φ/16, φ/32, φ/64)
• Interrupts can be generated when a counter value overflow or compare match with compare register 0 occurs
(the appropriate mode must be set for a compare match).
• The counter can be initialized to 0000H by a reset, software clear, or compare match with compare register 0.
• Register details
• Upper timer data register (TCDTH)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
T08
R/W
Address : 000067H
T15
T14
T13
T12
T11
T10
T09
00000000B
R/W
R/W R/W
R/W
R/W
R/W
R/W
• Lower timer data register (TCDTL)
Initial value
bit 7
bit 6
T06
bit 5
T05
bit 4
bit 3
bit 2
bit 1
bit 0
T00
R/W
Address : 000066H
T07
T04
T03
T02
T01
00000000B
R/W
R/W R/W
R/W
R/W
R/W
R/W
R/W : Readable and writable
The count value of the 16-bit free-run timer can be read from this register. The count is cleared to “0000B” by a
reset. Writing to this register sets the timer value. However, only write to the register when the timer is halted
(STOP = “1”). Always use word access.
The 16-bit free-run timer is initialized by the following.
• Reset
• The clear bit (CLR) of the control status register
• A match between the timer/counter value and compare register 0 of the output compare (if the appropriate
mode is set)
• Block diagram
φ
Interrupt request
IVF IVFE STOP MODE CLR CLK1 CLK0
Divider
Comparator 0
Clock
16-bit up-counter
Count value output T15 to T00
55
MB90650A Series
(2) Output Compare
The output compare consists of two 16-bit compare registers, compare output latches, and control registers.
The modules can invert the output level and generate an interrupt when the 16-bit free-run timer value matches
the compare register value.
• The four compare registers can be operated independently.
Each compare register has a corresponding output pin and interrupt flag.
• The four compare registers can be paired to control the output pins.
Invert the output pins using the four compare registers.
• Initial values can be set for the output pins.
• An interrupt can be generated when a compare match occurs.
• Register configuration
• Upper compare register channel 0 to channel 3 (OCCP0 to OCCP3)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Initial value
OCCP0 : 000051H
OCCP1 : 000053H
OCCP2 : 000055H
OCCP3 : 000057H
XXXXXXXXB
C15
R/W
C14
R/W
C13
C12
C11
R/W
C10
R/W
C09
R/W
C08
R/W
R/W R/W
• Lower compare register channel 0 to channel 3 (OCCP0 to OCCP3)
bit 7
bit 6
bit 5
bit 4
C04
bit 3
bit 2
bit 1
bit 0
Initial value
OCCP0 : 000050H
OCCP1 : 000052H
OCCP2 : 000054H
OCCP3 : 000056H
XXXXXXXXB
C07
R/W
C06
R/W
C05
C03
R/W
C02
R/W
C01
R/W
C00
R/W
R/W R/W
• Compare control status register channel 0 to channel 3 (OCS0 to OCS3)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Initial value
---00000B
OCS1 : 000059H
OCS3 : 00005BH
—
—
—
—
—
—
CMOD OTE1 OTE0 OTDI OTD0
R/W
bit 4
R/W
R/W
R/W
bit 1
R/W
bit 0
bit 7
bit 6
bit 5
bit 3
—
bit 2
—
Initial value
0000--00B
OCS0 : 000058H
OCS2 : 00005AH
ICP1 ICP0 ICE1 ICE0
R/W R/W R/W R/W
CST1 CST0
R/W R/W
—
—
R/W: Readable and writable
— : Unused
X
: Indeterminate
56
MB90650A Series
• Block diagram
16-bit timer/counter value (T15 to T00)
OUT0
OTEO
TQ
Compare control
(OUT2)
Compare register 0 (2)
CMOD
TQ
16-bit timer/counter value (T15 to T00)
OUT1
(OUT3)
OTE1
Compare control
Compare register 1 (3)
ICP1 ICP0 ICE1 ICE0
Compare 1 interrupt (3)
Compare 0 interrupt (2)
Controller
Control blocks
57
MB90650A Series
(3) Input Capture
The input capture consists of two independent external input pins, their corresponding capture registers, and
a control register. The value of the 16-bit free-run timer can be stored in the capture register and an interrupt
generated when the specified edge is detected on the signal from the external input pin.
• The edge to detect on the external input signal is selectable.
Detection of rising edges, falling edges, or either edge can be specified.
• The two input capture channels can operate independently.
• An interrupt can be generated on detection of the specified edge on the external input signal.
The input capture interrupt can activate the intelligent I/O service.
• Register details
• Input capture register channel 0, channel 1 (IPCP0, IPCP1)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
IPCP0 : 000061H
IPCP1 : 000063H
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08
XXXXXXXXB
R
R
R
R
R
R
R
R
Initial value
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IPCP0 : 000060H
IPCP1 : 000062H
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 XXXXXXXXB
R
R
R
R
R
R
R
R
• Input capture control status register (ICS0, 1)
Initial value
00000000B
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable and writable
000064H
R
X
: Read only
: Indeterminate
The 16-bit free-run timer value is stored in these registers when the specified edge is detected on the input
waveform from the corresponding external pin. (Always use word access. Writing is prohibited.)
• Block diagram
IN0
Capture data register 0
16-bit timer/counter value (T15 to T00)
Capture data register 1
Edge detection
EG11 EG10 EG01 EG00
IN1
Edge detection
ICP1 ICP0 ICE1 ICE0
Interrupt
Interrupt
58
MB90650A Series
11. Watchdog Timer, Timebase Timer, and Watch Timer
The watchdog timer consists of a 2-bit watchdog counter that uses the carry signal from the 18-bit timebase
timer or the 15-bit watch timer as aclock source, a control register, and a watchdog reset controller.
The timebase timer consists of an 18-bit timer and a circuit that controls interval interrupts. Note that the timebase
timer uses the main clock, regardless of the setting of the MCS bit and SCS bit in CKSCR.
The watch timer consists of a 15-bit timer and a circuit that controls interval interrupts. Note that the watch timer
uses the sub clock, regardless of the setting of the MCS bit SCS bit in CKSCR.
(1) Register Configuration
• Watchdog timer control register (WDTC)
Initial value
WRST ERST SRST WTE WT1 WT0 XXXXX111B
bit 7
PONR
R
bit 6
—
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address : 0000A8H
—
R
R
R
W
W
W
• Timebase timer control register (TBTC)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
TBIE TBOF TBR TBC1 TBC0
R/W R/W R/W R/W
Address : 0000A9H Reserved
—
—
—
—
—
1--00000B
W
• Watch timer control register (WTC)
Initial value
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address : 0000AAH
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 1X000000B
R/W R/W R/W R/W R/W R/W
R
R
R/W : Readable and writable
R
W
: Read only
: Write only
— : Unused
: Indeterminate
X
59
MB90650A Series
(2) Block Diagram
Main clock
TBTC
TBC1
212
Clock input
214
Selector
216
Timebase timer
219
TBC0
212 214 216 219
TBTRES
TBR
S
R
TBIE
AND
Q
TBOF
Timebase
interrupt
WDTC
Watchdog reset
generator
2-bit counter
WT1
WT0
Selector
OF
WDGRST
To internal reset
generator
CLR
CLR
WTE
WTC
AND
SCM
WDCS
Power-on reset
sub clock stops
S
R
SCE
Q
210 213 214 215
Watch timer
Clock input
210
213
214
215
WTC1
WTC0
Selector
WTR
WTIE
WTRES
S
Sub clock
AND
Q
R
WTOF
Timer
interrupt
WDTC
PONR
From power-on generation
WRST
ERST
SRST
RST pin
From RST bit in
the STBYC register
60
MB90650A Series
12. I2C Interface
The I2C interface is a serial I/O port that supports the Inter-IC bus and operates as a master/slave device on
the I2C bus. This module has the following features:
• Master/slave transmission/reception
• Arbitration function
• Clock synchronization function
• Slave address/general call address detection function
• Transfer direction detection function
• Start condition repeat generation and detection function
• Bus error detection function
(1) Register Configuration
• I2C bus status register (IBSR)
Initial value
bit 7
BB
R
bit 6
RSC
R
bit 5
AL
R
bit 4
LRB
R
bit 3
TRX
R
bit 2
bit 1
bit 0
FBT
R
Address : 000080H
AAS GCA
00000000B
R
R
• I2C bus control register (IBCR)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
BER BEIE SCC MSS ACK GCAA INTE
bit 8
INT
Address : 000081H
00000000B
R/W
R/W
R/W R/W
R/W
R/W
R/W
R/W
• I2C bus clock control register (ICCR)
Initial value
bit 7
bit 6
bit 5
EN
bit 4
bit 3
bit 2
bit 1
CS1
R/W
bit 0
CS0
R/W
Address : 000082H
—
—
—
—
CS4
R/W
CS3
R/W
CS2
R/W
--0XXXXXB
R/W
• I2C bus address register (IADR)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address : 000083H
—
—
A6
A5
A4
A3
A2
A1
A0
-XXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• I2C bus data register (IDAR)
Initial value
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D0
Address : 000084H
D7
D6
D5
D4
D3
D2
D1
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable and writable
R
—
X
: Read only
: Unused
: Indeterminate
61
MB90650A Series
(2) Block Diagram
ICCR
EN
I2C enable
Peripheral clock
Clock divider 1
ICCR
CS4
5
6
7
8
Clock selection 1
CS3
CS2
CS1
CS0
Clock divider 2
Sync
2 4 8 16 32 64 128 256
Shift clock generation
Clock selection 2
Shift clock edge
change timing
IBSR
BB
Bus busy
Repeat start
Last bit
RSC
LRB
TRX
FBT
AL
Start/stop
condition generation
Error
Transmit/receive
First byte
Arbitration lost detection
IBCR
BER
SCL
SDA
BEIE
INTE
INT
IRQ
Interrupt request
End
IBCR
SCC
Start
Master
MSS
ACK
Start/stop
condition generation
ACK enable
GC-ACK enable
GCAA
IDAR
IBSR
AAS
Slave
Slave address
comparison
Global call
GCA
IADR
62
MB90650A Series
13. External Bus Pin Control Circuit
The external bus pin control circuit controls the external bus pins required to extend the CPU’s address/data
bus outside the device.
(1) Register Configuration
• Auto-ready function selection register (ARSR)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address : 0000A5H
ICR1 ICR0 HMR1 HMR0
—
—
—
—
LMR1 LMR0
0011--00B
W
W
W
W
W
W
• External address output control register (HACR)
Initial value
00000000B
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
E16
W
Address : 0000A6H
E23
W
E22
W
E21
W
E20
W
E19
W
E18
W
E17
W
• Bus control signal selection register (ECSR)
Initial value
0000*00-B
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
CKE RYE HDE ICBS HMBS WRE LMBS
bit 8
Address : 0000A7H
—
—
W
W
W
W
W
W
W
: Write only
: Unused
: “1” or “0”
W
—
*
(2) Block Diagram
P3
P2
P1
P3
P0
P0
P0 data
P0 direction
RB
Data control
Address control
Access control
Access control
63
MB90650A Series
14. Low-power Consumption Mode (CPU Intermittent Operation Function, Oscillation
Stabilization Delay Time, Clock Multiplier Function)
The following are the operating modes: PLL clock mode, PLL sleep mode, PLL watch mode, pseudo-watch
mode, main clock mode, main sleep mode, main watch mode, main stop mode, sub clock mode, sub sleep
mode, sub watch mode, and sub stop mode. Aside from the PLL clock mode, all of the other operating modes
are low-power consumption modes.
In main clock mode and main sleep mode, the main clock (main OSC oscillation clock) and the sub clock (sub
OSC oscillation clock) operate. In these modes, the main clock divided by 2 is used as the operation clock, the
sub clock (sub OSC oscillation clock) is used as the timer clock, and the PLL clock (VCO oscillation clock) is
stopped.
In sub clock mode and sub sleep mode, only the sub clock operates. In these modes, the sub clock is used as
the operation clock, and the main clock and PLL clock are stopped.
In PLL sleep mode and main sleep mode, only the CPU’s operation clock is stopped; all clocks other than the
CPU clock operate.
In pseudo-watch mode, only the watch timer and timebase timer operate.
In PLL watch mode, main watch mode, and sub watch mode, only the watch timer operates. In this mode, only
the sub clock is used for operation, while the main clock and the PLL clock are stopped (the difference between
the PLL watch mode, the main watch mode and the sub watch mode is that it resumes operation after an interrupt
in the PLL clock mode, the main clock mode, and the sub clock mode respectively, and there is no reference
concerning about clock mode operation).
The main stop mode, sub stop mode, and hardware standby mode stop oscillation, making it possible to retain
data while consuming the least amount of power. (The difference between the main stop mode and the sub stop
mode is that it resumes operation in the main clock mode and the sub clock mode respectively, and there is no
reference concerning about stop mode operation).
The CPU intermittent operation function intermittently runs the clock supplied to the CPU when accessing
registers, on-chip memory, on-chip resources, and the external bus. Processing is possible with lower power
consumption by reducing the execution speed of the CPU while supplying a high-speed clock and using on-chip
resources.
The PLL clock multiplier can be selected as either 2, 4, 6, or 8 by setting the CS1 and CS0 bits. These clocks
are divided by 2 to be used as a machine clock.
The WS1 and WS0 bits can be used to set the main clock oscillation stabilization delay time for when stop mode
is woken up.
64
MB90650A Series
(1) Register Configuration
• Low-power consumption mode control register (LPMCR)
Initial value
bit 7
bit 6
SLP
W
bit 5
SPL
R/W
bit 4
RST TMD CG1 CG0
R/W R/W
bit 3
bit 2
bit 1
bit 0
—
Address : 0000A0
H
STP
W
00011000
B
W
W
• Clock selection register (CKSCR)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
SCM MCM WS1 WS0 SCS MCS CS1
bit 8
Address : 0000A1
H
CS0
R/W
11111100
B
R
R
R/W
R/W
R/W
R/W
R/W
: Readable and writable
: Read only
: Write only
R/W
R
W
: Unused
—
65
MB90650A Series
(2) Block Diagram
• Low-power consumption control circuit and clock generator
CKSCR
Sub clock divided by 4
(OSC oscillation)
Sub clock
SCM
SCS
switching control
CKSCR
MCM
Main clock
(OSC oscillation)
PLL multiplier
circuit
MCS
1
2
3
4
CPU
CPU clock
system clock
generation
CKSCR
CS1
1/2 S
CPU
0/9/17/33
intermittent cycle selection
Clock selector
CS0
LPMCR
CG1
CPU intermittent
operation function
Cycle count
CG0
selection circuit
Peripheral
clock
Peripheral clock
generation
LPMCR
SLP
SCM
SLEEP
Standby
controller
Main OSC stop
Sub OSC stop
STP
MSTP
STOP
TMD
RST
cancel
Interrupt request
or RST
CKSCR
WS1
Clock input
Timebase timer
212 214 216 219
24
Oscillation
213
215
218
stabilization
delay time
selector
WS0
LPMCR
SPL
Pin Hi-Z
Pin high-impedance controller
RST pin
LPMCR
RST
Internal reset
generator
Internal RST
To watchdog timer
WDGRST
66
MB90650A Series
• State transition diagram for clock selection (1)
Power-on
Main → PLL
×
Main
<2>
SCS = 1, MSC = 0
SCM = 1, MCM = 1
CS1/0 = ××
SCS = 1, MCS = 1
SCM = 1, MCM = 1
CS1/0 = ××
<1>
<3>
<7>
PLL1 → Main
PLL 1 multiplier
SCS = 1, MSC = 0
SCM = 1, MCM = 0
CS1/0 = 00
SCS = 0 or MCS = 0
SCM = 1, MCM = 0
<4>
<6>
<7> CS1/0 = 00
<7>
Sub → PLL×
PLL2
→
Main
PLL 2 multiplier
SCS = 1, MSC = 0
SCM = 1, MCM = 0
CS1/0 = 01
SCS = 1, MCS = 0
SCM = 0, MCM = 1
CS1/0 = ××
SCS = 0 or MCS = 1
SCM = 1, MCM = 0
CS1/0 = 01
<9>
<8>
<6>
<5>
<7>
PLL3
→ Main
PLL 3 multiplier
SCS = 1, MSC = 0
SCM = 1, MCM = 0
CS1/0 = 10
SCS = 0 or MCS = 1
SCM = 1, MCM = 0
CS1/0 = 10
<6>
<8>
<8>
<8>
Main → Sub
SCS = 0, MCS = ×
MCM = 1
PLL4
→ Main
PLL 4 multiplier
SCS = 1, MSC = 0
SCM = 1, MCM = 0
CS1/0 = 11
SCS = 0 or MCS = 1
SCM = 1, MCM = 0
CS1/0 = 11
<6>
SCM = 1
<1> MCS bit cleared and SCS bit set
<2> PLL clock oscillation stabilization delay complete and CS1/0 = 00
<3> PLL clock oscillation stabilization delay complete and CS1/0 = 01
<4> PLL clock oscillation stabilization delay complete and CS1/0 = 10
<5> PLL clock oscillation stabilization delay complete and CS1/0 = 11
<6> MCS bit set or SCS bit cleared
<7> PLL clock and main clock synchronized timing and SCS = 1
<8> PLL clock and main clock synchronized timing and SCS = 0
<9> Main clock oscillation stabilization delay complete and MCS = 0
67
MB90650A Series
• State transition diagam for clock selection (2)
Power-on
<1>
Main → Sub
SCS = 0
Main
SCS = 1, MCS = 1
SCM = 1
SCM = 1
MCM = 1
MCM = 1
<2>
<4>
Sub
Sub → Main
SCS = 1
<5>
PLL× → Sub
SCS = 0
SCM = 0
MCM = 1
SCS = 0, MCS = ×
SCM = 1, MCM = 0
CS1/0 = ××
SCM = 0
MCM = 1
<3>
<6>
Main → PLL×
SCS = 1, MCS = 0
SCM = 1, MCM = 1
CS1/0 = ××
<1> SCS bit cleared
<2> Sub clock edge detection timing
<3> SCS bit set
<4> Main clock oscillation stabilization delay complete and MCS = 1
<5> PLL clock and main clock synchronized timing and SCS = 0
<6> Main clock ascillation stabilization delay complete and MCS = 0
68
MB90650A Series
15. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to
the F2MC-16L CPU can be generated and cleared by software using this module.
(1) Register Details
• Delayed interrupt generation /release register (DIRR)
Initial value
-------0B
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
R0
Address : 00009FH
—
—
—
—
—
—
—
R/W
: Readable and writable
: Unused
R/W
—
The DIRR register controls generation and clearing of delayed interrupt requests. Writing “1” to the register
generates a delayed interrupt request. Writing “0” to the register clears the delayed interrupt request. The register
is set to the interrupt cleared state by a reset. Either “0” or “1” can be written to the reserved bits. However,
considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for
register access.
(2) Block Diagram
Delayed interrupt generation/release decoder
Interrupt latch
69
MB90650A Series
16. DTMF Generator
The DTMF (dual tone multifrequency) generator is a module that can generate a series of audio tones as heard
from a push-button telephone or a radio transceiver with a keypad. It has the following features:
Capable of generating DTMF tones continuously (or even a single tone)
Capable of generating all CCITT tones: 0 to 9, *, #, A to D
(1) Register list
• DTMF control register (DTMC)
Initial value
bit 7
bit 6
CSL2 CSL1 CSL0 CDIS RDIS OUTE
R/W
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
—
Address : 000088H
Address : 000089H
—
—
00000000B
—
R/W
R/W
R/W
R/W
R/W
• DTMF data register (DTMD)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
—
—
—
—
—
—
—
—
DDAT3 DDAT2 DDAT1
000X0000B
DDAT0
R/W
R/W
R/W
R/W
: Read/write enabled
: Unused
R/W
—
X : Undefined
(2) Block diagram
Clock pulse
Frequency divider
COL staircase
generator
Voltage data
Frequency
select
DTMF
ROW/COL
decoder
ROW staircase
generator
Adder
Frequency
select
Preset counter
Count clock
Terminate
Frequency
divider
Internal clock
Control signal generator
Frequency
select
DTMF control register (DTMC)
DTMF data register (DTMD)
Internal bus
70
MB90650A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V)
Value
Symbol
VCC1
Unit
Remarks
Parameter
Min.
Max.
VSS – 0.3
VSS – 0.3
VSS + 4.0
VSS + 7.0
V
V
MB90652A/653A/654A,
MB90F654A
VCC2
VCC
(VCC1 = VCC2)
VSS – 0.3
VSS + 7.0
V
MB90P653A
MB90652A/653A/654A,
VSS – 0.3
VSS – 0.3
VSS – 0.3
VSS – 0.3
VSS – 0.3
VSS – 0.3
VSS – 0.3
VSS – 0.3
VSS – 0.3
VSS – 0.3
—
VSS + 4.0
VSS + 7.0
VSS + 4.0
VSS + 7.0
VSS + 4.0
VSS + 7.0
VSS + 4.0
VSS + 7.0
VSS + 4.0
VSS + 7.0
10
V
V
MB90F654A
*1
AVCC
Power supply voltage
MB90P653A
*1
MB90652A/653A/654A,
MB90F654A
V
AVRH
AVRL
V
MB90P653A
MB90652A/653A/654A,
MB90F654A
V
DVRH
VI
V
MB90P653A
MB90652A/653A/654A,
V
MB90F654A
*2
Input voltage
V
MB90P653A
*2,*6
MB90652A/653A/654A,
V
MB90F654A
*2
Output voltage
VO
V
MB90P653A
*2,*6
MB90652A/653A/654A,
mA
“L” level maximum
output current
MB90F654A
*3
IOL
—
15
mA MB90P653A
*3
MB90652A/653A/654A,
—
3
mA
MB90F654A
*4
“L” level average output current
IOLAV
ΣIOL
ΣIOLAV
IOH
—
4
mA MB90P653A
*4
MB90652A/653A/654A,
MB90F654A
—
60
mA
“L” level total maximum
output current
—
100
mA MB90P653A
—
30
mA
“L” level total average
output current
—
50
MB90652A/653A/654A,
—
–10
mA
“H” level maximum
output current
MB90F654A
*3
—
–15
mA MB90P653A
*3
(Continued)
71
MB90650A Series
(Continued)
(VSS = AVSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
—
Max.
–3
MB90652A/653A/654A,
MB90F654A
mA
“H” level average
output current
*4
*4
IOHAV
—
–4
mA MB90P653A
MB90652A/653A/654A,
MB90F654A
—
–60
–100
–30
mA
“H” level total maximum
output current
ΣIOH
—
mA MB90P653A
mA
“H” level total average
output current
ΣIOHAV
—
*5
Power consumption
Operating temperature
Storage temperature
PD
—
200
+85
mW
°C
TA
–40
–55
Tstg
+150
°C
*1: AVCC, AVRH, AVRL and DVRH must not exceed VCC (VCC1 and VCC2 are contained). Similarly, AVRL must not
exceed AVRH.
*2: VI and VO must not exceed VCC (VCC1 and VCC2 are contained) + 0.3 V.
*3: Maximum output current specifies the peak value or one corresponding pin.
*4: The average output current is the rating for the current from an individual pin averaged over 100 ms.
*5: The average total output current is the rating for the current from all pins averaged over 100 ms.
*6: Applies to the P47 and P70 to P72 on the MB90652A/653A/654A and MB90F654A.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
72
MB90650A Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
For normal operation
(MB90652A/653A/654A)
2.2
3.6
V
VCC1
2.7
2.4
3.6
3.6
V
V
For normal operation (MB90P653A)
For normal operation (MB90F654A)
For normal operation
(MB90652A/653A/654A)
2.2
5.5
V
VCC2
2.7
2.4
5.5
5.5
V
V
For normal operation (MB90P653A)
For normal operation (MB90F654A)
To maintain statuses in stop mode
(MB90652A/653A/654A)
1.8
1.8
1.8
1.8
1.8
1.8
3.6
5.5
3.6
5.5
5.5
5.5
V
V
V
V
V
V
Power supply voltage
To maintain statuses in stop mode
(MB90P653A)
VCC1
To maintain statuses in stop mode
(MB90F654A)
To maintain statuses in stop mode
(MB90652A/653A/654A)
To maintain statuses in stop mode
(MB90P653A)
VCC2
To maintain statuses in stop mode
(MB90F654A)
VIH
0.7 VCC
0.8 VCC
VCC – 0.3
2.4
VCC + 0.3
VCC + 0.3
VCC + 0.3
VCC + 0.3
0.3 VCC
0.2 VCC
VSS + 0.3
0.8
V
V
Pins other than VIHS and VIHM
Hysteresis input pins
MD pin input
VIHS
VIHM
VIHT
VIL
“H” level input voltage
“L” level input voltage
V
V
TTL input pins
VSS – 0.3
VSS – 0.3
VSS – 0.3
VSS – 0.3
–40
V
PIns other than VILS and VILM
Hysteresis input pins
MD pin input
VILS
VILM
VILT
V
V
V
TTL input pins
Operating temperature TA
+85
°C
Note: I2C must be used at above 2.7 V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
73
MB90650A Series
3. DC Characteristics
(MB90652A/653A/654A: VCC = 2.2 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
(MB90P653A: VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
(MB92F654A: VCC = 2.4 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Parameter
“H” level
output
voltage*2
Pin name
Condition
Unit
Remarks
Min.
Typ. Max.
VCC2 = 4.5 V,
IOH = –4.0 mA
When the 5-V power
supply is used
VCC2– 0.5
—
—
—
—
—
—
V
V
V
V
Pins except
P47,
P70 to P72
VOH
VCC = 2.7 V,
IOH = –1.6 mA
When the 3-V power
supply is used
VCC1– 0.3
*1
VCC2 = 4.5 V,
IOL = 4.0 mA
When the 5-V power
supply is used
—
—
0.4
0.4
“L” level output
voltage*2
All output
pins
VOL
VCC = 2.7 V,
IOL = 2.0 mA
When the 3-V power
supply is used
Except P50
to P57,
P90, P91
Input leakage
current
VCC = 3.3 V,
VSS < VI < VCC
IIL
–10
—
10
µA
40
20
80 400 kΩ MB90P653A
MB90652A/653A/654A,
When VCC = 3.0 V,
TA = +25°C
Pull-up resistor RPULL
—
65 200 kΩ
MB90F654A
Open-drain
output leakage Ileak
current
P40 to P47,
P70 to P72
—
—
0.1 10
µA
MB90652A/653A/654A:
During normal operation
ICC
ICC
ICC
—
—
—
—
—
—
—
—
10 20 mA
17 24 mA
19 26 mA
MB90652A/653A/654A:
In A/D operation
When VCC = 3.0 V
Internal 8 MHz
operation
—
MB90652A/653A/654A:
In D/A operation
MB90652A/653A/654A:
During sleep
ICCS
2.5
5
mA
Power supply
current
MB90P653A:
During normal operation
ICC
20 27 mA
24 31 mA
26 33 mA
4.2 10 mA
MB90P653A:
In A/D operation
ICC
When VCC = 3.0 V
Internal 8 MHz
operation
—
MB90P653A:
In D/A operation
ICC
MB90P653A:
During sleep
ICCS
* 1 : P40 to P46 are N-ch open-drain pins to be controlled and are usually used as CMOS devices.
* 2 : When the device is used with dual power supplies, the P20 to P27, P30 to P37, P40 to P47, and P70 to P72
are the 5 V pins and the rest are the 3 V pins.
(Continued)
74
MB90650A Series
(Continued)
(MB90652A/653A/654A: VCC = 2.2 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
(MB90P653A: VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
(MB90F654A: VCC = 2.4 V to 3.6 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Parameter
Pin name
Condition
Unit
Remarks
Min.
Typ. Max.
MB90652A/653A/654A:
During normal operation
ICC
—
20
27
35 mA
45 mA
50 mA
41 mA
42 mA
10 mA
12 mA
MB90F654A:
During normal operation
ICC
—
—
—
—
—
—
—
—
When VCC = 3.0 V
Internal 16 MHz
operation
MB90F654A:
Flash write/erase
ICC
—
33
MB90652A/653A/654A:
In A/D operation
ICC
31
MB90652A/653A/654A:
In D/A operation
ICC
34
MB90652A/653A/654A:
During sleep
ICCS
ICCS
ICCH
ICCH
4.8
6.2
0.1
0.2
When VCC = 3.0 V
Internal 16 MHz
operation
—
—
MB90F654A:
During sleep
Power supply
current
MB90652A/653A/654A:
During stop
20
40
µA
µA
TA = +25°C
When VCC = 3.0 V
MB90F654A:
During stop
VCC = 3.0 V,
TA = +25°C
External 32 kHz
operation
(Internal 8 MHz
operation)
MB90652A/653A/654A,
16 140 µA MB90F654A:
ICCL
—
—
In sub operation
—
—
MB90P653A:
In sub operation
ICCL
4.4
6
mA
MB90652A/653A/654A:
In watch mode
ICCT
ICCT
ICCT
—
—
—
10
15
15
30
30
60
µA
µA
µA
VCC = 3.0 V,
TA = +25°C
External 32 kHz
operation
MB90F654A:
In watch mode
MB90P653A:
In watch mode
Except AVCC,
AVSS, VCC,
VSS
Input
capacitance
CIN
—
—
10
80
pF
Note: VCC = VCC1 = VCC2
75
MB90650A Series
4. AC Characteristics
(1) Clock Timing
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin
name
Parameter
Symbol
Condition
Unit
Remarks
Min.
Typ.
Max.
MB90652A/653A/
654A,MB90F654A
—
3
—
32
MHz
FCH
FCL
tC
X0, X1
X0A, X1A
X0, X1
X0A, X1A
X0
Clock frequency
—
—
3
—
16
—
MHz MB90P653A
kHz
—
32.768
MB90652A/653A/
654A,MB90F654A
—
31.25
—
333
ns
Clock cycle time
—
—
62.5
—
—
333
—
ns MB90P653A
tCL
30.5
µs
MB90652A/653A/
654A,MB90F654A*2
—
—
—
5
—
—
—
—
—
ns
PWH
PWL
Input clock pulse
width
10
—
ns MB90P653A
*2
*2
PWLH
PWLL
X0A
X0
15.2
µs
Input clock rise
tcr
—
—
—
—
—
5
ns External clock
time and fall time tcf
MB90652A/653A/
MHz
1.5
16
654A,MB90F654A
Internal
operating clock
frequency
fCP
—
—
—
—
1.5
—
—
8.192
—
8
MHz MB90P653A
fCPL
—
—
—
kHz
ns
Internal
tCP
62.5
666
operating clock
cycle time
tCPL
—
—
—
—
—
—
122.1
—
—
5
µs
Frequency
fluctuation ratio
∆f
%
When locked
*1
*1: The frequency fluction ratio indicates the maximum fluctuation ratio from the set center frequency while locked
when using the PLL multiplier.
+
+α
α
Center frequency
fO
∆f =
× 100 (%)
fO
–α
–
Because the PLL frequency fluctuates around the set frequency with a certain cycle [approximately CLK × (1 CYC
to 50 CYC)], the worst value is not maintained for long. (The pulse, if featured with the long period, would produce
practically no error.)
*2: The duty ratio should be in the range 30% to 70%.
Note: VCC = VCC1 = VCC2
76
MB90650A Series
•Main clock timing condition (X0, X1)
tC
0.8 VCC
0.2 VCC
X0
PWL
PWH
tcf
tcr
• Subclock timing condition (X0A, X1A )
tCL
0.8 VCC
0.2 VCC
X0A
PWLL
PWHL
77
MB90650A Series
• PLL operation assurance range
Relationship between the internal operating clock frequency and power supply voltage
(MB90652A/653A/654A, MB90F654A)
(V)
3.6
Normal operation range
PLL operation assurance range
2.7
2.5
2.2
1
3
5
16
(MHz)
Internal clock (fCP)
Relationship between the internal oprating clock frequency and power supply voltage
(MB90P653A)
(V)
Normal operation range
3.6
PLL operation
assurance range
2.7
1.5
3
8
(MHz)
Internal clock (fCP)
Relationship between the oscillation frequency and internal operating clock frequency
(MHz)
Multiply Multiply
by 4
by 3
16
12
No multiplier
Multiply
by 2
Multiply by 1
9
8
4
3 4
8
16
24
32
(MHz)
Oscillation clock (FC)
78
MB90650A Series
The AC characteristics are for the following measurement reference voltages.
• Output signal waveform
• Input signal waveform
Hysteresis input pins
0.8 VCC
Output pins
2.4 V
0.2 VCC
0.2 V
Other than hysteresis or MD input pins
0.7 VCC
0.3 VCC
79
MB90650A Series
(2) Clock Output Timing
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin
Symbol
Condition
Unit
Remarks
Parameter
Cycle time
name
Min.
Max.
tCYC
CLK
CLK
—
tCP
—
ns
ns
tCP / 2 – 20 tCP / 2 + 20
VCC = 3.0 V
±10%
In the external
frequency of
5 MHz
CLK ↑ → CLK↓
tCHCL
tCP / 2 – 64 tCP / 2 + 64
ns
tCP: See “(1) Clock Timing.”
Note: VCC = VCC1 = VCC2
tCYC
tCHCL
2.4 V
2.4 V
CLK
0.8 V
(3) Reset Input Specifications
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin
Symbol
tRSTL
Condition
Unit
Remarks
Parameter
Reset input time
name
Min.
Max.
RST
—
16 tCP
—
ns
tCP: See “(1) Clock Timing.”
Note: VCC = VCC1 = VCC2
t
RSTL
RST
0.2 VCC
0.2 VCC
• AC characteristics measurement conditions
Pin
CL : Load capacitance at testing
CLK, ALE: CL = 30 pF
AD15 to AD00 (address/data bus), RD, WR: CL = 80 pF
CL
80
MB90650A Series
(4) Power on Supply Specifications (Power-on Reset)
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
tR
tOFF
Pin name
Condition
Unit Remarks
Parameter
Min.
Max.
Power supply rising time
VCC
—
—
30
ms
*
Due to
ms repeat
Power supply cut-off time
VCC
—
1
—
operation
* : When the power rising, VCC must be less than 0.2 V.
Notes: • The above standards are the values needed in order to activate a power-on reset.
• Activate a power-on reset by turning on the power supply again this in device.
• VCC = VCC1 = VCC2
tR
2.7 V
VCC
0.2 V
tOFF
Abrupt changes in the power supply voltage may cause a power-on reset.
When changing the power supply voltage during operation, suppress variations in the voltage and
ensure that the voltage rises smoothly, as shown in the following figure.
Main power supply voltage
VCC
It is recommended that the rate of
increase in the voltage be kept to
no more than 50 mV/ms.
Sub-power supply voltage
Holding RAM data
VSS
81
MB90650A Series
(5) Bus Read Timing
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name Condition
Unit
Remarks
Parameter
Min.
Max.
—
tCP /2 – 20
tCP / 2 – 35
tCP / 2 – 25
tCP / 2 – 40
ns MASK/FLASH
ns MB90P653A
ns MASK/FLASH
ns MB90P653A
ALE pulse width
tLHLL
ALE
—
—
—
—
Multiplexed
address
Valid address → ALE ↓ time tAVLL
ALE ↓ → address valid time tLLAX
—
Multiplexed
address
—
—
tCP / 2 – 15
tCP – 15
—
—
ns
ns
Multiplexed
address
Valid address → RD ↓ time
tAVRL
—
5 tCP / 2 – 60 ns MASK/FLASH
5 tCP / 2 – 80 ns MB90P653A
Valid address → valid data
input
Multiplexed
address
tAVDV
tRLRH
tRLDV
—
—
—
—
RD pulse width
RD
3 tCP / 2 – 20
—
ns
—
5 tCP / 2 – 60 ns MASK/FLASH
5 tCP / 2 – 80 ns MB90P653A
RD ↓ → valid data input
D15 to D00
—
0
RD ↑ → data hold time
RD ↑ → ALE ↑ time
tRHDX
tRHLH
D15 to D00
RD, ALE
—
—
—
—
ns
ns
tCP / 2 – 15
Address,
RD
RD ↑ → address valid time tRHAX
Valid address → CLK ↑ time tAVCH
—
tCP / 2 – 10
—
ns
Address,
CLK
—
—
tCP / 2 –20
tCP / 2 – 20
—
—
ns
ns
RD ↓ → CLK ↑ time
tRLCH
RD, CLK
tCP: See “(1) Clock Timing.”
Note: VCC = VCC1 = VCC2
82
MB90650A Series
tAVCH
tRLCH
2.4 V
2.4 V
CLK
ALE
tRHLH
tAVLL
2.4 V 2.4 V
tLHLL
tLLAX
2.4 V
0.8 V
tAVRL
tRLRH
2.4 V
RD
0.8 V
tRHAX
A23 to
A16
2.4 V
0.8 V
2.4 V
0.8 V
tRLDV
tAVDV
tRHDX
2.4 V
0.8 V
0.7 VCC
0.3 VCC
2.4 V
0.8 V
0.7 VCC
0.3 VCC
D15 to
D00
Address
Read data
83
MB90650A Series
(6) Bus Write Timing
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name Condition
Unit
Remarks
Parameter
Min.
Max.
—
Valid address → WR ↓ time tAVWL
A23 to A00
WR
—
—
tCP – 15
ns
ns
WR pulse width
tWLWH
3 tCP / 2 – 20
—
Valid data output → WR ↑
time
tDVWH
D15 to D00
D15 to D00
—
—
3 tCP / 2 – 20
—
ns
20
—
—
—
—
—
ns MASK/FLASH
WR ↑ → data hold time
tWHDX
30
ns MB90P653A
WR ↑ → address valid time tWHAX
A23 to A00
WR, ALE
WR, ALE
—
—
—
tCP / 2 – 10
tCP / 2 – 15
tCP / 2 – 20
ns
ns
ns
WR ↑ → ALE ↑ time
WR ↓ → CLK ↑ time
tWHLH
tWLCH
tCP: See “(1) Clock Timing.”
Note: VCC = VCC1 = VCC2
tWLCH
2.4 V
CLK
ALE
tWHLH
2.4 V
tAVWL
tWLWH
2.4 V
WR
(WRL, WRH)
0.8 V
tWHAX
2.4 V
0.8 V
2.4 V
0.8 V
A23 to
A16
tDVWH
tWHDX
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
D15 to
D00
Write data
Address
84
MB90650A Series
(7) Ready Input Timing
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name
Condition
Unit
Remarks
Parameter
Min.
45
70
0
Max.
—
—
—
—
ns MASK/FLASH
ns MB90P653A
ns
RDY setup time
RDY hold time
tRYHS
tRYHH
RDY
RDY
—
—
Notes: • Use the auto-ready function if the RDY setup time is too short
• VCC = VCC1 = VCC2.
2.4 V
2.4 V
CLK
ALE
RD/WR
tRYHS
RDY (When
wait states are
not inserted)
tRYHH
0.8 VCC
0.8 VCC
RDY (When
one wait states
are inserted)
0.2 VCC
0.2 VCC
tRYHS
85
MB90650A Series
(8) Hold Timing
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name
Condition
Unit
Remarks
Parameter
Min.
30
Max.
tCP
Pin floating → HAK ↓ time
HAK ↑ → pin valid time
tXHAL
tHAHV
HAK
HAK
—
—
ns
ns
tCP
2 tCP
tCP: See “(1) Clock Timing.”
Notes: • After reading HRQ, more than one cycle is required before changing HAK.
• VCC = VCC1 = VCC 2
2.4 V
HAK
0.8 V
tHAHV
tXHAL
High impedance
Pin
86
MB90650A Series
(9) UART Timing
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin
Symbol
Condition
Unit
Remarks
Parameter
name
Min.
8 tCP
–80
Max.
—
Serial clock cycle time
tSCYC
—
—
ns
80
ns MASK/FLASH
ns MB90P653A
ns MASK/FLASH
ns MB90P653A
SCK ↓ → SOT delay time tSLOV
CL = 80 pF + 1 TTL
for the internal shift
clock mode output
pin
–120
100
120
—
Valid SIN → SCK ↑
tIVSH
—
200
—
SCK ↑ → valid SIN hold
time
tSHIX
tSHSL
tSLSH
—
—
—
tCP
—
—
—
ns
ns
ns
Serial clock “H” pulse
width
4 tCP
4 tCP
Serial clock “L” pulse
width
CL = 80 pF + 1 TTL
for the external
shift clock mode
output pin
—
—
150
200
—
ns MASK/FLASH
ns MB90P653A
ns MASK/FLASH
ns MB90P653A
ns MASK/FLASH
ns MB90P653A
SCK ↓ → SOT delay time tSLOV
—
—
—
60
Valid SIN → SCK ↑
tIVSH
120
60
—
—
SCK ↑ → valid SIN hold
time
tSHIX
120
—
Notes: • These are the AC characteristics for CLK synchronous mode.
• CL is the load capacitance connected to the pin at testing.
• tCP is the machine cycle period (unit: ns).
• VCC = VCC1 = VCC 2
87
MB90650A Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
SOT
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SIN
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
SCK
0.2 VCC
0.2 VCC
tSLOV
2.4 V
0.8 V
SOT
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SIN
88
MB90650A Series
(10) I/O Extended Serial Timing
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin
Symbol
Condition
Unit
Remarks
Parameter
name
Min.
8 tCP
—
Max.
—
Serial clock cycle time
tSCYC
—
—
ns
80
ns MASK/FLASH
ns MB90P653A
ns
CL = 80 pF + 1 TTL
for the internal shift
clock mode output
pin
SCK ↓ → SOT delay time tSLOV
—
160
—
Valid SIN → SCK ↑
tIVSH
tSHIX
—
—
tCP
SCK ↑ → valid SIN hold
tCP
—
ns
time
230
460
230
460
2 tCP
tCP
—
—
—
—
—
—
ns MASK/FLASH
ns MB90P653A
ns MASK/FLASH
ns MB90P653A
ns
Serial clock “H” pulse
width
tSHSL
—
—
Serial clock “L” pulse
width
CL = 80 pF + 1 TTL
for the external
shift clock mode
output pin
tSLSH
SCK ↓ → SOT delay time tSLOV
—
—
Valid SIN →SCK ↑
tIVSH
ns
SCK ↑ → valid SIN hold
time
tSHIX
—
2 tCP
—
ns
Notes: • These are the AC characteristics for CLK synchronous mode.
• CL is the load capacitance connected to the pin at testing.
• tCP is the machine cycle period (unit: ns).
• The values in the table are target values.
• VCC = VCC1 = VCC 2
89
MB90650A Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
SOT
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SIN
• External shift clock mode
tSLSH
tSHSL
0.8 V CC
0.8 VCC
SCK
0.2 VCC
0.2 VCC
tSLOV
2.4 V
0.8 V
SOT
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SIN
90
MB90650A Series
(11) I2C Timing
(VCC = 2.7 V to 3.3 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit
Remarks
Parameter
Min.
Max.
SCL clock frequency
fSCL
—
—
—
—
0
100
kHz
Bus free time between stop
and start conditions
tBUS
4.7
—
µs
The first clock
pulse is
generated after
this period.
Hold time (re-send) start
tHDSTA
—
—
4.0
—
µs
SCL clock L state hold time tLOW
—
—
—
—
4.7
4.0
—
—
µs
µs
SCL clock H state hold
tHIGH
time
Re-send start condition
tSUSTA
—
—
4.7
—
µs
setup time
Data hold time
Data setup time
tHDDAT
tSUDAT
—
—
—
—
0
—
—
µs
40
ns
SDA and SCL signal rising
time
tR
—
—
—
1000
ns
SDA and SCL signal falling
time
tF
—
—
—
—
—
300
—
ns
Stop condition setup time
Note: VCC = VCC1 = VCC2
tSUSTO
4.0
µs
0.8 VCC
0.2 VCC
SDA
tBUS
tHDSTA
tLOW
tR
tF
0.8 VCC
SCL
0.2 VCC
tHIGH
tSUDAT
tSUSTA
tSUSTO
tHDDAT
tHDSTA
91
MB90650A Series
5. A/D Converter Electrical Characteristics
(MB90652A/653A/654A: VCC = 2.2 V to 3.3V, VSS = AVSS =0.0V, 2.7 V ≤ AVRH – AVRL, TA = –40°C to +85°C)
(MB90F654A: VCC = 2.4 V to 3.6 V, VSS = AVSS = 0.0 V, 2.7 V ≤ AVRH – AVRL, TA = –40°C to +85°C)
(MB90P653A: VCC = 2.7 V to 3.3 V, VSS = AVSS = 0.0 V, 2.7 V ≤ AVRH – AVRL, TA = –40°C to +85°C)
Value
Symbol
Pin name
Unit
Remarks
Parameter
Min.
—
Typ.
10
—
Max.
10
Resolution
—
—
—
—
—
—
bit
Total error
—
±3.0
±2.0
±1.9
±1.5
LSB
LSB
Linearity error
—
—
—
—
LSB MASK/FLASH
LSB MB90P653A
Differential
linearity error
—
—
—
—
Zero transition
voltage
AVRL
– 1.5 LSB
AVRL
+ 0.5 LSB
AVRL
+ 2.5 LSB
VOT
AN0 to AN7
AN0 to AN7
mV
mV
Full scale
transition voltage
AVRH
– 4.5 LSB
AVRH
– 1.5 LSB
AVRH
+ 0.5 LSB
VFST
6.125*1
12.25*2
—
—
—
—
µs MASK/FLASH
µs MB90P653A
Conversion time
—
—
Analog port input
current
IAIN
AN0 to AN7
—
0.1
10
µA
Analog input
voltage
VAIN
AN0 to AN7
AVRH
AVRL
AVRL + 2.7
0
—
—
—
AVRH
AVCC
V
V
V
Reference voltage
—
AVRH –
2.7
AVRL
IA
AVCC
—
—
—
—
3
—
—
5*3
—
5*3
mA
µA
µA
µA
Power supply
current
IAH
IR
AVCC
AVRH
AVRH
200
—
Reference voltage
supply current
IRH
Variation between
channels
—
AN0 to AN7
—
—
4
LSB
*1: For a 16 MHz machine clock
*2: For an 8 MHz machine clock
*3: The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVRH = 3.0 V).
Notes: • The error increases proportionally as |AVRH – AVRL| decreases.
• The output impedance of the external circuits connected to the analog inputs should be in the following
range.
The output impedance of the external circuit should be less than approximately 7 kΩ.
When using an external capacitor, it is recommended to have several thousand times the capacitance of
theinternalcapacitorasaguid, ifonetakesintoconsiderationtheeffectofthedividedcapacitancebetween
the external capacitor and the internal capacitor.
• If the output impedance of the external circuit is too high, the sampling time might be insufficient (sampling
time = 3.75 µs at a machine clock of 16 MHz).
• VCC = VCC1 = VCC2
(Continued)
92
MB90650A Series
(Continued)
• Analog input circuit model diagram
Sample hold circuit
C0
Analog input
Comparator
RON1
RON2
RON3
RON4
C1
RON1 : Approx. 5 kΩ
RON2 : Approx. 617 Ω
RON3 : Approx. 617 Ω
RON4 : Approx. 473 Ω
C0 : Approx. 35 pF
C1 : Approx. 2 pF
Note: Use the values shown as guids only.
93
MB90650A Series
6. D/A Converter Electrical Characteristics
(MB90652A/653A : VCC = 2.2 V to 3.3 V, VSS = DVSS = 0.0 V, 2.2 V ≤ DVRH – DVSS, TA = –40°C to +85°C)
(MB90F654A : VCC = 2.4 V to 3.6 V, VSS = DVSS = 0.0 V, 2.4 V ≤ DVRH – DVSS, TA = –40°C to +85°C)
(MB90P653A : VCC = 2.7 V to 3.3 V, VSS = DVSS = 0.0 V, 2.7 V ≤ DVRH – DVSS, TA = –40°C to +85°C)
Value
Pin
Symbol
Unit
Remarks
Parameter
name
Min.
Typ.
Max.
Resolution
—
—
—
—
8
8
bit
Differential
linearity error
—
—
—
—
—
—
±0.9
LSB
Absolute
accuracy
—
1
%
Linearity error
—
—
—
—
—
—
—
10.0
—
±1.5
20.0
VCC
VCC
VCC
—
LSB
µs
V
Conversion time
*1
MB90652A/653A/654A*2
2.2
2.4
2.7
—
Analog
reference power
supply voltage
—
DVRH
—
V
MB90F654A
MB90P653A
*2
*2
*3
—
V
Reference
voltage supply
current
IDVR
100
µA
DVRH
—
IDVRS
—
—
—
5
µA
kΩ
*4
Analog output
impedance
—
28
—
*1: Conversion time is the value at the load capacitance = 20 pF.
*2: DVRH – DVSS (AVSS)
*3: Current value at conversion
*4: Current value when stopped
Note: VCC = VCC1 = VCC2
94
MB90650A Series
7. DTMF Electrical characteristics
(MB90652A/653A : VCC = 2.2 V to 3.3 V, VSS = DVSS = 0.0 V, 2.2 V ≤ DVRH – DVSS, TA = –40°C to +85°C)
(MB90F654A : VCC = 2.4 V to 3.6 V, VSS = DVSS = 0.0 V, 2.4 V ≤ DVRH – DVSS, TA = –40°C to +85°C)
(MB90P653A : VCC = 2.7 V to 3.3 V, VSS = DVSS = 0.0 V, 2.7 V ≤ DVRH – DVSS, TA = –40°C to +85°C)
Value
Symbol
Condition
Unit
Remarks
Parameter
Min.
Typ. Max.
Output load
condition
To be specified with DTMF
pin pull-down resistor
RO
30 k
—
—
—
Ω
DTMF output
offset voltage
(At signal output)
VMOF
—
0.4
V
VCC = 3 V
TA = 25°C
Machine clock
f = 16 MHz
DTMF output
amplitude
(COL single tone)
VMFC
450
530
600
mVP-P
When DTMF terminal is
opened
RO = 200 kΩ
DTMF output
amplitude
(ROW single tone)
VMFOR
330
1.6
440
2.0
500
2.4
mVP-P
COL/ROW level
difference
RMF
dB
Note: VCC =VCC1 = VCC2
• Output level measurement circuit
VCC
X0
Audio
Low-pass filter
16MHz
Output level
DTMF
Analizer
X1
−48 dB / oct
VSS
RO
95
MB90650A Series
■ EXAMPLE CHARACTERISTICS
(1) “H” Level Output Voltage
(2) “L” Level Output Voltage
VOL vs. IOL
V
OH vs. IOH
VOL (V)
1.0
VOH (V)
4.0
TA = +25°C
TA = +25°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
3.5
3.0
2.5
VCC = 3.6 V
VCC = 2.4 V
VCC = 3.3 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 2.7 V
VCC = 2.7 V
VCC = 2.5 V
VCC = 2.4 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 3.6 V
2.0
1.5
1.0
0.5
0.0
1
2
3
4
5
–1
–2
–3
–4
–5
IOH (mA)
IOL (mA)
(3) “H” Level Input Voltage/“L” Level Input Voltage
(COMS Input)
(4) “H” Level Input Voltage/“L” Level Input Voltage
(Hysteresis Input)
V
IN vs.
VCC
VIN vs.
V
CC
VIN (V)
2.4
VIN (V)
2.4
TA = +25°C
TA = +25°C
VIHS
2.2
2.0
1.8
1.6
1.4
2.2
2.0
1.8
1.6
1.4
VIH
VIL
1.2
1.0
0.8
0.6
0.4
1.2
1.0
0.8
0.6
0.4
VILS
2.4
2.7
3.0
3.3
3.6
2.4
2.7
3.0
3.3
3.6
VCC (V)
VCC (V)
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
VIH: Thresholdwheninputvoltageissetto“H”level
VIL: Threshold when input voltage is set to “L” level
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
96
MB90650A Series
(5) Power Supply Current (fCP = Internal Operating Clock Frequency)
• Mask ROM products
I
CC vs.
VCC
I
CCS vs.
VCC
ICC (mA)
30
ICCS (mA)
10
T
A
= +25°C
TA = +25°C
28
26
24
22
9
8
7
fCP = 16 MHZ
fCP = 16 MHZ
20
18
6
5
fCP = 10 MHZ
fCP = 8 MHZ
16
14
12
10
8
fCP = 10 MHZ
fCP = 8 MHZ
4
3
2
1
0
fCP = 5 MHZ
6
fCP = 5 MHZ
4
2
0
2.4
2.7
2.7
2.7
3
3.3
3.6
VCC (V)
2.4
2.7
2.7
2.7
3
3.3
3.6
VCC (V)
I
CCH vs.
V
CC
I
CCL vs.
V
CC
ICCH (µA)
ICCL (µA)
0.50
50
T
A
= +25°C
T
A
= +25°C
0.45
0.40
0.35
45
40
35
0.30
0.25
30
25
0.20
0.15
0.10
0.05
0.00
20
15
10
5
0
2.4
2.4
3
3.3
3.6
VCC (V)
3
3.3
3.6
VCC (V)
I
A
vs. A
V
CC
I
R
vs. A
V
CC
IA (mA)
4.0
IR (mA)
4.0
T
A
= +25°C
T
A
= +25°C
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.4
3
3.3
3.6
2.4
3
3.3
3.6
AVCC (V)
AVCC (V)
97
MB90650A Series
• OTPROM products
I
CC vs.
V
CC
I
CCS vs.
VCC
ICC (mA)
60
ICCS (mA)
15
14
13
12
11
10
9
8
7
6
5
T
A
= +25°C
TA = +25°C
55
50
45
40
35
30
25
20
15
10
5
fCP = 16 MHZ
fCP = 16 MHZ
fCP = 10 MHZ
fCP = 8 MHZ
fCP = 10 MHZ
fCP = 8 MHZ
fCP = 5 MHZ
4
3
2
1
0
fCP = 5 MHZ
0
2.4
2.7
3
3.3
3.6
2.4
2.7
3
3.3
3.6
VCC (V)
VCC (V)
I
CCH vs.
V
CC
I
CCL vs.
V
CC
ICCH (µA)
3.0
ICCL (mA)
10
T
A
= +25°C
T
A
= +25°C
2.8
9
8
7
6
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
5
4
3
2
1
0
2.4
2.7
3
3.3
3.6
2.4
2.7
3
3.3
3.6
VCC (V)
VCC (V)
98
MB90650A Series
• FLAH products
I
CC vs.
V
CC
I
CCS vs.
V
CC
ICC (mA)
ICCS (mA)
10
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
T
A
= +25 °C
TA = +25 °C
fCP
=
16 MHZ
9
8
7
fCP
=
16 MHZ
fCP
fCP
=
=
10 MHZ
8 MHZ
6
5
fCP
fCP
=
=
10 MHZ
8 MHZ
4
3
2
1
0
fCP
=
5 MHZ
fCP
=
5 MHZ
6
4
2
0
2.4
2.7
3
3.3
3.6
2.4
2.7
3
3.3
3.6
VCC (V)
VCC (V)
I
CCH vs.
V
CC
I
CCL vs.
V
CC
ICCH (µA)
ICCL (µA)
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
50
T
A
= +25 °C
T
A
= +25 °C
45
40
35
30
25
20
15
10
5
0
2.4
2.7
3
3.3
3.6
2.4
2.7
3
3.3
3.6
VCC (V)
VCC (V)
99
MB90650A Series
(6) Pull-up Resistance
• Mask ROM products
• OTPROM products
R
vs.
V
CC
R
vs.
V
CC
R (kΩ)
R (kΩ)
1000
1000
T
A
= +25°C
TA = +25°C
100
100
10
2.4
10
2.4
2.7
3
3.3
3.6
2.7
3
3.3
3.6
VCC (V)
VCC (V)
• FLASH products
R
vs.
V
CC
R (kΩ)
1000
TA = +25 °C
100
10
2.4
2.7
3
3.3
3.6
VCC (V)
100
MB90650A Series
■ INSTRUCTIONS (340 INSTRUCTIONS)
Table 1 Explanation of Items in Tables of Instructions
Meaning
Upper-case letters and symbols: Represented as they appear in assembler.
Item
Mnemonic
Lower-case letters: Replaced when described in assembler.
Numbers after lower-case letters:Indicate the bit width within the instruction.
#
~
Indicates the number of bytes.
Indicates the number of cycles.
m: When branching
n : When not branching
See Table 4 for details about meanings of other letters in items.
RG
B
Indicates the number of accesses to the register during execution of the instruction.
It is used calculate a correction value for intermittent operation of CPU.
Indicates the correction value for calculating the number of actual cycles during execution of the
instruction. (Table 5)
The number of actual cycles during execution of the instruction is the correction value summed
with the value in the “~” column.
Operation
LH
Indicates the operation of instruction.
Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.
Z : Transfers “0”.
X : Extends with a sign before transferring.
– : Transfers nothing.
AH
Indicates special operations involving the upper 16 bits in the accumulator.
* : Transfers from AL to AH.
– : No transfer.
Z : Transfers 00H to AH.
X : Transfers 00H or FFH to AH by signing and extending AL.
I
S
Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),
N (negative), Z (zero), V (overflow), and C (carry).
* : Changes due to execution of instruction.
– : No change.
S : Set by execution of instruction.
R : Reset by execution of instruction.
T
N
Z
V
C
RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that
reads data from memory, etc., processes the data, and then writes the result to memory.)
* : Instruction is a read-modify-write instruction.
– : Instruction is not a read-modify-write instruction.
Note: A read-modify-write instruction cannot be used on addresses that have different
meanings depending on whether they are read or written.
101
MB90650A Series
Table 2 Explanation of Symbols in Tables of Instructions
Meaning
Symbol
A
32-bit accumulator
The bit length varies according to the instruction.
Byte : Lower 8 bits of AL
Word : 16 bits of AL
Long : 32 bits of AL:AH
AH
AL
Upper 16 bits of A
Lower 16 bits of A
SP
PC
Stack pointer (USP or SSP)
Program counter
PCB
DTB
ADB
SSB
USB
SPB
DPR
brg1
brg2
Ri
Program bank register
Data bank register
Additional data bank register
System stack bank register
User stack bank register
Current stack bank register (SSB or USB)
Direct page register
DTB, ADB, SSB, USB, DPR, PCB, SPB
DTB, ADB, SSB, USB, DPR, SPB
R0, R1, R2, R3, R4, R5, R6, R7
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RW0, RW1, RW2, RW3
RWi
RWj
RLi
RL0, RL1, RL2, RL3
dir
Compact direct addressing
addr16
addr24
ad24 0 to 15
ad24 16 to 23
Direct addressing
Physical direct addressing
Bit 0 to bit 15 of addr24
Bit 16 to bit 23 of addr24
io
I/O area (000000H to 0000FFH)
imm4
imm8
4-bit immediate data
8-bit immediate data
imm16
imm32
ext (imm8)
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data
disp8
disp16
8-bit displacement
16-bit displacement
bp
Bit offset
vct4
vct8
Vector number (0 to 15)
Vector number (0 to 255)
( )b
Bit address
(Continued)
102
MB90650A Series
(Continued)
Symbol
Meaning
rel
Branch specification relative to PC
ear
eam
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
rlst
Register list
Table 3 Effective Address Fields
Address format
Number of bytes in address
extension *
Code
Notation
00
01
02
03
04
05
06
07
R0
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
RL0 Register direct
(RL0)
RL1 “ea” corresponds to byte, word, and
(RL1) long-word types, starting from the
RL2 left
(RL2)
RL3
R1
R2
R3
R4
R5
R6
R7
—
(RL3)
08
09
0A
0B
@RW0
Register indirect
@RW1
@RW2
@RW3
0
0
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
1
2
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacement
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
0
0
2
2
Note: The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)
column in the tables of instructions.
103
MB90650A Series
Table 4 Number of Execution Cycles for Each Type of Addressing
(a)
Number of register
accesses for each type of
addressing
Code
Operand
Number of execution cycles
for each type of addressing
Ri
RWi
RLi
00 to 07
Listed in tables of instructions Listed in tables of instructions
08 to 0B
0C to 0F
10 to 17
18 to 1B
@RWj
2
4
2
2
1
2
1
1
@RWj +
@RWi + disp8
@RWj + disp16
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
4
4
2
1
2
2
0
0
Note: “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.
Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles
(b) byte
Number Number
(c) word
Number Number
(d) long
Number Number
Operand
of cycles of access of cycles of access of cycles of access
Internal register
+0
1
+0
1
+0
2
Internal memory even address
Internal memory odd address
+0
+0
1
1
+0
+2
1
2
+0
+4
2
4
Even address on external data bus (16 bits)
Odd address on external data bus (16 bits)
+1
+1
1
1
+1
+4
1
2
+2
+8
2
4
External data bus (8 bits)
+1
1
+4
2
+8
4
Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)
in the tables of instructions.
• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles
Instruction
Internal memory
Byte boundary
Word boundary
—
—
+3
+2
+3
—
External data bus (16 bits)
External data bus (8 bits)
Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
• Because instruction execution is not slowed down by all program fetches in actuality, these correction
values should be used for “worst case” calculations.
104
MB90650A Series
Table 7 Transfer Instructions (Byte) [41 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
#
~
B
Operation
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RLi+disp8
2
3
1
2
3
4
2
2
0
0
1
1
(b) byte (A) ← (dir)
(b) byte (A) ← (addr16)
Z
Z
Z
Z
Z
Z
Z
Z
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
byte (A) ← (Ri)
byte (A) ← (ear)
2+ 3+ (a) 0
(b) byte (A) ← (eam)
(b) byte (A) ← (io)
2
2
2
3
1
3
2
3
10
1
0
0
0
2
0
0
byte (A) ← imm8
(b) byte (A) ← ((A))
(b) byte (A) ← ((RLi)+disp8) Z
MOVN A, #imm4
0
byte (A) ← imm4
Z
R
MOVX A, dir
MOVX A, addr16
MOVX A, Ri
MOVX A, ear
MOVX A, eam
MOVX A, io
MOVX A, #imm8
MOVX A, @A
MOVX A,@RWi+disp8
MOVX A, @RLi+disp8
2
3
2
2
3
4
2
2
0
0
1
1
(b) byte (A) ← (dir)
(b) byte (A) ← (addr16)
X
X
X
X
X
X
X
X
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
byte (A) ← (Ri)
byte (A) ← (ear)
2+ 3+ (a) 0
(b) byte (A) ← (eam)
(b) byte (A) ← (io)
2
2
2
2
3
3
2
3
5
10
0
0
0
1
2
0
byte (A) ← imm8
(b) byte (A) ← ((A))
(b) byte (A) ← ((RWi)+disp8) X
(b) byte (A) ← ((RLi)+disp8) X
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi+disp8, A
Ri, ear
Ri, eam
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
@AL, AH
2
3
1
2
3
4
2
2
0
0
1
1
(b) byte (dir) ← (A)
(b) byte (addr16) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
byte (Ri) ← (A)
byte (ear) ← (A)
2+ 3+ (a) 0
(b) byte (eam) ← (A)
(b) byte (io) ← (A)
(b) byte ((RLi) +disp8) ← (A) –
2
3
2
3
10
3
0
2
2
0
byte (Ri) ← (ear)
(b) byte (Ri) ← (eam)
byte (ear) ← (Ri)
(b) byte (eam) ← (Ri)
byte (Ri) ← imm8
–
–
–
–
–
–
–
–
–
–
2+ 4+ (a) 1
2
2+ 5+ (a) 1
2
3
3
3
4
2
0
2
5
5
2
1
0
0
1
0
(b) byte (io) ← imm8
(b) byte (dir) ← imm8
0
byte (ear) ← imm8
3+ 4+ (a) 0
2
(b) byte (eam) ← imm8
(b) byte ((A)) ← (AH)
3
0
XCH
XCH
XCH
XCH
A, ear
2
4
2
0
byte (A) ↔ (ear)
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A, eam
Ri, ear
Ri, eam
2+ 5+ (a) 0 2× (b) byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
2+ 9+ (a) 2 2× (b) byte (Ri) ↔ (eam)
2
7
4
0
Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
105
MB90650A Series
Table 8 Transfer Instructions (Word/Long Word) [38 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
MOVW A, dir
MOVW A, addr16
MOVW A, SP
MOVW A, RWi
MOVW A, ear
MOVW A, eam
MOVW A, io
MOVW A, @A
#
~
B
Operation
2
3
1
1
2
3
4
1
2
2
0
0
0
1
1
(c) word (A) ← (dir)
(c) word (A) ← (addr16)
0
0
0
(c) word (A) ← (eam)
(c) word (A) ← (io)
(c) word (A) ← ((A))
0
(c)
(c)
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
2+ 3+ (a) 0
2
2
3
2
3
3
3
2
5
10
0
0
0
1
2
MOVW A, #imm16
MOVW A, @RWi+disp8
MOVW A, @RLi+disp8
word (A) ← imm16
word (A) ← ((RWi) +disp8)
word (A) ← ((RLi) +disp8)
MOVW dir, A
MOVW addr16, A
MOVW SP, A
MOVW RWi, A
MOVW ear, A
MOVW eam, A
MOVW io, A
MOVW @RWi+disp8, A
MOVW @RLi+disp8, A
MOVW RWi, ear
MOVW RWi, eam
MOVW ear, RWi
MOVW eam, RWi
MOVW RWi, #imm16
MOVW io, #imm16
MOVW ear, #imm16
MOVW eam, #imm16
2
3
1
1
2
3
4
1
2
2
0
0
0
1
1
(c) word (dir) ← (A)
(c) word (addr16) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
2+ 3+ (a) 0
(c) word (eam) ← (A)
(c) word (io) ← (A)
2
2
3
2
3
5
10
3
0
1
2
2
word ((RWi) +disp8) ← (A)
word ((RLi) +disp8) ← (A)
(c)
(c)
(0) word (RWi) ← (ear)
(c) word (RWi) ← (eam)
2+ 4+ (a) 1
2
2+ 5+ (a) 1
3
4
4
4
2
0
word (ear) ← (RWi)
(c) word (eam) ← (RWi)
word (RWi) ← imm16
(c) word (io) ← imm16
word (ear) ← imm16
2
5
2
1
0
1
0
0
4+ 4+ (a) 0
(c) word (eam) ← imm16
MOVW @AL, AH
2
2
3
4
0
2
(c) word ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
XCHW A, ear
0
word (A) ↔ (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
XCHW A, eam
XCHW RWi, ear
XCHW RWi, eam
2+ 5+ (a) 0 2× (c) word (A) ↔ (eam)
word (RWi) ↔ (ear)
2+ 9+ (a) 2 2× (c) word (RWi) ↔ (eam)
2
7
4
0
MOVL A, ear
MOVL A, eam
MOVL A, #imm32
2
4
2
0
long (A) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
2+ 5+ (a) 0
5
(d) long (A) ← (eam)
3
0
0
0
long (A) ← imm32
long (ear) ← (A)
MOVL ear, A
MOVL eam, A
2
4
2
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
2+ 5+ (a) 0
(d) long (eam) ← (A)
Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
106
MB90650A Series
Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
#
~
B
Operation
ADD
A,#imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
2
2
2
2
5
3
0
0
1
0
byte (A) ← (A) +imm8
Z
Z
Z
Z
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC A, ear
ADDC A, eam
ADDDC A
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC A, ear
SUBC A, eam
SUBDC A
(b) byte (A) ← (A) +(dir)
byte (A) ← (A) +(ear)
(b) byte (A) ← (A) +(eam)
byte (ear) ← (ear) + (A)
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) + (A)
0
2+ 4+ (a) 0
2
3
2
0
1
2
2
3
0
1
0
0
byte (A) ← (AH) + (AL) + (C) Z
byte (A) ← (A) + (ear) + (C)
Z
2+ 4+ (a) 0
(b) byte (A) ← (A) + (eam) + (C) Z
0
0
byte (A) ← (AH) + (AL) + (C) (decimal)
1
2
2
2
3
2
5
3
0
0
0
1
Z
Z
Z
Z
Z
–
–
Z
Z
Z
Z
A, #imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
byte (A) ← (A) –imm8
(b) byte (A) ← (A) – (dir)
byte (A) ← (A) – (ear)
(b) byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) – (A)
0
2+ 4+ (a) 0
2
3
2
0
1
2
2
3
0
1
0
0
byte (A) ← (AH) – (AL) – (C)
byte (A) ← (A) – (ear) – (C)
–
–
–
–
2+ 4+ (a) 0
1
(b) byte (A) ← (A) – (eam) – (C)
0
byte (A) ← (AH) – (AL) – (C) (decimal)
3
0
ADDW A
1
2
2
3
0
1
0
0
word (A) ← (AH) + (AL)
word (A) ← (A) +(ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
*
ADDW A, ear
ADDW A, eam
ADDW A, #imm16
ADDW ear, A
ADDW eam, A
ADDCWA, ear
ADDCWA, eam
SUBW A
SUBW A, ear
SUBW A, eam
SUBW A, #imm16
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam
2+ 4+ (a) 0
3
2
(c) word (A) ← (A) +(eam)
0
0
2
3
0
2
word (A) ← (A) +imm16
word (ear) ← (ear) + (A)
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
2
3
1
0
2+ 4+ (a) 0
1
2
2+ 4+ (a) 0
3
2
(c) word (A) ← (A) + (eam) + (C) –
0
0
(c) word (A) ← (A) – (eam)
0
0
2
3
0
1
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
–
–
–
–
–
–
–
2
3
0
2
word (A) ← (A) –imm16
word (ear) ← (ear) – (A)
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
2
3
1
0
–
–
2+ 4+ (a) 0
(c) word (A) ← (A) – (eam) – (C) –
ADDL A, ear
2
6
2
0
long (A) ← (A) + (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
ADDL A, eam
ADDL A, #imm32
SUBL A, ear
SUBL A, eam
SUBL A, #imm32
2+ 7+ (a) 0
5
2
2+ 7+ (a) 0
5
(d) long (A) ← (A) + (eam)
0
0
4
6
0
2
long (A) ← (A) +imm32
long (A) ← (A) – (ear)
(d) long (A) ← (A) – (eam)
long (A) ← (A) –imm32
4
0
0
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
107
MB90650A Series
Table 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
#
~
B
Operation
INC
INC
ear
eam
2
2
2
0
byte (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) +1
DEC
DEC
ear
eam
2
3
2
0
byte (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) –1
INCW ear
INCW eam
2
3
2
0
word (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) +1
DECW ear
DECW eam
2
3
2
0
word (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) –1
INCL ear
INCL eam
2
7
4
0
long (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 9+ (a) 0 2× (d) long (eam) ← (eam) +1
DECL ear
DECL eam
2
7
4
0
long (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 9+ (a) 0 2× (d) long (eam) ← (eam) –1
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 11 Compare Instructions (Byte/Word/Long Word) [11 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
#
~
B
Operation
CMP
A
1
2
1
2
0
1
0
0
byte (AH) – (AL)
byte (A) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMP
CMP
CMP
A, ear
A, eam
A, #imm8
2+ 3+ (a) 0
2
(b) byte (A) ← (eam)
0
2
0
byte (A) ← imm8
CMPW A
1
2
1
2
0
1
0
0
word (AH) – (AL)
word (A) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW A, ear
CMPW A, eam
CMPW A, #imm16
2+ 3+ (a) 0
3
(c) word (A) ← (eam)
0
2
0
word (A) ← imm16
CMPL A, ear
CMPL A, eam
CMPL A, #imm32
2
6
2
0
word (A) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
2+ 7+ (a) 0
5
(d) word (A) ← (eam)
word (A) ← imm32
3
0
0
Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
108
MB90650A Series
Table 12 Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
1
DIVU
A
1
0
0 word (AH) /byte (AL)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
Quotient → byte (AL) Remainder → byte (AH)
2
DIVU
DIVU
A, ear
2
1
0
1
0
0 word (A)/byte (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
Quotient → byte (A) Remainder → byte (ear)
6
3
A, eam 2+
word (A)/byte (eam)
Quotient → byte (A) Remainder → byte (eam)
*
*
4
DIVUW A, ear
2
long (A)/word (ear)
Quotient → word (A) Remainder → word (ear)
0
*
7
5
DIVUW A, eam 2+
long (A)/word (eam)
Quotient → word (A) Remainder → word (ear)
*
*
8
MULU
MULU A, ear
MULU A, eam 2+
A
1
2
0
1
0
byte (AH) *byte (AL) → word (A)
byte (A) *byte (ear) → word (A)
byte (A) *byte (eam) → word (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
(b)
*
9
*
10
*
MULUW A
MULUW A, ear
MULUW A, eam 2+
1
2
11
12
13
0
1
0
word (AH) *word (AL) → long (A)
word (A) *word (ear) → long (A)
word (A) *word (eam) → long (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
(c)
*
*
*
*1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally.
*2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally.
*3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.
*4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally.
*5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.
*6: (b) when the result is zero or when an overflow occurs, and 2 × (b) normally.
*7: (c) when the result is zero or when an overflow occurs, and 2 × (c) normally.
*8: 3 when byte (AH) is zero, and 7 when byte (AH) is not zero.
*9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero.
*10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.
*11: 3 when word (AH) is zero, and 11 when word (AH) is not zero.
*12: 4 when word (ear) is zero, and 12 when word (ear) is not zero.
*13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
109
MB90650A Series
Table 13 Logical 1 Instructions (Byte/Word) [39 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
AND A, #imm8
#
~
B
Operation
2
2
2
3
0
1
0
0
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
AND
AND
AND
AND
A, ear
A, eam
ear, A
2+ 4+ (a) 0
(b) byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
2
3
2
0
eam, A
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) and (A) –
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
2
2
2
3
0
1
0
0
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
2+ 4+ (a) 0
(b) byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) or (A)
2
3
2
0
eam, A
XOR A, #imm8
XOR A, ear
XOR A, eam
XOR ear, A
XOR eam, A
2
2
2
3
0
1
0
0
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
2+ 4+ (a) 0
2
2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) xor (A) –
(b) byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
3
2
0
NOT
NOT
NOT
A
ear
eam
1
2
2
3
0
2
0
0
byte (A) ← not (A)
byte (ear) ← not (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
2+ 5+ (a) 0 2× (b) byte (eam) ← not (eam)
ANDW A
1
3
2
2
2
3
0
0
1
0
0
0
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
ANDW A, #imm16
ANDW A, ear
ANDW A, eam
ANDW ear, A
ANDW eam, A
2+ 4+ (a) 0
2
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) and (A) –
(c) word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
3
2
0
ORW
A
1
3
2
2
2
3
0
0
1
0
0
0
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
ORW A, #imm16
ORW A, ear
ORW A, eam
ORW ear, A
2+ 4+ (a) 0
2
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) or (A) –
(c) word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
3
2
0
ORW eam, A
XORW A
1
3
2
2
2
3
0
0
1
0
0
0
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
XORW A, #imm16
XORW A, ear
XORW A, eam
XORW ear, A
XORW eam, A
2+ 4+ (a) 0
(c) word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
2+ 5+ (a) 0 2× (c) word (eam) ← (eam) xor (A)
2
3
2
0
NOTW A
NOTW ear
NOTW eam
1
2
2
3
0
2
0
0
word (A) ← not (A)
word (ear) ← not (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
2+ 5+ (a) 0 2× (c) word (eam) ← not (eam)
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
110
MB90650A Series
Table 14 Logical 2 Instructions (Long Word) [6 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
#
~
B
Operation
ANDL A, ear
ANDL A, eam
2
6
2
0
long (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 7+ (a) 0
(d) long (A) ← (A) and (eam)
ORL
ORL
A, ear
A, eam
2
6
2
0
long (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 7+ (a) 0
(d) long (A) ← (A) or (eam)
XORL A, ea
XORL A, eam
2
6
2
0
long (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 7+ (a) 0
(d) long (A) ← (A) xor (eam)
Table 15 Sign Inversion Instructions (Byte/Word) [6 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
#
~
B
Operation
NEG
A
1
2
0
0
byte (A) ← 0 – (A)
X
–
–
–
–
*
*
*
*
–
NEG ear
NEG eam
2
3
2
0
byte (ear) ← 0 – (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
2+ 5+ (a) 0 2× (b) byte (eam) ← 0 – (eam)
NEGW A
1
2
0
0
word (A) ← 0 – (A)
–
–
–
–
–
*
*
*
*
–
NEGW ear
NEGW eam
2
3
2
0
word (ear) ← 0 – (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
2+ 5+ (a) 0 2× (c) word (eam) ← 0 – (eam)
Table 16 Normalize Instruction (Long Word) [1 Instruction]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
RG
B
Operation
1
NRML A, R0
2
1
0
long (A) ← Shift until first digit is “1” –
byte (R0) ← Current shift count
–
–
–
–
–
*
–
–
–
*
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
111
MB90650A Series
Table 17 Shift Instructions (Byte/Word/Long Word) [18 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
RORC A
#
~
B
Operation
byte (A) ← Right rotation with carry
byte (A) ← Left rotation with carry
2
2
2
2
0
0
0
0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
*
*
–
–
ROLC A
RORC ear
RORC eam
ROLC ear
ROLC eam
byte (ear) ← Right rotation with carry
byte (eam) ← Right rotation with carry
byte (ear) ← Left rotation with carry
byte (eam) ← Left rotation with carry
2
2+
2
3
2
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
–
*
–
*
5+ (a)
0 2× (b)
2
0 2× (b)
0
3
2+
5+ (a)
byte (A) ← Arithmetic right barrel shift (A, R0)
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
ASR A, R0
LSR A, R0
LSL A, R0
1
2
2
2
1
1
1
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*
*
*
1
1
word (A) ← Arithmetic right shift (A, 1 bit)
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
ASRWA
LSRW A/SHRW A
LSLW A/SHLW A
1
1
1
2
2
2
0
0
0
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
R
*
*
*
*
–
–
–
*
*
*
–
–
–
1
word (A) ← Arithmetic right barrel shift (A, R0)
word (A) ← Logical right barrel shift (A, R0)
word (A) ← Logical left barrel shift (A, R0)
ASRW A, R0
LSRW A, R0
LSLW A, R0
2
2
2
1
1
1
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*
*
*
1
1
2
ASRL A, R0
LSRL A, R0
LSLL A, R0
long (A) ← Arithmetic right shift (A, R0)
long (A) ← Logical right barrel shift (A, R0)
long (A) ← Logical left barrel shift (A, R0)
2
2
2
1
1
1
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*
*
*
2
2
*1: 6 when R0 is 0, 5 + (R0) in all other cases.
*2: 6 when R0 is 0, 6 + (R0) in all other cases.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
112
MB90650A Series
Table 18 Branch 1 Instructions [31 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
#
~
B
Operation
1
BZ/BEQ
BNZ/BNE rel
BC/BLO
BNC/BHS rel
rel
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Branch when (Z) = 1
Branch when (Z) = 0
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
Branch when (T) = 0
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
Branch when ((V) xor (N)) or (Z) = 1
Branch when ((V) xor (N)) or (Z) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
1
rel
1
1
BN
BP
BV
BNV
BT
BNT
BLT
BGE
BLE
BGT
BLS
BHI
BRA
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
1
1
1
1
1
1
1
1
1
1
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally
1
1
*
JMP
JMP
JMP
JMP
@A
1
3
2
2
3
3
0
0
1
0
2
0
0
0
0
0
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
addr16
@ear
@eam
2+ 4+ (a)
2
2+ 6+ (a)
4
2
(c) word (PC) ← (eam)
0
(d)
0
JMPP @ear *3
JMPP @eam *3
JMPP addr24
word (PC) ← (ear), (PCB) ← (ear +2)
5
word (PC) ← (eam), (PCB) ← (eam +2)
4
6
word (PC) ← ad24 0 to 15,
(PCB) ← ad24 16 to 23
CALL @ear *4
CALL @eam *4
CALL addr16 *5
CALLV #vct4 *5
CALLP @ear *6
1
(c) word (PC) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2+ 7+ (a) 0 2× (c) word (PC) ← (eam)
3
1
2
6
7
10
0
(c) word (PC) ← addr16
0 2× (c) Vector call instruction
2 2× (c) word (PC) ← (ear) 0 to 15,
(PCB) ← (ear) 16 to 23
2
CALLP @eam *6
CALLP addr24 *7
2+ 11+ (a)
10
0
0
word (PC) ← (eam) 0 to 15,
(PCB) ← (eam) 16 to 23
word (PC) ← addr0 to 15,
(PCB) ← addr16 to 23
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
4
2× (c)
*1: 4 when branching, 3 when not branching.
*2: (b) + 3 × (c)
*3: Read (word) branch address.
*4: W: Save (word) to stack; R: read (word) branch address.
*5: Save (word) to stack.
*6: W: Save (long word) to W stack; R: read (long word) R branch address.
*7: Save (long word) to stack.
Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
113
MB90650A Series
Table 19 Branch 2 Instructions [19 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
#
~
B
Operation
1
Branch when byte (A) ≠ imm8
Branch when word (A) ≠ imm16
CBNE A, #imm8, rel
CWBNE A, #imm16, rel
3
4
0
0
0
0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
*
*
1
2
Branch when byte (ear) ≠ imm8
Branch when byte (eam) ≠ imm8
Branch when word (ear) ≠ imm16
Branch when word (eam) ≠ imm16
CBNE ear, #imm8, rel
4
4+
5
*
*
*
*
1
0
1
0
0
(b)
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CBNE
eam, #imm8, rel*9
3
4
CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel*9
3
5+
(c)
5
DBNZ ear, rel
DBNZ eam, rel
3
2
0
Branch when byte (ear) =
(ear) – 1, and (ear) ≠ 0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
*
6
*
3+
2 2× (b) Branch when byte (eam) =
(eam) – 1, and (eam) ≠ 0
5
DWBNZ ear, rel
DWBNZ eam, rel
3
*
2
0
Branch when word (ear) =
(ear) – 1, and (ear) ≠ 0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
6
3+
2 2× (c) Branch when word (eam) =
(eam) – 1, and (eam) ≠ 0
*
INT
INT
INTP
INT9
RETI
#vct8
addr16
addr24
8× (c)
6× (c)
6× (c)
8× (c)
6× (c)
2
3
4
1
1
0
0
0
0
0
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
–
–
–
–
–
–
–
–
–
–
R S –
R S –
R S –
R S –
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
–
20
16
17
20
15
*
*
*
LINK
#local8
(c)
2
0
At constant entry, save old
frame pointer to stack, set
new frame pointer, and
–
–
–
–
–
–
–
–
–
–
6
allocate local pointer area
At constant entry, retrieve
old frame pointer from stack.
UNLINK
(c)
1
0
–
–
–
–
–
–
–
–
–
–
5
RET *7
(c)
(d)
1
1
0
0
Return from subroutine
Return from subroutine
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
4
6
RETP *8
*1: 5 when branching, 4 when not branching
*2: 13 when branching, 12 when not branching
*3: 7 + (a) when branching, 6 + (a) when not branching
*4: 8 when branching, 7 when not branching
*5: 7 when branching, 6 when not branching
*6: 8 + (a) when branching, 7 + (a) when not branching
*7: Retrieve (word) from stack
*8: Retrieve (long word) from stack
*9: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
114
MB90650A Series
Table 20 Other Control Instructions (Byte/Word/Long Word) [36 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
#
~
B
Operation
word (SP) ← (SP) –2, ((SP)) ← (A)
word (SP) ← (SP) –2, ((SP)) ← (AH)
word (SP) ← (SP) –2, ((SP)) ← (PS)
(SP) ← (SP) –2n, ((SP)) ← (rlst)
1
1
1
2
4
4
4
0
0
0
(c)
(c)
(c)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
5
4
*
*
*
word (A) ← ((SP)), (SP) ← (SP) +2
word (AH) ← ((SP)), (SP) ← (SP) +2
word (PS) ← ((SP)), (SP) ← (SP) +2
(rlst) ← ((SP)), (SP) ← (SP) +2n
POPW A
1
1
1
2
–
–
–
–
*
–
–
*
–
–
*
–
–
*
–
–
*
–
–
*
–
–
*
–
–
*
–
–
–
–
3
3
4
0
0
0
(c)
(c)
(c)
POPW AH
POPW PS
POPW rlst
–
–
–
2
5
4
–
–
–
–
–
–
–
*
*
*
JCTX @A
1
Context switch instruction
0 6× (c)
–
–
*
*
*
*
*
*
*
–
14
AND CCR, #imm8
OR CCR, #imm8
2
2
byte (CCR) ← (CCR) and imm8 –
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
3
3
0
0
0
0
byte (CCR) ← (CCR) or imm8
–
MOV RP, #imm8
MOV ILM, #imm8
2
2
byte (RP) ←imm8
byte (ILM) ←imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
0
0
0
0
MOVEA RWi, ear
MOVEA RWi, eam 2+
MOVEA A, ear
MOVEA A, eam
2
word (RWi) ←ear
word (RWi) ←eam
word(A) ←ear
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
1
0
0
0
0
2+ (a) 1
2
2+
1
0
word (A) ←eam
*
1+ (a) 0
ADDSP #imm8
ADDSP #imm16
2
3
word (SP) ← (SP) +ext (imm8)
word (SP) ← (SP) +imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
3
0
0
0
0
1
MOV
MOV
A, brgl
brg2, A
2
2
byte (A) ← (brgl)
byte (brg2) ← (A)
Z
–
*
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
0
0
0
0
*
1
NOP
ADB
DTB
PCB
SPB
NCC
CMR
1
1
1
1
1
1
1
No operation
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no flag change
Prefix code for common register bank
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB, DPR : 2 states
*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)
*3: 29 + (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)
*4: Pop count × (c), or push count × (c)
*5: Pop count or push count.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
115
MB90650A Series
Table 21 Bit Manipulation Instructions [21 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
#
~
B
Operation
MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp
3
4
3
5
5
4
0
0
0
(b) byte (A) ← (dir:bp) b
(b) byte (A) ← (addr16:bp) b
(b) byte (A) ← (io:bp) b
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A
3
4
3
7
7
6
0 2× (b) bit (dir:bp) b ← (A)
0 2× (b) bit (addr16:bp) b ← (A)
0 2× (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
SETB dir:bp
SETB addr16:bp
SETB io:bp
3
4
3
7
7
7
0 2× (b) bit (dir:bp) b ← 1
0 2× (b) bit (addr16:bp) b ← 1
0 2× (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
CLRB dir:bp
CLRB addr16:bp
CLRB io:bp
3
4
3
7
7
7
0 2× (b) bit (dir:bp) b ← 0
0 2× (b) bit (addr16:bp) b ← 0
0 2× (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
1
BBC dir:bp, rel
BBC addr16:bp, rel
BBC io:bp, rel
4
5
4
0
0
0
(b) Branch when (dir:bp) b = 0
(b) Branch when (addr16:bp) b = 0
(b) Branch when (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
*
1
*
2
*
1
BBS dir:bp, rel
BBS addr16:bp, rel
BBS io:bp, rel
4
5
4
0
0
0
(b) Branch when (dir:bp) b = 1
(b) Branch when (addr16:bp) b = 1
(b) Branch when (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
*
1
*
2
*
3
Branch when (addr16:bp) b = 1, bit = 1
SBBS addr16:bp, rel
WBTS io:bp
5
3
3
0 2× (b)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
*
*
5
4
0
0
Wait until (io:bp) b = 1
Wait until (io:bp) b = 0
–
–
–
–
*
*
*
4
5
WBTC io:bp
*
*1: 8 when branching, 7 when not branching
*2: 7 when branching, 6 when not branching
*3: 10 when condition is satisfied, 9 when not satisfied
*4: Undefined count
*5: Until condition is satisfied
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
116
MB90650A Series
Table 22 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
SWAP
SWAPW
EXT
EXTW
ZEXT
ZEXTW
#
~
B
Operation
1
1
1
1
1
1
3
2
1
2
1
1
0
0
0
0
0
0
0 byte (A) 0 to 7 ↔ (A) 8 to 15
0 word (AH) ↔ (AL)
0 byte sign extension
0 word sign extension
0 byte zero extension
0 word zero extension
–
–
X
–
Z
–
–
*
–
X
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
Table 23 String Instructions [10 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
#
~
B
Operation
2
5
3
Byte transfer @AH+ ← @AL+, counter = RW0
Byte transfer @AH– ← @AL–, counter = RW0
MOVS/MOVSI
MOVSD
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
2
5
3
*
1
5
4
Byte retrieval (@AH+) – AL, counter = RW0
Byte retrieval (@AH–) – AL, counter = RW0
SCEQ/SCEQI
SCEQD
2
2
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
*
*
*
*
*
1
5
4
*
5
3
Byte filling @AH+ ← AL, counter = RW0
FISL/FILSI
2
–
–
–
–
–
*
*
–
–
–
6m +6
*
*
2
8
6
Word transfer @AH+ ← @AL+, counter = RW0
Word transfer @AH– ← @AL–, counter = RW0
MOVSW/MOVSWI 2
MOVSWD
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
2
8
6
2
*
1
8
7
Word retrieval (@AH+) – AL, counter = RW0
Word retrieval (@AH–) – AL, counter = RW0
SCWEQ/SCWEQI 2
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
*
*
*
*
*
1
8
7
SCWEQD
2
*
8
6
Word filling @AH+ ← AL, counter = RW0
FILSW/FILSWI
2
–
–
–
–
–
*
*
–
–
–
6m +6
*
*
m: RW0 value (counter value)
n: Loop count
*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs
*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case
*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) separately
for each.
*4: (b) × n
*5: 2 × (RW0)
*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c) separately
for each.
*7: (c) × n
*8: 2 × (RW0)
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
117
MB90650A Series
■ ORDERING INFORMATION
Model
Package
Remarks
MB90652APFV
MB90653APFV
MB90P653APFV
MB90654APFV
MB90F654APFV
100-pin plastic LQFP
(FPT-100P-M05)
MB90652APF
MB90653APF
MB90P653APF
MB90654APF
MB90F654APF
100-pin plastic QFP
(FPT-100P-M06)
118
MB90650A Series
■ PACKAGE DIMENSIONS
100-pin plastic LQFP
(FPT-100P-M05)
16.00±0.20(.630±.008)SQ
1.50 –+00..1200
.059 –+..000048
(Mouting height)
75
51
14.00±0.10(.551±.004)SQ
76
50
12.00
(.472)
REF
15.00
(.591)
NOM
Details of "A" part
0.15(.006)
INDEX
0.15(.006)
100
26
0.15(.006)MAX
0.40(.016)MAX
"B"
1
25
LEAD No.
"A"
0.50(.0197)TYP
0.18 –+00..0038
0.127 +–00..0025
.005 +–..000012
M
Details of "B" part
0.08(.003)
.007 –+..000013
0.10±0.10
(.004±.004)
(STAND OFF)
0.50±0.20(.020±.008)
0.10(.004)
0~10°
C
Dimensions in mm (inches)
1995 FUJITSU LIMITED F100007S-2C-3
100-pin plastic QFP
(FPT-100P-M06)
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
3.35(.132)MAX
(Mounting height)
0.05(.002)MIN
(STAND OFF)
80
51
81
50
12.35(.486)
16.30±0.40
14.00±0.20 17.90±0.40
(.551±.008) (.705±.016)
REF
(.642±.016)
INDEX
31
100
"A"
1
30
LEAD No.
0.65(.0256)TYP
0.30±0.10
(.012±.004)
0.15±0.05(.006±.002)
Details of "B" part
M
0.13(.005)
Details of "A" part
0.25(.010)
0.30(.012)
"B"
0.10(.004)
0
10°
0.18(.007)MAX
0.53(.021)MAX
18.85(.742)REF
0.80±0.20
(.031±.008)
22.30±0.40(.878±.016)
C
1994 FUJITSU LIMITED F100008-3C-2
Dimensions in mm (inches)
119
MB90650A Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
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The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
measurement equipment, personal or household devices, etc.).
CAUTION:
Fax: (408) 922-9179
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
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FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
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Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
http://www.fmap.com.sg/
F9910
FUJITSU LIMITED Printed in Japan
相关型号：
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