MB90800_09_技术文档

FUJITSU MICROELECTRONICS

DATA SHEET

DS07-13733-6E

16-bit Microcontroller

CMOS

F²MC-16LX MB90800 Series

MB90803/803S/F803/F803S/F804-101/

MB90F804-201/F809/F809S/V800

■ DESCRIPTION

The MB90800 series is a general-purpose 16-bit microcontroller that has been developed for high-speed real-

time processing required for industrial and office automation equipment and process control, etc. The LCD

controller of 48 segment four common is built into.

Instruction set has taken over the same AT architecture as in the F²MC-8L and F²MC-16L, and is further enhanced

to support high level languages, extend addressing mode, enhanced divide/multiply instructions with sign and

enrichmentofbitprocessing. Inaddition, longwordprocessingisnowavailablebyintroducinga32-bitaccumulator.

Note: F²MC is the abbreviation of Fujitsu Flexible Microcontroller.

■ FEATURES

• Clock

• Built-in PLL clock frequency multiplication circuit

• Operating clock (PLL clock) : divided-by-2 of oscillation (at oscillation of 6.25 MHz) or

1 to 4 times the oscillation (at oscillation of 6.25 MHz to 25 MHz).

• Minimum instruction execution time of 40.0 ns (at oscillation of 6.25 MHz, four times the PLL clock, operation

at Vcc = 3.3 V)

• The maximum memory space:16 Mbytes

• 24-bit internal addressing

• Bank addressing

(Continued)

For the information for microcontroller supports, see the following web site.

http://edevice.fujitsu.com/micom/en-support/

2009.9

MB90800 Series

(Continued)

• Optimized instruction set for controller applications

• Wide choice of data types (bit, byte, word, and long word)

• Wide choice of addressing modes (23 types)

• High code efficiency

• Enhanced high-precision computing with 32-bit accumulator

• Enhanced Multiply/Divide instructions with sign and the RETI instruction

• Instruction system compatible with high-level language (C language) and multitask

• Employing system stack pointer

• Instruction set has symmetry and barrel shift instructions

• Program Patch Function (2 address pointer)

• 4-byte instruction queue

• Interrupt function

• The priority level can be set to programmable.

• Interrupt function with 32 factors

• Data transfer function

• Expanded intelligent I/O service function (EI²OS): Maximum of 16 channels

• Low Power Consumption Mode

• Sleep mode (a mode that halts CPU operating clock)

• Time-base timer mode (a mode that operates oscillation clock and time-base timer)

• Watch mode (mode in which only the subclock and watch timers operate)

• Stop mode (a mode that stops oscillation clock and sub clock)

• CPU blocking mode (operating CPU at each set cycle)

• Package

• QFP-100 (FPT-100P-M06 : 0.65 mm lead pitch)

• Process : CMOS technology

2

DS07-13733-6E

MB90800 Series

■ PRODUCT LINEUP

Part number

MB90V800-

101/201

MB90F804-

101/201

MB90803/

MB90803S

MB90F803/

MB90F803S

MB90F809/

MB90F809S

Item

Flash

memory

products

Evaluation

product

Mask ROM prod-

ucts

Type

Flash memory products

On-chip PLL clock multiplication method( × 1, × 2, × 3, × 4, 1/2 when PLL stops)

Minimum instruction execution time of 40.0 ns

System clock

Sub clock

(at oscillation of 6.25 MHz, four times the PLL clock)

With sub clock:

201 option

With sub clock:

Part number of products without "S" suffix

Without sub clock: 101 option

Without sub clock: Part number of products with "S" suffix

128 Kbytes

ROM capacity

RAM capacity

No

256 Kbytes

16 Kbytes

128 Kbytes

4 Kbytes

dual

operation

192 Kbytes

10 Kbytes

28 Kbytes

4 Kbytes

Number of basic instructions

Minimum instruction execution time : 40.0 ns/6.25 MHz oscillator

(When four times is used : machine clock

: 351

CPU functions

Ports

25 MHz, Power supply voltage : 3.3 V 0.3 V)

: 23 types

: 2 address pointers

: 16 Mbytes

Addressing type

Program Patch Function

The maximum memory space

I/O port (CMOS) 68 ports (shared with resources), (70 ports when the subclock is not used)

LCD

Segment driver that can drive the LCD panel (liquid crystal display) directly, and common driv-

controller/driver

er 48 SEG × 4 COM

16-bit

free-run

timer

1 channel

Overflow interrupt

16-bit

Output

input/

2 channels

compare

output

(OCU)

timer

Pin input factor: matching of the compare register

Input

capture

(ICU)

2 channels

Rewriting a register value upon a pin input (rising edge, falling edge, or both edges)

16-bit reload timer operation (toggle output, single shot output selectable)

The event count function is optional. The event count function is optional.

Three channels are built in.

16-bit

Reload Timer

Output pin × 2 ports

Operating clock frequency : fcp, fcp/22, fcp/24, fcp/26

Two channels are built in.

16-bit

PPG timer

Time-base timer

Watchdog timer

1 channel

Timer clock

output

circuit

Clock with a frequency of external input clock divided by 16/32/64/128 can be

output externally.

I²C bus

I²C Interface. 1 channel is built-in.

(Continued)

DS07-13733-6E

3

MB90800 Series

(Continued)

Part number

MB90V800-

101/201

MB90F804-

101/201

MB90803/

MB90803S

MB90F803/

MB90F803S

MB90F809/

MB90F809S

Item

12 channels (input multiplex)

The 8-bit resolution or 10-bit resolution can be set.

Conversion time : 5.9 μs (When machine clock 16.8 MHz works).

8/10-bit

A/D converter

Full-duplex double buffer

UART

Asynchronous/synchronous transmit (with start/stop bits) are supported.

Two channels are built in.

Extended I/O serial

interface

Two channels are built in.

Interrupt delay

interrupt

One channel

DTP/External

interrupt

4 channels

Interrupt causes : “L”→“H” edge/“H”→“L” edge/“L” level/“H” level selectable

Low Power

Consumption Mode

Sleep mode/Time-base timer mode/Watch mode/Stop mode/CPU intermittent mode

Process

CMOS

Operating voltage

2.7 V to 3.6 V

4

DS07-13733-6E

MB90800 Series

■ PIN ASSIGNMENT

(TOP VIEW)

P24/SEG32

P25/SEG33

P26/SEG34

1

2

3

4

5

6

7

8

9

80 P03/SEG15

79 P02/SEG14

78 P01/SEG13

77 P00/SEG12

76 SEG11

75 SEG10

74 SEG9

73 SEG8

72 SEG7

71 SEG6

70 SEG5

69 SEG4

68 SEG3

67 SEG2

66 V^SS

P27/SEG35

P30/SEG36/SO3

P31/SEG37/SC3

P32/SEG38/SI3

P33/SEG39/TMCK

P34/SEG40/IC0

P35/SEG41/IC1 10

P36/SEG42/OCU0 11

P37SEG43/OCU1 12

X0A/P90 13

X1A/P91 14

V^CC15

VSS 16

P40/LED0 17

P41/LED1 18

P42/LED2 19

P43/LED3 20

P44/LED4 21

QFP-100

65 VCC

64 SEG1

63 SEG0

62 P84/COM3

61 P83/COM2

60 COM1

59 COM0

58 V3

57 V2/P82

56 V1/P81

55 V0/P80

54 RST

P45/LED5/TOT0 22

P46/LED6/TOT1 23

P47/LED7/TOT2 24

P50/SEG44/TIN0 25

P51/SEG45/TIN1 26

P52/SEG46/TIN2/PPG0 27

P53/SEG47/PPG1 28

P54/SI0 29

53 MD0

52 MD1

P55/SC0 30

51 MD2

(FPT-100P-M06)

DS07-13733-6E

5

MB90800 Series

■ PIN DESCRIPTION

I/O

Pin Name Circuit

Status/function

at reset

Pin No.

Function

Type*

It is a terminal which connects the oscillator.

When connecting an external clock, leave the x1 pin

unconnected.

Oscillation

status

92, 93

X1, X0

A

Oscillation

status

It is 32 kHz oscillation pin.

(Dual-line model)

X0A, X1A

P90, P91

MD2

B

G

M

13, 14

51

Port input

(High-Z)

General purpose input/output port.

(Single-line model)

Input pin for selecting operation mode.

Connect directly to Vss.

Mode Pins

Input pin for selecting operation mode.

Connect directly to Vcc.

52, 53

54

MD1, MD0

RST

L

Mode Pins

Reset input

K

External reset input pin.

SEG0

to

SEG11

63, 64,

67 to 76

LCD SEG

output

A segment output terminal of the LCD controller/

driver.

D

SEG12

to

SEG19

A segment output terminal of the LCD controller/

driver.

77 to 84

E

P00 to P07

General purpose input/output port.

SEG20

to

SEG27

A segment output terminal of the LCD controller/

driver.

85 to 89,

94 to 96

E

P10 to P17

General purpose input/output port.

SEG28

to

SEG35

A segment output terminal of the LCD controller/

driver.

97 to 100,

1 to 4

P20 to P27

SEG36

P30

General purpose input/output port.

Port input

(High-Z)

A segment output terminal of the LCD controller/

driver.

General purpose input/output port.

5

6

E

Serial data output pin of serial I/O ch.3.

Valid when serial data output of serial I/O ch.3 is

enabled.

SO3

A segment output terminal of the LCD controller/

driver.

SEG37

P31

General purpose input/output port.

Serial clock I/O pin of serial I/O ch.3.

Valid when serial clock output of serial I/O ch.3 is

enabled.

SC3

(Continued)

6

DS07-13733-6E

MB90800 Series

I/O

Pin Name Circuit

Type*

Status/function

at reset

Pin No.

Function

A segment output terminal of the LCD controller/

driver.

SEG38

P32

E

General purpose input/output port.

7

Serial data input pin of serial I/O ch.3.

SI3

This pin may be used during serial I/O ch.3 in input

mode, so it cannot use as other pin function.

A segment output terminal of the LCD controller/

driver.

SEG39

8

P33

E

General purpose input/output port.

Timer clock output pin.

It is effective when permitting the power output.

TMCK

SEG40,

SEG41

A segment output terminal of the LCD controller/

driver.

9, 10

P34, P35

IC0, IC1

General purpose input/output port.

External trigger input pin of input capture ch.0/ch.1.

SEG42,

SEG43

A segment output terminal of the LCD controller/

driver.

11, 12

P36, P37

E

F

General purpose input/output port.

Port input

(High-Z)

OCU0,

OCU1

Output terminal for the output compares ch.0/ch.1.

LED0

to

LED4

It is a output terminal for LED (I^OL= 15 mA).

General purpose input/output port.

17 to 21

P40 to P44

LED5

to

LED7

It is a output terminal for LED (I^OL= 15 mA).

General purpose input/output port.

P45 to P47

22 to 24

F

External event output pin of reload timer ch.0 to

ch.2.

It is effective when permitting the external event

output.

TOT0

to

TOT2

SEG44,

SEG45

A segment output terminal of the LCD controller/

driver.

P50, P51

General purpose input/output port.

25, 26

E

External clock input pin of reload timer ch.0, ch.1.

It is effective when permitting the external clock

input.

TIN0,

TIN1

(Continued)

DS07-13733-6E

7

MB90800 Series

I/O

Pin Name Circuit

Status/function

at reset

Pin No.

Function

Type*

A segment output terminal of the LCD controller/

driver.

SEG46

P52

General purpose input/output port.

27

E

External clock input pin of reload timer ch.2.

It is effective when permitting the external clock

input.

TIN2

PPG0

PPG timer (ch.0) output pin.

A segment output terminal of the LCD controller/

driver.

SEG47

28

E

P53

General purpose input/output port.

PPG (ch.1) timer output pin.

PPG1

Serial data input pin of UART ch.0.

SIO

P54

SC0

P55

SO0

P56

SI1

This pin may be used during UART ch.0 in receiving

mode, so it cannot use as other pin function.

29

30

31

G

General purpose input/output port.

Port input

(High-Z)

Serial clock input/output pin of UART ch.0.

It is effective when permitting the serial clock output

of UART ch.0.

General purpose input/output port.

Serial data output pin of UART ch.0.

It is effective when permitting the serial clock output

of UART ch.0.

General purpose input/output port.

Serial data input pin of UART ch.1.

This pin may be used during UART ch.1 in receiving

mode, so it cannot use as other pin function.

33

34

G

I

P57

P76

General purpose input/output port.

AN0

to

AN4

Analog input pin ch.0 to ch.4 of A/D

converter. Enabled when analog input setting is

“enabled”(set by ADER).

36 to 40

P60 to P64

General purpose input/output port.

(Continued)

8

DS07-13733-6E

MB90800 Series

I/O

Pin Name Circuit

Type*

Status/function

at reset

Pin No.

Function

AN5

to

AN7

Analog input pin ch.5 to ch.7 of A/D

converter. Enabled when analog input setting is

“enabled”.

41 to 43

P65 to P67

I

General purpose input/output port.

INT0

to

INT2

Functions as an external interrupt ch.0 to ch.2 input

pin.

Analog input

(High-Z)

Analog input pin ch.8 of A/D converter.

Enabled when analog input setting is “enabled”.

AN8

45

46

I

P70

General purpose input/output port.

INT3

Functions as an external interrupt ch.3 input pin.

Analog input pin ch.9 of A/D converter.

Enabled when analog input setting is “enabled”.

AN9

P71

General purpose input/output port.

Serial clock input/output pin of UART ch.1.

It is effective when permitting the serial clock output

of UART ch.1.

SC1

Analog input pin ch.10 of A/D converter.

Enabled when analog input setting is “enabled”.

AN10

P72

Port input

(High-Z)

General purpose input/output port.

47

48

I

Serial data output pin of serial I/O ch.1.

Valid when serial data output of serial I/O ch.1 is

enabled.

SO1

Analog input pin ch.11 of A/D converter.

Enabled when analog input setting is “enabled”.

AN11

P73

General purpose input/output port.

Serial data input pin of serial I/O ch.2.

SI2

This pin may be used during serial I/O ch.2 in input

mode, so it cannot use as other pin function.

(Continued)

DS07-13733-6E

9

MB90800 Series

(Continued)

I/O

Pin Name Circuit

Status/function

at reset

Pin No.

Function

Type*

Data input/output pin of I²C Interface.

This pin is enabled when the I²C interface is operated.

While the I²C interface is running, the port must be set

for input use.

SDA

49

H

General purpose input/output port.

(N-ch open-drain, withstand voltage of 5 V.)

P74

SC2

Serial clock input pin of serial I/O ch.2.

Valid when serial clock output of serial I/O ch.2 is

enabled.

Port input

(High-Z)

Clock input/output pin of I²C Interface.

This pin is enabled when the I²C interface is operated.

While the I²C interface is running, the port must be set

for input use.

SCL

50

H

General purpose input/output port.

(N-ch open-drain, withstand voltage of 5 V.)

P75

Serial data output pin of serial I/O ch.2.

Valid when serial data output of serial I/O ch.2 is

enabled.

SO2

LCD controller/driver.

Reference power terminals of LCD controller/driver.

V0 to V2

LCD drive power

supply input

55 to 57

59, 60

61, 62

J

D

E

P80 to P82

General purpose input/output port.

COM0,

COM1

LCD COM

output

A common output terminal of the LCD controller/

driver.

P83, P84

General purpose input/output port.

Port input

(High-Z)

COM2,

COM3

A common output terminal of the LCD controller/

driver.

32

35

AV^CC

AV^SS

C

A/D converter exclusive power supply input pin.

A/D converter-exclusive GND power supply pin.

LCD controller/driver

58

V3

V^CC

V^SS

J

Power supply Reference power terminals of LCD controller/driver.

15, 65, 90

⎯

These are power supply input pins.

16, 44,

66, 91

GND power supply pin.

* : Refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types.

10

DS07-13733-6E

MB90800 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

Oscillation feedback resistance :

1 MΩ approx.

X1

Clock input

P-ch N-ch

X0

Standby control signal

Clock input

B

Low-rate oscillation feedback resistor,

approx.10 MΩ

X1A

P-ch N-ch

X0A

Standby control signal

C

Analog power supply input protection

circuit

P-ch

N-ch

AVP

D

LCDC output

P-ch

N-ch

R

LCDC output

E

• CMOS output

• LCDC output

P-ch

• CMOS hysteresis input

(With input interception function at

standby)

N-ch

R

LCDC output

CMOS hysteresis input

Standby control signal

(Continued)

DS07-13733-6E

11

MB90800 Series

Type

Circuit

Remarks

• CMOS output

F

(Heavy-current I^OL=15 mA for LED

drive)

• CMOS hysteresis input

(With input interception function at

standby)

P-ch

N-ch

R

CMOS hysteresis input

Standby control signal

G

• CMOS output

• CMOS hysteresis input

(With input interception function at

standby)

P-ch

N-ch

Notes:•TheI/Oportandinternalresources

share one output buffer for their

outputs.

R

CMOS hysteresis input

Standby control signal

• TheI/Oportandinternalresources

share one input buffer for their

input.

H

• CMOS hysteresis input

(With input interception function at

standby)

N-ch

Nout

• N-ch open drain output

R

CMOS hysteresis input

Standby control signal

I

• CMOS output

• CMOS hysteresis input

(With input interception function at

standby)

P-ch

N-ch

• Analog input

(If the bit of analog input enable

register = 1, the analog input of A/D

converter is enabled.)

R

CMOS hysteresis input

Standby control signal

A/D converter

Analog input

Notes:•TheI/Oportandinternalresources

share one output buffer for their

outputs.

• TheI/Oportandinternalresources

share one input buffer for their

inputs.

(Continued)

12

DS07-13733-6E

MB90800 Series

(Continued)

Type

Circuit

Remarks

J

• CMOS output

• CMOS hysteresis input

(With input interception function at

standby)

P-ch

N-ch

• LCD drive power supply input

R

CMOS hysteresis input

Standby control signal

LCD drive power supply

K

L

CMOS hysteresis input with pull-up

resistor.

R

Reset input

CMOS hysteresis input

R

CMOS hysteresis input

M

CMOS hysteresis input with pull-down

resistor

R

DS07-13733-6E

13

MB90800 Series

■ HANDLING DEVICES

1. Preventing Latch-up, Turning on Power Supply

Latch-up may occur on CMOS IC under the following conditions:

• If a voltage higher than V^CCor lower than VSS is applied to input and output pins,

• A voltage higher than the rated voltage is applied between V^CCpin and VSS pin.

• If the AV^CCpower supply is turned on before the VCC voltage.

Ensure that you apply a voltage to the analog power supply at the same time as V^CCor after you turn on the

digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as

V^CCand the digital power supply).

When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When

using CMOS IC, take great care to prevent the occurrence of latch-up.

2. Treatment of unused pins

If unused input pins are left open, they may cause abnormal operation or latch-up which may lead to permanent

damage to the semiconductor. Any such pins should be pulled up or pulled down through resistance of at least

2 kΩ.

Any unused input/output pins should be left open in output status, or if found set to input status, they should be

treated in the same way as input pins.

Any unused output pins should be left open.

3. Treatment of A/D converter power supply pins

Even if the A/D converter is not used, pins should be connected so that AVCC = VCC, and AVSS = VSS.

4. About the attention when the external clock is used

In using an external clock, drive pin X0 only and leave pin X1 open.

The example of using an external clock is shown below.

X0

MB90800 Series

OPEN

X1

Please set X0A = GND and X1A = open without subclock mode.

The following figure shows the using sample.

X0A

MB90800 Series

OPEN

X1A

14

DS07-13733-6E

MB90800 Series

5. Treatment of power supply pins (VCC/VSS)

In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device

to avoid abnormal operations including latch-up. However, you must connect all power supply pins to external

power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of

strobe signals caused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the V^CCand VSS pins of this device at the low impedance.

It is also advisable to connect a ceramic capacitor of approximately 0.1 μF as a bypass capacitor between V^CC

and VSS near this device.

6. About Crystal oscillators circuit

Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the printed circuit

board so that X0/X1 pins and X0A/X1A pins, the crystal oscillator (or the ceramic oscillator) and the bypass

capacitor to ground are located as close to the device as possible.

It is strongly recommended to design the PC board artwork with the X0/X1 pins and X0A/X1A pins surrounded

by ground plane because stable operation can be expected with such a layout.

Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.

7. Caution on Operations during PLL Clock Mode

On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while

the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its

self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.

8. Stabilization of Supply Power Supply

A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage

operating range.Therefore, the V^CCsupply voltage should be stabilized. For reference, the supply voltage should

be controlled so that V^CCripple variations (peak- to-peak values) at commercial frequencies (50 Hz/60 Hz) fall

below 10% of the standard V^CCsupply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at

instantaneous power switching.

9. Note on Using the two-subsystem product as one-subsystem product

If you are using only one subsystem of the MB90800 series that come in one two-subsystem product, use it with

X0A = V^SSand X1A = OPEN.

10. Write to FLASH

Ensure that you must write to FLASH at the operating voltage VCC = 3.0 V to 3.6 V.

DS07-13733-6E

15

MB90800 Series

■ BLOCK DIAGRAM

X0, X1

X0A*, X1A*

RST

CPU F²MC-16LX

core

Clock control

circuit

RAM

V0/P80

V1/P81

V2/P82

V3

COM0

COM1

(2/4/10/16/28 Kbytes)

ROM/Flash

(128/192/256 Kbytes)

Port

8

Interrupt controller

P83/COM2

P84/COM3

12

SEG0 to SEG11

P60/AN0

P61/AN1

P62/AN2

P63/AN3

8/10 bits PPG

A/D converter

8

P00 to P07/

SEG12 to SEG19

LCD

Controller/

Driver

Port

0

Port

6

P64/AN4

P65/AN5/INT0

P66/AN6/INT1

P67/AN7/INT2

External interrupt

(4 channels)

P10 to P17/

SEG20 to SEG27

Port

1

P70/AN8/INT3

P71/AN9/SC1

P72/AN10/SO1

P73/AN11/SI2

P74/SDA/SC2

P75/SCL/SO2

P76

I²C

Port

7

P20 to P27/

SEG28 to SEG35

Port

2

Serial I/O 2/3

P30/SEG36/SO3

P31/SEG37/SC3

P32/SEG38/SI3

P33/SEG39/TMCK

P34/SEG40/IC0

P35/SEG41/IC1

P36/SEG42/OCU0

P37/SEG43/OCU1

Prescaler

2/3

Port

3

P90*

P91*

Port

9

OCU0/OCU1

Free-run timer

* : X0A/X1A and P90/P91 can be

switched by the option.

P40/LED0

P41/LED1

P42/LED2

P43/LED3

P44/LED4

ICU0/ICU1

X0A/X1A: With sub clock

Part number of products without

201 option

P90/P91: Without sub clock

Part number of products with

101 option

Port

4

“S” suffix/

Timer clock output

P45/LED5/TOT0

P46/LED6/TOT1

P47/LED7/TOT2

Reload timer

0/1/2

“S” suffix/

P50/SEG44/TIN0

P51/SEG45/TIN1

P52/SEG46/TIN2/PPG0

P53/SEG47/PPG1

P54/SI0

PPG0/PPG1

Notes:

Port

5

• Built-in ROM of MB90V800 (evaluation) is not

exist.

• The device has built-in RAM of 28 Kbytes.

UART0/UART1

P55/SC0

P56/SO0

P57/SI1

Prescaler

0/1

16

DS07-13733-6E

MB90800 Series

■ MEMORY MAP

ROM mirror function

ROM area

FFFFFFH

Address #2

00FFFFH

008000H

ROM mirror area

32 Kbytes

007917H

007900H

Extended I/O area 2

Address #1

RAM area

Register

000100H

0000CFH

0000C0H

Extended I/O area 1

I/O area

0000BFH

000000H

Part number

Address #1

Address #2

MB90803/S,

MB90F803/S

0010FF^H

FE0000H

MB90F809/S

0028FFH

0040FFH

0070FFH

FD0000H

FC0000H

F80000H*

MB90F804-101/201

MB90V800-101/201

* : ROM is not built into MB90V800.

F80000^His ROM decipherment region on the tool side.

Memory Map of MB90800 Series

Notes : • When the ROM mirror function register has been set, the mirror image data at higher addresses

( “FF4000^Hto FFFFFFH” ) of bank FF is visible from the higher addresses ( “008000H to 00FFFFH”) of

bank 00.

• The ROM mirror function is for using the C compiler small model.

• The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Note that because the ROM

area of bank FF exceeds.

32 Kbytes, all data in the ROM area cannot be shown in mirror image in bank 00.

• When the C compiler small model is used, the data table can be shown as mirror image at “008000^Hto

00FFFF^H”by storing the data table at “FF8000H to FFFFFFH”. Therefore, data tables in the ROM area

can be referenced without declaring the far addressing with the pointer.

DS07-13733-6E

17

MB90800 Series

■ F²MC-16L CPU Programming model

• Dedicated Registers

AH

AL

Accumulator

USP

SSP

PS

User stack pointer

System stack pointer

Processor status

Program counter

PC

DPR

Direct page register

PCB

DTB

USB

SSB

ADB

Program bank register

Data bank register

User stack bank register

System stack bank register

Additional data bank register

8-bit

16-bit

32-bit

• General purpose registers

MSB

LSB

16-bit

000180^H+ RP × 10H

RW0

RW1

RW2

RW3

RL0

RL1

RL2

RL3

R1

R3

R5

R7

R0

R2

R4

R6

RW4

RW5

RW6

RW7

• Processor status

bit

15

13 12

8 7

0

PS

ILM

RP

CCR

18

DS07-13733-6E

MB90800 Series

■ I/O MAP

Register

abbreviation

Read/

Write

Address

Register

Port 0 data register

Resource name

Initial Value

000000^H

000001H

000002H

000003H

000004H

000005H

000006H

000007H

000008H

000009H

PDR0

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

XXXXXXXXB

- XXXXXXXB

- - - XXXXXB

- - - - - - XXB

PDR1

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

Port 5 data register

Port 6 data register

Port 7 data register

Port 8 data register

Port 9 data register

PDR2

PDR3

PDR4

PDR5

PDR6

PDR7

PDR8

PDR9

00000AH

to

Prohibited

00000F^H

000010^H

000011H

000012H

000013H

000014H

000015H

000016H

000017H

000018H

000019H

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

DDR7

DDR8

DDR9

Port 0 direction register

Port 1 direction register

Port 2 direction register

Port 3 direction register

Port 4 direction register

Port 5 direction register

Port 6 direction register

Port 7 direction register

Port 8 direction register

Port 9 direction register

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

0 0 0 0 0 0 0 0B

- 0 0 0 0 0 0 0B

- - - 0 0 0 0 0B

- - - - - - 0 0B

00001AH

to

Prohibited

00001D^H

00001E^H

00001FH

000020H

000021H

ADER0

ADER1

SMR0

SCR0

Analog input enable 0 register

Analog input enable 1 register

Serial mode register

R/W

Port 6, A/D

Port 7, A/D

1 1 1 1 1 1 1 1B

- - - - 1 1 1 1B

0 0 0 0 0 - 0 0B

0 0 0 0 0 1 0 0B

Serial control register

UART0

SIDR0/

SODR0

000022H

Serial input/output register

Serial data register

R/W

XXXXXXXX^B

000023H

000024H

SSR0

0 0 0 0 1 0 0 0B

Prohibited

Communication prescaler control

register

000025^H

CDCR0

R/W

Prescaler 0

0 0 - - 0 0 0 0^B

000026H

000027^H

Prohibited

(Continued)

DS07-13733-6E

19

MB90800 Series

Register

Address

Read/

Write

Register

Serial mode register

Resource name

Initial Value

abbreviation

000028^H

000029H

SMR1

SCR1

R/W

0 0 0 0 0 - 0 0B

0 0 0 0 0 1 0 0B

Serial control register

Serial input/output register

Serial data register

R/W, W

UART1

SIDR1/

SODR1

00002AH

R/W

XXXXXXXX^B

00002BH

00002CH

SSR1

R/W, R

0 0 0 0 1 0 0 0B

Prohibited

Communication prescaler control

register

00002D^H

CDCR1

R/W

Prescaler 1

0 0 - - 0 0 0 0^B

00002EH

00002F^H

000030H

000031H

000032H

000033H

000034^H

000035H

000036H

000037H

000038H

000039^H

00003AH

00003BH

00003CH

00003DH

Prohibited

ENIR

EIRR

ELVR

Interrupt/DTP enable

Interrupt/DTP source

Request level set register

R/W

- - - - 0 0 0 0B

- - - - XXXXB

External interrupt

0 0 0 0 0 0 0 0B

Prohibited

ADCS0

ADCS1

ADCR0

ADCR1

Control status register (lower)

Control status register (upper)

Data register (lower)

R/W

W, R/W

R

0 0 - - - - - - B

0 0 0 0 0 0 0 0B

XXXXXXXXB

A/D converter

Data register (upper)

R, W

0 0 1 0 1 - XXB

Prohibited

ADMR

A/D conversion channel set register

Compare clear register

R/W

0 0 0 0 0 0 0 0B

XXXXXXXX^B

CPCLR

XXXXXXXXB

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

TCDT

TCCSL

TCCSH

Timer counter data register

R/W

16-bit free-run

timer

Timer counter control/status register

(lower)

00003EH

00003FH

0 0 0 0 0 0 0 0^B

0 - - 0 0 0 0 0^B

Timer counter control/status register

(upper)

000040H

to

Prohibited

000043^H

000044^H

000045H

000046H

000047H

000048H

000049H

00004A^H

00004BH

00004CH

00004DH

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

0 0 0 0 0 0 0 0B

IPCP0

Input capture data register 0

R

Input Capture 0/1

IPCP1

ICS01

Input capture data register 1

Control status register

R/W

Prohibited

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

(Continued)

OCCP0

OCCP1

Compare register 0

Compare register 1

R/W

Output compare 0

Output compare 1

20

DS07-13733-6E

MB90800 Series

Register

abbreviation

Read/

Write

Address

Register

Resource name

Initial Value

00004E^H

00004FH

000050H

OCSL

OCSH

Control status register (lower)

Control status register (upper)

R/W

0 0 0 0 - - 0 0B

- - - 0 0 0 0 0B

0 0 0 0 0 0 0 0B

- - - - 0 0 0 0B

XXXXXXXX^B

XXXXXXXXB

0 0 0 0 0 0 0 0B

- - - - 0 0 0 0B

XXXXXXXX^B

XXXXXXXXB

0 0 0 0 0 0 0 0^B

- - - - 0 0 0 0B

XXXXXXXX^B

XXXXXXXXB

0 0 0 1 0 0 0 0^B

0 0 0 0 0 0 0 0B

Output Compare

0/1

TMCSR0L Timer control status register (lower)

000051H TMCSR0H Timer control status register (upper)

16-bit reload

timer 0

000052H

000053H

000054H

TMR0/

TMRLR0

16-bit timer register/Reload register

R/W

TMCSR1L Timer control status register (lower)

R/W

000055H TMCSR1H Timer control status register (upper)

16-bit reload

timer 1

000056H

000057H

000058H

TMR1/

TMRLR1

16-bit timer register/Reload register

R/W

TMCSR2L Timer control status register (lower)

R/W

000059H TMCSR2H Timer control status register (upper)

16-bit reload

timer 2

00005AH

00005BH

00005CH

00005DH

00005EH

00005FH

000060^H

000061H

000062H

TMR2/

TMRLR2

16-bit timer register/Reload register

R/W

LCRL

LCRH

LCRR

LCDC control register (lower)

LCDC control register (upper)

LCDC range register

R/W

LCD controller/

driver

Prohibited

R, R/W

R/W

0 0 0 0 0 0 1 0^B

- - - - 0 0 0 0B

XXXXXXXXB

SIO

(Extended Serial

I/O)

SMCS0

Serial mode control status register

Serial Data Register

SDR0

R/W

Communication prescaler control

register

Communication

prescaler (SIO)

000063H

SDCR0

R/W

0 - - - 0 0 0 0^B

000064H

000065H

000066H

R, R/W

R/W

0 0 0 0 0 0 1 0^B

- - - - 0 0 0 0B

XXXXXXXXB

SIO

(Extended Serial

I/O)

SMCS1

Serial mode control status register

Serial Data Register

SDR1

R/W

Communication prescaler control

register

Communication

prescaler (SIO)

000067H

SDCR1

R/W

0 - - - 0 0 0 0^B

000068H

000069^H

00006AH

00006BH

00006CH

00006DH

00006EH

00006FH

Prohibited

IBSR

IBCR

ICCR

IADR

IDAR

ROMM

I²C status register

I²C control register

I²C clock control register

I²C address register

I²C data register

R

R/W

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

XX0XXXXXB

XXXXXXXXB

XXXXXXX1B

(Continued)

R/W

I²C

R/W

ROM mirror function select register

R/W, W

ROM mirror

DS07-13733-6E

21

MB90800 Series

Register

Address

Read/

Write

Register

Resource name

Initial Value

abbreviation

000070^H

000071H

000072H

000073H

000074H

000075H

000076H

000077H

000078H

000079H

00007AH

00007BH

00007CH

00007DH

00007EH

00007FH

PDCRL0

PDCRH0

PCSRL0

PCSRH0

PDUTL0

PDUTH0

PCNTL0

PCNTH0

PDCRL1

PDCRH1

PCSRL1

PCSRH1

PDUTL1

PDUTH1

PCNTL1

PCNTH1

1 1 1 1 1 1 1 1^B

1 1 1 1 1 1 1 1B

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

- - 0 0 0 0 0 0^B

0 0 0 0 0 0 0 -B

1 1 1 1 1 1 1 1^B

1 1 1 1 1 1 1 1B

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

- - 0 0 0 0 0 0^B

0 0 0 0 0 0 0 -B

PDCRL0/PDCRH0 PPG down counter

register

R

W

PCSRL0/PCSRH0 PPG cycle set

register

16-bit

PPG0

PDUTL0/PDUTH0 PPG duty setting

register

W

PCNTL0/PCNTH0 PPG control status

register

R/W

R

PDCRL1/PDCRH1 PPG down counter

register

PCSRL1/PCSRH1 PPG cycle set

register

W

16-bit

PPG1

PDUTL1/PDUTH1 PPG duty setting

register

W

PCNTL1/PCNTH1 PPG control status

register

R/W

000080H

to

(Reserved)

000095^H

000096^H

000097^H

Prohibited

(Reserved)

000098^H

to

Prohibited

00009D^H

00009E^H

PACSR

DIRR

ROM correction control register

R/W

ROM Correction 0 0 0 0 0 0 0 0B

Delayed interrupt source generated/

release register

00009FH

Delayed interrupt

- - - - - - - 0^B

Low power consumption mode control

register

Low power

consumption

control circuit

0000A0H

0000A1H

LPMCR

CKSCR

R/W, W

R/W, R

0 0 0 1 1 0 0 0^B

1 1 1 1 1 1 0 0B

Clock selector register

0000A2H

to

Prohibited

0000A7^H

0000A8^H

0000A9H

WDTC

TBTC

Watchdog timer control register

Time-base timer control register

R, W

Watchdog timer

XXXXX 1 1 1B

R/W, W Time-base timer 1 - - 0 0 1 0 0B

Watch timer

0000AAH

WTC

Watch timer control register

R/W, R

1 X0 1 1 0 0 0^B

(Sub clock)

0000AB^H

to

Prohibited

0000AD^H

(Continued)

22

DS07-13733-6E

MB90800 Series

(Continued)

Register

abbreviation

Read/

Write

Resource

Initial Value

name

Address

0000AE^H

0000AFH

Register

Flash control register

FMCS

R/W

Flash I/F

0 0 0 X 0 0 0 0B

Timer clock

divide

TMCS

Timer clock output control register

R/W

XXXXX 0 0 0^B

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

0000BDH

0000BEH

0000BFH

0000CAH

0000CBH

0000CCH

001FF0H

001FF1H

001FF2H

001FF3H

001FF4H

001FF5H

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

FWR0

FWR1

SSR0

Interrupt control register 00

Interrupt control register 01

Interrupt control register 02

Interrupt control register 03

Interrupt control register 04

Interrupt control register 05

Interrupt control register 06

Interrupt control register 07

Interrupt control register 08

Interrupt control register 09

Interrupt control register 10

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

Interrupt control register 14

Interrupt control register 15

Flash Program Control Register 0

Flash Program Control Register 1

Sector Conversion Setting Register

R/W, W, R

R/W

0 0 0 0 0 1 1 1B

0 0 0 0 0 0 0 0^B

Interrupt

controller

Flash I/F

R/W

(MB90F803/S 0 0 0 0 0 0 0 0B

only object)

R/W

0 0 XXXXX 0B

XXXXXXXX^B

PADR0

Program address detection register 0

R/W

XXXXXXXXB

Address

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

matching

detection

function

PADR1

VRAM

Program address detection register 1

LCD display RAM

R/W

007900H

to

007917^H

LCD controller/

driver

XXXXXXXX^B

• Read/Write

R/W : Readable and Writable

R

: Read only

: Write only

W

• Initial values

0

1

X

-

: Initial Value is “0”.

: Initial Value is “1”.

: Initial Value is Indeterminate.

: Unused bit

DS07-13733-6E

23

MB90800 Series

■ INTERRUPT SOURCES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS

EI²OS

readiness

Interrupt vector

Number* Address

08H FFFFDCH

Interrupt control register

Interrupt source

Priority

ICR

⎯

Address

⎯

Reset

×

#08

#09

#10

#11

#13

#15

#16

#17

#18

#19

#21

#23

#24

#25

#26

#27

#29

#31

#33

#35

#36

#37

#38

#39

#40

#41

#42

High

INT 9 instruction

09^HFFFFD8H

0A^HFFFFD4H

0B^HFFFFD0H

0DH FFFFC8H

0FH FFFFC0H

10H FFFFBCH

11H FFFFB8H

12H FFFFB4H

13H FFFFB0H

15H FFFFA8H

17H FFFFA0H

18H FFFF9CH

19H FFFF98H

1AH FFFF94H

1BH FFFF90H

1DH FFFF88H

1FH FFFF80H

21H FFFF78H

23H FFFF70H

24H FFFF6CH

25H FFFF68H

26H FFFF64H

27H FFFF60H

28H FFFF5CH

29H FFFF58H

2AH FFFF54H

⎯

Exceptional treatment

DTP/External interrupt ch.0

DTP/External interrupt ch.1

Serial I/O ch.2

⎯

ICR00

ICR01

0000B0H

0000B1H

×

ICR02

ICR03

0000B2H

0000B3H

DTP/External interrupt ch.2/ch.3

Serial I/O ch.3

16-bit free-run timer

Watch timer

ICR04

ICR05

0000B4H

0000B5H

16-bit Reload Timer ch.2

16-bit Reload Timer ch.0

16-bit Reload Timer ch.1

Input capture ch.0

ICR06

ICR07

0000B6H

0000B7H

Input capture ch.1

PPG timer ch.0 counter-borrow

Output compare match

PPG timer ch.1 counter-borrow

Time-base timer

ICR08

ICR09

ICR10

ICR11

0000B8H

0000B9H

0000BAH

0000BBH

×

UART0 reception end

UART0 transmission end

A/D converter conversion termination

I²C Interface

ICR12

ICR13

ICR14

ICR15

0000BCH

0000BDH

0000BEH

0000BFH

UART1 : Reception

UART1 : Transmission

Flash memory status

Delayed interrupt output module

×

Low

: Available

× : Unavailable

: Available El²OS function is provided.

: Available when a cause of interrupt sharing a same ICR is not used.

* : When interrupts of the same level are output at the same time, the interrupt with the smallest interrupt vector

number has the priority.

• For a resource that has two interrupt causes in the same interrupt control register (ICR), use of EI²OS is

enabled, EI²OS is started upon detection of one of the interrupt causes. As interrupts other than the start

causearemaskedduringEI²OSstart, maskingoneoftheinterruptcausesisrecommendedwhenusingEI²OS.

• For a resource that has two interrupt causes in the same interrupt control register (ICR), the interrupt flag is

cleared by an EI²OS interrupt clear signal.

24

DS07-13733-6E

MB90800 Series

■ PERIPHERAL RESOURCES

1. I/O port

The I/O ports function to output data from the CPU to I/O pins by setting their port data register (PDR) and send

signals input to I/O pins to the CPU. In addition, the port can randomly set the direction of the input/output of

the port in bit by the port direction register (DDR).

The MB90800 series has 68 (70 ports when the subclock is not used) input/output pins. Port0 to port8 (port0 to

port9 when product without the subclock is used) are input/output port.

(1) Port data register

PDR0

bit

Initial Value Access

Indeterminate R/W*

7

6

5

4

3

2

1

0

Address : 000000^H

P07

P06

P05

P04

P03

P02

P01

P00

PDR1

bit

15

14

13

12

11

10

9

8

Address : 000001^H

Indeterminate R/W*

P17

P16

P15

P14

P13

P12

P11

P10

PDR2

bit

7

6

5

4

3

2

1

0

Address : 000002^H

P27

P26

P25

P24

P23

P22

P21

P20

PDR3

bit

15

14

13

12

11

10

9

8

Address : 000003^H

P37

P36

P35

P34

P33

P32

P31

P30

PDR4

bit

7

6

5

4

3

2

1

0

Address : 000004^H

P47

P46

P45

P44

P43

P42

P41

P40

PDR5

bit

15

14

13

12

11

10

9

8

Address : 000005^H

P57

P56

P55

P54

P53

P52

P51

P50

PDR6

bit

7

6

5

4

3

2

1

0

Address : 000006^H

P67

P66

P65

P64

P63

P62

P61

P60

PDR7

bit

15

14

13

12

11

10

9

8

Address : 000007^H

⎯

P76

P75

P74

P73

P72

P71

P70

PDR8

bit

7

6

5

4

3

2

1

0

Address : 000008^H

⎯

P84

P83

P82

P81

P80

PDR9

bit

15

14

13

12

11

10

9

8

Address : 000009^H

⎯

P91

P90

- : Unused

* : R/W access to I/O ports is a bit different in behavior from R/W access to memory as follows

• Input mode

When reading : Read the corresponding pin level.

When writing : Write into the latch for the output.

• Output mode

When reading : Read the value of the data register latch.

When writing : Write into the corresponding pin.

DS07-13733-6E

25

MB90800 Series

(2) Port direction register

DDR0

bit

Initial Value Access

7

6

5

4

3

2

1

0

Address : 000010^H

00000000B

- 0000000B

- - - 00000B

- - - - - - 00B

R/W

D07

D06

D05

D04

D03

D02

D01

D00

DDR1

bit

15

14

13

12

11

10

9

8

Address : 000011^H

D17

D16

D15

D14

D13

D12

D11

D10

DDR2

bit

7

6

5

4

3

2

1

0

Address : 000012^H

D27

D26

D25

D24

D23

D22

D21

D20

DDR3

bit

15

14

13

12

11

10

9

8

Address : 000013^H

D37

D36

D35

D34

D33

D32

D31

D30

DDR4

bit

7

6

5

4

3

2

1

0

Address : 000014^H

D47

D46

D45

D44

D43

D42

D41

D40

DDR5

bit

15

14

13

12

11

10

9

8

Address : 000015^H

D57

D56

D55

D54

D53

D52

D51

D50

DDR6

bit

7

6

5

4

3

2

1

0

Address : 000016^H

D67

D66

D65

D64

D63

D62

D61

D60

DDR7

bit

15

14

13

12

11

10

9

8

Address : 000017^H

D75

D74

D73

D72

D71

D70

⎯

D76

DDR8

bit

7

6

5

4

3

2

1

0

Address : 000018^H

⎯

D84

D83

D82

D81

D80

DDR9

bit

15

14

13

12

11

10

9

8

Address : 000019^H

⎯

D91

D90

- : Unused

When each terminal functions as a port, each correspondent pin are controlled by the port direction register to

following;

0 : Input mode

1 : Output mode This bit becomes “0” after a reset.

Note : When accessing this register by using the instruction of the read modify write system (instructions such as

bit set) is mode, the bit targeted by an instruction becomes the defined value. However, the content of the

output register set to input with the other changes to input value of the pin at that time. Therefore, be sure

to write an expected value into PDR firstly, and then set DDR and finally change to the output when changing

the input pin to the output pin is made.

26

DS07-13733-6E

MB90800 Series

(3) Analog Input Enable register

ADER0

bit

Initial Value Access

7

6

5

4

3

2

1

0

Address : 00001E^H

11111111B

R/W

ADE3

ADE2

ADE1

ADE0

ADE7

ADE6

ADE5

ADE4

ADER1

bit

15

14

13

12

11

10

9

8

Address : 00001F^H

- : Unused

- - - -1111B

R/W

⎯

ADE11 ADE10 ADE9

ADE8

Each pin of port 6 is controlled by the analog input enable register as follow.

0 : Port input/output mode.

1 : Analog input mode.This bit becomes “1” after a reset.

DS07-13733-6E

27

MB90800 Series

2. UART

UART is a serial I/O port for asynchronous (start-stop synchronization) communication or CLK synchronous

communications.

• With full-duplex double buffer

• Clock asynchronous (start-stop synchronization) , CLK synchronous communications (no start-bit/stop-bit)

can be used.

• Supports multi-processor mode

• Built-in dedicated baud rate generator

Asynchronous

: 120192/60096/30048/15024/781.25 K/390.625 kbps

CLK synchronous : 25 M/12.5 M/6.25 M/3.125 M/1.5627 M/781.25 kbps

• Variable baud rate can be set by an external clock.

• 7 bits data length (only asynchronous normal mode) /8 bits length

• Master/slave type communication function (at multiprocessor mode) : The communication between one (mas-

ter) to n (slave) can be operating.

• Error detection functions(parity, framing, overrun)

• Transmission signal format is NRZ

28

DS07-13733-6E

MB90800 Series

(1) Register list

bit 15

8

7

0

CDCR

SCR

SSR

8-bit

⎯

SMR

SIDR (R)/SODR (W)

8-bit

Serial mode register (SMR0, SMR1)

bit

Initial Value

00000 - 00B

Read/Write

7

6

5

4

3

2

1

0

000020^H

000028H

MD1

MD0

CS2

CS1

CS0

⎯

SCKE

SOE

Address :

R/W

⎯

R/W

Serial control register(SCR0, SCR1)

bit

Initial Value

00000100B

Read/Write

15

14

P

13

12

11

10

9

8

000021^H

000029H

Address :

PEN

SBL

CL

A/D

REC

RXE

TXE

R/W

W

R/W

Serial input/output register (SIDR0, SIDR1/SODR0, SODR1)

bit

Initial Value

XXXXXXXXB

Read/Write

7

6

5

4

3

2

1

0

000022^H

00002AH

Address :

D7

D6

D5

D4

D3

D2

D1

D0

R/W

12

R/W

11

R/W

Serial Data Register (SSR0, SSR1)

bit

Initial Value

00001000B

Read/Write

15

14

13

10

9

8

000023^H

00002BH

Address :

PE

R

ORE

FRE

RDRF TDRE

BDS

RIE

TIE

R

R/W

Communication prescaler control register (CDCR0, CDCR1)

bit

Initial Value

00 - - 0000B

15

14

13

12

11

10

9

8

000025^H

00002DH

Address :

Reserved

MD

URST

⎯

DIV2

DIV1

DIV0

Read/Write

R/W

⎯

R/W

- : Unused

DS07-13733-6E

29

MB90800 Series

(2) Block Diagram

Control signal

RXinterrupt

(to CPU)

Special-purpose

baud-rate generator

Clock

Transmission clock

TX interrupt

(to CPU)

selection

circuit

16-bit reload timer 0

SC Pin

Reception clock

Receptioncontrol

Transmission

control circuit

circuit

SI Pin

Start bit

detection circuit

Transmission

start circuit

Reception bit

counter

Transmission bit

counter

Transmission

parity counter

Reception

parity counter

SO Pin

Receive status

decision circuit

RX shifter

TX shifter

Reception

control

circuit

Reception error

occurrence signal

for EI²OS (to CPU)

Start

transmission

SIDR

SODR

F²MC-16LX bus

MD1

MD0

CS2

PEN

PE

ORE

P

SBL

CL

FRE

RDRF

TDRE

BDS

RIE

SMR

Register

SCR

Register

SSR

Register

CS1

CS0

A/D

REC

RXE

TXE

SCKE

SOE

TIE

Control signal

30

DS07-13733-6E

MB90800 Series

3. I²C Interface

I²C interface is the serial input/output port that support Inter IC BUS and functions as the master/slave device

on the I²C bus. MB90800 series have 1 channel of the built-in I²C interface.

It has the features of I²C interface below.

• Master/slave sending and receiving

• Arbitration function

• Clock synchronization function

• Slave address and general call address detection function

• Detecting transmitting direction function

• Repeat generating and detecting function of the start conditions

• Bus error detection function

• The forwarding rate can be supported to 100 kbps.

(1) Register list

I²C status register (IBSR)

bit

Address :00006A^H

Initial Value

00000000B

7

6

5

4

3

2

1

0

BB

RSC

AL

LRB

TRX

AAS

GCA

FBT

R

Read/Write

I²C control register (IBCR)

bit

Initial Value

00000000B

15

14

13

12

11

10

9

8

Address :00006B^H

BER

R/W

BEIE

R/W

SCC

R/W

MSS

R/W

ACK

R/W

GCAA

R/W

INTE

R/W

INT

R/W

Read/Write

I²C clock control register (ICCR)

bit

Initial Value

XX0XXXXXB

7

6

5

4

3

2

1

0

Address :00006C^H

⎯

EN

R/W

CS4

R/W

CS3

R/W

CS2

R/W

CS1

R/W

CS0

R/W

Read/Write

I²C data register(IDAR)

bit

15

Initial Value

XXXXXXXXB

14

13

12

11

10

9

8

Address :00006E^H

D7

D6

D5

D4

D3

D2

D1

D0

R/W

Read/Write

I²C address register (IADR)

bit

Initial Value

XXXXXXXXB

7

6

5

4

3

2

1

0

Address :00006D^H

⎯

A6

A5

A4

A3

A2

A1

A0

R/W

Read/Write

- : Unused

DS07-13733-6E

31

MB90800 Series

(2) Block Diagram

ICCR

EN

I²C Enable

Clock divide 1

Machine clock

ICCR

CS4

5

6

7

8

Clock selector 1

Clock divide 2

CS3

CS2

CS1

CS0

Sync

2

4 8

16

32 64 128 256

Generating shift clock

Clock selector 2

Change timing of

shift clock edge

IBSR

BB

Bus busy

Repeat start

Last Bit

RSC

LRB

TRX

FBT

AL

Start • stop Condition detection

Transfer/

reception

Error

First Byte

Arbitration lost detection

IBCR

BER

SCL

SDA

BEIE

INTE

INT

IRQ

Interrupt request

End

IBCR

SCC

Start

Master

MSS

ACK

Start • stop Condition detection

ACK enable

GC-ACK enable

GCAA

IDAR

IBSR

AAS

Slave

Global call

Slave address

compare

GCA

IADR

32

DS07-13733-6E

MB90800 Series

4. Extended I/O serial interface

The extended I/O serial interface is a serial I/O interface that can transfer data through the adoption of 8-bit ×

2 channels configured clock synchronization scheme. The extended I/O serial interface also has two alternatives

in data transfer called LSB first and MSB first.

The serial I/O interface operates in two modes:

• Internal shift clock mode : Transfer data in sync with the internal clock.

• External shift clock mode : Transfers data in sync with the clock input through an external pin (SC) . In this

mode, transfer operation performed by the CPU instruction is also available by

operating the general-use port sharing an external pin (SC) .

(1) Register list

Serial mode control status register (SMCS0, SMCS1)

bit

000060^H

000064H

Initial Value

00000010B

Read/Write

15

14

13

12

11

10

9

8

Address :

SMD2 SMD1 SMD0

SIE

SIR

BUSY

STOP

STRT

R/W

R

R/W

bit

7

6

5

4

3

2

1

0

000061^H

000065H

Address :

----0000B

⎯

MODE

BDS

SOE

SCOE

R/W

⎯

Read/Write

Serial Data Register (SDR0, SDR1)

bit

7

6

5

4

3

2

1

0

000062^H

000066H

Address :

XXXXXXXXB

Read/Write

D7

D6

D5

D4

D3

D2

D1

D0

R/W

Communication Prescaler control register (SDCR0, SDCR1)

bit

15

14

13

12

11

10

9

8

000063^H

000067H

Reserved

Address :

0---0000B

MD

⎯

DIV2

DIV1

DIV0

R/W

⎯

R/W

Read/Write

- : Unused

DS07-13733-6E

33

MB90800 Series

(2) Block Diagram

Internal data bus

Initial Value

(MSB fast) D0 to D7

(LSB fast) D7 to D0

Transfer direction selection

SI2, SI3

Read

Write

SDR (Serial Data Register)

SO2, SO3

SC2, SC3

Shift clock counter

Control circuit

Internal clock

2

1

0

SMD2 SMD1 SMD0 SIE

SIR BUSY STOP STRT MODE BDS SOE SCOE

Interrupt

request

Internal data bus

34

DS07-13733-6E

MB90800 Series

5. 8/10-bit A/D converter

The feature of 8/10-bit A/D converter is shown as follows.

• conversion time : 3.1 μs minimum per 1 channel

(78 machine cycle/at machine clock 25 MHz/including the sampling time)

• Sampling time : 2.0 μs minimum per 1channel

(50 machine cycle/at machine clock 25 MHz)

• Uses RC-type successive approximation conversion method with a sample & hold circuit

• 8-bit resolution or 10-bit resolution can be select.

• 12 channel program-selectable analog inputs.

Single conversion mode

Scan conversion mode

: Convert specified 1 channel

: Continuous plural channels (maximum 12 channels can be programmed) are

converted.

Continuous conversion mode : Selected channel converted continuously.

Stop conversion time : Perform conversion for one channel, then pause it to wait for the next activation

trigger (synchronizes the conversion start timing)

• EI²OS can be activated by outputting the interrupt request when the A/D conversion completes.

• If the A/D conversion is performed under the condition of the interrupt enable, the converting data will be

protected.

• Selectable conversion activation trigger : Software, or reload timer (rising edge)

(1) Register list

ADCS1, ADCS0 (Control status register)

ADCS0

bit

Initial Value

00 - - - - - - B

7

6

5

4

3

2

1

0

Address : 000034^H

MD1

MD0

⎯

R/W

⎯

Read/Write

ADCS1

bit

Initial Value

00000000B

15

14

13

12

11

10

9

8

Address : 000035^H

BUSY

INT

INTE

PAUS

STS1

STS0

STRT Reserved

R/W

W

R/W

Read/Write

ADCR1, ADCR0 (Data register)

ADCR0

bit

Initial Value

7

6

5

4

3

2

1

0

Address : 000036^H

XXXXXXXXB

D7

D6

D5

D4

D3

D2

D1

D0

R

Read/Write

ADCR1

bit

Initial Value

00101 - XXB

15

14

13

12

11

10

9

8

Address : 000037^H

S10

ST1

ST0

CT1

CT0

⎯

D9

D8

W

⎯

R

Read/Write

- : Unused

DS07-13733-6E

35

MB90800 Series

(2) Block Diagram

AVCC

AVR

MPX

AVSS

AN0

AN1

AN2

AN3

D/A converter

AN4

Input

circuit

AN5

AN6

Sequential compare

register

AN7

AN8

AN9

Comparator

AN10

AN11

Sample & hold circuit

Data register

ADCR0, ADCR1

Decoder

A/D conversion channel set

register

ADCS0 A/D control status

register 0 (lower)

ADCS1 A/D control status

register 1 (upper)

Timer start-up

ADCS0, ADCS1,

ADMR

16-bit Reload Timer

Operation clock

φ

Prescaler

36

DS07-13733-6E

MB90800 Series

6. 16 bits PPG

The PPG timer consists of the following:

• Prescaler

• 16-bit down-counter: 1

• 16-bit data register with a cycle setting buffer

• 16-bit compare register with a duty setting buffer

• Pin control unit

The PPG timer can output pulses synchronized to the software trigger.

The output pulse can be changed to any cycle and duty freely by updating the PCSRL, PCSRH/PDUTL, PDUTH

registers.

• PWM function

The PPG timer can output pulses programmably by updating the PCSR and PDUT registers described above

in synchronization to the trigger.

Can also be used as a D/A converter by an external circuit.

• Single shot function

By detecting an edge of the trigger input, a single pulse can be output.

• 16-bit down counter

The counter operation clock comes from eight kinds optional. There are eight kinds of internal clocks.

(φ, φ2, φ4, φ8, φ16, φ32, φ64, φ128) φ : machine clock

The counter can be initialized to “FFFF^H” at a reset or counter borrow.

• Interrupt request

The PPG timer generates an interrupt request when :

• Timer start-up

• Counter borrow occurrence (cycle match)

• Duty match occurrence

DS07-13733-6E

37

MB90800 Series

(1) Register list

PCNTH (PCNTH0/PCNTH1 PPG Control Status register)

bit

15

CNTE STGR MDSE RTRG

R/W R/W R/W R/W

14

13

12

11

10

9

8

000077^H

00007FH

Initial Value

0000000-^B

Read/Write

CKS2

CKS1

CKS0 PGMS

R/W

PCNTL (PCNTL0/PCNTL1 PPG Control Status register)

bit

7

6

5

4

3

2

1

0

000076^H

00007EH

Initial Value

- - 000000^B

Read/Write

⎯

IREN

IRQF

IRS1

IRS0

POEN

OSEL

⎯

R/W

PDCRH (PDCRH0/PDCRH1 PPG Down Counter Register)

bit

15

14

13

12

11

10

9

8

000071^H

000079H

Initial Value

11111111^B

Read/Write

DC15

DC14

DC13

DC12

DC11

DC10

DC09

DC08

R

PDCRL (PDCRL0/PDCRL1 PPG Down Counter Register)

bit

7

6

5

4

3

2

1

0

000070^H

000078H

Initial Value

11111111^B

Read/Write

DC07

DC06

DC05

DC04

DC03

DC02

DC01

DC00

R

PCSRH (PCSRH0/PCSRH1 PPG cycle set register)

bit

15

14

13

12

11

10

9

8

000073^H

00007BH

Initial Value

XXXXXXXX^B

Read/Write

CS15

CS14

CS13

CS12

CS11

CS10

CS09

CS08

W

PCSRL (PCSRL0/PCSRL1 PPG cycle set register)

bit

7

6

5

4

3

2

1

0

000072^H

00007AH

Initial Value

XXXXXXXX^B

Read/Write

CS07

CS06

CS05

CS04

CS03

CS02

CS01

CS00

W

PDUTH (PDUTH0/PDUTH1 PPG duty set register)

bit

15

14

13

12

11

10

9

8

000075^H

00007DH

Initial Value

XXXXXXXX^B

Read/Write

DU15

DU14

DU13

DU12

DU11

DU10

DU09

DU08

W

PDUTL (PDUTL0/PDUTL1 PPG duty set register)

bit

7

6

5

4

3

2

1

0

000074^H

00007CH

Initial Value

XXXXXXXX^B

Read/Write

DU07

DU06

DU05

DU04

DU03

DU02

DU01

DU00

W

- : Unused

38

DS07-13733-6E

MB90800 Series

(2) Block Diagram

• 16-bit PPG ch.0/ch.1 block diagram

Prescaler

1/1

1/2

PCSR

PDUT

1/4

1/8

1/16

Load

Clock

1/32

1/64

CMP

PCNT

16-bit down counter

1/128

Start Borrow

PPG mask

Machine clock φ

S

R

Q

PPG output

Reverse bit

Enable

Interrupt

select

Interrupt

Soft trigger

DS07-13733-6E

39

MB90800 Series

7. Delay interrupt generator module

The delayed interrupt generation module outputs an interrupt request for task switching. The hardware interrupt

request can be generated by software.

(1) Register list

Delayed Interrupt/release register(DIRR)

DIRR

bit

Initial Value

15

⎯

14

⎯

13

⎯

12

⎯

11

⎯

10

⎯

9

8

Address : 00009F^H

- - - - - - - 0B

⎯

R0

Read/Write

R/W

- : Unused

(2) Block diagram

F²MC-16LX bus

Delay interruption factor generation/

release decoder

Factor latch

40

DS07-13733-6E

MB90800 Series

8. DTP/External interrupt

DTP (Data Transfer Peripheral)/External interrupt circuit detects the interrupt request input from the external

interrupt input terminal, and outputs the interrupt request.

(1) Register list

Interrupt/DTP enable register (ENIR)

ENIR

bit

Initial Value

7

6

⎯

5

4

3

2

1

0

Address : 000030^H

- - - - 0000B

⎯

EN3

R/W

EN2

R/W

EN1

R/W

EN0

R/W

Read/Write

Interrupt/DTP source register (EIRR)

EIRR

bit

Initial Value

15

⎯

14

⎯

13

⎯

12

11

10

9

8

Address : 000031^H

- - - - XXXXB

⎯

ER3

R/W

ER2

R/W

ER1

R/W

ER0

R/W

Read/Write

Request level setting register (ELVR)

ELVR

bit

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 000032^H

LB3

R/W

LA3

R/W

LB2

R/W

LA2

R/W

LB1

R/W

LA1

R/W

LB0

R/W

LA0

R/W

Read/Write

- : Unused

(2) Block diagram

F²MC-16LX bus

4

Interrupt/DTP enable register

4

8

4

Edge detection circuit

Source F/F

Request input

Gate

Interrupt/DTP source register

Request level setting register

DS07-13733-6E

41

MB90800 Series

9. 16-bit input/output timer

The 16-bit I/O timer consists of one 16-bit free-run timer, two output compare and two input capture. This function

enables six independent waveforms to be output based on the 16-bit free-run timer, and input pulse widths and

external clock frequencies to be measured.

• Register list

• 16-bit free-run timer

bit 15

00003BH/00003AH

0

Compare clear register

CPCLR

TCDT

Timer counter data register

00003DH/00003CH

00003FH/00003EH

Timer counter

control/status register

TCCSH

TCCSL

• 16-bit Output Compare

bit

15

0

00004A

00004C

H

/00004B

/00004D

H

,

Compare register

OCCP0, OCCP1

H

Control status register

00004F

H

/00004E

H

OCSH

OCSL

• 16-bit Input Capture

bit 15

0

000044

000046

H

/000045

/000047

H

,

Input capture data register

Control status register

IPCP0, IPCP1

H

000048

H

ICS01

42

DS07-13733-6E

MB90800 Series

• Block diagram

Control logic

Interrupt

16-bit free-run timer

To each

block

16-bit timer

Clear

Output

compare 0

OCU0

OCU1

Compare register 0

Compare register 1

TQ

Output

compare 1

Input capture 0

Input capture 1

Capture register 0

Capture register 1

Edge select

IC0

IC1

DS07-13733-6E

43

MB90800 Series

(1) 16-bit free-run timer

The 16-bit free-run timer consists of a 16-bit up-down counter and control status register.

Counter value of 16-bit free-run timer is available as base timer for input capture and output compare.

• Clock for the counter operation can be selected from eight types.

• The counter overflow interruption can be generated.

• Setting the mode enables initialization of the counter through compare-match operation with the value of the

compare clear register in the output compare and that of the free-run timer counter.

• Register list

Compare clear register (CPCLR)

bit

Initial Value

15

14

13

12

11

10

9

8

00003B^H

XXXXXXXXB

CL15

R/W

CL14

R/W

CL13

R/W

CL12

R/W

CL11

R/W

CL10

R/W

CL09

R/W

CL08

R/W

Read/Write

bit

Initial Value

7

6

5

4

3

2

1

0

00003A^H

XXXXXXXXB

CL07

R/W

CL06

R/W

CL05

R/W

CL04

R/W

CL03

R/W

CL02

R/W

CL01

R/W

CL00

R/W

Read/Write

Timer counter data register (TCDT)

bit

Initial Value

00000000B

15

14

13

12

11

10

9

8

00003D^H

T15

R/W

T14

T13

R/W

T12

R/W

T11

R/W

T10

R/W

T09

R/W

T08

R/W

Read/Write

R/W

bit

Initial Value

00000000B

7

6

5

4

3

2

1

0

00003C^H

T07

R/W

T06

R/W

T05

R/W

T04

R/W

T03

R/W

T02

R/W

T01

R/W

T00

R/W

Read/Write

Timer counter control/status register (TCCS)

bit

Initial Value

0--00000B

15

14

⎯

13

⎯

12

11

10

9

8

00003F^H

ECKE

R/W

MSI2

R/W

MSI1

R/W

MSI0

R/W

ICLR

R/W

ICRE

R/W

Read/Write

bit

00003E^H

Initial Value

00000000B

7

6

5

4

3

2

1

0

IVF

R/W

IVFE

R/W

STOP MODE SCLR

R/W R/W R/W

CLK2

R/W

CLK1

R/W

CLK0

R/W

Read/Write

- : Unused

44

DS07-13733-6E

MB90800 Series

• Block diagram

φ

Interrupt request

Divider

IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0

Clock

16-bit free-run timer

Count value output T15 to T00

16-bit compare clear register

MSI2 to MSI0

Compare circuit

ICLR ICRE

Interrupt request

DS07-13733-6E

45

MB90800 Series

(2) Output compare

The output compare consists of 16-bit compare registers, compare output pin part and a control register. It can

reverse the output level for the pin and at the same time, generate an interrupt when the 16-bit free-run timer

value matches a value set in one of the 16-bit compare registers of this module.

• It has a total of six compare registers that can operate independently. In addition, the output can be set to be

controlled by using two compare registers.

• An interrupt can be set by a comparing match.

• Register list

Compare register (OCCP0, OCCP1)

bit

Initial Value

00000000B

15

14

13

12

11

10

9

8

00004B^H

00004DH

OP15

R/W

OP14

R/W

OP13

R/W

OP12

R/W

OP11

R/W

OP10

R/W

OP09

R/W

OP08

R/W

Read/Write

bit

Initial Value

00000000B

7

6

5

4

3

2

1

0

00004A^H

00004CH

OP07

R/W

OP06

R/W

OP05

R/W

OP04

R/W

OP03

R/W

OP02

R/W

OP01

R/W

C00

R/W

Read/Write

Control register (OCSH)

bit

Initial Value

---00000B

15

⎯

14

⎯

13

⎯

12

11

10

9

8

00004F^H

CMOD OTE1

OTE0

R/W

OTD1

R/W

OTD0

R/W

Read/Write

R/W

Control register (OCSL)

bit

Initial Value

0000--00B

7

6

5

4

3

2

1

0

00004E^H

IOP1

R/W

IOP0

R/W

IOE1

R/W

IOE0

R/W

⎯

CST1

R/W

CST0

R/W

Read/Write

- : Unused

46

DS07-13733-6E

MB90800 Series

• Block diagram

16-bit timer counter value (T15 to T00)

Compare control

TQ

CMOD

TQ

OTE0

Compare register 0

16-bit timer counter value (T15 to T00)

Compare control

OTE1

Compare register 1

ICP1 ICP0 ICE0 ICE0

Interrupt

#29

Control logic

#29

Each control blocks

DS07-13733-6E

47

MB90800 Series

(3) Input capture

The input capture consists of input capture and control registers. Each input capture has its corresponding

external input pin.

This module has a function that detects a rising edge, falling edge or both edges and holds a value of the 16-

bit free-run timer in a register at the time of detection. It can also generate an interrupt when detecting an edge.

• The detection edge of an external input can be selected from among three types. Rising edge/falling edge/

both edges.

• It can generate an interrupt when it detects the valid edge of the external input.

• Register list

Input capture data register (IPCP0, IPCP1)

Initial Value

bit

15

CP15

R

14

CP14

R

13

CP13

R

12

CP12

R

11

CP11

R

10

CP10

R

9

CP09

R

8

CP08

R

000045^H

000047H

XXXXXXXX^B

Read/Write

Initial Value

bit

7

CP07

R

6

CP06

R

5

CP05

R

4

3

CP03

R

2

CP02

R

1

CP01

R

0

CP00

R

000044^H

000046H

XXXXXXXX^B

CP04

R

Read/Write

Control status register (ICS01)

Initial Value

00000000^B

bit

7

6

5

4

3

2

1

0

000048^H

ICP1

R/W

ICP0

R/W

ICE1

R/W

ICE0

R/W

EG11

R/W

EG10

R/W

EG01

R/W

EG00

R/W

Read/Write

48

DS07-13733-6E

MB90800 Series

• Block diagram

IC0

Capture data register 0

Edge detection

16-bit timer counter value (T15 to T00)

Capture data register 1

EG11 EG10 EG01 EG00

Edge detection

IC1

ICP1 ICP0 ICE1 ICE0

Interrupt #25

DS07-13733-6E

49

MB90800 Series

10. 16-bit reload timer

The 16-bit reload timer provides two functions either one which can be selected, the internal clock mode that

performs the count down by synchronizing with 3-type internal clocks and the event count mode that performs

the count down by detecting the arbitration. This timer defines an underflow as a transition of the count value

from 0000^Hto FFFFH. Therefore, when the equation (counted value = reload register setting value+1) holds, an

underflow occurs. Either mode can be selected for the count operation from the reload mode which repeats the

count by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the

count at the underflow occurrence. The interrupt can be generated at the counter underflow occurrence so as

to correspond to the DTC.

(1) Register list

• TMCSR Timer control status register

Timer control status register (upper) (TMCSR0H to TMCSR2H)

bit

Initial Value

- - - - 0000B

15

14

13

12

11

10

9

8

000051^H

⎯

CSL1

CSL0

MOD2 MOD1

000055H

000059H

Read/Write

⎯

R/W

Timer control status register (lower) (TMCSR0L to TMCSR2L)

bit

Initial Value

00000000B

7

6

5

4

3

2

1

0

000050^H

000054H

000058H

MOD0 OUTE OUTL

R/W R/W R/W

RELD

INTE

UF

CNTE

TRG

Read/Write

R/W

• 16-bit timer register/16-bit reload register TMR0 to TMR2/TMRLR0 to TMRLR2 (upper)

bit

Initial Value

15

14

13

12

11

10

9

8

XXXXXXXXB

000053^H

D15

D14

D13

D12

D11

D10

D9

D8

000057H

00005BH

R/W

Read/Write

TMR0 to TMR2/TMRLR0 to TMRLR2 (lower)

bit

Initial Value

7

6

5

4

3

2

1

0

XXXXXXXXB

000052^H

000056H

00005AH

D7

D6

D5

D4

D3

D2

D1

D0

R/W

Read/Write

- : Unused

50

DS07-13733-6E

MB90800 Series

(2) Block diagram

Internal data bus

TMRLR

16-bit reload register

Reload signal

TMR

Reload control

circuit

16-bit timer register

(down counter)

UF

CLK

Count clock generation circuit

Gate

input

Wait signal

3

Valid clock

identification circuit

Machine

clock φ

Prescaler

Clear

CLK

Output signal

generation circuit

Re-

verse

Clock

selector

Inputcontrol

Output signal

generation circuit

circuit

EN

External clock

Operation

control circuit

OUTL

RELD

3

2

Select

function

Select signal

OUTE

Timer control status register (TMCSR)

DS07-13733-6E

51

MB90800 Series

11. Watch timer

The watch timer is a 15-bit timer using the subclock. It can generate the interrupt request for each interval time.

The watch timer can also be used as the clock source of the watchdog timer by setting so.

(1) Register list

Watch timer control register (WTC)

bit

Initial Value

1X011000B

7

6

5

4

3

2

1

0

0000AA^H

WDCS

SCE

WTIE

WTOF

WTR

WTC2 WTC1 WTC0

R/W R/W R/W

R/W

R

R/W

Read/Write

(2) Block diagram

Watch timer control register (WTC)

WDCS

SCE

WTIE

WTOF

WTR

WTC2

WTC1 WTC0

Clear

2⁸

2⁹

Sub clock

Interrupt

generation

circuit

Interval

selector

2¹⁰

2¹¹

2¹²

2¹³

2¹⁴

Watch timer

interrupt

Watch counter

2¹⁰2¹³2¹⁴2¹⁵

To watchdog timer

52

DS07-13733-6E

MB90800 Series

12. Watchdog timer

The watchdog timer is a timer counter provided for preventing program malfunction. The watchdog timer is a 2-

bit counter operating with an output of the timebase timer or watch timer as count clock and resets the CPU

when the counter is not cleared within the interval time.

(1) Register list

Watchdog timer control register (WDTC)

bit

Initial Value

XXXXX111B

7

6

5

4

3

2

1

0

0000A8^H

PONR

⎯

WRST

ERST

SRST

WTE

WT1

WT0

R

⎯

R

W

Read/Write

− : Unused

(2) Block diagram

Watchdog timer control register (WDTC)

PONR

WRST ERST SRST WTE WT1 WT0

WDCS bit of watch timer

control register (WTC)

2

SCM bit of clock selection

register (CKSCR)

Watch mode start

Time-base timer mode start

Sleep mode start

Hold status start

CLR and start-up

Watchdog timer

CLR

Counter

clear control

circuit

Count

clock

selector

Watchdog reset

generation

circuit

2-bit

counter

Internal

reset

generation

circuit

Stop mode start

CLR

4

Clear

Time base counter

× 2¹× 2²

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

Dividing HCLK by 2

SCLK

× 2¹× 2²

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

HCLK: Oscillation clock

SCLK: Sub clock

DS07-13733-6E

53

MB90800 Series

13. Time-base timer

The time-base timer has a function that enables a selection of four interval times using 18-bit free-run counter

(time-base counter) with synchronizing to the internal count clock (two division of original oscillation). Further-

more, the function of timer output of oscillation stabilization wait or function supplying operation clocks for

watchdog timer are provided.

(1) Register list

Time-base timer control register (TBTC)

bit

Initial Value

1 - - 00100B

15

14

13

12

11

10

9

8

0000A9^H

Reserved

⎯

TBIE

TBOF

TBR

TBC1

TBC0

R/W

⎯

R/W

W

R/W

Read/Write

- : Unused

(2) Block diagram

To PPG timer

Time-base timer counter

To watchdog timer

Dividing HCLK by 2

× 2¹× 2²

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

OF

Power-on reset

Stop mode start

To clock controller

Oscillationstabilizing

Wait time selector

Counter

clear

control

circuit

Hold status start

CKSCR : MCS = 1→0*¹

CKSCR : SCS = 0→1*²

Interval timer selector

TBOF clear

TBOF set

Time-base timer control register (TBTC)

Time-base timer interrupt signal

Reserved

⎯

TBIE TBOF TBR TBC1 TBC0

⎯

OF

: Unused

: Overflow

HCLK : Oscillation clock

*1

*2

: The machine clock is switched from main/sub clock to PLL clock.

: The machine clock is switched from sub clock to main clock.

54

DS07-13733-6E

MB90800 Series

14. Clock generator

TheclockgeneratorcontrolsoperationoftheinternalclockwhichistheoperationclockfortheCPUandperipheral

devices. This internal clock is used as machine clock and its one cycle as machine cycle. In addition, the clock

generated by original oscillation is used as oscillation clock and that by internal PLL oscillation as PLL clock.

(1) Register list

Clock selection register (CKSCR)

bit

Initial Value

11111100B

15

14

13

12

11

10

9

8

0000A1^H

SCM

MCM

WS1

WS0

SCS

MCS

CS1

CS0

Read/Write

R

R/W

DS07-13733-6E

55

MB90800 Series

(2) Block diagram

Standby control circuit

Low power consumption mode control register (LPMCR)

Reserved

STP SLP SPL RST TMD CG1 CG0

Pin High-Z

control circuit

Pin High-Z control

Internal reset

generation circuit

RST

Internal reset

CPU intermittent

operation selector

Intermittent cycle selection

CPU clock

control circuit

Stop, sleep signal

Stop signal

CPU clock

Standby control

circuit

Release

interrupting

Peripheral clock

control circuit

Peripheral clock

Machine clock

Oscillation stabilization wait

Clock generation block

Clock

selector

Oscillation

stabilization

wait time

2

SCLK

Dividing

by 4

selector

2

PLL multiplying

circuit

SCM MCM WS1 WS0 SCS MCS CS1 CS0

Sub clock

generation

circuit

Clock selection register (CKSCR)

System

clock

generation

circuit

X0A

X1A

Dividing

by 2

Dividing

by 2

Dividing

by 4

Dividing

by 2

Dividing

by 4

Dividing

by 4

by

1024

HCLK MCLK

X0

X1

Time-base timer

To watchdog timer

HCLK : Oscillation clock

MCLK : Main clock

SCLK : Sub clock

56

DS07-13733-6E

MB90800 Series

(3) Clock supply map

Clock generation circuit

Timer clock divider

Watchdog timer

X0

X1

Watch timer

Oscillation

circuit

Internal resources

Selector

X0A

X1A

Oscillation

circuit

LCD controller

16-bit Reload Timer

8/10-bit A/D converter

Serial I/O

Time-base timer

Free-run timer

Input capture

Output compare

1

2

3

4

PLL multiplying circuit

PCLK

CPU (F²MC-16LX)

2 division circuit

Selector

HCLK

MCLK

ROM/RAM (memory)

2 division circuit

SCLK

HCLK : Oscillation clock

MCLK : Main clock

PCLK : PLL clock

SCLK : Sub clock

DS07-13733-6E

57

MB90800 Series

15. Low power consumption mode

The low-power consumption mode has the following CPU operation modes by selecting the operation clock and

operating the control of the clock.

• Clock mode

(PLL clock mode, main clock mode and sub clock mode)

• CPU intermittent operation mode

(PLL clock intermittent operation mode, main clock intermittent operation mode and subclock intermittent

operation mode)

• Standby mode

(Sleep mode, time base timer mode, stop mode and watch mode)

(1) Register list

Low power consumption mode control register (LPMCR)

bit

Initial Value

00011000B

7

6

5

4

3

2

1

0

0000A0^H

Reserved

STP

SLP

SPL

RST

TMD

CG1

CG0

Read/Write

W

R/W

W

R/W

58

DS07-13733-6E

MB90800 Series

(2) Block diagram

Standby control circuit

Low power consumption mode control register (LPMCR)

Reserved

STP SLP SPL RST TMD CG1 CG0

Pin High-Z

control circuit

Pin High-Z control

Internal reset

RST

generation

Internal reset

circuit

CPU intermittent

operation selector

Intermittent cycle selection

CPU clock

control circuit

Standby control

Stop, sleep signal

Stop signal

Release of

interrupt

circuit

Peripheral

Peripheralclock

clock control

Machine clock

Release of oscillation stabilization wait

Clock generation block

Clock

selector

Oscillation

stabilization

wait time

2

SCLK

selector

Dividing

by 4

2

PLL multiplying

circuit

SCM MCM WS1 WS0 SCS MCS CS1 CS0

Sub

clock

Clock selection register (CKSCR)

generation

circuit

System

clock

generation

circuit

X0A

X1A

Dividing

by 1024

Dividing

by 4

Dividing

by 2

Dividing

by 2

Dividing

by 2

Dividing

by 4

Dividing

by 4

HCLK MCLK

Time-base timer

X0

X1

To watchdog timer

HCLK : Oscillation clock

MCLK : Main clock

SCLK : Sub clock

DS07-13733-6E

59

MB90800 Series

(3) Figure of status transition

External reset, watchdog timer reset, software reset

Power supply

Power-on reset

Reset

SCS = 0

SCS = 1

MCS = 0

MCS = 1

SCS = 0

SCS = 1

Endofoscillation

stabilization wait

PLL clock mode

Main clock mode

Sub clock mode

SLP = 1

Interrupt

Main sleep mode

Interrupt

PLL sleep mode

Sub sleep mode

TMD = 0

Interrupt

Time-base

timer mode

Time-base

timer mode

Watch mode

STP = 1

Main stop mode

STP = 1

PLL stop mode

STP = 1

Sub stop mode

End of oscillation

stabilization wait

End of oscillation

stabilization wait

End of oscillation

stabilization wait

Interrupt

PLL clock Oscillation

stabilization wait

Sub clock Oscillation

stabilization wait

Main clock Oscillation

stabilization wait

60

DS07-13733-6E

MB90800 Series

16. Timer clock output

The timer clock output circuit divides the oscillation clock by the time-base timer and generates and outputs the

set division clock. Selectable from 32/64/128/256 division of the oscillation clock.

The timer clock output circuit is inactive in reset or stop mode. It is active in normal run, sleep, or pseudo-timer

mode.

Pseudo

clock

PLL_Run

Main_Run

Sleep

STOP

Reset

Operation status

×

Note : When the time-base timer is cleared while using the timer clock output circuit, the clock is not correctly output.

For detail of the time-base timer’s clear condition, see the section of time-base timer in the MB90800

Hardware Manual.

(1) Register list

Watch clock output control register (TMCS)

bit

Initial Value

XXXXX000B

15

⎯

14

⎯

13

⎯

12

⎯

11

⎯

10

9

8

0000AF^H

TEN

TS1

TS0

Read/Write

R/W

- : Unused

(2) Block diagram

Timer clock selection circuit

Selector

X0

X1

Timer clock output

Oscillation

circuit

Time-base timer

Dividing by 2

DS07-13733-6E

61

MB90800 Series

17. ROM mirroring function selection module

ROM mirroring function selection module provides the setting so that ROM data located in FF bank can be read

by access to 00 bank.

(1) Register list

ROM mirror function select register (ROMM)

bit

Initial Value

XXXXXXX1B

15

14

13

12

11

10

9

8

00006F^H

MI

Read/Write

R/W

- : Unused

(2) Block diagram

F²MC-16LX bus

ROM mirroring function selection

Address area

Address

FF bank

00 bank

Data

ROM

Note : Do not access to ROM mirroring function selection register in the middle of the operation of the address

008000^Hto 00FFFFH.

62

DS07-13733-6E

MB90800 Series

18. Interrupt controller

Interrupt control register is in the interrupt controller. The register corresponds to all I/O of interrupt function. The

register has following functions;

• Setting of Interrupt level at correspondent peripheral circuit.

(1) Register list (at writing)

Interrupt control register

Initial Value

00000111B

Address :

ICR01 0000B1^H

ICR03 0000B3H

ICR05 0000B5H

ICR07 0000B7H

ICR09 0000B9H

ICR11 0000BBH

ICR13 0000BDH

ICR15 0000BFH

bit

15

14

13

12

11

10

9

8

ICS3

ICS2

ICS1

ICS0

ISE

IL2

IL1

IL0

Read/Write

Initial Value

W

R/W

Interrupt control register

Address :

ICR00 0000B0^H

ICR02 0000B2H

ICR04 0000B4H

ICR06 0000B6H

ICR08 0000B8H

ICR10 0000BAH

ICR12 0000BCH

ICR14 0000BEH

bit

7

6

5

4

3

2

1

0

00000111B

Read/Write

ICS3

ICS2

ICS1

ICS0

ISE

IL2

IL1

IL0

W

R/W

Note : Do not access using read modify write instruction because it causes the malfunction.

DS07-13733-6E

63

MB90800 Series

(2)Register list (at reading)

Interrupt control register

Initial Value

00000111B

Address :

ICR01 0000B1^H

ICR03 0000B3H

ICR05 0000B5H

ICR07 0000B7H

ICR09 0000B9H

ICR11 0000BBH

ICR13 0000BDH

ICR15 0000BFH

bit

15

14

13

12

11

10

9

8

⎯

S1

S0

ISE

IL2

IL1

IL0

Read/Write

Initial Value

Read/Write

Initial Value

⎯

R

R/W

Interrupt control register

Address :

ICR00 0000B0^H

ICR02 0000B2H

ICR04 0000B4H

ICR06 0000B6H

ICR08 0000B8H

ICR10 0000BAH

ICR12 0000BCH

ICR14 0000BEH

bit

7

6

5

4

3

2

1

0

00000111B

Read/Write

⎯

S1

S0

ISE

IL2

IL1

IL0

Read/Write

Initial Value

R

R/W

- : Unused

Note : Do not access using read modify write instruction because it causes the malfunction.

64

DS07-13733-6E

MB90800 Series

(3) Block diagram

Interrupt request

(Peripheral resources)

3

32

IL2

IL1

IL0

Judging the priority

of interrupt

3

(CPU)

Interrupt level

DS07-13733-6E

65

MB90800 Series

19. LCD controller/driver

The LCD controller/driver contains 24 × 8-bit display data memory and controls the LCD display with four common

output lines and 48 segment output lines. Three duty outputs can be selected to directly drive the LCD panel

(liquid crystal display).

• Contains an LCD driving voltage split resistor. Moreover, the external division resistance can be connected.

• A maximum of four common output lines (COM0 to COM3) and 48 segment output lines (SEG0 to SEG47)

are available.

• Contains 24-byte display data memory (display RAM).

• For the duty, 1/2, 1/3, or 1/4 can be selected (restricted by bias setting).

• The LCD can directly be driven.

Bias

1/2 duty

1/3 duty

1/4 duty

1/2 bias

1/3 bias

×

: Recommended mode

× : Disable

(1) Register list

• LCDC control register (upper) (LCRH)

bit

Initial Value

15

14

13

12

11

10

9

8

00000000B

Read/Write

00005D^H

SS4

VS0

CS1

CS0

SS3

SS2

R/W

SS1

R/W

SS0

R/W

• LCDC control register (lower) (LCRL)

bit

Initial Value

00010000B

7

6

5

4

3

2

1

0

00005C^H

CSS

LCEN

VSEL

BK

MS1

MS0

FP1

FP0

R/W

Read/Write

• LCDC range register (LCRR)

bit

Initial Value

00000000B

7

6

5

4

3

2

1

0

Reserved Reserved

00005E^H

SE4

SE3

SE2

SE1

SE0

LCR

R/W

Read/Write

66

DS07-13733-6E

MB90800 Series

(2) Block diagram

LCDC range register

(LCRR)

V0 V1 V2 V3

LCD control register

(LCRL)

Division resistor

Main

Clock

4

COM0

Timing

controller

COM1

COM2

COM3

Common

driver

Prescaler

Sub clock

(32 kHz)

Circuit

of

making

to

exchange

SEG0

SEG1

SEG2

SEG3

SEG4

to

48

Segment

driver

Display RAM

24 × 8-bit

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

LCD control register

(LCRH)

Controller

Driver

DS07-13733-6E

67

MB90800 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

VCC

VSS − 0.3

VSS + 4.0

V

Power supply voltage*¹

AV^CC

VCC ≥ AVCC*²

*3

Input voltage*¹

VI

N-ch open-drain

(5 V withstand voltageI/O) *⁴

V^SS− 0.3

VSS − 0.3

⎯

VSS + 6.0

VSS + 4.0

10

V

Output voltage*¹

VO

*3

Other than P74, P75,

P40 to P47*⁵

I^OL11

mA

“L” level maximum output current

“L” level average output current

P74, P75, P40 to P47

(Heavy-current output port) *⁵

IOL12

I^OLAV1

IOLAV2

⎯

30

3

mA

Other than P74, P75,

P40 to P47*⁶

P74, P75, P40 to P47

(Heavy-current output port) *⁶

15

mA

“L” level maximum total output current

“L” level average total output current

ΣIOL

⎯

120

60

ΣI^OLAV

mA *7

Other than P74, P75,

I^OH11

⎯

− 10

mA

P40 to P47*⁵

“H” level maximum output current

“H” level average output current

P40 to P47

(Heavy-current output port) *⁵

IOH12

IOHAV

ΣI^OH

⎯

− 12

− 3

mA *6

mA

“H” level maximum total output

current

− 120

“H” level average total output current

Power consumption

ΣI^OHAV

Pd

⎯

− 60

351

mA *7

mW

⎯

Operating temperature

Storage temperature

T^A

− 40

− 55

+ 85

+ 150

°C

T^STG

°C

*1 : The parameter is based on VSS = AVSS = 0.0 V.

*2 : AV^CCshould not be exceeding VCC at power-on etc.

*3 : V^I, VO, should not exceed Vcc + 0.3 V.

*4 : Applicable to pins : P74, P75

*5 : A peak value of an applicable one pin is specified as a maximum output current.

*6 : An average current value of an applicable one pin within 100 ms is specified as an average output current.

(Average value is found by multiplying operating current by operating rate.)

*7 : An average current value of all pins within 100 ms is specified as an average total output current.

(Average value is found by multiplying operating current by operating rate.)

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

68

DS07-13733-6E

MB90800 Series

2. Recommended Operating Conditions

( VSS = AVSS = 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

2.7

Max

3.6

V

At normal operating

Power supply voltage

V^CC

1.8

3.6

Stop operation state maintenance

CMOS input pin

V^IH

0.7 VCC

VCC + 0.3

CMOS hysteresis input pin

(Resisting pressure of 5 V is V^CC= 5.0 V)

“H” level input voltage

V^IHS

0.8 VCC

V

V^IHM

V^IL

VCC − 0.3

VSS − 0.3

− 40

VCC + 0.3

0.3 VCC

0.2 VCC

VSS + 0.3

+ 85

V

MD pin input

CMOS input pin

CMOS hysteresis input pin

MD pin input

“L” level input voltage

Operating temperature

V^ILS

V^ILM

T^A

V

°C

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

DS07-13733-6E

69

MB90800 Series

3. DC Characteristics

Sym-

(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Parameter

Pin name

Conditions

Unit

Remarks

bol

Min

Typ

Max

Outputpins

other than

P40toP47,

P74, P75

V^OH

I^OH= − 4.0 mA VCC − 0.5

⎯

Vcc

V

“H” level output

voltage

Heavy-current

output port

V^OH1P40 to P47 IOH = − 8.0 mA VCC − 0.5

⎯

Vcc

Outputpins

other than

P40toP47,

P74, P75

V^OL

I^OL= 4.0 mA

Vss

Vss + 0.4

“L” level output

voltage

Heavy-current

output port

V^OL1P40 to P47 IOL = 15.0 mA

Vss

⎯

0.5

⎯

Vss + 0.6

Vss + 0.8

Vss + 5.5

V

V^OL2

V^D1

P74, P75

IOL = 15.0 mA

Open-drain pin

Open-drain output

application voltage

⎯

Vss − 0.3

All output

pins

VCC = 3.3 V,

Input leak current

Pull-up resistor

I^IL

− 10

⎯

+ 10

μA

kΩ

V^SS< VI < VCC

Vcc = 3.3 V,

T^A= + 25 °C

R^UP

RST

25

50

100

Except

Vcc = 3.3 V,

T^A= + 25 °C

Pull-down resistor R^DOWN

MD2

25

50

100

10

kΩ Flash memory

products

Open drain output

current

I^leak

P74, P75

⎯

0.1

μA

VCC = 3.3 V,

Internal fre-

quency 25 MHz

At normal oper-

ating

⎯

48

60

mA

V^CC= 3.3 V,

Internal fre-

quency 25 MHz

At Flash writing

I^CC

Flash memory

mA

⎯

60

75

30

products

Power

supply

current

VCC

V^CC= 3.3 V,

Internal fre-

quency 25 MHz

At Flash erasing

Flash memory

mA

products

VCC = 3.3 V,

Internal fre-

quency 25 MHz

at sleep mode

I^CCS

22.5

mA

(Continued)

70

DS07-13733-6E

MB90800 Series

(Continued)

(V^CC= AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit Remarks

Min

Typ Max

VCC = 3.3 V,

Internal frequency 3 MHz

at timer mode

I^CCTS

⎯

0.75

15

7

mA

MASK ROM

products

⎯

140 μA

VCC = 3.3 V,

Internal frequency 8 kHz

at subclock operation,

(T^A= + 25 °C)

I^CCL

Flash

0.5

0.9 mA memory

products

Power

supply

current

VCC = 3.3 V,

Internal frequency 8 kHz

at subclock sleep operation,

(T^A= + 25 °C)

VCC

I^CCLS

⎯

13

40

μA

VCC = 3.3 V,

Internal frequency 8 kHz

at watch mode

I^CCT

⎯

1.8

0.8

40

μA

(T^A= + 25 °C)

At Stop mode,

(T^A= + 25 °C)

I^CCH

VCC − V3

V^CC− V3

At LCR = 0 setting

At LCR = 1 setting

100

200 400

25 50

12.5

V0 − V1,

V1 − V2,

V2 − V3

LCD division

resistance

At LCR = 0 setting

At LCR = 1 setting

50

100 200

R^LCD

kΩ

*

V0 − V1,

V1 − V2,

V2 − V3

6.25 12.5 25

COM0

to

COM3

COM0 to COM3

output impedance

R^VCOM

⎯

2.5

15

kΩ

V1 to V3 = 3.3 V

SEG0

to

SEG47

SEG0 to SEG47

output impedance

R^VSEG

V0 to V3,

COM0

to

LCD leak current

I^LCDC

COM3,

SEG0

to

⎯

− 5

⎯

+ 5

μA

SEG47

* : LCD internal divided resistor can be select two type resistor by internal divided resistor selecting bit (LCR) of

LCDC range register (LCRR) .

DS07-13733-6E

71

MB90800 Series

4. AC Characteristics

(1) Clock timing

(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Sym

bol

Condi-

tions

Parameter

Pin name

Unit

Remarks

Min

Typ

Max

External crystal

oscillation

3

16

× 1/2 (at PLL stop)

3

4

3

4

16

At oscillation circuit

Multiply by 1

At oscillation circuit

X0, X1

Multiply by 2

At oscillation circuit

12.5

8.33

Multiply by 3

At oscillation circuit

Multiply by 4

At oscillation circuit

f^CH

⎯

6.25 MHz

Clock frequency

× 1/2 (at PLL stop)

At external clock

25

Multiply by 1

At external clock

25

Multiply by 2

At external clock

X0

12.5

8.33

6.25

Multiply by 3

At external clock

⎯

Multiply by 4

At external clock

f^CLX0A, X1A

t^HCYLX0, X1

⎯

40

⎯

32.768

⎯

333

⎯

kHz

ns

Clock cycle time

t^LCYLX0A, X1A

30.5

μs

P^WH

X0

5

⎯

15.2

⎯

5

ns Set duty ratio 50% 3%

PWL

Input clock pulse width

P^WLH

X0A

PWLL

Set duty ratio at 30% to

μs

⎯

70% as a guideline.

Input clock rise time and

fall time

tcr

X0

tcf

ns At external clock

When main clock is

f^CP

f^CP1

t^CP

⎯

1.5

⎯

25

⎯

MHz

used

Internal operating clock

frequency

8.192

⎯

kHz When sub clock is used

When main clock is

used

40

⎯

666

⎯

ns

Internal operating clock

cycle time

t^CP1

122.1

μs When sub clock is used

72

DS07-13733-6E

MB90800 Series

• X0, X1 clock timing

tC

0.8 VCC

0.2 VCC

PWH

PWL

tcr

tcf

• X0A, X1A clock timing

tCL

0.8 VCC

0.2 VCC

PWLH

PWLL

tcr

tcf

DS07-13733-6E

73

MB90800 Series

• PLL operation guarantee range

Relation between internal operation clock frequency and power supply voltage

PLL operation guarantee range

3.6

3.0

2.7

Normal operation

assurance range

1.5

4.5

16

25

Internal operation clock f^CP(MHz)

Relation between oscillation clock frequency and internal operating clock frequency

Multiply by 1

Multiply by 4 Multiply by 3

Multiply by 2

25

16

12

× 1/2

(PLLoff)

8

6

External clock

4.5

4

3

4.5

6

8

12

16

25

4

Original oscillation clock fCH (MHz)

Rating values of alternating current is defined by the measurement reference voltage values shown below :

• Input signal waveform

• Output signal waveform

Hysteresis input pin

Output pin

0.8 VCC

2.4 V

0.2 VCC

0.8 V

74

DS07-13733-6E

MB90800 Series

(2) Reset input timing

(V^CC= AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Sym-

bol

Condi-

tions

Parameter

Pin name

Unit

Remarks

Min

Max

At normal operating,

at time base timer mode,

at main sleep mode,

at PLL sleep mode

500

⎯

ns

Reset input time

t^RSTL

RST

⎯

At stop mode,

Oscillation time

of oscillator*+

500 ns

at sub clock mode,

at sub sleep mode,

at watch mode

⎯

μs

* : Oscillation time of oscillator is time until oscillation reaches 90% of amplitude. It takes several milliseconds to

several dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds

on a ceramic oscillator, and 0 milliseconds on an external clock.

• In normal operating, time base timer mode, main sleep mode and PLL sleep mode

t

RSTL

RST

0.2 VCC

• In stop mode, sub clock mode, sub sleep mode and watch mode

t

RSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal operating

clock

Oscillationtime

of oscillator

500 ns

Wait time for stabilization oscillator

Execute instruction

Internal reset

DS07-13733-6E

75

MB90800 Series

(3) Power-on reset

(V^CC= AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Condi-

tions

Parameter

Symbol Pin name

Unit

Remarks

Min

Max

Power supply rising time

t^R

VCC

⎯

30

ms At normal operating

⎯

Power supply shutdown

time

Wait time until power

t^OFF

1

⎯

ms

on

Notes : • V^CCshould be set under 0.2 V before power-on rising up.

• These value are for power-on reset.

• In the device, there are internal registers which is initialized only by a power-on reset. If these initialization

is executing, power-on procedure must be obeyed by these value.

tR

2.7 V

V

CC

0.2 V

tOFF

Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power

supply voltages during operation, raise the power smoothly by suppressing variation of voltages as shown

below.

VCC

Limiting the slope of rising within

50 mV/ms is recommended.

2.7 0.3 V

RAM data hold

VSS

76

DS07-13733-6E

MB90800 Series

(4) Serial I/O

(V^CC= AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Min

Max

Serial clock cycle time

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

SCK ↑ → Valid

SIN hold time

t^SCYC

t^SLOV

t^IVSH

t^SHIX

SC0 to SC3

8 t^CP

⎯

ns

SC0 to SC3,

SO0 to SO3

−80

100

60

+ 80

⎯

Internal shift clock

mode output pin :

C^L= 80 pF + 1TTL

SC0 to SC3,

SI0 to SI3

⎯

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

t^SLSH

4 t^CP

⎯

ns

SC0 to SC3

4 tCP

SC0 to SC3,

SO0 to SO3

External shift clock

mode output pin :

C^L= 80 pF + 1TTL

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

SCK ↑ → valid

SIN hold time

t^SLOV

t^IVSH

t^SHIX

⎯

60

150

⎯

ns

SC0 to SC3,

SI0 to SI3

⎯

Notes : • The above rating is in CLK synchronous mode.

• C^Lis a load capacitance value on pins for testing.

• t^CPis machine cycle frequency (ns) . Refer to “ (1) Clock timing”.

• Internal shift clock mode

tSCYC

SC

2.4 V

0.8 V

tSLOV

2.4 V

SO

0.8 V

tIVSH

tSHIX

0.8 V^CC

0.2 VCC

0.8 VCC

0.2 VCC

SI

• External shift clock mode

t

SLSH

t

SHSL

SC

0.8 VCC

0.2 VCC

t

SLOV

2.4 V

0.8 V

SO

t

IVSH

t

SHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SI

DS07-13733-6E

77

MB90800 Series

(5) Timer input timing

(V^CC= AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Min

Max

t^TIWH

tTIWL

TIN0 to TIN2,

IC0, IC1

Input pulse width

⎯

4 t^CP

⎯

ns

Note : t^CPis machine cycle frequency (ns) . Refer to “ (1) Clock timing”.

• Timer Input Timing

0.8 VCC

0.2 VCC

TINx

ICx

0.2 VCC

t

TIWH

tTIWL

(6) Timer output timing

Parameter

(V^CC= AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Symbol

Pin name

Conditions

Unit

Min

Max

TOT0 to TOT2,

PPG0, PPG1,

OCU0, OCU1

CLK ↑ → T^OUTchange time

tTO

⎯

30

⎯

ns

• Timer Output Timing

2.4 V

CLK

t^TO

TOTx

PPGx

OCUx

2.4 V

0.8 V

(7) Trigger input timing

(V^CC= AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)

Value

Condi-

tions

Parameter

Symbol

Pin name

Unit

Remarks

Min

5 t^CP

1

Max

⎯

ns

At normal operating

In Stop mode

t^TRGH

tTRGL

Input pulse width

INT0 to INT3

⎯

μs

Note : t^CPis machine cycle frequency (ns) . Refer to “ (1) Clock timing”.

• Trigger Input Timing

0.8 VCC

0.2 VCC

INTx

0.2 VCC

tTRGH

tTRGL

78

DS07-13733-6E

MB90800 Series

(8) I²C timing

(AV^CC= VCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)

Standard-

mode

Parameter

Symbol

Conditions

Unit

Min Max

SCL clock frequency

f^SCL

0

100 kHz

Hold time (repeated) START condition

SDA ↓ → SCL ↓

t^HDSTA

4.0

⎯

μs

When power supply voltage of external

pull-up resistor is 5.0 V

“L” width of the SCL clock

“H” width of the SCL clock

t^LOW

t^HIGH

4.7

4.0

⎯

μs

R = 1.0 kΩ, C = 50 pF*²

When power supply voltage of external

pull-up resistor is 3.6 V

Set-up time for a repeated START condition

SCL ↑ → SDA ↓

t^SUSTA

t^HDDAT

4.7

0

⎯

μs

R = 1.0 kΩ, C = 50 pF*²

Data hold time

SCL ↓ → SDA ↓ ↑

3.45

3

*

When power supply voltage of external

pull-up resistor is 5.0 V

f^CP*¹≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*²250

⎯

ns

4

When power supply voltage of external

pull-up resistor is 3.6 V

*

f^CP*¹≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*²

Data set-up time

SDA ↓ ↑ → SCL ↑

t^SUDAT

When power supply voltage of external

pull-up resistor is 5.0 V

f^CP*¹> 20 MHz, R = 1.0 kΩ, C = 50 pF*²200

4

When power supply voltage of external

pull-up resistor is 3.6 V

f^CP*¹> 20 MHz, R = 1.0 kΩ, C = 50 pF*²

*

Set-up time for STOP condition

SCL ↑ → SDA ↑

When power supply voltage of external

pull-up resistor is 5.0 V

t^SUSTO

4.0

4.7

⎯

μs

R = 1.0 kΩ, C = 50 pF*²

When power supply voltage of external

pull-up resistor is 3.6 V

Bus free time between a STOP and START

condition

t^BUS

R = 1.0 kΩ, C = 50 pF*²

*1 : f^CPis internal operation clock frequency. Refer to “ (1) Clock timing”.

*2 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*3 : The maximum t^HDDATonly has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.

*4 : Refer to “• Note of SDA and SCL set-up time”.

DS07-13733-6E

79

MB90800 Series

• Note of SDA and SCL set-up time

SDA

Input data set-up time

SCL

6 tcp

Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on

the load capacitance or pull-up resistor.

Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be

satisfied.

• Timing definition

SDA

tBUS

tHDSTA

tSUDAT

tLOW

SCL

tHDSTA

tSUSTA

tHIGH

tSUSTO

tHDDAT

fSCL

80

DS07-13733-6E

MB90800 Series

5. A/D Converter

(1) A/D Converter Electrical Characteristics

(V^CC= AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40°C to + 85 °C)

Value

Typ

⎯

Sym-

bol

name

Condi-

tions

Parameter

Resolution

Unit

Remarks

Min

⎯

Max

10

⎯

bit

Total error

3.0

2.5

LSB

Nonlinear error

⎯

Differential linear

error

⎯

1.9

LSB

AN0

to

AN11

Zero transition

voltage

V^OT

AV^SS− 1.5LSB AVss + 0.5LSB AVSS + 2.5LSB

AVcc − 3.5LSB AVcc − 1.5LSB AVcc + 0.5LSB

V

1 LSB =

(AV^CC- AVSS)/

1024

Full-scale

transition

voltage

AN0

to

AN11

V^FST

V

Conversion time

Sampling time

⎯

8.64*¹

2

⎯

μs

AN0

to

AN11

Analog port input

current

⎯

I^AIN

⎯

10

μA

AN0

to

AN11

Analog input

voltage

V^AIN

0

⎯

AVcc

V

Reference

voltage

⎯

AVcc

3.0

I^A

I^AH

I^R

AVcc

⎯

1.4

⎯

3.5

5*²

mA

μA

Power supply

current

Reference

94

150

voltage supplying

current

I^RH

AVcc

⎯

5*²

μA

AN0

to

AN11

Interchannel

disparity

⎯

4

LSB

*1 : At operating, main clock 25 MHz.

*2 : If A/D converter is not operating, a current when CPU is stopped is applicable (at Vcc − CPU = AVcc = 3.3 V)

DS07-13733-6E

81

MB90800 Series

(2) Notes on Using A/D Converter

• About the external impedance of analog input and its sampling time

A/D converter with sample & hold circuit. If the external impedance is too high to keep sufficient sampling time,

the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relation-ship

between the external impedance and minimum sampling time and either adjust the resistor value and operating

frequency or decrease the external impedance so that the sampling time is longer than the minimum value.

And, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.

• Analog input circuit model

R

Analog input

Comparator

C

During sampling : ON

R

1.9 kΩ (Max) 32.3 pF (Max)

MB90F804-201(101)/F803(S)/F809(S) 1.9 kΩ (Max) 25.0 pF (Max)

MB90V800 1.9 kΩ (Max) 32.3 pF (Max)

C

MB90803 (S)

Note : The values are reference values.

• The relationship between external impedance and minimum sampling time

(External impedance = 0 kΩ to 100 kΩ)

(External impedance = 0 kΩ to 20 kΩ)

MB90F804-201(101)/

MB90F803(S)/

MB90F809(S)

MB90803(S)/

MB90V800

MB90F803(S)/

MB90F809(S)

MB90803(S)/

MB90V800

20

18

16

14

12

10

8

100

90

80

70

60

50

40

30

20

10

0

6

4

2

0

1

2

3

4

5

6

7

8

0

5

10

15

20

25

30

35

Minimum sampling time [μs]

• About errors

As | AV^CC− AVSS | becomes smaller, values of relative errors grow larger.

82

DS07-13733-6E

MB90800 Series

6. Definition of A/D Converter Terms

Resolution

Analog variation that is recognized by an A/D converter.

The 10-bit can resolve analog voltage into 2¹⁰= 1024.

Total error

This shows the difference between the actual voltage and the ideal value and means a total of error because of

offset error, gain error, non-linearity error and noise.

Linearity error

^{Deviation between a line across zero-transition line (00 0000 0000}↔00 0000 0001) and full-scale transition line

^{(11 1111 1110}↔11 1111 1111) and actual conversion characteristics.

Differential linear error

Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.

Total error

3FF

3FE

3FD

H

1.5 LSB

H

Actual conversion

characteristic

H

{1 LSB × (N − 1) + 0.5 LSB}

004

003

002

001

H

V^NT

(measurement value)

Actual conversion

characteristics

Ideal characteristics

0.5 LSB

AVSS

(AVRL)

AVCC

(AVRH)

Analog input

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

Total error of digital output N =

[LSB]

1 LSB

AV^CC− AVSS

1LSB(Ideal value) =

[V]

1024

N : A/D converter digital output value

VOT(Ideal value) = AVSS + 0.5 LSB [V]

V^FST(Ideal value) = AVCC − 1.5 LSB [V]

V^NT: A voltage at which digital output transitions from (N − 1)H to NH.

(Continued)

DS07-13733-6E

83

MB90800 Series

(Continued)

Linearity error

Differential linear error

Actual conversion characteristic

Ideal characteristics

3FF

H

Actual conversion

characteristics

{1 LSB (N 1) V }

3FE

H

(N + 1)

H

×

−

+

OT

V

FST

3FDH

(measurement value)

N

V

NT

(measurement value)

004

003

002

001

H

V

(N + 1)T

Actual conversion

characteristics

(measurement value)

H

(N − 1)

(N − 2)

V

NT

H

(measurement value)

Ideal characteristics

OT (actual measurement value)

Actual conversion

characteristics

V

AVCC

(AVRH)

AVSS

(AVRL)

AVSS

(AVRL)

AVCC

(AVRH)

Analog input

V^NT− {1 LSB × (N − 1) + VOT}

Linear error in digital output N =

[LSB]

1 LSB

V^{(N + 1) T}− VNT

− 1LSB

Differential linear error in digital output N =

1 LSB =

1 LSB

V^FST− VOT

[V]

1022

N : A/D converter digital output value

V^OT: Voltage at which digital output transits from 000H to 001H.

VFST : Voltage at which digital output transits from 3FEH to 3FFH.

84

DS07-13733-6E

MB90800 Series

7. Flash Memory (MB90F804-101/201, MB90F809/S)

Value

Parameter

Conditions

Unit

Remarks

Min

⎯

Typ

1

Max

15

Sector erase time

Chip erase time

Excludes 00^Hprogramming

prior to erasure.

s

T^A= + 25 °C

Vcc = 3.0 V

⎯

9

⎯

Word (16-bit width)

programming time

Except for the over head time

of the system.

⎯

10000

20

16

⎯

3600

⎯

μs

Program/erase cycle

⎯

cycle

year

Flash memory data

retention time

Average

T^A= + 85 °C

⎯

*

* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at + 85 °C).

8. Dual Operation Flash Memory (MB90F803/S)

Value

Parameter

Conditions

Unit

Remarks

Min

Typ

Max

Sector erase time

(4 Kbytes sector )

⎯

0.2

0.5

Excludes 00^Hprogramming

prior to erasure.

Sector erase time

(16 Kbytes sector)

s

⎯

0.5

4.6

64

⎯

7.5

⎯

T^A= +25 °C

Vcc = 3.0 V

Chip erase time

Word (16-bit width)

programming time

Except for the over head time

of the system.

⎯

3600

⎯

μs

⎯

Program/erase cycle

10000

20

cycle

year

Flash memory data

retention time

Average

T^A= + 85 °C

⎯

*

* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at + 85 °C).

DS07-13733-6E

85

MB90800 Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB90F804-101PF-G

MB90F804-201PF-G

MB90F803PF-G

MB90F803SPF-G

MB90F809PF-G

With sub clock:

Products without "S" suffix

201 option products

Without sub clock:

100-pin plastic QFP

(FPT-100P-M06)

MB90F809SPF-G

Products with "S" suffix

101 option products

MB90803PF-G

MB90803SPF-G

86

DS07-13733-6E

MB90800 Series

■ PACKAGE DIMENSION

100-pin plastic QFP

Lead pitch

0.65 mm

Package width ×

package length

14.00 × 20.00 mm

Gullwing

Lead shape

Sealing method

Mounting height

Plastic mold

3.35 mm MAX

P-QFP100-14×20-0.65

Code

(Reference)

(FPT-100P-M06)

100-pin plastic QFP

(FPT-100P-M06)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

23.90±0.40(.941±.016)

*

20.00±0.20(.787±.008)

80

51

81

50

0.10(.004)

17.90±0.40

(.705±.016)

*

14.00±0.20

(.551±.008)

INDEX

Details of "A" part

100

31

0.25(.010)

3.00 ⁺^–0⁰^.^.²³⁰⁵

.118 ⁺^–.^.⁰⁰⁰¹⁸⁴

(Mounting height)

0~8˚

1

30

0.65(.026)

0.32±0.05

(.013±.002)

0.17±0.06

(.007±.002)

M

0.13(.005)

0.25±0.20

(.010±.008)

(Stand off)

0.80±0.20

(.031±.008)

"A"

0.88±0.15

(.035±.006)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2002 FUJITSU LIMITED F100008S-c-5-5

Please check the latest Package dimension at the following URL.

http://edevice.fujitsu.com/package/en-search/

DS07-13733-6E

87

MB90800 Series

■ MAIN CHANGES IN THIS EDITION

Page

Section

■ MEMORY MAP

Change Results

Corrected “Address #2” for part number MB90F809/S.

17

FC8000^H→ FD0000H

The vertical lines marked in the left side of the page show the changes.

88

DS07-13733-6E

MB90800 Series

MEMO

DS07-13733-6E

89

MB90800 Series

MEMO

90

DS07-13733-6E

MB90800 Series

MEMO

DS07-13733-6E

91

MB90800 Series

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,

Shinjuku-ku, Tokyo 163-0722, Japan

Tel: +81-3-5322-3329

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

Asia Pacific

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://www.fmal.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.

Rm. 3102, Bund Center, No.222 Yan An Road (E),

Shanghai 200002, China

Tel : +86-21-6146-3688 Fax : +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

Korea

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road,

Tsimshatsui, Kowloon, Hong Kong

Tel : +852-2377-0226 Fax : +852-2376-3269

http://cn.fujitsu.com/fmc/en/

FUJITSU MICROELECTRONICS KOREA LTD.

206 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fmk/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating

the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or

other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to

the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear

facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon

system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Sales Promotion Department


型号：	MB90800_09
厂家：	FUJITSU
描述：	16-bit Microcontroller 16位微控制器微控制器
文件：	总92页 (文件大小：458K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90800_09 [FUJITSU]

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