MB90F574APMC1 [FUJITSU]
16-bit Proprietary Microcontroller; 16位微控制器专有型号: | MB90F574APMC1 |
厂家: | FUJITSU |
描述: | 16-bit Proprietary Microcontroller |
文件: | 总120页 (文件大小:2711K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13701-9E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90570A/570C Series
MB90573/574C/F574A/V570A
■ DESCRIPTION
The MB90570A/570C series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for
process control applications in consumer products that require high-speed real time processing. It contains an
I2C bus interface that allows inter-equipment communication to be implemented readily. This product is well
adapted to car audio equipment, VTR systems, and other equipment and systems.
The instruction set of F2MC-16LX CPU core inherits AT architecture of F2MC* family with additional instruction
sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and en-
hanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data.
The MB90570A/570C series has peripheral resources of an 8/10-bit A/D converter, an 8-bit D/A converter, UART
(SCI), an extended I/O serial interface, an 8/16-bit up/down counter/timer, an 8/16-bit PPG timer, I/O timer (a 16-
bit free run timer, an input capture (ICU), an output compare (OCU)).
*: F2MC is the abbreviation for Fujitsu Flexible Microcontroller.
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2001-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.9
MB90570A/570C Series
■ FEATURES
• Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from 1/2 to 4× oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, 4× PLL clock, operation at VCC of 5.0 V)
• Maximum memory space
16 Mbytes
• Instruction set optimized for controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed
4-byte instruction queue
• Enhanced interrupt function
8 levels, 34 factors
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS): Up to 16 channels
• Embedded ROM size and types
Mask ROM: 128 kbytes/256 kbytes
Flash ROM: 256 kbytes
Embedded RAM size:6 kbytes/10 kbytes (mask ROM)
10 kbytes (flash memory)
10 kbytes (evaluation device)
• Low-power consumption (standby) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Hardware standby mode
• Process
CMOS technology
• I/O port
General-purpose I/O ports (CMOS): 63 ports
General-purpose I/O ports (with pull-up resistors): 24 ports
General-purpose I/O ports (open-drain): 10 ports
Total: 97 ports
• Timer
Timebase timer/watchdog timer: 1 channel
8/16-bit PPG timer: 8-bit × 2 channels or 16-bit × 1 channel
• 8/16-bit up/down counter/timer: 1 channel (8-bit × 2 channels)
(Continued)
2
DS07-13701-9E
MB90570A/570C Series
(Continued)
• 16-bit I/O timer
16-bit free run timer:
Input capture (ICU):
1 channel
Generates an interrupt request by latching a 16-bit free run timer counter value upon
detection of an edge input to the pin.
Output compare (OCU): Generates an interrupt request and reverse the output level upon detection of a match
between the 16-bit free run timer counter value and the compare setting value.
• Extended I/O serial interface: 3 channels
• I2C interface (1 channel)
Serial I/O port for supporting Inter IC BUS
• UART0 (SCI), UART1 (SCI)
With full-duplex double buffer
Clock asynchronized or clock synchronized transmission can be selectively used.
• DTP/external interrupt circuit (8 channels)
A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt triggered
by an external input.
• Delayed interrupt generation module
Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
8/10-bit resolution
Starting by an external trigger input.
Conversion time: 26.3 µs
• 8-bit D/A converter (based on the R-2R system)
8-bit resolution: 2 channels (independent)
Setup time: 12.5 µs
• Watch timer: 1 channel
• Chip select output (8 channels)
An active level can be set.
• Clock output function
DS07-13701-9E
3
MB90570A/570C Series
■ PRODUCT LINEUP
Part number
MB90573
Item
MB90574C
MB90F574A
MB90V570A
Classification
ROM size
Mask ROM products
Flash ROM products Evaluation product
256 kbytes None
128 kbytes
6 kbytes
RAM size
10 kbytes
The number of instructions: 340
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
CPU functions
Minimum execution time: 62.5 ns (at machine clock of 16 MHz)
Interrupt processing time: 1.5 µs (at machine clock of 16 MHz, minimum value)
General-purpose I/O ports (CMOS output): 63
General-purpose I/O ports (with pull-up resistor): 24
General-purpose I/O ports (N-ch open-drain output): 10
Total: 97
Ports
Clock synchronized transmission (62.5 kbps to 1 Mbps)
Clock asynchronized transmission (1202 bps to 9615 bps)
Transmission can be performed by bi-directional serial transmission or by
master/slave connection.
UART0 (SCI), UART1 (SCI)
Resolution: 8/10-bit
Number of inputs: 8
One-shot conversion mode (converts selected channel only once)
Scan conversion mode (converts two or more successive channels and can
program up to 8 channels.)
8/10-bit A/D converter
8/16-bit PPG timer
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
Number of channels: 1 (or 8-bit × 2 channels)
PPG operation of 8-bit or 16-bit
A pulse wave of given intervals and given duty ratios can be output.
Pulse interval: 62.5 ns to 1 µs (at oscillation of 4 MHz, machine clock of 16 MHz)
Number of channels: 1 (or 8-bit × 2 channels)
Event input: 6 channels
8-bit up/down counter/timer used: 2 channels
8-bit re-load/compare function supported: 1 channel
8/16-bit up/down counter/
timer
16-bit
free run timer
Number of channel: 1
Overflow interrupts
Output
compare
(OCU)
Number of channels: 4
Pin input factor: A match signal of compare register
16-bit
I/O timer
Input
capture
(ICU)
Number of channels: 2
Rewriting a register value upon a pin input (rising, falling, or both edges)
(Continued)
4
DS07-13701-9E
MB90570A/570C Series
(Continued)
Part number
MB90573
MB90574C
MB90F574A
MB90V570A
Item
Number of inputs: 8
DTP/external interrupt
circuit
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
External interrupt circuit or extended intelligent I/O service (EI2OS) can be used.
Delayed interrupt
generation module
An interrupt generation module for switching tasks used in real time operating
systems.
Clock synchronized transmission (3125 bps to 1 Mbps)
LSB first/MSB first
Extended I/O serial interface
I2C interface
Serial I/O port for supporting Inter IC BUS
18-bit counter
Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms
(at oscillation of 4 MHz)
Timebase timer
8-bit resolution
8-bit D/A converter
Watchdog timer
Number of channels: 2 channels
Based on the R-2R system
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Low-power consumption
(standby) mode
Sleep/stop/CPU intermittent operation/watch timer/hardware standby
Process
CMOS
Power supply voltage for
operation*
4.5 V to 5.5 V
* : Varies with conditions such as the operating frequency. (See section “■ ELECTRICAL CHARACTERISTICS.”)
Assurance for the MB90V570A is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an
operating temperature of 0 °C to +25 °C, and an operating frequency of 1 MHz to 16 MHz.
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
MB90573
MB90F574A
MB90574C
FPT-120P-M24
FPT-120P-M13
FPT-120P-M21
×
×
: Available ×: Not available
Note : For more information about each package, see section “■ PACKAGE DIMENSIONS.”
DS07-13701-9E
5
MB90570A/570C Series
■ DIFFERENCES AMONG PRODUCTS
Memory Size
In evaluation with an evaluation product, note the difference between the evaluation product and the product
actually used. The following items must be taken into consideration.
• The MB90V570A does not have an internal ROM, however, operations equivalent to chips with an internal
ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of
the development tool.
• In the MB90V570A, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to
mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.)
• In the MB90573/574C/F574A, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to
FF3FFFH to bank FF only.
• The products designated with /A or /C are different from those without /A or /C in that they are DTP/externally-
interrupted types which return from standby mode at the ch.0 to ch.1 edge request.
6
DS07-13701-9E
MB90570A/570C Series
■ PIN ASSIGNMENT
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
RST
MD0
MD1
MD2
HST
PC3
PC2
PC1
P31/RD
P32/WRL
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
VCC
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
P45/SCK1
P46/PPG0
P47/PPG1
P50/SIN2
P51/SOT2
P52/SCK2
P53/SIN3
P54/SOT3
P55/SCK3
P56/IN0
P57/IN1
P60/SIN4
P61/SOT4
P62/SCK4
P63/CKOT
P64/OUT0
P65/OUT1
PC0
PB7
PB6/ADTG
PB5/IRQ5
PB4/IRQ4
PB3/IRQ3
PB2/IRQ2
PB1/IRQ1
X0A
X1A
PB0/IRQ0
PA7/SCL
PA6/SDA
PA5/ZIN1
PA4/BIN1
PA3/AIN1/IRQ7
PA2/ZIN0
PA1/BIN0
PA0/AIN0/IRQ6
VSS
P97/CS7
P96/CS6
(FPT-120P-M24)
(FPT-120P-M13)
(FPT-120P-M21)
DS07-13701-9E
7
MB90570A/570C Series
■ PIN DESCRIPTION
Pin no.
Circuit
LQFP *1
QFP *2
Pin name
Function
type
92,93
74,73
X0,X1
A
B
High speed oscillator pins
Low speed oscillator pins
X0A,X1A
These are input pins used to designate the operating mode. They
should be connected directly to Vcc or Vss.
89 to 87
MD0 to MD2
C
90
86
RST
HST
C
C
Reset input pin
Hardware standby input pin
In single chip mode, these are general purpose I/O pins. When set for
input, they can be set by the pull-up resistance setting register
(RDR0). When set for output, this setting will be invalid.
P00 to P07
AD00 toAD07
P10 to P17
95 to 102
D
D
In external bus mode, these pins function as address low output/data
low I/O pins.
In single chip mode, these are general purpose I/O pins. When set for
input, they can be set by the pull-up resistance setting register
(RDR1). When set for output, the setting will be invalid.
103 to 110
In external bus mode, these pins function as address middle output/
data high I/O pins.
AD08 toAD15
P20 to P27
A16 to A23
P30
In single chip mode this is a general-purpose I/O port.
111 to 118
E
E
E
E
E
E
In external bus mode, these pins function as address high output
pins.
In single chip mode this is a general-purpose I/O port.
120
1
In external bus mode, this pin functions as the address latch enable
signal output pin.
ALE
P31
In single chip mode this is a general-purpose I/O port.
In external bus mode, this pin functions as the read strobe signal out-
put pin.
RD
P32
In single chip mode this is a general-purpose I/O port.
2
In external bus mode, this pin functions as the data bus lower 8-bit
write strobe signal output pin.
WRL
P33
In single chip mode this is a general-purpose I/O port.
3
In external bus mode, this pin functions as the data bus upper 8-bit
write strobe signal output pin.
WRH
P34
In single chip mode this is a general-purpose I/O port.
4
In external bus mode, this pin functions as the hold request signal in-
put pin.
HRQ
P35
In single chip mode this is a general-purpose I/O port.
5
6
E
E
In external bus mode, this pin functions as the hold acknowledge sig-
nal output pin.
HAK
P36
In single chip mode this is a general-purpose I/O port.
RDY
In external bus mode, this pin functions as the ready signal input pin.
*1 : FPT-120P-M24
*2 : FPT-120P-M13, FPT-120P-M21
(Continued)
8
DS07-13701-9E
MB90570A/570C Series
Pin no.
Circuit
type
LQFP *1
Pin name
P37
Function
QFP *2
In single chip mode this is a general-purpose I/O port.
7
9
E
In external bus mode, this pin functions as the clock (CLK) signal out-
put pin.
CLK
P40
In single chip mode this is a general-purpose I/O port. It can be set to
open drain by the ODR4 register.
This is also the UART ch.0 serial data input pin. While UART ch.0 is
in input operation, this input signal is in continuous use, and therefore
the output function should only be used when needed. If shared by
output from other functions, this pin should be output disabled during
SIN operation.
F
SIN0
In single chip mode this is a general-purpose I/O port. It can be set to
open drain by the ODR4 register.
P41
10
11
F
F
This is also the UART ch.0 serial data output pin. This function is valid
when UART ch.0 is enabled for data output.
SOT0
P42
In single chip mode this is a general-purpose I/O port. It can be set to
open drain by the ODR4 register.
This is also the UART ch.0 serial clock I/O pin. This function is valid
when UART ch.0 is enabled for clock output.
SCK0
P43
In single chip mode this is a general-purpose I/O port. It can be set to
open-drain by the ODR4 register.
This is also the UART ch.1 serial data input pin. While UART ch.1 is
in input operation, this input signal is in continuous use, and therefore
the output function should only be used when needed. If shared by
output from other functions, this pin should be output disabled during
SIN operation.
12
F
SIN1
In single chip mode this is a general-purpose I/O port. It can be set to
opendrain by the ODR4 register.
P44
13
14
F
F
F
E
This is also the UART ch.1 serial data output pin. This function is valid
when UART ch.1 is enabled for data output.
SOT1
P45
In single chip mode this is a general-purpose I/O port. It can be set to
open drain by the ODR4 register.
This is also the UART ch.1 serial clock I/O pin. This function is valid
when UART ch.1 is enabled for clock output.
SCK1
P46,P47
In single chip mode this is a general-purpose I/O port. It can be set to
open drain by the ODR4 register.
15,16
17
These are also the PPG0, 1 output pins. This function is valid when
PPG0, 1 output is enabled.
PPG0,PPG1
P50
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.0 data input pin. During serial data input,
this input signal is in continuous use, and therefore the output function
should only be used when needed.
SIN2
*1 : FPT-120P-M24
*2 : FPT-120P-M13, FPT-120P-M21
(Continued)
DS07-13701-9E
9
MB90570A/570C Series
Pin no.
Circuit
LQFP *1
QFP *2
Pin name
Function
type
P51
In single chip mode this is a general-purpose I/O port.
18
19
E
This is also the I/O serial ch.0 data output pin. This function is valid
when serial ch.0 is enabled for serial data output.
SOT2
P52
In single chip mode this is a general-purpose I/O port.
E
E
This is also the I/O serial ch.0 clock I/O pin. This function is valid when
serial ch.0 is enabled for serial data output.
SCK2
P53
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.1 data input pin. During serial data input,
this input signal is in continuous use, and therefore the output function
should only be used when needed.
20
SIN3
P54
In single chip mode this is a general-purpose I/O port.
21
22
E
E
This is also the I/O serial ch.1 data output pin. This function is valid
when serial ch.1 is enabled for serial data output.
SOT3
P55
In single chip mode this is a general-purpose I/O port.
This is also the I/O serial ch.1 clock I/O pin. This function is valid when
serial ch.1 is enabled for serial data output.
SCK3
P56,P57
In single chip mode this is a general-purpose I/O port.
These are also the input capture ch.0/1 trigger input pins. During input
capture signal input on ch.0/1 this function is in continuous use, and
therefore the output function should only be used when needed.
23,24
25
E
F
IN0,IN1
P60
In single chip mode this is a general-purpose I/O port. When set for
input it can be set by the pull-up resistance register (RDR6). When set
for output this setting will be invalid.
This is also the I/O serial ch.2 data input pin. During serial data input
this function is in continuous use, and therefore the output function
should only be used when needed.
SIN4
In single chip mode this is a general-purpose I/O port. When set for
input it can be set by the pull-up resistance register (RDR6). When set
for output this setting will be invalid.
P61
26
27
28
F
F
F
This is also the I/O serial ch.2 data output pin. This function is valid
when serial ch.2 is enabled for serial data output.
SOT4
P62
In single chip mode this is a general-purpose I/O port. When set for
input it can be set by the pull-up resistance register (RDR6). When set
for output this setting will be invalid.
This is also the I/O serial ch.2 serial clock I/O pin. This function is valid
when serial ch.2 is enabled for serial data output.
SCK4
P63
In single chip mode this is a general-purpose I/O port. When set for
input it can be set by the pull-up resistance register (RDR6). When set
for output this setting will be invalid.
This is also the clock monitor output pin. This function is valid when
clock monitor output is enabled.
CKOT
*1 : FPT-120P-M24
*2 : FPT-120P-M13, FPT-120P-M21
(Continued)
10
DS07-13701-9E
MB90570A/570C Series
Pin no.
LQFP *1
QFP *2
Circuit
type
Pin name
Function
In single chip mode these are general-purpose I/O ports. When set for
input they can be set by the pull-up resistance register (RDR6). When
set for output this setting will be invalid.
P64 to P67
29 to 32
F
These are also the output compare ch.0 to ch.3 event output pins.
This function is valid when the respective channel(s) are enabled for
output.
OUT0 to
OUT3
35 to 37
40,41
P70 to P72
P73,P74
E
I
These are general purpose I/O ports.
These are general purpose I/O ports.
DA0,DA1
P80 to P87
These are also the D/A converter ch.0,1 analog signal output pins.
These are general purpose I/O ports.
46 to 53
K
These are also A/D converter analog input pins. This function is valid
when analog input is enabled.
AN0 to AN7
P90 to P97
CS0 to CS7
These are general purpose I/O ports.
55 to 62
34
E
These are also chip select signal output pins. This function is valid
when chip select signal output is enabled.
This is the power supply stabilization capacitor pin. It should be
connected externally to an 0.1 µF ceramic capacitor. Note that this is
not required on the FLASH model (MB90F574A) and MB90574C.
C
G
PA0
This is a general purpose I/O port.
This pin is also used as count clock A input for 8/16-bit up-down
counter ch.0.
64
AIN0
E
IRQ6
PA1
This pin can also be used as interrupt request input ch. 6.
This is a general purpose I/O port.
65
66
E
E
This pin is also used as count clock B input for 8/16-bit up-down
counter ch.0.
BIN0
PA2
This is a general purpose I/O port.
This pin is also used as count clock Z input for 8/16-bit up-down
counter ch.0.
ZIN0
PA3
This is a general purpose I/O port.
This pin is also used as count clock A input for 8/16-bit up-down
counter ch.1.
67
AIN1
E
IRQ7
PA4
This pin can also be used as interrupt request input ch.7.
This is a general purpose I/O port.
68
69
E
E
This pin is also used as count clock B input for 8/16-bit up-down
counter ch.1.
BIN1
PA5
This is a general purpose I/O port.
This pin is also used as count clock Z input for 8/16-bit up-down
counter ch.1.
ZIN1
*1 : FPT-120P-M24
*2 : FPT-120P-M13, FPT-120P-M21
(Continued)
DS07-13701-9E
11
MB90570A/570C Series
(Continued)
Pin no.
Circuit
Pin name
Function
LQFP *1
QFP *2
type
PA6
This is a general purpose I/O port.
This pin is also used as the data I/O pin for the I2C interface. This
function is valid when the I2C interface is enabled for operation. While
the I2C interface is operating, this port should be set to the input level
(DDRA: bit6 = 0).
70
71
L
SDA
PA7
SCL
This is a general purpose I/O port.
This pin is also used as the clock I/O pin for the I2C interface. This
function is valid when the I2C interface is enabled for operation. While
the I2C interface is operating, this port should be set to the input level
(DDRA: bit7 = 0).
L
PB0,
PB1 to PB5
These are general-purpose I/O ports.
These pins are also the external interrupt input pins. IRQ0, 1 are en-
abled for both rising and falling edge detection, and therefore cannot
be used for recovery from STOP status for MB90573. However, IRQ0,
1 can be used for recovery from STOP status for MB90V570A,
MB90F574A and MB90574C.
72,
75 to 79
E
E
IRQ0,
IRQ1 to IRQ5
PB6
This is a general purpose I/O port.
This is also the A/D converter external trigger input pin. While the A/D
converter is in input operation, this input signal is in continuous use,
and therefore the output function should only be used when needed.
80
ADTG
81
PB7
E
E
This is a general purpose I/O port.
These are general purpose I/O ports.
82 to 85
PC0 to PC3
Power
supply
8,54,94
VCC
These are power supply (5V) input pins.
33,63,
91,119
Power
supply
VSS
These are power supply (0V) input pins.
42
AVCC
AVRH
H
This is the analog macro (D/A, A/D etc.) Vcc power supply input pin.
This is the A/D converter Vref+ input pin. The input voltage should not
exceed Vcc.
43
J
This is the A/D converter Vref- input pin. The input voltage should not
less than Vss.
44
45
38
AVRL
AVSS
DVCC
H
H
H
This is the analog macro (D/A, A/D etc.) Vss power supply input pin.
This is the D/A converter Vref input pin. The input voltage should not
exceed Vcc.
This is the D/A converter GND power supply pin. It should be set to
Vss equivalent potential.
39
DVSS
H
*1 : FPT-120P-M24
*2 : FPT-120P-M13, FPT-120P-M21
12
DS07-13701-9E
MB90570A/570C Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Oscillator circuit
Oscillator recovery resistance for high
speed = approx. 1 MΩ
X1
X0
A
Standby control signal
• Oscillator circuit
X1A
Oscillator recovery resistance for low
speed = approx. 10 MΩ
X0A
B
Standby control signal
• Hysteresis input pin
Resistance value = approx. 50 kΩ (typ.)
R
Hysteresis input
C
• CMOS hysteresis input pin with input
pull-up control
• CMOS level output.
• CMOS hysteresis input
(Includes input shut down standby
control function)
• Pull-up resistance value =
approx. 50 kΩ(typ.)
IOL = 4mA
VCC
Selective signal either
with a pull-up resistor or
without it.
VCC
P-ch
P-ch
D
N-ch
R
Hysteresis input
Standby control for input interruption
IOL = 4 mA
(Continued)
DS07-13701-9E
13
MB90570A/570C Series
Type
Circuit
Remarks
• CMOS hysteresis input/output pin.
• CMOS level output
VCC
• CMOS hysteresis input
(Includes input shut down standby
control function)
P-ch
E
N-ch
IOL = 4 mA
R
Hysteresis input
Standby control for input interruption
IOL = 4 mA
• CMOS hysteresis input/output pin.
• CMOS level output
VCC
• CMOS hysteresis input
(Includes input shut down standby
control function)
P-ch
F
N-ch
IOL = 10 mA (Large current port)
R
Hysteresis input
Standby control for input interruption
IOL = 10 mA
• C pin output
VCC
(capacitance connector pin).
P-ch
N-ch
G
• Analog power supply protector
circuit.
VCC
P-ch
H
AVP
N-ch
• CMOS hysteresis input/output
• Analog output/CMOS output
dual-function pin (CMOS output is not
available during analog output.)
(Analog output priority: DAE = 1)
• Includes input shut down standby
control function.
VCC
P-ch
N-ch
I
R
Hysteresis input
IOL = 4mA
Standby control for input interruption
DAO
IOL = 4 mA
(Continued)
14
DS07-13701-9E
MB90570A/570C Series
(Continued)
Type
Circuit
Remarks
• A/D converter ref+ power supply input
pin(AVRH), with power supply
protector circuit.
VCC
P-ch
ANE
AVR
ANE
P-ch
N-ch
J
N-ch
• CMOS hysteresis input /analog input
dual-function pin.
VCC
P-ch
• CMOS output
• Includes input shut down function at
input shut down standby.
N-ch
K
R
Hysteresis input
Standby control for input interruption
Analog input
IOL = 4 mA
• Hysteresis input
VCC
N-ch
N-ch
• N-ch open-drain output
• Includes input shut down standby
control function.
IOL= 4mA
L
R
Hysteresis input
Standby control for input interruption
IOL = 4 mA
DS07-13701-9E
15
MB90570A/570C Series
■ HANDLING DEVICES
1. Preventing Latchup
CMOS ICs may cause latchup in the following situations:
• When a voltage higher than Vcc or lower than Vss is applied to input or output pins.
• When a voltage exceeding the rating is applied between Vcc and Vss.
• When AVcc power is supplied prior to the Vcc voltage.
In turning on/turning off the analog power supply, make sure the analog power voltage (AVCC, AVRH, DVCC)and
analog input voltages not exceed the digital voltage (VCC).
2. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefor they must be tied to VCC or Ground through resistors. In this case those resistors should be
more than 2 kΩ.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3. Notes on Using External Clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected.
• Using external clock
MB90570A/570C series
X0
X1
Open
4. Unused Sub Clock Mode
If sub clock modes are not used, the oscillator should be connected to the X01A pin and X1A pin
5. Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to
avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to
lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise
in the ground level, and to conform to the total current rating.
Make sure to connect VCC and VSS pins via lowest impedance to power lines.
16
DS07-13701-9E
MB90570A/570C Series
It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pin near the device.
• Using power supply pins
VCC
VSS
VCC
VSS
VSS
VCC
MB90570A/570C
series
VCC
VSS
VCC
VSS
6. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand
area for stabilizing the operation.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL,
DVCC,DVSS) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simulta-
neously is acceptable).
8. Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = DVCC = VSS.
9. N.C. Pins
The N.C. (internally connected) pins must be opened for use.
10. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
or more µs (0.2 V to 2.7 V).
11. Indeterminate outputs from ports 0 and 1
The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during
a power-on reset) after the power is turned on. (MB90573, MB90V570A)
DS07-13701-9E
17
MB90570A/570C Series
The series without built-in step-down circuit have no oscillation setting time of step-down circuit, so outputs
should not become indeterminate. (MB90F574A,MB90574C)
Timing chart of indeterminate outputs from ports 0 and 1
Oscillation setting time *2
Step-down circuit setting time *1
VCC (power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operating clock A) signal
KB (internal operating clock B) signal
Period of indeterminate
PORT (port output) signal
*1: Step-down circuit setting time217/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms)
*2: Oscillation setting time
218/oscillation clock frequency (oscillation clock frequency of 16 MHz: 16.38 ms)
12. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. Turn on the power again
to initialize these registers.
13. Return from standby state
If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may
fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal
state.
14. Precautions for Use of ’DIV A, Ri,’ and ’DIVW A, Ri’ Instructions
The signed multiplication-division instructions ’DIV A, Ri,’ and ’DIVW A, RWi’ should be used when the corre-
sponding bank registers (DTB, ADB, USB, SSB) are set to value ’00h.’ If the corresponding bank registers (DTB,
ADB, USB, SSB) are set to a value other than ’00h,’ then the remainder obtained after the execution of the
instruction will not be placed in the instruction operand register.
15. Precautions for Use of REALOS
Extended intelligent I/O service (EI2OS) cannot be used, when REALOS is used.
16. Caution on PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
18
DS07-13701-9E
MB90570A/570C Series
■ BLOCK DIAGRAM
Interrupt controller
3
F2MC–16LX
CPU
P70 to P72
Port 7
Main clock
Sub clock
2
P73/DA0
P74/DA1
X0, X1
X0A,
RST
HS
8-bit
D/A
converter
× 2 ch.
Clock control
block
(including timebase
timer)
DVCC
DVSS
8
8
P00/AD00 to P07/
Port 0, 1, 2
16
Port 9
P10/AD08 to P17/AD15
P20/A16 to P27/A23
8
8
8
Chip select
output
P90/CS0 to P97/CS7
8
P30/ALE
P31/RD
Port A
2
PA1/BIN0
External bus
interface
P32/WRL
P33/WRH
P34/HRQ
PA2/ZIN0
6
PA3/AIN1/IRQ7
PA4/BIN1
6
8/16-bit up/down
counter/timer
P35/
PA5/ZIN1
P36/RDY
P37/CLK
Port 3
Port 4
2
PA6/SDA
PA7/SCL
I2C bus
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN1
P44/SOT1
P45/SCK1
P46/
PA0/AIN0/IRQ6
DTP/
external
interrupt
circuit
2
UART0
(SCI),
UART1
(SCI)
6
6
2
PB0/IRQ0 to
PB5/IRQ5
2
PB7
Port B
8/16-bit
PPG timer
ch.0
P47/PPG1
PB6/ADTG
AVR
AVR
AVCC
AVSS
P80/AN0 to
P87/AN7
P50/SIN2
P51/SOT2
P52/SCK2
Port 5
2
8/10-bit
A/D converter
× 8 ch.
8
8
2
P53/SIN3
P54/SOT3
P55/SCK3
SIO × 2 ch
2
Port 8
Port C
P56/IN0
P57/IN1
4
2
PC0 to PC3
Input capture
16-bit free run timer
4
4
Output
compare
(OCU)
RAM
ROM
P64/OUT0 to P67/OUT3
P60/SIN4
P61/SOT4
P62/SCK4
SIO × 1 ch.
Port 6
Clock output
P63/CKOT
Other pins
P00 to P07 (8 ports): Provided with a register optional input pull-up resistor
P10 to P17 (8 ports): Provided with a register optional input pull-up resistor
P40 to P47 (8 ports): Heavy-current (IOL = 10 mA) port
MD0 to MD2,
C, VCC, VSS
P60 to P67 (8 ports): Provided with a register optional input pull-up resistor
DS07-13701-9E
19
MB90570A/570C Series
■ MEMORY MAP
Internal ROM
Single chip mode
A mirror function is
supported.
external bus mode
A mirror function
is supported.
External ROM
external bus mode
FFFFFFH
ROM area
Address #1
ROM area
FC0000H
010000H
ROM area
(image of
bank FF)
ROM area
(image of
bank FF)
Address #2
004000H
Address #3
Register
RAM
Register
RAM
Register
RAM
000100H
0000C0H
000000H
Peripheral
Peripheral
Peripheral
Part number
MB90573
Address #1*
FE0000H
Address #2*
004000H
Address #3*
001800H
002900H
002900H
MB90574C
MB90F574A
FC0000H
004000H
FC0000H
004000H
: Internal access memory
: External access memory
: Inhibited area
*: Addresses #1, #2 and #3 are unique to the product type.
Note : The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C
compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same
address, enabling reference of the table on the ROM without stating “far”.
For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are
accessed actually. Since the ROM area of the FF bank exceeds 48 kbytes, the whole area cannot be reflected
in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image
for 00400H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H
to FFFFFFH.
20
DS07-13701-9E
MB90570A/570C Series
■ F2MC-16LX CPU PROGRAMMING MODEL
• Dedicated registers
:Accumulator (A)
AH
AL
Dual 16-bit register used for storing results of calculation etc. The two
16-bit registers can be combined to be used as a 32-bit register.
:User stack pointer (USP)
The 16-bit pointer indicating a user stack address.
USP
SSP
PS
:System stack pointer (SSP)
The 16-bit pointer indicating the status of the system stack address.
:Processor status (PS)
The 16-bit register indicating the system status.
:Program counter (PC)
The 16-bit register indicating storing location of the current instruction
code.
PC
:Direct page register (DPR)
DPR
The 8-bit register indicating bit 8 through 15 of the operand address
in the short direct addressing mode.
:Program bank register (PCB)
The 8-bit register indicating the program space.
PCB
DTB
USB
SSB
:Data bank register (DTB)
The 8-bit register indicating the data space.
:User stack bank register (USB)
The 8-bit register indicating the user stack space.
:System stack bank register (SSB)
The 8-bit register indicating the system stack space.
:Additional data bank register (ADB)
The 8-bit register indicating the additional data space.
ADB
8-bit
16-bit
32-bit
DS07-13701-9E
21
MB90570A/570C Series
• General-purpose registers
Maximum of 32 banks
RW7
R7
R6
RL3
RL2
RL1
RL0
RW6
RW5
RW4
R5
R3
R4
R2
R1
R0
RW3
RW2
RW1
RW0
000180H + (RP × 10H)
16-bit
• Processor status (PS)
ILM
RP
CCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PS
ILM2 ILM1 ILM0 B4
B3
0
B2
0
B1
0
B0
0
—
—
I
S
1
T
X
N
X
Z
X
V
X
C
Initial value
0
0
0
0
0
X
—: Reserved
X: Undefined
22
DS07-13701-9E
MB90570A/570C Series
■ I/O MAP
Abbreviated
Read/
write
Address
register
name
Register name
Port 0 data register
Resource name
Initial value
000000H
000001H
000002H
000003H
000004H
000005H
000006H
000007H
000008H
000009H
00000AH
00000BH
00000CH
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
PDRB
PDRC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port C
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
Port 5 data register
Port 6 data register
Port 7 data register
Port 8 data register
Port 9 data register
Port A data register
Port B data register
Port C data register
00000DH
to
(Disabled)
00000FH
000010H
000011H
000012H
000013H
000014H
000015H
000016H
000017H
000018H
000019H
00001AH
00001BH
00001CH
00001DH
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
DDRA
DDRB
DDRC
ODR4
Port 0 direction register
Port 1 direction register
Port 2 direction register
Port 3 direction register
Port 4 direction register
Port 5 direction register
Port 6 direction register
Port 7 direction register
Port 8 direction register
Port 9 direction register
Port A direction register
Port B direction register
Port C direction register
Port 4 output pin register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port C
Port 4
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
– – – 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
Port 8,
8/10-bit
00001EH
ADER
Analog input enable register
R/W
1 1 1 1 1 1 1 1B
A/D converter
00001FH
000020H
000021H
(Disabled)
SMR0
SCR0
Serial mode register 0
Serial control register 0
R/W
R/W
0 0 0 0 0 0 0 0B
0 0 0 0 0 1 0 0B
UART0
(SCI)
(Continued)
DS07-13701-9E
23
MB90570A/570C Series
Abbreviated
Read/
write
Resource
name
Address
register
name
Register name
Initial value
SIDR0/
SODR0
Serial input data register 0/
serial output data register 0
000022H
R/W
X X X X X X X XB
UART0
(SCI)
000023H
000024H
000025H
SSR0
SMR1
SCR1
Serial status register 0
Serial mode register 1
Serial control register 1
R/W
R/W
R/W
0 0 0 0 1 – 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 1 0 0B
UART1
(SCI)
SIDR1/
SODR1
Serial input data register 1/
serial output data register 1
000026H
000027H
R/W
R/W
X X X X X X X XB
0 0 0 0 1 – 0 0B
SSR1
Serial status register 1
Communica-
tions
prescaler
register 0
Communications prescaler control
register 0
000028H
000029H
00002AH
CDCR0
R/W
0 – – – 1 1 1 1B
(Disabled)
Communica-
tions
prescaler
register 0
Communications prescaler control
register 1
CDCR1
R/W
0 – – – 1 1 1 1B
00002BH
to
(Disabled)
00002FH
000030H
000031H
000032H
000033H
000034H
000035H
ENIR
EIRR
DTP/interrupt enable register
DTP/interrupt factor register
R/W
R/W
0 0 0 0 0 0 0 0B
X X X X X X X XB
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
DTP/external
interrupt circuit
ELVR
Request level setting register
R/W
(Disabled)
A/D control status register lower
digits
000036H
000037H
ADCS1
ADCS2
R/W
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
A/D control status register upper
digits
8/10-bit A/D
converter
R/W or W
000038H
000039H
00003AH
00003BH
00003CH
00003DH
ADCR1
ADCR2
DADR0
DADR1
DACR0
DACR1
A/D data register lower digits
A/D data register upper digits
D/A converter data register ch.0
D/A converter data register ch.1
D/A control register 0
R
X X X X X X X XB
0 0 0 0 1 – X XB
X X X X X X X XB
X X X X X X X XB
– – – – – – – 0B
– – – – – – – 0B
W
R/W
R/W
R/W
R/W
8-bit D/A
converter
D/A control register 1
Clock monitor
function
00003EH
CLKR
Clock output enable register
R/W
– – – – 0 0 0 0B
00003FH
000040H
000041H
(Disabled)
PRLL0
PRLH0
PPG0 reload register L ch.0
PPG0 reload register H ch.0
R/W
R/W
X X X X X X X XB
X X X X X X X XB
(Continued)
8/16-bit PPG
timer 0
24
DS07-13701-9E
MB90570A/570C Series
Abbreviated
register
name
Read/
write
Address
Register name
Resource name
Initial value
000042H
000043H
PRLL1
PRLH1
PPG1 reload register L ch.1
PPG1 reload register H ch.1
R/W
R/W
X X X X X X X XB
X X X X X X X XB
8/16-bit PPG
timer 1
PPG0 operating mode control
register ch.0
8/16-bit PPG
timer 0
000044H
000045H
PPGC0
PPGC1
PPGOE
R/W
R/W
R/W
0 X 0 0 0 X X 1B
0 X 0 0 0 0 0 1B
0 0 0 0 0 0 X XB
PPG1 operating mode control
register ch.1
8/16-bit PPG
timer 1
PPG0 and 1 output control registers
ch.0 and ch.1
8/16-bit PPG
timer 0, 1
000046H
000047H
000048H
(Disabled)
Serial mode control lower status
register 0
SMCSL0
R/W
– – – – 0 0 0 0B
Extended I/O
serial interface 0
Serial mode control upper status
register 0
000049H
SMCSH0
SDR0
R/W
R/W
0 0 0 0 0 0 1 0B
X X X X X X X XB
00004AH
00004BH
Serial data register 0
(Disabled)
Serial mode control lower status
register 1
00004CH
00004DH
SMCSL1
R/W
– – – – 0 0 0 0B
Extended I/O
serial interface 1
Serial mode control upper status
register 1
SMCSH1
SDR1
R/W
R/W
0 0 0 0 0 0 1 0B
X X X X X X X XB
00004EH
00004FH
000050H
000051H
000052H
000053H
000054H
000055H
000056H
000057H
000058H
000059H
00005AH
00005BH
00005CH
00005DH
00005EH
00005FH
Serial data register 1
(Disabled)
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
0 0 0 0 0 0 0 0B
IPCP0
ICU data register ch.0
R
16-bit I/O timer
(input capture
(ICU) section)
IPCP1
ICS01
ICU data register ch.1
R
ICU control status register
R/W
(Disabled)
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
16-bit I/O timer
(16-bit free run
timer section)
TCDT
TCCS
Free run timer data register
R/W
R/W
Free run timer control status register
(Disabled)
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
(Continued)
OCCP0
OCCP1
OCCP2
OCU compare register ch.0
OCU compare register ch.1
OCU compare register ch.2
R/W
R/W
R/W
16-bit I/O timer
(output compare
(OCU) section)
DS07-13701-9E
25
MB90570A/570C Series
Abbreviated
Read/
write
Address
register
name
Register name
Resource name
Initial value
000060H
000061H
000062H
000063H
000064H
000065H
000066H
000067H
000068H
000069H
00006AH
00006BH
00006CH
00006DH
00006EH
X X X X X X X XB
X X X X X X X XB
0 0 0 0 – – 0 0B
– – – 0 0 0 0 0B
0 0 0 0 – – 0 0B
– – – 0 0 0 0 0B
OCCP3
OCU compare register ch.3
R/W
16-bit I/O timer
(output compare
(OCU) section)
OCS0
OCS1
OCS2
OCS3
OCU control status register ch.0
OCU control status register ch.1
OCU control status register ch.2
OCU control status register ch.3
R/W
R/W
R/W
R/W
(Disabled)
IBSR
IBCR
ICCR
IADR
IDAR
I2C bus status register
I2C bus control register
I2C bus clock control register
I2C bus address register
I2C bus data register
R
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
– – 0 X X X X XB
– X X X X X X XB
X X X X X X X XB
R/W
R/W
R/W
R/W
I2C interface
(Disabled)
ROM mirroring
function
selection module
ROM mirroring function selection
register
00006FH
ROMM
W
– – – – – – – 1B
000070H
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
UDCR0
UDCR1
RCR0
Up/down count register 0
Up/down count register 1
Reload compare register 0
Reload compare register 1
Counter status register 0
R
R
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
8/16-bit up/down
counter/timer
W
RCR1
W
CSR0
R/W
(Reserved area)*3
CCRL0
CCRH0
CSR1
– 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
Counter control register 0
Counter status register 1
R/W
8/16-bit up/down
counter/timer
R/W
(Reserved area)*3
CCRL1
CCRH1
– 0 0 0 0 0 0 0B
– 0 0 0 0 0 0 0B
8/16-bit up/down
counter/timer
Counter control register 1
R/W
Serial mode control lower status
register 2
00007CH
00007DH
SMCSL2
R/W
– – – – 0 0 0 0B
Extended I/O
serial interface 2
Serial mode control higher status
register 2
SMCSH2
SDR2
R/W
R/W
0 0 0 0 0 0 1 0B
X X X X X X X XB
00007EH
00007FH
Serial data register 2
(Disabled)
(Continued)
26
DS07-13701-9E
MB90570A/570C Series
Abbreviated
register
name
Read/
write
Address
Register name
Resource name
Initial value
000080H
000081H
000082H
000083H
000084H
000085H
000086H
CSCR0
CSCR1
CSCR2
CSCR3
CSCR4
CSCR5
CSCR6
Chip selection control register 0
Chip selection control register 1
Chip selection control register 2
Chip selection control register 3
Chip selection control register 4
Chip selection control register 5
Chip selection control register 6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
– – – – 0 0 0 0B
– – – – 0 0 0 0B
– – – – 0 0 0 0B
– – – – 0 0 0 0B
– – – – 0 0 0 0B
– – – – 0 0 0 0B
– – – – 0 0 0 0B
Chip select
output
000087H
to
(Disabled)
00008BH
Port 0 input pull-up resistor setup
register
00008CH
00008DH
00008EH
RDR0
RDR1
RDR6
R/W
R/W
R/W
Port 0
Port 1
Port 6
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
Port 1 input pull-up resistor setup
register
Port 6 input pull-up resistor setup
register
00008FH
to
(Disabled)
00009DH
Address match
detection
Program address detection control
status register
00009EH
00009FH
PACSR
DIRR
R/W
R/W
0 0 0 0 0 0 0 0B
– – – – – – – 0B
function
Delayed
interrupt
generation
module
Delayed interrupt factor generation/
cancellation register
Low-power consumption mode
control register
Low-power
consumption
(standby) mode
0000A0H
0000A1H
LPMCR
CKSCR
R/W
R/W
0 0 0 1 1 0 0 0B
1 1 1 1 1 1 0 0B
Clock select register
0000A2H
to
(Disabled)
0000A4H
Automatic ready function select
register
0000A5H
ARSR
W
0 0 1 1 – – 0 0B
External bus pin
0000A6H
0000A7H
0000A8H
0000A9H
0000AAH
HACR
ECSR
WDTC
TBTC
WTC
Upper address control register
Bus control signal select register
Watchdog timer control register
Timebase timer control register
Watch timer control register
W
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
X X X X X X X XB
1 – – 0 0 1 0 0B
1 X 0 0 0 0 0 0B
(Continued)
W
R/W
R/W
R/W
Watchdog timer
Timebase timer
Watch timer
DS07-13701-9E
27
MB90570A/570C Series
(Continued)
Abbreviated
Read/
write
Address
register
name
Register name
Resource name
Initial value
0000ABH
to
(Disabled)
0000ADH
0000AEH
0000AFH
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
0000BDH
0000BEH
0000BFH
FMCS
Flash control register
R/W
Flash interface
0 0 0 X 0 X X 0B
(Disabled)
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
Interrupt control register 00
Interrupt control register 01
Interrupt control register 02
Interrupt control register 03
Interrupt control register 04
Interrupt control register 05
Interrupt control register 06
Interrupt control register 07
Interrupt control register 08
Interrupt control register 09
Interrupt control register 10
Interrupt control register 11
Interrupt control register 12
Interrupt control register 13
Interrupt control register 14
Interrupt control register 15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
Interrupt
controller
0000C0H
to
0000FFH
(External area)*1
(RAM area)*2
000100H
to
000###H
000###H
to
(Reserved area)*3
001FEFH
001FF0H
001FF1H
001FF2H
001FF3H
001FF4H
001FF5H
Program address detection register 0
Program address detection register 1
Program address detection register 2
Program address detection register 3
Program address detection register 4
Program address detection register 5
R/W
R/W
R/W
R/W
R/W
R/W
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
X X X X X X X XB
PADR0
PADR1
Address match
detection
function
001FF6H
to
(Reserved area)
001FFFH
28
DS07-13701-9E
MB90570A/570C Series
Descriptions for read/write
R/W : Readable and writable
R
W
: Read only
: Write only
Descriptions for initial value
0
1
X
–
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is undefined.
: This bit is unused. The initial value is undefined.
*1 : This area is the only external access area having an address of 0000FFH or lower. An access operation to this
area is handled as that to external I/O area.
*2 : For details of the RAM area, see “■ MEMORY MAP”.
*3 : The reserved area is disabled because it is used in the system.
Notes : • For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an
initial value. Note that the values are different from reading results.
ForLPMCR/CKSCR/WDTC, there are caseswhereinitializationisperformedornotperformed, depending
on the types of the reset. However initial value for resets that initializes the value are listed.
• The addresses following 0000FFH are reserved. No external bus access signal is generated.
• Boundary ####H between the RAM area and the reserved area varies with the product model.
DS07-13701-9E
29
MB90570A/570C Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt vector
Number Address
Interrupt control register
EI2OS
support
Interrupt source
Priority
ICR
—
Address
Reset
×
×
×
# 08
# 09
# 10
# 11
# 12
# 13
# 14
# 15
# 16
# 17
# 18
# 19
# 20
# 21
# 22
# 23
# 24
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
—
—
—
High
INT9 instruction
—
Exception
—
8/10-bit A/D converter
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
Input capture 0 (ICU) include
DTP0 (external interrupt 0)
Input capture 1 (ICU) include
Output compare 0 (OCU) match
Output compare 1 (OCU) match
Output compare 2 (OCU) match
Output compare 3 (OCU) match
Extended I/O serial interface 0
16-bit free run timer
×
×
Extended I/O serial interface 1
Watch timer
Extended I/O serial interface 2
DTP1 (external interrupt 1)
DTP2/DTP3 (external interrupt 2/
external interrupt 3)
# 25
# 26
# 27
# 28
# 29
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
ICR07
ICR08
0000B7H
0000B8H
8/16-bit PPG timer 0 counter borrow
×
×
DTP4/DTP5 (external interrupt 4/
external interrupt 5)
8/16-bit PPG timer 1 counter borrow
8/16-bit up/down counter/timer 0
borrow/overflow/inversion
ICR09
0000B9H
8/16-bit up/down counter/timer 0
compare match
# 30
# 31
# 32
FFFF84H
FFFF80H
FFFF7CH
8/16-bit up/down counter/timer 1
borrow/overflow/inversion
0000BAH
0000BAH
ICR10
ICR11
8/16-bit up/down counter/timer 1
compare match
DTP6 (external interrupt 6)
Timebase timer
# 33
# 34
FFFF78H
FFFF74H
0000BBH
×
Low
(Continued)
30
DS07-13701-9E
MB90570A/570C Series
(Continued)
Interrupt source
Interrupt vector
Interrupt control register
EI2OS
Priority
support
Number
# 35
Address
FFFF70H
FFFF6CH
FFFF68H
ICR
Address
DTP7 (external interrupt 7)
I2C interface
High
ICR12
0000BCH
×
# 36
UART1 (SCI) reception complete
# 37
ICR13
ICR14
ICR15
0000BDH
0000BEH
0000BFH
UART1 (SCI) transmission
complete
# 38
# 39
# 40
# 41
# 42
FFFF64H
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
UART0 (SCI) reception complete
UART0 (SCI) transmission
complete
Flash memory
×
×
Delayed interrupt generation
module
Low
:Can be used
:Can not be used
:Can be used. With EI2OS stop function.
×
DS07-13701-9E
31
MB90570A/570C Series
■ PERIPHERALS
1. I/O Port
(1) Input/output Port
Port 0 through 4, 6, 8, A and B are general-purpose I/O ports having a combined function as an external bus
pin and a resource input. Port 0 to Port 3 have a general-purpose I/O ports function only in the single-chip mode.
• Operation as output port
The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.
Writing data to PDR register when the port is configured as output, the data is retained in the output latch in
the PDR and directly output to the pin.
The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR
register.
Note : When a read-modify-write instruction (e.g. bit set instruction) is performed to the port data register, the
destination bit of the operation is set to the specified value, not affecting the bits configured by the DDR
register for output, however, values of bits configured by the DDR register as inputs are changed because
input values to the pins are written into the output latch. To avoid this situation, configure the pins by the DDR
register as output after writing output data to the PDR register when configuring the bit used as input as
outputs.
• Operation as input port
The pin is configured as an input by setting the corresponding bit of the DDR register to “0”.
When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance
status.
When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs
are unaffected.
Reading the PDR register reads out the pin level (“0” or “1”).
32
DS07-13701-9E
MB90570A/570C Series
(2) Register Configuration
• Port 0 data register (PDR0)
. . . . . . . . . . . .
Address bit 15
000000H
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX
(PDR1)
B
P07
R/W
P06
R/W
P05
R/W
P04
R/W
P03
R/W
P02
R/W
P01
R/W
P00
R/W
• Port 1 data register (PDR1)
. . . . . . . . . . . .
(PDR0)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8 bit 7
P10
bit 0
Initial value
Address
000001H
B
XXXXXXXX
P17
R/W
P16
R/W
P15
R/W
P14
R/W
P13
R/W
P12
R/W
P11
R/W
R/W
• Port 2 data register (PDR2)
. . . . . . . . . . . .
Address bit 15
000002H
bit 8 bit 7
P27
bit 6
bit 5
bit 4
bit 3
bit 2
P22
R/W
bit 1
P21
R/W
bit 0
P20
R/W
Initial value
XXXXXXXX
(PDR3)
P26
R/W
P25
R/W
P24
R/W
P23
R/W
B
R/W
• Port 3 data register (PDR3)
. . . . . . . . . . . .
(PDR2)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8 bit 7
bit 0
Initial value
Address
000003H
B
XXXXXXXX
P37
R/W
P36
R/W
P35
R/W
P34
R/W
P33
R/W
P32
R/W
P31
R/W
P30
R/W
• Port 4 data register (PDR4)
. . . . . . . . . . . .
Address bit 15
000004H
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
P40
R/W
Initial value
XXXXXXXX
B
(PDR5)
P47
R/W
P46
R/W
P45
R/W
P44
R/W
P43
R/W
P42
R/W
P41
R/W
• Port 5 data register (PDR5)
. . . . . . . . . . . .
(PDR4)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8 bit 7
bit 0
Initial value
Address
000005H
B
XXXXXXXX
P57
R/W
P56
R/W
P55
R/W
P54
R/W
P53
R/W
P52
R/W
P51
R/W
P50
R/W
• Port 6 data register (PDR6)
. . . . . . . . . . . .
Address bit 15
000006H
bit 8 bit 7
P67
bit 6
bit 5
bit 4
bit 3
bit 2
P62
R/W
bit 1
P61
R/W
bit 0
P60
R/W
Initial value
XXXXXXXX
(PDR7)
P66
R/W
P65
R/W
P64
R/W
P63
R/W
B
R/W
• Port 7 data register (PDR7)
. . . . . . . . . . . .
(PDR6)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8 bit 7
P70
bit 0
Initial value
Address
000007H
B
—
—
—
—
—
P74
R/W
P73
R/W
P72
R/W
P71
R/W
- - - XXXXX
—
R/W
• Port 8 data register (PDR8)
. . . . . . . . . . . .
Address bit 15
000008H
bit 8 bit 7
P87
bit 6
bit 5
bit 4
bit 3
bit 2
P82
R/W
bit 1
P81
R/W
bit 0
P80
R/W
Initial value
XXXXXXXX
(PDR9)
P86
R/W
P85
R/W
P84
R/W
P83
R/W
B
R/W
(Continued)
DS07-13701-9E
33
MB90570A/570C Series
• Port 9 data register (PDR9)
. . . . . . . . . . . .
(PDR8)
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8 bit 7
bit 0
Initial value
000009H
B
XXXXXXXX
P97
R/W
P96
R/W
P95
R/W
P94
R/W
P93
R/W
P92
R/W
P91
R/W
P90
R/W
• Port A data register (PDRA)
. . . . . . . . . . . .
Address bit 15
00000AH
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PA0
Initial value
XXXXXXXX
B
(PDRB)
PA7
R/W
PA6
R/W
PA5
R/W
PA4
R/W
PA3
R/W
PA2
R/W
PA1
R/W
R/W
• Port B data register (PDRB)
. . . . . . . . . . . .
Address bit 15
00000BH
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX
(PDRA)
B
PB7
R/W
PB6
R/W
PB5
R/W
PB4
R/W
PB3
R/W
PB2
R/W
PB1
R/W
PB0
R/W
• Port C data register (PDRC)
. . . . . . . . . . . .
Address bit 15
00000CH
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX
(Disabled)
B
—
—
—
—
—
—
—
—
PC3
R/W
PC2
R/W
PC1
R/W
PC0
R/W
• Port 0 direction register (DDR0)
. . . . . . . . . . . .
Address bit 15
000010H
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
(DDR1)
B
D07
R/W
D06
R/W
D05
R/W
D04
R/W
D03
R/W
D02
R/W
D01
R/W
D00
R/W
00000000
• Port 1 direction register (DDR1)
. . . . . . . . . . . .
(DDR0)
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8 bit 7
bit 0
Initial value
000011H
B
00000000
D17
R/W
D16
R/W
D15
R/W
D14
R/W
D13
R/W
D12
R/W
D11
R/W
D10
R/W
• Port 2 direction register (DDR2)
. . . . . . . . . . . .
Address bit 15
000012H
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D20
R/W
Initial value
00000000
(DDR3)
B
D27
R/W
D26
R/W
D25
R/W
D24
R/W
D23
R/W
D22
R/W
D21
R/W
• Port 3 direction register (DDR3)
. . . . . . . . . . . .
(DDR2)
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8 bit 7
bit 0
Initial value
000013H
B
00000000
D37
R/W
D36
R/W
D35
R/W
D34
R/W
D33
R/W
D32
R/W
D31
R/W
D30
R/W
• Port 4 direction register (DDR4)
. . . . . . . . . . . .
Address bit 15
000014H
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D40
R/W
Initial value
00000000
(DDR5)
B
D47
R/W
D46
R/W
D45
R/W
D44
R/W
D43
R/W
D42
R/W
D41
R/W
(Continued)
34
DS07-13701-9E
MB90570A/570C Series
• Port 5 direction register (DDR5)
. . . . . . . . . . . .
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
D51
R/W
bit 8 bit 7
D50
bit 0
Initial value
000015H
B
00000000
D57
R/W
D56
R/W
D55
R/W
D54
R/W
D53
R/W
D52
R/W
(DDR4)
R/W
• Port 6 direction register (DDR6)
. . . . . . . . . . . .
Address bit 15
000016H
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000
B
(DDR7)
D67
R/W
D66
R/W
D65
R/W
D64
R/W
D63
R/W
D62
R/W
D61
R/W
D60
R/W
• Port 7 direction register (DDR7)
. . . . . . . . . . . .
(DDR6)
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8 bit 7
D70
bit 0
Initial value
000017H
B
- - - 00000
—
—
—
—
—
D74
R/W
D73
R/W
D72
R/W
D71
R/W
—
R/W
• Port 8 direction register (DDR8)
. . . . . . . . . . . .
Address bit 15
000018H
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D80
R/W
Initial value
00000000
(DDR9)
B
D87
R/W
D86
R/W
D85
R/W
D84
R/W
D83
R/W
D82
R/W
D81
R/W
• Port 9 direction register (DDR9)
. . . . . . . . . . . .
(DDR8)
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8 bit 7
D90
bit 0
Initial value
000019H
B
00000000
D97
R/W
D96
R/W
D95
R/W
D94
R/W
D93
R/W
D92
R/W
D91
R/W
R/W
• Port A direction register (DDRA)
. . . . . . . . . . . .
Address bit 15
00001AH
bit 8 bit 7
DA7
bit 6
bit 5
bit 4
bit 3
bit 2
DA2
R/W
bit 1
DA1
R/W
bit 0
DA0
Initial value
00000000
(DDRB)
DA6
R/W
DA5
R/W
DA4
R/W
DA3
R/W
B
R/W
R/W
• Port B direction register (DDRB)
. . . . . . . . . . . .
bit 15
bit 8 bit 7
DB7
bit 6
DB6
R/W
bit 5
DB5
R/W
bit 4
DB4
R/W
bit 3
DB3
R/W
bit 2
DB2
R/W
bit 1
DB1
R/W
bit 0
DB0
R/W
Address
00001BH
Initial value
00000000
(DDRA)
B
R/W
• Port C direction register (DDRC)
. . . . . . . . . . . .
Address bit 15
00001CH
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
(ODR4)
B
—
—
—
—
—
—
—
—
DC3
R/W
DC2
R/W
DC1
R/W
DC0
R/W
00000000
• Port 4 output pin register (ODR4)
. . . . . . . . . . . .
Address bit 15
00001DH
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000
(DDRC)
B
OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 0 input pull-up resistor setup register (RDR0)
. . . . . . . . . . . .
Address bit 15
00008CH
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000
(RDR1)
B
RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00
R/W R/W R/W R/W R/W R/W R/W R/W
(Continued)
DS07-13701-9E
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MB90570A/570C Series
(Continued)
• Port 1 input pull-up resistor setup register (RDR1)
. . . . . . . . . . . .
(RDR0)
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10
R/W R/W R/W R/W R/W R/W R/W R/W
bit 9
bit 8 bit 7
bit 0
Initial value
00008DH
B
00000000
• Port 6 input pull-up resistor setup register (RDR6)
. . . . . . . . . . . .
Address bit 15
00008EH
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000
(Disabled)
B
RD67 RD66 RD65 RD64 RD63 RD62 RD61 RD60
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Analog input enable register (ADER)
. . . . . . . . . . . .
bit 15
bit 8 bit 7
bit 6
ADE6
R/W
bit 5
ADE5
R/W
bit 4
bit 3
bit 2
ADE2
R/W
bit 1
ADE1
R/W
bit 0
Address
00001EH
Initial value
ADE0
B
(Disabled)
11111111
ADE4 ADE3
R/W R/W
ADE7
R/W
R/W
R/W:Readable and writable
—:Reserved
X:Undefined
36
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MB90570A/570C Series
(3) Block Diagram
• Input/output port
PDR (port data register)
PDR read
Output latch
P-ch
PDR write
Pin
DDR (port direction register)
N-ch
Direction latch
DDR write
Standby control (SPL=1)
DDR read
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
• Output pin register (ODR)
To resource input
From resource output
Resource output enable
PDR (port data register)
PDR read
Output latch
P-ch
N-ch
PDR write
Pin
DDR (port direction register)
Direction latch
DDR write
Standby control
(SPL=1)
DDR read
ODR (output pin register)
ODR latch
ODR write
ODR read
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
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MB90570A/570C Series
• Input pull-up resistor setup register (RDR)
To resource input
PDR (port data register)
Pull-up resistor
About 50 kΩ
PDR read
(5.0 V)
Output latch
PDR write
P-ch
N-ch
P-ch
Pin
DDR (port direction register)
Direction latch
DDR write
Standby control
(SPL=1)
DDR read
RDR latch
RDR write
RDR
(input pull-up resistor setup register)
RDR read
Standby control: Stop, timebase timer mode and SPL=1
• Analog input enable register (ADER)
ADER (analog input enable register)
ADER read
ADER latch
To analog input
ADER write
PDR (port data register)
RMW
(read-modify-write
type instruction)
PDR read
Output latch
PDR write
P-ch
N-ch
Pin
DDR (port direction register)
Direction latch
DDR write
Standby control
(SPL=1)
DDR read
Standby control: Stop, timebase timer mode and SPL=1
38
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2. Timebase Timer
The timebase timer is a 18-bit free run counter (timebase counter) for counting up in synchronization to the
internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from
four types of 212/HCLK, 214/HCLK, 216/HCLK, and 219/HCLK.
The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation
stabilization time or the watchdog timer etc.
(1) Register Configuration
• Timebase timer control register (TBTC)
. . . . . . . . . . . .
Address
0000A9H
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8 bit 7
TBIE TBOF TBR TBC1 TBC0
R/W R/W R/W R/W
bit 0
Initial value
1--00100B
(WDTC)
—
—
—
—
RESV
—
W
R/W:Readable and writable
W:Write only
—:Unused
RESV: Reserved bit
(2) Block Diagram
To watchdog timer
To 8/16-bit PPG timer
Timebase timer counter
× 21 × 22 × 23
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
. . . . . .
Divided-by-2
of HCLK
OF
OF
OF
OF
To oscillation stabilization
time selector of clock control block
Power-on reset
Counter
clear circuit
Interval
timer selector
Start stop mode
CKSCR: MCS = 1→0*1
Set TBOF
Clear TBOF
Timebase timer control register
(TBTC)
RESV
—
—
TBIE TBOF TBR TBC1 TBC0
Timebase timer
interrupt signal
#34*2
OF: Overflow
HCLK: Oscillation clock
*1: Switch machine clock from oscillation clock to PLL clock
*2: Interrupt signal
DS07-13701-9E
39
MB90570A/570C Series
3. Watchdog Timer
The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when
the counter is not cleared for a preset period of time.
(1) Register Configuration
• Watchdog timer control register (WDTC)
. . . . . . . . . . . .
(TBTC)
Address bit 15
0000A8H
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
WT1
W
bit 0
WT0
W
Initial value
B
PONR STBR WRST ERST SRST WTE
XXXXXXXX
R
R
R
R
R
W
R:Read only
W:Write only
X:Indeterminate
(2) Block Diagram
Watchdog timer control register (WDTC)
PONR STBR WRST ERST SRST WTE WT1 WT0
2
Watchdog timer
CLR and start
Overflow
CLR
Watchdog timer
reset generation
circuit
Start sleep mode
Start hold status
Start stop mode
Counter clear
control circuit
Count clock
selector
2-bit
counter
To internal reset
generation circuit
CLR
4
Clear
(Timebase timer counter)
. . .
Divided-by-2
of HCLK
× 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
× 28
× 21 × 22
HCLK: Oscillation clock
40
DS07-13701-9E
MB90570A/570C Series
4. 8/16-bit PPG Timer
The 8/16-bit PPG timer is a 2-CH reload timer module for outputting pulse having given frequencies/duty ratios.
The two modules performs the following operation by combining functions.
• 8-bit PPG output 2-CH independent operation mode
This is a mode for operating independent 2-CH 8-bit PPG timer, in which PPG0 and PPG1 pins correspond
to outputs from PPG0 and PPG1 respectively.
• 16-bit PPG timer output operation mode
In this mode, PPG0 and PPG1 are combined to be operated as a 1-CH 8/16-bit PPG timer operating as a 16-
bit timer. Because PPG0 and PPG1 outputs are reversed by an underflow from PPG1 outputting the same
output pulses from PPG0 and PPG1 pins.
• 8 + 8-bit PPG timer output operation mode
In this mode, PPG0 is operated as an 8-bit communications prescaler, in which an underflow output of PPG0
is used as a clock source for PPG1. A toggle output of PPG0 and PPG output of PPG1 are output from PPG0
and PPG1 respectively.
• PPG output operation
A pulse wave with any period/duty ratio is output. The module can also be used as a D/A converter with an
external add-on circuit.
DS07-13701-9E
41
MB90570A/570C Series
(1) Register Configuration
• PPG0 operating mode control register ch.0 (PPGC0)
. . . . . . . . . . . .
Address bit 15
000044H
bit 8 bit 7
PEN0
bit 6
—
bit 5
PE00 PIE0 PUF0
R/W R/W R/W
bit 4
bit 3
bit 2
—
bit 1
—
bit 0
RESV
—
Initial value
0X000XX1
(PPGC1)
B
R/W
—
—
—
• PPG1 operating mode control register ch.1 (PPGC1)
. . . . . . . . . . . .
(PPGC0)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
MD0 RESV
R/W R/W
bit 8 bit 7
bit 0
Address
000045H
Initial value
B
0X000001
PEN1
R/W
—
PEI0
R/W
PIE1 PUF1 MD1
R/W R/W R/W
R/W
• PPG0, 1 output control register ch.0, ch.1(PPGOE)
. . . . . . . . . . . .
Address bit 15
000046H
bit 8 bit 7
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
R/W R/W R/W R/W R/W R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
—
bit 0
Initial value
000000XX
(Disabled)
—
B
—
—
• PPG0 reload register H ch.0 (PRLH0)
. . . . . . . . . . . .
(PRLL0)
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8 bit 7
R/W
bit 0
bit 0
Initial value
000041H
B
XXXXXXXX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• PPG1 reload register H ch.1 (PRLH1)
. . . . . . . . . . . .
(PRLL1)
Address
000043H
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
R/W
bit 8 bit 7
R/W
Initial value
B
XXXXXXXX
R/W
R/W
R/W
R/W
R/W
R/W
• PPG0 reload register L ch.0 (PRLL0)
Address
000040H
. . . . . . . . . . . .
(PRLH0)
bit 15
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
B
XXXXXXXX
R/W
R/W
bit 6
R/W
bit 5
R/W
bit 4
R/W
bit 3
R/W
bit 2
R/W
bit 1
R/W
• PPG1 reload register L ch.1 (PRLL1)
Address
000042H
. . . . . . . . . . . .
bit 15
bit 8 bit 7
bit 0
R/W
Initial value
B
XXXXXXXX
(PRLH1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W:Readable and writable
—:Reserved
X:Undefined
RESV: Reserved bit
42
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MB90570A/570C Series
(2) Block Diagram
• Block diagram of 8/16-bit PPG timer (ch.0)
Data bus for “H” digits
Data bus for “L” digits
PPG0 output
PPG0 reload
register
PPG0 operating mode
control register
ch.0 (PPGOE0)
control register ch.0 (PPGC0)
PEN0
—
PE00 PIE0 PUF0
—
—
RESV PCM2 PCM1 PCM0
PRLH0
PRLL0
R
Temporary buffer
(PRLBH0)
Interrupt request
#26*
S
Q
2
Mode control signal
Select signal
Reload register
(L/H selector)
PPG1 underflow
PPG0 underflow
(to PPG1)
Count value
Re-load
Clear
Pulse selector
Underflow
Down counter
(PCNT0)
CLK
PPG0
Pin
output latch
Reverse
P46/PPG0
PPG output
control circuit
Timebase timer output (512/HCLK)
Peripheral clock (16/φ)
Peripheral clock (8/φ)
Count
clock
selector
Peripheral clock (4/φ)
3
Peripheral clock (2/φ)
Peripheral clock (1/φ)
Select signal
*:Interrupt number
HCLK:Oscillation clock
φ:Machine clock frequency
DS07-13701-9E
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MB90570A/570C Series
• Block diagram of 8/16-bit PPG timer (ch.1)
Data bus for “H” digits
Data bus for “L” digits
PPG1 output control
register ch.1 (PPGOE1)
PPG1 reload
register
PPG1 operating mode
control register ch.1 (PPGC1)
PCS1 PCS0
PCS2
RESV
PEI0 PIE1 PUF1 MD1 MD0
PEN1
—
PRLL1
PRLH1
Operating mode
control signal
2
Temporary buffer
(PRLBH1)
R
Interrupt request
#28*
Q
S
Reload selector
(L/H selector)
Select signal
Count value
Re-load
Clear
Underflow
PPG1
output latch
Down counter
(PCNT1)
Pin
Reverse
P47/PPG1
CLK
PPG1 underflow
(to PPG0)
PPG output control circuit
MD0
PPG0 underflow
Timebase timer output (512/HCLK)
Peripheral clock (16/φ)
Peripheral clock (8/φ)
Peripheral clock (4/φ)
Peripheral clock (2/φ)
Peripheral clock (1/φ)
Count clock selector
Select signal
*:Interrupt number
HCLK:Oscillation clock
φ:Machine clock frequency
44
DS07-13701-9E
MB90570A/570C Series
5. 16-bit I/O timer
The 16-bit I/O timer module consists of one 16-bit free run timer, two input capture circuits, and four output
comparators. This module allows two independent waveforms to be output on the basis of the 16-bit free run
timer. Input pulse width and external clock periods can, therefore, be measured.
• Block Diagram
Internal data bus
16-bit
free run timer
Dedicated
bus
Dedicated
bus
Input capture
Output compare
DS07-13701-9E
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MB90570A/570C Series
(1) 16-bit free run Timer
The 16-bit free run timer consists of a 16-bit up counter, a control register, and a communications prescaler
register. The value output from the timer counter is used as basic timer (base timer) for input capture (ICU) and
output compare (OCU).
• A counter operation clock can be selected from four internal clocks (φ/4, φ/16, φ/32 and φ/64).
• An interrupt can be generated by overflow of counter value or compare match with OCU compare register 0.
(Compare match requires mode setup.)
• The counter value can be initialized to “0000H” by a reset, software clear or compare match with OCU compare
register 0.
• Register Configuration
• free run timer data register (TCDT)
Address
bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Initial value
00000000B
000056H
000057H
T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
• free run timer control status register (TCCS)
. . . . . . . . . . . . .
bit 15
bit 8 bit 7
RESV
bit 6
IVF
bit 5
IVFE STOP MODE CLR CLK1 CLK0
R/W R/W R/W R/W R/W R/W
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000B
Address
000058H
(Disabled)
R/W
R/W
R/W: Readable and writable
RESV: Reserved bit
• Block Diagram
Count value output
to ICU and OCU
free run timer data register (TCDT)
16-bit counter
OF
CLK
STOP
CLR
Communications
prescaler register
φ
OCU compare register
ch.0 match signal
2
free run timer
control status register
(TCCS)
RESV IVF IVFE STOP MODE CLR CLK1 CLK0
16-bit free run timer
interrupt request
#20*
*:Interrupt number
φ:Machine clock frequency
OF:Overflow
46
DS07-13701-9E
MB90570A/570C Series
(2) Input Capture (ICU)
The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of
current counter value of the 16-bit free run timer to the ICU data register (IPCP) upon an input of a trigger edge
to the external pin.
There are four sets (four channels) of the input capture external pins and ICU data registers, enabling measure-
ments of maximum of four events.
• The input capture has two sets of external input pins (IN0, IN1) and ICU registers (IPCP), enabling measure-
ments of maximum of four events.
• A trigger edge direction can be selected from rising/falling/both edges.
• The input capture can be set to generate an interrupt request at the storage timing of the counter value of the
16-bit free run timer to the ICU data register (IPCP).
• The input compare conforms to the extended intelligent I/O service (EI2OS).
• The input capture (ICU) function is suited for measurements of intervals (frequencies) and pulse widths.
• Register Configuration
• ICU data register ch.0, ch.1 (IPCP0, IPCP1)
. . . . . . . . . . . . .
Address
IPCP0(high): 000051H
IPCP1(high): 000053H
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8 bit 7
bit 0
Initial value
XXXXXXXXB
(IPCP0 low, IPCP1 low)
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08
R
R
R
R
R
R
R
R
. . . . . . . . . . . .
bit 15
Address
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
IPCP0(low): 000050H
IPCP1(low): 000052H
XXXXXXXXB
(IPCP0 high, IPCP1 high)
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00
R
R
R
R
R
R
R
R
Note: This register holds a 16-bit free run timer value when the valid edge of the corresponding external pin input waveform is
detected. (You can word-access this register, but you cannot program it.)
• ICU control status register (ICS01)
. . . . . . . . . . . .
Address
000054H
bit 15
bit 8 bit 7
ICP1 ICP0
R/W R/W
bit 6
bit 5
ICE1 ICE0 EG11 EG10 EG01 EG00
R/W R/W R/W R/W R/W R/W
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000B
(Disabled)
R/W:Readable and writable
R:Read only
X:Undefined
DS07-13701-9E
47
MB90570A/570C Series
• Block Diagram
Internal data bus
Latch
signal
Output latch
ICU data register (IPCP)
16
Edge detection circuit
P56/IN0
Data latch signal
Pin
IPCP0H
IPCP1H
IPCP0L
2
16-bit free run
P57/IN1
16
Pin
IPCP1L
2
ICU control status register (ICS01)
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
Interrupt request
#12*
Interrupt request
#14*
*: Interrupt number
48
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MB90570A/570C Series
(3) Output Compare (OCU)
The output compare (OCU) is two sets of compare units consisting of four-channel OCU compare registers, a
comparator and a control register.
An interrupt request can be generated for each channel upon a match detection by performing time-division
comparison between the OCU compare data register setting value and the counter value of the 16-bit free run
timer.
The OUT pin can be used as a waveform output pin for reversing output upon a match detection or a general-
purpose output port for directly outputting the setting value of the CMOD bit.
• Register Configuration
• OCU control status register ch.1, ch.3 (OCS1, OCS3)
. . . . . . . . . . . . .
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8 bit 7
CMOD OTE1 OTE0 OTD1 OTD0 (OCS0, OCS2)
R/W R/W R/W R/W R/W
bit 0
Initial value
000063H
000065H
B
- - -00000
—
—
—
—
—
—
• OCU control status register ch.0, ch.2 (OCS0, OCS2)
. . . . . . . . . . . .
Initial value
Address bit 15
000062H
bit 8 bit 7
ICP1 ICP0 ICE1
R/W R/W R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
B
0000- -00
(OCS1, OCS3)
ICE0
R/W
—
—
—
—
CST1 CST0
000064H
R/W
R/W
• OCU compare register ch.0 to ch.3 (OCCP0 to OCCP3)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Initial value
Address
OCCP0 (high order address): 00005BH
OCCP1 (high order address): 00005DH
OCCP2 (high order address): 00005FH
OCCP3 (high order address): 000061H
B
XXXXXXXX
C15
R/W
C14
R/W
C13
R/W
C12
R/W
C11
R/W
C10
R/W
C09
R/W
C08
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
C00
R/W
Initial value
Address
OCCP0 (low order address): 00005AH
OCCP1 (low order address): 00005CH
OCCP2 (low order address): 00005EH
OCCP3 (low order address): 000060H
C07
R/W
C06
R/W
C05
R/W
C04
R/W
C03
R/W
C02
R/W
C01
R/W
B
XXXXXXXX
R/W:Readable and writable
—:Reserved
X:Undefined
DS07-13701-9E
49
MB90570A/570C Series
• Block diagram
#16*
#15*
Output compare
interrupt request
OCU control
status register ch.0, ch.1 (OCS0, OCS1)
—
—
—
CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0
—
—
CST1 CST0
2
2
16-bit free run timer
Compare control circuit 3
OCU compare register ch.3
Compare control circuit 2
OCU compare register ch.2
Compare control circuit 1
OCCP3
OCCP2
P67/OUT3
Pin
Output
control circuit 3
P66/OUT2
Pin
Output
control circuit 2
P65/OUT1
Pin
Output
control circuit 1
OCCP1
OCCP0
OCU compare register ch.1
Compare control circuit 0
P64/OUT0
Pin
Output
control circuit 0
OCU compare register ch.0
2
2
OCU control status register
ch.2, ch.3 (OCS2, OCS3)
—
—
—
CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0
—
—
CST1 CST0
#18*
#17*
Output compare
interrupt request
*: Interrupt number
50
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6. 8/16-bit up/down counter/timer
The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, two 8-bit
reload compare registers, and their controllers.
(1) Register configuration
• Up/down count register 0 (UDCR0)
. . . . . . . . . . . .
bit 15
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address
Initial value
00000000
B
000070H
(UDCR1)
D07
R
D06
R
D05
R
D04
R
D03
R
D02
R
D01
R
D00
R
• Up/down count register 1 (UDCR1)
. . . . . . . . . . . . .
(UDCR0)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8 bit 7
bit 0
Initial value
00000000
Address
D17
D16
D15
D14
R
D13
R
D12
R
D11
R
D10
R
000071H
B
R
R
R
• Reload compare register 0 (RCR0)
. . . . . . . . . . . .
bit 15
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
D02
W
bit 1
D01
W
bit 0
D00
Address
Initial value
00000000
(RCR1)
D07
W
D06
W
D05
W
D04
W
D03
W
B
000072H
W
• Reload compare register 1 (RCR1)
. . . . . . . . . . . . .
(RCR0)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8 bit 7
D10
bit 0
Initial value
00000000
Address
D17
D16
D15
D14
D13
W
D12
W
D11
W
000073H
B
B
B
W
W
W
W
W
• Counter status register 0, 1 (CSR0, CSR1)
. . . . . . . . . . . .
bit 15
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address
000074H
000078H
Initial value
00000000
(Reserved area)
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
R/W
R/W
R/W
bit 5
R/W
bit 4
R/W
bit 3
R/W
bit 2
R
R
• Counter control register 0, 1 (CCRL0, CCRL1)
. . . . . . . . . . . .
bit 15
bit 8 bit 7
bit 6
bit 1
bit 0
Address
000076H
00007AH
Initial value
- 0000000
(CCRH0, CCRH1)
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
R/W R/W R/W R/W R/W R/W R/W
—
—
• Counter control register 0 (CCRH0)
. . . . . . . . . . . . .
(CCRL0)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8 bit 7
bit 0
bit 0
Initial value
00000000
Address
000077H
M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Counter control register 1 (CCRH1)
. . . . . . . . . . . . .
(CCRL1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8 bit 7
Initial value
- 0000000
Address
CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
R/W R/W R/W R/W R/W R/W R/W
—
—
00007BH
B
R/W:Readable and writable
R:Read only
W:Write only
—:Undefined
DS07-13701-9E
51
MB90570A/570C Series
(2) Block Diagram
• Block diagram of 8/16-bit up/down counter/timer 0
Internal data bus
RCR0
Reload compare register 0
Re-load
control
circuit
UDCR0
CARRY/
BORRW
(to channel 1)
Up/down count register 0
Counter control
register 0 (CCRL0)
UCRE RLDE UDCC CGSC CGE1 CGE0
— CTUT
Compare
control circuit
Counter clear
circuit
PA2/ZIN0
Pin
Edge/level
detection circuit
Count clock
Counter status
register 0 (CSR0)
φ
Prescaler
UP/down count
clock selector
PA0/AIN0/IRQ6
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
Pin
Pin
PA1/BIN0
Interrupt request
#29*
Interrupt request
#30*
CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
M16E
Counter control register 0 (CCRH0)
M16E
(to channel 1)
*:Interrupt number
φ:Machine clock frequency
52
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MB90570A/570C Series
• Block diagram of 8/16-bit up/down counter/timer 1
Internal data bus
RCR1
Reload compare register 1
Re-load
control
circuit
UDCR1
Up/down count register 1
Counter control
register 1 (CCRL1)
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
—
Compare
control circuit
PA5/ZIN1
Pin
Counter clear
Edge/level
detection circuit
circuit
CARRY/BORRW
(from channel 0)
Count clock
Counter status
register 1 (CSR1)
φ
Prescaler
PA3/AIN1/IRQ7
UP/down count
clock selector
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
Pin
Pin
PA4/BIN1
Interrupt request
#31*
M16E
(from channel 1)
Interrupt request
#32*
CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
—
Counter control register 1 (CCRH1)
*:Interrupt number
φ:Machine clock frequency
DS07-13701-9E
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MB90570A/570C Series
7. Extended I/O serial interface
The extended I/O serial interface transfers data using a clock synchronization system having an 8-bit x 1 channel
configuration.
For data transfer, you can select LSB first/MSB first.
(1) Register Configuration
• Serial mode control upper status register 0 to 2 (SMCSH0 to SMCSH2)
. . . . . . . . . . . . .
(SMCSL)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8 bit 7
BUSY STOP STRT
R/W R/W
bit 0
Initial value
00000010
Address
SMCSH0: 000049H
SMCSH1: 00004DH
SMCSH2: 00007DH
B
SMD2 SMD1 SMD0 SIE
R/W R/W R/W R/W
SIR
R/W
R
• Serial mode control lower status register 0 to 2 (SMCSL0 to SMCSL2)
. . . . . . . . . . . .
bit 15
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address
Initial value
- - - - 0000
SMCSL0: 000048H
(SMCSH)
MODE BDS
SOE SCOE
B
—
—
—
—
—
—
—
—
SMCSL1: 00004CH
SMCSL2: 00007CH
R/W
R/W
R/W
R/W
• Serial data register 0 to 2 (SDR0 to SDR2)
. . . . . . . . . . . .
(Disabled)
bit 15
bit 8 bit 7
bit 6
D6
bit 5
D5
bit 4
D4
bit 3
D3
bit 2
D2
bit 1
D1
bit 0
D0
Address
SDR0: 00004AH
Initial value
XXXXXXXX
D7
B
SDR1: 00004EH
SDR2: 00007EH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W:Readable and writable
R:Read only
—:Reserved
X:Undefined
54
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MB90570A/570C Series
(2) Block Diagram
Internal data bus
D7 to D0 (LSB first)
(MSB first) D0 to D7
Pin
P40/SIN0
Pin
Transfer direction selection
Read
Write
Serial data register
(SDR)
P43/SIN1
Pin
P41/SOT0
Pin
Pin
P50/SIN2
P44/SOT1
Pin
P51/SOT2
Pin
P45/SCK1
Control circuit
Shift clock counter
Pin
P52/SCK2
Pin
P42/SCK0
Internal clock
2
1
0
MODE
SCOE
BDS SOE
SMD2 SMD1 SMD0
BUSY STOP STRT
SIE SIR
—
—
—
—
Serial mode control
status register (SMCS)
Interrupt request
#19 (SMCS0)*
#21 (SMCS1)*
#23 (SMCS2)*
*: Interrupt number
DS07-13701-9E
55
MB90570A/570C Series
8. I2C Interface
The I2C interface is a serial I/O port supporting Inter IC BUS operating as master/slave devices on I2C bus.
The MB90570A/570C series contains one channel of an I2C interface, having the following features.
• Master/slave transmission/reception
• Arbitration function
• Clock synchronization function
• Slave address/general call address detection function
• Transmission direction detection function
• Repeated generation function start condition and detection function
• Bus error detection function
(1) Register Configuration
• I2C bus status register (IBSR)
. . . . . . . . . . . .
Address bit 15
000068H
Initial value
00000000B
bit 8 bit 7
BB
bit 6
bit 5
AL
bit 4
LRB
bit 3
TRX
bit 2
AAS
bit 1
bit 0
(IBCR)
RSC
GCA FBT
R
R
R
R
R
R
R
R
• I2C bus control register (IBCR)
. . . . . . . . . . . .
Address
000069H
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8 bit 7
INT
bit 0
Initial value
00000000B
(IBSR)
BER BEIE SCC
R/W R/W R/W
MSS
R/W
ACK GCAA INTE
R/W R/W R/W
R/W
• I2C bus clock control register (ICCR)
. . . . . . . . . . . .
Address bit 15
00006AH
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
CS2
R/W
bit 1
CS1
R/W
bit 0
CS0
R/W
Initial value
--0XXXXXB
(IADR)
—
—
—
—
EN
CS4
R/W
CS3
R/W
R/W
• I2C bus address register (IADR)
. . . . . . . . . . . .
Address
00006BH
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8 bit 7
A0
bit 0
Initial value
-XXXXXXXB
(ICCR)
—
—
A6
A5
A4
A3
A2
A1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• I2C bus data register (IDAR)
. . . . . . . . . . . .
Address
00006CH
bit 15
bit 8 bit 7
D7
bit 6
bit 5
bit 4
bit 3
bit 2
D2
bit 1
D1
bit 0
D0
R/W
Initial value
(Disabled)
D6
D5
D4
D3
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable and writable
R: Read only
—: Reserved
X: Indeterminate
56
DS07-13701-9E
MB90570A/570C Series
(2) Block Diagram
Internal data bus
I2C bus status register
I2C bus control register
(IBCR)
(IBSR)
BER BEIE SCC MSS ACK GCAA INTE INT
BB RSC AL LRB TRX AAS GCA FBT
Number of
interrupt
request
generated
Start stop condition
generation circuit
Start stop condition
detection circuit
Interrupt request signal
#36*
SDA line
SCL line
Pin
PA6/SDA
I2C enable
Pin
PA7/SCL
IDAR register
Arbitration lost
detection circuit
Slave address
comparison circuit
IADR register
Clock control block
Sync
Clock
4
Count
clock
selector 1
8
Count
clock
selector 2
Shift clock
generation
circuit
Clock
divider 2
divider 1
(1/5 to
1/8)
φ
I2C enable
—
—
EN CS4 CS3 CS2 CS1 CS0
I2C bus clock control register
(ICCR)
φ:Machine clock frequency
*:Interrupt number
DS07-13701-9E
57
MB90570A/570C Series
9. UART0 (SCI), UART1 (SCI)
UART0 (SCI) and UART1 (SCI) are general-purpose serial data communication interfaces for performing syn-
chronous or asynchronous communication (start-stop synchronization system).
• Data buffer: Full-duplex double buffer
• Transfer mode: Clock synchronized (with start and stop bit)
Clock asynchronized (start-stop synchronization system)
• Baud rate: Embedded dedicated baud rate generator
External clock input possible
Internal clock (a clock supplied from 8-bit PPG timer ch1 or 16-bit PPG timer can be used.)
Internal machine clock
For 6 MHz, 8 MHz, 10 MHz
12 MHz and 16 MHz
Asynchronization 9615 bps/31250 bps/4808 bps/2404 bps/1202 bps
CLK synchronization 1 Mbps/500 kbps/250 kbps/125 kbps/62.5 kbps
}
• Data length: 7 bit to 9 bit selective (without a parity bit)
6 bit to 8 bit selective (with a parity bit)
• Signal format: NRZ (Non Return to Zero) system
• Reception error detection:Framing error
Overrun error
Parity error (multi-processor mode is supported, enabling setup of any baud rate
by an external clock.)
• Interrupt request: Receive interrupt (receive complete, receive error detection)
Transmit interrupt (transmission complete)
Transmit/receive conforms to extended intelligent I/O service (EI2OS)
58
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MB90570A/570C Series
(1) Register Configuration
• Serial control register 0,1 (SCR0, SCR1)
. . . . . . . . . . . . .
bit 0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8 bit 7
TXE
Address
000021H
000025H
Initial value
00000100
B
PEN
R/W
P
SBL
R/W
CL
A/D
REC
W
RXE
R/W
(SMR0, SMR1)
R/W
R/W
R/W
R/W
• Serial mode register 0, 1 (SMR0, SMR1)
. . . . . . . . . . . .
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 15
bit 8
Address
000020H
000024H
Initial value
B
(SCR0, SCR1)
MD1
R/W
MD0
R/W
CS2
R/W
CS1
R/W
CS0 RESV SCKE SOE
R/W R/W R/W R/W
00000000
• Serial status register 0,1 (SSR0, SSR1)
. . . . . . . . . . . . .
bit 0
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8 bit 7
Address
000023H
000027H
Initial value
B
00001 - 00
PE
R
ORE
R
FRE RDRF TRDE
—
—
RIE
TIE
(SIDR0, SIDR1/SODR0,SODR1)
R
R
R
R/W
R/W
• Serial input data register 0,1 (SIDR0, SIDR1)
. . . . . . . . . . . .
bit 7
D7
R
bit 6
bit 5
bit 4
bit 3
bit 2
D2
R
bit 1
D1
R
bit 0
D0
R
bit 15
bit 8
Address
000022H
000026H
Initial value
B
XXXXXXXX
(SSR0, SSR1)
D6
R
D5
R
D4
R
D3
R
• Serial output data register 0,1 (SODR0, SODR1)
. . . . . . . . . . . .
bit 7
D7
W
bit 6
D6
W
bit 5
D5
W
bit 4
D4
W
bit 3
D3
W
bit 2
D2
W
bit 1
D1
W
bit 0
D0
W
Address
000022H
000026H
bit 15
bit 8
Initial value
B
XXXXXXXX
(SSR0, SSR1)
• Communications prescaler control register 0,1 (CDCR0, CDCR1)
. . . . . . . . . . . .
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 15
bit 8
Address
000028H
00002AH
Initial value
B
0 - - - 1111
(Disabled)
MD
—
—
—
DIV3 DIV2
R/W R/W
DIV1 DIV0
R/W R/W
R/W
—
—
—
R/W :Readable and writable
R
:Read only
:Write only
:Reserved
:Undefined
W
—
X
RESV: Reserved bit
DS07-13701-9E
59
MB90570A/570C Series
(2) Block Diagram
• UART0 (SCI)
Control bus
Receive
interrupt signal
Dedicated baud
rate generator
Transmit
clock
#39*
Transmit
interrupt signal
#40*
Clock
selector
8/16-bit PPG
timer 1 (upper)
External clock
Receive
clock
Receive
control circuit
Transmit
control circuit
Pin
P42/SCK0
Start bit
Transmit start
detection circuit
circuit
Transmit bit
counter
Receive bit
counter
Receive parity
counter
Transmit parity
counter
Pin
P41/SOT0
Shift register for
transmission
Shift register for
reception
Pin
P40/SIN0
Reception
complete
Start transmission
SIDR0
SODR0
Receive condition
decision circuit
To I2C reception
error generation
signal (to CPU)
Internal data bus
PE
ORE
FRE
RDRF
TDRE
PEN
P
SBL
CL
A/D
REC
RXE
TXE
MD1
MD0
CS2
CS1
CS0
SMR0
register
SCR0
register
SSR0
register
RIE
TIE
SCKE
SOE
*: Interrupt number
60
DS07-13701-9E
MB90570A/570C Series
• UART1 (SCI)
Control bus
Receive
interrupt signal
#37*
Transmit
interrupt signal
#38*
Transmit
clock
Dedicated baud
rate generator
Clock
selector
8/16-bit PPG
timer 1 (upper)
Receive
clock
Receive
control circuit
Transmit
control circuit
Pin
P45/SCK1
Start bit
Transmit start
detection circuit
circuit
Transmit bit
counter
Receive bit
counter
Receive parity
counter
Transmit parity
counter
Pin
P44/SOT1
Shift register for
transmission
Shift register for
reception
Pin
P43/SIN1
Reception
complete
Start transmission
SIDR1
SODR1
Receive condition
decision circuit
To EI2OS reception
error generation
signal (to CPU)
Internal data bus
PE
PEN
MD1
P
SBL
CL
A/D
REC
RXE
TXE
ORE
MD0
CS2
CS1
CS0
FRE
SMR1
register
SCR1
register
SSR1
register
RDRF
TDRE
RIE
TIE
SCKE
SOE
*: Interrupt number
DS07-13701-9E
61
MB90570A/570C Series
10. DTP/External Interrupt Circuit
DTP (Data Transfer Peripheral), which is located between the peripheral circuit outside the device and the
F2MC-16LX CPU, receives an interrupt request or DMA request generated by the external peripheral circuit* for
transmission to the F2MC-16LX CPU. DTP is used to activate the intelligent I/O service or interrupt processing.
As request levels for IRQ2 to IRQ7, two types of “H” and “L” can be selected for the intelligent I/O service. Rising
and falling edges as well as “H” and “L” can be selected for an external interrupt request. For IRQ0 and IRQ1,
a request by a level cannot be entered, but both edges can be entered.
* : The external peripheral circuit is connected outside the MB90570A/570C series device.
Note : IRQ0 and IRQ1 cannot be used for the intelligent I/O service and return from an interrupt.
(1) Register Configuration
• DTP/interrupt factor register (EIRR)
. . . . . . . . . . . .
(ENIR)
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
000031H
bit 9
ER1
R/W
bit 8 bit 7
ER0
bit 0
Initial value
ER7
R/W
ER6
R/W
ER5
R/W
ER4
R/W
ER3
R/W
ER2
R/W
B
XXXXXXXX
R/W
• DTP/interrupt enable register (ENIR)
. . . . . . . . . . . .
Address bit 15
000030H
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
EN2
R/W
bit 1
EN1
R/W
bit 0
EN0
Initial value
(EIRR)
EN7
R/W
EN6
R/W
EN5
R/W
EN4
R/W
EN3
R/W
B
00000000
R/W
• Request level setting register (ELVR)
. . . . . . . . . . . .
Address bit 15
Low order address 000032H
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
B
(ELVR upper)
LB3
R/W
LA3
R/W
LB2
R/W
LA2
R/W
LB1
R/W
LA1
R/W
LB0
R/W
LA0
R/W
00000000
. . . . . . . . . . . .
(ELVR lower)
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8 bit 7
LA4
bit 0
Initial value
High order address 000033H
LB7
R/W
LA7
R/W
LB6
R/W
LA6
R/W
LB5
R/W
LA5
R/W
LB4
R/W
B
00000000
R/W
R/W:Readable and writable
X:Undefined
62
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(2) Block Diagram
Internal data bus
DS07-13701-9E
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MB90570A/570C Series
11. Delayed Interrupt Generation Module
The delayed interrupt generation module generates interrupts for switching tasks for development on a real-time
operating system (REALOS series). The module can be used to generate softwarewise generates hardware
interrupt requests to the CPU and cancel the interrupts.
This module does not conform to the extended intelligent I/O service (EI2OS).
(1) Register Configuration
• Delayed interrupt factor generation/cancellation register (DIRR)
. . . . . . . . . . . .
(PACSR)
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
00009FH
bit 9
bit 8 bit 7
R0
bit 0
Initial value
—
—
—
—
—
—
—
—
—
—
—
—
—
B
- - - - - - - 0
—
R/W
Note: Upon a reset, an interrupt is canceled.
R/W:Readable and writable
—:Reserved
The DIRR is the register used to control delay interrupt request generation/cancellation. Programming this
register with “1” generates a delay interrupt request. Programming this register with “0” cancels a delay interrupt
request. Upon a reset, an interrupt is canceled. The reserved bit area can be programmed with either “0” or “1”.
For future extension, however, it is recommended that bit set and clear instructions be used to access this register.
(2) Block Diagram
Internal data bus
—
—
—
—
—
—
—
R0
S factor
R latch
Interrupt request signal
#42*
Delayed interrupt factor generation/
cancellation register (DIRR)
*: Interrupt number
64
DS07-13701-9E
MB90570A/570C Series
12. 8/10-bit A/D Converter
The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input
voltage) to digital values (A/D conversion) and has the following features.
• Minimum conversion time: 26.3 µs (at machine clock of 16 MHz, including sampling time)
• Minimum sampling time: 4 µs/256 µs (at machine clock of 16 MHz)
• Compare time: 176/352 machine cycles per channel (176 machine cycles are used for a machine clock below
8 MHz.)
• Conversion method: RC successive approximation method with a sample and hold circuit.
• 8-bit or 10-bit resolution
• Analog input pins: Selectable from eight channels by software
Single conversion mode: Selects and converts one channel.
Scan conversion mode:Converts two or more successive channels. Up to eight channels can be programmed.
Continuous conversion mode: Repeatedly converts specified channels.
Stop conversion mode:Stops conversion after completing a conversion for one channel and wait for the next
activation (conversion can be started synchronously.)
• Interrupt requests can be generated and the extended intelligent I/O service (EI2OS) can be started after the
end of A/D conversion. Furthermore, A/D conversion result data can be transferred to the memory, enabling
efficient continuous processing.
• When interrupts are enabled, there is no loss of data even in continuous operations because the conversion
data protection function is in effect.
• Starting factors for conversion: Selected from software activation, and external trigger (falling edge).
DS07-13701-9E
65
MB90570A/570C Series
(1) Register Configuration
• A/D control status register upper digits (ADCS2)
. . . . . . . . . . . .
(ADCS1)
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
000037H
bit 9
bit 8 bit 7
bit 0
Initial value
B
BUSY INT
R/W R/W
INTE PAUS STS1 STS0 STRT RESV
00000000
R/W
R/W
R/W
R/W
W
R/W
• A/D control status register lower digits (ADCS1)
. . . . . . . . . . . .
Address bit 15
000036H
bit 8 bit 7
bit 6
MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
R/W R/W R/W R/W R/W R/W R/W
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
(ADCS2)
MD1
B
00000000
R/W
• A/D data register upper digits (ADCR2)
. . . . . . . . . . . .
(ADCR1)
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
000039H
bit 9
bit 8 bit 7
bit 0
Initial value
B
00001 - XX
DSEL ST1
ST0
W
CT1 XCT0
—
—
D9
—
D8
—
W
W
W
W
• A/D data register lower digits (ADCR1)
. . . . . . . . . . . .
Address bit 15
000038H
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
D2
R
bit 1
D1
R
bit 0
D0
Initial value
B
XXXXXXXX
(ADCR2)
D7
R
D6
R
D5
R
D4
R
D3
R
R
R/W :Readable and writable
R
W
:Read only
:Write only
— :Reserved
:Undefined
RESV: Reserved bit
X
66
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MB90570A/570C Series
(2) Block Diagram
A/D control status
Interrupt request #11*
register (ADCS)
BUSY
ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
INT INTE PAUS STS1 STS0 STRT
DA MD1 MD0
6
2
PB6/ADTG
TO
Clock selector
Decoder
φ
Comparator
P87/AN7
Sample hold
circuit
P86/AN6
P85/AN5
P84/AN4
P83/AN3
P82/AN2
P81/AN1
P80/AN0
Control circuit
Analog
channel
selector
AVRH, AVRL
AVCC
8-bit D/A converter
AVSS
A/D data register
(ADCR)
RESV
ST1 ST0 CT1 CT0
—
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
φ:Machine clock frequency
TO:8/16-bit PPG timer channel 1 output
*:Interrupt number
DS07-13701-9E
67
MB90570A/570C Series
13. 8-bit D/A Converter
The 8-bit D/A converter, which is based on the R-2R system, supports 8-bit resolution mode. It contains two
channels each of which can be controlled in terms of output by the D/A control register.
(1) Register Configuration
• D/A converter data register ch.0 (DADR0)
. . . . . . . . . . . .
Address
00003AH
bit 15
bit 8 bit 7
DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00
R/W R/W R/W R/W R/W R/W R/W R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
(DADR1)
B
XXXXXXXX
• D/A converter data register ch.1 (DADR1)
. . . . . . . . . . . .
(DADR0)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10
R/W R/W R/W R/W R/W R/W R/W R/W
bit 9
bit 8 bit 7
bit 0
Address
00003BH
Initial value
B
XXXXXXXX
• D/A control register 0 (DACR0)
. . . . . . . . . . . .
Address
00003CH
bit 15
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
—
bit 1
—
bit 0
DAE0
R/W
Initial value
B
- - - - - - - 0
(DACR1)
—
—
—
—
—
—
—
—
—
—
—
—
• D/A control register 1 (DACR1)
. . . . . . . . . . . .
(DACR0)
Address
00003DH
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8 bit 7
DAE1
bit 0
Initial value
B
- - - - - - - 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R/W
R/W:Readable and writable
—:Reserved
X:Undefined
68
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MB90570A/570C Series
(2) Block Diagram
Internal data bus
D/A converter data register ch.1 (DADR1)
DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10
D/A converter data register ch.0 (DADR0)
DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00
D/A converter 1
D/A converter 0
DVRH
DVRL
DA17
DA07
Pin
P74/DA1
Pin
2R
2R
P73/DA0
R
R
R
R
R
R
DA16
DA06
DA05
DA04
DA03
DA02
DA01
DA00
2R
2R
2R
2R
2R
R
DA15
2R
R
DA14
2R
R
DA13
2R
R
DA12
2R
2R
2R
2R
R
R
R
DA11
2R
R
DA10
2R
2R
2R
DVSS
DVSS
Standby control
Standby control
D/A control register 1 (DACR1)
D/A control register 0 (DACR0)
—
—
—
—
—
—
—
DAE1
—
—
—
—
—
—
— DAE0
Internal data bus
DS07-13701-9E
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MB90570A/570C Series
14. Watch Timer
The watch timer control register (WTC) controls operation of the watch timer, and time for an interval interrupt.
(1) Register Configuration
• watch timer control register (WTC)
. . . . . . . . . . . .
bit 15
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address
0000AAH
Initial value
B
(Disabled)
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
R/W R/W R/W R/W R/W R/W
1X000000
R
R
R/W:Readable and writable
R:Read only
X:Undefined
(2) Block Diagram
To watchdog timer
watch counter
× 21 × 22 × 23 × 24 × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215
LCLK
OF
OF
OF
OF
OF
OF
OF
Power-on reset
Counter
Shift to a hardware standby
Shift to stop mode
To sub-clock oscillation stabilization
time controller
clear circuit
Interval
timer selector
Watch timer interrupt request
#22*
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
Watch timer control register (WTC)
*:Interrupt number
OF:Overflow
LCLK:Oscillation sub-clock frequency
70
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MB90570A/570C Series
15. Chip Select Output
This module generates a chip select signal for facilitating a memory and I/O unit, and is provided with eight chip
select output pins. When access to an address is detected with a hardware-set area set for each pin register, a
select signal is output from the pin.
(1) Register Configuration
• Chip selection control register 1, 3, 5, 7 (CSCR1, CSCR3, CSCR5, CSCR7)
Address
CSCR1: 000081H
CSCR3: 000083H
CSCR5: 000085H
CSCR7: 000087H
. . . . . . . . . . . .
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
ACTL OPEL CSA1 CSA0
R/W R/W R/W R/W
bit 8 bit 7
bit 0
Initial value
(CSCR0, CSCR2, CSCR4, CSCR6)
—
—
—
—
—
—
—
—
B
- - - - 0000
• Chip selection control register 0, 2, 4, 6 (CSCR0, CSCR2, CSCR4, CSCR6)
. . . . . . . . . . . .
Address bit 15
bit 8 bit 7
bit 6
bit 5
bit 4
bit 3
ACTL OPEL CSA1 CSA0
R/W R/W R/W R/W
bit 2
bit 1
bit 0
Initial value
CSCR0: 000080H
CSCR2: 000082H
CSCR4: 000084H
CSCR6: 000086H
(CSCR1, CSCR3, CSCR5, CSCR7)
B
—
—
—
—
—
—
—
—
- - - - 0000
R/W:Readable and writable
—:Reserved
DS07-13701-9E
71
MB90570A/570C Series
(2) Block Diagram
From address (CPU)
A23
A22
⋅ ⋅ ⋅ ⋅ ⋅
A17
A16
A15
A14
⋅ ⋅ ⋅ ⋅ ⋅
A01
A00
Address decoder
Address decoder
Decode signal
Program area
Decode
P90/CS0
(Program ROM area application)
2
Select and set
Select and set
Select and set
Chip selection control register 0 (CSCR0)
Chip selection control register 1 (CSCR1)
Chip selection control register 2 (CSCR2)
Selector
Selector
Selector
P91/CS1
P92/CS2
P93/CS3
P94/CS4
P95/CS5
P96/CS6
P97/CS7
Select and set
Select and set
Select and set
Select and set
Select and set
Chip selection control register 3 (CSCR3)
Chip selection control register 4 (CSCR4)
Selector
Selector
Selector
Selector
Selector
Chip selection control register 5 (CSCR5)
Chip selection control register 6 (CSCR6)
Chip selection control register 7 (CSCR7)
72
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MB90570A/570C Series
(3) Decode Address Spaces
CSA
Pin
name
Number of
area bytes
Decode space
Remarks
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
—
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
—
F00000H to FFFFFFH
1 Mbyte
512 kbyte
128 kbyte
Disabled
1 Mbyte
512 kbyte
128 kbyte
128 byte
4 kbyte
F80000H to FFFFFFH
Becomes active when the program ROM
area or the program vector is fetched.
CS0
FE0000H to FFFFFFH
—
E00000H to EFFFFFH
Adapted to the data ROM and RAM areas,
and external circuit connection applica-
tions.
F00000H to F7FFFFH
CS1
CS2
CS3
CS4
CS5
FC0000H to FDFFFFH
68FF80H to 68FFFFH
003000H to 003FFFH
Adapted to the data ROM and RAM areas,
and external circuit connection applica-
tions.
FA0000H to FBFFFFH
128 kbyte
128 byte
128 byte
128 kbyte
128 byte
128 byte
Disabled
2 kbyte
68FF80H to 68FFFFH
68FF00H to 68FF7FH
F80000H to F9FFFFH
Adapted to the data ROM and RAM areas,
and external circuit connection applica-
tions.
68FF00H to 68FF7FH
68FE80H to 68FEFFH
—
002800H to 002FFFH
Adapted to the data ROM and RAM areas,
and external circuit connection applica-
tions.
68FE80H to 68FEFFH
128 byte
Disabled
Disabled
128 byte
Disabled
Disabled
Disabled
128 byte
Disabled
Disabled
Disabled
Disabled
—
—
68FF80H to 68FFFFH
Adapted to the data ROM and RAM areas,
and external circuit connection applica-
tions.
—
—
—
68FF00H to 68FF7FH
Adapted to the data ROM and RAM areas,
and external circuit connection applica-
tions.
—
—
—
—
CS6
CS7
Disabled
DS07-13701-9E
73
MB90570A/570C Series
16. Communications Prescaler Register
This register controls machine clock division.
Output from the communications prescaler register is used for UART0 (SCI), UART1 (SCI), and extended I/O
serial interface.
The communications prescaler register is so designed that a constant baud rate may be acquired for various
machine clocks.
(1) Register Configuration
• Communications prescaler control register 0,1 (CDCR0, CDCR1)
. . . . . . . . . . . .
(Disabled)
Address
bit 15
bit 8 bit 7
MD
bit 6
—
bit 5
—
bit 4
—
bit 3
DIV3 DIV2 DIV1 DIV0
R/W R/W R/W R/W
bit 2
bit 1
bit 0
Initial value
000028H
00002AH
B
0 - - - 1111
R/W
—
—
—
R/W:Readable and writable
—:Reserved
74
DS07-13701-9E
MB90570A/570C Series
17. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the
CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set
instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program
patching function to be implemented.
Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value
set in the address detection register matches an address and if the interrupt enable bit is set at “1”, the instruction
code loaded into the CPU is replaced forcibly with the INT9 instruction code.
(1) Register Configuration
• Program address detection register 0 to 2 (PADR0)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
B
XXXXXXXX
PADR0 (Low order address): 001FF0H
R/W
bit 7
R/W
bit 6
R/W
bit 5
R/W
bit 4
R/W
bit 3
R/W
bit 2
R/W
bit 1
R/W
bit 0
Address
Initial value
PADR0 (Middle order address): 001FF1H
B
XXXXXXXX
R/W
bit 7
R/W
bit 6
R/W
bit 5
R/W
bit 4
R/W
bit 3
R/W
bit 2
R/W
bit 1
R/W
bit 0
Address
Initial value
B
XXXXXXXX
PADR0 (High order address): 001FF2H
R/W
R/W
R/W
R/W
bit 4
R/W
bit 3
R/W
bit 2
R/W
bit 1
R/W
bit 0
• Program address detection register 3 to 5 (PADR1)
Address
bit 7
bit 6
bit 5
Initial value
B
XXXXXXXX
PADR1 (Low order address): 001FF3H
R/W
bit 7
R/W
bit 6
R/W
bit 5
R/W
bit 4
R/W
bit 3
R/W
bit 2
R/W
bit 1
R/W
bit 0
Address
Initial value
B
XXXXXXXX
PADR1 (Middle order address): 001FF4H
R/W
bit 7
R/W
bit 6
R/W
bit 5
R/W
bit 4
R/W
bit 3
R/W
bit 2
R/W
bit 1
R/W
bit 0
Address
Initial value
B
XXXXXXXX
PADR1 (High order address): 001FF5H
R/W
R/W
R/W
R/W
R/W
bit 3
R/W
bit 2
R/W
bit 1
R/W
bit 0
• Program address detection control status register (PACSR)
Address
bit 7
bit 6
bit 5
bit 4
Initial value
B
00000000
RESV RESV RESV RESV AD1E RESV AD0E RESV
R/W R/W R/W R/W R/W R/W R/W R/W
00009EH
R/W :Readable and writable
:Undefined
RESV:Reserved bit
X
DS07-13701-9E
75
MB90570A/570C Series
(2) Block Diagram
Address latch
Address detection
register
INT9
instruction
F2MC-16LX
CPU core
Enable bit
76
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MB90570A/570C Series
18. ROM Mirroring Function Selection Module
The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the
00 bank according to register settings.
(1) Register Configuration
• ROM mirroring function selection register (ROMM)
. . . . . . . . . . . .
(Disabled)
Address
00006FH
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
—
bit 8 bit 7
bit 0
Initial value
—
—
—
—
—
—
—
—
—
—
—
—
MI
W
B
- - - - - - - 1
—
W:Write only
—:Reserved
Note : Do not access this register during operation at addresses 004000H to 00FFFFH.
(2) Block Diagram
ROM mirroring function selection
register (ROMM)
Address area
Address
FF bank
00 bank
Data
ROM
DS07-13701-9E
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MB90570A/570C Series
19. Low-power Consumption (Standby) Mode
The F2MC-16LX has the following CPU operating mode configured by selection of an operating clock and clock
operation control.
• Clock mode
PLL clock mode: A mode in which the CPU and peripheral equipment are driven by PLL-multiplied oscillation
clock (HCLK).
Main clock mode:A mode in which the CPU and peripheral equipment are driven by divided-by-2 of the oscil
lation clock (HCLK).
The PLL multiplication circuits stops in the main clock mode.
• CPU intermittent operation mode
The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU
intermittently while external bus and peripheral functions are operated at a high-speed.
• Hardware standby mode
The hardware standby mode is a mode for reducing power consumption by stopping clock supply to the CPU
by the low-power consumption control circuit, stopping clock supplies to the CPU and peripheral functions
(timebase timer mode), and stopping oscillation clock (stop mode, hardware standby mode). Of these modes,
modes other than the PLL clock mode are power consumption modes.
(1) Register Configuration
• Clock select register (CKSCR)
. . . . . . . . . . . .
(LPMCR)
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
CS1
R/W
bit 8 bit 7
CS0
bit 0
Initial value
0000A1H
SCM MCM WS1 WS0
R/W R/W
SCS
R/W
MCS
R/W
B
11111100
R
R
R/W
• Low-power consumption mode control register (LPMCR)
. . . . . . . . . . . .
Address bit 15
bit 8 bit 7
bit 6
SLP
W
bit 5
SPL
R/W
bit 4
bit 3
bit 2
CG1
W
bit 1
CG0
R/W
bit 0
SSR
R/W
Initial value
0000A0H
B
(CKSCR)
STP
RST
W
TMD
R/W
00011000
W
R/W:Readable and writable
R:Read only
W:Write only
78
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MB90570A/570C Series
(2) Block Diagram
Standby control circuit
Low-power consumption mode control register
(LPMCR)
CPUintermittent
operation cycle
selector
CPU clock
control circuit
CPU operation
clock
STP SLP SPL RST TMD CG1 CG0 SSR
2
Clock mode
Sleep signal
Stop signal
Peripheral clock
control circuit
Hardware
standby
Peripheral function
operation clock
S
R
Q
Q
S
R
Q
Q
Machine clock
S
R
S
R
Reset
Interrupt
Oscillation
stabilization
time selector
Clock selector
2
2
PLL multiplication
circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock select register (CKSCR)
X0 Pin
1/2
1/2048
1/4
1/8
1/4
Oscillation
clock
Main
clock
X1
Pin
Clock oscillator
Timebase timer
To watchdog timer
X0A Pin
1/2
1/8
1/2
1/1024
Watch timer
Oscillation
sub-clock
X1A
Pin
Sub-clock oscillator
S: Set
R: Reset
Q: Output
DS07-13701-9E
79
MB90570A/570C Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min
Max
VCC
VSS – 0.3
VSS – 0.3
VSS + 6.0
VSS + 6.0
V
V
AVCC
*1
*1
Power supply voltage
AVRH,
AVRL
VSS – 0.3
VSS + 6.0
V
DVRH
VI
VSS – 0.3
VSS + 6.0
VSS + 6.0
VSS + 6.0
15
V
*1
*2
*2
*3
*4
Input voltage
VSS – 0.3
V
Output voltage
VO
VSS – 0.3
V
“L” level maximum output current
“L” level average output current
“L” level total maximum output current
“L” level total average output current
“H” level maximum output current
“H” level average output current
“H” level total maximum output current
“H” level total average output current
IOL
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
mA
mA
mA
mA
mA
mA
mA
mA
IOLAV
ΣIOL
ΣIOLAV
IOH
4
100
50
*5
*3
*4
–15
IOHAV
ΣIOH
ΣIOHAV
–4
–100
–50
*5
MB90573,
MB90V570A
⎯
300
mW
Power consumption
PD
⎯
⎯
500
800
mW
mW
°C
MB90574C
MB90F574A
Operating temperature
Storage temperature
TA
–40
–55
+85
Tstg
+150
°C
*1 : Care must be taken that AVCC, AVRH, AVRL, and DVRH do not exceed VCC. Also, care must be taken that
AVRH and AVRL do not exceed AVCC, and AVRL does not exceed AVRH.
*2 : VI and VO shall never exceed VCC + 0.3 V.
*3 : The maximum output current is a peak value for a corresponding pin.
*4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins.
Note : Average output current = operating × operating efficiency
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
80
DS07-13701-9E
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2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min
3.0
4.5
Max
5.5
VCC
VCC
V
V
Normal operation (MB90574C)
Normal operation (MB90F574A)
5.5
Power supply voltage
Retains status at the time of operation
stop
VCC
3.0
5.5
V
Smoothing capacitor
CS
TA
0.1
1.0
µF
°C
*
Operating temperature
–40
+85
* : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be
connected to the VCC pin must have a capacitance value higher than CS.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
• C pin connection circuit
C
CS
DS07-13701-9E
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MB90570A/570C Series
3. DC Characteristics
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter Symbol Pin name
Condition
Unit
Remarks
Min
Typ
Max
VCC + 0.3
VCC + 0.3
0.2 VCC
VSS + 0.3
—
CMOS
VIHS
VIHM
VILS
VILM
VOH
hysteresis
input pin
0.8 VCC
—
—
—
—
—
V
V
V
V
V
“H” level input
voltage
VCC = 3.0 V to 5.5 V
(MB90573/574C)
VCC = 4.5 V to 5.5 V
(MB90F574A)
MD pin input
VCC – 0.3
VSS – 0.3
VSS – 0.3
VCC – 0.5
CMOS
hysteresis
input pin
“L” level input
voltage
MD pin input
Other than
PA6 and
PA7
“H”leveloutput
voltage
VCC = 4.5 V
IOH = –2.0 mA
“L” level output
voltage
All output
pins
VCC = 4.5 V
IOL = 2.0 mA
VOL
—
—
—
0.4
5
V
Open-drain
output leakage
current
Ileak
PA6, PA7
—
0.1
µA
Other than
PA6 and
PA7
Input leakage
current
VCC = 5.5 V
VSS < VI < VCC
IIL
–5
—
5
µA
P00 to P07,
P10 to P17,
P60 to P67,
RST, MD0,
MD1
Pull-up
resistance
RUP
—
—
15
15
30
30
100
100
kΩ
kΩ
Pull-down
resistance
RDOWN MD0 to MD2
ICC
ICC
ICC
ICC
ICC
VCC
VCC
VCC
VCC
VCC
Internal operation
at 16 MHz
VCC at 5.0 V
—
—
—
—
—
30
85
50
35
90
40
130
80
mA MB90573
mA MB90F574A
mA MB90574C
mA MB90573
mA MB90F574A
Normal operation
Internal operation
at 16 MHz
VCC at 5.0 V
A/D converter
operation
45
140
Power supply
current
ICC
VCC
—
55
85
mA MB90574C
ICC
ICC
VCC
VCC
Internal operation
at 16 MHz
VCC at 5.0 V
D/A converter
operation
—
—
40
95
50
mA MB90573
145
mA MB90F574A
ICC
VCC
—
65
85
mA MB90574C
(Continued)
82
DS07-13701-9E
MB90570A/570C Series
(Continued)
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter Symbol Pin name
Condition
Unit
Remarks
Min
Typ
Max
When data written
in flash mode
programming of
erasing
ICC
VCC
—
95
140
mA MB90F574A
ICCS
ICCS
ICCS
ICCL
ICCL
VCC
VCC
VCC
VCC
VCC
Internal operation
at 16 MHz
VCC = 5.0 V
—
—
—
—
—
7
25
15
0.1
4
12
30
20
1.0
7
mA MB90573
mA MB90F574A
mA MB90574C
mA MB90573
mA MB90F574A
In sleep mode
Internal operation
at 8 kHz
VCC = 5.0 V
TA = +25°C
Subsystem
operation
ICCL
VCC
—
0.03
1
mA MB90574C
Power supply
current
ICCLS
ICCLS
VCC
VCC
Internal operation
at 8 kHz
VCC = 5.0 V
—
—
30
50
1
µA MB90573
0.1
mA MB90F574A
TA = +25°C
In subsleep mode
ICCLS
VCC
—
10
50
µA MB90574C
ICCT
ICCT
VCC
VCC
Internal operation
at 8 kHz
VCC = 5.0 V
—
—
15
30
30
50
µA MB90573
µA MB90F574A
TA = +25°C
ICCT
ICCH
ICCH
VCC
VCC
VCC
—
—
—
1.0
5
30
20
10
µA MB90574C
µA MB90573
In clock mode
TA = +25°C
In stop mode
MB90F574A
µA
0.1
MB90574C
Other than
AVCC,
AVSS, VCC,
VSS
Input
capacitance
CIN
—
—
10
80
pF
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MB90570A/570C Series
4. AC Characteristics
(1) Reset, Hardware Standby Input Timing
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin
name
Symbol
Condition
Unit
Remarks
Parameter
Min
Max
Under normal
operation
4 tCP
—
ns
Reset input time
tRSTL
RST
HST
—
Oscillation time of
oscillator * + 4 tCP
—
—
ms In stop mode
ns
Hardware standby input time
tHSTL
4 tCP
* : Oscillation time of oscillator is time that the amplitude reached the 90 %.
In the crystal oscillator, the oscillation time is between several ms to tens ms. In ceramic oscillator, the oscillation
time is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms.
Note : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Under Normal operation
tRSTL, tHSTL
RST
HST
0.2 VCC
0.2 VCC
In Stop Mode
tRSTL
RST
0.2 VCC
0.2 VCC
90 % of
amplitude
X0
Internal operation clock
4 tCP
Oscillation time
of oscillator
Oscillation setting time
Instruction execution
Internal reset
• Measurement conditions for AC characteristics
Pin
CL
CL is a load capacitance connected to a pin under test.
Capacitors of CL = 30 pF must be connected to CLK and ALE pins, while CL of 80 pF must
be connected to address data bus (AD15 to AD00), RD, WRL, and WRH pins.
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MB90570A/570C Series
(2) Specification for Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condi-
tion
Symbol Pin name
Unit
Remarks
Parameter
Min
Max
Power supply rising time
Power supply cut-off time
tR
VCC
VCC
0.05
30
ms
ms
*
—
Due to repeated
operations
tOFF
4
—
* : VCC must be kept lower than 0.2 V before power-on.
Note : • The above ratings are values for causing a power-on reset.
• There are internal registers which can be initialized only by a power-on reset.
Apply power according to this rating to ensure initialization of the registers.
tR
2.7 V
0.2 V
VCC
0.2 V
0.2 V
tOFF
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to raise the voltage
smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V/s or fewer per sec-
ond, however, you can use the PLL clock.
VCC
It is recommended to keep the rising
speed of the supply voltage at 50 mV/ms
3.0 V
or slower.
VSS
DS07-13701-9E
85
MB90570A/570C Series
(3) Clock Timings
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condi-
tion
Symbol Pin name
Unit
Remarks
Parameter
Min
3
Typ
Max
16
FC
X0, X1
—
MHz
kHz
ns
Clock frequency
FCL
X0A, X1A
X0, X1
—
32.768
—
—
tHCYL
tLCYL
62.5
—
333
—
Clock cycle time
X0A, X1A
30.5
µs
Recommend
ns duty ratio of
30% to 70%
PWH,
PWL
X0
10
—
—
Input clock pulse width
PWLH,
PWLL
X0A
X0, X0A
—
—
—
15.2
—
—
5
µs
tCR,
tCF
External clock
operation
Input clock rising/falling time
ns
—
Main clock op-
fCP
fLCP
tCP
1.5
—
—
16
—
333
—
5
MHz
eration
Internal operating clock fre-
quency
Subclock oper-
—
8.192
—
kHz
ation
External clock
—
62.5
—
ns
operation
Internal operating clock cycle
time
Subclock oper-
tLCP
∆f
—
122.1
—
µs
ation
Frequency fluctuation rate
locked
—
—
%
*
* : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied
PLL signal is locked.
+
+ α
fO
| α |
fO
∆f =
× 100 (%)
Center frequency
– α
–
The PLL frequency deviation changes periodically from the preset frequency “(about CLK × (1CYC to 50 CYC)”,
thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with
long intervals).
86
DS07-13701-9E
MB90570A/570C Series
• X0, X1 clock timing
tHCYL
0.8 VCC
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
X0
PWH
PWL
tCF
tCR
• X0A, X1A clock timing
tLCYL
0.8 VCC
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
X0A
PWLH
PWLL
tCF
tCR
• PLL operation guarantee range
Relationship between internal operating clock
frequency and power supply voltage
Operation guarantee range (MB90F574A)
(V)
Operation guarantee range MB90574C
5.5
4.5
PLL operation
guarantee range
Operation guarantee range
MB90V570A
3.3
3.0
Operation guarantee range
MB90573
(MHz)
1.5
3
8
12
16
Internal clock fCP
Relationship between oscillating frequency, internal
operating clock frequency, and power supply voltage
(MHz)
16
Multiplied-
by-4
Multiplied-
by-3
Multiplied-by-2
Multiplied-by-1
12
9
8
Not multiplied
6
4
3
2
1.5
(MHz)
3
4
6
8
12
16
Oscillation clock FC
DS07-13701-9E
87
MB90570A/570C Series
The AC ratings are measured for the following measurement reference voltages.
• Input signal waveform
• Output signal waveform
Hystheresis input pin
0.8 VCC
Hystheresis input pin
2.4 VCC
0.2 VCC
0.8 VCC
Pins other than hystheresis input/MD input
0.7 VCC
0.3 VCC
(4) Clock Output Timing
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min
62.5
20
Max
—
Cycle time
CLK ↑ → CLK ↓
tCYC
CLK
ns
ns
—
tCHCL
CLK
—
tCYC
tCHCL
2.4 V
2.4 V
0.8 V
CLK
88
DS07-13701-9E
MB90570A/570C Series
(5) Bus Read Timing
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min
Max
ALE pulse width
tLHLL
ALE
1 tCP*/2 – 20
—
ns
ALE,
A23 to A16,
AD15 to AD00
Effective address →
ALE ↓ time
tAVLL
tLLAX
tAVRL
1 tCP*/2 – 20
1 tCP*/2 – 15
1 tCP* – 15
—
—
—
ns
ns
ns
ALE ↓ → address
effective time
ALE,
AD15 to AD00
RD,
A23 to A16,
AD15 to AD00
Effective address →
RD ↓ time
Effective address →
A23 to A16,
AD15 to AD00
tAVDV
tRLRH
tRLDV
—
3 tCP*/2 – 20
—
5 tCP*/2 – 60 ns
ns
3 tCP*/2 – 60 ns
valid data input
RD pulse width
RD
—
—
RD,
AD15 to AD00
RD ↓ → valid data input
RD,
AD15 to AD00
RD ↑ → data hold time
RD ↑ → ALE ↑ time
tRHDX
tRHLH
tRHAX
0
—
—
—
ns
ns
ns
ALE, RD
1 tCP*/2 – 15
1 tCP*/2 – 10
RD ↑ → address
effective time
ALE,
A23 to A16
CLK,
A23 to A16,
AD15 to AD00
Effective address →
CLK ↑ time
tAVCH
1 tCP*/2 – 20
—
ns
RD ↓ → CLK ↑ time
ALE ↓ → RD ↓ time
tRLCH
tALRL
CLK, RD
ALE, RD
1 tCP*/2 – 20
1 tCP*/2 – 15
—
—
ns
ns
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
DS07-13701-9E
89
MB90570A/570C Series
tAVCH
tRLCH
2.4 V
2.4 V
CLK
tRHLH
2.4 V
2.4 V
2.4 V
0.8 V
tLHLL
tAVLL
ALE
RD
tLLAX
tRLRH
2.4 V
0.8 V
tRHAX
tAVRL
tRLDV
2.4 V
0.8 V
2.4 V
0.8 V
AD23 to AD16
AD15 to AD00
tAVDV
tRHDX
2.4 V
0.8 V
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
Address
Read data
90
DS07-13701-9E
MB90570A/570C Series
(6) Bus Write Timing
Parameter
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min
Max
WRL, WRH,
A23 to A16,
AD15 to AD00
Effective address →
WR ↓ time
tAVWL
1 tCP – 15
—
ns
WR pulse width
tWLWH
tDVWH
WRL, WRH
3 tCP*/2 – 20
3 tCP*/2 – 20
—
—
ns
ns
WRL, WRH,
AD15 to AD00
Write data → WR ↑ time
—
WRL, WRH,
WR ↑ → data hold time
tWHDX
20
—
—
ns
ns
AD15 to AD00
WR ↑ → address
effective time
WRL, WRH,
A23 to A16
tWHAX
1 tCP*/2 – 10
WR ↑ → ALE ↑ time
WR ↓ → CLK ↑ time
tWHLH
tWLCH
ALE, WRL
CLK, WRH
1 tCP*/2 – 15
1 tCP*/2 – 20
—
—
ns
ns
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
WRL, WRH
2.4 V
0.8 V
tWHAX
2.4 V
0.8 V
2.4 V
0.8 V
A23 to A16
tDVWH
tWHDX
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
AD15 to AD00
Address
Write data
DS07-13701-9E
91
MB90570A/570C Series
(7) Ready Input Timing
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min
45
0
Max
—
RDY setup time
RDY hold time
tRYHS
tRYHH
RDY
RDY
ns
ns
—
—
Note : Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient.
2.4 V
2.4 V
CLK
ALE
RD/WRL, RD/WRH
tRYHS
tRYHS
RDY
(wait inserted)
0.2 VCC
0.2 VCC
RDY
0.8 VCC
0.8 VCC
(wait not inserted)
tRYHH
(8) Hold Timing
Parameter
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min
30
Max
1 tCP*
2 tCP*
Pins in floating status →
HAK ↓ time
tXHAL
HAK
HAK
ns
ns
—
HAK ↑ → pin valid time
tHAHV
1 tCP*
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Note : More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.
HAK
2.4 V
0.8 V
tXHAL
tHAHV
2.4 V
0.8 V
2.4 V
0.8 V
Each pin
High-Z
92
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MB90570A/570C Series
(9) UART0 (SCI), UART1 (SCI) Timing
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min
Max
Serial clock cycle time
tSCYC
tSLOV
SCK0 to SCK4
8 tCP*
—
ns
ns
SCK ↓ → SOT delay
time
SCK0 to SCK4,
SOT0 to SOT4
Internalshiftclock
mode
CL = 80 pF
+ 1 TTL for an
output pin
– 80
100
60
80
—
SCK0 to SCK4,
SIN0 to SIN4
Valid SIN → SCK ↑
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
ns
ns
ns
ns
ns
ns
ns
SCK ↑ → valid SIN hold
time
SCK0 to SCK4,
SIN0 to SIN4
—
Serial clock “H” pulse
width
SCK0 to SCK4
SCK0 to SCK4
4 tCP*
4 tCP*
—
—
Serial clock “L” pulse
width
—
External shift
clock mode
CL = 80 pF
+ 1 TTL for an
output pin
SCK ↓ → SOT delay
time
SCK0 to SCK4,
SOT0 to SOT4
150
—
SCK0 to SCK4,
SIN0 to SIN4
Valid SIN → SCK ↑
60
SCK ↑ → valid SIN hold
time
SCK0 to SCK4,
SIN0 to SIN4
60
—
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Notes : • These are AC ratings in the CLK synchronous mode.
• CL is the load capacitance value connected to pins while testing.
DS07-13701-9E
93
MB90570A/570C Series
• Internal shift clock mode
tSCYC
SCK0 to SCK4
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
0.2 V
SOT0 to SOT4
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SIN0 to SIN4
• External shift clock mode
tSLSH
tSHSL
SCK0 to SCK4
SOT0 to SOT4
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SIN0 to SIN4
94
DS07-13701-9E
MB90570A/570C Series
(10) Timer Input Timing
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min
Max
tTIWH,
tTIWL
Input pulse width
IN0, IN1
—
4 tCP*
—
ns
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
IN0, IN1
tTIWH
tTIWL
(11) Timer Output Timing
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min
Max
CLK ↑ → TOUT
transition time
OUT0 to OUT3,
PPG0, PPG1
tTO
—
30
—
ns
2.4 V
CLK
tTO
2.4 V
0.8 V
TOUT
DS07-13701-9E
95
MB90570A/570C Series
(12) Trigger Input Timing
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit
Remarks
Parameter
Min
5 tCP *
1
Max
—
IRQ0 to IRQ7,
ADTG, IN0, IN1
Under normal
operation
ns
tTRGH
tTRGL
Input pulse width
—
IRQ0 to IRQ5
—
µs In stop mode
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
IRQ0 to IRQ7
ADTG, IN0, IN1
tTRGH
tTRGL
96
DS07-13701-9E
MB90570A/570C Series
(13) Chip Select Output Timing
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min
Max
Valid chip select output
→ Valid data input time
CS0 to CS7,
AD15 to AD00
tSVDV
tRHSV
tWHSV
tSVCH
—
5 tCP*/2 – 60 ns
RD ↑ → chip select
output effective time
RD,
CS0 to CS7
1 tCP*/2 – 10
1 tCP*/2 – 10
1 tCP*/2 – 20
—
—
—
ns
ns
ns
—
WR ↑ → chip select
output effective time
CS0 to CS7,
WRL, WRH
Valid chip select output
→ CLK ↑ time
CLK,
CS0 to CS7
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
tSVCH
CLK
2.4 V
RD
2.4 V
tRHSV
A23 to A16
CS0 to CS7
2.4 V
0.8 V
tSVDV
2.4 V
0.8 V
AD15 to AD00
Read data
tWHSV
WRL, WRH
2.4 V
AD15 to AD00
Write data
DS07-13701-9E
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MB90570A/570C Series
(14) I2C Timing
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Symbol Pin name
Unit
Remarks
Parameter
Min
Max
Internal clock cycle time
Start condition output
tCP
—
62.5
666
ns All products
tSTAO
tCP×m×n/2-20 tCP×m×n/2+20 ns
Only as master
Only as slave
Only as master
tCP(m×n/
2+4)-20
tCP(m×n/
2+4)+20
Stop condition output
tSTOO
ns
SDA,SCL
Start condition detection
Stop condition detection
SCL output “L” width
tSTAI
tSTOI
3tCP+40
3tCP+40
—
—
ns
ns
tLOWO
tCP×m×n/2-20 tCP×m×n/2+20 ns
SCL
tCP(m×n/
2+4)-20
tCP(m×n/
2+4)+20
SCL output “H” width
SDA output delay time
tHIGHO
tDOO
—
ns
ns
ns
2tCP-20
4tCP-20
2tCP+20
—
SDA,SCL
Setup after SDA output
interrupt period
tDOSUO
SCL input “L” width
SCL input “H” width
SDA input setup time
SDA input hold time
tLOWI
tHIGHI
tSUI
3tCP+40
tCP+40
40
—
—
—
—
ns
ns
ns
ns
SCL
SDA,SCL
tHOI
0
Notes : • “m” and “n” in the above table represent the values of shift clock frequency setting bits (CS4-CS0) in
the clock control register “ICCR”. For details, refer to the register description in the hardware manual.
• tDOSUO represents the minimum value when the interrupt period is equal to or greater than the SCL “L” width.
• The SDA and SCL output values indicate that rise time is 0 ns.
• For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
98
DS07-13701-9E
MB90570A/570C Series
• I2C interface [data transmitter (master/slave)]
tLOWO
tHIGHO
0.8 VCC
0.8 VCC
0.8 VCC
0.8 VCC 0.8 VCC
SCL
SDA
0.2 VCC
tDOO
0.2 VCC
1
8
9
tSTAO
tDOO
tSUI
tHOI
tDOSUO
ACK
• I2C interface [data receiver (master/slave)]
tHIGHI
tLOWI
0.8 VCC
tSUI
0.8 VCC
0.8 VCC
SCL
SDA
0.2 VCC
tHOI
0.2 VCC
8
0.2 VCC
0.2 VCC
6
7
9
tSTOI
tDOO
tDOO
tDOSUO
ACK
DS07-13701-9E
99
MB90570A/570C Series
(15) Pulse Width on External Interrupt Pin at Return from STOP Mode
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol
Pin name
Condition
Unit
Remarks
Min
Max
tIRQWH
tIRQWL
Input pulse width
IRQ2 to IRQ7
⎯
6tCP *
⎯
ns
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
0.8VCC
0.2VCC
0.8VCC
0.2VCC
IRQ2∼IRQ7
tIRQWH
tIRQWL
100
DS07-13701-9E
MB90570A/570C Series
5. A/D Converter Electrical Characteristics
≤
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, 2.7 V AVRH – AVRL, TA = –40°C to +85°C)
Value
Symbol Pin name
Condition
Unit
Parameter
Resolution
Min
—
Typ
8/10
—
Max
—
—
—
—
—
—
—
bit
Total error
—
5.0
2.5
LSB
LSB
Non-linear error
—
—
Differential
linearity error
—
VOT
VFST
—
—
—
—
1.9
LSB
V
—
Zero transition
voltage
AN0 to
AN7
AVRL
AVRL
AVRL
–3.5 LSB –0.5 LSB +4.5 LSB
AVRH AVRH AVRH
–6.5 LSB –1.5 LSB +1.5 LSB
Full-scale
transition voltage
AN0 to
AN7
V
A/D conversion
time
VCC = 5.0 V 10%
at machine clock of 16 MHz
—
—
416tCP
64tCP
—
—
—
—
—
—
—
—
µs
µs
µA
V
VCC = 5.0 V 10% at machine
clock of 6 MHz
Sampling period
—
Analog port
input current
AN0 to
AN7
IAIN
VAIN
—
10
Analog input
voltage
AN0 to
AN7
AVRL
AVRH
AVCC
—
AVRL
+3.0
AVRH
V
Reference
voltage
AVRH
–3.0
—
IA
AVRL
0
—
5
V
AVCC
—
—
mA
Power supply
current
CPU stopped and 8/10-bit
A/D converter not in operation
(VCC = AVCC = AVRH = 5.0 V)
IAH
IR
AVCC
—
—
—
—
400
—
5
µA
µA
µA
AVRH
AVRH
—
—
5
Reference
voltage supply
current
CPU stopped and 8/10-bit
A/D converter not in operation
(VCC = AVCC = AVRH = 5.0 V)
IRH
Offset between
channels
AN0 to
AN7
—
—
—
—
4
LSB
DS07-13701-9E
101
MB90570A/570C Series
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter
Linearity error:The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000
0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual con-
version characteristics
Differential linearity error:The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error:The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
Total error
3FF
0.5 LSB
3FE
3FD
Actual conversion
value
{1 LSB × (N – 1) + 0.5 LSB}
004
003
002
001
VNT
(measured value)
Actual conversion
characteristics
Theoretical
characteristics
0.5 LSB
Analog input
AVRL
AVRH
AVRH – AVRL
1024
VNT – {1 LSB × (N – 1) + 0.5 LSB}
1 LSB = (Theoretical value)
[V]
Total error for digital output N
[LSB]
=
1 LSB
VOT (Theoretical value) = AVRL + 0.5 LSB[V]
VFST (Theoretical value) = AVRH – 1.5 LSB[V]
VNT: Voltage at a transition of digital output from (N – 1) to N
(Continued)
102
DS07-13701-9E
MB90570A/570C Series
(Continued)
Linearity error
Differential linearity error
Theoretical characteristics
3FF
3FE
3FD
Actual conversion
value
N + 1
Actual conversion value
{1 LSB × (N – 1)+ VOT}
VFST
N
N – 1
N – 2
(measured value)
VNT
004
003
002
001
V(N + 1)T
(measured value)
Actual conversion
characteristics
VNT (measured value)
Theoretical
Actual conversion
value
characteristics
VOT (measured value)
Analog input
AVRL
AVRH
AVRL
Analog input
AVRH
Linearity error of
digital output N
VNT – {1 LSB × (N – 1) + VOT}
[LSB]
=
1 LSB
Differential linearity error
of digital N
V(N + 1)T – VNT
1 LSB
– 1 LSB [LSB]
=
VFST – VOT
1022
1 LSB
[V]
=
VOT:Voltage at transition of digital output from “000H” to “001H”
VFST:Voltage at transition of digital output from “3FEH” to “3FFH”
DS07-13701-9E
103
MB90570A/570C Series
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions.
Output impedance values of the external circuit MB90V570A/573 are 5 kΩ or lower, MB90F574A/574C are 10
kΩ or lower are recommended.
When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor
value is recommended to minimized the effect of voltage distribution between the external capacitor and internal
capacitor.
When the output impedance of the external circuit is too high, the sampling period for analog voltages may not
be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz).
• Equipment of analog input circuit model
C0
Analog input
Comparator
C1
MB90573, MB90V570A
MB90F574A
MB90574C
R ≅ 3.2 kΩ, C ≅ 30 pF
R ≅ 7.1 kΩ, C ≅ 48.3 pF
R ≅ 2.2 kΩ, C ≅ 45 pF
Note : Listed values must be considered as standards.
• Error
The smaller the | AVRH – AVRL |, the greater the error would become relatively.
104
DS07-13701-9E
MB90570A/570C Series
8. D/A Converter Electrical Characteristics
(AVCC = VCC = DVCC = 5.0 V 10%, AVSS = VSS = DVSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Unit
Remarks
Parameter
Resolution
Min
Typ
Max
—
—
—
—
—
8
—
bit
Differential linearity
error
—
—
0.9
LSB
Absolute accuracy
Linearity error
—
—
—
—
—
—
—
—
—
—
—
10
1.2
1.5
20
%
LSB
Conversion time
µs Load capacitance: 20 pF
Analog reference
voltage
—
DVCC
VSS + 3.0
—
AVCC
V
Conversion under
no load
IDVR
IDVRS
—
DVCC
DVCC
—
—
—
120
—
300
10
µA
Reference voltage
supply current
µA In sleep mode
kΩ
Analog output
impedance
—
20
—
9. Flash Memory Program/Erase Characteristics
Value
Condition
Unit
Remarks
Parameter
Min
Typ
Max
Except for the write time before
internal erase operation
Sector erase time
Chip erase time
—
1.5
30
s
s
TA = + 25°C
VCC = 5.0 V
Except for the write time before
internal erase operation
—
—
13.5
32
—
Word (16bit width)
programming time
Except for the over head time of
the system
1,000
µs
Program/Erase time
Data hold time
—
—
10,000
—
—
—
—
cycle
h
100,000
DS07-13701-9E
105
MB90570A/570C Series
■ EXAMPLE CHARACTERISTICS
(1) Power Supply Current (MB90573)
ICC - VCC
ICC (mA)
35
ICCS - VCC
ICCS (mA)
10
TA = +25°C
TA = +25°C
9
8
7
6
5
4
3
2
1
30
Fc = 16 MHz
Fc = 16 MHz
25
20
15
10
5
Fc = 12.5 MHz
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
Fc = 2 MHz
3.0
4.0
5.0
6.0
VCC (V)
3.0
4.0
5.0
6.0
VCC (V)
ICC - TA
ICCS - TA
ICC (mA)
35
ICCS (mA)
10
VCC = 5.0 V
VCC = 5.0 V
9
8
7
6
5
4
3
2
1
30
25
20
15
10
5
Fc = 16 MHz
Fc = 16 MHz
Fc = 12.5 MHz
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
–20
+10 +40
ICCL - VCC
+70 +100
TA (°C)
–20
+10
+40
+70
+100
TA (°C)
ICCLS - VCC
ICCLS (mA)
70
ICCL (µA)
160
TA = +25°C
TA = +25°C
60
50
40
30
20
10
140
120
100
80
Fc = 8 kHz
Fc = 8 kHz
60
40
20
3.0
4.0
5.0
6.0
VCC (V)
3.0
4.0
5.0
6.0
VCC (V)
(Continued)
DS07-13701-9E
106
MB90570A/570C Series
ICC - Fc
ICCS - Fc
ICC (mA)
35
ICCS (mA)
10
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
TA = +25°C
9
8
7
6
5
4
3
2
1
TA = +25°C
30
25
20
15
10
5
VCC = 3.0 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 2.5 V
4.0
6.0
8.0
12.0 16.0
Fc (MHz)
4.0
6.0
8.0
12.0 16.0
Fc (MHz)
ICCH - VCC
ICCT - VCC
ICCH (µA)
10
ICCT (µA)
20
TA = +25°C
TA = +25°C
9
8
7
6
5
4
3
2
1
18
16
14
12
10
8
Fc = 8 kHz
6
4
2
3.0
4.0
5.0
6.0
VCC (V)
3.0
4.0
5.0
6.0
VCC (V)
ICCT - TA
ICCT (µA)
10
ICCLH (µA)
ICCLH - TA
10
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
9
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
1
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
–20
+10 +40
+70
+100
TA (°C)
–20
+10 +40
+70
+100
TA (°C)
(Continued)
107
DS07-13701-9E
MB90570A/570C Series
(Continued)
ICCL - TA
ICCLS - TA
ICCL (µA)
ICCLS (µA)
20
14
VCC = 6.0 V
VCC = 5.5 V
18
16
14
12
10
8
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 5.0 V
12
10
8
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 3.0 V
VCC = 2.5 V
6
6
4
4
2
2
–20
+10 +40
+70
+100
TA (°C)
–20
+10 +40
+70
+100
TA (°C)
108
DS07-13701-9E
MB90570A/570C Series
(2) Power Supply Current (MB90F574A)
ICCS - VCC
ICC - VCC
ICCS (mA)
ICC (mA)
140
40
TA = +25°C
TA = +25°C
Fc = 16 MHz
120
100
80
35
Fc = 12.5 MHz
Fc = 16 MHz
30
Fc = 10 MHz
Fc = 8 MHz
25
20
15
10
5
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
60
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
Fc = 2 MHz
40
20
3.0
4.0
5.0
6.0
VCC (V)
3.0
4.0
5.0
6.0
VCC (V)
ICC - TA
ICCS - TA
ICC (mA)
120
ICCS (mA)
40
VCC = 5.0 V
VCC = 5.0 V
35
30
25
20
15
10
5
100
80
Fc = 16 MHz
Fc = 12.5 MHz
Fc = 16 MHz
Fc = 10 MHz
Fc = 8 MHz
60
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 5 MHz
Fc = 4 MHz
40
20
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
Fc = 2 MHz
–20
+10 +40
+70
+100
TA (°C)
–20
+10 +40
+70
+100
TA (°C)
(Continued)
DS07-13701-9E
109
MB90570A/570C Series
ICCLS - VCC
ICCLS (µA)
200
TA = +25°C
180
160
140
120
FC = 8 kHz
100
80
60
40
20
3.0
4.0
5.0
6.0
VCC (V)
ICCS - FC
ICC - FC
ICCS (mA)
40
ICC (mA)
120
VCC = 6.0 V
TA = +25°C
TA = +25°C
35
30
100
80
VCC = 5.5 V
VCC = 5.0 V
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
25
20
15
10
VCC = 4.5 V
VCC = 4.0 V
60
40
20
VCC = 3.5 V
VCC = 3.0 V
VCC = 3.0 V
VCC = 2.5 V
5
VCC = 2.5 V
4.0
8.0
12.0
16.0
FC (MHZ)
4.0
8.0
12.0
16.0
FC (MHZ)
ICCT - VCC
ICCH -VCC
ICCH (µA)
10
ICCT (µA)
50
TA = +25°C
TA = +25°C
9
40
30
20
8
7
6
5
4
3
FC = 8 kHZ
10
2
1
6.0
VCC (V)
3.0
4.0
5.0
3
5
4
6
VCC (V)
(Continued)
110
DS07-13701-9E
MB90570A/570C Series
(Continued)
ICCT - TA
ICCH - TA
ICCT (µA)
10
ICCH (µA)
10
9
9
8
8
7
6
7
6
5
4
3
2
1
5
4
3
2
1
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
+10
+40 +70
TA (°C)
+100
+40 +70
+100
TA (°C)
-20
+10
-20
ICCLS - TA
ICCLS (µA)
20
18
16
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
14
12
VCC = 4.5 V
VCC = 4.0 V
10
8
VCC = 3.5 V
VCC = 3.0 V
6
VCC = 2.5 V
4
2
+40 +70
+100
TA (°C)
+10
-20
DS07-13701-9E
111
MB90570A/570C Series
(3) Power Supply Current (MB90574C)
ICC (mA)
ICC (mA)
50
ICC - TA
VCC = 5.0 V
ICC - VCC
TA = +25 °C
70
60
50
40
30
20
10
0
FC = 16 MHz
45
40
35
30
25
20
15
10
FC = 16 MHz
FC = 12 MHz
FC = 10 MHz
FC = 8 MHz
FC = 12 MHz
FC = 10 MHz
FC = 8 MHz
FC = 5 MHz
FC = 4 MHz
FC = 2 MHz
FC = 5 MHz
FC = 4 MHz
FC = 2 MHz
5
0
−50
−20
10
40
70
100
3.0
3.5
4.0
4.5
5.0
5.5
6.0
TA (°C)
VCC (V)
ICCS (mA)
18
ICC (mA)
70
ICCS - VCC
TA = +25 °C
ICC - FC
TA = +25 °C
FC = 16 MHz
16
14
60
50
40
30
20
10
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
FC = 12 MHz
FC = 10 MHz
FC = 8 MHz
12
10
8
FC = 5 MHz
FC = 4 MHz
FC = 2 MHz
6
4
2
0
0
2
3.000 3.500 4.000
5.000
6.000
5.500
4
6
10 12
16
14
4.500
8
VCC (V)
FC (MHz)
ICCS (mA)
18
ICCS (mA)
ICCS - TA
VCC = 5 V
ICCS - FC
TA = +25 °C
18
16
14
12
10
8
VCC = 6.0 V
VCC = 5.5 V
16
14
12
10
8
FC = 16 MHz
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
FC = 12 MHz
FC = 10 MHz
FC = 8 MHz
6
6
FC = 4 MHz
4
2
4
FC = 2 MHz
2
0
−50
0
2
−20
10
40
70
100
4
6
8
10 12 14
16
TA (°C)
FC (MHz)
(Continued)
DS07-13701-9E
112
MB90570A/570C Series
ICCH (µA)
ICCH (µA)
ICCH - VCC
TA = +25 °C
ICCH - TA
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
3.000 3.500 4.000 4.500 5.000 5.500 6.000
VCC (V)
−50
−20
10
40
70
100
TA (°C)
ICCT (µA)
ICCT (µA)
ICCT - TA
ICCT - VCC
TA = +25 °C
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
0
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
FC = 8 kHz
0
−50
−20
10
40
70
100
TA (°C)
3.000 3.500 4.000 4.500 5.000 5.500 6.000
VCC (V)
ICCL (µA)
70
ICCL (µA)
70
ICCL - VCC
TA = +25 °C
ICCL - TA
60
50
40
30
20
10
0
60
50
40
30
20
10
0
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
FC = 8 kHz
−50 −20
10
40
70
100
TA (°C)
3.000 3.500 4.000 4.500 5.000 5.500 6.000
VCC (V)
(Continued)
DS07-13701-9E
113
MB90570A/570C Series
(Continued)
ICCLS (µA)
ICCLS (µA)
25
ICCLS - VCC
TA = +25 °C
ICCLS - TA
25
20
15
10
5
20
15
10
5
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
FC = 8 kHz
0
0
−50 −20
10
40
70
100
TA (°C)
3.000 3.500 4.000 4.500 5.000 5.500 6.000
VCC (V)
114
DS07-13701-9E
MB90570A/570C Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB90F574APMC1
MB90573PMC1
120-pin Plastic LQFP
(FPT-120P-M24)
MB90F574APFV
MB90574CPFV
MB90573PFV
120-pin Plastic QFP
(FPT-120P-M13)
MB90574CPMT
MB90F574APMT
120-pin Plastic LQFP
(FPT-120P-M21)
DS07-13701-9E
115
MB90570A/570C Series
■ PACKAGE DIMENSIONS
120-pin plastic LQFP
Lead pitch
0.40 mm
14.0 mm × 14.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
1.70 mm MAX
Code
(Reference)
P-LFQFP120-14×14-0.40
(FPT-120P-M24)
120-pin plastic LQFP
(FPT-120P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*
14.00±0.10(.551±.004)SQ
90
61
91
60
0.08(.003)
Details of "A" part
1.50 +–00..1200
.059 +–..000048
(Mounting height)
INDEX
120
31
"A"
0~8˚
1
30
LEAD No.
0.10±0.10
(.004±.004)
(Stand off)
0.16±0.05
(.006±.002)
0.145±0.055
(.006±.002)
0.50±0.20
(.020±.008)
M
0.40(.016)
0.07(.003)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2006-2008 FUJITSU MICROELECTRONICS LIMITED F120036S-c-1-2
2006 FUJITSU LIMITED F120036S-c-1-1
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
116
DS07-13701-9E
MB90570A/570C Series
120-pin plastic QFP
Lead pitch
0.50 mm
20.0 × 20.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
3.85 mm MAX
2.58g
Code
(Reference)
(FPT-120P-M13)
P-FQFP120-20×20-0.50
120-pin plastic QFP
(FPT-120P-M13)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
22.60±0.20(.890±.008)SQ
*
20.00±0.10(.787±.004)SQ
0.145±0.055
(.006±.002)
90
61
91
60
0.08(.003)
Details of "A" part
3.53 –+00..2302
(Mouting height)
.139 –+..000183
0.20 –+00..1150
.008 –+..000064
(Stand off)
0°~8°
INDEX
120
31
0.25(.010)
0.50±0.20
(.020±.008)
"A"
0.60±0.15
(.024±.006)
1
30
LEAD No.
0.50(.020)
0.22±0.05
(.009±.002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2003-2008 FUJITSU MICROELECTRONICS LIMITED F120013S-c-4-7
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS07-13701-9E
117
MB90570A/570C Series
(Continued)
120-pin plastic LQFP
Lead pitch
0.50 mm
16.0 × 16.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.88 g
Code
(Reference)
(FPT-120P-M21)
P-LFQFP120-16×16-0.50
120-pin plastic LQFP
(FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
16.00 –0.10
.630 +–..000146 SQ
*
90
61
91
60
0.08(.003)
Details of "A" part
1.50 +–00..1200
.059 –+..000048
(Mounting height)
INDEX
0~8˚
"A"
120
31
0.10±0.05
(.004±.002)
(Stand off)
1
30
LEAD No.
0.145 +–00..0035
.006 +–..000012
0.60±0.15
(.024±.006)
0.22±0.05
(.009±.002)
M
0.50(.020)
0.08(.003)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2002-2008 FUJITSU MICROELECTRONICS LIMITED F120033S-c-4-5
2002 FUJITSU LIMITED F120033S-c-4-4
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
118
DS07-13701-9E
MB90570A/570C Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
Series name is changed
MB90570 series → MB90570A/570C series
⎯
⎯
Deleted the part number;
MB90574, MB90F574, MB90V570
⎯
⎯
⎯
⎯
⎯
⎯
The package code is changed.
(FPT-120P-M05 → FPT-120P-M24)
Peripheral Resource name is changed.
Clock Timer → Watch Timer
■ PERIPHERALS
1. I/O port
Changed the pull-up resister value in "? Input pull-up resistor
setup register (RDR)".
38
5.0 kΩ → 50 kΩ
■ ELECTRICAL CHARACTERISTICS Changed the value of ICCS (Condition : Internal operation at 16
83
88
3. DC Characteristics
MHz VCC = 5.0 V In sleep mode) When MB90F574A
(Min : 5, Max : 10 → Min : 25, Max : 30)
■ ELECTRICAL CHARACTERISTICS Deleted the "(4) Recommended Resonator Manufacturers".
4. AC Characteristics
■ ELECTRICAL CHARACTERISTICS Changed the value of "Zero transition voltage".
5. Electrical Characteristics for the
A/D Converter
(Added "AVRL")
Changed the unit of "Zero transition voltage" and "Full-scale
101
transition voltage".
(mV → V)
■ ORDERING INFORMATION
■ PACKAGE DIMENSIONS
Changed the part namber;
MB90573PFF → MB90573PMC1
MB90F574APFF → MB90F574APMC1
115
116
Changed the figure of package.
FPT-120P-M05 → FPT-120P-M24
The vertical lines marked in the left side of the page show the changes.
DS07-13701-9E
119
MB90570A/570C Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
Asia Pacific
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Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
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http://www.fmal.fujitsu.com/
Europe
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Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
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Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
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other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Business & Media Promotion Dept.
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