MB90M407APF_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13718-2E

16-Bit Original Microcontroller

CMOS

F²MC-16LX MB90M405 Series

Built in FL Display Controller Circuit

MB90MF408/M408/M407/MF408A/

MB90M408A/M407A

■ DESCRIPTION

TheMB90M405seriesisageneral-purpose16-bitmicrocontroller, developedforapplicationsrequiringfluorescent

display tube panel control. Each microcontroller is equipped with 60 highly voltage-resistant output pins, needed

for fluorescent display control. The command structure inherits the same AT architecture as the F²MC-8L and

F²MC-16L, in order to provide enhanced C-language support, improved extended/signed multiplication/division

instructions in addressing mode, and enhanced bit processing. In addition, an onboard 32-bit accumulator allows

long word processing.

Note : F²MC stands for FUJITSU Flexible MicroController, and is a registered trademark of Fujitsu Limited.

■ FEATURES

• Clock

• Internal PLL clock multiplication circuit

• Oscillation clock

1/2 main oscillation clock

1 × to 4 × PLL oscillation clock (2 MHz to 16 MHz at 4 MHz oscillation) , can be set from machine clock

• Minimum instruction execution time : 62.5 ns (operating at 4 MHz oscillation, 4 × PLL clock, V^CC= 3 V)

• Oscillation clock can generate 1/32, 1/64, 1/128, and 1/256 external clock outputs.

• Maximum memory space : 16 Mbytes

• Can also use 24-bit addressing

(Continued)

■ PACKAGE

100-pin plastic QFP

(FPT-100P-M06)

MB90M405 Series

• Command structure optimized for controller applications

• Able to handle following data types : bit, byte, word, and long word

• 23 types of addressing mode

• High code efficiency (compiler)

• Enhanced calculation precision using a 32-bit accumulator

• Enhanced signed multiplication and division instructions and RETI instructions

• Command structure supports C language/multitasking

• Employs system stack pointers

• Instruction set had symmetry and barrel shift instruction functions

• Program patch functions (2-address pointers)

• Improved execution speed

• 4-byte built-in instruction queue allows instructions to be read ahead of time, speeding up execution.

• Interrupt function

• 8 programmable priority level settings

• Incorporates powerful 32-factor interrupt function

• Data transfer function

• Extended intelligent I/O service function : allows up to 16 channels to be set

• Low-power consumption modes

• Sleep mode (CPU operation clock stops)

• Timebase timer mode (oscillation clock and timebase timer operate)

• Stop mode (oscillation clock stops)

• CPU intermittent operation mode (CPU operates intermittently at the specified intervals)

• Package

• QFP-100 (FPT-100P-M06 : 0.65 mm pin pitch)

• Process

• CMOS technology

• I/O ports : Maximum 26 (26 ports, also used for internal resources)

• Timebase timer : 1 channel

• Watchdog timer : 1 channel

• 16-bit reload timer : 3 channels

• 16-bit freerun timers : 1 channel

• Output compare : 1 channel

• If the count value of the 16-bit freerun timer and compare register setting match, an interrupt request can

be output

• Input capture : 2 channels

• By detecting a valid edge in a signal input from the external input pin, it is possible to read the 16-bit freerun

timer count into the input capture data register, and output an interrupt request.

• Serial I/O : 2 channels

• UART : 2 channels

• Includes full-duplex double buffer (8 bits length)

• Can be set to clock-asynchronous transfer or clock-synchronized serial transfer (I/O extended serial)

• DTP/external interrupt (4 channels)

• Extended intelligent I/O service can be started via external input

• It is possible to generate an internal hardware interrupt via external input

• Delayed interrupt generation module

• It is possible to output task switching interrupt requests

• 8/10 bit A/D converter (16 channels)

• Choice of 8 and 10-bit resolution selectable

(Continued)

2

MB90M405 Series

(Continued)

• FL control circuit

• FL driver control enabled (up to 32 digits and up to 60 segments with automatic display control)

- Any number between 1 and 32 digits can be set

- Dimmer setting possible

• LED driver control enabled (up to 16 with automatic display control)

- Up to 16 automatic display control possible at 1/2 duty

• Time clock output circuit

• Can be set to 1/32, 1/64, 1/128, or 1/256 of oscillation clock

3

MB90M405 Series

■ PRODUCT LINEUP

MB90MF408*¹

MB90MF408A*²

MB90M408*¹

MB90M408A*²

MB90M407*¹

MB90M407A*²

Part Number

Classification

MB90MV405

Internal flash

memory type

Internal mask ROM type

Evaluation

ROM size

128 Kbytes

96 Kbytes

4 Kbytes

None onboard

4 Kbytes

RAM size

4 Kbytes

Emulator power supply*³

⎯

Included

Number of basic instructions

: 351

Minimum instruction execution time

Addressing modes

: 62.5 ns/4 MHz (with x4 multiplier)

: 23

CPU functions

Program patch function

Maximum memory space

: 2 address pointers

: 16 Mbytes

Ports

26 (CMOS) I/O ports (26 ports, also used for resources)

60 FL outputs possible (during LED control, 43 FL output and 17 LED control)

FL and LED driver control enabled

FL-control circuit

During FL driver control, both digit and segment dimmer setting possible

Includes full-duplex double buffer

Clock-synchronized/asynchronous settings available

Can also be used as clock synchronized extended I/O serial

Also equipped with dedicated baud rate generator

Serial I/O: 2 channels, UART: 2 channels

Serial I/O (UART)

16-bit reload timer operation (can be set to toggle or one-shot output)

Event count function can be set

3 channels built in

16-bit reload timers

16-bit I/O timer

One 16-bit output comparison channel (for clearing freerun timer)

Two 16-bit input capture channels

16 channels (input multiplex)

Choice of 8 and 10-bit resolution available

Conversion time : 6.125 µs (when machine clock operating at 16 MHz)

8/10 bit

A/D converter

Time clock

output circuit

Possible to divide external input oscillation clock and output externally

Programmable divisions : 32/64/128/256

I²C*⁴Bus

One I²C interface channel built in

DTP/external

interrupt

4 independent channels (also used with A/D input)

Interrupt factors : can be set to “L”→“H” edge/“H”→“L” edge/“L” level/“H” level

Low-power modes

Process

Sleep mode/timebase timer mode, stop mode, and intermittent CPU mode

CMOS

Package

QFP-100 (0.65 mm pitch)

PGA256

Operating voltage

3.3 V 0.3 V (16 MHz : 4 MHz 4x)

*1 : All FL-output pins (FIP0 to FIP59) have pull downs

*2 : Some FL-output pins (FIP0 to FIP16) do not have pull downs. The remaining FL-output pins (FIP17 to FIP59)

have pull downs.

*3 : Setting of DIP Switch (S2) when using emulation pod (MB2145-507) . Refer to “2.7 Dedicated Emulator Power

Supply” in the “MB2145-507 Hardware Manual” for details.

*4 : Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use, these

components in an I²C system provided that the system conforms to the I²C Standard Specification as defined

by Philips.

4

MB90M405 Series

■ PIN ASSIGNMENTS

(TOP VIEW)

FIP16/LED16

FIP17

1

2

3

80 PB7/AN15/INT3

79 PB6/AN14/INT2

78 PB5/AN13/SO2/TO0

77 RST

FIP18

FIP19

4

FIP20

FIP21

FIP22

FIP23

5

6

7

8

76 PB4/AN12/SC2/TIN0

75 PB3/AN11/SI2

74 PB2/AN10

73 PB1/AN9

FIP24

9

72 PB0/AN8

FIP25

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

71 PA7/AN7

70 PA6/AN6

69 PA5/AN5

68 PA4/AN4

67 PA3/AN3

66 PA2/AN2

65 PA1/AN1

64 PA0/AN0/TMCK

63 AV^SS

V

SS-IO

FIP26

FIP27

FIP28

FIP29

FIP30

FIP31

FIP32

FIP33

FIP34

FIP35

FIP36

DD-FIP

FIP37

FIP38

FIP39

FIP40

FIP41

FIP42

FIP43

62

AVCC

61 P91/SCL/SC3

60 P90/SDA/SO3

59 P87/SO1

58 P86/SC1

57 P85/SI1

56 P84/SO0

55 P83/SC0

54 P82/SI0

V

53 P81/IC1/INT1

52 P80/IC0/INT0

51 MD2

(FPT-100P-M06)

5

MB90M405 Series

■ PIN DESCRIPTIONS

Pin No.

Circuit

State/

Function at

Reset

Pin Name

Description

Type

QFP-100

Oscillation Input/Output pin

When connected to external clock, please free pin X1

82, 83

77

X0, X1

A

B

Oscillating

RST

FIP0 to FIP15

LED0 to LED15

FIP16

Reset input External reset input pin

Set when FL driver authorized

85 to 100

1

Set when LED driver authorized

V^KK

Set when FL driver authorized

Pull-down

output

C

D

LED16

Set when LED driver authorized

2 to 10

12 to 19

(If pull-down

resistance

is set)

FIP17 to FIP33

Dedicated FL driver output pin

20 to 22

24 to 41

43 to 47

FIP34 to FIP59

P80

IC0

I/O port

Input capture ch 0 is external trigger input pin

52

53

External interrupt input ch 0 is external factor input pin

Accepted when bit EN0 set to enabled

INT0

P81

IC1

I/O port

Input capture ch 1 is external trigger input pin

External interrupt input ch 1 is external factor input pin

Accepted when bit EN1 set to enabled

INT1

P82

I/O port

Serial data input pin for serial I/O ch 0

During input operation by serial I/O ch 0, pin is used

continuously, so do not use as a different pin

54

55

56

57

SI0

P83

SC0

P84

SO0

P85

SI1

Port input

(Hi-z)

E

I/O port

Serial clock I/O pin for serial I/O ch 0

Effective when serial clock output for serial I/O ch 0 en-

abled

I/O port

Serial data output pin for serial I/O ch 0

Effective when serial data output for serial I/O ch 0 en-

abled

I/O port

Serial data input pin for serial I/O ch 1

During input operation by serial I/O ch 1, pin is used

continuously, so do not use as a different pin

(Continued)

6

MB90M405 Series

Pin No.

State/

Functionat

Reset

Circuit

Type

Pin Name

P86

Description

QFP-100

I/O port

Serial clock I/O pin for serial I/O ch 1

Effective when serial clock output for serial I/O ch 1 en-

abled

58

59

SC1

E

P87

I/O port

Serial data output pin for serial I/O ch 1

Effective when serial data output for serial I/O ch 1 en-

abled

SO1

P90

I/O port (however, Nch open drain)

I²C interface data I/O pin. This function is effective when

I²C interface operation is enabled. While the I²C inter-

face is operating, set the port to input (DDR9 : bit 8 = 0) .

SDA

Port input

(Hi-z)

60

G

Serial data output pin for serial I/O ch 3

Effective when serial data output for serial I/O ch 3 en-

abled

SO3

P91

I/O port (however, Nch open drain)

I²C interface clock I/O pin. This function is effective

when I²C interface operation is enabled. While the I²C

interface is operating, set the port to input (DDR9 : bit 9

= 0) .

SCL

61

G

Serial clock I/O pin for serial I/O ch 3

Effective when serial clock output for serial I/O ch 3 en-

abled

SC3

PA0

AN0

I/O port

Ch 0 of A/D converter analog input pin

Effective when analog input setting enabled (set with

ADER)

64

65 to 74

75

Time clock output pin. Effective when output enabled.

Note that this is not effective when analog input enabled

via ADER.

TMCK

PA1 to PB2

AN1 to AN10

PB3

I/O port

Ch 1 to ch 10 of A/D converter analog input pin

Effective when analog input setting enabled (set with

ADER)

F

Analog input

I/O port

Ch 11 of A/D converter analog input pin

Effective when analog input setting enabled (set with

ADER)

AN11

Serial data input pin for serial I/O ch 2

SI2

During input operation by serial I/O ch 2, pin is used

continuously, so do not use as a different pin

(Continued)

7

MB90M405 Series

(Continued)

Pin No.

Cir-

State/

Pin Name

cuit Functionat

Type

Description

QFP-100

Reset

PB4

I/O port

Ch 12 of A/D converter analog input pin

Effective when analog input setting enabled (set with ADER)

AN12

Serial clock I/O pin for serial I/O ch 2

Effective when serial clock output for serial I/O ch 2 enabled

76

SC2

External clock input pin of reload timer ch 0

Effective when external clock input enabled (ADER is priori-

tized)

TIN0

PB5

I/O port

Ch 13 of A/D converter analog input pin

Effective when analog input setting enabled (set with ADER)

AN13

F

Analog input

Serial data output pin for serial I/O ch 2

Effective when serial data output for serial I/O ch 2 enabled

78

SO2

TO0

External event output pin of reload timer ch 0

Effective when external event output enabled (ADER is pri-

oritized)

PB6, PB7

I/O port

Ch 14 and ch 15 of A/D converter analog input pin

Effective when analog input setting enabled (set with ADER)

AN14, AN15

79, 80

External interrupt input ch 2 and ch 3 are external factor input

pins

INT2, INT3

Accepted when bits EN2 and EN3 set to enabled

62

63

AV^CC

AV^SS

Vcc power input pin of analog macro

Vss power input pin of analog macro

H

Power input

Power pin of pull-down side during high voltage resistant out-

put

48

V^KK

⎯

Input pin for specifying operating mode. Connect to V^CC.

Additionally, when flash boot program is being used, be sure

to switch to V^SS.

49

50

51

MD0

MD1

MD2

B

Mode pins Input pin for specifying operating mode. Connect to V^CC.

Input pin for specifying operating mode. Connect to V^SS.

Additionally, when flash boot program is being used, be sure

to switch to V^CC.

11, 42

23

V^SS−IO

V^DD−FIP

V^SS−CPU

V^CC−CPU

I/O power (0 V : GND) input pin

FIP power (3 V : V^CC) input pin

Power input

⎯

81

Control circuit power (0 V : GND) input pin

84

Control circuit power (3 V : V^CC) input pin

8

MB90M405 Series

■ I/O CIRCUITS

Type

Circuit

Remarks

• Oscillation circuit

Oscillation return resistance =

approx. 1 MΩ

X1

Nch

Xout

Pch

Nch

X0

A

Standby control signal

• Hysteresis input pin

Built-in pull-up resistance (Rp)

Rp

B

• Pch open drain output

- High voltage resistance port output

I^OL= −23 mA

Pout

Pch

C

When used as normal port, connect a

diode clamp or the like to prevent volt-

age V^KKfrom being applied to the pin

during “L” level output.

R

KK

V

KK

(See “■ HANDLING DEVICES”)

• Pch open drain output

- High voltage resistance port output

I^OL= −12 mA

Pout

Pch

D

When used as normal port, connect a

diode clamp or the like to prevent volt-

age V^KKfrom being applied to the pin

during "L" level output.

R

KK

V

KK

(See "■ HANDLING DEVICES")

• CMOS hysteresis I/O pin

- CMOS output

- CMOS hysteresis input

(Equipped with function to block

input during standby)

I^OL= 4 mA

Pch

Pout

Nout

Nch

R

E

CMOS hysteresis input

Standby control

(Continued)

9

MB90M405 Series

(Continued)

Type

Circuit

Remarks

• Analog/CMOS hysteresis I/O pin

- CMOS output

- CMOS hysteresis input

(Equipped with function to block in-

put during standby)

Pch

Pout

Nout

Nch

R

F

- Analog input

(When ADER-compatible bit is “1”

analog input is enabled)

I^OL= 4 mA

CMOS hysteresis input

Standby control

Analog input

• Nch open drain output

- CMOS hysteresis input

(Equipped with function to block in-

put during standby)

Nch

R

Nout

Unlike the CMOS I/O pin, there is no

Pch transistor. Therefore, when the de-

vice power is shut off, there will be no

flow of current to the device power

(V^CC-IO/V^CC-CPU) , even if external

voltage is applied to the pin.

G

CMOS hysteresis input

Standby control

• Analog power input protection circuit

Pch

Nch

H

IN

10

MB90M405 Series

■ HANDLING DEVICES

This section contains important information on handling the device, regarding the following :

• Do not exceed maximum rated voltage (to prevent latch-up)

• Supply voltage stability

• Power-on precautions

• Treatment of unused pins

• Treatment of A/D converter power supply pin

• Notes on using external clock

• Power supply pin

• Sequence for applying power analog input of A/D converter

• Output of high-voltage output pin (circuit types C & D)

• Do not exceed maximum rated voltage (to prevent latch-up)

• With a CMOS IC, if voltage above V^CCor below V^SSis applied to an output or input pin other than a medium/

high voltage resistance pin, or if voltage between V^CCand V^SS, but exceeding the rated voltage, is applied, a

latch-up state could be generated. In the event of a latch-up, the power current will increase drastically, possibly

destroying the chip due to overheating. For this reason, make sure not to exceed the maximum rating.

• When applying or shutting off analog power, make sure that the analog power (AV^CC) and analog input voltage

do not exceed the digital power voltage (V^CC) .

• Supply voltage stability

Even within the scope of operational protection for V^CCpower voltage, a sudden increase in power voltage could

cause the unit to malfunction. For this reason, please stabilize the V^CCpower voltage.

The standard for stabilizing voltage is a V^CCripple fluctuation (peak to peak value) of no more than 10% of

standard V^CCpower voltage at commercial power frequencies (50 Hz to 60 Hz) , and an excess fluctuation rate

of no more than 0.1 V/ms for instantaneous changes when switching power.

• Power-on precautions

When turning on the power, ensure that the power voltage (V^CC) power-up time is at least 50 µs (0.2 V to

2.7 V) , in order to keep the built-in step-down circuit from malfunctioning.

• Treatment of unused pins

Leaving unused input pins free could cause permanent damage due to malfunctions and latch-ups. For this

reason, set unused input pins to pull-up or pull-down via resistance of 2 kΩ or more. Additionally, if there are

unused I/O pins, either set them to output and leave them free, or set them to input and treat them as input pins.

• Notes on using external clock

When using an external clock, please drive pin X1 only, and free pin X1. An example of using an external clock

is shown in the figure below:

X0

MB90M405 series

X1

OPEN

11

MB90M405 Series

• Power supply pin

• When there are multiple V^CC/V^SS, in order to prevent latch-ups and other malfunctions, then from design

considerations, although pins of the same potential are connected device-internally, make sure to connect the

V^CCand V^SSpins to power and grounds, in order to reduce unneeded radiation, and prevent strobe signal

malfunctions due to rises in ground level.

• Connect V^CCand V^SSto MB90M405 series devices from a current supply source at low impedance.

• Connect an approximately 0.1 µF capacitor as a bypass capacitor between the V^CCand V^SS, near the V^CCand

Vss pins, in order to combat power-source noise in MB90M405 series devices.

• Crystal Oscillation Circuit

• Noise to the X0 and X1 pins can cause MB90M405 series devices to malfunction. Design the printed circuit

board so that pins X0 and X1, and the crystal oscillator (or ceramic oscillator) and the capacitor to the ground,

are near pins X0 and X1, and not crossing the X0 and X1, or other wiring.

• Stable operation can be expected from PCB artwork that surrounds pins X0 and X1 with grounds.

• Sequence for applying power analog input of A/D converter

• Always make sure to apply voltage to the digital power pin (V^CC) before applying voltage to the A/D converter

power pin (AV^CC) and analog input pins (AN0 to AN15) .

• When shutting off the power, shut off digital power (V^CC) after shutting off A/D converter power and analog input.

• If a port pin also used for analog input is used as an input port, make sure that the analog input voltage does

not exceed AV^CC(there is no problem with simultaneously applying and cutting analog and digital power) .

• Pin handling when not using A/D converter

• When not using the A/D converter, connect so that AV^CC= V^CCand AV^SS= V^SS.

• Output of high-voltage resistance output pin (circuit types C & D)

If using high voltage-resistance output (circuit types C & D) as the ordinary output port, when outputting “L” level,

a value of pull-down for V^KKpin voltage is output. In this case, the V^KKlevel voltage is applied to the external

circuit, so add a diode clamp circuit as shown in the figure below:

Diode clamp circuit

Pout

Pch

RKK

VKK

• Notes on PLL clock mode

If the oscillator is disconnected, or clock input stops, when the PLL clock is selected on the microcontroller, the

microcontroller may continue to operate, using the free-run frequency of the PLL-internal self-exciting oscillation

circuit. This operation is not guaranteed.

12

MB90M405 Series

■ BLOCK DIAGRAM

CPU control

circuit part

PA0/AN0/TMCK

PA1/AN1

PA2/AN2

PA3/AN3

PA4/AN4

PA5/AN5

PA6/AN6

PA7/AN7

Time clock

output circuit

X0, X1

RST

Clock control

circuit

8/10-bit

A/D

Converter

MD2, MD1, MD0

ROM

(96/128 KB)

Serial I/O

(ch 2)

RAM

External

interrupts

input control

(4 KB)

PB0/AN8

PB1/AN9

PB2/AN10

FIP0/LED0

FL control circuit

V-RAM

to

16-bit

freerun timer

FIP16/LED16

PB3/AN11/SI2

PB4/AN12/SC2/TIN0

PB5/AN13/SO2/TO0

PB6/AN14/INT2

FIP17 to FIP59

16-bit input

capture

(ch 0, ch 1)

V^KK

VCC/VSS

AVCC/AVSS

PB7/AN15/INT3

16-bit output

Compare

P80/IC0/INT0

P81/IC1/INT1

P82/SI0

16-bit

reload timer

(ch 0 to ch 2)

Serial I/O

(ch 3)

P83/SC0

P90/SDA/SO3

P91/SCL/SC3

P84/SO0

P85/SI1

UART

(ch 0, ch 1)

I²C

Interface

P86/SC1

P87/SO1

13

MB90M405 Series

■ MEMORY MAP

Single chip mode

(with ROM miror function)

FFFFFFH

ROM area

Address #1

010000H

ROM area

(image oh FF bank)

Address #2

Address #3

RAM

Registers

area

000100H

0000C0H

:

Access prohibited

Peripherals

000000H

Model

Address #1

Address #2

Address #3

MB90M407/A

MB90M408/A

MB90MF408/A

MB90MV405

FE8000^H

FE0000^H

F80000^H*

004000^H

001100^H

* : V products have no built-in ROM. Show the ROM decode area on the tool side.

The purpose of the ROM mirror function is to use a small C compiler model.

The lower 16-bit address of the FF bank is the same as the lower 16-bit address of the 00 bank. However, as

the ROM area of the FF bank exceeds 48 Kbytes, a mirror image of all the data in the ROM area cannot be

shown in the 00 bank.

When using a small C compiler model, storing a data table in “FF4000^Hto FFFFFF^H” allows a mirror image of

the data table to be shown in “004000^Hto 00FFFF^H”. Consequently, it is possible to refer to the data table in the

ROM area without declaring a far pointer.

• When setting the ROM mirror function register, a mirror image of the data in the upper side of bank FF

(“FF4000^Hto FFFFFF^H”) can be seen in the upper side of bank 00 (“004000^Hto 00FFFF^H”) .

• See “■ PERIPHERAL FUNCTIONS 15. ROM Mirror Function Selection Module” for details on setting the ROM

mirror function.

14

MB90M405 Series

■ I/O MAP

Abbreviated

Register

Name.

Read/

Write

Address

Register name

Resource Name

Initial Value

000000^H

to

Access prohibited

000007^H

000008^H

000009^H

00000A^H

00000B^H

PDR8

PDR9

PDRA

PDRB

Port 8 data register

R/W

Port 8

Port 9

Port A

Port B

XXXXXXXX^B

Port 9 data register

Port A data register

Port B data register

00000C^H

to

Access prohibited

000017^H

000018^H

000019^H

00001A^H

00001B^H

DDR8

DDR9

DDRA

DDRB

Port 8 direction register

Port 9 direction register

Port A direction register

Port B direction register

R/W

Port 8

Port 9

Port A

Port B

0 0 0 0 0 0 0 0^B

XXXXXX 0 0^B

0 0 0 0 0 0 0 0^B

00001C^H

to

Access prohibited

00001D^H

00001E^H

00001F^H

000020^H

000021^H

ADER0

ADER1

SMR0

SCR0

Analog input enable register 0

Analog input enable register 1

Mode register ch 0

R/W

R

Port A, A/D

Port B, A/D

1 1 1 1 1 1 1 1^B

0 0 0 0 0 X 0 0^B

0 0 0 0 0 1 0 0^B

0 0 0 0 0 0 0 0^B

XXXXXXXX^B

Control register ch 0

SIDR0

SODR0

SSR0

Input data register ch 0

Output data register ch 0

Status register ch 0

UART ch0

UART ch1

000022^H

W

000023^H

000024^H

000025^H

R/W

R

0 0 0 0 1 0 0 0^B

0 0 0 0 0 X 0 0^B

0 0 0 0 0 1 0 0^B

SMR1

SCR1

Mode register ch 1

Control register ch 1

SIDR1

SODR1

SSR1

Input data register ch 1

Output data register ch 1

Status register ch 1

000026^H

XXXXXXXX^B

W

000027^H

000028^H

R/W

0 0 0 0 1 0 0 0^B

0 XXX 0 0 0 0^B

Communication prescaler

control register ch 0

Communication

prescaler 0

CDCR0

CDCR1

R/W

Communication prescaler

control register ch 1

Communication

prescaler 1

000029^H

0 XXX 0 0 0 0^B

(Continued)

15

MB90M405 Series

Abbreviated

Register

Name.

Read/

Write

Address

Register name

I²C status register

Resource Name

Initial Value

00002A^H

00002B^H

00002C^H

00002D^H

00002E^H

00002F^H

000030^H

000031^H

000032^H

000033^H

000034^H

IBSR

IBCR

ICCR

IADR

IDAR

ISEL

R

0 0 0 0 0 0 0 0^B

XX 0 XXXXX^B

XXXXXXXX^B

XXXXXXX 0^B

XXXX 0 0 0 0^B

XXXXXXXX^B

0 0 0 0 0 0 0 0^B

I²C control register

R/W

I²C clock control register

I²C address register

I²C interface

I²C data register

I²C port selection register

DTP/external interrupt enable register

DTP/external interrupt factor register

Request level setting register

ENIR

EIRR

ELVR

DTP/external

interrupt circuit

Access prohibited

ADCS0

ADCS1

A/D control status register 0 (low-order)

R/W

0 0 XXXXXX^B

XXXXXXXX^B

A/D control status register 1

(high-order)

000035^H

R/W

8/10 bit

A/D converter

000036^H

000037^H

000038^H

ADCR0

ADCR1

A/D data register 0(low-order)

A/D data register 1 (high-order)

R/W

XXXXXXXX^B

0 0 0 0 0 XXX^B

Access prohibited

8/10 bit

A/D converter

000039^H

ADMR

TCCS

A/D conversion channel setting register

R/W

0 0 0 0 0 0 0 0^B

00003A^H

to

00003F^H

Access prohibited

000040^H

000041^H

000042^H

000043^H

000044^H

000045^H

000046^H

000047^H

000048^H

000049^H

00004A^H

00004B^H

00004C^H

00004D^H

Timer counter control status register

R/W

16-bit free-run timer 0 0 0 0 0 0 0 0^B

Access prohibited

0 0 0 0 0 0 0 0^B

16-bit free-run timer

TCDT

IPC0

Timer counter data register

R/W

R

0 0 0 0 0 0 0 0^B

XXXXXXXX^B

Input capture data register ch 0

Input capture

XXXXXXXX^B

0 0 0 0 0 0 0 0^B

IPC1

Input capture data register ch 1

R

ICS01

Input capture control status register

R/W

Access prohibited

XXXXXXXX^B

XX 0 0 XXX 0^B

OCCP0

OCS0

Output compare register

R/W

Output compare

Output compare control status register

Reserved

00004E^H,

00004F^H

Access prohibited

(Continued)

16

MB90M405 Series

Abbreviated

Register

Name.

Address

Register name

Read/Write Resource Name Initial Value

000050^H

000051^H

000052^H

0 0 0 0 0 0 0 0^B

TMCSR0 Timer control status register ch 0

R/W

XXXX 0 0 0 0^B

16-bit reload

TMR0 : R

TMRLR0 :

W

XXXXXXXX^B

timer ch 0

TMR0/

16-bit timer register ch 0 (R)

16-bit reload register ch 0 (W)

TMRLR0

000053^H

XXXXXXXX^B

000054^H

000055^H

000056^H

0 0 0 0 0 0 0 0^B

XXXX 0 0 0 0^B

XXXXXXXX^B

TMCSR1 Timer control status register ch 1

R/W

16-bit reload

timer ch 1

TMR1 : R

TMRLR1 :

W

TMR1/

16-bit timer register ch 1 (R)

16-bit reload register ch 1 (W)

TMRLR1

000057^H

XXXXXXXX^B

000058^H

000059^H

00005A^H

0 0 0 0 0 0 0 0^B

XXXX 0 0 0 0^B

XXXXXXXX^B

TMCSR2 Timer control status register ch 2

R/W

16-bit reload

timer ch 2

TMR2 : R

TMRLR2 :

W

TMR2/

16-bit timer register ch 2 (R)

16-bit reload register ch 2 (W)

TMRLR2

00005B^H

XXXXXXXX^B

00005C^H

to

Access prohibited

00005F^H

000060^H

000061^H

000062^H

000063^H

000064^H

000065^H

000066^H

000067^H

000068^H

000069^H

00006A^H

00006B^H

00006C^H

XXXX 0 0 0 0^B

SMCS2

SDR2

Serial mode control status register ch 2

Serial shift data register ch 2

R/W

Serial I/O ch 2 0 0 0 0 0 0 1 0^B

XXXXXXXX^B

Access prohibited

XXXX 0 0 0 0^B

Serial I/O ch 3 0 0 0 0 0 0 1 0^B

XXXXXXXX^B

SMCS3

SDR3

Serial mode control status register ch 3

Serial shift data register ch 3

R/W

Access prohibited

FLC1

FLC2

FLDG

FLDC

Display control register 1

Display control register 2

Digit setting register

W

XXXXXX 0 0^B

0 0 0 0 0 0 0 0^B

FL control circuit

0 0 0 0 0 0 0 0^B

Digit number register

0 0 0 0 0 0 0 0^B

Access prohibited

R

XX 1 XXX 0 0^B

FL control circuit

00006D^H

00006E^H

FLST

Status register/definition register

Access prohibited

ROM mirror function selection register

W

0 0 XXXXXX^B

ROM mirror

00006F^H

ROMM

W

function

XXXXXXX 1^B

selection module

(Continued)

17

MB90M405 Series

Abbreviated

Register

Name.

Read/

Write

Address

Register name

Resource Name

Initial Value

000070^H

to

SEGD0 to 7 Segment dimmer setting register

W

XXXXXXXX^B

000077^H

FL control circuit

000078^H

000079^H

00007A^H

FLPD0

FLPD1

FLPD2

FIP36 to 43

W

0 0 0 0 0 0 0 0^B

Port register

FIP44 to 51

FIP52 to 59

00007B^H

to

Access prohibited

00009D^H

Program address detection

control status register

Address match

detection function

00009E^H

00009F^H

PACSR

DIRR

R/W

0 0 0 0 0 0 0 0^B

XXXXXXX 0^B

Delayed interrupt factor

generation/cancel register

Delayed interrupt

generation module

R/W

0000A0^H

0000A1^H

LPMCR

CKSCR

Low-power mode control register

Clock selection register

R/W

0 0 0 1 1 0 0 0^B

1 1 1 1 1 1 0 0^B

Low-power

control circuit

0000A2^H

to

Access prohibited

0000A7^H

0000A8^H

0000A9^H

WDTC

TBTC

Watchdog timer control register

Timebase timer control register

R/W

Watchdog timer

Timebase timer

XXXXX 1 1 1^B

1 XX 0 0 1 0 0^B

0000AA^H

to

Access prohibited

0000AD

Flash memory control

status register

0000AE^H

0000AF^H

FMCS

TMCS

R/W 1 Mbit flash memory 0 0 0 0 0 0 0 0^B

Clock division

Time clock output control register

R/W

XXXXX 0 0 0^B

for time clock

Interrupt control register 00 (for writing) W, R/W

Interrupt control register 00 (for reading) R, R/W

Interrupt control register 01 (for writing) W, R/W

Interrupt control register 01 (for reading) R, R/W

Interrupt control register 02 (for writing) W, R/W

Interrupt control register 02 (for reading) R, R/W

Interrupt control register 03 (for writing) W, R/W

Interrupt control register 03 (for reading) R, R/W

Interrupt control register 04 (for writing) W, R/W

Interrupt control register 04 (for reading) R, R/W

Interrupt control register 05 (for writing) W, R/W

Interrupt control register 05 (for reading) R, R/W

0 0 0 0 0 1 1 1^B

XX 0 0 0 1 1 1^B

0 0 0 0 0 1 1 1^B

XX 0 0 0 1 1 1^B

0 0 0 0 0 1 1 1^B

XX 0 0 0 1 1 1^B

0 0 0 0 0 1 1 1^B

XX 0 0 0 1 1 1^B

0 0 0 0 0 1 1 1^B

XX 0 0 0 1 1 1^B

0 0 0 0 0 1 1 1^B

0000B0^H

0000B1^H

0000B2^H

0000B3^H

0000B4^H

0000B5^H

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

Interrupt

XX 0 0 0 1 1 1^B

(Continued)

18

MB90M405 Series

Abbreviated

Register

Name.

Read/

Write

Address

Register name

Resource Name

Initial Value

Interrupt control register 06 (for writing) W, R/W

Interrupt control register 06 (for reading) R, R/W

Interrupt control register 07 (for writing) W, R/W

Interrupt control register 07 (for reading) R, R/W

Interrupt control register 08 (for writing) W, R/W

Interrupt control register 08 (for reading) R, R/W

Interrupt control register 09 (for writing) W, R/W

Interrupt control register 09 (for reading) R, R/W

Interrupt control register 10 (for writing) W, R/W

Interrupt control register 10 (for reading) R, R/W

Interrupt control register 11 (for writing) W, R/W

Interrupt control register 11 (for reading) R, R/W

Interrupt control register 12 (for writing) W, R/W

Interrupt control register 12 (for reading) R, R/W

Interrupt control register 13 (for writing) W, R/W

Interrupt control register 13 (for reading) R, R/W

Interrupt control register 14 (for writing) W, R/W

Interrupt control register 14 (for reading) R, R/W

Interrupt control register 15 (for writing) W, R/W

Interrupt control register 15 (for reading) R, R/W

0 0 0 0 0 1 1 1^B

XX 0 0 0 1 1 1^B

0 0 0 0 0 1 1 1^B

XX 0 0 0 1 1 1^B

0 0 0 0 0 1 1 1^B

XX 0 0 0 1 1 1^B

0 0 0 0 0 1 1 1^B

XX 0 0 0 1 1 1^B

0 0 0 0 0 1 1 1^B

XX 0 0 0 1 1 1^B

0 0 0 0 0 1 1 1^B

XX 0 0 0 1 1 1^B

0 0 0 0 0 1 1 1^B

XX 0 0 0 1 1 1^B

0 0 0 0 0 1 1 1^B

XX 0 0 0 1 1 1^B

0 0 0 0 0 1 1 1^B

XX 0 0 0 1 1 1^B

0 0 0 0 0 1 1 1^B

XX 0 0 0 1 1 1^B

0000B6H

0000B7^H

0000B8^H

0000B9^H

0000BA^H

0000BB^H

0000BC^H

0000BD^H

0000BE^H

0000BF^H

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

Interrupt

0000C0^H

to

0000FF^H

Unused area

RAM area

000100^H

to

0010FF^H

001100^H

to

FL000 to 255 Data RAM for display

R/W

FL control circuit

XXXXXXXX^B

0011FF^H

001200^H

to

Reserved area

001FEF^H

(Continued)

19

MB90M405 Series

(Continued)

Abbreviated

Register

Name.

Read/

Write

Address

Register name

Resource Name

Initial Value

Program address detection register

(low-order)

001FF0^H

001FF1^H

001FF2^H

001FF3^H

001FF4^H

001FF5^H

R/W

XXXXXXXX^B

Program address detection register

(middle-order)

PADR0

PADR1

Program address detection register

(high-order)

Address match

detection function

Program address detection register

(low-order)

Program address detection register

(middle-order)

Program address detection register

(high-order)

001FF6^H

to

Unused area

001FFF^H

Read/Write symbols used :

R/W : Read/write enabled

R : Read only

W : Write only

Default value symbols used :

0 : Default value is “0”

1 : Default value is “1”

X : Default value is undefined

20

MB90M405 Series

■ INTERRUPT, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

Interrupt Control

Register

Interrupt Vector

2

EI OS

Interrupt

Priority

Support

NO.*

#08

Address

ICR

⎯

Address

⎯

Reset

×

08^H

09^H

0A^H

0B^H

0D^H

0F^H

10^H

11^H

12^H

⎯

FFFFDC^H

FFFFD8^H

FFFFD4^H

High

INT9 instruction

Exception

#09

#10

#11

#13

#15

#16

#17

#18

#20

#21

#23

#24

#25

#26

#27

#29

#31

#33

#34

#35

#36

#37

#38

#39

#40

#41

#42

⎯

DTP/external interrupt ch 0

DTP/external interrupt ch 1

Serial I/O ch 2

FFFFD0^HICR00

FFFFC8^HICR01

0000B0^H

0000B1^H

FFFFC0^H

ICR02

0000B2^H

0000B3^H

DTP/external interrupt ch 2/3

Serial I/O ch 3

FFFFCC^H

FFFFB8^H

ICR03

16-bit free-run timer

Reserved

FFFFB4^H

⎯

FFFFAC^HICR04

FFFFA8^HICR05

0000B4^H

0000B5^H

16-bit reload timer ch 2

16-bit reload timer ch 0

16-bit reload timer ch 1

Input capture ch 0

15^H

17^H

18^H

19^H

1A^H

⎯

FFFFA0^H

ICR06

0000B6^H

0000B7^H

FFFF9C^H

FFFF98^H

ICR07

Input capture ch 1

FFFF94^H

Reserved

⎯

×

FFFF90^HICR08

FFFF88^HICR09

FFFF80^HICR10

0000B8^H

0000B9^H

0000BA^H

Output comparison match

Reserved

1D^H

⎯

×

Timebase timer

21^H

⎯

FFFF78^H

ICR11

0000BB^H

0000BC^H

0000BD^H

0000BE^H

0000BF^H

Reserved

⎯

FFFF74^H

UART0 reception complete

UART0 transmission complete

A/D converter conversion complete

I²C interface

23^H

24^H

25^H

26^H

27^H

28^H

29^H

2A^H

FFFF70^H

ICR12

FFFF6C^H

FFFF68^H

ICR13

FFFF64^H

UART1 reception complete

UART1 transmission complete

Flash memory status

Delayed interrupt output module

FFFF60^H

ICR14

FFFF6C^H

×

FFFF58^H

ICR15

FFFF54^H

Low

: Supported

× : Not supported

: Supported, includes EI²OS stop function

: Available if interrupt that shares the same ICR is not used

* : If two interrupts of the same level are output simultaneously, the interrupt with the lower interrupt vector number

has priority.

21

MB90M405 Series

■ PERIPHERAL FUNCTIONS

1. I/O Ports

There are a maximum of 26 I/O ports (parallel I/O ports) , which are also used as resource I/O pins (peripheral

function I/O pins) .

• I/O Port Functions

There are two kinds of I/O port : port direction registers (DDRs) and port data registers (PDRs) . The port direction

register (DDR) can set port pin I/O at the bit level. The port data register (PDR) sets output data to the port pins.

If the port direction register (DDR) sets the I/O port pin to input, the port pin level value can be read by reading

the port data register (PDR) . If the port direction register (DDR) sets the I/O port pin to output, the port data

register (PDR) value is output to the port pin. Below is a list of the functions of each I/O port, and dual use

resources.

• Port 8 : I/O port/resource use (external interrupt input pin, ICU, UART)

• Port 9 : I/O port/resource use (I²C, serial I/O ch3)

• Port A : I/O port/resource use (A/D converter, time clock output)

• Port B : I/O port/resource use (A/D converter, serial I/O ch2, external interrupt input pin, reload timer ch0)

I/OPort

Name

Input

Format Format

Output

Pin Name

Function

I/O Port P87 P86 P85 P84 P83 P82 P81 P80

Port 8 P80 to P87

CMOS

IC1

IC0

Resource SO1 SC1 SI1 SO0 SC0 SI0

INT1 INT0

P91 P90

SCL SDA

SC3 SO3

I/O Port

⎯

P90/SDA/

Port 9 SO3, P91/

SCL/SC3

N-ch

open

drain

Resource

CMOS

(hystere-

sis)

I/O Port PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

PA0/AN0/

TMCK to

PA7/AN7

Port A

AN0

Resource AN7 AN6 AN5 AN4 AN3 AN2 AN1

TMCK

CMOS I/O Port PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8

PB0/AN8 to

Port B PB7/AN15/

INT3

Resource

SO2 SC2

TO0 TIN0

INT3 INT2

SI2

⎯

Note: If port A and port B are also used as analog input pins, and are being used as I/O ports, then in addition to

the ports A and B direction registers (DDR A/B) and ports A and B data registers (PDR A/B) , set both analog

input enable register 0 and 1 (ADER 0/1) to “00^H”. Upon reset, analog input enable registers 0 and 1 are set

to “FF^H” by default.

22

MB90M405 Series

• Block Diagram for Port 8 Pins

Resource input

PDR8 read

PDR8 write

Input buffer

I/O selection

circuit

PDR8

DDR8

Output buffer

Port 8 pin

Standby control (LPMCR : SPL = "1")

I/O control circuit

Resource output

• Block Diagram for Port 9 Pins

PDR9 read

I/O selection

circuit

PDR9

Output buffer

PDR9 write

Port 9 pin

Standby control (LPMCR : SPL = "1")

DDR9

23

MB90M405 Series

• Block Diagram for Port A Pins

A/D converter

Analog input signal

ADER0

PDRA read

PDRA

Input buffer

I/O selection

circuit

Output buffer

PDRA write

Port A pin

Standby control (LPMCR : SPL = "1")

DDRA

• Block Diagram for Port B Pins

Resource input

A/D converter

Analog input signal

ADER1

PDRB read

PDRB

Input buffer

I/O selection

circuit

Output buffer

Port B pin

PDRB write

Standby control (LPMCR : SPL = "1")

DDRB

I/O control circuit

Resource output

24

MB90M405 Series

2. Serial I/O

Serial I/O allows data transfer via synchronization with a clock consisting of two 8-bit channels. In addition, LSB

first or MSB first can be selected for data transfer.

• Overview of Serial I/O

There are two types of serial I/O operation mode :

• Internal shift clock mode

Data is transferred in synchronization with internal clock (communication prescaler)

• External shift clock mode

Data is transferred in synchronization with clock input from external pin (SC) . In this mode, it is also possible

to transfer data via CPU instructions (port inversion instruction execution timing) by manipulating the general-

purpose port sharing the external pin (SC) .

• Block Diagram of Serial I/O

Internal data bus

(MSB first) D0 to D7

D0 to D7 (LSB first)

Transference direction selection

SI0, SI1

Read

Write

SDR (serial data register)

SO0, SO1

SC0, SC1

Shift clock

counter

Control circuit

Internal clock

(Communication prescaler control register (CDCR) )

2

1

0

SMD2 SMD1 SMD0 SIE

SIR BUSY STOP STRT MODE BDS SOE SCOE

Interrupt

request

Internal data bus

25

MB90M405 Series

3. Timebase Timer

The timebase timer is a 18-bit free-run counter that counts up in synchronization with the main clock. The timer

has an interval timer function capable of setting four different intervals, and a function for supplying clocks to the

oscillator stabilization standby timer, watchdog timer, and time clock output circuit.

• Interval timer function

The interval timer function sends an interrupt request at set intervals.

• When the timebase timer counter’s interval timer counter overflows, an interrupt request is output.

• One of four intervals can be set for the interval timer.

Main Clock Cycle

Interval Times

2¹²/HCLK (Approx. 1.02 ms)

2¹⁴/HCLK (Approx. 4.09 ms)

2¹⁶/HCLK (Approx. 16.38 ms)

2¹⁹/HCLK (Approx. 131.1 ms)

2/HCLK (0.5 µs)

HCLK : Oscillator clock frequency

Values in parentheses ( ) are when oscillator clock frequency is 4 MHz.

• Clock Supply Function

The clock supply function supplies operation clocks to the oscillation stabilization standby timer and some

peripheral functions.

Clock Supply Destination

Clock Cycles

Remarks

Oscillation stabilization standby for ce-

ramic oscillator

2¹³/HCLK (Approx. 2.05 ms)

Oscillation stabilization standby

2¹⁵/HCLK (Approx. 8.2 ms)

2¹⁸/HCLK (Approx. 65.53 ms)

2¹²/HCLK (Approx. 1.02 ms)

2¹⁴/HCLK (Approx. 4.1 ms)

2¹⁶/HCLK (Approx. 16.38 ms)

2¹⁹/HCLK (Approx. 131.07 ms)

Oscillation stabilization standby for

crystal oscillator

Watchdog timer

Count-up clock for watchdog timer

HCLK : Oscillator clock frequency

Values in parentheses ( ) are when oscillator clock frequency is 4 MHz.

Reference : Immediately after oscillation begins, the oscillation cycles are unstable; oscillation stabilization standby

is a rough measure of the time for oscillation to become stable.

26

MB90M405 Series

• Block Diagram of Timebase Timer

To PPG timer

To watchdog timer

Timebase timer counter

× 2¹× 2²× 2³

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

Main clock

OF

Clock controller

Wait for oscillator stabilization

To time selector

Power-on reset

Counter clear

circuit

Transition to stop mode

Interval timer

selector

CKSCR : MCS = "1"

"0"*¹

TBOF

set

TBOF clear

Timebase timer register Reser-

(TBTC)

⎯

TBIE TBOF TBR TBC1 TBC0

ved

Timebase timer interrupt signal

#34 (22^H)*²

⎯

: Undefined bit

OF : Overflow

*1 : Switching of machine clock from main clock to PLL clock

*2 : Interrupt number

27

MB90M405 Series

4. Watchdog Timer

The watchdog timer is a two-bit timer that uses the output of the timebase timer as a count clock. When the

watchdog timer is started, if it is not cleared within the set interval, the CPU is reset.

• Watchdog Timer Function

The watchdog timer detects runaway programs. When the watchdog timer is started, it must be cleared within

a set interval. If a program enters an infinite loop, or for some other reason the watchdog timer is not cleared

within the minimum time, a watchdog reset is generated to the CPU, sending it to a reset state. The watchdog

timerintervalissetbytheintervaltimesettingbits(WT1andWT0)ofthewatchdogtimercontrolregister (WDTC).

Interval Times

WT1

WT0

Minimum*

Maximum*

Oscillator clock cycles

2¹⁴2¹¹cycles

0

1

0

1

0

1

Approx. 3.59 ms

Approx. 4.61 ms

Approx. 14.33 ms Approx. 18.43 ms

Approx. 57.34 ms Approx. 73.74 ms

Approx. 458.76 ms Approx. 589.82 ms

2¹⁶2¹³cycles

2¹⁸2¹⁵cycles

2²¹2¹⁸cycles

* : When oscillator clock frequency is 4 MHz.

Reference : After the watchdog timer is started, it can be halted via a power-on reset, or a reset by the watchdog

timer. While an external reset, internal reset, setting the watchdog control bit (WTE) of the watchdog

timer control register (WDTC) , or going to sleep or stop mode can clear the watchdog timer, these

actions will not change the watchdog function setting, or halt the watchdog timer.

Note: The watchdog timer is made up of a two-bit timer that counts the carry signal of the timebase timer. Because

the watchdog timer uses the carry signal of the timebase timer, if the timebase timer is cleared, then the

watchdog reset interval may be longer than the set time.

• Block Diagram of Watchdog Timer

Watchdog timer control register (WDTC)

PONR

⎯

WRST ERST SRST WTE WT1 WT0

2

Watchdog timer

Clear and start

Clear

Over

flow

Sleep mode start

Hold status start

Stop mode start

Timer clear

control

circuit

Watchdog reset

generation circuit

To inter reset

generation circuit

2-bit

counter

Count clock

selector

Clear

4

Clear

(Timebase timer counter)

× 2¹× 2²× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

Main clock

⎯ : Undefined bit

28

MB90M405 Series

5. 16-bit Reload Timer

The MB90M405 series has 3 built-in 16-bit reload timer channels. They can be configured with the following

clock modes and counter operation modes :

• Clock Modes

• Internal Clock Mode : In this mode, the timer counts down in synchronization with the internal clock

• Event Count Mode : In this mode, the timer counts down in accordance with external input pulses

• Counter Operation Modes

• Reload Mode : In this mode, the count setting is reloaded, and the count is repeated

• One-shot Mode : In this mode, the count is halted due to an underflow

• 16-bit Reload Timer Operation Modes

Clock Mode

Counter Operation Mode

Reload mode

Operation Mode

Software trigger operation

External trigger operation

External gate input operation

Internal Clock Mode

One-shot mode

Reload mode

Event Count Mode

(External Clock Mode)

Software trigger operation

One-shot mode

• Internal Clock Mode

When the count clock setting bits (CSL1, CSL0) of the timer control status register (TMCSR) are set to “00^B”,

“01^B”, or “10^B”, the mode is set to internal clock mode. In internal clock mode, the following operation modes can

be set :

• Software trigger operation

If the count enable bit (CNTE) of the timer control status register (TMCSR) is set to “1”, setting the software

trigger bit (TRG) to “1” will initiate count operation.

• External trigger input operation

If the count enable bit (CNTE) of the timer control status register (TMCSR) is set to “1”, then when a valid edge

(rising, falling, or both edges can be set) set beforehand in the operation mode setting bits (MOD2, MOD1,

MOD0) is input to the TIN pin, count operation is initiated.

• External gate input operation

If the count enable bit (CNTE) of the timer control status register (TMCSR) is set to “1”, then count operation

is conducted while a valid gate input level (“L” or “H” can be set) set beforehand in the operation mode setting

bits (MOD2, MOD1, MOD0) is input to the TIN pin.

• Event Count Mode (External Clock Mode)

When the count clock setting bits (CSL1, CSL0) of the timer control status register (TMCSR) are set to “11^B”,

the mode is set to event count mode (external clock) . If the count enable bit (CNTE) is set to “1”, then when a

valid edge (rising, falling, or both edges can be set) set in the operation mode setting bits (MOD2, MOD1, MOD0)

is input to the TIN pin, count operation is initiated. If an external clock is input at set intervals, then it can also

be used as an interval timer.

29

MB90M405 Series

• Counter Operation

• Reload mode

When the 16-bit down counter underflows (“0000^H” to “FFFF^H”) , the value of the 16-bit reload register (TMRLR)

is loaded into the 16-bit down counter, and count operation is conducted. In addition, when an underflow occurs

an interrupt request is output, so this can also be used as an interval timer. It is possible to output the inverted

toggle waveform from the TO pin with each underflow.

Count Clock

Count Clock Cycle

2¹/φ (0.125 µs)

2³/φ (0.5 µs)

Interval Time

0.125 µs to 8.192 ms

0.5 µs to 32.768 ms

2.0 µs to 131.1 ms

0.5 µs +

Internal Count Clock

2⁵/φ (2.0 µs)

2³/φ+ (0.5 µs)

External Count Clock

φ : Machine clock frequency

Values in parentheses ( ) are when machine clock frequency is 16 MHz.

• One-shot mode

When the 16-bit down counter underflows (“0000^H” to “FFFF^H”) , count operation is halted.

Reference :

• 16-bit reload timer 0 can be used to create the UART baud rate.

• 16-bit reload timer 1 can be used as the start trigger for the A/D converter.

• 16-bit Reload Timer Interrupts and EI²OS

When the 16-bit down counter underflows (“0000^H” to “FFFF^H”) , an interrupt request is output.

Interrupt Control Register

Vector Table Address

Interrupt

No.

EI²OS

Channel

Register Name

Address

0000B6^H

0000B5^H

Lower

Upper

Bank

16-bit reload timer 0 #23 (17^H)

16-bit reload timer 1 #24 (18^H)

16-bit reload timer 2 #21 (15^H)

FFFFA0^H

FFFF9C^H

FFFFA8^H

FFFFA1^H

FFFF9D^H

FFFFA9^H

FFFFA2^H

FFFF9E^H

FFFFAA^H

ICR06

ICR05

: Available if interrupt factors sharing ICR are not used

30

MB90M405 Series

• Block Diagram of 16-bit Reload Timer

Internal data bus

TMRLR

16-bit reload register

Reload signal

Reload

control circuit

TMR

UF

16-bit timer register (down counter)

CLK

Count clock generation circuit

Gate

input

Effective

clock

decision

circuit

Machine

clock

φ

3

Wait signal

Prescaler

Clear

UART*¹

To A/D converter*²

CLK

Output control circuit

Internal

clock

Output signal

Input

control

circuit

Clock

selector

generation circuit

Re-

verse

EN

External

clock

Select

signal

3

2

Operation

control

circuit

Function selection

⎯

CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG

Timer control status register (TMCSR)

Interrupt request signal

*1 : ch 0

*2 : ch 1

31

MB90M405 Series

6. 16-bit I/O Timers

The16-bitI/Otimercanperformdualindependentwaveformoutput, inputpulsewidthmeasurement, andexternal

clock cycle measurement, based on the 16-bit freerun timer.

• 16-bit freerun timer (1 channel)

The 16-bit freerun timer is made up of a 16-bit up counter (timer counter data register (TCDT) ) , timer counter

control status register (TCCS) , and prescaler. The counter output value of the 16-bit freerun timer is used as

the base timer for output comparison and input capture.

• Counter operation clock (4 different settings available)

4 internal clock types : φ/4, φ/16, φ/32, φ/64

φ : Machine clock frequency

• Interrupt

An interrupt can be output to the CPU when the counter value overflows, or when it matches the value of

comparison register 0.

• Initialize

When a reset is input, if the software reset bit is cleared to “0”, or if the values of comparison register 0 and

the freerun timer count match, the counter value can be initialized to “0000^H”.

• Output compare (1 channel)

The output comparison module consists of a 1-channel 16-bit comparison register, and control register. If the

value of the 16-bit freerun timer and that of the compare register match, an interrupt request can be output to

the CPU.

• Input capture (2 channels)

The input capture module consists of a capture register and a control register. Both support two independent

external input pin channels. The capture register can store the value of the 16-bit freerun timer. Additionally, the

register can detect signal input edges from external pins, and simultaneously output interrupts to the CPU.

• The detection edge of the external input signal can be configured (rising edge, falling edge, both edges)

• The two input capture channels can operate independently

Interrupts can be output upon detection of a valid edge in an external input signal

• Input capture interrupts start the extended intelligent I/O service

32

MB90M405 Series

• Block Diagram of 16-bit I/O Timer

Interrupt request

φ

IVF IVFE STOP MODE CLR CLK1 CLK0

(TCCS)

Divider

Comparator 0

16-bit freerun timer

Clock

(Timer counter data register TCDT)

Count value output (T15 to T00)

Compare control

Compare register 0 (2)

⎯

ICP0

⎯ ICE0

Compare 0 (2)

interrupt

Controller

Each

control block

Edge detection

Capture data register 0

IC0

EG11EG10EG01EG00

Edge detection

IC1

Capture data register 1

ICP1 ICP0 ICE1 ICE0

Capture interrupt

33

MB90M405 Series

7. UART

The UART is a general-purpose serial data communications interface for both synchronous and asynchronous

(start-stop synchronization) communications with external devices. Two types of communication are available:

two-way communication (normal mode) and master/slave communication (multiprocessor mode; only the master

side is supported) .

• UART Functions

The UART is a general-purpose serial data communications interface for sending and receiving serial data to

and from other CPUs and peripheral devices. It provides the following functions:

Function

Data Buffer

Full-duplex double buffer

• Clock-synchronous (no start/stop bit)

• Clock-asynchronous (start-stop synchronization)

Transfer Mode

• Max 2 MHz (with machine clock at 16 MHz)

• Baud rate via dedicated baud rate generator

• Baud rate via external clock (SC pin input clock)

• Baud rate via internal clock (clock supplied from 16-bit reload timer)

• Total of 8 types of baud rate may be set

Baud Rate

• 7 bits (in asynchronous normal mode only)

• 8 bits

Data Length

Signal Format

NRZ (Non Return to Zero)

• Framing errors

Receive Error Detection

• Overrun errors

• Parity errors (undetectable in multiprocessor mode)

• Receive interrupts (receive complete, receive error detection)

• Send interrupts (send complete)

• Extended intelligent I/O service (EI²OS) supported for both sending and receiv-

Interrupt Requests

ing

Master/Slave

Communications Function

(Multiprocessor Mode)

Enables 1 (master) to n (slave) communication

(Only master side supported)

Note : The UART does not add a start or stop bit during clock-synchronous transfer. Only the data is forwarded.

Data Length

Operation Mode

Normal Mode

Synchronization Stop Bit Length

No Parity

With Parity

0

1

2

7 bits or 8 bits

Asynchronous

1 bit or 2 bits*²

Asynchronous

Multiprocessor Mode

Normal Mode

8 + 1*¹

⎯

8

Synchronous

None

⎯ : Not available

*1 : “+1” is the address/data setting bit (A/D) used for communications control.

*2 : During reception, only a stop bit length of 1 can be detected.

34

MB90M405 Series

• Block Diagram of UART

Control bus

Receive

interrupt signal

Dedicated baud rate

generator

Transmission

interrupt signal

Transmit clock

Clock

16-bit reload timer 0

selector

Receive clock

Receive

control circuit

Transmission

control circuit

Start bit

Transmission

detection circuit

start circuit

Receive

bit counter

Transmission

bit counter

Transmission

parity counter

Receive

parity counter

Receive shift

register

Transmission shift

register

Receive

complete

Transmission start

SIDR0/SIDR1

SODR0/SODR1

Receive error

detection signal

for EI²OS

Receive status

evaluation circuit

(to CPU).

Internal data bus

PEN

P

SBL

CL

A/D

REC

RXE

TXE

PE

MD1

MD0

CS2

CS1

CS0

ORE

FRE

RDRF

TDRE

BDS

RIE

SMR0/

SMR1

Register

SCR0/

SCR1

Register

SSR0/

SSR1

Register

SCKE

SOE

TIE

35

MB90M405 Series

8. DTP/External Interrupt Circuit

The DTP (Data Transfer Peripheral) /external interrupt circuit detects interrupt requests input from the external

interrupt input pin, and outputs interrupt requests.

• DTP/External Interrupt Function

The DTP/external interrupt circuit outputs interrupt requests upon detection of an edge input from the external

interrupt input pin, or a level signal. Interrupt requests are accepted by the CPU, and if extended intelligent I/O

service (EI²OS) is enabled, the CPU conducts automated data transfer (DTP function) via EI²OS, then branches

into an interrupt processing routine. If EI²OS is disabled, the CPU branches into an interrupt processing routine,

without starting automated data transfer (DTP function) via EI²OS.

External Interrupt Function

DTP Function

Input pins

4 channels (P80/INT0, P81/INT1, PB6/INT2, PB7/INT3)

The level or edge to detect can be set independently for each pin in the detection level

setup register (ELVR)

Interrupt conditions

“L” level/“H” level input

Rising edge/falling edge input

Interrupt number

Interrupt control

Interrupt flag

#11 (0B^H), #13 (0D^H) , #16(10^H)

Enable/disable interrupt request output in the DTP/external interrupt enable register

(ENIR)

The DTP/interrupt factor register (EIRR) stores interrupt conditions.

Set EI²OS to disabled

(ICR : ISE = “0”)

Set EI²OS to enabled

(ICR : ISE = “1”)

Processing selection

Branch to interrupt processing routine after

automatic data transfer by EI²OS completes.

Operation

Branch to interrupt processing routine

ICR : Interrupt Control Register

• DTP/External Interrupt Circuit Interrupts and EI²OS

Interrupt Control Register

Vector Table Address

Channel

Interrupt No.

EI²

OS

Register Name

ICR00

Address

0000B0^H

0000B1^H

Lower

Upper

Bank

INT0

INT1

INT2

INT3

#11 (0B^H)

#13 (0D^H)

FFFFD0^H

FFFFC8^H

FFFFD1^H

FFFFC9^H

FFFFD2^H

FFFFCA^H

ICR01

#16 (10^H)

ICR02

0000B2^H

FFFFBC^H

FFFFBD^H

FFFFBE^H

36

MB90M405 Series

• Block Diagram of DTP/External Interrupt Circuit

Request level setting register (ELVR)

⎯

LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

Selector

INT0

Selector

INT1

Selector

INT2

Selector

INT3

⎯

⎯ ER3 ER2 ER1 ER0

Interrupt request

⎯

⎯ EN3 EN2 EN1 EN0

• DTP/External Interrupt Input Detection Circuit

If a signal input to the external interrupt input pin matches the level set in the request level setting register

(ELVR) or edge, the DTP/external interrupt factor flag bit (EIRR : ER3 to ER0) corresponding to the external

interrupt input pin is set to “1”.

• Request Level Setting Register (ELVR)

The interrupt request detection conditions (level or edge) are set for each external interrupt input pin

• DTP/External Interrupt Factor Register (EIRR)

Stores and clears interrupt factors

• DTP/External Interrupt Enable Register (ENIR)

Interrupt requests are enabled/disabled for each external interrupt input pin.

37

MB90M405 Series

9. I²C Interface

The I²C interface is a serial I/O port that supports the Inter IC BUS. It operates as a master/slave device on an

I²C bus, with the following features :

• I²C Interface Features

The MB90M405 series has one I²C interface channel.

Below are features of the I²C interface :

• Master/slave send/receive

• Arbitration function

• Clock synchronization function

• Slave address/general call address detection function

• Transfer direction detection function

• Start condition loop generation and detection function

• Bus error detection function

• Transfer rates of up to 100 Kbps supported

38

MB90M405 Series

• Block Diagram of I²C Interface

ICCR

I²C enable

Clock divider 1

EN

Machine clock

5

6

7

8

ICCR

CS4

CS3

Clock selection 1

Clock divider 2

2 4 8 16 32 64 128 256

CS2

CS1

CS0

Sync

Shift clock generation

Clock selection 2

Shift clock edge

change timing

IBSR

BB

Bus busy

Repeat start

Last bit

RSC

LRB

TRX

FBT

AL

Start stop condition detection

Transmission/

Receive

Error

First Byte

Arbitration lost detection

IBCR

BER

BEIE

INTE

INT

SCL

SDA

Interrupt request

End

IRQ

IBCR

SCC

Start

Master

ACK

MSS

ACK

Start stop condition

generation

permission

GC-ACK

permission

GCAA

IDAR

IBSR

AAS

GCA

Slave

Slave address

compare

Global call

IADR

39

MB90M405 Series

10. 8/10 Bit A/D Converter

The 8/10 bit A/D converter has a function to convert analog input voltage to a 10 or 8-bit value using the RC

successive approximation conversion method.

• 8/10 Bit A/D Converter Functions

Below are the functions of the 8/10 bit A/D converter :

• The minimum conversion time is 6.125 µs (with machine clock frequency of 16 MHz, including sampling time)

• The minimum sampling time is 2 µs (with machine clock frequency of 16 MHz)

• The RC successive approximation conversion method with sample-hold circuit is used for conversion

• Resolution can be set to 10 or 8 bits

• Input signal programmable from 8-channel analog input pins

• When A/D conversion is completed, it is possible to output an interrupt request, and start EI²OS

• In an interrupt-enabled state, when A/D conversion is executed, a conversion data protection function is

invoked

• The conversion start factor can be set to software or 16-bit reload timer 1 output (rising edge)

The following 4 conversion modes are available :

Conversion Mode

Single Conversion Operation

Scan Conversion Operation

One-shot Conversion

Mode 1

The set channel performs conversion Multiple linked channels (up to 16 channels can

One-shot Conversion once, then stops

Mode 2

be set) perform conversion once, then stop

Continuous Conversion The set channel performs conversion Multiple linked channels (up to 16 channels can

Mode

repeatedly

be set) perform conversion repeatedly

The set channel performs conversion Multiple linked channels (up to 16 channels can

Stop Conversion

Mode

once, then pauses, and goes into

standby until started again

be set) perform conversion once, then pause,

and go into standby until started again

• 8/10 Bit A/D Converter Functions Interrupts and EI²OS

Interrupt Control Register

Interrupt No.

Vector Table Address

EI²OS

Register Name

Address

Lower

Upper

Bank

#37 (25^H)

ICR13

0000BD^H

FFFF68^H

FFFF69^H

FFFF6A^H

: Available

40

MB90M405 Series

• Block Diagram of 8/10 Bit A/D Converter

A/D control status

register

Interrupt request signal #37 (25^H) *

A/D cmversion channel setting register (ADMR)

(ADCS0/ADCS1)

Rese-

BUSY INT INTE PAUS STS1 STS0 STRT

MD1 MD0 ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0

8

rved

2

Decoder

16-bit reload

timer 1 output

Clock selector

φ

Comparator

Sample hold

Circuit

Control circuit

PB7/AN15

Analog

channel

selector

to

PA0/AN0

2

AVR

AV^CC

AVSS

D/A converter

A/D data register

(ADCR0/ADCR1)

S10 ST1 ST0 CT1 CT0

⎯

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

φ : Machine clock

* : Interrupt signal

• A/D control status register 0/1 (ADCS0/ADCS1)

The A/D control status register 1 (ADCS1) has functions to set the A/D conversion start factor, enable/disable

interrupt requests, check the status of interrupt requests, and check whether A/D conversion is halted/ongoing.

• A/D data register (ADCR0/ADCR1)

This register stores the results of A/D conversion. It has functions to set the A/D conversion resolution, A/D

conversion sampling time, and A/D conversion comparison time.

• A/D conversion channel setting register (ADMR)

Provides a function to set the A/D conversion start/stop channel

• Clock selector

This selector sets the A/D conversion start clock. The 16-bit reload timer 1 output can be set in the start clock.

• Decoder

This circuit sets the analog input pin to use from the setting of the A/D conversion end channel setting bit

(ANE0 to ANE3) and A/D conversion start channel setting bit (ANS0 to ANS3) of the A/D control status register

(ADCS0) .

41

MB90M405 Series

11. FL-control Circuit

The FL control circuit has a fluorescent tube automated display function and an LED automated display function.

The fluorescent tube automated display function is capable of up to 32 digits, and 60 combined segment and

digit automated display. The LED automated display function can output LED1 pin to LED16 pin at 1/2 duty, with

LED0 pin as common output.

• High voltage resistance output pins

• There are 60 onboard high voltage resistance output pins (FIP0 pin to FIP59 pin) .

• There are 34 high-current output pins (FIP0 pin to FIP33 pin) and 26 mid-current output pins (FIP34 pin to

FIP59 pin) .

• Pull-down resistance can be set for all high voltage-resistance output. Alternately, they can be combined.

• Fluorescent tube automated display function

• Has 32 × 60-bit display data RAM.

• The display timing can be set to between 1 and 32.

• 60 bits can be set for both digits and segments for each timing.

• The digit pins are FIP0 pin to FIP31 pin; from the pin set for digit start, the digits can be set in series for the

number of pins set in the digit number register.

• Segments can control up to 59 outputs.

• There are 4 types of display scan cycle (segment width) .

• Digit dimmer control controls the T on both sides of the digit for segment output. Adjustment is available in 7

steps (dimmer applied to all digits) .

• All digit and segment can be inverted.

• Segment output of an arbitrary timing is capable of gradated display (segment dimmer) . The T of both sides

of the segment are as follows :

Digit Dimmer Control

Digit output

Segment output

T

Segment Dimmer Control

Digit output

"H"

"L"

Output

Segment output

example

T

Note : Dimmer can be applied to a defined segment in the setup timing.

42

MB90M405 Series

• LED automated display function

• Pins between LED0 pin and LED16 pin not set to digits can be set as LED pins.

• As shown in the figure below, LED0 pin becomes common output, and LED1 pin to LED16 pin become LED

segment output.

• When LED0 pin is set to “H”, the values corresponding to LED1 pin to LED16 pin are output at the timing T1

in display data RAM; when LED0 pin is set to “L”, the values corresponding to LED1 pin to LED16 pin are

output at the timing T2 in display data RAM.

• 1/2 duty LED output can be obtained by externally inverting the LED0 pin common output.

• As shown below, the output timing of LED1 pin to LED16 pin from LED0 pin and the inverted signal of LED0

pin is 5.12 ms for LED0 pin, and 4.096 ms for LED1 pin to LED16 pin (when machine clock (peripheral operation

clock) frequency is 16 MHz) .

LED automated display timing

5.12 ms

4.096 ms 1.024 ms 4.096 ms

LED0 pin common output

Inverting output created

outside device

LED segment output from

LED1 pin to LED16 pin

T1

T2

T1

T2

43

MB90M405 Series

• Block Diagram of FL Control Circuit

FLST

Control circuit

FLC1

S

W

LED controller

FIP controller

Width setting

FLC2

Inverting output,

timing No. setup

Digit

Segment

Dimmer width

setting

FLDG

FLDC

Start pin

setting

Number setting

Dimmer width

setting

Dimmer

applicable

SEGD

segment setting

RAM for

display data

32 × 60 bit

34 large current

Pch Tr

Timing selection

for setting

segment dimmer

SEGDT

32 × 1 bit

Two intermediate

current Pch Tr

24

FLPD

44

MB90M405 Series

12. Time Clock Output

The time clock output circuit divides the oscillator clock by means of the timebase timer, and outputs the set

division clock. Can be set to 1/32, 1/64, 1/128, or 1/256 of oscillator clock.

• Time clock output circuit

The timer clock output circuit is disabled in reset and stop modes. It is enabled in normal run modes, sleep mode,

and pseudo clock mode.

PLL_Run

Main_Run

Sleep

Pseudo Clock

STOP

Reset

Operating

State

×

If the timebase timer is cleared while the time clock output circuit is in use, clock output cannot be conducted

normally.

• Block Diagram of Time Clock Output Circuit

Time clock selection circuit

X0

X1

Selector

Time clock output

Oscillator

Timebase timer

Divide-by-two

circuit

45

MB90M405 Series

13. Delayed Interrupt Generation Module

The delayed interrupt generation module outputs task switching interrupt requests. When the delayed interrupt

generation module is used, it is possible to output interrupt requests and releases to an MB90M405 series CPU

via the software for task switching.

• Block Diagram of Delayed Interrupt Generation Module

Delayed interrupt request generation/reset decoder

Interrupt factor latch

46

MB90M405 Series

14. Address Match Detection Function

If a program address matches the value set in the address match detection register, the instruction code read

into the CPU is changed to an INT9 instruction code. It is possible to realize a program patch assignment function

by processing an INT #9 interrupt routine.

• Block Diagram of Address Match Detection Function

Address latch

Address detection register

MB90M405

Series

Acknowledge bit

CPU core

47

MB90M405 Series

15. ROM Mirror Function Selection Module

The ROM Mirror Function Selection Module allows the ROM data of bank FF to be viewed from bank 00, by

setting the ROM mirror function selection module register. Using the ROM mirror function makes it possible to

access the corresponding area (“FF4000^H” to “FFFFFF^H”) from the I/O and RAM areas, without crossing banks.

• Block Diagram of ROM Mirror Function Selection Module

ROM mirror function selection register (ROM)

Address space

Address

FF bank

00 bank

Data

ROM

48

MB90M405 Series

16. 1 Mbit Flash Memory

The 1 Mbit flash memory is arrayed on the CPU memory map in banks FE^Hto FF^H. It allows read and program

access from the CPU in the same manner as mask ROM. Data is written to and deleted from flash memory by

means of instructions from the CPU, via the flash memory interface circuit. This allows the implementation state

to be overwritten via onboard CPU control, allowing programs and data to be modified efficiently.

• 1 Mbit Flash Memory Length

• 128 Kword × 8/64 Kword × 16 bit (16 K + 8 K + 8 K + 32 K + 64 K) sector configuration.

• Automated program algorithm (same as Embedded Algorithm* : MBM29F400TA)

• Built-in deletion pause/resume function

• Write/deletion completion detection by CPU interrupt

• JEDEC standard command compatible

• Sector-by-sector deletion possible (sectors can be combined freely)

• Write/deletion guaranteed through 10,000 iterations

* : Embedded Algorithm is a trademark of Advanced Micro Device.

• Method for Writing to and Deleting Flash Memory

There are two methods for writing to/deleting from flash memory :

1. Dedicated serial writer

(YDC AF220)

YDC: Yokogawa Digital Computer

2. Writing/deletion via program execution

It is not possible to simultaneously write to and read from flash memory. When writing to/deleting from flash

memory, programs in flash memory are temporarily copied to RAM, and run from there; this allows data to be

written to flash memory.

49

MB90M405 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(V^SS-CPU = V^SS-IO = AV^SS= 0.0 V)

Rating

Parameter

Signal

Unit

Remarks

Min

Max

V^CC-CPU V^SS− 0.3 V^SS+ 4.0

V^DD-FIP V^SS− 0.3 V^SS+ 4.0

V

Control circuit power pin

FIP power pin

V^CC≥ AV^CC*¹

Power Supply Voltage

AV^CC

V^SS− 0.3 V^SS+ 4.0

Power supply pin of pull-down side during

high voltage resistant output

V^KK

V^CC− 45 V^CC+ 0.3

V

V^I

V^I2

V^O

V^O2

V^SS− 0.3 V^SS+ 4.0

V^SS− 0.3 V^SS+ 5.5

V^SS− 0.3 V^SS+ 4.0

V^SS− 0.3 V^SS+ 5.5

V

*2

Input Voltage

*3

*2

Output Voltage

*3 (open drain output)

“L” Level Maximum

Output Current

I^OL

⎯

15

4

mA *4, *5

“L” Level Average

Output Current

Average value (operating current × oper-

ating rate) *⁵

I^OLAV

ΣI^OL

mA

“L” Level Maximum

Overall Output Current

100

50

mA *5

“L” Level Average

Overall Output Current

Average value (operating current × oper-

ating rate) *⁵

ΣI^OLAV

mA

I^OH

⎯

−15

−27

−14

mA *4, *5

“H” Level Maximum

Output Current

I^OHFIP1

I^OHFIP2

mA FIP0 to FIP33 pins

mA FIP34 to FIP59 pins

“H” Level Average

Output Current

Average value (operating current × oper-

I^OHAV

ΣI^OH

ΣI^OHAV

ΣI^OHFIPAV

⎯

−4

mA

ating rate) *⁵

“H” Level Maximum

Overall Output Current

−100

−50

mA *5

Average value (operating current × oper-

mA

ating rate) *⁵

“H” Level Average

Overall Output Current

Average value (operating current × oper-

−180

mA

ating rate) *⁶

P^D_CPU

P^D_FL

Ta

⎯

300

1176

+85

mW During CPU_Chip independent operation

Consumption Power

mW During FL_Chip independent operation

Operating Temperature

Storage Temperature

−40

−55

°C

Tstg

+150

*1 : Make sure that AVcc does not exceed V^CCwhen applying power, etc.

*2 : V^I, V^Omust not exceed V^CC+ 0.3 V.

*3 : 5 V voltage resistant pin for I²C. Only applies to P90/SDA and P91/SCL.

*4 : The standard for maximum output current is the peak value of a single corresponding pin.

*5 : Excludes current at pins FIP0 to FIP59.

50

MB90M405 Series

*6 : Corresponds to pins FIP0 to FIP59.

Note : V^CCin the standard signifies V^DD-FIP = V^CC-CPU. Also, use the 3 pins on the left at the same power level.

Here, V^SSsignifies V^SS-IO = V^SS-CPU. Please connect this pin to GND as well.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

2. Recommended Operating Conditions

(V^SS-IO = V^SS-CPU = AV^SS= 0.0 V)

Values

Parameter

Symbol

Unit

Remarks

Min

3.0

Max

3.6

V^CC-CPU

V

During normal operation

Power Voltage V^DD-FIP

3.0

3.6

During normal operation

V^CC

V^HIS

2.5

3.6

Save stop operation status

0.8 V^CC

V^CC− 0.3

V^SS− 0.3

V^CC+ 0.3

V^SS+ 5.0

V^CC+ 0.3

0.2 V^CC

V^SS+ 0.3

CMOS hysteresis input pin except I²C

I²C CMOS hysteresis input pin (5 V voltage resistant)

MD pin input

Input “H ” Volt-

age

V^HIS2

V^HIM

V^ILS

CMOS hysteresis input pin except I²C

I²C CMOS hysteresis input pin (5 V voltage resistant)

MD pin input

Input “ L” Volt-

age

V^ILS2

V^ILM

Operating

Ta

−40

+85

°C

Temperature

Note : V^CCin the standard signifies V^DD-FIP = V^CC-CPU. Also, use the 3 pins on the left at the same power level.

Here, Vss signifies V^SS-IO = V^SS-CPU. Please connect this pin to GND as well.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

51

MB90M405 Series

3. DC Standard

(Ta = −40 °C to +85 °C, V^DD-FIP = V^CC-CPU = AV^CC= 3.0 V to 3.6 V, V^SS-IO = V^SS-CPU = AV^SS= 0 V)

Value

Typ

⎯

Sym

bol

Parameter

Pin Name

Conditions

Unit

Remarks

Min

Max

⎯

V^OH5

V^OH4

V^OH3

V^OH2

V^OH1

I^OH5= −23 mA

I^OH4= −12 mA

I^OH3= −12 mA

I^OH2= −5 mA

I^OH1= −4 mA

V^CC− 2.5

V^CC− 1.3

V^CC− 2.0

V^CC− 1.0

⎯

V

FIP0 - FIP33

⎯

Output “H ”

Voltage

FIP34 - FIP59

SDA/SCL

⎯

5.5

Open drain pin

All output pins ex-

cept for the above

V^OH0

V^OL1

V^OL

I^OH= −2.0 mA

I^OL= 15 mA

I^OL= 2.0 mA

V^CC− 0.5 V^CC− 0.3

⎯

V

SDA/SCL

⎯

0.5

0.2

0.8

0.4

Output “ L”

Voltage

All output pins ex-

cept for the above

Input Leak

Voltage

V^CC= 3.0 V

All input pins

except FIP0 - FIP59

I^IL

−5

⎯

−1

⎯

+5

20

10

µA

(V^SS< V¹< V^CC)

V^KK=

V^CCto V^CC− 43

I^LO3

I^LO2

FIP0 - FIP33

FIP34 - FIP59

Output Leak

Voltage

V^KK=

V^CCto V^CC− 43

V^CC= 3.3 V

Internal frequency 16 MHz

During normal operation

MB90M407/A*

MB90M408/A*

⎯

32

37

40

45

50

mA

V^CC= 3.3 V

Internal frequency 16 MHz

During A/D operation

MB90M407/A*

MB90M408/A*

V^CC= 3.3 V

Internal frequency 16 MHz

During normal operation

I^CC

MB90MF408/A

MB90MV405*

Power Current

V^CC

V^CC= 3.3 V

Internal frequency 16 MHz

During A/D operation

MB90MF408/A

MB90MV405*

⎯

45

40

15

55

50

Flash memory

During write/deletion

mA MB90MF408/A

V^CC= 3.3 V

Internal frequency 16 MHz

During sleep

I^CCS

20

mA *

I^CCH

R^UP

During stop, Ta = +25 °C

⎯

15

65

µA

Pull-up

Resistance

RST

⎯

20

200 kΩ

R^DW1

MD2

⎯

20

80

65

200 kΩ

160 kΩ

Pull-down

Resistance

FIP0 - FIP59

When set

120

* : The standard current values do not include current consumption by the high voltage resistance pins. This

indicates the current consumption of the internal circuit.

52

MB90M405 Series

Notes: • V^CCinthestandardsignifiesV^DD-FIP= V^DD-VFT= V^CC-CPU. Also, usethe3pinsontheleftatthesamepower

level. Here, V^SSsignifies V^SS-IO = V^SS-CPU. Please connect this pin to GND as well.

• Current values are subject to change without notice, in order to affect improvements in characteristics, etc.

The power current measurement condition is the external clock.

• Scope of Guaranteed PLL Operation

Relationship between Internal Operation Clock Frequency and Power Voltage

PLL guaranteed operation range

3.6

3.0

1.5

3

16

Internal operating clock frequency fCP (MHz)

Relationship between Source Oscillation Clock Frequency and Internal Operating Clock Frequency

×4 ×3

×2

×1

16

12

9

8

No multiplier

6

4

3

2

1.5

3

4

6

8

12

16

Source oscillation clock fCH (MHz)

53

MB90M405 Series

4. AC Characteristics

(1) Clock Timings

(Ta = −40 °C to +85 °C, V^DD-FIP = V^CC-CPU = AV^CC= 3.0 V to 3.6 V, V^SS-IO = V^SS-CPU = AV^SS= 0 V)

Value

Sym

bol

Condi-

tion

Parameter

Pin Name

Unit

Remarks

Min

Typ

Max

3

16

× 1/2 (When PLL

stops)

3

16

3

16

8

PLL × 1

PLL × 2

PLL × 3

PLL × 4

Clock frequency

f^C

X0, X1

⎯

MHz

3

5.33

4

3

Clock cycle time

t^HCYL

X0, X1

X0

62.5

⎯

333

ns

⎯

P^WH

P^WL

Recommended duty

ratio = 30% to 70%

Input clock pulse width

10

⎯

5

tcr

tcf

When using an

external clock

Input clock rise/fall time

X0

⎯

ns

MHz

ns

Internal operating clock

frequency

f^CP

t^CP

1.5

62.5

16

666

Internal operating clock

cycle time

• X0 and X1 clock timing

tHCYL

0.8 VCC

0.2 VCC

X0

PWH

PWL

tcr

tcf

54

MB90M405 Series

(2) Reset

(Ta = −40 °C to +85 °C, V^DD-FIP = V^CC-CPU = AV^CC= 3.0 V to 3.6 V, V^SS-IO = V^SS-CPU = AV^SS= 0 V)

Value

Parameter

Symbol Pin Name Condition

Unit

Remarks

Min

Max

16 t^CP

⎯

ns In normal operation

ms In stop mode

Reset input time

t^RSTL

RST

⎯

Oscillator oscillation

⎯

time* + 16 t^CP

*: Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several

dozen ms; for a FAR/ceramic oscillator, this is several hundred µs to a few ms, and for an external clock this is 0 ms.

• In normal operation

tRSTL

RST

0.2 VCC

• In stop mode

t

RSTL

RST

0.2Vcc

90 % of

amplitude

X0

Internal

operation

clock

Oscillator

oscillation time

16 tCP

Oscillator stabilization wait time

Execution of the instruction

Internal

reset

55

MB90M405 Series

(3) Power-On Reset

(Ta = −40 °C to +85 °C, V^DD-FIP = V^CC-CPU = AV^CC= 3.0 V to 3.6 V, V^SS-IO = V^SS-CPU = AV^SS= 0 V)

Value

Condi-

tion

Parameter

Symbol Pin Name

Unit

Remarks

Min

0.05

4

Max

30

Power supply rise time

Power supply cutoff time

t^R

V^CC*

V^CC

ms

⎯

t^OFF

⎯

ms For repeated operation

* : V^CCmust be less than 0.2 V before power-on.

Notes : • The above rating values are for generating a power-on reset.

• Some internal registers are only initialized by a power-on reset. Always apply the power supply in

accordance with the above ratings if you wish to initialize these registers.

tR

2.7 V

0.2 V

VCC

0.2 V

tOFF

Sudden changes in the power supply voltage may cause a power-on reset.

The recommended practice if you wish to change the power supply voltage while the device is

operating is to raise the voltage smoothly as shown below. Also, changes to the supply voltage

should be performed when the PLL clock is not in use. The PLL clock may be used, however, if

the rate of voltage change is 1 V/s or less.

VCC

Recommended rate of voltage

rise is 50 mV/ms or less.

2.5 V

Maintain RAM data

VSS

56

MB90M405 Series

(4) Serial I/O

(Ta = −40 °C to +85 °C, V^DD-FIP = V^CC-CPU = AV^CC= 3.0 V to 3.6 V, V^SS-IO = V^SS-CPU = AV^SS= 0 V)

Value

Parameter

Symbol Pin Name

Condition

Unit Remarks

Min Max

Serial clock cycle time

t^SCYC

t^SLOV

t^IVSH

t^SHIX

SC0 to SC3

8 t^CP

⎯

ns

SC0 to SC3

SO0 to SO3

SCK ↓ → SOT delay time

−80

80

Internal shift clock

mode, output pin

load is

SC0 to SC3

SI0 to SI2

Valid SIN → SCK ↑

100

60

⎯

ns

C^L= 80 pF + 1 TTL

SC0 to SC3

SI0 to SI2

SCK ↑ → valid SIN hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

t^SLSH

SC0 to SC3

4 t^CP

⎯

ns

SC0 to SC3 External shift clock

SO0 to SO3 mode, output pin

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SLOV

t^IVSH

t^SHIX

⎯

60

150

⎯

ns

load is

C^L= 80 pF + 1 TTL

SC0 to SC3

SI0 to SI3

SC0 to SC3

SI0 to SI2

SCK ↑ → valid SIN hold time

⎯

Notes : • Above rating is the case of CLK synchronous mode.

• C^Lis the load capacitor connected to the pin for testing.

• t^CPis the machine cycle period (unit = ns)

57

MB90M405 Series

• Internal shift clock mode

tSCYC

SC

2.4 V

0.8 V

tSLOV

2.4 V

0.8 V

SO

SI

tIVSH

tSHIX

0.8 V^CC

0.2 VCC

0.8 VCC

0.2 VCC

• External shift clock mode

tSLSH

tSHSL

SC

0.8 VCC

0.2 VCC

tSLOV

0.2 VCC

2.4 V

0.8 V

SO

SI

tIVSH

tSHIX

0.8 V^CC

0.2 VCC

0.8 VCC

0.2 VCC

58

MB90M405 Series

(5) Timer Input Timings

(Ta = −40 °C to +85 °C, V^DD-FIP = V^CC-CPU = AV^CC= 3.0 V to 3.6 V, V^SS-IO = V^SS-CPU = AV^SS= 0 V)

Value

Condi-

tion

Parameter

Symbol

Pin Name

Unit

Remarks

Min

Max

Input pulse width

t^TIWH, t^TIWL

TIN0

⎯

4 t^CP

⎯

ns

0.8 VCC

0.2 VCC

TIN0

t

TIWH

tTIWL

(6) Timer Output Timings

(Ta = −40 °C to +85 °C, V^DD-FIP = V^CC-CPU = AV^CC= 3.0 V to 3.6 V, V^SS-IO = V^SS-CPU = AV^SS= 0 V)

Value

Parameter

Symbol

Pin Name

Condition

Unit Remarks

Min

Max

CLK ↑ → T^OUTchange time

t^TO

TO0

⎯

30

⎯

ns

2.4 V

CLK

TO0

t^TO

2.4 V

0.8 V

(7) Trigger Input Timings

(Ta = −40 °C to +85 °C, V^DD-FIP = V^CC-CPU = AV^CC= 3.0 V to 3.6 V, V^SS-IO = V^SS-CPU = AV^SS= 0 V)

Value

Parameter

Symbol

Pin Name

Condition

Unit

Remarks

Min

5 t^CP

1

Max

⎯

ns

In normal operation

In stop mode

Input pulse width

t^TRGL

INT0 to INT3

⎯

µs

0.8 VCC

0.2 VCC

INT0 to INT3

tTRGH

tTRGL

59

MB90M405 Series

5. Electrical Characteristics of A/D Converter

(Ta = −40 °C to +85 °C, V^CC-CPU ≤ AV^CC= 3.0 V to 3.6 V, V^SS-CPU = V^SS-IO = AV^SS= 0 V)

Value

Typ

⎯

Sym-

bol

Parameter

Resolution

Pin Name

Unit

Remarks

Min

⎯

Max

10

⎯

bit

Total Error

⎯

3.0

LSB

Non-linear Error

Differential Linear Error

⎯

2.5

⎯

1.9

AV^SS

Zero Transition Voltage

V^OTAN0 to AN15

mV

− 1.5 LSB + 0.5 LSB + 2.5 LSB

AV^CCAV^CCAV^CC

− 3.5 LSB − 1.5 LSB + 0.5 LSB

1 LSB = AV^CC/1024

Full-scale Transition Voltage V^FSTAN0 to AN15

Conversion Time

⎯

98 t^CP*²

⎯

ns 16 MHz Operation

(sampling + comparison)

Sampling Time

⎯

32 t^CP*²

66 t^CP*²

⎯

1

⎯

ns 16 MHz Operation

Comparison Time

ns 16 MHz Operation

Analog Port Input Voltage

Analog Input Voltage

Reference Voltage

I^AINAN0 to AN15

V^AINAN0 to AN15

10

AV^CC

5

µA

0

V

⎯

I^A

AV^CC

3.0

⎯

V

mA

Power Current

I^AH

I^R

AV^CC

⎯

100

⎯

5

µA *1

µA

AV^CC

⎯

200

5

Reference Voltage Supply

Current

I^RH

⎯

AV^CC

⎯

µA *1

LSB

Inter-channel Variance

AN0 to AN15

⎯

4

*1 : When the A/D converter is not operating, voltage when CPU stopped (at V^CC-CPU= AV^CC= 3.3 V)

*2 : t^CPsignifies 1/internal operating frequency. With t^CPat internal 16 MHz, 1/16 MHz = 62.5 ns.

Notes: • Reference “L” side set permanently to AV^SS, and reference “H” side set permanently to AV^CC. As AV^CC

decreases, relative error increases.

• Please use the output impedance of the external analog input circuit under the following conditions :

External circuit output impedance ≤ 10 kΩ

• An overly high external circuit output impedance could cause a lack of analog voltage sampling time.

• Analog Input Circuit Equivalent Circuit Diagram

R^ON

C

Comparator

Analog input

MB90M407/A,MB90M408/A

R^ON= approx. 1.5 kΩ

C = approx. 30 pF

MB90MF408/A, MB90MV405

R^ON= approx. 3.0 kΩ

C = approx. 65 pF

Note : Please use the figures given here as a rough guide.

60

MB90M405 Series

■ SAMPLE CHARACTERISTICS

(1) “H” level output voltage

(V^CC− V^OH) − I^OH

(2) “L” level output voltage

V^OL− I^OL

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

TA = +25 °C

VCC = 2.7 V

V^CC= 3 V

VCC = 3.3 V

V^CC= 3.6 V

V^CC= 3.9 V

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

VCC = 2.7 V

V^CC= 3 V

V^CC= 3.3 V

V^CC= 3.6 V

V^CC= 3.9 V

−1

−2

−3

−4

−5

1

2

3

4

5

IOL (mA)

IOH (mA)

(3) “H” level input voltage/ “L” level input voltage

(CMOS input)

(4) “H” level input voltage/ “L” level input voltage

(hysteresis input)

V^IN− V^CC

2.5

TA = +25 °C

2

V^IH

VIH

V^IL

1.5

VIL

1

0.5

0

1

0.5

0

2.7

3

3.3

3.6

3.9

2.7

3

3.3

3.6

3.9

VCC (V)

61

MB90M405 Series

■ ORDERING INFORMATION

Part NO.

Package

Remarks

MB90MF408PF

MB90M408PF

MB90M407PF

All FL output pins (FIP0 to FIP59) have pull downs

100-pin plastic QFP

(FPT-100P-M06)

MB90MF408APF

MB90M408APF

MB90M407APF

Some FL output pins (FIP0 to FIP16) do not have pull downs.

The remaining FL output pins (FIP17 to FIP59) have pull downs.

62

MB90M405 Series

■ PACKAGE DIMENSIONS

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

100-pin plastic QFP

(FPT-100P-M06)

23.90±0.40(.941±.016)

*

20.00±0.20(.787±.008)

80

51

81

50

0.10(.004)

17.90±0.40

(.705±.016)

*

14.00±0.20

(.551±.008)

INDEX

Details of "A" part

100

31

0.25(.010)

3.00 –⁺0⁰.^.2³0⁵

.118 ⁺^–.^.⁰⁰⁰¹⁸⁴

(Mounting height)

0~8

˚

1

30

0.65(.026)

0.32±0.05

(.013±.002)

0.17±0.06

(.007±.002)

M

0.13(.005)

0.25±0.20

(.010±.008)

(Stand off)

0.80±0.20

(.031±.008)

"A"

0.88±0.15

(.035±.006)

C

2002 FUJITSU LIMITED F100008S-c-5-5

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

63

MB90M405 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0508


型号：	MB90M407APF
厂家：	FUJITSU
描述：	16-Bit Original Microcontroller 16位微控制器原创微控制器和处理器外围集成电路时钟
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MB90M407APF [FUJITSU]

相关型号：

MB90M407PF

MB90M408

MB90M408A

MB90M408APF

MB90M408PF

MB90MF408

MB90MF408A

MB90MF408APF

MB90MF408PF

MB90MV405

MB90P214A

MB90P214APF