MB90P673PF_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13602-4E

16-bit Proprietary Microcontroller

CMOS

F²MC-16L MB90670/675 Series

MB90671/672/673/T673/P673 (MB90670 Series)

MB90676/677/678/T678/P678 (MB90675 Series)

■ DESCRIPTION

The MB90670/675 series is a member of 16-bit proprietary single-chip microcontroller F²MC*¹-16L family

designed to be combined with an ASIC (Application Specific IC) core. The MB90670/675 series is a high-

performance

general-purpose 16-bit microcontroller for high-speed real-time processing in various industrial equipment, OA

equipment, and process control.

The instruction set of F²MC-16L CPU core inherits AT architecture of F²MC-8 family with additional instruction

sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and

enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word

data (32-bit).

The MB90670/675 series has peripheral resources of UART0, UART1(SCI), an 8/10-bit A/D converter, an

8/16-bit PPG timer, a 16-bit reload timer, a 24-bit free-run timer, an output compare (OCU), an input capture

(ICU), DTP/external interrupt circuit, an I²C*²interface (in MB90675 series only). Embedded peripheral

resources performs data transmission with an intelligent I/O service function without the intervention of the CPU,

enabling real-time control in various applications.

*1: F²MC stands for FUJITSU Flexible Microcontroller.

*2: Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use these

components in an I²C system, provided that the system conforms to the I²C Standard Specification as

defined by Philips.

■ PACKAGE

80-pin Plastic LQFP

80-pin Plastic QFP

100-pin Plastic LQFP

100-pin Plastic QFP

(FPT-80P-M05)

(FPT-80P-M06)

(FPT-100P-M05)

(FPT-100P-M06)

MB90670/675 Series

■ FEATURES

• Clock

Embedded PLL clock multiplication circuit

Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation

(at oscillation of 4 MHz, 4 MHz to 16 MHz).

Minimum instruction execution time of 62.5 ns (at oscillation of 4 MHz, four times the PLL clock, operation at

Vcc of 5.0 V)

• CPU addressing space of 16 Mbytes

Internal addressing of 24-bit

External accessing can be performed by selecting 8/16-bit bus width (external bus mode)

• Instruction set optimized for controller applications

Rich data types (bit, byte, word, long word)

Rich addressing mode (23 types)

High code efficiency

Enhanced precision calculation realized by the 32-bit accumulator

• Instruction set designed for high level language (C) and multi-task operations

Adoption of system stack pointer

Enhanced pointer indirect instructions

Barrel shift instructions

• Enhanced execution speed

4-byte instruction queue

• Enhanced interrupt function

8 levels, 32 factors

• Automatic data transmission function independent of CPU operation

Extended intelligent I/O service function (EI²OS)

• Low-power consumption (standby) mode

Sleep mode (mode in which CPU operating clock is stopped)

Timebase timer mode (mode in which other than oscillation and timebase timer are stopped)

Stop mode (mode in which oscillation is stopped)

CPU intermittent operation mode

Hardware standby mode

• Process

CMOS technology

• I/O port

MB90670 series: Maximum of 65 ports

MB90675 series: Maximum of 84 ports

• Timer

Timebase timer/watchdog timer: 1 channel

8/16-bit PPG timer: 8-bit × 2 channels or 16-bit × 1 channel

16-bit reload timer: 2 channels

24-bit free-run timer: 1 channel

• Input capture (ICU)

Generates an interrupt request by latching a 24-bit free-run timer counter value upon detection of an edge

input to the pin.

• Output compare (OCU)

Generates an interrupt request and reverse the output level upon detection of a match between the 24-bit free-

run timer counter value and the compare setting value.

• I²C interface (in MB90675 series only)

Serial I/O port for supporting Inter IC BUS

(Continued)

2

MB90670/675 Series

(Continued)

• UART0

With full-duplex double buffer (8-bit length)

Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used.

• UART1 (SCI)

With full-duplex double buffer (8-bit length)

Clock asynchronized or clock synchronized serial transmission (I/O extended serial) can be selectively used.

• DTP/external interrupt circuit (4 channels)

A module for starting extended intelligent I/O service (EI²OS) and generating an external interrupt triggered

by an external input.

• Wake-up interrupt

Receives external interrupt requests and generates an interrupt request upon an “L” level input.

• Delayed interrupt generation module

Generates an interrupt request for switching tasks.

• 8/10-bit A/D converter (8 channels)

8-bit or 10-bit resolution can be selectively used.

Starting by an external trigger input.

3

MB90670/675 Series

■ PRODUCT LINEUP

• MB90670 series

Part number

MB90671

Item

MB90672

MB90673

MB90T673

MB90P673

External ROM

product

One-time PROM

product

Classification

Mask ROM products

ROM size

RAM size

16 Kbytes

640 bytes

32 Kbytes

48 Kbytes

External ROM

2 Kbytes

48 Kbytes

1.64 Kbytes

Number of instructions:340

Instruction bit length:8 bits, 16 bits

Instruction length:1 byte to 7 bytes

Data bit length:1 bit, 8 bits, 16 bits

CPU functions

Minimum execution time:62.5 ns (at machine clock of 16 MHz)

Interrupt processing time:1.5 µs (at machine clock of 16 MHz, minimum value)

General-purpose I/O ports (CMOS output): 57

General-purpose I/O ports (N-ch open-drain output): 8

Total: 65

Ports

Clock synchronized transmission (500 Kbps to 2 Mbps)

Clock asynchronized transmission (4800 Kbps to 500 kbps)

Transmission can be performed by bi-directional serial transmission or by master/

slave connection.

UART0

Clock synchronized transmission (500 Kbps to 2 Mbps)

Clock asynchronized transmission (2400 Kbps to 62500 bps)

Transmission can be performed by bi-directional serial transmission or by master/

slave connection.

UART1 (SCI)

Conversion precision: 10-bit or 8-bit selectable

Number of inputs: 8

One-shot conversion mode (converts selected channel only once)

Continuous conversion mode (converts selected channel continuously)

Stop conversion mode (converts selected channel and stop operation repeatedly)

8/10-bit A/D converter

8/16-bit PPG timer

Number of channels: 2

8-bit or 16-bit PPG operation

A pulse wave of given intervals and given duty ratios can be output.

Pulse cycle: 125 ns to 16.78 s (at oscillation of 4 MHz, machine clock of 16 MHz)

Number of channels: 2

16-bit reload timer operation

Interval: 125 ns to 131 ms (at machine clock of 16 MHz)

16-bit reload timer

24-bit free-run timer

External event count can be performed.

Number of channel :1

Overflow interrupts or intermediate bit interrupts may be generated.

Output compare unit

(OCU)

Number of channels: 8

Pin input factor: A match signal of compare register

(Continued)

4

MB90670/675 Series

(Continued)

Part number

MB90671

MB90672

MB90673

MB90T673

MB90P673

Item

Number of channels: 4

Rewriting a register value upon a pin input (rising, falling, or both edges)

Input capture unit (ICU)

Number of inputs: 4

DTP/external interrupt circuit Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.

External interrupt circuit or extended intelligent I/O service (EI²OS) can be used.

Number of inputs: 8

Started by an “L” level input.

Wake-up interrupt

Delayed interrupt generation

module

An interrupt generation module for switching tasks used in real-time operating

systems.

I²C interface

None

18-bit counter

Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms

(at oscillation of 4 MHz)

Timebase timer

Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms

(at oscillation of 4 MHz, minimum value)

Watchdog timer

Low-power consumption

(standby) mode

Sleep/stop/CPU intermittent operation/timebase timer/hardware stand-by

Process

CMOS

Operating voltage*

2.7 V to 5.5 V

* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

5

MB90670/675 Series

• MB90675 series

Part number

MB90676

MB90677

MB90678

MB90T678

MB90P678

MB90V670

Item

One-time

PROM

product

External ROM

product

Evaluation

product

Classification

Mask ROM products

48 Kbytes

ROM size

RAM size

32 Kbytes

64 Kbytes

None

64 Kbytes

—

1.64 Kbytes

2 Kbytes

3 Kbytes

4 Kbytes

The number of instructions: 340

Instruction bit length: 8 bits, 16 bits

Instruction length: 1 byte to 7 bytes

Data bit length: 1 bit, 8 bits, 16 bits

CPU functions

Minimum execution time: 62.5 ns (at machine clock of 16 MHz)

Interrupt processing time: 1.5 µs (at machine clock of 16 MHz, minimum value)

General-purpose I/O ports (CMOS output): 74

General-purpose I/O ports (N-ch open-drain output): 10

Total: 84

Ports

Clock synchronized transmission (500 Kbps to 2 Mbps)

Clock asynchronized transmission (4800 Kbps to 500 Kbps)

Transmission can be performed by bi-directional serial transmission or by master/slave

connection.

UART0

Clock synchronized transmission (500 Kbps to 2 Mbps)

Clock asynchronized transmission (2400 Kbps to 62500 bps)

Transmission can be performed by bi-directional serial transmission or by master/slave

connection.

UART1 (SCI)

Conversion precision: 10-bit or 8-bit can be selectively used.

Number of inputs: 8

One-shot conversion mode (converts selected channel only once)

Continuous conversion mode (converts selected channel continuously)

Stop conversion mode (converts selected channel and stop operation repeatedly)

8/10-bit A/D

converter

Number of channels: 2

PPG operation of 8-bit or 16-bit

Pulse of given intervals and given duty ratios can be output

Pulse interval 125 ns to 16.78 s (at oscillation of 4 MHz, machine clock of 16 MHz)

8/16-bit PPG timer

16-bit reload timer

Number of channels: 2

16-bit reload timer operation

Interval: 125 ns to 131 ms (at machine clock of 16 MHz)

External event count can be performed.

24-bit free-run

timer

Number of channel :1

Overflow interrupts or intermediate bit interrupts may be generated.

Output compare

(OCU)

Number of channels: 8

Pin input factor: a match signal of compare register

(Continued)

6

MB90670/675 Series

(Continued)

Part number

MB90676

MB90677

MB90678

MB90T678

MB90P678

MB90V670

Item

Number of channels: 4

Rewriting a register value upon a pin input (rising, falling, or both edges)

Input capture (ICU)

Number of inputs: 4

DTP/external

interrupt circuit

Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.

External interrupt circuit or extended intelligent I/O service (EI²OS) can be used.

Number of inputs: 8

Started by an “L” level input.

Wake-up interrupt

Delayed interrupt

generation module

An interrupt generation module for switching tasks used in real-time operating systems.

Serial I/O port for supporting Inter IC BUS

I²C interface

18-bit counter

Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms

(at oscillation of 4 MHz)

Timebase timer

Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms

(at oscillation of 4 MHz, minimum value)

Watchdog timer

Low-power

consumption

(stand-by) mode

Sleep/stop/CPU intermittent operation/timebase timer/hardware stand-by

Process

CMOS

Power supply

voltage for

operation*

2.7 V to 5.5 V

* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”) Assurance

for the MB90V670 is given only for operation with a tool at a power voltage of 2.7 V to 5.5 V, an operating

temperature of 0°C to 70°C, and an operating frequency of 1.5 MHz to 16 MHz.

■ PACKAGE AND CORRESPONDING PRODUCTS

MB90671

MB90672

MB90673

MB90T673

MB90676

MB90677

MB90678

MB90T678

Package

MB90P673

MB90P678

MB90V670

FPT-80P-M05

FPT-80P-M06

FPT-100P-M05

FPT-100P-M06

×

: Available × : Not available

Note: For more information about each package, see section “■ Package Dimensions.”

7

MB90670/675 Series

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

In evaluation with an evaluation product, note the difference between the evaluation chip and the chip actually

used. The following items must be taken into consideration.

• The MB90V670 does not have an internal ROM, however, operations equivalent to chips with an internal ROM

can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the

development tool.

• In the MB90V670, images from FF4400^Hto FFFFFF^Hare mapped to bank 00, and FE0000^Hto FF3FFF^Hto

mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.)

• In the MB90678/MB90P678, images from FF4000^Hto FFFFFF^Hare mapped to bank 00, and FF0000^Hto

FF3FFF^Hto bank FF only.

2. Mask Options

Functions selected by optional settings and methods for setting the options are dependent on the product types.

Refer to “■ Mask Options” for detailed information.

Note that mask option is fixed in MB90V670 series.

8

MB90670/675 Series

■ PIN ASSIGNMENT

(Top view)

1

2

3

4

5

6

7

8

P20/A16

P21/A17

P22/A18

P23/A19

P24/TIN0

P25/TIN1

P26/TOT0

P27/TOT1

V^SS

RST

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

P80/PPG1

P77/DOT7

P76/DOT6

P75/DOT5

P74/DOT4

P73/DOT3

P72/DOT2

P71/DOT1

P70/DOT0

P67/ASR3

P66/ASR2

P65/ASR1

P64/ASR0

P63/INT3

P62/INT2

P61/INT1

P60/INT0

HST

9

10

11

12

13

14

15

16

17

18

19

20

P30/ALE

P31/RD

P32/WRL/WR

P33/WRH

P34/HRQ

P35/HAK

P36/RDY

P37/CLK

P40/SIN0

P41/SOT0

P42/SCK0

MD2

(FPT-80P-M05)

9

MB90670/675 Series

(Top view)

X0

V^SS

RST

P16/AD14/WI6

P17/AD15/WI7

P20/A16

P21/A17

P22/A18

1

2

3

4

5

6

7

8

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

P80/PPG1

P77/DOT7

P76/DOT6

P75/DOT5

P74/DOT4

P73/DOT3

P72/DOT2

P71/DOT1

P70/DOT0

P67/ASR3

P66/ASR2

P65/ASR1

P64/ASR0

P63/INT3

P62/INT2

P61/INT1

P60/INT0

HST

P23/A19

P24/TIN0

P25/TIN1

P26/TOT0

P27/TOT1

V^SS

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

P30/ALE

P31/RD

P32/WRL/WR

P33/WRH

P34/HRQ

P35/HAK

P36/RDY

P37/CLK

P40/SIN0

P41/SOT0

P42/SCK0

P43/SIN1

P44/SOT10

MD2

MD1

MD0

(FPT-80P-M06)

10

MB90670/675 Series

(Top view)

P22/A18

P23/A19

P24/TIN0

P25/TIN1

P26/TOT0

P27/TOT1

P30/ALE

P31/RD

1

2

3

4

5

6

7

8

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

RST

PA7

PA6

PA5

PA4

PA3

PA2

PA1

V^SS

9

PA0

P32/WRL/WR

P33/WRH

P34/HRQ

P35/HAK

P36/RDY

P37/CLK

P40/SIN0

P41/SOT0

P42/SCK0

P43/SIN1

P44/SOT1

V^CC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P77/DOT7

P76/DOT6

P75/DOT5

P74/DOT4

P73/DOT3

P72/DOT2

P71/DOT1

P70/DOT0

P67/ASR3

P66/ASR2

P65/ASR1

P64/ASR0

P63/INT3

P62/INT2

P61/INT1

P60/INT0

P45/SCK1

P46/PPG0

P47/ATG

P80/PPG1

(FPT-100P-M05)

11

MB90670/675 Series

(Top view)

P20/A16

P21/A17

P22/A18

P23/A19

P24/TIN0

P25/TIN1

P26/TOT0

P27/TOT1

P30/ALE

P31/RD

PB2

PB1

PB0

RST

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

P77/DOT7

P76/DOT6

P75/DOT5

P74/DOT4

P73/DOT3

P72/DOT2

P71/DOT1

P70/DOT0

P67/ASR3

P66/ASR2

P65/ASR1

P64/ASR0

P63/INT3

P62/INT2

P61/INT1

P60/INT0

HST

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V^SS

P32/WRL/WR

P33/WRH

P34/HRQ

P35/HAK

P36/RDY

P37/CLK

P40/SIN0

P41/SOT0

P42/SCK0

P43/SIN1

P44/SOT1

V^CC

P45/SCK1

P46/PPG0

P47/ATG

P80/PPG1

P81

P82

P83

MD2

(FPT-100P-M06)

12

MB90670/675 Series

■ PIN DESCRIPTION

Pin no.

Circuit

type

Pin name

Function

LQFP

-80*¹

QFP

-80*²

LQFP

QFP

-100*³-100*⁴

62

63

64

65

80

81

82

83

X0

X1

A

Crystal oscillator pins

(Oscillation)

39 to 41 41 to 43 47 to 49 49 to 51 MD0 to

MD2

F

Input pins for selecting operation modes

(CMOS) Connect directly to V^CCor V^SS.

60

62

75

77

RST

H

External reset request input

Hardware standby input pin

General-purpose I/O port

(CMOS/H)

42

44

50

52

HST

G

(CMOS/H)

65 to 72 67 to 74 83 to 90 85 to 92 P00 to P07

B

(CMOS) This function is valid in the single-chip mode.

AD00 to

AD07

I/O pins for the lower 8-bit of the external address

data bus

This function is valid in the mode where the

external bus is valid.

73 to 78, 75 to 80, 91 to 96, 93 to 98, P10 to P15,

B

General-purpose I/O port

79,

1,

97,

99,

P16,

(CMOS) This function is valid in the single-chip mode.

80

2

98

100 P17

AD08 to

I/O pins for the upper 8-bit of the external address

data bus

This function is valid in the mode where the

external bus is valid.

AD13,

AD14,

AD15

WI0 to WI5,

WI6,

WI7

I/O pins for wake-up interrupts

This function is valid in the single-chip mode.

Because the input of the DTP/external interrupt

circuit is used as required when the DTP/external

interrupt circuit is enabled, and it is necessary to

stop outputs by other functions unless such

outputs are made intentionally.

1,

2,

3,

4

3,

4,

5,

6

99,

100,

1,

2,

3,

4

P20,

P21,

P22,

P23

B

General-purpose I/O port

(CMOS) This function becomes valid in the single-chip

mode or the external address output control

register is set to select a port.

2

A16,

A17,

A18,

A19

Output pins for the external address bus of A16 to

A19

This function is valid in the mode where the

external bus is valid and the upper address

control register is set to select an address.

*1: FPT-80P-M05

*2: FPT-80P-M06

*3: FPT-100P-M05

*4: FPT-100P-M06

(Continued)

13

MB90670/675 Series

Pin no.

Circuit

type

Pin name

Function

General-purpose I/O port

LQFP

-80*¹

QFP

-80*²

LQFP

QFP

-100*³-100*⁴

5,

6

7,

8

3,

4

5,

6

P24,

P25

E

(CMOS/H) This function is always valid.

TIN0,

TIN1

Event input pins of 16-bit reload timer 0 and 1

Because this input is used as required when the

16-bit reload timer is performing input operations,

and it is necessary to stop outputs by other functions

unless such outputs are made intentionally.

7,

8

9,

10

5,

6

7,

8

P26,

P27

E

General-purpose I/O port

(CMOS/H) This function is valid when outputs from 16-bit

reload timer 0 and 1 are disabled.

TOT0,

TOT1

Output pins for 16-bit reload timer 0 and 1

This function is valid when output from 16-bit

reload timer 0 and 1 are enabled.

10

11

12

13

14

7

8

9

P30

ALE

B

General-purpose I/O port

(CMOS) This function is valid in the single-chip mode.

Address latch enable output pin

This function is valid in the mode where the

external bus is valid.

10

12

P31

RD

B

General-purpose I/O port

(CMOS) This function is valid in the single-chip mode.

Read strobe output pin for the data bus

This function is valid in the mode where the

external bus is valid.

10

P32

B

General-purpose I/O port

(CMOS) This function is valid in the single-chip mode or

WRL/WR pin output is disabled.

WRL

WR

Write strobe output pin for the data bus

This function is valid when WRL/WR pin output is

enabled in the mode where external bus is valid.

WRL is used for holding the lower 8-bit for write

strobe in 16-bit access operations, while WR is

used for holding 8-bit data for write strobe in

8-bit access operations.

13

15

11

13

P33

B

General-purpose I/O port

(CMOS) This function is valid in the single-chip mode, in

the external bus 8-bit mode, or WRH pin output is

disabled.

WRH

Write strobe output pin for the upper 8-bit of the

data bus

This function is valid when the external bus 16-bit

mode is selected in the mode where the external

bus is valid, and WRH output pin is enabled.

*1: FPT-80P-M05

*2: FPT-80P-M06

*3: FPT-100P-M05

*4: FPT-100P-M06

(Continued)

14

MB90670/675 Series

Pin no.

Circuit

type

Pin name

P34

Function

LQFP

-80*¹

QFP

LQFP

QFP

-80*²

-100*³-100*⁴

14

15

16

12

13

14

15

16

B

General-purpose I/O port

(CMOS) This function is valid when both the single-chip

mode and the hold function are disabled.

HRQ

Hold request input pin

This function is valid in the mode where the

external bus is valid or when the hold function is

enabled.

17

18

P35

B

General-purpose I/O port

(CMOS) This function is valid when both the single-chip

mode and the hold function are disabled.

HAK

Hold acknowledge output pin

This function is valid in the mode where the

external bus is valid or when the hold function is

enabled.

P36

B

General-purpose I/O port

(CMOS) This function is valid when both the single-chip

mode and the external ready function are

disabled.

RDY

Ready input pin

This function is valid when the external ready

function is enabled in the mode where the

external bus is valid.

17

18

19

20

15

16

17

18

P37

CLK

B

General-purpose I/O port

(CMOS) This function is valid in the single-chip mode or

when the CLK output is disabled.

CLK output pin

This function is valid when CLK output is disabled

in the mode where the external bus is valid.

P40

E

General-purpose I/O port

(CMOS/H) This function is always valid.

SIN0

Serial data input pin of UART0

Because this input is used as required when

UART0 is performing input operations, and it is

necessary to stop outputs by other functions

unless such outputs are made intentionally.

19

21

17

19

P41

E

General-purpose I/O port

(CMOS/H) This function is valid when serial data output from

UART0 is disabled.

SOT0

Serial data output pin of UART0

This function is valid when serial data output from

UART0 is enabled.

*1: FPT-80P-M05

*2: FPT-80P-M06

*3: FPT-100P-M05

*4: FPT-100P-M06

(Continued)

15

MB90670/675 Series

Pin no.

Circuit

type

Pin name

P42

Function

General-purpose I/O port

LQFP

-80*¹

QFP

-80*²

LQFP

QFP

-100*³-100*⁴

20

22

18 20

E

(CMOS/H) This function is valid when clock output from

UART0 is disabled.

SCK0

Clock I/O pin of UART0

This function is valid when clock output from

UART0 is enabled.

Because this input is used as required when

UART0 is performing input operations, and it is

necessary to stop outputs by other functions

unless such outputs are made intentionally.

21

23

19

21

P43

E

General-purpose I/O port

(CMOS/H) This function is always valid.

SIN1

Serial data input pin of UART1 (SCI)

Because this input is used as required when

UART1 (SCI) is performing input operations, and it

is necessary to stop outputs by other functions

unless such outputs are made intentionally.

22

23

24

25

20

22

24

P44

E

General-purpose I/O port

(CMOS/H) This function is valid when serial data output from

UART1 (SCI) is disabled.

SOT1

P45

Serial data output pin of UART1 (SCI)

This function is valid when serial data output from

UART1 (SCI) is enabled.

E

General-purpose I/O port

(CMOS/H) This function is valid when clock output from

UART1 (SCI) is disabled.

SCK1

Clock I/O pin of UART1 (SCI)

This function is valid when clock output from

UART1 (SCI) is enabled.

Because this input is used as required when

UART1 (SCI) is performing input operations, and it

is necessary to stop outputs by other functions

unless such outputs are made intentionally.

24

26

23

25

P46

E

General-purpose I/O port

(CMOS/H) This function is valid when waveform output from

8/16-bit PPG timer 0 is disabled.

PPG0

Output pin of 8/16-bit PPG timer 0

This function is valid when waveform output from

8/16-bit PPG timer 0 is enabled.

*1: FPT-80P-M05

*2: FPT-80P-M06

*3: FPT-100P-M05

*4: FPT-100P-M06

(Continued)

16

MB90670/675 Series

Pin no.

Circuit

type

Pin name

P47

Function

LQFP

-80*¹

QFP

LQFP

QFP

-80*²

-100*³-100*⁴

25

27

24

26

E

General-purpose I/O port

(CMOS/H) This function is always valid.

ATG

Trigger input pin of the 8/10-bit A/D converter

Because this input is used as requited when the

8/10-bit A/D converter is performing input operations,

and it is necessary to stop outputs by other functions

unless such outputs are made intentionally.

30,

31,

33,

34,

32,

33,

35,

36,

37,

38,

39,

38,

39,

40,

41,

P50,

P51,

P52,

P53,

C

I/O port of an open-drain type

(CMOS/H) The input function is valid when the analog input

enable register is set to select a port.

35 to 38 37 to 40 41 to 44 43 to 46 P54 to P57

AN0,

AN1,

AN2,

Analog input pins of the 8/10-bit A/D converter

This function is valid when the analog input enable

register is set to select AD.

AN3,

AN4 to AN7

43 to 46 45 to 48 51 to 54 53 to 56 P60 to P63

INT0 to INT3

E

General-purpose I/O port

(CMOS/H) This function is always valid.

Request input pins of the DTP/external interrupt

circuit

Because this input is used as required when the

DTP/external interrupt circuit is performing input

operations, and it is necessary to stop outputs from

other functions unless such outputs are made

intentionally.

47 to 50 49 to 52 55 to 58 57 to 60 P64 to P67

E

General-purpose I/O port

(CMOS/H) This function is always valid.

ASR0 to

ASR3

Sample data input pins for ICU0 to ICU3

Because this input is used as required when the input

capture (ICU) is performing input operations, and it is

necessary to stop outputs from other functions unless

such outputs are made intentionally.

51 to 58 53 to 60 59 to 66 61 to 68 P70 to P77

E

General-purpose I/O port

(CMOS/H) This function is valid when waveform output from the

output compare (OCU) is disabled.

DOT0 to

DOT7

Waveform output pins of OCU0 and OCU1

This function is valid when waveform output from

the output compare (OCU) is enabled and output

from the port is selected.

*1: FPT-80P-M05

*2: FPT-80P-M06

*3: FPT-100P-M05

*4: FPT-100P-M06

(Continued)

17

MB90670/675 Series

(Continued)

Pin no.

Circuit

type

Pin name

P80

Function

General-purpose I/O port

LQFP

-80*¹

QFP

-80*²

LQFP

QFP

-100*³-100*⁴

59

61

25 27

E

(CMOS/H) This function is valid when waveform output from

8/16-bit PPG timer 1 is disabled.

PPG1

Output pin of 8/16-bit PPG timer 1

This function is valid when waveform output from

8/16-bit PPG timer 1 is enabled.

26 to 31 28 to 33 P81 to P86

E

General-purpose I/O port

—

(CMOS/H) This function is always valid.

45

47

P90

D

I/O port of an open-drain type

(NMOS/H) This function is always valid.

I/O pin of the I²C interface

SDA

This function is valid when operation of the I²C

interface is enabled.

Hold the port output in the high-impedance status

(PDR = 1) when the I²C interface is in operation.

46

48

P91

SCL

D

I/O port of an open-drain type

(NMOS/H) This function is always valid.

Clock I/O pin of the I²C interface

This function is valid when operation of the I²C

—

interface is enabled.

Hold the port output in the high-impedance status

(PDR = 1) when the I²C interface is in operation.

67 to 74 69 to 76 PA0 to PA7

76 to 78 78 to 80 PB0 to PB2

E

General-purpose I/O port

(CMOS/H) This function is always valid.

General-purpose I/O port

(CMOS/H) This function is always valid.

E

—

64

66

21,

82

23,

84

V^CC

V^SS

Power

supply

Power supply to the digital circuit

9,

32,

61

11,

34,

63

9,

40,

79

11,

42,

81

Power

supply

Ground level of the digital circuit

26

28

32

34

AV^CC

Power

supply

Power supply to the analog circuit

Make sure to turn on/turn off this power supply

with a voltage exceeding AV^CCapplied to V^CC.

27

29

33

35

AVRH

Power

supply

Reference voltage input to the analog circuit

Make sure to turn on/turn off this power supply

with a voltage exceeding AVRH applied to AV^CC.

28

29

30

31

34

35

36

37

AVRL

AV^SS

Power

supply

Reference voltage input to the analog circuit

Power

supply

Ground level of the analog circuit

*1: FPT-80P-M05

*2: FPT-80P-M06

*3: FPT-100P-M05

*4: FPT-100P-M06

18

MB90670/675 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• External clock frequency 3 MHz to 32 MHz

• Oscillation feedback resistor approx.

1MΩ

X1

Clock input

P-ch

X0

N-ch

Standby control signal

B

• CMOS level input/output

(with standby control)

• Pull-up option selectable

(with standby control)

R

P-ch

N-ch

Digital output

• No pull-up resistor in the MB90V670

Digital input

Standby control signal

C

• N-ch open-drain output

• CMOS level hystheresis input

(with A/D control)

Digital output

A/D input

Digital input

A/D disable

D

• NMOS open-drain output

• CMOS level hysteresis input

(with standby control)

P-ch

N-ch

Digital output

Digital input

Standby control signal

(Continued)

19

MB90670/675 Series

(Continued)

Type

Circuit

Remarks

• CMOS level output

E

• CMOS level hysteresis input

(with standby control)

• Pull-up option selectable

(with standby control)

R

P-ch

Digital output

• No pull-up resistor in the MB90V670

N-ch

Digital input

Standby control signal

F

• CMOS level input/output

(without standby control)

• Pull-up/pull-down option selectable

(without stand-by control)

• In mask ROM versions, MD2 pin is fixed

to pull-down resistor, and optionally

selectable the resistor in other pins.

• The MB90V670 has no pull-up/pull-down

resistors.

R

P-ch

N-ch

Digital input

G

• CMOS level hysteresis input

(without standby control)

P-ch

N-ch

Digital input

H

• CMOS level hysteresis input

(without standby control)

R

• Pull-up option selectable

(without standby control)

• No pull-up resistor in the MB90V670

P-ch

N-ch

Digital input

20

MB90670/675 Series

■ HANDLING DEVICES

1. Make Sure that the Voltage not Exceed the Maximum Rating (to Avoid a Latch-up).

In CMOS ICs, a latch-up phenomenon is caused when an voltage exceeding V^CCor an voltage below V^SSis

applied to input or output pins or a voltage exceeding the rating is applied across V^CCand V^SS.

When a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal

break-down of devices. To avoid the latch-up, make sure that the voltage not exceed the maximum rating.

In turning on/turning off the analog power supply, make sure the analog power voltage (AV^CC, AVRH) and analog

input voltages not exceed the digital voltage (V^CC).

2. Connection of Unused Pins

Leaving unused pins open may result in abnormal operations. Clamp the pin level by connecting it to a pull-up

or a pull-down resistor.

3. Notes on Using External Clock

In using the external clock, drive X0 pin only and leave X1 pin unconnected.

• Using external clock

X0

Open

X1

MB90670/675 series

4. Power Supply Pins

In products with multiple V^CCor V^SSpins, the pins of a same potential are internally connected in the device to

avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to

lower the electro-magnetic emission level and abnormal operation of strobe signals caused by the rise in the

ground level, and to conform to the total current rating.

Make sure to connect V^CCand V^SSpins via lowest impedance to power lines.

It is recommended to provide a bypass capacitor of around 0.1 µF between V^CCand V^SSpin near the device.

5. Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass

capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and

make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand

area for stabilizing the operation.

21

MB90670/675 Series

6. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply (AV^CC, AVRH, AVRL) and analog inputs (AN0 to AN7)

after turning-on the digital power supply (V^CC).

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure

that the voltage not exceed AVRH or AV^CC(turning on/off the analog and digital power supplies simultaneously

is acceptable).

7. Connection of Unused Pins of A/D Converter

Connect unused pins of A/D converter to AV^CC= V^CC, AV^SS= AVRH = V^SS.

8. “MOV @AL, AH”, “MOVW @AL, AH” Instructions

When the above instruction is performed to I/O space, an unnecessary writing operation (#FF, #FFFF) may be

performed in the internal bus.

Use the compiler function for inserting an NOP instruction before the above instructions to avoid the writing

operation.

Accessing RAM space with the above instruction does not cause any problem.

9. Initialization

In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers,

turning on the power again.

22

MB90670/675 Series

■ PROGRAMMING TO THE ONE-TIME PROM ON THE MB90P673/P678

The MB90P673 and MB90P678 has a PROM mode for emulation operation of the MBM27C1000/1000A, to

which writing codes by a general-purpose ROM writer can be done via a dedicated adapter. Please note that

the device is not compatible with the electronic signature (device ID code) mode.

1. Writing Sequence

The memory map for the PROM mode is shown as follows. Write option data to the option setting area according

by referring to “7. PROM Option Bit Map”.

PROM mode

Normal operation mode

FFFFFF^H

1FFFFF^H

Programarea

(PROM)

Programarea

(PROM)

Address*¹

Address*²

010000^H

ROM image

004000^H

000000^H

0002C^H

00000^H

Option

setting area

Type

MB90P673

MB90P678

Address*¹

14000^H

Address*²

FF4000^H

FF0000^H

Number of bytes

48 Kbytes

64 Kbytes

10000^H

Note: The ROM image size for bank 00 is 48 Kbytes (ROM image for between FF4000^Hto FFFFFF^H).

Write data to the one-time PROM microcontrollers according to the following sequence.

(1) Set the PROM programer to select the MBM27C1000/1000A.

(2) Load the program data to the ROM programer address ^*1to 1FFFF^H. To select a PROM option, load the

option data from 00000^Hto 0002C^Hreferring to “7. PROM Option Bit Map”.

(3) Set the chip to the adapter socket and load the socket to the ROM programer. Make sure that the device

and adapter socket are properly oriented.

(4) Program from 00000^Hto 1FFFF^H.

Notes: • In mask-ROM products, there is no PROM mode and it is impossible to read data by a ROM programer.

• Contact sales personnel when purchasing a ROM programer.

2. Program Mode

In the MB90P673/P678, all the bits are set to “1” upon shipping from FUJITSU or erasing operation. To write

data, set desired bit selectively to “0”. However it is impossible to write electronically to the bits.

23

MB90670/675 Series

3. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening precedure for a product with a blanked

One-time PROM microcomputer program.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

4. Programming Yield

All bits cannnot be programmed at Fujitsu shipping test to a blanked One-time PROM microcomputer, due to

its nature. For this reason, a programming yield of 100% cannnot be assured at all times.

5. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer

Part no.

Package

MB90P673PF MB90P673PFV MB90P678PF MB90P678PFV

QFP-80

LQFP-80

QFP-100

LQFP-100

Compatible socket adapter

Sun Hayato Co., Ltd.

ROM-80QF-

32DP-16L

ROM-80SQF- ROM-100QF- ROM-100SQF-

32DP-16L

—

32DP-16L

—

32DP-16L

1890A

1891

—

Recommended

Minato Electronics Inc.

—

Recommended

1930

UNISITE

3900

Data I/O Co., Ltd.

2900

Inquiry: San Hayato Co., Ltd.: TEL: (81)-3-3986-0403

FAX: (81)-3-5396-9106

Minato Electronics Inc.: TEL: USA (1)-916-348-6066

JAPAN (81)-45-591-5611

Data I/O Co., Ltd.: TEL: USA/ASIA (1)-206-881-6444

EUROPE (49)-8-985-8580

24

MB90670/675 Series

6. Pin Assignment for EPROM Mode

• MBM27C1000/1000A pin compatible

MBM27C1000/1000A

MB90P673/MB90P678

MBM27C1000/1000A

MB90P673/MB90P678

Pin no. Pin name

V^CC

Pin no.

Pin name

V^PP

Pin no.

Pin name

MD2

P32

Pin no.

32

Pin name

V^CC

1

2

OE

31

PGM

N.C.

A14

A13

A08

A09

A11

A16

A10

CE

P33

—

3

A15

A12

A07

A06

A05

A04

A03

A02

A01

A00

D00

D01

D02

GND

P17

30

4

P14

29

P16

P15

P10

P11

P13

P30

P12

P31

P07

P06

P05

P04

P03

5

P27

28

6

P26

27

7

P25

26

8

P24

25

9

P23

24

10

11

12

13

14

15

16

P22

23

P21

22

P20

21

D07

D06

D05

D04

D03

P00

20

P01

19

P02

18

V^SS

17

• Pin assignments for products not compatible

with MBM27C1000/1000A

• Power supply, GND connected pin

Pin no.

Pin name

processing

Type

Pin no.

Refer to pin

Pin name

MD0

MD1

X0

HST

V^CC

Power supply

Connect a pull-up

resistor of 4.7 kΩ.

assignments.

P34

P35

P36

RST

AVRL

AV^SS

V^SS

X1

OPEN

Refer to pin

assignments.

AV^CC

AVRH

P37

P40 to P47

P50 to P57

P60 to P67

P70 to P77

P80 to P86

P90

GND

Connect a pull-up

resistor having

a resistance of

approximately

1 MΩ to each pin.

P91

PA0 to PA7

PB0 to PB2

Note: Only MB90675 series has P81 to P86, P90, P91, PA0 to PA7, PB0 to PB2 pins.

25

MB90670/675 Series

7. PROM Option Bit Map

Address

bit 7

bit 6

RST

bit 5

bit 4

MD1

bit 3

MD1

bit 2

MD0

bit 1

MD0

bit 0

Vacancy

Pull-up

1: No

Pull-up

1: No

Pull-down Pull-up

Pull-down

1: No

00000^H

1: No

0: Yes

P07

P06

P05

P04

P03

P02

P01

P00

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

00004^H

00008^H

0000C^H

00010^H

00014^H

0001C^H

00020^H

00024^H

00028^H

0002C^H

P17

P16

P15

P14

P13

P12

P11

P10

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P27

P26

P25

P24

P23

P22

P21

P20

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P37

P36

P35

P34

P33

P32

P31

P30

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P47

P46

P45

P44

P43

P42

P41

P40

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P67

P66

P65

P64

P63

P62

P61

P60

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P77

P76

P75

P74

P73

P72

P71

P70

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Vacancy

P86

P85

P84

P83

P82

P81

P80

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

PA5

PA4

PA3

PA2

PA1

PA0

Vacancy

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Vacancy

PB2

PB1

PB0

PA7

PA6

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Notes: • Data “1” must be programed to the reserved bits and address other than listed above.

• Only MB90P678 has pull-up options for P81 to P86, PA0 to PA7, and PB0 to PB2 pins.

• Data “1” must be programed for the MB90P673.

26

MB90670/675 Series

■ BLOCK DIAGRAM

F²MC–16L

CPU

Interrupt controller

Port 5

8

P50/AN0 to

P57/AN7

X0

X1

RST

HST

Clock control block

(including timebase timer)

8

AV^CC

8/10-bit

A/D converter

AVRH

AVRL

AV^SS

8

P10/AD08/WI0 to

P17/AD15/WI7

Wake-up

interrupt

P47/ATG

Port 0, 1

16

Port 4

8

P00/AD00 to

P07/AD07

P40/SIN0

P41/SOT0

P42/SCK0

UART0

4

P20/A16 to P23/A19

P30/ALE

P31/RD

P32/WRL/WR

P33/WRH

P34/HRQ

P43/SIN1

P44/SOT1

P45/SCK1

UART1

(SCI)

External bus

interface

2

16-bit PPG timer

10

8-bit

PPG timer 0

P46/PPG0

P35/HAK

P36/RDY

P37/CLK

8-bit

PPG timer 1

P80/PPG1

P81 to P86

Port 2, 3

6

P24/TIN0

P26/TOT0

16-bit

Port 8

Port 6

reload timer 0

P25/TIN1

P27/TOT1

16-bit

reload timer 1

4

DTP/external

interrupt circuit

0 to 3

4

P60/INT0 to

P63/INT3

Port 7

Input capture

(ICU)

P64/ASR0 to

P67/ASR3

4

Output compare

(unit 0)

8

P70/DOT0 to

P77/DOT7

24-bit

free-run timer

4

Output compare

8

3

(unit 1)

PA0 to PA7

PB0 to PB2

Port A, B *

Port 9*

P90/SDA

P91/SCL

Other pins

RAM

ROM

2

I²C interface *

V^CC,V^SS,

MD0 to MD2

* : Not included in the MB90670 series.

27

MB90670/675 Series

■ MEMORY MAP

External ROM

external bus mode

Internal ROM

external bus mode

Single-chip mode

FFFFFF^H

1

*

ROM area

Address#1

ROM area

100000^H

Externalarea

010000^H

ROM area

(image of

bank FF)

ROM area

(image of

bank FF)

Externalarea

Address #2

004000^H

Externalarea

002000^H

Address #3

Register

RAM

Register

RAM

Register

RAM

000100^H

0000C0^H

000000^H

Externalarea

Peripheral

Externalarea

Peripheral

Part number

MB90671

Address #1*²

Address #2*²

00C000^H

008000^H

004000^H

—

Address #3*²

000380^H

000780^H

000900^H

000780^H

000900^H

000D00^H

FFC000^H

FF8000^H

FF4000^H

—

MB90672

MB90673

MB90T673

MB90P673

MB90676

FF4000^H

FF8000^H

FF4000^H

FF0000^H

—

004000^H

008000^H

004000^H

—

MB90677

MB90678

MB90T678

MB90P678

FF0000^H

004000^H

: Internal access memory

: Enternal access memory

: Inhibited area

*1: The same external memory is accessed for bank 0F, 1F, 2F through FF.

*2: Addresses #1, #2 and #3 are unique to the product type.

Notes: • The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C

compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same

address, enabling reference of the table on the ROM without stating “far”.

However, the ROM area of the MB90678/P678 exceeds 48 Kbytes, and for this reason, the image from

FF4000^Hto FFFFFF^His reflected on bank 00 and image from FF0000^Hto FF3FFF^Hbank FF only.

• In the MB90670/675 series, the upper 4-bit of the address are not output to the external bus. For this

reason, the maximum area accessible is 1 Mbyte. The same address is accessed through different banks

in different images.

For example, accessing “A00000^H” and “B00000^H” accesses the same address on the external bus.

• To prevent the memory or I/O from being accessed through images, and the data from being destroyed,

it is recommended to limit number of banks to a maximum of 16 so that the banks are mapped without

interfering each other. Caution must be also taken when masking the upper address with the external

address output control register (HACR).

28

MB90670/675 Series

■ F²MC-16L CPU PROGRAMMING MODEL

(1) Dedicated Registers

: Accumlator (A)

AH

AL

Dual 16-bit register used for storing results of calculation etc. The two 16-bit

registers can be combined to be used as a 32-bit register.

: User stack pointer (USP)

The 16-bit pointer indicating a user stack address.

USP

SSP

PS

: System stack pointer (SSP)

The 16-bit pointer indicating the status of the system stack address.

: Processor status (PS)

The 16-bit register indicating the system status.

: Program counter (PC)

The 16-bit register indicating storing location of the current instruction code.

PC

: Direct page register (DPR)

DPR

The 8-bit register for specifying bit 8 through 15 of the operand address in the

short direct addressing mode.

: Program bank register (PCB)

The 8-bit register indicating the program space.

PCB

DTB

USB

SSB

: Data bank register (DTB)

The 8-bit register indicating the data space.

: User stack bank register (USB)

The 8-bit register indicating the user stack space.

: System stack bank register (SSB)

The 8-bit register indicating the system stack space.

: Additional data bank register (ADB)

The 8-bit register indicating the additional space.

ADB

8-bit

16-bit

32-bit

29

MB90670/675 Series

(2) General-purpose Registers

Maximum of 32 banks

RW7

R7

R6

RL3

RL2

RL1

RL0

RW6

RW5

RW4

R5

R3

R4

R2

R1

R0

RW3

RW2

RW1

RW0

000180 ^H+ (RP × 10 ^H)

16-bit

(3) Processor Status (PS)

ILM

RP

CCR

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

—

PS

ILM2 ILM1 ILM0 B4

B3

0

B2

0

B1

0

B0

0

I

S

1

T

X

N

X

Z

X

V

X

C

X

Initial value

0

— : Unused

X : Indeterminate

30

MB90670/675 Series

■ I/O MAP

Abbreviated

Read/

Resource

name

Address

Register name

Port 0 data register

Initial value

register name

write

R/W

R

000000^H

000001^H

000002^H

000003^H

000004^H

000005^H

000006^H

000007^H

000008^H

000009^H

00000A^H

00000B^H

PDR0

Port 0

Port 1

X X X X X X X X ^B

1 1 1 1 1 1 1 1 ^B

X X X X X X X X ^B

– X X X X X X X ^B

– – – – – – 1 1 ^B

X X X X X X X X ^B

– – – – – X X X ^B

PDR1

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

Port 5 data register

Port 6 data register

Port 7 data register

Port 8 data register

Port 9 data register

Port A data register

Port B data register

PDR2

Port 2

PDR3

Port 3

PDR4

Port 4

PDR5

Port 5

PDR6

Port 6

PDR7

Port 7

Port 8*⁵

Port 9*⁵

Port A*⁵

Port B*⁵

PDR8

R/W

PDR9

PDRA

PDRB

00000C^H

to

(Vacancy)*³

00000E^H

Wake-up

interrupt

00000F^H

EIFR

Wake-up interrupt flag register

R/W

– – – – – – – 0 ^B

000010^H

000011^H

000012^H

000013^H

000014^H

DDR0

DDR1

DDR2

DDR3

DDR4

Port 0 data direction register

Port 1 data direction register

Port 2 data direction register

Port 3 data direction register

Port 4 data direction register

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

0 0 0 0 0 0 0 0 ^B

Port 5,

analog input

000015^H

ADER

Analog input enable register

R/W

1 1 1 1 1 1 1 1 ^B

000016^H

000017^H

000018^H

000019^H

00001A^H

00001B^H

DDR6

DDR7

DDR8

Port 6 data direction register

Port 7 data direction register

Port 8 data direction register

R/W

Port 6

Port 7

0 0 0 0 0 0 0 0 ^B

– 0 0 0 0 0 0 0 ^B

Port 8*⁵

(Vacancy)*³

Port A*⁵

Port B*⁵

DDRA

DDRB

Port A data direction register

Port B data direction register

R/W

0 0 0 0 0 0 0 0 ^B

– – – – – 0 0 0 ^B

00001C^H

to

(Vacancy)*³

00001E^H

Wake-up

interrupt

00001F^H

EICR

Wake-up interrupt enable register

W

0 0 0 0 0 0 0 0 ^B

(Continued)

31

MB90670/675 Series

Abbreviated

register name

Read/

write

Resource

name

Address

Register name

Initial value

000020^H

000021^H

UMC0

Mode control register 0

Status register 0

R/W!

0 0 0 0 0 1 0 0 ^B

0 0 0 1 0 0 0 0 ^B

USR0

UART0

UIDR0/

UODR0

Input data register 0/

output data register 0

000022^H

R/W

X X X X X X X X ^B

000023^H

000024^H

000025^H

URD0

SMR1

SCR1

Rate and data register 0

Mode register 1

R/W

R/W!

0 0 0 0 0 0 0 0 ^B

0 0 0 0 0 1 0 0 ^B

Control register 1

UART1

(SCI)

SIDR1/

SODR1

Input data register 1/

output data register 1

000026^H

R/W

X X X X X X X X ^B

000027^H

000028^H

000029^H

00002A^H

00002B^H

00002C^H

00002D^H

00002E^H

00002F^H

SSR1

ENIR

EIRR

ELVR

Status register 1

R/W!

R/W

0 0 0 0 1 – 0 0 ^B

– – – – 0 0 0 0 ^B

0 0 0 0 0 0 0 0 ^B

DTP/interrupt enable register

DTP/interrupt factor register

Request level setting register

DTP/external

interrupt circuit

(Vacancy)*³

0 0 0 0 0 0 0 0 ^B

X X X X X X X X ^B

0 0 0 0 0 0 X X ^B

A/D convertor control status

register

ADCS

ADCR

R/W!

8/10-bit A/D

converter

A/D convertor data register

R/W!*⁴

PPG0 operating mode control

register

8/16-bit PPG

timer 0

000030^H

000031^H

PPGC0

PPGC1

R/W!

0 – 0 0 0 0 0 1 ^B

0 0 0 0 0 0 0 0 ^B

PPG1 operating mode control

register

8/16-bit PPG

timer 1

000032^H

000033^H

000034^H

000035^H

000036^H

000037^H

000038^H

000039^H

00003A^H

00003B^H

00003C^H

00003D^H

00003E^H

00003F^H

(Vacancy)*³

PRLL0

PRLH0

PRLL1

PRLH1

R/W

X X X X X X X X ^B

0 0 0 0 0 0 0 0 ^B

– – – – 0 0 0 0 ^B

X X X X X X X X ^B

0 0 0 0 0 0 0 0 ^B

– – – – 0 0 0 0 ^B

X X X X X X X X ^B

(Continued)

8/16-bit PPG

timer 0

PPG0 reload register

8/16-bit PPG

timer 1

PPG1 reload register

TMCSR0

Timer control status register 0

R/W!

R/W

R/W!

R/W

16-bit reload

timer 0

TMR0/

TMRLR0

16-bit timer register 0/

16-bit reload register 0

TMCSR1

Timer control status register 1

16-bit reload

timer 1

TMR1/

TMRLR1

16-bit timer register 1/

16-bit reload register 1

32

MB90670/675 Series

Abbreviated

register name

Read/

write

Resource

name

Address

Register name

Initial value

I²C bus status register

I²C bus control register

I²C bus clock control register

I²C bus address register

I²C bus data register

000040^H

000041^H

000042^H

000043^H

000044^H

IBSR

IBCR

ICCR

IADR

IDAR

R

0 0 0 0 0 0 0 0 ^B

– – 0 X X X X X ^B

– X X X X X X X ^B

X X X X X X X X ^B

R/W

I²C interface*⁶

000045^H

to

(Vacancy)*³

00004F^H

000050^H

000051^H

000052^H

000053^H

000054^H

000055^H

000056^H

000057^H

000058^H

000059^H

00005A^H

00005B^H

00005C^H

00005D^H

00005E^H

00005F^H

000060^H

000061^H

000062^H

000063^H

000064^H

000065^H

000066^H

000067^H

000068^H

000069^H

1 1 0 0 0 0 0 0 ^B

– – 1 1 1 1 1 1 ^B

0 0 0 0 0 0 0 0 ^B

1 1 1 1 0 0 0 0 ^B

– – – – 0 0 0 0 ^B

0 0 0 0 0 0 0 0 ^B

1 1 1 1 0 0 0 0 ^B

– – – – 0 0 0 0 ^B

0 0 0 0 0 0 0 0 ^B

X X X X X X X X ^B

0 0 0 0 0 0 0 0 ^B

X X X X X X X X ^B

0 0 0 0 0 0 0 0 ^B

X X X X X X X X ^B

24-bit free-run

timer

TCCR

ICC

Free-run timer control register

ICU control register

R/W!

R/W

R

Input capture

(ICU)

TCRL

Free-run timer lower data register

Free-run timer upper data register

OCU control register 00

OCU control register 01

OCU control register 10

OCU control register 11

ICU lower data register 0

ICU upper data register 0

ICU lower data register 1

ICU upper data register 1

ICU lower data register 2

24-bit free-run

timer

TCRH

R

CCR00

CCR01

CCR10

CCR11

ICDR0L

ICDR0H

ICDR1L

ICDR1H

ICDR2L

R/W

R

Output compare

(OCU)

(unit 0)

Output compare

(OCU)

(unit 1)

R

Input capture

(ICU)

R

(Continued)

33

MB90670/675 Series

Abbreviated

register name

Read/

write

Resource

name

Address

Register name

Initial value

00006A^H

00006B^H

00006C^H

00006D^H

00006E^H

00006F^H

000070^H

000071^H

000072^H

000073^H

000074^H

000075^H

000076^H

000077^H

000078^H

000079^H

00007A^H

00007B^H

00007C^H

00007D^H

00007E^H

00007F^H

000080^H

000081^H

000082^H

000083^H

000084^H

000085^H

000086^H

000087^H

000088^H

000089^H

00008A^H

00008B^H

X X X X X X X X ^B

0 0 0 0 0 0 0 0 ^B

X X X X X X X X ^B

0 0 0 0 0 0 0 0 ^B

ICDR2H

ICU upper data register 2

ICU lower data register 3

ICU upper data register 3

R

Input capture

(ICU)

ICDR3L

ICDR3H

CPR00L

CPR00H

CPR01L

CPR01H

CPR02L

CPR02H

CPR03L

CPR03H

CPR04L

CPR04H

CPR05L

CPR05H

CPR06L

CPR06H

R

OCU compare lower data

register 0

R/W

OCU compare upper data

register 0

OCU compare lower data

register 1

OCU compare upper data

register 1

Output compare

(OCU)

(unit 0)

OCU compare lower data

register 2

OCU compare upper data

register 2

OCU compare lower data

register 3

OCU compare upper data

register 3

OCU compare lower data

register 4

OCU compare upper data

register 4

OCU compare lower data

register 5

Output compare

(OCU)

(unit 1)

OCU compare upper data

register 5

OCU compare lower data

register 6

OCU compare upper data

register 6

(Continued)

34

MB90670/675 Series

Abbreviated

register name

Read/

write

Resource

name

Address

Register name

Initial value

00008C^H

00008D^H

00008E^H

00008F^H

0 0 0 0 0 0 0 0 ^B

OCU compare lower data

register 7

CPR07L

CPR07H

R/W

Output compare

(OCU)

(unit 1)

OCU compare upper data

register 7

R/W

000090^H

to

(System reservation area)*¹

00009E^H

Delayed

interrupt

generation

module

Delayed interrupt factor

generation/

cancellation register

00009F^H

DIRR

R/W

– – – – – – – 0 ^B

Low-power

consumption

(stand-by) mode

Low-power consumption mode

control register

0000A0^H

0000A1^H

LPMCR

CKSCR

R/W!

0 0 0 1 1 0 0 0 ^B

1 1 1 1 1 1 0 0 ^B

Low-power

consumption

Clock selection register

(stand-by) mode

0000A2^H

to

(Vacancy)*³

0000A4^H

Automatic ready function select

register

0000A5^H

ARSR

W

External bus pin

0 0 1 1 – – 0 0 ^B

0000A6^H

0000A7^H

0000A8^H

0000A9^H

HACR

EPCR

WDTC

TBTC

Upper address control register

Bus control signal select register

Watchdog timer control register

Timebase timer control register

W

External bus pin

Watchdog timer

Timebase timer

– – – – 0 0 0 0 ^B

0 0 0 0 * 0 0 – ^B

X X X X X 1 1 1 ^B

1 – – 0 0 1 0 0 ^B

W

R/W!

0000AA^H

to

(Vacancy)*³

0000AF^H

0000B0^H

0000B1^H

0000B2^H

0000B3^H

0000B4^H

0000B5^H

0000B6^H

0000B7^H

0000B8^H

0000B9^H

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

Interrupt control register 00

Interrupt control register 01

Interrupt control register 02

Interrupt control register 03

Interrupt control register 04

Interrupt control register 05

Interrupt control register 06

Interrupt control register 07

Interrupt control register 08

Interrupt control register 09

R/W!

0 0 0 0 0 1 1 1 ^B

Interrupt

controller

(Continued)

35

MB90670/675 Series

(Continued)

Abbreviated

register name

Read/

write

Resource

name

Address

Register name

Initial value

0000BA^H

0000BB^H

0000BC^H

0000BD^H

0000BE^H

0000BF^H

ICR10

Interrupt control register 10

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

Interrupt control register 14

Interrupt control register 15

R/W!

0 0 0 0 0 1 1 1 ^B

ICR11

ICR12

Interrupt

controller

ICR13

ICR14

ICR15

0000C0^H

to

(External area)*²

0000FF^H

36

MB90670/675 Series

Descriptions for read/write

R/W: Readable and writable

R: Read only

W: Write only

R/W!: Bits for reading operation only or writing operation only are included. Refer to the register lists for specific

resource for detailed information.

Descriptions for initial value

0 : The initial value of this bit is “0”.

1 : The initial value of this bit is “1”.

* : The initial value of this bit is “1” or “0” (decided by levels on pins of MD0 through MD2).

X : The initial value of this bit is indeterminate.

– : This bit is not used. The initial value is indeterminate.

*1: Access prohibited.

*2: This area is the only external access area having an address of 0000FF^Hor lower. An access operation to this

area is handled as that to external I/O area.

*3: The area corresponding to the “(Vacancy)” on the I/O map is reserved, and accessing operation to this area is

handled as that to internal area. No access signal to external devices are generated.

*4: Only bit 15 is writable. Reading bit 10 through bit 15 returns “0” as a reading result.

*5: In the MB90670 series, P81 through P86, P90, P91, PA0 through PA7, PB0 through PB2 are not present. For

this reason, bits corresponding to these pins are not used.

*6: The MB90670 series does not have the I²C interface. For this reason, this area is “(Vacancy)” in the MB90670

series.

Note: For bits that is only allowed to program, the initial value set by the reset operation is listed as an initial value.

Note that the values are different from reading results.

For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending

on the types of the reset. However initial value for resets that initializes the value are listed.

37

MB90670/675 Series

■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

Interrupt vector

Number Address

Interrupt control register

EI²OS

Interrupt source

Priority*⁴

support

ICR

—

Address

Reset

×

# 08

# 09

# 10

08^H

09^H

0A^H

FFFFDC^H

FFFFD8^H

FFFFD4^H

—

High

INT9 instruction

Exception

—

DTP/external interrupt circuit

Channel 0

# 11

0B^H

FFFFD0^H

FFFFCC^H

FFFFC8^H

FFFFC4^H

ICR00

ICR01

0000B0^H*²

0000B1^H*²

DTP/external interrupt circuit

Channel 1

# 12 0C^H

# 13 0D^H

DTP/external interrupt circuit

Channel 2

DTP/external interrupt circuit

Channel 3

# 14

0E^H

Output compare Channel 0

Output compare Channel 1

Output compare Channel 2

Output compare Channel 3

Output compare Channel 4

Output compare Channel 5

Output compare Channel 6

Output compare Channel 7

24-bit free-run timer Overflow

# 15

# 16

# 17

# 18

# 19

# 20

# 21

# 22

# 23

0F^H

10^H

11^H

12^H

13^H

14^H

15^H

16^H

17^H

FFFFC0^H

FFFFBC^H

FFFFB8^H

FFFFB4^H

FFFFB0^H

FFFFAC^H

FFFFA8^H

FFFFA4^H

FFFFA0^H

0000B2^H*²

0000B3^H*²

0000B4^H*²

0000B5^H*²

ICR02

ICR03

ICR04

ICR05

ICR06

0000B6^H*²

24-bit free-run timer Intermediate

bit

# 24

18^H

FFFF9C^H

Input capture Channel 0

Input capture Channel 1

Input capture Channel 2

Input capture Channel 3

# 25

# 26

# 27

19^H

1A^H

1B^H

FFFF98^H

FFFF94^H

FFFF90^H

FFFF8C^H

0000B7^H*²

0000B8^H*²

ICR07

ICR08

# 28 1C^H

# 29 1D^H

16-bit reload timer/

8/16-bit PPG timer 0

FFFF88^H

FFFF84^H

FFFF80^H

ICR09

0000B9^H*^2,*³

16-bit reload timer/

8/16-bit PPG timer 1

# 30

# 31

1E^H

1F^H

8/10-bit A/D converter

measurement complete

ICR10

ICR11

0000BA^H

Wake-up interrupt

×

# 33

# 34

21^H

22^H

FFFF78^H

FFFF74^H

0000BB^H*²

Timebase timer interval interrupt

Low

(Continued)

38

MB90670/675 Series

(Continued)

Interrupt source

Interrupt control

Interrupt vector

Number Address

EI²OS

support

register

Priority*⁴

ICR

Address

UART1 (SCI) transmission

complete

# 35

23^H

FFFF70^H

High

0000BC^H*²

ICR12

UART0 transmission complete

UART1 (SCI) reception complete

I²C interface*¹

# 36

24^H

25^H

FFFF6C^H

FFFF68^H

FFFF64^H

# 37

ICR13

0000BD^H*²

×

# 38 26

H

UART0 reception complete

# 39

# 42

27^H

2A^H

FFFF60^H

FFFF54^H

ICR14

ICR15

0000BE^H

0000BF^H

Delayed interrupt generation

module

Low

: Can be used

×

: Can not be used

: Can be used. With EI²OS stop function.

: Can be used if interrupt request using ICR are not commonly used.

*1: In MB90670 series, this interrupt vector is not used because the series does not have the I²C interface.

*2: • Interrupt levels for peripherals that commonly use the ICR register are in the same level.

• When the extended intelligent I/O service (EI²OS) is specified in a peripheral device commonly using the ICR

register, only one of the functions can be used.

• When the extended intelligent I/O service (EI²OS) is specified for one of the peripheral functions, interrupts

can not be used on the other function.

*3: Only 16-bit reload timer conforms to the extended intelligent I/O service (EI²OS). Because the 8/16-bit PPG

timer does not conform to the extended intelligent I/O service (EI²OS), disable interrupts of the 8/16-bit PPG

timer when using the extended intelligent I/O service (EI²OS) in the 16-bit reload timer.

*4: The level shows priority of same level of interrupt invoked simultaneously.

39

MB90670/675 Series

■ PERIPHERALS

1. I/O Port

(1) Input/output Port

Port 0 to 4, 6, 8, A, and B are general-purpose I/O ports having a combined function as an external bus pin and

a resource input. The input output ports function as general-purpose I/O port only in the single-chip mode. In

the external bus mode, the ports are configured as external bus pins, and part of pins for port 3 can be configured

as general-purpose I/O port by setting the bus control signal select register (ECSR). Each pin corresponding

to upper 4-bit of the port 2 can be switched between a resource and a port bitwise.

Only MB90675 series has port A and port B.

• Operation as output port

The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.

Writing data to PDR register when the port is configured as output, the data is retained in the output latch in

the PDR and directly output to the pin.

The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR

register.

Note: When a read-modify-write instruction (e.g. bit set instruction) is performed to the port data register, the

destination bit of the operation is set to the specified value, not affecting the bits configured by the DDR

register for output, however, values of bits configured by the DDR register as inputs are changed because

input values to the pins are written into the output latch. To avoid this situation, configure the pins by the

DDR register as output after writing output data to the PDR register when configuring the bit used as

input as outputs.

• Operation as input port

The pin is configured as an input by setting the corresponding bit of the DDR register to “0”.

When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance

status.

When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs

are unaffected.

Reading the PDR register reads out the pin level (“0” or “1”).

• Block diagram

PDR (port data register)

PDR read

Output latch

P-ch

PDR write

DDR (port direction register)

N-ch

Direction latch

DDR write

Standby control (SPL=1)

DDR read

Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode

40

MB90670/675 Series

(2) N-ch Open-drain Port

Port 5 and port 9 are general-purpose I/O ports having a combined function as resource input/output. Each pin

can be switched between resource and port bitwise.

Only MB90675 series has port 9.

• Operation as output port

When a data is written into the PDR register, the data is latched to the output latch of PDR. When the output

latch value is set to “0”, the output transistor is turned on and the pin status is put into an “L” level output, while

writing “1” turns off the transistor and put the pin in a high-impedance status.

If the output pin is pulled-up, setting output latch value to “1” puts the pin in the pull-up status.

Reading the PDR register returns the pin value (same as the output latch value in the PDR).

Note: Execution of a read-modify-write instruction (e.g. bit set instruction) reads out the output latch value rather

than the pin value, leaving output latch that is not manipulated unchanged.

• Operation as input port

Setting corresponding bit of the PDR register to “1” turns off the output transistor and the pin is put into a high-

impedance status.

Reading the PDR register returns the pin level (“0” or “1”).

• Block diagram of port 5

ADER (analog input enable register)

To analog input

ADER read

ADER latch

ADER write

PDR (port data register)

RMW

(read-modify-write

instruction)

PDRread

Output trigger

Output latch

PDR write

Standby control (SPL=1)

Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode

• Block diagram of port 9

From resource output

Standby control

(SPL=1)

To resource input

PDR (port data register)

PDRread

RMW

(read-modify-

write instruc-

tion)

Output

trigger

Output latch

PDR write

Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode

41

MB90670/675 Series

(3) Output Port

Port 7 is a general-purpose output port having a combined function as an output compare (OCU) output. Note

that only OCU output can be output when the pin is configured as an output, and it is not used for outputting

given data by writing to the data register. Each pin can be switched between an output compare output and a

port bitwise.

• Operation as output port (operation of OCU output)

Setting the corresponding bit of the DDR register to “1” configures the pin as an output port. In this case, lower

4-bit of CCR01 and CCR register are output.

When configured as an output, the output buffer is turned on and data retained in the output latch in the PDR

of the output compare is output to the pin.

Writing data to DOT bit of the OCU control register (CCR01, CCR11) corresponding to each pin writes data

in synchronization to a match operation of the output compare and output to the pin.

Reading the PDR register returns the pin level (same as the output latch value of the PDR).

When output of output compare is enabled, an output value from the output compare can be read out.

• Operation as input port

Setting corresponding bit of the DDR register to “0” configures the pin as input port.

When the pin is configured as an input port, the output buffer is turned off and the pin is put into a high-

impedance status.

Reading the PDR register returns the pin level (“0” or “1”).

• Block diagram

PDR (port data register)

PDR read

OCU control register

P-ch

OCU control register write

DDR (port direction register)

N-ch

Direction latch

DDR write

DDR read

Standby control (SPL=1)

Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode

42

MB90670/675 Series

(4) Register Configuration

. . . . . . . . . . . .

Address bit 15

000000^H

bit 8 bit 7

P07

bit 6

P06

R/W

bit 5

P05

R/W

bit 4

P04

R/W

bit 3

P03

R/W

bit 2

P02

R/W

bit 1

P01

R/W

bit 0

P00

R/W

Port 0 data register

(PDR0)

(PDR1)

R/W

. . . . . . . . . . . .

bit 0

Address

000001^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

Port 1 data register

(PDR1)

(PDR0)

P17

R/W

P16

R/W

P15

R/W

P14

R/W

P13

R/W

P12

R/W

P11

R/W

P10

R/W

. . . . . . . . . . . .

Address bit 15

000002^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

P20

R/W

Port 2 data register

(PDR2)

(PDR3)

P27

R/W

P26

R/W

P25

R/W

P24

R/W

P23

R/W

P22

R/W

P21

R/W

. . . . . . . . . . . .

bit 0

Address

000003^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

P30

Port 3 data register

(PDR3)

P37

R/W

P36

R/W

P35

R/W

P34

R/W

P33

R/W

P32

R/W

P31

R/W

(PDR2)

R/W

. . . . . . . . . . . .

Address bit 15

000004^H

bit 8 bit 7

P47

bit 6

bit 5

bit 4

bit 3

bit 2

P42

R/W

bit 1

P41

R/W

bit 0

P40

R/W

Port 4 data register

(PDR4)

(PDR5)

P46

R/W

P45

R/W

P44

R/W

P43

R/W

. . . . . . . . . . . .

bit 0

Address

000005^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

P50

Port 5 data register

(PDR5)

P57

R/W

P56

P55

R/W

P54

R/W

P53

R/W

P52

R/W

P51

R/W

(PDR4)

R/W

. . . . . . . . . . . .

Address bit 15

000006^H

bit 8 bit 7

P67

bit 6

bit 5

bit 4

bit 3

bit 2

P62

R/W

bit 1

P61

R/W

bit 0

P60

R/W

Port 6 data register

(PDR6)

(PDR7)

P66

R/W

P65

R/W

P64

R/W

P63

R/W

. . . . . . . . . . . .

bit 0

Address

000007^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

P70

Port 7 data register

(PDR7)

P77

R/W

P76

R/W

P75

R/W

P74

R/W

P73

R/W

P72

R/W

P71

R/W

(PDR6)

R/W

. . . . . . . . . . . .

Address bit 15

000008^H

bit 8 bit 7

—

bit 6

bit 5

bit 4

bit 3

bit 2

P82

R/W

bit 1

P81

R/W

bit 0

P80

R/W

Port 8 data register

(PDR8)

(PDR9)

P86

R/W

P85

R/W

P84

R/W

P83

R/W

. . . . . . . . . . . .

bit 0

Address

000009^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

P90

Port 9 data register

(PDR9)

—

P91

R/W

(PDR8)

R/W

. . . . . . . . . . . .

Address bit 15

00000A^H

bit 8 bit 7

PA7

bit 6

bit 5

bit 4

bit 3

bit 2

PA2

R/W

bit 1

PA1

R/W

bit 0

PA0

R/W

Port A data register

(PDRA)

(PDRB)

PA6

R/W

PA5

R/W

PA4

R/W

PA3

R/W

. . . . . . . . . . . .

bit 0

Address

00000B^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

PB0

Port B data register

(PDRB)

—

PB2

R/W

PB1

R/W

(PDRA)

R/W

(Continued)

43

MB90670/675 Series

(Continued)

. . . . . . . . . . . .

bit-15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Address

000010^H

Port 0 data direction register

(DDR0)

(DDR1)

P07

R/W

P06

R/W

P05

R/W

P04

R/W

P03

R/W

P02

R/W

P01

R/W

P00

R/W

. . . . . . . . . . . .

bit 0

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

Address

000011^H

Port 1 data direction register

(DDR1)

(DDR0)

P17

R/W

P16

R/W

P15

R/W

P14

R/W

P13

R/W

P12

R/W

P11

R/W

P10

R/W

. . . . . . . . . . . .

bit 15

bit 8 bit 7

P27

bit 6

bit 5

bit 4

bit 3

bit 2

P22

R/W

bit 1

P21

R/W

bit 0

P20

R/W

Address

000012^H

Port 2 data direction register

(DDR2)

(DDR3)

P26

R/W

P25

R/W

P24

R/W

P23

R/W

. . . . . . . . . . . .

bit 0

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

Address

000013^H

Port 3 data direction register

(DDR3)

P37

R/W

P36

R/W

P35

R/W

P34

R/W

P33

R/W

P32

R/W

P31

R/W

P30

R/W

(DDR2)

. . . . . . . . . . . .

Address bit 15

000014^H

bit 8 bit 7

P47

bit 6

bit 5

bit 4

bit 3

bit 2

P42

R/W

bit 1

P41

R/W

bit 0

P40

R/W

Port 4 data direction register

(DDR4)

(ADER)

P46

R/W

P45

R/W

P44

R/W

P43

R/W

. . . . . . . . . . . .

bit 0

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

Address

000015^H

Analog input enable register

(ADER)

P57

R/W

P56

R/W

P55

R/W

P54

R/W

P53

R/W

P52

R/W

P51

R/W

P50

(DDR4)

R/W

. . . . . . . . . . . .

Address bit 15

000016^H

bit 8 bit 7

P67

bit 6

bit 5

bit 4

bit 3

bit 2

P62

bit 1

P61

bit 0

P60

R/W

Port 6 data direction register

(DDR6)

(DDR7)

P66

R/W

P65

R/W

P64

R/W

P63

R/W

. . . . . . . . . . . .

bit 0

Address

000017^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

Port 7 data direction register

(DDR7)

P77

P76

P75

R/W

P74

R/W

P73

R/W

P72

R/W

P71

R/W

P70

(DDR6)

R/W

. . . . . . . . . . . .

bit 15

bit 8 bit 7

—

bit 6

bit 5

bit 4

bit 3

bit 2

P82

bit 1

P81

bit 0

P80

Address

000018^H

Port 8 data direction register

(DDR8)

(Vacancy)

P86

P85

P84

P83

R/W

bit 6

R/W

bit 5

R/W

bit 4

R/W

bit 3

R/W

bit 2

R/W

bit 1

R/W

bit 0

. . . . . . . . . . . .

Address bit 15

00001A^H

bit 8 bit 7

Port A data direction register

(DDRA)

(DDRB)

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

R/W

. . . . . . . . . . . .

bit 0

Address

00001B^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

PB0

Port B data direction register

(DDRB)

—

PB2

R/W

PB1

R/W

(DDRA)

R/W

Note: Only MB90675 series has P81 through P86, P90, PA0 through PA7, and PB0 through PB2, and MB90670 series does not

have such pins.

44

MB90670/675 Series

2. Timebase Timer

The timebase timer is a 18-bit free-run counter (timebase counter) for counting up in synchronization to the

internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from

four types of 2¹²/HCLK, 2¹⁴/HCLK, 2¹⁶/HCLK, and 2¹⁹/HCLK.

The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation

stabilization time or the watchdog timer etc.

(1) Register Configuration

• Timebase timer control register (TBTC)

. . . . . . . . . . . .

Address

0000A9^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

TBIE TBOF TBR TBC1 TBC0

R/W R/W R/W R/W

bit 0

Initial value

1--00100^B

(WDTC)

—

RESV

R/W

W

R/W: Readable and writable

W : Read only

— : Unused

(2) Block Diagram

To watchdog timer

To PPG timer

Timebase timer counter

× 2¹× 2²× 2³

× 2⁸× 2⁹

× 2¹⁰

× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

. . . . . .

Divided-by-2

of HCLK

OF

To oscillation stabilization

time selector of clock control block

Power-on reset

Counter

clear circuit

Interval

timer selector

Start stop mode

CKSCR : MCS = 1→0*¹

Set TBOF

Clear TBOF

Timebase timer control register

(TBTC)

—

TBIE TBOF TBR TBC1 TBC0

Timebase timer

interrupt signal

#34(22^H)*²

OF : Overflow

HCLK: Oscillation clock

*1

*2

: Switch machine clock from oscillation clock to PLL clock

: Interrupt number

45

MB90670/675 Series

3. Watchdog Timer

The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when

the counter is not cleared for a preset period of time.

(1) Register Configuration

• Watchdog timer control register (WDTC)

. . . . . . . . . . . .

(TBTC)

Address bit 15

0000A8^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

WT1

W

bit 0

WT0

W

Initial value

B

PONR STBR WRST ERST SRST WTE

XXXXX111

R

W

R : Read only

W: Write only

X : Indeterminate

(2) Block Diagram

Watchdog timer control register (WDTC)

PONR STBR WRST ERST SRST WTE WT1 WT0

2

Watchdog timer

CLR and start

Overflow

CLR

Start sleep mode

Counter clear

control circuit

Count clock

selector

2-bit

counter

Watchdog reset

generation circuit

To internal reset

generation circuit

Start hold status

Start stop mode

CLR

4

Clear

(Timebase timer counter)

Divided-by-2

of HCLK

× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

× 2⁸

× 2¹× 2²

. . .

HCLK: Oscillation clock

46

MB90670/675 Series

4. 8/16-bit PPG Timer

The 8/16-bit PPG timer is 2-channel reload timer module for outputting pulse having given frequencies/duty

ratios.

The two modules performs the following operation by combining functions.

• 8-bit PPG output 2-channel independent operation mode

This is a mode for operating independent 2-channel 8-bit PPG timer, in which PPG0 and PPG1 pins correspond

to outputs from PPG0 and PPG1 respectively.

• 16-bit PPG output operation mode

In this mode, PPG0 and PPG1 are combined to be operated as a 1-channel 8/16-bit PPG timer operating as

a 16-bit timer. Because PPG0 and PPG1 outputs are reversed by an underflow from PPG1 outputting the

same output pulses from PPG0 and PPG1 pins.

• 8 + 8-bit PPG output operation mode

In this mode, PPG0 is operated as an 8-bit prescaler, in which an underflow output of PPG0 is used as a clock

source for PPG1. A toggle output of PPG0 and PPG output of PPG1 are output from PPG0 and PPG1

respectively.

The module can also be used as a D/A converter with an external add-on circuit.

(1) Register Configuration

• PPG0 operating mode control register (PPGC0)

. . . . . . . . . . . .

Address bit 15

bit 8 bit 7

bit 6

bit 5

POE0 PIE0 PUF0 PCM1 PCM0 RESV

R/W R/W R/W R/W R/W R/W

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

000030^H

(PPGC1)

PEN0

R/W

—

B

0 - 000001

• PPG1 operating mode control register (PPGC 1)

. . . . . . . . . . . .

(PPGC0)

Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

bit 0

Initial value

000031^H

B

PEN1 PCS1 POE1 PIE1 PUF1 MD1

MD0 RESV

R/W R/W

00000001

R/W

• PPG reload register (PRLL0,PRLH0,PRLL1,PRLH1)

. . . . . . . . . . . .

Address bit 15

PRLH0:000035^H

PRLH1:000037^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

R/W

bit 1

R/W

bit 0

Initial value

(PRLH0,PRLH1 )

B

XXXXXXXX

R/W

Address

PRLL0:000034^H

PRLL1:000036^H

. . . . . . . . . . . .

bit 0

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

Initial value

(PRLL0,PRLL1)

B

XXXXXXXX

R/W

R/W: Readable and writable

— : Unused

X : Indeterminate

47

MB90670/675 Series

(2) Block Diagram

• Block diagram of 8/16-bit PPG timer 0

Data bus for “H” digits

Data bus for “L” digits

PPG0 reload

register

PPG0 operating mode control register (PPGC0)

PEN0

—

POE0 PIE0 PUF0 PCM1 PCM0 RESV

PRLH0

PRLL0

R

S

Temporary buffer

(PRLBH0)

Interrupt request

#29 (1D^H)*

Q

2

Mode control signal

Select signal

Reload selector

(L/H selector)

PPG1 underflow

PPG0 underflow

(to PPG1)

Count value

reload

Clear

Pulse selector

Underflow

Down counter

(PCNT0)

CLK

PPG0

output latch

Reverse

P46/PPG0

PPG output

control circuit

Timebase timer output (512/HCLK)

Peripheral clock (16/φ)

Peripheral clock (4/φ)

Peripheral clock (1/φ)

Count clock selector

2

Select signal

*

: Interrupt number

HCLK: Oscillation clock

: Machine clock frequency

φ

48

MB90670/675 Series

• Block diagram of 8/16-bit PPG timer 1

Data bus for “H” digits

Data bus for “L” digits

PPG1 operating mode control register (PPGC1)

PPG1 reload

register

PEN1 PCS1 POE1 PIE1 PUF1 MD1 MD0 RESV

PRLH1

PRLL1

2

Operating mode

control signal

R

S

Temporary buffer

(PRLBH0)

Interrupt request

#30 (1E^H)*

Q

reload selector

(L/H selector)

Select signal

Count value

reload

Clear

Underflow

Down counter

(PCNT1)

PPG1

output latch

Reverse

MD0

P80/PPG1

CLK

PPG output control circuit

PPG1 underflow

(to PPG0)

PPG0 underflow

Timebase timer output (512/HCLK)

Peripheral clock (1/φ)

Count clock selector

Select signal

*

: Interrupt number

HCLK: Oscillation clock

: Machine clock frequency

φ

49

MB90670/675 Series

5. 16-bit Reload Timer

The 16-bit reload timer has an internal clock mode for counting down in synchronization to three types of internal

clocks and an event count mode for counting down detecting a given edge of the pulse input to the external bus

pin, and either of the two functions can be selectively used.

For this timer, an “underflow” is defined as the counter value of “0000^H” to “FFFF^H”. According to this definition,

an underflow occurs after [reload register setting value + 1] counts.

In operating the counter, the reload mode for repeating counting operation after reloading a counter setting

value after an underflow or the one-shot mode for stopping the counting operation after an underflow can be

selectively used.

Because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent

I/O service (EI²OS).

The MB90670/675 series has 2 channels of 16-bit reload timers.

(1) Register Configuration

• Timer control status register upper digits (TMCSR0,TMCSR1 : H)

. . . . . . . . . . . . .

(TMCSR : L)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

CSL1 CSL0 MOD2 MOD1

R/W R/W R/W R/W

bit 0

Initial value

Address

TMCSR0:000039^H

TMCSR1:00003D^H

B

- - - -0000

—

• Timer control status register lower digits (TMCSR0,TMCSR1 : L)

. . . . . . . . . . . . .

bit 15 bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

CNTE TRG

R/W R/W

bit 0

Initial value

Address

TMCSR0:000038^H

TMCSR1:00003C^H

B

00000000

(TMCSR : H)

MOD1 OUTE OUTL RELD INTE

R/W R/W R/W R/W R/W

UF

R/W

• 16-bit timer register 0, 1 (TMR0,TMR1)

bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Initial value

XXXXXXXX^B

Address

00003A^H

00003B^H

00003E^H

00003F^H

R

• 16-bit reload register 0, 1 (TMRL0,TMRL1)

bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Initial value

XXXXXXXX^B

Address

00003A^H

00003B^H

00003E^H

00003F^H

W

R/W : Readable and writable

: Read only

R

W : Write only

— : Unused

X

: Indeterminate

50

MB90670/675 Series

(2) Block Diagram

Internal data bus

TMRLR0*¹

16-bit reload register

reload signal

reload

control circuit

TMRR0*¹

<TMR1>

16-bit timer register (down counter) UF

CLK

Count clock generation circuit

Gate input

Wait signal

3

Valid clock

decision

circuit

Prescaler

φ

To UART0, 1*¹

Clear

CLK

Internal

clock

Output control circuit

Output

Input

control

circuit

generation circuit

Clock

selector

P26/TOT0*¹

Reverse

EN

External

clock

P24/TIN0*¹

3

2

Select

signal

Operation

control circuit

Function select

—

— CSL1CSL0MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG

Timer control status register (TMCSR0)*¹

Interrupt request signal

#29 (1DH)*²

<#30 (1EH)>

*1: The timer has ch.0 and ch.1, and listed in the parenthesis <> are for ch.1.

*2: Interrupt number

φ: Machine clock frequency

51

MB90670/675 Series

6. 24-bit Free-run Timer

The 24-bit free-run timer is a 24-bit up counter for counting up in synchronization to divided-by-3 or divided-by-

4 of the machine clock, in which an interrupt factor can be selected from the overflow interrupt and four types

of timer intermediate bit interrupt to be operated as an interval timer.

The free-run timer can be used to generating reference timing signals for the input capture (ICU) and output

compare (OCU).

(1) Register Configuration

• Free-run timer control register upper digits (TCCR : H)

. . . . . . . . . . . . .

(TCCR : L)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

RESV RESV RESV RESV RESV PR0

R/W R/W R/W R/W R/W R/W

bit 0

Initial value

Address

000051^H

B

- -111111

—

• Free-run timer control register lower digits (TCCR : L)

. . . . . . . . . . . . .

Address

bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

TIME TIS1

R/W R/W

bit 1

bit 0

TIS0

R/W

Initial value

11000000^B

000050^H

(TCCR : H)

STP

W

CLR

W

IVF

IVFE

R/W

TIM

R/W

• Free-run timer upper data register (TCRH)

bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Address

000056^H

000057^H

Initial value

00000000^B

—

R

—

R

—

R

—

R

—

R

—

R

—

R

—

R

T23 T22 T21 T20 T19 T18 T17 T16

R

• Free-run timer lower data register (TCRL)

bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Address

000054^H

000055^H

Initial value

00000000^B

T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0

R

R/W : Readable and writable

R

: Read only

W : Write only

— : Unused

52

MB90670/675 Series

(2) Block Diagram

Internal data bus

24-bit counter

(TCR)

Output buffer

8

T16 to T23 To output compare (OCU)

16

T0 to T15

To input capture (ICU)

TCRH

TCRL

Carry

Upper 8-bit counter

Lower 16-bit counter

Carry

4

Prescaler

φ

φ/3

Count

clock

selector

Intermediate

bit interrupt

φ/4

control circuit

Select signal

Pause

Carry

detection

Overfolw

—

RESV RESV RESV RESV RESV PR0 STP CLR IVF IVFE TIM TIME TIS1 TIS0

Free-run timer control register (TCCR)

Intermediate bit interrupt

request signal

#24 (18H)*

* : Interrupt number

φ: Machine clock frequency

Overflow interrupt

request signal

#23 (17H)*

53

MB90670/675 Series

7. Input Capture (ICU)

The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of

current counter value of the 24-bit free-run timer to the ICU data register (ICDR) upon an input of a trigger edge

to the external pin.

There are four sets (four channels) of the input capture external pins and ICU data registers (ICDR), enabling

measurements of maximum of four events.

• The input capture has four sets of external input pins (ASR0 to ASR3) and ICU registers (ICDR), enabling

measurements of maximum of four events.

• A trigger edge direction can be selected from rising/falling/both edges.

• The input capture can be set to generate an interrupt request at the storage timing of the counter value of the

24-bit free-run timer to the ICU data register (ICDR).

• The input compare conforms to the extended intelligent I/O service (EI²OS).

• The input capture function is suited for measurements of intervals (frequencies) and pulse-widths.

(1) Register Configuration

• ICU control register upper digits (ICC : H)

. . . . . . . . . . . . .

(ICC : L)

Address

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

bit 0

Initial value

00000000^B

IRE3 IRE2

R/W R/W

IRE1 IRE0

R/W R/W

IR3

IR2

IR1

IR0

000053^H

R/W

• ICU control register lower digits (ICC : L)

. . . . . . . . . . . .

bit 15

Address

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

00000000^B

(ICC : H)

EG3B EG3A EG2B EG2A EG1B EG1A EG0B EG0A

000052^H

R/W

• ICU upper data register 0 to 3 (ICDR0H to ICDR3H)

Address

ICDR0H : 000063^H

ICDR1H : 000067^H

ICDR2H : 00006B^H

ICDR3H : 00006F^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8

Initial value

00000000^B

—

R

—

R

—

R

—

R

—

R

—

R

—

R

—

R

Address

ICDR0H : 000062^H

ICDR1H : 000066^H

ICDR2H : 00006A^H

ICDR3H : 00006E^H

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

D16

R

Initial value

D23

R

D22

R

D21

R

D20

R

D19

R

D18

R

D17

R

XXXXXXXX^B

• ICU lower data register 0 to 3 (ICDR0L to ICDR3L)

Address

ICDR0L : 000061^H

ICDR1L : 000065^H

ICDR2L : 000069^H

ICDR3L : 00006D^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8

Initial value

D15

R

D14

R

D13

R

D12

R

D11

R

D10

R

D9

R

D8

R

XXXXXXXX^B

Address

ICDR0L : 000060^H

ICDR1L : 000064^H

ICDR2L : 000068^H

ICDR3L : 00006C^H

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

D0

R

Initial value

D7

R

D6

R

D5

R

D4

R

D3

R

D2

R

D1

R

XXXXXXXX^B

R/W : Readable and writable

R

: Read only

— : Unused

: Indeterminate

X

54

MB90670/675 Series

(2) Block Diagram

Internal data bus

Output latch

Latch

signal

ICU data register

(ICDR)

Edge detection circuit

P61/ASR0

24

Data latch signal

ICDR0H

ICDR1H

ICDR2H

ICDR3H

ICDR0L

2

P65/ASR1

24

ICDR1L

2

24-bit free-run

P66/ASR2

24

timer

ICDR2L

ICDR3L

2

P67/ASR3

2

ICU control

register (ICC)

IRE3 IRE2 IRE1 IRE0 IR3 IR2 IR1 IR0 EG3B EG3A EG2B EG2A EG1B EG1A EG0B EG0A

#25 (19^H)*

#26 (1A^H)*

Input capature interrupt

request signal

#27 (1B^H)*

#28 (1C^H)*

*: Interrupt number

55

MB90670/675 Series

8. Output Compare (OCU)

The output compare (OCU) is two sets of compare units consisting of four-channel OCU compare data registers,

a comparator and a control register.

An interrupt request can be generated for each channel upon a match detection by performing time-division

comparison between the OCU compare data register setting value and the counter value of the 24-bit free-run

timer.

The DOT pin can be used as a waveform output pin for reversing output upon a match detection or a general-

purpose output port for directly outputting the setting value of the DOT bit.

(1) Register Configuration

• OCU control register 00 upper digits (CCR00 : H)

. . . . . . . . . . . . .

(CCR00 : L)

Address

000059^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

bit 0

Initial value

B

—

MD3

R/W

MD2 MD1

R/W R/W

MD0

R/W

- - - -0000

• OCU control register 00 lower digits (CCR00 : L)

. . . . . . . . . . . .

bit 15

Address

000058^H

bit 8 bit 7

RESV RESV RESV RESV CPE3 CPE2 CPE1 CPE0

R/W R/W R/W R/W R/W R/W R/W R/W

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

11110000^B

(CCR00 : H)

• OCU control register 01 upper digits (CCR01 : H)

. . . . . . . . . . . . .

(CCR01 : L)

Address

00005B^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

bit 0

Initial value

00000000^B

ICE3

R/W

ICE2 ICE1

R/W R/W

ICE0

R/W

IC3

IC2

IC1

IC0

R/W

• OCU control register 01 lower digits (CCR01 : L)

. . . . . . . . . . . .

bit 15

Address

00005A^H

bit 8 bit 7

bit 6

—

bit 5

bit 4

bit 3

DOT3 DOT2 DOT1 DOT0

R/W R/W R/W R/W

bit 2

bit 1

bit 0

Initial value

B

- - - -0000

(CCR01 : H)

—

R/W : Readable and writable

— : Unused

(Continued)

56

MB90670/675 Series

(Continued)

• OCU compare upper data register 0 to 7 (CPR00H to CPR07H)

Address

CPR00H : 000073^H

CPR01H : 000077^H

CPR02H : 00007B^H

CPR03H : 00007F^H

CPR04H : 000083^H

CPR05H : 000087^H

CPR06H : 00008B^H

CPR07H : 00008F^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

Initial value

00000000^B

—

R/W

Address

CPR00H : 000072^H

CPR01H : 000076^H

CPR02H : 00007A^H

CPR03H : 00007E^H

CPR04H : 000082^H

CPR05H : 000086^H

CPR06H : 00008A^H

CPR07H : 00008E^H

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

D16

R/W

Initial value

00000000^B

D23

R/W

D22

R/W

D21

R/W

D20

R/W

D19

R/W

D18

R/W

D17

R/W

• OCU compare lower data register 0 to 7 (CPR00L to CPR07L)

Address

CPR00L : 000071^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

Initial value

00000000^B

CPR01L : 000075^H

CPR02L : 000079^H

CPR03L : 00007D^H

CPR04L : 000081^H

CPR05L : 000085^H

CPR06L : 000089^H

CPR07L : 00008D^H

D15

R/W

D14

R/W

D13

R/W

D12

R/W

D11

R/W

D10

R/W

D9

D8

R/W

Address

CPR00L : 000070^H

CPR01L : 000074^H

CPR02L : 000078^H

CPR03L : 00007C^H

CPR04L : 000080^H

CPR05L : 000084^H

CPR06L : 000088^H

CPR07L : 00008C^H

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

D0

Initial value

00000000^B

D7

D6

D5

D4

D3

D2

D1

R/W

R/W : Readable and writable

— : Unused

57

MB90670/675 Series

(2) Block Diagram of Output Compare (OCU)

• Overall block diagram

Free-run timer data

Output compare unit

4

MATCH0 to MATCH3

23

T1 to T23

4

Interrupt request

(ICOMP0 to ICOMP3)

ICOMP0 to ICOMP3

16

RB15 to RB0

Output compare unit 00 to 03

(unit 0)

DOT0 to DOT3

P70/DOT0 to P73/DOT3

4

EXT0 to EXT3

OPEN

MATCH4 to MATCH7

T1 to T23

4

Interrupt request

(ICOMP4 to ICOMP7)

ICOMP4 to ICOMP7

16

RB15 to RB0

Output compare unit 04 to 07

(unit 1)

DOT4 to DOT7

P74/DOT4 to P77/DOT7

EXT0 to EXT3

58

MB90670/675 Series

• Block diagram of unit 0

OCU control register 00 (CCR00)

—

MD3 MD2 MD1 MD0 RESV RESV RESV RESV CPE3 CPE2 CPE1 CPE0

4

Match operation enabled

4

General-purpose port/

compare pin switching

MATCH0 to MATCH3

(to unit 1)

Compare circuit

24-bit free-run timer

Output

control circuit

T1 T0

2

bit 23 to bit 2

Compare

control

Clock

selector

4

Compare control block

Data latch

Match

signal

4

P73/DOT3

CPR00H

CPR01H

CPR02H

CPR03H

CPR00L

CPR01L

CPR02L

CPR03L

P72/DOT2

Output

latch

P71/DOT1

P70/DOT0

OCU compare data register 0 to 3

—

ICE3 ICE2 ICE1 ICE0 IC3 IC2

IC1 IC0

DOT3 DOT2 DOT1 DOT0

OCU control register 01 (CCR01)

#15 (0F^H)*

#16 (10^H)*

Output compare

interrupt request signal

#17 (11^H)*

#18 (12^H)*

* : Interrupt number

59

MB90670/675 Series

• Block diagram of unit 1

OCU control register10 (CCR10)

—

MD3 MD2 MD1 MD0 SEL3 SEL2 SEL1 SEL0 CPE3 CPE2 CPE1 CPE0

4

Output control circuit

4

General-purpose port/compare pin switching

MATCH0 to MATCH3

(from unit 0)

4

Factor

selector

4

Compare circuit

Match

operation

enabled

2

24-bit free-run timer

bit 23 to bit 2

T1 T0

Compare

control

Clock

selector

4

Compare control block

Match

signal

4

Data latch

P77/DOT7

CPR04H

CPR05H

CPR06H

CPR04L

P76/DOT6

CPR05L

CPR06L

CPR07L

Output

latch

P75/DOT5

P74/DOT4

CPR07H

OCU compare data register 4 to 7

ICE3 ICE2 ICE1 ICE0 IC3

IC2

IC1 IC0

—

DOT3 DOT2 DOT1 DOT0

OCU control register 11 (CCR11)

#19 (13^H)*

#20 (14^H)*

Output compare

interrupt request signal

#21 (15^H)*

#22 (16^H)*

* : Interrupt number

60

MB90670/675 Series

9. I²C Interface (Included Only in MB90675 Series)

The I²C interface is a serial I/O port supporting Inter IC BUS operating as master/slave devices on I²C bus and

has the following features.

• Master/slave transmission/reception

• Arbitration function

• Clock synchronization function

• Slave address/general call address detection function

• Transmission direction detection function

• Repeated generation function start condition and detection function

• Bus error detection function

(1) Register Configuration

• I²C bus status register (IBSR)

. . . . . . . . . . . .

Address bit 15

000040^H

Initial value

00000000^B

bit 8 bit 7

BB

bit 6

bit 5

AL

bit 4

LRB

bit 3

TRX

bit 2

AAS

bit 1

bit 0

FBT

(IBCR)

RSC

GCA

R

• I²C bus control register (IBCR)

. . . . . . . . . . . .

Address

000041^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

INT

bit 0

Initial value

00000000^B

(IBSR)

BER BEIE SCC

R/W R/W R/W

MSS

R/W

ACK GCAA INTE

R/W R/W R/W

R/W

• I²C bus clock control register (ICCR)

. . . . . . . . . . . .

Address bit 15

000042^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

CS2

R/W

bit 1

CS1

R/W

bit 0

CS0

R/W

Initial value

--0XXXXX^B

(IADR)

—

EN

CS4

R/W

CS3

R/W

• I²C address register (IADR)

. . . . . . . . . . . .

bit 0

Address

000043^H

(IADR)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8 bit 7

A0

Initial value

-XXXXXXX^B

(ICCR)

—

A6

A5

A4

A3

A2

A1

R/W

. . . . . . . . . . . .

Address bit 15

000044^H

(IDAR)

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

D2

bit 1

D1

bit 0

D0

R/W

Initial value

(Reserved area)

D7

D6

D5

D4

D3

XXXXXXXX^B

R/W

R/W: Readable and writable

R : Read only

— : Uunsed

X : Indeterminate

61

MB90670/675 Series

(2) Block Diagram

Internal data bus

I²C bus status register

I²C bus control register

(IBCR)

(IBSR)

BER BEIE SCC MSS ACK GCAA INTE INT

BB RSC AL LRB TRX AAS GCA FBT

Number of

interrupt

Start stop condition

generation circuit

Start stop condition

detection circuit

request

generated

Interrupt request signal

#38 (26^H)*

SDA line

CCL line

P90/SDA

I²C enable

P91/SCL

IDAR register

Arbitration lost

detection circuit

Slave address

comparison circuit

IADR register

Clock control block

Sync

Clock

4

Count

clock

selector 1

8

Count

clock

selector 2

Shift clock

generation

circuit

divider 1

(1/5 to

1/8)

Clock

divider 2

φ

I²C enable

—

EN CS4 CS3 CS2 CS1 CS0

I²C bus clock control register

(ICCR)

φ: Machine clock frequency

* : Interrupt number

62

MB90670/675 Series

10. UART0

UART0 is a general-purpose serial data communication interface for performing synchronous or asynchronous

communication (start-stop synchronization system). In addition to the normal duplex communication function

(normal mode), UART0 has a master/slave type communication function (multi-processor mode).

• Data buffer: Full-duplex double buffer

• Transfer mode: Clock synchronized (with start and stop bit)

Clock asynchronized (start-stop synchronization system)

• Baud rate: With dedicated baud rate generator, selectable from 12 types

External clock input possible

Internal clock (a clock supplied from 16-bit reload timer can be used.)

• Data length: 7 bits to 9 bits selective (with a parity bit)

6 bits to 8 bits selective (without a parity bit)

• Signal format: NRZ (Non Return to Zero) system

• Reception error detection: Framing error

Overrun error

Parity error (not available in multi-processor mode)

• Interrupt request: Receive interrupt (reception complete, receive error detection)

Receive interrupt (transmission complete)

Transmit/receive conforms to extended intelligent I/O service (EI²OS)

• Master/slave type communication function (multi-processor mode): 1 (master) to n (slave) communication

possible

(1) Register Configuration

• Status register 0 (USR0)

. . . . . . . . . . . . .

(UMC0)

Address

000021^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

bit 0

Initial value

00100000^B

RDRF ORFE

R/W R/W

PE

TDRE RIE

R/W R/W

TIE

RBF

R/W

TBF

R/W

• Mode control register 0 (UMC0)

. . . . . . . . . . . .

Address

000020^H

bit 15

bit 8 bit 7

PEN

bit 6

bit 5

MC1 MC0 SMDE RFC SCKE SOE

R/W R/W R/W R/W R/W R/W

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

00000100^B

(USR0)

SBL

R/W

• Rate and data register 0 (URD0)

. . . . . . . . . . . . .

Address

000023^H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

bit 0

Initial value

00000000^B

(UIDR0/UODR0)

BCH RC3

R/W R/W

RC2

R/W

RC1

R/W

RC0 BCH0

R/W R/W

P

D8

R/W

• Input data register 0 (UIDR0)

. . . . .

bit 9 bit 8

Address

000022^H

bit 15

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

D2

R

bit 1

D1

R

bit 0

D0

R

Initial value

(URD0) D8

D7

R

D6

R

D5

R

D4

R

D3

R

XXXXXXXX^B

R

• Output data register 0 (UODR)

. . . . .

Address

bit 15

bit 9 bit 8

bit 7

D7

W

bit 6

D6

W

bit 5

D5

W

bit 4

D4

W

bit 3

D3

W

bit 2

D2

W

bit 1

D1

W

bit 0

D0

W

Initial value

000022^H

(URD0)

D8

W

XXXXXXXX^B

R/W : Readable and writable

: Read only

W : Write only

: Indeterminate

R

X

63

MB90670/675 Series

(2) Block Diagram

Control bus

Receive

interrupt signal

#39 (27^H)*

Dedicated baud

rate generator

Transmit

clock

Transmit

interrupt signal

#36 (24^H)*

Clock

16-bit reload

timer 0

selector

Receive

clock

Transmit

control circuit

Receive

control circuit

P42/SCK0

Start bit

detection circuit

Transmit start

circuit

Receive bit

counter

Transmit bit

counter

Receive parity

counter

Transmit parity

counter

P42/SOT0

Shift register for

reception

Shift register for

transmission

P40/SIN0

Reception

complete

Start transmission

UIDR0

UODR0

Receive condition

decision circuit

To EI²OS reception

error generation

signal (to CPU)

Internal data bus

BCH

RC3

RDRF

ORFE

PE

TDRE

RIE

TIE

RBF

TBF

PEN

SBL

RC2

RC1

RC0

BCH0

P

MC1

MC0

SMDE

RFC

SCKE

SOE

UMC0

register

USR0

register

URD0

register

D8

* : Interrupt number

64

MB90670/675 Series

11. UART1 (SCI)

UART1 (SCI) is a general-purpose serial data communication interface for performing synchronous or

asynchronous communication (start-stop synchronization system). In addition to the normal duplex

communication function (normal mode), UART1 has a master-slave type communication function (multi-

processor mode).

• Data buffer: Full-duplex double buffer

• Transfer mode: Clock synchronized (no start or stop bit)

Clock asynchronized (start-stop synchronization system)

• Baud rate: With dedicated baud rate generator, selectable from 8 types

External clock input possible

Internal clock (a internal clock supplied from 16-bit reload timer can be used.)

• Data length: 7 bits (for asynchronous normal mode only)

8 bits

• Signal format: NRZ (Non Return to Zero) system

• Reception error detection: Framing error

Overrun error

Parity error (not available in multi-processor mode)

• Interrupt request: Receive interrupt (receptioncomplete, receive error detection)

Receive interrupt (transmission complete)

Transmit/receive conforms to extended intelligent I/O service (EI²OS)

• Master/slave type communication function (multi-processor mode):1 (master) to n (slave) communication

possible (supported only for master station)

(1) Register Configuration

• Control register 1 (SCR1)

............

(SMR1)

Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7

PEN SBL CL A/D REC RXE TXE

R/W R/W R/W R/W R/W R/W R/W R/W

bit 0

Initial value

00000100^B

P

000025^H

• Mode register 1 (SMR1)

............

(SCR1)

Address bit 15

bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

MD1 MD0 CS2 CS1 CS0 BCH SCKE SOE

R/W R/W R/W R/W R/W R/W R/W R/W

Initial value

00000000^B

000024^H

• Status register 1 (SSR1)

............

Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7

bit 0

Initial value

00001-00^B

PE ORE FRE RDRF TDRE

—

RIE TIE (SIDR1/SODR1)

R/W R/W

000027^H

R

• Input data register 1 (SIDR1)

............

Address bit 15

bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Initial value

(SSR1)

D7

R

D6

R

D5

R

D4

R

D3

R

D2

R

D1

R

D0

R

000026^H

XXXXXXXX^B

• Output data register 1 (SODR1)

............

Address bit 15

bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Initial value

(SSR1)

D7

W

D6

W

D5

W

D4

W

D3

W

D2

W

D1

W

D0

W

000026^H

XXXXXXXX^B

R/W: Readable and writable

R : Read only

W : Write only

— : Unused

X : Indeterminate

65

MB90670/675 Series

(2) Block Diagram

Control bus

Receive

interrupt signal

#37 (25^H)*

Transmit

interrupt signal

#35 (23^H)*

Dedicated baud

rate generator

Transmit

clock

Clock

selector

16-bit reload

timer 1

Receive

clock

Transmit

control circuit

Receive

control circuit

P45/SCK1

Start bit

Transmit start

detection circuit

circuit

Receive bit

counter

Transmit bit

counter

Receive parity

counter

Transmit parity

counter

P44/SOT1

Shift register for

reception

Shift register for

transmission

P43/SIN1

Reception

complete

Start transmission

SIDR1

SODR1

Receive condition

decision circuit

To EI²OS reception

error generation

signal (to CPU)

s

l data bu

Interna

MD1

MD0

CS2

CS1

CS0

BCH

PEN

P

PE

ORE

FRE

RDRF

TDRE

SBL

CL

A/D

REC

RXE

TXE

SMR1

register

SCR1

register

SSR1

register

SCKE

SOE

RIE

TIE

*: Interrupt number

66

MB90670/675 Series

12. DTP/External Interrupt Circuit

TheDTP(DataTransferPeripheral)/externalinterruptcircuitislocatedbetweenperipheralequipmentconnected

externally and the F²MC-16L CPU and transmits interrupt requests or data transfer requests generated by

peripheral equipment to the CPU, generates external interrupt request and starts the extended intelligent I/O

service (EI²OS).

(1) Register Configuration

• DTP/interrupt factor register (EIRR)

. . . . . . . . . . . .

(ENIR)

Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

000029^H

bit 9

bit 8 bit 7

bit 0

Initial value

B

—

ER3

R/W

ER2

R/W

ER1

R/W

ER0

R/W

- - - - 0000

• DTP/interrupt enable register (ENIR)

. . . . . . . . . . . .

Address bit 15

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

EN0

Initial value

000028^H

B

(EIRR)

—

EN3

R/W

EN2

R/W

EN1

R/W

- - - - 0000

R/W

• Request level setting register (ELVR)

. . . . . . . . . . . .

Address bit 15

00002A^H

bit 8 bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

00000000^B

(Vacancy)

LB3

R/W

LA3

R/W

LB2

R/W

LA2

R/W

LB1

R/W

LA1

R/W

LB0

R/W

LA0

R/W

R/W: Readable and writable

— : Unused

67

MB90670/675 Series

(2) Block Diagram

Request level setting register (ELVR)

LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

2

P60/INT0

Level edge

selector 3

Level edge

selector 1

Level edge

selector 2

Level edge

selector 0

P61/INT1

DTP/external interrupt input

detection circuit

P62/INT2

P63/INT3

DTP/interrupt factor register

(EIRR)

—

ER3 ER2 ER1 ER0

Interrupt request signal

#14 (0E^H)*

#13 (0D^H)*

#14 (0C^H)*

#11 (0B^H)*

DTP/interrupt enable register

(ENIR)

—

EN3 EN2 EN1 EN0

*: Interrupt signal

68

MB90670/675 Series

13. Wake-up Interrupt

Wake-up interrupts transmits interrupt request (“L” level) generated by peripheral device located between

external peripheral devices and the F²MC-16L CPU to the CPU and invokes interrupt processing.

The interrupt does not conform to the extended intelligent I/O service (EI²OS).

(1) Register Configuration

• Wake-up interrupt flag register (EIFR)

Address

00000F^H

. . . . . . . . . . . .

(Vacancy)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

bit 0

Initial value

—

WIF

R/W

B

- - - - - - - 0

• Wake-up interrupt enable register (EICR)

Address

. . . . . . . . . . . .

(Vacancy)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

Initial value

00000000^B

00001F^H

EN7

R/W

EN6

R/W

EN5

R/W

EN4

R/W

EN3

R/W

EN2

R/W

EN1

R/W

EN0

R/W

R/W: Readable and writable

— : Unused

(2) Block Diagram

Internal data bus

Wake-up interrupt

enable register (EICR)

Wake-up interrupt flag

register (EIFR)

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

—

WIF

Interrupt request detection circuit

P10/AD08/WI0

P11/AD09/WI1

P12/AD10/WI2

Wake-up interrupt

request

#33 (21^H)*

P13/AD11/WI3

P14/AD12/WI4

P15/AD13/WI5

P16/AD14/WI6

P17/AD15/WI7

*: Interrupt number

69

MB90670/675 Series

14. Delayed Interrupt Generation Module

The delayed interrupt generation module generates interrupts for switching tasks for development on a real-

time operating system (REALOS software). The module can be used to generate hardware interrupt requests

to the CPU with software and cancel the interrupt requests.

This module does not conform to the extended intelligent I/O service (EI²OS).

(1) Register Configuration

• Delayed interrupt factor generation/cancellation register (DIRR)

. . . . . . . . . . . .

Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

bit 8 bit 7

bit 0

Initial value

00009F^H

—

R0

(Reserved area)

B

- - - - - - - 0

—

R/W

R/W: Readable and writable

— : Unused

(2) Block Diagram

Internal data bus

—

R0

S factor

R latch

Interrupt request signal

#42 (2A^H)*

Delayed interrupt factor generation/

cancellation register (DIRR)

*: Interrupt signal

70

MB90670/675 Series

15. 8/10-bit A/D Converter

The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input

voltage) to digital values (A/D conversion) and has the following features.

• Minimum conversion time: 6.13 µs (at machine clock of 16 MHz, including sampling time)

• Minimum sampling time: 3.75 µs (at machine clock of 16 MHz)

• Conversion method: RC successive approximation method with a sample and hold circuit.

• Resolution: 10-bit or 8-bit selective

• Analog input pins: Selectable from eight channels by software

One-shot conversion mode:Stops conversion after completing a conversion for a stopped channel (one

channel only) or for successive channels (maximum of eight channels can be

specified)

Continuous conversion mode:Continues conversions for a specified channel (one channel only) or for

successive channels (maximum of eight channels can be specified)

Stop conversion mode:Stops conversion after completing a conversion for one channel and wait for the next

activation.

• Interrupt requests can be generated and the extended intelligent I/O service (EI²OS) can be started after the

end of A/D conversion.

• When interrupts are enabled, there is no loss of data even in continuous operations because the conversion

data protection function is in effect.

• Starting factors for conversion: Selected from software activation, 16-bit reload timer 1 output (rising edge),

and external trigger (falling edge).

(1) Register Configuration

• A/D control status register upper digits (ADCS: H)

. . . . . . . . . . . .

(ADCS: L)

Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

INTE PAUS STS1 STS0 STRT RESV

R/W R/W R/W R/W R/W

bit 8 bit 7

bit 0

Initial value

00000000^B

00002D^H

BUSY INT

R/W R/W

W

• A/D control status register lower digits (ADCS: L)

. . . . . . . . . . . .

Address bit 15

bit 8 bit 7

bit 6

MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0

R/W R/W R/W R/W R/W R/W R/W

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

00000000^B

00002C^H

(ADCS: H)

MD1

R/W

• A/D data register (ADCR)

Address bit 15bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Initial value

XXXXXXXX^B

0000000X^B

00002E^H

S10

R/W

—

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

R

R/W: Readable and writable

R : Read only

W : Write only

— : Unused

X : Indeterminate

71

MB90670/675 Series

(2) Block Diagram

A/D control status

register (ADCS)

Interrupt request signal #31 (1F^H)*

BUSY

INT INTE PAUS STS1 STS0 STRT RESV MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0

6

2

P47/ATG

TO

Clock selector

Decoder

φ

Comparator

P57/AN7

P56/AN6

P55/AN5

P54/AN4

P53/AN3

P52/AN2

P51/AN1

P50/AN0

Sample hold

circuit

Control circuit

Analog

channel

selector

AVR

AV^CC

AV^SS

D/A converter

A/D data register

(ADCR)

S10

—

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

φ : Machine clock frequency

TO : 16-bit reload timer channel 1 output

: Interrupt number

*

72

MB90670/675 Series

16. Low-power Consumption (Standby) Mode

The F²MC-16L has the following CPU operating mode configured by selection of an operating clock and clock

operation control.

• Clock mode

PLL clock mode: A mode in which the CPU and peripheral equipment are driven by PLL-multiplied oscillation

clock (HCLK).

Main clock mode: A mode in which the CPU and peripheral equipment are driven by divided-by-2 of the

oscillation clock (HCLK).

The PLL multiplication circuits stops in the mainclock mode.

• CPU intermittent operation mode

The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU

intermittently while external bus and peripheral functions are operated at a high-speed.

• Hardware stand-by mode

The hardware standby mode is a mode for reducing power consumption by stopping clock supply (sleep mode)

to the CPU by the low-power consumption control circuit, stopping clock supplies to the CPU and peripheral

functions (timebase timer mode), and stopping oscillation clock (stop mode, hardware standby mode).

Of these modes, modes other than the PLL clock mode are power consumption modes.

(1) Register Configuration

• Clock select register (CKSCR)

. . . . . . . . . . . .

(LPMCR)

Address

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10

bit 9

CS1

W

bit 8 bit 7

CS0

bit 0

Initial value

0000A1^H

RESV MCM WS1 WS0 RESV MCS

B

11111100

R/W

R

R/W

• Low-power consumption mode control register (LPMCR)

. . . . . . . . . . . .

Address bit 15

bit 8 bit 7

bit 6

SLP

W

bit 5

SPL

R/W

bit 4

RST RESV CG1

R/W R/W

bit 3

bit 2

bit 1

CG0 RESV

R/W R/W

bit 0

Initial value

0000A0^H

B

(CKSCR)

STP

00011000

W

R/W: Readable and writable

R : Read only

W : Write only

73

MB90670/675 Series

(2) Block Diagram

Low-power consumption mode control register (LPMCR)

STP SLP SPL RST RESV CG1 CG0 RESV

Pin Hi-z control

Internal reset

high-impedance

control circuit

Internal reset

generation

circuit

RST Pin

CPUintermittent

operation

Select intermittent cycle

CPU clock

selector

CPU clock

control circuit

Cancellation of reset

RST

2

Stop and sleep signal

Standby control

circuit

Cancellation of interrupt

HST Pin

Stop signal

Machine clock

Cancellation of

oscillation

stabilization time

Peripheral clock

control circuit

Peripheral clock

Clock

generation

block

Oscillation

stabilization

time selector

Clock selector

2

PLL multiplication

circuit

RESV MCM WS1 WS0 RESV MCS CS1 CS0

Clock selection register (CKSCR)

System clock

generation

circuit

Divided

-by-2

Divided

-by-2048

Divided

-by-4

Divided

-by-4

Divided

-by-8

X0

X1

Main clock

Timebase timer

74

MB90670/675 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AV^SS= V^SS= 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

V^CC

V^SS– 0.3

V^SS+ 7.0

V

AV^CC

*1

Power supply voltage

AVRH,

AVRL

V^SS– 0.3

V^SS+ 7.0

V

Input voltage

V^I

V^SS– 0.3

V^CC+ 0.3

15

V

*2

*3

*4

Output voltage

V^O

I^OL

V

“L” level maximum output current

“L” level average output current

mA

mW

°C

I^OLAV

4

“L” level total maximum output current ΣI^OL

100

“L” level total average output current

“H” level maximum output current

“H” level average output current

ΣI^OLAV

50

*5

*3

*4

I^OH

–15

I^OHAV

–4

“H” level total maximum output current ΣI^OH

–100

–50

“H” level total average output current

Power consumption

ΣI^OHAV

*5

P^D

400

Operating temperature

T^A

–40

–55

+85

Storage temperature

Tstg

+150

°C

*1: AV^CC, AVRH, and AVRL shall never exceed V^CC. AVRL shall never exceed AVRH.

*2: V^Iand V^Oshall never exceed V^CC+ 0.3 V.

*3: The maximum output current is a peak value for a corresponding pin.

*4: Average output current is an average current value observed for a 100 ms period for a corresponding pin.

*5: Total average current is an average current value observed for a 100 ms period for all corresponding pins.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

75

MB90670/675 Series

2. Recommended Operating Conditions

(AV^SS= V^SS= 0.0 V)

Remarks

Normal operation

Value

Symbol

Unit

Parameter

Min.

Max.

V^CC

2.7

5.5

V

Power supply voltage

Retains status at the time of

operation stop

2.0

5.5

Operating temperature T^A

–40

+85

°C

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

76

MB90670/675 Series

3. DC Characteristics

Parameter Symbol

(AV^CC= V^CC= 2.7 V to 5.5 V, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Pin name

Condition

Unit Remarks

Min.

Typ.

Max.

Pins other than V^IHS

and V^IHM

V^IH

0.7 V^CC

—

V^CC+ 0.3

V

Hysteresis input pins

P24 to P27, P40 to P47,

P60 to P67, P70 to P77,

P80, HST, RST

MB90670

series

V^IHS

0.8 V^CC

—

V^CC+ 0.3

V

“H” level

input

voltage

Hysteresis input pins

P24 to P27, P40 to P47,

P60 to P67, P70 to P77,

P80 to P86, HST, RST,

P90, P91, PA0 to PA7,

PB0 to PB2

MB90675

series

V^IHS

V

V^IHM

V^IL

MD pin input

V^CC– 0.3

V^SS– 0.3

—

V^CC+ 0.3

0.3 V^CC

V

—

Pins other than V^ILS

and V^ILM

Hysteresis input pins

P24 to P27, P40 to P47,

P60 to P67, P70 to P77,

P80, HST, RST

MB90670

series

V^ILS

V^SS– 0.3

—

0.2 V^CC

V

“L” level

input

voltage

Hysteresis input pins

P24 to P27, P40 to P47,

P60 to P67, P70 to P77,

P80 to P86, HST, RST,

P90, P91, PA0 to PA7,

PB0 to PB2

MB90675

series

V^ILS

V

V^ILM

V^OH

MD pin input

V^SS– 0.3

V^CC– 0.5

—

V^SS+ 0.3

—

V

Other than P50 to

P57

V^CC= 4.5 V

I^OH= –4.0 mA

“H” level

output

voltage

Other than P50 to

P57

V^CC= 2.7 V

I^OH= –1.6 mA

V^OH

V^OL

V^CC– 0.3

—

V

V^CC= 4.5 V

I^OL= 4.0 mA

All output pins

—

0.4

“L” level

output

voltage

V^CC= 2.7 V

I^OL= 2.0 mA

Open-drain

output

leakage

P50 to P57, P90,

P91^*1

I^leak

—

0.1

10

µA

current

Input

leakage

current

Other than P50 to

P57, P90 and P91

V^CC= 5.5 V

V^SS< V^I< V^CC

I^IL

–10

—

10

R

—

V^CC= 5.0 V

V^CC= 3.0 V

25

40

45

95

100

200

kΩ

Pull-up

resistance

kΩ

(Continued)

77

MB90670/675 Series

(Continued)

(AV^CC= V^CC= 2.7 V to 5.5 V, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Parameter Symbol

Pin name

Condition

Unit Remarks

Min.

25

Typ.

50

Max.

200

R

—

V^CC= 5.0 V

V^CC= 3.0 V

kΩ

Pull-down

resistance

40

100

400

Internal

operation at

16 MHz

Normal

mA

I^CC

—

50

10

12

2.5

70

30

20

10

operation*²

V^CCat 5.0 V

Internal

operation at

16 MHz

In sleep

mA

I^CCS

mode*²

V^CCat 5.0 V

Internal

operation at

8 MHz

Normal

mA

Power

supply

current

I^CC

operation*²

V

^CCat 3.0 V

Internal

operation at

8 MHz

In sleep

mA

I^CCS

mode*²

V^CCat 3.0 V

In stop

mode and

µA hardware

standby

I^CCH

—

T^A= +25°C

—

0.1

10

—

mode*²

Input

capacitance

Other than AV^CC,

AV^SS, V^CC, V^SS

C^IN

—

pF

*1: Only MB90675 series has P90 and P91 pins.

*2: The current value is preliminary value and may be subject to change for enhanced characteristics without

previous notice.

78

MB90670/675 Series

4. AC Characteristics

(1) Reset Input Timing, Hardware Standby Input Timing

(AV^CC= V^CC= 2.7 V to 5.5 V, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Min.

Max.

—

Reset input time

t^RSTL

RST

HST

16 t^CP*

ns

—

Hardware standby input time t^HSTL

—

* : For t^CP(internal operating clock cycle time), refer to “(3) Clock Timings.”

t^RSTL, t^HSTL

RST

HST

0.2 V^CC

• Measurement conditions for AC ratings

C^L

C^Lis a load capacitance connected to a pin under test.

CLK, ALE: C^L= 30 pF

Address data bus (AD15 to AD00), RD, WR: C^L= 80 pF

79

MB90670/675 Series

(2) Specification for Power-on Reset

(AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Min.

Max.

Power supply rising time

Power supply cut-off time

t^R

V^CC

—

30

ms

*

—

Due to repeated

operations

t^OFF

1

—

* : V^CCmust be kept lower than 0.2 V before power-on.

Notes: • The above ratings are values for causing a power-on reset.

• When HST is set to “L” level, apply power according to this table to cause a power-on reset irrespective

of whether or not a power-on reset is required.

• For built-in resources in the device, re-apply power to the resources to cause a power-on reset.

• There are internal registers which can be initialized only by a power-on reset. Apply power according to

this rating to ensure initialization of the registers.

t^R

2.7 V

0.2 V

V^CC

0.2 V

t^OFF

Sudden changes in the power supply voltage may cause a power-on reset.

To change the power supply voltage while the device is in operation, it is recommended to raise the voltage

smoothly to suppress fluctuations as shown below.

Main power

supply voltage

V^CC

It is recommended to keep the rising

speed of the supply voltage at 50 mV/ms

or slower.

Sub power supply voltage

V^SS

RAM data retained

80

MB90670/675 Series

(3) Clock Timing

• Operation at 5.0 V ± 10%

(AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Min.

3

Typ. Max.

Clock frequency

Clock cycle time

FC

tC

X0, X1

—

32

MHz

ns

X0, X1

31.25

333

Recommended

ns duty ratio of

P^WH,

P^WL

Input clock pulse width

X0

10

—

30% to 70%

t^CR,

t^CF

Input clock rising/falling time

X0

—

1.5

62.5

—

5

16

666

3

ns

MHz

ns

—

Internal operating clock

frequency

f^CP

t^CP

∆f

—

Internal operating clock cycle

time

Frequency fluctuation rate

locked

P37/CLK

%

*

* : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied

PLL signal is locked.

+

+ α

| α |

f^O

∆f =

× 100 (%)

Center frequency f^O

– α

–

The PLL frequency deviation changes periodically from the preset frequency “(about CLK × (1CYC to 50 CYC)”,

thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with

long intervals).

81

MB90670/675 Series

• Operation at V^CC= 2.7 V (minimum value)

(AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Clock frequency

Min.

3

Typ. Max.

F^C

t^C

X0, X1

—

16

MHz

ns

Clock cycle time

62.5

333

Recommended

ns duty ratio of

30% to 70%

P^WH,

P^WL

Input clock pulse width

X0

20

—

t^CR,

t^CF

Input clock rising/falling time

X0

—

1.5

125

—

5

8

ns

MHz

ns

—

Internal operating clock

frequency

f^CP

t^CP

∆f

—

Internal operating clock cycle

time

666

3

Frequency fluctuation rate

locked

P37/CLK

%

*

* : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied

PLL signal is locked.

+

+ α

| α |

f^O

∆f =

× 100 (%)

Center frequency f^O

– α

–

The PLL frequency deviation changes periodically from the preset frequency “(about CLK × (1CYC to 50 CYC)”,

thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with

long intervals).

82

MB90670/675 Series

• Clock timing

t^C

0.8 V^CC

0.2 V^CC

0.8 V^CC

0.2 V^CC

P^WH

P^WL

t^CF

t^CR

• PLL operation guarantee range

Relationship between internal operating clock

frequency and power supply voltage

(V)

5.5

4.5

Normal operation

range

PLL operation

guarantee range

3.3

2.7

1.5

3

8

16

(MHz)

Internal clock f^CP

Relationship between clock frequency, internal

operating clock frequency, and power supply voltage

(MHz)

Multiplied-by-4

Multiplied-by-3

Not multiplied

Multiplied-by-1

Multiplied-

by-2

3 4

8

16

24

32 (MHz)

Oscillation clock F^C

Note: The operation guarantee range on the lower voltage is 2.7 V for the evaluation chips.

The AC ratings are measured for the following measurement reference voltages.

• Input signal waveform

• Output signal waveform

Hystheresis input pin

0.8 V^CC

Output pin

2.4 V

0.2 V^CC

0.8 V

Pins other than hystheresis input/MD input

0.7 V^CC

0.3 V^CC

83

MB90670/675 Series

(4) Recommended Resonator Manufacturers

• Sample application of piezoelectric resonator (FAR family)

X0

X1

R

FAR*¹

C¹*²

C²*²

*1: Fujitsu Acoustic Resonator

Temperature

characteristics of

FAR frequency

(T^A= –20°C to

+60°C)

Initial deviation

of FAR

frequency

(T^A= +25°C)

Frequency Dumping

Loading

FAR part number

(built-in capacitor type)

(MHz)

resistor

capacitors*²

2.00

4.00

510 Ω

—

±0.5%

Built-in

FAR-C4 C-2000- 20

FAR-C4 A-4000- 01

FAR-C4 B-4000- 02

FAR-C4 B-4000- 00

FAR-C4 B-8000- 02

FAR-C4 B-12000- 02

FAR-C4 B-16000- 02

FAR-C4 B-20000-L14B

FAR-C4 B-24000-L14A

4.00

—

4.00

—

8.00

—

12.00

16.00

20.00

24.00

—

Inquiry: FUJITSU LIMITED

84

MB90670/675 Series

• Sample application of ceramic resonator

X0

X1

R

*

C¹

C²

• Mask ROM product

Frequency

(MHz)

Resonator

KBR-2.0MS

C¹(pF)

C²(pF)

R

manufacturer

2.00

4.00

6.00

8.00

10.00

12.00

2.00

4.00

6.00

8.00

150

Not required

680 Ω

PBRC-2.00A

KBR-4.0MSA

KBR-4.0MKS

PBRC4.00A

PBRC4.00B

KBR-6.0MSA

KBR-6.0MKS

PBRC6.00A

PBRC6.00B

KBR-8.0M

33

Built-in

33

Built-in

33

680 Ω

Built-in

33

Built-in

33

680 Ω

Not required

560 Ω

Built-in

33

Built-in

33

Kyocera

Corporation

Built-in

33

Built-in

33

PBRC8.00A

PBRC8.00B

KBR-10.0M

33

Not required

330 Ω

Built-in

33

Built-in

33

PBRC10.00B

KBR-12.0M

Built-in

33

Built-in

33

680 Ω

330 Ω

PBRC-12.00B

CSA2.00MG040

CST2.00MG040

CSA4.00MG040

Built-in

100

Built-in

100

680 Ω

Not required

Built-in

100

Built-in

100

CST4.00MGW040

CSA6.00MG

Built-in

30

Built-in

30

Murata

Mfg. Co., Ltd.

CST6.00MGW

CSA8.00MTZ

CST8.00MTW

Built-in

30

Built-in

30

Built-in

(Continued)

85

MB90670/675 Series

(Continued)

Frequency

(MHz)

Resonator

C¹(pF)

C²(pF)

R

manufacturer

CSA10.0MTZ

CST10.0MTW

CSA12.0MTZ

CST12.0MTW

CSA16.00MXZ040

10.00

12.00

16.00

20.00

24.00

32.00

4.00

30

Built-in

30

Built-in

30

Not required

Built-in

15

Built-in

15

Murata

Mfg. Co., Ltd.

CST16.00MXW0C3

Built-in

10

Built-in

10

CSA20.00MXZ040

CSA24.00MXZ040

5

CST24.00MXW0H1

Built-in

5

Built-in

5

CSA32.00MXZ040

CST32.00MXW040

Built-in

TDK Corporation FCR4.0MC5

• One-time product

Frequency

(MHz)

Resonator

C¹(pF)

C²(pF)

R

manufacturer

CSTCS4.00MG0C5

CST8.00MTW

4.0

8.00

10.00

4.00

Built-in

30

Built-in

30

Not required

Murata

Mfg. Co., Ltd.

CSACS8.00MT

CSA10.0MTZ

CST10.0MTW

30

Built-in

TDK Corporation FCR4.0MC5

Inquiry:Kyocera Corporation

• AVX Corporation

North American Sales Headquarters: TEL 1-803-448-9411

• AVX Limited

European Sales Headquarters: TEL 44-1252-770000

• AVX/Kyocera H.K. Ltd.

Asian Sales Headquarters: TEL 852-363-3303

Murata Mfg. Co., Ltd.

• Murata Electronics North America, Inc.: TEL 1-404-436-1300

• Murata Europe Management GmbH: TEL 49-911-66870

• Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233

TDK Corporation

• TDK Corporation of America

Chicago Regional Office: TEL 1-708-803-6100

• TDK Electronics Europe GmbH

Components Division: TEL 49-2102-9450

• TDK Singapore (PTE) Ltd.: TEL 65-273-5022

• TDK Hongkong Co., Ltd.: TEL 852-736-2238

• Korea Branch, TDK Corporation: TEL 82-2-554-6633

86

MB90670/675 Series

(5) Clock Output Timing

(AV^CC= V^CC= 5.0 V ±10%, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol

Pin name

CLK

Condition

Unit Remarks

Parameter

Cycle time

CLK ↑ → CLK ↓

Min.

Max.

t^CYC

1 t^CP*

—

ns

—

t^CHCL

1 t^CP*/2 – 20 1 t^CP*/2 + 20 ns

* : For t^CP(internal operating clock cycle time), refer to “(3) Clock Timing”.

t^CYC

t^CHCL

2.4 V

CLK

0.8 V

87

MB90670/675 Series

(6) Bus Read Timing

(AV^CC= V^CC= 2.7 V to 5.5 V, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min.

Max.

—

t^LHLL

t^AVLL

ALE

V^CC= 5.0 V ±10% 1 t^CP*/2 – 20

V^CC= 3.0 V ±10% 1 t^CP*/2 – 35

ns

ALE pulse width

—

AD15 to AD00 V^CC= 5.0 V ±10% 1 t^CP*/2 – 25

AD15 to AD00 V^CC= 3.0 V ±10% 1 t^CP*/2 – 40

—

Effective address →

ALE ↓ time

—

ALE ↓ → address

effective time

t^LLAX

AD15 to AD00

1 t^CP*/2 – 15

1 t^CP* – 15

—

ns

—

Effective address → RD

↓ time

t^AVRL

t^AVDV

t^RLRH

t^RLDV

AD15 to AD00 V^CC= 5.0 V ±10%

AD15 to AD00 V^CC= 3.0 V ±10%

—

5 t^CP*/2 – 60 ns

5 t^CP*/2 – 80 ns

Effective address →

read data time

—

RD pulse width

RD

—

3 t^CP*/2 – 20

—

ns

AD15 to AD00 V^CC= 5.0 V ±10%

—

3 t^CP*/2 – 60 ns

3 t^CP*/2 – 80 ns

RD ↓ → read data time

AD15 to AD00 V^CC= 3.0 V ±10%

—

0

RD ↑ → data hold time t^RHDX

AD15 to AD00

RD, ALE

RD,

—

ns

RD ↑ → ALE ↑ time

t^RHLH

1 t^CP*/2 – 15

RD ↑ → address

disappear time

t^RHAX

1 t^CP*/2 – 10

—

ns

A19 to A16

—

Effective address →

CLK ↑ time

CLK,

A19 to A16

t^AVCH

t^RLCH

1 t^CP*/2 – 20

—

ns

RD ↓ → CLK ↑ time

RD, CLK

* : For t^CP(internal operating clock cycle time), refer to “(3) Clock Timing”.

88

MB90670/675 Series

t^AVCH

t^RLCH

2.4 V

CLK

t^RHLH

2.4 V

0.8 V

2.4 V

t^LHLL

t^AVLL

2.4 V

ALE

RD

t^LLAX

t^RLRH

2.4 V

0.8 V

t^RHAX

t^AVRL

t^RLDV

2.4 V

0.8 V

2.4 V

0.8 V

AD19 to AD16

AD15 to AD00

t^AVDV

t^RHDX

2.4 V

0.8 V

2.4 V

0.8 V

0.7 V^CC

0.3 V^CC

0.7 V^CC

0.3 V^CC

Address

Read data

89

MB90670/675 Series

(7) Bus Write Timing

(AV^CC= V^CC= 5.0 V ±10%, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min.

Max.

Effective address → WR

↓ time

t^AVWL

A19 to A00

1 t^CP– 15

—

ns

—

WR pulse width

t^WLWH

WR

3 t^CP*/2 – 20

—

ns

Write data → WR ↑ time t^DVWH

AD15 to AD00

3 t^CP*/2 – 20

t^WHDX

WR ↑ → data hold time

t^WHDX

AD15 to AD00 V^CC= 5.0 V ±10%

AD15 to AD00 V^CC= 3.0 V ±10%

20

30

WR ↑ → address

t^WHAX

A19 to A00

1 t^CP*/2 – 10

—

ns

disappear time

—

WR ↑ → ALE ↑ time

WR ↓ → CLK ↑ time

t^WHLH

t^WLCH

WRL, ALE

1 t^CP*/2 – 15

1 t^CP*/2 – 20

—

ns

WRH, CLK

* : For t^CP(internal operating clock cycle time), refer to “(3) Clock Timing”.

t^WLCH

2.4 V

CLK

t^WHLH

2.4 V

ALE

t^AVWL

t^WLWH

WRL, WRH

2.4 V

0.8 V

t^WHAX

2.4 V

0.8 V

2.4 V

0.8 V

A19 to A16

t^DVWH

t^WHDX

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

Address

Write data

AD15 to AD00

90

MB90670/675 Series

(8) Ready Input Timing

(AV^CC= V^CC= 2.7 V to 5.5 V, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min.

45

70

0

Max.

—

t^RYHS

t^RYHH

RDY

V^CC= 5.0 V ±10%

V^CC= 3.0 V ±10%

—

ns

RDY setup time

RDY hold time

RDY

—

Note: Use the auto-ready function when the setup time for the rising of the RDY signal is not sufficient.

2.4 V

CLK

ALE

RD/WR

t^RYHS

0.2 V^CC

t^RYHS

RDY

(WAIT inserted)

0.2 V^CC

RDY

(WAIT inserted)

0.8 V^CC

t^RYHH

(9) Hold Timing

Parameter

(AV^CC= V^CC= 2.7 V to 5.5 V, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Min.

30

Max.

1 t^CP*

2 t^CP*

Pins in floating status →

HAK ↓ time

t^XHAL

HAK

* : For t^CP(internal operating clock cycle time), refer to “(3) Clock Timing”.

ns

—

HAK ↑ → pin valid time t^HAHV

1 t^CP*

Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.

HAK

2.4 V

0.8 V

t^XHAL

2.4 V

0.8 V

t^HAHV

2.4 V

0.8 V

Pins

High impedance

91

MB90670/675 Series

(10) UART0 Timing

(AV^CC= V^CC= 5.0 V ±10%, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol Pin name

Condition

Unit

Remarks

Parameter

Min.

8 t^CP*

– 80

– 120

100

Max.

—

Serial clock cycle time

t^SCYC

t^SLOV

t^IVSH

—

ns

V^CC= 5.0 V ±10%

V^CC= 3.0 V ±10%

V^CC= 5.0 V ±10%

V^CC= 3.0 V ±10%

80

SCK ↓ → SOT delay

Internal shift

clock mode

C^L= 80 pF

+ 1 TTL for an

output pin

time

120

—

Valid SIN → SCK ↑

200

—

SCK ↑ → valid SIN hold

t^SHIX

t^SHSL

t^SLSH

—

1 t^CP*

4 t^CP*

—

ns

time

Serial clock “H” pulse

width

—

Serial clock “L” pulse

width

External shift

clock mode

C^L= 80 pF

+ 1 TTL for an

output pin

t^SLOV

t^IVSH

t^SHIX

—

V^CC= 5.0 V ±10%

V^CC= 3.0 V ±10%

V^CC= 5.0 V ±10%

V^CC= 3.0 V ±10%

V^CC= 5.0 V ±10%

V^CC= 3.0 V ±10%

—

150

200

—

ns

SCK ↓ → SOT delay

time

60

Valid SIN → SCK ↑

120

60

—

SCK ↑ → valid SIN hold

time

120

—

* : For t^CP(internal operating clock cycle time), refer to “(3) Clock Timing”.

Notes: • These are AC ratings in the CLK synchronous mode.

• C^Lis the load capacitor connected to pins while testing.

92

MB90670/675 Series

• Internal shift clock mode

t^SCYC

SCK

2.4 V

0.8 V

t^SLOV

0.8 V

2.4 V

0.8 V

SOT

SIN

t^IVSH

t^SHIX

2.4 V^CC

0.8 V^CC

2.4 V^CC

0.8 V^CC

• External shift clock mode

t^SLSH

t^SHSL

SCK

0.8 V^CC

0.2 V^CC

t^IVSH

2.4 V

0.2 V

SOT

SIN

t^IVSH

t^SHIX

0.8 V^CC

0.2 V^CC

0.8 V^CC

0.2 V^CC

93

MB90670/675 Series

(11) UART1 Timing

(AV^CC= V^CC= 5.0 V ±10%, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol Pin name

Condition

Unit

Remarks

Parameter

Min.

8 t^CP*

– 80

– 120

100

Max.

—

Serial clock cycle time

t^SCYC

t^SLOV

t^IVSH

—

ns

V^CC= 5.0 V ±10%

V^CC= 3.0 V ±10%

V^CC= 5.0 V ±10%

V^CC= 3.0 V ±10%

80

SCK ↓ → SOT delay

Internal shift

clock mode

C^L= 80 pF

+ 1 TTL for an

output pin

time

120

—

Valid SIN → SCK ↑

200

—

SCK ↑ → valid SIN hold

t^SHIX

t^SHSL

t^SLSH

—

1 t^CP*

4 t^CP*

—

ns

time

Serial clock “H” pulse

width

—

Serial clock “L” pulse

width

External shift

clock mode

C^L= 80 pF

+ 1 TTL for an

output pin

t^SLOV

t^IVSH

t^SHIX

—

V^CC= 5.0 V ±10%

V^CC= 3.0 V ±10%

V^CC= 5.0 V ±10%

V^CC= 3.0 V ±10%

V^CC= 5.0 V ±10%

V^CC= 3.0 V ±10%

—

150

200

—

ns

SCK ↓ → SOT delay

time

60

Valid SIN → SCK ↑

120

60

—

SCK ↑ → valid SIN hold

time

120

—

* : For t^CP(internal operating clock cycle time), refer to “(3) Clock Timing”.

Notes: • These are AC ratings in the CLK synchronous mode.

• C^Lis the load capacitor connected to pins while testing.

94

MB90670/675 Series

• Internal shift clock mode

t^SCYC

SCK

2.4 V

0.8 V

t^SLOV

0.8 V

2.4 V

0.2 V

SOT

t^IVSH

t^SHIX

0.8 V^CC

0.2 V^CC

0.8 V^CC

0.2 V^CC

SIN

• External shift clock mode

t^SLSH

t^SHSL

SCK

SOT

0.8 V^CC

0.2 V^CC

t^SLOV

2.4 V

0.8 V

t^IVSH

t^SHIX

0.8 V^CC

0.2 V^CC

0.8 V^CC

0.2 V^CC

SIN

95

MB90670/675 Series

(12) Timer Input Timing

(AV^CC= V^CC= 5.0 V ±10%, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min.

Max.

t^TIWH,

t^TIWL

Input pulse width

TIN0, TON1

—

4 t^CP*

—

ns

* : For t^CP(internal operating clock cycle time), refer to “(3) Clock Timing”.

0.8 V^CC

0.2 V^CC

TIN

t^TIWH

t^TIWL

(13) Timer Output Timing

(AV^CC= V^CC= 2.7 V to 5.5 V, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min.

30

Max.

—

t^TO

TOT0, TOT1

V^CC= 5.0 V ±10%

V^CC= 3.0 V ±10%

ns

CLK ↑ → T^OUT

transition time

80

—

2.4 V

CLK

T^OUT

2.4 V

0.8 V

t^TO

96

MB90670/675 Series

(14) I²C Timing

(AV^CC= V^CC= 5.0 V ±10%, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol Pin name

Condition

Unit

Remarks

Parameter

Min.

Max.

SCL clock frequency

f^SCL

—

0

100

kHz

Bus free time between

stop and start conditions

t^BUS

4.7

4.0

—

µs

The first clock

pulse is

Hold time

(re-transmission) start

t^HDSTA

—

µs generated

after this

period.

LOW status hold time of

SCL clock

t^LOW

—

4.7

4.0

—

µs

HIGH status hold time of

SCL clock

t^HIGH

—

Setup time for

conditions for starting

t^SUSTA

—

4.7

—

µs

re-transmission

Data hold time

Data setup time

t^HDDAT

t^SUDAT

—

0

—

µs

250

ns

Rising time of SDA and

SCL signals

t^R

—

1000

300

—

ns

µs

Falling time of SDA and

SCL signals

t^F

Setup time for stop

conditions

t^SUSTO

4.0

Note: Only MB90675 series has I²C.

0.8 V^CC

0.2 V^CC

SDA

t^BUS

t^LOW

t^R

t^F

t^HDSTA

0.8 V^CC

t^SUSTA

SCL

0.2 V^CC

t^HDSTA

t^SUDAT

t^SUSTO

t^HDDAT

t^HIGH

f^SCL

97

MB90670/675 Series

5. A/D Converter Electrical Characteristics

≤

(AV^CC= V^CC= 2.7 V to 5.5 V, AV^SS= V^SS= 0.0 V, 2.7 V AVRH – AVRL, T^A= –40°C to +85°C)

Value

Symbol Pin name

Condition

Unit

Parameter

Min.

—

Typ.

—

Max.

10

Resolution

—

bit

Total error

—

±3.0

±2.0

±1.5

AVRL

LSB

Linearity error

—

Differential linearity error

—

AN0 to

AN7

AVRL

Zero transition voltage

V^OT

V^FST

mV

– 1.5 LSB + 0.5 LSB + 2.5 LSB

AN0 to

AN7

AVRH

+ 0.5 LSB

AVRH

– 4.5 LSB – 1.5 LSB

Full-scale transition voltage

V^CC= 5.0 V ±10%

at machine clock of 6.125

16 MHz

—

µs

Conversion time

V^CC= 3.0 V ±10%

at machine clock of 12.25

8 MHz

—

AN0 to

AN7

Analog port input current

Analog input voltage

I^AIN

—

0.1

—

10

µA

V

AN0 to

AN7

V^AIN

AVRL

AVRH

AV^CC

—

AVRL

– 2.7

—

AVRH

—

V

Reference voltage

AVRH

– 2.7

AVRL

AV^CC

0

—

3

V

I^A

—

5

mA

Supply current

when CPU

stopped and A/D

converter not in

operation

(V^CC= AV^CC=

AVRH = 5.0 V)

Power supply current

I^AH

AV^CC

—

200

—

µA

I^R

AVRH

—

5

Supply current

when CPU

stopped and A/D

converter not in

operation

Reference voltage supply

current

I^RH

(V^CC= AV^CC=

AVRH = 5.0 V)

AN0 to

AN7

Offset between channels

—

4

LSB

98

MB90670/675 Series

6. A/D Converter Glossary

Resolution: Analog changes that are identifiable with the A/D converter

Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00

0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual

conversion characteristics

Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the

theoretical value

Total error: The total error is defined as a difference between the actual value and the theoretical value, which

includes zero-transition error/full-scale transition error and linearity error.

Total error

3FF

0.5 LSB’

3FE

3FD

Actual conversion

characteristics

{1 LSB × (N – 1) + 0.5 LSB}

004

003

002

001

V^NT

(Mesured value)

Actual conversion

characteristics

Theoretical

characteristics

0.5 LSB’

AVRL

AVRH

Analog input

AVRH – AVRL

1024

V^NT– {1 LSB’ × (N – 1) + 0.5 LSB’}

1 LSB’ = (Theoretical value)

[V]

Total error for digital output N

[LSB]

=

1 LSB’

V^NT: Voltage at a transition of digital output from (N – 1) to N

V^OT’ (Theoretical value) = AVRL + 0.5 LSB’ [V]

V^FST’ (Theoretical value) = AVRH – 1.5 LSB’ [V]

(Continued)

99

MB90670/675 Series

(Continued)

Linearity error

Differential linearity error

Theoretical

3FF

characteristics

Actual conversion

characteristics

3FE

Actual conversion

characteristics

N + 1

{1 LSB × (N – 1)

+ V^OT’}

3FD

V^FST

(Mesured value)

N

V^NT

004

003

002

001

V^{(N + 1)T}

(Mesured value)

Actual conversion

characteristics

N – 1

N – 2

V^NT(Mesured value)

Theoretical

characteristics

Actual conversion

characteristics

V^OT(Mesured value)

Analog input

AVRL

AVRH

AVRL

Analog input

AVRH

Linearity error of

digital output N

V^NT– {1 LSB × (N – 1) + V^OT}

Differential linearity error

of digital output N

V^{(N + 1)T}– V^NT

1 LSB’

[LSB]

– 1 LSB [LSB]

=

1 LSB’

AVRH – AVRL

1022

1 LSB

[V]

=

V^OT:Voltage at transition of digital output from “000^H” to “001^H”

V^FST: Voltage at transition of digital output from “3FE^H” to “3FF^H”

7. Notes on Using A/D Converter

Select the output impedance value for the external circuit of analog input according to the following conditions.

Output impedance values of the external circuit of 7 kΩ or lower are recommended.

When capacitors are connected to externalpins, the capacitance of severalthousand timesthe internalcapacitor

value is recommended to minimized the effect of voltage distribution between the external capacitor and internal

capacitor.

When the output impedance of the external circuit is too high, the sampling time for analog voltages may not

be sufficient (sampling time = 3.75 µs @machine clock of 16 MHz).

• Block diagram of analog input circuit model

Sample hold circuit

Analog input

C⁰

Comparator

R^ON1

R^ON2

R^ON3

R^ON4

C¹

R^ON1: Approx. 1.5 kΩ(V^CC= 5.0 V)

R^ON2: Approx. 0.5 kΩ (V^CC= 5.0 V)

R^ON3: Approx. 0.5 kΩ(V^CC= 5.0 V) C⁰: Approx. 60 pF

R^ON4: Approx. 0.5 kΩ (V^CC= 5.0 V) C¹: Approx. 4 pF

Note: Listed values must be considered as standards.

• Error

The smaller the | AVRH – AVRL |, the greater the error would become relatively.

100

MB90670/675 Series

■ EXAMPLE CHARACTERISTICS

(1) “H” Level Output Voltage

(2) “L” Level Output Voltage

V^OH(V)

1.0

V^OHvs. I^OH

V^OL(V)

1.0

V^OLvs. I^OL

V^CC= 2.7 V

T^A= +25°C

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V^CC= 2.7 V

V^CC= 3.0 V

V^CC= 3.5 V

V^CC= 4.0 V

V^CC= 4.5 V

V^CC= 5.0 V

V^CC= 3.5 V

V^CC= 4.0 V

V^CC= 4.5 V

V^CC= 5.0 V

–2

–4

–6

–8

I^OH(mA)

2

4

6

8

I^OL(mA)

(3) “H” Level Input Voltage/“L” Level Input Voltage (4) “H” Level Input Voltage/“L” Level Input Voltage

(CMOS Input)

(Hysteresis Input)

V^IN(V)

5.0

V^INvs. V^CC

T^A= +25°C

4.5

V^IN(V)

V^INvs. V^CC

4.0

5.0

V^IHS

V^ILS

3.5

T^A= +25°C

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.0

2.5

2.0

1.5

1.0

0.5

0.0

2

3

4

5

6

V^CC(V)

V^IHS: Threshold when input voltage in hysteresis

characteristics is set to “H” level

2

3

4

5

6

V^CC(V)

V^ILS: Threshold when input voltage in hysteresis

characteristics is set to “L” level

101

MB90670/675 Series

(5) Power Supply Current (f^CP= Internal Operating Clock Frequency)

I^CCvs. V^CC

I^CCSvs. V^CC

I^CC(mA)

70

65

60

55

50

45

40

35

30

25

20

15

10

5

I^CCS(mA)

15

14

13

12

11

10

9

8

7

6

5

f^CP= 16 MHz

T^A= +25°C

f^CP= 16 MHz

f^CP= 12.5 MHz

f^CP= 8 MHz

f^CP= 4 MHz

f^CP= 8 MHz

f^CP= 4 MHz

4

3

2

1

0

3.0

4.0

5.0

6.0

V^CC(V)

3.0

4.0

5.0

6.0

V^CC(V)

I^Avs. AV^CC

I^Rvs. AVR

I^A(mA)

6.0

I^A(mA)

0.30

T^A= +25°C

f^CP= 16 MHz

T^A= +25°C

f^CP= 16 MHz

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

0.20

0.10

0

3.0

4.0

5.0

6.0

AV^CC(V)

3.0

4.0

5.0

6.0

AVR (V)

(6) Pull-up Resistance

R vs. V^CC

R (kΩ)

1000

T^A= +25°C

100

10

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

V^CC(V)

102

MB90670/675 Series

■ INSTRUCTIONS (340 INSTRUCTIONS)

Table 1 Explanation of Items in Tables of Instructions

Meaning

Upper-case letters and symbols: Represented as they appear in assembler.

Item

Mnemonic

Lower-case letters: Replaced when described in assembler.

Numbers after lower-case letters:Indicate the bit width within the instruction.

#

~

Indicates the number of bytes.

Indicates the number of cycles.

m: When branching

n : When not branching

See Table 4 for details about meanings of other letters in items.

RG

B

Indicates the number of accesses to the register during execution of the instruction.

It is used calculate a correction value for intermittent operation of CPU.

Indicates the correction value for calculating the number of actual cycles during execution of the

instruction. (Table 5)

The number of actual cycles during execution of the instruction is the correction value summed

with the value in the “~” column.

Operation

LH

Indicates the operation of instruction.

Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.

Z : Transfers “0”.

X : Extends with a sign before transferring.

– : Transfers nothing.

AH

Indicates special operations involving the upper 16 bits in the accumulator.

* : Transfers from AL to AH.

– : No transfer.

Z : Transfers 00^Hto AH.

X : Transfers 00^Hor FF^Hto AH by signing and extending AL.

I

S

Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),

N (negative), Z (zero), V (overflow), and C (carry).

* : Changes due to execution of instruction.

– : No change.

S : Set by execution of instruction.

R : Reset by execution of instruction.

T

N

Z

V

C

RMW

Indicates whether the instruction is a read-modify-write instruction. (a single instruction that

reads data from memory, etc., processes the data, and then writes the result to memory.)

* : Instruction is a read-modify-write instruction.

– : Instruction is not a read-modify-write instruction.

Note: A read-modify-write instruction cannot be used on addresses that have different

meanings depending on whether they are read or written.

103

MB90670/675 Series

Table 2 Explanation of Symbols in Tables of Instructions

Meaning

Symbol

A

32-bit accumulator

The bit length varies according to the instruction.

Byte : Lower 8 bits of AL

Word : 16 bits of AL

Long : 32 bits of AL:AH

AH

AL

Upper 16 bits of A

Lower 16 bits of A

SP

PC

Stack pointer (USP or SSP)

Program counter

PCB

DTB

ADB

SSB

USB

SPB

DPR

brg1

brg2

Ri

Program bank register

Data bank register

Additional data bank register

System stack bank register

User stack bank register

Current stack bank register (SSB or USB)

Direct page register

DTB, ADB, SSB, USB, DPR, PCB, SPB

DTB, ADB, SSB, USB, DPR, SPB

R0, R1, R2, R3, R4, R5, R6, R7

RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

RW0, RW1, RW2, RW3

RWi

RWj

RLi

RL0, RL1, RL2, RL3

dir

Compact direct addressing

addr16

addr24

ad24 0 to 15

ad24 16 to 23

Direct addressing

Physical direct addressing

Bit 0 to bit 15 of addr24

Bit 16 to bit 23 of addr24

io

I/O area (000000^Hto 0000FF^H)

imm4

imm8

4-bit immediate data

8-bit immediate data

imm16

imm32

ext (imm8)

16-bit immediate data

32-bit immediate data

16-bit data signed and extended from 8-bit immediate data

disp8

disp16

8-bit displacement

16-bit displacement

bp

Bit offset

vct4

vct8

Vector number (0 to 15)

Vector number (0 to 255)

( )b

Bit address

(Continued)

104

MB90670/675 Series

(Continued)

Symbol

Meaning

rel

Branch specification relative to PC

ear

eam

Effective addressing (codes 00 to 07)

Effective addressing (codes 08 to 1F)

rlst

Register list

Table 3 Effective Address Fields

Address format

Number of bytes in address

extension *

Code

Notation

00

01

02

03

04

05

06

07

R0

RW0

RW1

RW2

RW3

RW4

RW5

RW6

RW7

RL0 Register direct

(RL0)

RL1 “ea” corresponds to byte, word, and

(RL1) long-word types, starting from the

RL2 left

(RL2)

RL3

R1

R2

R3

R4

R5

R6

R7

—

(RL3)

08

09

0A

0B

@RW0

Register indirect

@RW1

@RW2

@RW3

0

0C

0D

0E

0F

@RW0 +

@RW1 +

@RW2 +

@RW3 +

Register indirect with post-increment

10

11

12

13

14

15

16

17

@RW0 + disp8

@RW1 + disp8

@RW2 + disp8

@RW3 + disp8

@RW4 + disp8

@RW5 + disp8

@RW6 + disp8

@RW7 + disp8

Register indirect with 8-bit

displacement

1

2

18

19

1A

1B

@RW0 + disp16

@RW1 + disp16

@RW2 + disp16

@RW3 + disp16

Register indirect with 16-bit

displacement

1C

1D

1E

1F

@RW0 + RW7

@RW1 + RW7

@PC + disp16

addr16

Register indirect with index

PC indirect with 16-bit displacement

Direct address

0

2

Note: The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)

column in the tables of instructions.

105

MB90670/675 Series

Table 4 Number of Execution Cycles for Each Type of Addressing

(a)

Number of register

accesses for each type of

addressing

Code

Operand

Number of execution cycles

for each type of addressing

Ri

RWi

00 to 07

Listed in tables of instructions Listed in tables of instructions

RLi

08 to 0B

0C to 0F

10 to 17

18 to 1B

@RWj

2

4

2

1

2

1

@RWj +

@RWi + disp8

@RWj + disp16

1C

1D

1E

1F

@RW0 + RW7

@RW1 + RW7

@PC + disp16

addr16

4

2

1

2

0

Note: “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.

Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles

(b) byte

(c) word

(d) long

Number

Operand

Number

of cycles

Number

of cycles

Number

of cycles

of

access

Internal register

+0

1

+0

1

+0

2

Internal memory even address

Internal memory odd address

+0

1

+0

+2

1

2

+0

+4

2

4

Even address on external data bus (16 bits)

Odd address on external data bus (16 bits)

+1

1

+1

+4

1

2

+2

+8

2

4

External data bus (8 bits)

+1

1

+4

2

+8

4

Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)

in the tables of instructions.

• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready

input and automatic ready.

Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles

Instruction

Internal memory

Byte boundary

Word boundary

—

+3

+2

+3

—

External data bus (16 bits)

External data bus (8 bits)

Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready

input and automatic ready.

• Because instruction execution is not slowed down by all program fetches in actuality, these correction

values should be used for “worst case” calculations.

106

MB90670/675 Series

Table 7 Transfer Instructions (Byte) [41 Instructions]

R

G

L

H

A

H

RM

W

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C

MOV

A, dir

A, addr16

A, Ri

A, ear

A, eam

A, io

A, #imm8

A, @A

A, @RLi+disp8

2

3

1

2

3

4

2

0

1

(b) byte (A) ← (dir)

(b) byte (A) ← (addr16)

Z

*

–

*

–

*

–

0

byte (A) ← (Ri)

byte (A) ← (ear)

2+ 3+ (a) 0

(b) byte (A) ← (eam)

(b) byte (A) ← (io)

2

3

1

3

2

3

10

0

2

0

byte (A) ← imm8

(b) byte (A) ← ((A))

(b) byte (A) ←

MOVN A, #imm4

1

0

((RLi)+disp8)

byte (A) ← imm4

R

MOVX A, dir

MOVX A, addr16

MOVX A, Ri

MOVX A, ear

MOVX A, eam

MOVX A, io

MOVX A, #imm8

MOVX A, @A

MOVX A,@RWi+disp8

MOVX A, @RLi+disp8

2

3

2

3

4

2

0

1

(b)

X

*

–

*

–

*

–

(b) byte (A) ← (dir)

0

(b) byte (A) ← (ear)

(b) byte (A) ← (eam)

byte (A) ← (addr16)

byte (A) ← (Ri)

2+ 3+ (a) 0

2

3

2

3

5

10

0

1

2

0

byte (A) ← (io)

(b) byte (A) ← imm8

(b) byte (A) ← ((A))

(b) byte (A) ←

((RWi)+disp8)

MOV

dir, A

addr16, A

Ri, A

ear, A

eam, A

io, A

@RLi+disp8, A

Ri, ear

Ri, eam

ear, Ri

eam, Ri

Ri, #imm8

io, #imm8

dir, #imm8

ear, #imm8

eam, #imm8

@AL, AH

2

3

1

2

3

4

2

0

1

(b) byte (A) ←

(b) ((RLi)+disp8)

0

–

*

–

*

–

*

–

*

–

*

–

0

byte (dir) ← (A)

2+ 3+ (a) 0

(b) byte (addr16) ← (A)

(b) byte (Ri) ← (A)

(b) byte (ear) ← (A)

2

3

2

3

10

3

0

2

0

byte (eam) ← (A)

2+ 4+ (a) 1

2

2+ 5+ (a) 1

2

3

(b) byte (io) ← (A)

4

2

0

byte ((RLi) +disp8) ←

(b) (A)

2

5

2

1

0

1

0

byte (Ri) ← (ear)

(b) byte (Ri) ← (eam)

(b) byte (ear) ← (Ri)

0

byte (eam) ← (Ri)

3+ 4+ (a) 0

2

(b) byte (Ri) ← imm8

(b) byte (io) ← imm8

byte (dir) ← imm8

3

0

/MOV @A, T

byte (ear) ← imm8

byte (eam) ← imm8

2+ 5+ (a) 0 2× (b) byte ((A)) ← (AH)

XCH

A, ear

2

4

2

0

Z

–

A, eam

Ri, ear

Ri, eam

2

7

4

0

2+ 9+ (a) 2 2× (b)

byte (A) ↔ (ear)

byte (A) ↔ (eam)

byte (Ri) ↔ (ear)

byte (Ri) ↔ (eam)

Note: Foran explanation of “(a)” to “(d)”, referto Table 4, “Number of Execution CyclesforEach Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

107

MB90670/675 Series

Table 8 Transfer Instructions (Word/Long Word) [38 Instructions]

R

G

L

A

H

RM

W

Mnemonic

MOVW A, dir

MOVW A, addr16

MOVW A, SP

MOVW A, RWi

MOVW A, ear

MOVW A, eam

MOVW A, io

MOVW A, @A

#

~

B

Operation

I

S

T

N

Z

V

C

H

2

3

1

2

3

4

1

2

0

1

(c) word (A) ← (dir)

(c) word (A) ← (addr16)

0

(c) word (A) ← (eam)

(c) word (A) ← (io)

(c) word (A) ← ((A))

–

*

–

*

–

*

–

word (A) ← (SP)

word (A) ← (RWi)

word (A) ← (ear)

2+ 3+ (a) 0

2

3

2

3

2

5

10

0

1

2

MOVW A, #imm16

MOVW A, @RWi+disp8

MOVW A, @RLi+disp8

0

word (A) ← imm16

(c) word (A) ← ((RWi)

(c) +disp8)

word (A) ← ((RLi)

(c) +disp8)

(c)

0

(c) word (RWi) ← (A)

(c) word (ear) ← (A)

(c) word (eam) ← (A)

(c) word (io) ← (A)

(0) word ((RWi) +disp8) ←

(c) (A)

MOVW dir, A

MOVW addr16, A

MOVW SP, A

MOVW RWi, A

MOVW ear, A

MOVW eam, A

MOVW io, A

MOVW @RWi+disp8, A

MOVW @RLi+disp8, A

MOVW RWi, ear

MOVW RWi, eam

MOVW ear, RWi

MOVW eam, RWi

MOVW RWi, #imm16

MOVW io, #imm16

MOVW ear, #imm16

MOVW eam, #imm16

2

3

1

2

3

4

1

2

0

1

–

*

–

*

–

*

–

*

–

word (dir) ← (A)

word (addr16) ← (A)

word (SP) ← (A)

2+ 3+ (a) 0

2

3

2

3

5

10

3

0

1

2

2+ 4+ (a) 1

2

4

2

0

word ((RLi) +disp8) ←

2+ 5+ (a) 1

(c) (A)

0

(c) word (RWi) ← (eam)

0

(c) word (eam) ← (RWi)

word (RWi) ← imm16

(c) word (io) ← imm16

word (ear) ← imm16

word (eam) ← imm16

0

3

4

2

5

2

1

0

1

word (RWi) ← (ear)

word (ear) ← (RWi)

4+ 4+ (a) 0

MOVW AL, AH

/MOVW @A, T

2

3

4

0

2

–

*

–

XCHW A, ear

–

XCHW A, eam

XCHW RWi, ear

XCHW RWi, eam

2+ 5+ (a) 0 2× (c) word ((A)) ← (AH)

2

7

4

0

2+ 9+ (a) 2 2× (c)

word (A) ↔ (ear)

word (A) ↔ (eam)

word (RWi) ↔ (ear)

word (RWi) ↔ (eam)

MOVL A, ear

MOVL A, eam

MOVL A, #imm32

2

4

2

0

long (A) ← (ear)

–

*

–

2+ 5+ (a) 0

5

(d) long (A) ← (eam)

0

3

0

long (A) ← imm32

MOVL ear, A

MOVL eam, A

2

4

2

0

long (ear) ← (A)

–

*

–

2+ 5+ (a) 0

(d) long (eam) ← (A)

Note: Foran explanation of “(a)” to “(d)”, referto Table 4, “Number of Execution CyclesforEach Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

108

MB90670/675 Series

Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]

R

G

L

A

H

RM

W

Mnemonic

ADD

#

~

B

Operation

I

S

T

N

Z

V

C

H

2

5

3

0

1

0

byte (A) ← (A) +imm8

Z

–

Z

–

Z

–

*

–

*

–

*

A,#imm8

ADD

ADDC

(b) byte (A) ← (A) +(dir)

byte (A) ← (A) +(ear)

(b) byte (A) ← (A) +(eam)

byte (ear) ← (ear) + (A)

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) + (A)

A, dir

A, ear

A, eam

ear, A

eam, A

A

0

2+ 4+ (a) 0

2

3

2

0

1

2

3

0

1

0

byte (A) ← (AH) + (AL) + (C)

byte (A) ← (A) + (ear) + (C)

ADDC A, ear

ADDC A, eam

ADDDC A

2+ 4+ (a) 0

(b) byte (A) ← (A) + (eam) + (C)

0

1

2

3

2

5

3

0

1

byte (A) ← (AH) + (AL) + (C)

(decimal)

SUB

A,

(b) byte (A) ← (A) –imm8

byte (A) ← (A) – (dir)

(b) byte (A) ← (A) – (ear)

byte (A) ← (A) – (eam)

2+ 5+ (a) 0 2× (b) byte (ear) ← (ear) – (A)

#imm8

SUB

SUBC

0

A, dir

A, ear

A, eam

ear, A

eam, A

A

2+ 4+ (a) 0

2

3

2

0

1

2

3

0

1

0

byte (eam) ← (eam) – (A)

byte (A) ← (AH) – (AL) – (C)

–

2+ 4+ (a) 0

(b) byte (A) ← (A) – (ear) – (C)

0

SUBC A, ear

SUBC A, eam

SUBDC A

1

3

0

byte (A) ← (A) – (eam) – (C)

byte (A) ← (AH) – (AL) – (C)

(decimal)

ADDW A

ADDW A, ear

ADDW A, eam

ADDW

#imm16

ADDW ear, A

ADDW eam, A

ADDCWA, ear

ADDCWA, eam

SUBW A

SUBW A, ear

SUBW A, eam

SUBW

#imm16

SUBW ear, A

SUBW eam, A

SUBCW A, ear

SUBCW A, eam

1

2

3

0

1

0

word (A) ← (AH) + (AL)

word (A) ← (A) +(ear)

–

*

–

*

–

*

2+ 4+ (a) 0

3

2

(c) word (A) ← (A) +(eam)

0

A,

2

3

0

2

word (A) ← (A) +imm16

word (ear) ← (ear) + (A)

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) + (A)

word (A) ← (A) + (ear) + (C)

(c) word (A) ← (A) + (eam) + (C)

2

3

1

0

2+ 4+ (a) 0

1

2

3

0

1

0

word (A) ← (AH) – (AL)

word (A) ← (A) – (ear)

2+ 4+ (a) 0

3

2

(c) word (A) ← (A) – (eam)

0

2

3

0

2

word (A) ← (A) –imm16

word (ear) ← (ear) – (A)

A,

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) – (A)

word (A) ← (A) – (ear) – (C)

(c) word (A) ← (A) – (eam) – (C)

2

3

1

0

–

2+ 4+ (a) 0

ADDL A, ear

ADDL A, eam

2

6

2

0

long (A) ← (A) + (ear)

–

*

–

2+ 7+ (a) 0

5

2

2+ 7+ (a) 0

5

(d) long (A) ← (A) + (eam)

0

ADDL

A,

4

6

0

2

long (A) ← (A) +imm32

long (A) ← (A) – (ear)

#imm32

SUBL A, ear

SUBL A, eam

(d) long (A) ← (A) – (eam)

long (A) ← (A) –imm32

4

0

SUBL

A,

#imm32

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

109

MB90670/675 Series

Table 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]

R

G

L

H

A

H

RM

W

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C

INC

ear

eam

2

0

byte (ear) ← (ear) +1

–

*

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) +1

DEC

ear

eam

2

3

2

0

byte (ear) ← (ear) –1

–

*

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) –1

INCW ear

INCW eam

2

3

2

0

word (ear) ← (ear) +1

–

*

–

*

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) +1

DECW ear

DECW eam

2

3

2

0

word (ear) ← (ear) –1

–

*

–

*

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) –1

INCL ear

INCL eam

2

7

4

0

long (ear) ← (ear) +1

–

*

–

*

2+ 9+ (a) 0 2× (d) long (eam) ← (eam) +1

DECL ear

DECL eam

2

7

4

0

long (ear) ← (ear) –1

–

*

–

*

2+ 9+ (a) 0 2× (d) long (eam) ← (eam) –1

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 11 Compare Instructions (Byte/Word/Long Word) [11 Instructions]

R

G

L

H

A

H

RM

W

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C

CMP

A

1

2

1

2

0

1

0

byte (AH) – (AL)

byte (A) ← (ear)

–

*

–

CMP

A, ear

A, eam

A, #imm8

2+ 3+ (a) 0

2

(b) byte (A) ← (eam)

0

2

0

byte (A) ← imm8

CMPW A

1

2

1

2

0

1

0

word (AH) – (AL)

word (A) ← (ear)

–

*

–

CMPW A, ear

CMPW A, eam

CMPW A, #imm16

2+ 3+ (a) 0

3

(c) word (A) ← (eam)

0

2

0

word (A) ← imm16

CMPL A, ear

CMPL A, eam

CMPL A, #imm32

2

6

2

0

word (A) ← (ear)

–

*

–

2+ 7+ (a) 0

5

(d) word (A) ← (eam)

word (A) ← imm32

3

0

Note: Foran explanation of “(a)” to “(d)”, referto Table 4, “Number of Execution CyclesforEach Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

110

MB90670/675 Series

Table 12 Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]

R

G

L

A

H

RM

W

Mnemonic

#

1

~

B

Operation

I

S

–

T

–

N

–

Z

–

V

*

C

*

H

1

DIVU

A

0

1

0

1

0

0 word (AH) /byte (AL)

Quotient → byte (AL) Remainder →

0 byte (AH)

–

*

2

DIVU

ear

A,

2

*

word (A)/byte (ear)

Quotient → byte (A) Remainder →

byte (ear)

word (A)/byte (eam)

Quotient → byte (A) Remainder →

byte (eam)

6

3

2+

2

*

DIVU

eam

A,

4

*

0

*

7

5

*

DIVUW A,

ear

2+

*

long (A)/word (ear)

Quotient → word (A) Remainder →

word (ear)

long (A)/word (eam)

Quotient → word (A) Remainder →

word (eam)

8

0

(b)

DIVUW A,

eam

1

2

2+

*

0

1

0

–

9

*

10

*

11

12

13

0

MULU

A

1

2

2+

0

1

0

–

*

0 byte (AH) *byte (AL) → word (A)

(c) byte (A) *byte (ear) → word (A)

byte (A) *byte (eam) → word (A)

MULU A,

ear

MULU A,

eam

word (AH) *word (AL) → long (A)

word (A) *word (ear) → long (A)

word (A) *word (eam) → long (A)

MULUW A

MULUW A,

ear

MULUW A,

eam

*1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally.

*2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally.

*3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.

*4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally.

*5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.

*6: (b) when the result is zero or when an overflow occurs, and 2 × (b) normally.

*7: (c) when the result is zero or when an overflow occurs, and 2 × (c) normally.

*8: 3 when byte (AH) is zero, and 7 when byte (AH) is not zero.

*9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero.

*10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.

*11: 3 when word (AH) is zero, and 11 when word (AH) is not zero.

*12: 4 when word (ear) is zero, and 12 when word (ear) is not zero.

*13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

111

MB90670/675 Series

Table 13 Logical 1 Instructions (Byte/Word) [39 Instructions]

R

G

L

A

H

RM

W

Mnemonic

AND A, #imm8

#

~

B

Operation

I

S

T

N

Z

V

C

H

2

3

0

1

0

byte (A) ← (A) and imm8

byte (A) ← (A) and (ear)

–

*

R

–

*

AND

A, ear

A, eam

ear, A

2+ 4+ (a) 0

(b) byte (A) ← (A) and (eam)

0

2

3

2

byte (ear) ← (ear) and (A)

eam, A

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) and (A) –

OR

A, #imm8

A, ear

A, eam

ear, A

eam, A

2

3

0

1

0

byte (A) ← (A) or imm8

byte (A) ← (A) or (ear)

–

*

R

–

*

2+ 4+ (a) 0

(b) byte (A) ← (A) or (eam)

byte (ear) ← (ear) or (A)

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) or (A)

2

3

2

0

XOR A, #imm8

XOR A, ear

XOR A, eam

XOR ear, A

XOR eam, A

2

3

0

1

0

byte (A) ← (A) xor imm8

byte (A) ← (A) xor (ear)

–

*

R

–

*

2+ 4+ (a) 0

2

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) xor (A) –

(b) byte (A) ← (A) xor (eam)

byte (ear) ← (ear) xor (A)

3

2

0

NOT

A

ear

eam

1

2

3

0

2

0

byte (A) ← not (A)

byte (ear) ← not (ear)

–

*

R

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← not (eam)

ANDW A

1

3

2

3

0

1

0

word (A) ← (AH) and (A)

word (A) ← (A) and imm16

word (A) ← (A) and (ear)

–

*

R

–

*

ANDW A, #imm16

ANDW A, ear

ANDW A, eam

ANDW ear, A

ANDW eam, A

2+ 4+ (a) 0

2

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) and (A) –

(c) word (A) ← (A) and (eam)

0

3

2

word (ear) ← (ear) and (A)

ORW

A

1

3

2

3

0

1

0

word (A) ← (AH) or (A)

word (A) ← (A) or imm16

word (A) ← (A) or (ear)

–

*

R

–

*

ORW A, #imm16

ORW A, ear

ORW A, eam

ORW ear, A

2+ 4+ (a) 0

2

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) or (A) –

(c) word (A) ← (A) or (eam)

word (ear) ← (ear) or (A)

3

2

0

ORW eam, A

XORW A

1

3

2

3

0

1

0

word (A) ← (AH) xor (A)

word (A) ← (A) xor imm16

word (A) ← (A) xor (ear)

–

*

R

–

*

XORW A, #imm16

XORW A, ear

XORW A, eam

XORW ear, A

XORW eam, A

2+ 4+ (a) 0

(c) word (A) ← (A) xor (eam)

word (ear) ← (ear) xor (A)

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) xor (A)

2

3

2

0

NOTW A

NOTW ear

NOTW eam

1

2

3

0

2

0

word (A) ← not (A)

word (ear) ← not (ear)

–

*

R

–

*

2+ 5+ (a) 0 2× (c) word (eam) ← not (eam)

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

112

MB90670/675 Series

Table 14 Logical 2 Instructions (Long Word) [6 Instructions]

R

G

L

H

A

H

RM

W

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C

ANDL A, ear

ANDL A, eam

2

6

2

0

long (A) ← (A) and (ear)

–

*

R

–

2+ 7+ (a) 0

(d) long (A) ← (A) and (eam)

ORL

A, ear

A, eam

2

6

2

0

long (A) ← (A) or (ear)

–

*

R

–

2+ 7+ (a) 0

(d) long (A) ← (A) or (eam)

XORL A, ea

XORL A, eam

2

6

2

0

long (A) ← (A) xor (ear)

–

*

R

–

2+ 7+ (a) 0

(d) long (A) ← (A) xor (eam)

Table 15 Sign Inversion Instructions (Byte/Word) [6 Instructions]

R

G

L

A

H

RM

W

Mnemonic

#

1

2

~

2

3

B

0

Operation

byte (A) ← 0 – (A)

byte (ear) ← 0 – (ear)

I

S

T

N

Z

V

C

H

NEG

A

0

X

–

*

–

NEG ear

NEG eam

2

–

*

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← 0 – (eam)

NEGW A

1

2

0

word (A) ← 0 – (A)

–

*

–

NEGW ear

NEGW eam

2

3

2

0

word (ear) ← 0 – (ear)

–

*

–

*

2+ 5+ (a) 0 2× (c) word (eam) ← 0 – (eam)

Table 16 Normalize Instruction (Long Word) [1 Instruction]

L

H

A

H

RM

W

Mnemonic

#

~

RG

B

Operation

I

S

T

N

Z

V

C

1

NRML A, R0

2

1

0

long (A) ← Shift until first

digit is “1”

–

*

–

*

byte (R0) ← Current shift

count

*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

113

MB90670/675 Series

Table 17 Shift Instructions (Byte/Word/Long Word) [18 Instructions]

R

G

L

A

RM

W

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V C

H H

RORCA

ROLC A

2

0

byte (A) ← Right rotation with carry

byte (A) ← Left rotation with carry

–

*

–

*

–

RORCear

RORCeam

ROLC ear

ROLC eam

2

3

2

0

byte (ear) ← Right rotation with carry –

–

*

–

*

–

*

–

2+ 5+ 0 2× (b) byte (eam) ← Right rotation with

2

2+

–

(a)

3

5+

(a)

2

0

carry

0 2× (b) byte (ear) ← Left rotation with carry

byte (eam) ← Left rotation with carry

*

ASR A, R0

LSR A, R0

LSL A, R0

2

1

0

–

*

–

*

–

*

–

byte (A) ← Arithmetic right barrel shift (A,

R0)

byte (A) ← Logical right barrel shift

1

*

1

*

1

(A, R0)

*

byte (A) ← Logical left barrel shift (A,

R0)

ASRWA

LSRWA/SHRW 1

A

LSLW A/SHLW

A

1

2

0

word (A) ← Arithmetic right shift (A, 1

bit)

word (A) ← Logical right shift (A, 1

bit)

word (A) ← Logical left shift (A, 1 bit)

–

*

–

*

R

*

–

*

–

1

2

1

0

–

*

–

*

–

*

–

*

1

*

1

ASRWA, R0

LSRWA, R0

LSLW A, R0

word (A) ← Arithmetic right barrel shift (A,

R0)

word (A) ← Logical right barrel shift

*

(A, R0)

word (A) ← Logical left barrel shift (A,

R0)

2

ASRL A, R0

LSRL A, R0

LSLL A, R0

2

1

0

long (A) ← Arithmetic right shift (A,

R0)

long (A) ← Logical right barrel shift

(A, R0)

–

*

–

*

–

*

–

*

2

*

2

*

long (A) ← Logical left barrel shift (A,

R0)

*1: 6 when R0 is 0, 5 + (R0) in all other cases.

*2: 6 when R0 is 0, 6 + (R0) in all other cases.

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

114

MB90670/675 Series

Table 18 Branch 1 Instructions [31 Instructions]

L

H

A

H

RM

W

Mnemonic

#

~

RG

B

Operation

I

S

T

N

Z

V

C

1

BZ/BEQ

BNZ/BNE rel

BC/BLO

BNC/BHS rel

rel

2

0

Branch when (Z) = 1

Branch when (Z) = 0

Branch when (C) = 1

Branch when (C) = 0

Branch when (N) = 1

Branch when (N) = 0

Branch when (V) = 1

Branch when (V) = 0

Branch when (T) = 1

Branch when (T) = 0

Branch when (V) xor (N) = 1

Branch when (V) xor (N) = 0

Branch when ((V) xor (N)) or

(Z) = 1

–

*

1

*

1

rel

*

1

BN

BP

BV

BNV

BT

BNT

BLT

BGE

BLE

BGT

BLS

BHI

BRA

rel

1

*

1

*

1

*

1

*

1

Branch when ((V) xor (N)) or

(Z) = 0

Branch when (C) or (Z) = 1

Branch when (C) or (Z) = 0

Branch unconditionally

1

*

2

3

JMP

@A

1

3

2

2+

2

2+

4

0

1

0

2

0

–

addr16

@ear

@eam

3

4+ (a)

5

6+ (a)

4

word (PC) ← (A)

(c) word (PC) ← addr16

word (PC) ← (ear)

(d) word (PC) ← (eam)

JMPP @ear *³

JMPP @eam *³

JMPP addr24

0

word (PC) ← (ear), (PCB) ←

(ear +2)

CALL @ear *⁴

CALL @eam *⁴

CALL addr16 *⁵

CALLV #vct4 *⁵

CALLP @ear *⁶

6

7+ (a)

6

7

10

2

2+

3

1

2

1

0

2

(c) word (PC) ← (eam), (PCB) ←

2× (c) (eam +2)

(c) word (PC) ← ad24 0 to 15,

2× (c) (PCB) ← ad24 16 to 23

2× (c) word (PC) ← (ear)

–

word (PC) ← (eam)

word (PC) ← addr16

2

CALLP @eam *⁶

CALLP addr24 *⁷

11+ (a)

10

2+

4

0

–

*

Vector call instruction

word (PC) ← (ear) 0 to 15

(PCB) ← (ear) 16 to 23

word (PC) ← (eam) 0 to 15

(PCB) ← (eam) 16 to 23

word (PC) ← addr0 to 15,

(PCB) ← addr16 to 23

2× (c)

*1: 4 when branching, 3 when not branching.

*2: (b) + 3 × (c)

*3: Read (word) branch address.

*4: W: Save (word) to stack; R: read (word) branch address.

*5: Save (word) to stack.

*6: W: Save (long word) to W stack; R: read (long word) R branch address.

*7: Save (long word) to stack.

Note: Foran explanation of “(a)” to “(d)”, referto Table 4, “Number of Execution CyclesforEach Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

115

MB90670/675 Series

Table 19 Branch 2 Instructions [19 Instructions]

L

H

A

H

RM

W

Mnemonic

#

~ RG

B

Operation

I

S

T

N

Z

V

C

1

CBNE A, #imm8, rel

CWBNEA, #imm16, rel

3

4

0

Branch when byte (A) ≠

imm8

Branch when word (A) ≠

–

*

–

*

1

2

3

4

3

CBNE ear, #imm8, rel

CBNE eam, #imm8,

rel*⁹

CWBNEear, #imm16,

rel

4

4+

5

*

1

0

1

0

(b)

0

imm16

–

*

–

Branch when byte (ear) ≠

5+

(c) imm8

Branch when byte (eam) ≠

imm8

Branch when word (ear) ≠

2 2× (b) imm16

Branch when word (eam) ≠

5

3

2

0

–

*

–

*

CWBNEeam, #imm16,

*

rel*⁹

6

3+

DBNZ ear, rel

imm16

5

3

*

2

0

–

*

–

*

DBNZ eam, rel

Branch when byte (ear) =

6

3+

2× (c) (ear) – 1, and (ear) ≠ 0

Branch when byte (eam) =

(eam) – 1, and (eam) ≠ 0

8× (c)

6× (c)

8× (c)

6× (c)

DWBNZ ear, rel

DWBNZ eam, rel

2

3

4

1

0

–

R

*

S

*

–

*

–

*

–

*

–

*

–

*

–

20

16

17

20

15

Branch when word (ear) =

(ear) – 1, and (ear) ≠ 0

Branch when word (eam) =

INT

#vct8

addr16

(eam) – 1, and (eam) ≠ 0

INTP

INT9

RETI

addr24

(c)

2

0

Software interrupt

Return from interrupt

–

6

LINK

#local8

(c)

1

0

–

5

At constant entry, save old

frame pointer to stack, set

new frame pointer, and

(c)

(d)

1

0

–

4

6

UNLINK

allocate local pointer area

At constant entry, retrieve

old frame pointer from stack.

RET *⁷

RETP *⁸

Return from subroutine

*1: 5 when branching, 4 when not branching

*2: 13 when branching, 12 when not branching

*3: 7 + (a) when branching, 6 + (a) when not branching

*4: 8 when branching, 7 when not branching

*5: 7 when branching, 6 when not branching

*6: 8 + (a) when branching, 7 + (a) when not branching

*7: Retrieve (word) from stack

*8: Retrieve (long word) from stack

*9: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

116

MB90670/675 Series

Table 20 Other Control Instructions (Byte/Word/Long Word) [28 Instructions]

L

A

RM

W

Mnemonic

PUSHWA

PUSHWAH

PUSHWPS

PUSHWrlst

#

~

RG

B

Operation

I

S

T

N

Z

V C

H H

1

2

4

0

(c) word (SP) ← (SP) –2, ((SP)) ←

(c) (A)

–

(c) word (SP) ← (SP) –2, ((SP)) ←

3

5

4

(AH)

*

word (SP) ← (SP) –2, ((SP)) ←

(PS)

(SP) ← (SP) –2n, ((SP)) ←

(rlst)

POPW A

1

2

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

3

4

0

(c)

POPW AH

POPW PS

POPW rlst

–

2

5

4

–

*

word (A) ← ((SP)), (SP) ← (SP)

JCTX @A

1

+2

–

*

–

14

0 6× (c)

word (AH) ← ((SP)), (SP) ←

(SP) +2

word (PS) ← ((SP)), (SP) ←

(SP) +2

AND CCR,

#imm8

2

–

*

–

3

0

OR

CCR,

#imm8

2

(rlst) ← ((SP)), (SP) ← (SP)

+2n

–

2

0

MOV RP, #imm8

MOV ILM, #imm8

2

2+

2

Context switch instruction

–

*

–

3

1

0

2+ (a) 1

MOVEA RWi, ear

MOVEA RWi, eam 2+

MOVEA A, ear

byte (CCR) ← (CCR) and imm8 –

byte (CCR) ← (CCR) or imm8

1

0

–

*

1+ (a) 0

MOVEA A, eam

2

3

byte (RP) ←imm8

byte (ILM) ←imm8

–

3

0

ADDSP #imm8

ADDSP #imm16

1

2

word (RWi) ←ear

word (RWi) ←eam

word(A) ←ear

Z

–

*

–

*

–

0

*

1

MOV A, brgl

MOV brg2, A

1

word (A) ←eam

–

0

1

NOP

ADB

DTB

PCB

SPB

NCC

CMR

word (SP) ← (SP) +ext (imm8)

word (SP) ← (SP) +imm16

byte (A) ← (brgl)

byte (brg2) ← (A)

No operation

Prefix code for accessing AD

space

Prefix code for accessing DT

space

Prefix code for accessing PC

space

Prefix code for accessing SP

space

Prefix code for no flag change

Prefix code for common

register bank

*1: PCB, ADB, SSB, USB, and SPB : 1 state

DTB, DPR : 2 states

*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)

*3: 29 + (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)

*4: Pop count × (c), or push count × (c)

117

MB90670/675 Series

*5: Pop count or push count.

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 21 Bit Manipulation Instructions [21 Instructions]

L

A

RM

W

Mnemonic

#

~

RG

B

Operation

I

S

T

N

Z

V

C

H H

MOVB A, dir:bp

MOVB A,

addr16:bp

3

4

3

5

4

0

(b) byte (A) ← (dir:bp) b

(b) byte (A) ← (addr16:bp) b

(b) byte (A) ← (io:bp) b

Z

*

–

*

–

MOVB A, io:bp

3

4

3

7

6

0 2× (b) bit (dir:bp) b ← (A)

0 2× (b) bit (addr16:bp) b ← (A)

0 2× (b) bit (io:bp) b ← (A)

–

*

–

*

MOVB dir:bp, A

MOVB addr16:bp,

A

MOVB io:bp, A

3

4

3

7

0 2× (b) bit (dir:bp) b ← 1

0 2× (b) bit (addr16:bp) b ← 1

0 2× (b) bit (io:bp) b ← 1

–

*

SETB dir:bp

SETB addr16:bp

SETB io:bp

3

4

3

7

0 2× (b) bit (dir:bp) b ← 0

0 2× (b) bit (addr16:bp) b ← 0

0 2× (b) bit (io:bp) b ← 0

–

*

CLRB dir:bp

CLRB addr16:bp

CLRB io:bp

1

4

5

4

0

(b) Branch when (dir:bp) b = 0

(b) Branch when (addr16:bp) b = 0

(b) Branch when (io:bp) b = 0

–

*

–

*

1

*

2

BBC dir:bp, rel

BBC addr16:bp,

rel

*

1

4

5

4

0

(b) Branch when (dir:bp) b = 1

(b) Branch when (addr16:bp) b = 1

(b) Branch when (io:bp) b = 1

–

*

–

*

1

BBC io:bp, rel

*

2

*

BBS dir:bp, rel

BBS addr16:bp,

rel

3

5

3

0 2× (b) Branch when (addr16:bp) b = 1, –

–

*

–

*

bit = 1

5

4

BBS io:bp, rel

0

–

*

Wait until (io:bp) b = 1

Wait until (io:bp) b = 0

4

5

SBBS addr16:bp,

rel

*

WBTS io:bp

WBTC io:bp

*1: 8 when branching, 7 when not branching

*2: 7 when branching, 6 when not branching

*3: 10 when condition is satisfied, 9 when not satisfied

*4: Undefined count

*5: Until condition is satisfied

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

118

MB90670/675 Series

Table 22 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]

R

G

L

A

H

RM

W

Mnemonic

SWAP

SWAPW/XCHW AL, AH

EXT

EXTW

ZEXT

ZEXTW

#

~

B

Operation

I

S

T

N

Z

V

C

H

1

3

2

1

2

1

0

0 byte (A) 0 to 7 ↔ (A) 8 to 15

0 word (AH) ↔ (AL)

0 byte sign extension

0 word sign extension

0 byte zero extension

0 word zero extension

–

X

–

Z

–

*

–

X

–

Z

–

*

R

–

*

–

*

Table 23 String Instructions [10 Instructions]

R

G

L

H

A

H

RM

W

Mnemonic

#

~

B

Operation

I

S

T

N

Z

V

C

2

5

3

MOVS/MOVSI

MOVSD

2

Byte transfer @AH+ ← @AL+, counter

= RW0

Byte transfer @AH– ← @AL–, counter

= RW0

–

*

2

5

3

*

1

5

4

SCEQ/SCEQI

SCEQD

2

*

–

*

–

1

5

4

*

Byte retrieval (@AH+) – AL, counter =

RW0

5

3

6m +6

FISL/FILSI

2

–

*

–

*

Byte retrieval (@AH–) – AL, counter =

RW0

Byte filling @AH+ ← AL, counter =

RW0

2

8

6

MOVSW/

MOVSWI

MOVSWD

2

Word transfer @AH+ ←@AL+, counter –

–

*

2

8

6

= RW0

–

*

Word transfer @AH– ←@AL–, counter

= RW0

1

8

7

2

*

–

*

–

1

8

7

SCWEQ/

SCWEQI

SCWEQD

*

Word retrieval (@AH+) – AL, counter =

RW0

8

6

6m +6

2

–

*

–

*

Word retrieval (@AH–) – AL, counter =

RW0

FILSW/FILSWI

Word filling @AH+ ← AL, counter =

RW0

m: RW0 value (counter value)

n: Loop count

*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs

*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case

*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) separately

for each.

*4: (b) × n

*5: 2 × (RW0)

*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c) separately

for each.

*7: (c) × n

*8: 2 × (RW0)

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

119

MB90670/675 Series

■ MASK OPTIONS

• MB90670 series

MB90671

MB90672

MB90673

Part number

MB90P673

MB90V670

No.

Specify when ordering

masking

Set with EPROM

programmer

Specifying procedure

Setting not possible

Pull-up resistors

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47, P60 to P67,

P70 to P77, P80,

1

2

Specify by pin

Without pull-up resistor

RST, MD1, MD0

Pull-down resistors

MD1, MD0

Specify by pin

• MB90675 series

Part number

MB90676

MB90677

MB90678

MB90P678

MB90V670

No.

Specify when ordering

masking

Set with EPROM

programmer

Specifying procedure

Setting not possible

Pull-up resistors

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47, P60 to P67,

P70 to P77, P80 to P86,

P90, P91, PA0 to PA7,

PB0 to PB2,

1

2

Specify by pin

Without pull-up resistor

RST, MD1, MD0

Pull-down resistors

MD1, MD0

Specify by pin

Notes: • The pull-up register configured as a port pin is switched-off in the stop mode and during the

hardware standby.

• In turning on power, option settings can not be made until clocks are supplied because 8 machine cycles

are needed for option settings for the MB90P670/P675.

120

MB90670/675 Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB90671PFV

MB90672PFV

MB90673PFV

MB90T673PFV

MB90P673PFV

80-pin Plastic LQFP

(FPT-80P-M05)

MB90671PF

MB90672PF

MB90673PF

MB90T673PF

MB90P673PF

80-pin Plastic QFP

(FPT-80P-M06)

MB90676PFV

MB90677PFV

MB90678PFV

MB90T678PFV

MB90P678PFV

100-pin Plastic LQFP

(FPT-100P-M05)

MB90676PF

MB90677PF

MB90678PF

MB90T678PF

MB90P678PF

100-pin Plastic QFP

(FPT-100P-M06)

121

MB90670/675 Series

■ PACKAGE DIMENSIONS

80-pin Plastic LQFP

(FPT-80P-M05)

14.00±0.20(.551±.008)SQ

1.50−⁺0⁰.^.210⁰

.059 −⁺.^.0⁰⁰04⁸

(Mounting height)

12.00±0.10(.472±.004)SQ

60

41

61

40

13.00

(.512)

NOM

9.50

(.374)

REF

INDEX

80

21

1

20

LEAD No.

Details of "A" part

"A"

0.50±0.08

(.0197±.0031)

0.18−⁺0⁰.^.003⁸

.007 −⁺.^.0⁰⁰01³

0.127 ⁺−0⁰.^.002⁵

.005−⁺.^.0⁰⁰01²

0.10±0.10

(.004±.004)

(STAND OFF)

0.50±0.20(.020±.008)

0.10(.004)

0

10˚

C

1995 FUJITSU LIMITED F80008S-2C-5

Dimensions in mm (inches)

80-pin Plastic QFP

(FPT-80P-M06)

23.90±0.40(.941±.016)

20.00±0.20(.787±.008)

3.35(.132)MAX

(Mounting height)

0.05(.002)MIN

(STAND OFF)

64

41

65

40

12.00(.472)

16.30±0.40

14.00±0.20 17.90±0.40

(.551±.008) (.705±.016)

REF

(.642±.016)

INDEX

80

25

"A"

1

24

LEAD No.

0.80(.0315)TYP

0.35±0.10

(.014±.004)

0.15±0.05(.006±.002)

Details of "B" part

M

0.16(.006)

Details of "A" part

0.25(.010)

0.30(.012)

"B"

0.10(.004)

0

10°

0.18(.007)MAX

0.58(.023)MAX

18.40(.724)REF

0.80±0.20

(.031±.008)

22.30±0.40(.878±.016)

C

1994 FUJITSU LIMITED F80010S-3C-2

Dimensions in mm (inches)

122

MB90670/675 Series

100-pin Plastic LQFP

(FPT-100P-M05)

1.50−⁺0⁰.^.210⁰

16.00±0.20(.630±.008)SQ

14.00±0.10(.551±.004)SQ

(Mounting height)

.059 −⁺.^.0⁰⁰04⁸

75

51

76

50

12.00

(.472)

REF

15.00

(.591)

NOM

Details of "A" part

0.15(.006)

INDEX

0.15(.006)

100

26

0.15(.006)MAX

0.40(.016)MAX

"B"

1

25

LEAD No.

"A"

0.50(.0197)TYP

0.18−⁺0⁰.^.003⁸

.007 −⁺.^.0⁰⁰01³

0.127 ⁺−0⁰.^.002⁵

.005−⁺.^.0⁰⁰01²

M

Details of "B" part

0.08(.003)

0.10±0.10

(.004±.004)

(STAND OFF)

0.50±0.20(.020±.008)

0.10(.004)

0~10˚

C

1995 FUJITSU LIMITED F100007S-2C-3

Dimensions in mm (inches)

100-pin Plastic QFP

(FPT-100P-M06)

23.90±0.40(.941±.016)

20.00±0.20(.787±.008)

3.35(.132)MAX

(Mounting height)

0.05(.002)MIN

(STAND OFF)

80

51

81

50

12.35(.486)

16.30±0.40

14.00±0.20 17.90±0.40

(.551±.008) (.705±.016)

REF

(.642±.016)

INDEX

31

100

"A"

1

30

LEAD No.

0.65(.0256)TYP

0.30±0.10

(.012±.004)

0.15±0.05(.006±.002)

Details of "B" part

M

0.13(.005)

Details of "A" part

0.25(.010)

"B"

0.10(.004)

0.30(.012)

0.18(.007)MAX

0.53(.021)MAX

0

10°

18.85(.742)REF

0.80±0.20

(.031±.008)

22.30±0.40(.878±.016)

C

1994 FUJITSU LIMITED F100008-3C-2

Dimensions in mm (inches)

123

MB90670/675 Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: 81(44) 754-3763

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

Fax: 81(44) 754-3329

http://www.fujitsu.co.jp/

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications,

and are not intended to be incorporated in devices for actual use.

Also, FUJITSU is unable to assume responsibility for

infringement of any patent rights or other rights of third parties

arising from the use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

Fax: (408) 922-9179

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and measurement

equipment, personal or household devices, etc.).

CAUTION:

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded (such

as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608

Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Any semiconductor devices have an inherent chance of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for

export of those products from Japan.

Fax: (65) 281-0220

http://www.fmap.com.sg/

F9811

FUJITSU LIMITED Printed in Japan

124


型号：	MB90P673PF
厂家：	FUJITSU
描述：	16-bit Proprietary Microcontroller 16位微控制器专有微控制器和处理器外围集成电路可编程只读存储器时钟
文件：	总124页 (文件大小：2396K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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