MB90W214A [FUJITSU]
16-bit Proprietary Microcontroller; 16位微控制器专有型号: | MB90W214A |
厂家: | FUJITSU |
描述: | 16-bit Proprietary Microcontroller |
文件: | 总100页 (文件大小:1563K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13501-6E
16-bit Proprietary Microcontroller
CMOS
F2MC-16F MB90210 Series
MB90214/P214A/P214B/W214A/W214B/V210
■ OUTLINE
The MB90210 series is a line of 16-bit microcontrollers particularly suitable for system control of video cameras,
VTRs, and copiers. The F2MC-16F CPU integrated in this series is based on the F2MC*-16, while providing
enhanced instructions for high-level languages and supporting extended addressing modes.
The MB90210 series incorporates a variety of peripheral resources such as a PWC timer with 4 channels, a 10-
bit A/D converter with 8 channels, UART serial ports with 3 channels (1 channel for CTS and 1 channel for dual
input/output pin switching), 16-bit reload timers with 8 channels, and an 8-bit PPG timer with 1 channel.
MB90P214B/W214B is under development.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ PACKAGE
80-pin Plastic QFP
80-pin Ceramic QFP
(FPT-80P-M06)
(FPT-80C-C02)
MB90210 Series
■ FEATURES
F2MC-16F CPU
• Minimum execution time: 62.5 ns/16-MHz oscillation (using a duty control system)
• Instruction sets optimized for controllers
Upward object-compatible with the F2MC-16(H)
Various data types (bit, byte, word, and long-word)
Instruction cycle improved to speed up operation
Extended addressing modes: 25 types
High coding efficiency
Access method (bank access with linear pointer)
Enhanced multiplication and division instructions (with signed instructions added)
Higher-precision operation using a 32-bit accumulator
• Extended intelligent I/O service (Automatic transfer function independent of instructions) access area
expanded to 64 Kbytes
• Enhanced instruction set applicable to high-level language (C) and multitasking
System stack pointer
Enhanced pointer-indirect instructions
Barrel shift instruction
Stack check function
• Increased execution speed: 8-byte instruction queue
• Powerful interrupt functions: 8 levels and 29 sources
Integrated Peripheral Resources
• ROM
: 64 Kbytes (MB90214)
EPROM : 64 Kbytes (MB90W214A/W214B)
OTPROM: 64Kbytes (MB90P214A/P214B)
• RAM: 3 Kbytes (MB90214)
4 Kbytes (MB90P214A/P214B/W214A/W214B/V210)
• General-purpose ports: max. 65 channels
• PWC timer with time measurement function: 4 channels
• 10-bit A/D converter: 8 channels
• UART: 3 channels
• Including: 1 channel with CTS function
1 channel with I/O pin switching function
• 16-bit reload timer
Toggled output, external clock, and gate functions: 4 channels
External clock and gate functions: 4 channels
• 8-bit PPG timer: 1 channel
• DTP/External-interrupt inputs: 4 channels
• Write-inhibit RAM: 256 bytes (MB90V210: 512 bytes)
• Timebase counter: 18 bits
• Clock gear function
• Low-power consumption mode
Sleep mode
Stop mode
Hardware standby mode
2
MB90210 Series
Product Description
• MB90214 is a mask ROM product.
• MB90P214A/P214B are OTPROM products.
• MB90W214A/W214B are EPROM products. ES only.
• Operating temperature of MB90P214A/W214A is –40°C to +85°C. (However, the AC characteristics is assured
in –40°C to +70°C)
• MB90V210 is a evaluation device for the program development. ES only.
3
MB90210 Series
■ PRODUCT LINEUP
Part number
MB90214
MB90P214A
MB90P214B
MB90W214A
MB90W214B
MB90V210
Item
Classification
ROM size
Mask ROM product
64 Kbytes
OTPROM product
64 Kbytes
EPROM product
64 Kbytes
For evaluation
—
RAM size
3 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
CPU functions
The number of instructions:
Instruction bit length:
Instruction length:
412
8 or 16 bits
1 to 7 bytes
Data bit length:
Minimum execution time:
Interrupt processing time:
1, 4, 8, 16, or 32 bits
62.5 ns/16 MHz
1.0 µs/16 MHz (min.)
Ports
I/O ports (N-ch open-drain):
I/O ports (CMOS):
Total:
8
57
65
PWC timer
Number of channels: 4
16-bit reload timer operation (operating clock cycle: 0.25 µs to 1.31 ms)
16-bit pulse-width count operation (Allowing continuous/one-shot measurement, H/L width
measurement, inter-edge measurement, and divided-frequency measurement)
10-bit
A/D converter
Resolution: 10 or 8 bits, Number of inputs: 8
Single conversion mode (conversion for each input channel)
Scan conversion mode (continuous conversion for up to 8 consecutive channels)
Continuous conversion mode (repeated conversion for a selected channel)
Stop conversion mode (conversion every fixed cycle)
UART
Number of channels: 3
(1 channel with CTS function; 1 channel with I/O pin switching function)
Clock-synchronous transfer mode
(full-duplex double buffering, 7- to 9-bit data length, 2400 to 62500 bps)
Asynchronous transfer mode
(full-duplex double buffering, 7- to 9-bit data length, 2400 to 62500 bps)
Timer
Number of channels: 4 channels × 2 types
16-bit reload timer operation (operating clock cycle: 0.25 µs to 1.05 s)
8-bit PPG timer
Number of channels: 1
8-bit PPG operation (operating clock cycle: 0.25 µs to 6 s)
DTP/External
interrupt
Number of inputs: 4
External interrupt mode (allowing interrupts to activate at four different request levels)
Simple DMA start mode (allowing extended I2OS to activate at two different request levels)
Write-inhibit RAM
RAM size: 256 bytes (MB90V210: 512 bytes)
RAM write-protectable with WI pin
Standby mode
Gear function
Package
Stop mode (activated by software or hardware) and sleep mode
Machine clock operating frequency switching: 16, 8, 4, or 1 MHz (at 16 MHz oscillation)
FPT-80P-M06
FPT-80C-C02
PGA-256C-A02
4
MB90210 Series
■ DIFFERENCES BETWEEN MB90214 (MASK ROM PRODUCT) AND MB90P214A/P214B/
W214A/W214B
Part number
MB90P214A
MB90P214B
MB90W214A
MB90W214B
MB90214
Item
ROM
Mask ROM
64 Kbytes
OTPROM
64 Kbytes
EPROM
64 Kbytes
Pin function
43 pins
MD2 pin
MD2/VPP pin
Note: MB90V210, device used for evaluation, is not warranted for electrical specifications.
5
MB90210 Series
■ PIN ASSIGNMENT
(Top view)
X1 65
40 P67/AN7
39 P66/AN6
38 P65/AN5
V
CC
66
P00/D00 67
68
P02/D02 69
37
36 P63/AN3
P01/D01
P64/AN4
70
71
35
34
P03/D03
P04/D04
P62/AN2
V
SS
P05/D05 72
33 P61/AN1
P06/D06 73
32 P60/AN0
74
31
P07/D07
AVSS
P10/D08 75
P11/D09 76
30 AVRL
29 AVRH
P12/D10
AVCC
77
28
P13/D11 78
P14/D12 79
27 PWC3/P47/A23/POUT3
26 PWC2/P46/A22/POUT2
80
25
P15/D13
PWC1/P45/A21/POUT1
(FPT-80P-M06)
(FPT-80C-C02)
6
MB90210 Series
■ PIN DESCRIPTION
Pin no.
Pin name
QFP*
Circuit
type
Function
64,
65
X0,
X1
A
Crystal oscillator pins (16 MHz)
62
66
RST
VCC
VSS
H
External reset request input pin
Digital circuit power supply pin
Digital circuit grounding level
Power supply
Power supply
11,
34,
63
67 to 74
P00 to P07
D00 to D07
B
B
General-purpose I/O ports
These ports are available only in the single-chip mode.
I/O pins for the lower eight bits of external data bus
These pins are available in an external-bus mode.
75 to 80, P10 to P15,
General-purpose I/O ports
1,
2
P16,
P17
These ports are available in the single-chip mode and in an
external-bus mode with the 8-bit data bus specified.
D08 to D13,
D14,
D15
I/O pins for the upper eight bits of external data bus
These pins are available in an external-bus mode with the 16-bit
data bus specified.
3 to 6
7 to 10
12
P20 to P23
A00 to A03
TIN0 to TIN3
E
E
E
General-purpose I/O ports
These ports are available only in the single-chip mode.
Output pins for external address buses A00 to A03
These pins are available in an external-bus mode.
16-bit reload timer 1 (ch.0 to ch.3) input pins
These pins are available when the 16-bit reload timer 1 (ch.0 to
ch.3) input specification is “enabled”. The data on the pin is read
as the 16-bit reload timer 1 (ch.0 to ch.3) input (TIN0 to TIN3).
P24 to P27
A04 to A07
TIN4 to TIN7
General-purpose I/O ports
These ports are available only in the single-chip mode.
Output pins for external address buses A04 to A07
These pins are available in an external-bus mode.
16-bit reload timer 2 (ch.4 to ch.7) input pins
These pins are available when the 16-bit reload timer 2 (ch.4 to
ch.7) input specification is “enabled”. The data on the pin is read
as the 16-bit reload timer 2 (ch.4 to ch.7) input (TIN4 to TIN7).
P30
A08
General-purpose I/O port
This port is available in the single-chip mode or when the middle
address control register setting is “port.”
Output pin for external address bus A08
This pin is available in an external-bus mode and when the middle
address control register set to “address.”
* : FPT-80P-M06, FPT-80C-C02
(Continued)
7
MB90210 Series
Pin no.
Pin name
QFP*
Circuit
type
Function
13
14 to 17
18
P31
E
E
E
General-purpose I/O port
This port is available in the single-chip mode or when the middle
address control register setting is “port”, with the 8-bit PPG
output is disabled.
A09
Output pin for external address bus A09
This pin is available in an external-bus mode and when the middle
address control register setting is “address.”
PPG
PPG timer output pin
This pin is available when the PPG operation mode control
register specification is the PPG output pin.
P32 to P35
General-purpose I/O ports
These ports are available in the single-chip mode or when the
middle address control register setting is “port”, with the 16-bit
reload timer 1 (ch.0 to ch.3) output is disabled.
A10 to A13
TOUT0 to TOUT3
P36
Output pins for external address buses A10 to A13
These pins are available in an external-bus mode and when the
middle address control register setting is “address.”
16-bit reload timer 1 (ch.0 to ch.3) output pin
These pins are available when the 16-bit reload timer 1 (ch.0 to
ch.3) is output operation.
General-purpose I/O port
This port is available when the UART (ch.2) clock output is
disabled either in the single-chip mode or when the middle
address control register setting is “port.”
A14
Output pin for external address bus A14
This pin is available when the UART (ch.2) clock output is
disabled in an external-bus mode and when the middle address
control register setting is “address.”
SCK3
UART (ch.2) clock output pin (SCK3)
This pin is available when the UART (ch.2) clock output is
enabled.
UART (ch.2) external clock input pin (SCK3)
This pin is available when the port is in input mode and the UART
(ch.2) specification is external clock mode.
19
P37
A15
SID3
E
General-purpose I/O port
This port is available in the single-chip mode or when the middle
address control register setting is “port.”
Output pin for external address bus A15
This pin is available in an external-bus mode and when middle
address control register setting is “address.”
UART (ch.2) serial data input pin (SID3)
Since this input is used whenever the SID3 is in input operation,
the output by any other function must be suspended unless the
output is intentionally performed.
* : FPT-80P-M06, FPT-80C-C02
(Continued)
8
MB90210 Series
Pin no.
QFP*
20
Circuit
type
Pin name
Function
P40
E
General-purpose I/O port
This port is available when the UART (ch.2) serial data output
from SOD3 is disabled either in the single-chip mode or when the
upper address control register setting is “port.”
A16
Output pin for external address bus A16
This pin is available when the UART (ch.2) serial data output
from SOD3 is disabled in an external-bus mode and when the
upper address control register setting is “address.”
SOD3
P41
UART (ch.2) serial data output pin (SOD3)
This pin is available when the UART (ch.2) serial data output is
enabled.
21
E
General-purpose I/O port
This port is available when the UART (ch.2) clock output is
disabled either in the single-chip mode or when the upper
address control register setting is “port.”
A17
Output pin for external address bus A17
This pin is available when the UART (ch.2) clock output is
disabled in an external-bus mode and when the upper address
control register setting is “address.”
SCK2
UART (ch.2) clock output pin (SCK2)
This pin is available when the UART (ch.2) clock output is
enabled.
UART (ch.2) external clock input pin (SCK2)
This pin is available when the port is in input mode and the UART
(ch.2) specification is external clock mode.
22
P42
A18
SID2
E
General-purpose I/O port
This port is available in the single-chip mode or when the upper
address control register setting is “port.”
Output pin for external address bus A18
This pin is available in an external-bus mode and when the upper
address control register setting is “address.”
UART (ch.2) serial data input pin (SID2)
Since this input is used whenever the SID2 is in input operation,
the output by any other function must be suspended unless the
output is intentionally performed.
23
P43
E
General-purpose I/O port
This port is available when the UART (ch.2) serial data output
from SOD2 is disabled either in the single-chip mode or when the
upper address control register setting is “port.”
A19
Output pin for external address bus A19
This pin is available when the UART (ch.2) serial data output
from SOD2 is disabled in an external-bus mode and when the
upper address control register setting is “address.”
SOD2
UART (ch.2) serial data output pin (SOD2)
This pin is available when the UART (ch.2) serial data output
from SOD2 is enabled.
* : FPT-80P-M06, FPT-80C-C02
(Continued)
9
MB90210 Series
Pin no.
Pin name
QFP*
Circuit
type
Function
24
PWC0
E
PWC timer input pin
Since this input is used whenever the PWC0 timer is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.
POUT0
P45
PWC timer output pin
This pin is available when the PWC0 is output operation.
25
E
General-purpose I/O port
This port is available in the single-chip mode or when the upper
address control register setting is “port.”
A21
Output pin for external address bus A21
This pin is available in an external-bus mode and when the upper
address control register setting is “address.”
PWC1
PWC timer data sample input pin
Since this input is used whenever the PWC1 timer is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.
POUT1
P46
PWC timer output pin
This pin is available when the PWC1 is output operation.
26
E
General-purpose I/O port
This port is available in the single-chip mode or when the upper
address control register setting is “port.”
A22
Output pin for external address bus A22
This pin is available in an external-bus mode and when the upper
address control register setting is “address.”
PWC2
PWC timer input pin
Since this input is used whenever the PWC2 timer is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.
POUT2
P47
PWC timer output pin
This pin is available when the PWC2 is output operation.
27
E
General-purpose I/O port
This port is available in the single-chip mode or when the upper
address control register setting is “port.”
A23
Output pin for external address bus A23
This pin is available in an external-bus mode and when the upper
address control register setting is “address.”
PWC3
PWC timer input pin
Since this input is used whenever the PWC3 timer is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.
POUT3
PWC timer output pin
This pin is available when the PWC3 is output operation.
* : FPT-80P-M06, FPT-80C-C02
(Continued)
10
MB90210 Series
Pin no.
QFP*
54
Circuit
type
Pin name
P50
Function
E
E
E
E
General-purpose I/O port
This port is available in the single-chip mode and when the CLK
output is disabled.
CLK
P51
RDY
P52
HAK
P53
HRQ
CLK output pin
This pin is available in an external-bus mode with the CLK output
enabled.
55
56
57
General-purpose I/O port
This port is available in the single-chip mode or when the ready
function is disable.
Ready signal input pin
This pin is available in an external-bus mode and when the ready
function is enabled.
General-purpose I/O port
This port is available in the single-chip mode or when the hold
function is disabled.
Hold acknowledge output pin
This pin is available in an external-bus mode and when the hold
function is enabled.
General-purpose I/O port
This port is available in the single-chip mode or when the hold
function is disabled in an external-bus mode.
Hold request input pin
This pin is available in an external-bus mode and when the hold
function is enabled.
Since this input is used during this operation at any time, the
output by any other function must be suspended unless the
output is intentionally performed.
58
P54
D
General-purpose I/O port
This port is available in the single-chip mode, in the external bus
8-bit mode, or when the WRH pin output is disabled.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
CTS0
UART (ch.0) clear-to-send input pin
Since this input is used whenever the UART (ch.0) CTS function
is enabled, the output by any other function must be suspended
unless the output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
WRH
Write strobe output pin for the upper eight bits of data bus
This pin is available in the external bus 16-bit mode with the
WRH pin output enabled in an external-bus mode.
* : FPT-80P-M06, FPT-80C-C02
(Continued)
11
MB90210 Series
Pin no.
Pin name
QFP*
Circuit
type
Function
External interrupt request input pin
58
INT3
D
Since this input is used whenever external interrupts are enabled,
the output by any other function must be suspended unless the
output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
59
P55
E
General-purpose I/O port
This port is available in the single-chip mode or when the WRL
pin output is disabled.
WRL
Write strobe output pin for the lower eight bits of data bus
This pin is available in an external-bus mode and when the WRL
pin output is enabled.
60
61
P56
RD
E
D
General-purpose I/O port
This port is available in the single-chip mode.
Data bus read strobe output pin
This pin is available in an external-bus mode.
P57
General-purpose I/O port
This port is always available.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
WI
RAM write disable request input
Since this input is used during this operation at any time, the
output by any other function must be suspended unless the
output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
32,
33,
35 to 40
P60,
P61,
P62 to P67
C
F
Open-drain I/O ports
These ports are available when the analog input enable register
setting is “port.”
AN0,
AN1,
AN2 to AN7
10-bit A/D converter analog input pins
These pins are available when the analog input enable register
setting is “analog input.”
41 to 43
MD0 to MD2
Operation mode select signal input pins
Connect these pins directly to VCC or VSS.
44
45
HST
P70
G
E
Hardware standby input pin
General-purpose I/O port
This port is available when the UART (ch.1) clock output is
disabled.
* : FPT-80P-M06, FPT-80C-C02
(Continued)
12
MB90210 Series
Pin no.
QFP*
45
Circuit
type
Pin name
SCK1
Function
E
UART (ch.1) clock output pin
This pin is available when the UART (ch.1) clock output is
enabled.
UART (ch.1) external clock input pin
This pin is available when the port is in input mode and the UART
(ch.1) specification is external clock mode.
46
P71
E
General-purpose I/O port
This port is always available.
SID1
UART (ch.1) serial data input pin
Since this input is used whenever the UART (ch.1) is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.
47
48
P72
E
E
General-purpose I/O port
This port is available when the UART (ch.1) serial data output is
disabled.
SOD1
P73
UART (ch.1) serial data output pin
This pin is available when the UART (ch.1) serial data output is
enabled.
General-purpose I/O port
This port is available when the UART (ch.0) clock output is
disabled.
SCK0
UART (ch.0) clock output pin
This pin is available when the UART (ch.0) clock output is
enabled.
UART (ch.0) external clock input pin
This pin is available when the port is in input mode and the UART
(ch.0) specification is external clock mode.
49
50
P74
E
E
D
General-purpose I/O port
This port is always available.
SID0
UART (ch.0) serial data input pin
Since this input is used whenever the UART (ch.0) is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.
P75
General-purpose I/O port
This port is available when the UART (ch.0) serial data output is
disabled.
SOD0
UART (ch.0) serial data output pin
This pin is available when the UART (ch.0) serial data output is
enabled.
51,
52
P80,
P81
General-purpose I/O port
This port is always available.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
* : FPT-80P-M06, FPT-80C-C02
(Continued)
13
MB90210 Series
(Continued)
Pin no.
Pin name
QFP*
Circuit
type
Function
External interrupt request input pin
Since this input is used whenever external interrupts are enabled,
the output by any other function must be suspended unless the
output is intentionally performed.
51,
52
INT0,
INT1
D
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
53
P82
D
General-purpose I/O port
This port is always available.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
INT2
External interrupt request input pin
Since this input is used whenever external interrupts are enabled,
the output by any other function must be suspended unless the
output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
ATG
10-bit A/D converter trigger input pin
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to VCC/VSS
level to use these pins in input mode.
Power supply
Power supply
28
29
AVCC
Analog circuit power supply pin
This power supply must be turned on or off with a potential equal
to or higher than AVCC applied to VCC.
Be sure that AVCC= VCC before use and during operation.
AVRH
Analog circuit reference voltage input pin
This pins must be turned on or off with a potential equal to or
higher than AVRH applied to AVCC.
Power supply
Power supply
30
31
AVRL
AVSS
Analog circuit reference voltage input pin
Analog circuit grounding level
* : FPT-80P-M06, FPT-80C-C02
14
MB90210 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• Oscillation feedback resistor: Approx.1 MΩ
X1
MB90214
MB90P214B
MB90W214B
X0
Standby control
X1
• Oscillation feedback resistor: Approx.1 MΩ
MB90P214A
MB90W214A
X0
Standby control
B
• CMOS-level I/O
R
Standby control provided
MB90214: With or without pull-up/pull-down
reisistor optional
MB90P214A/P214B: Without pull-up/pull-down
resistor
Digital output
Digital output
R
MB90W214A/W214B: Without pull-up/pull-down
resistor
R
Digital input
Standby control
C
• N-ch open-drain output
• CMOS-level hysteresis input
A/D control provided
Digital output
R
A/D input
Digital input
D
• CMOS-level output
R
R
• CMOS-level hysteresis input
Standby control not provided
MB90214: With or without pull-up/pull-down
reisistor optional
MB90P214A/P214B: Without pull-up/pull-down
resistor
Digital output
Digital output
R
MB90W214A/W214B: Without pull-up/pull-down
resistor
Digital input
(Continued)
15
MB90210 Series
(Continued)
Type
Circuit
Remarks
• CMOS-level output
E
R
R
• CMOS-level hysteresis input
Standby control provided
MB90214: With or without pull-up/pull-down
reisistor optional
MB90P214A/P214B: Without pull-up/pull-down
resistor
MB90W214A/W214B: Without pull-up/pull-down
resistor
Digital output
Digital output
R
Digital input
F
• CMOS-level input with no standby control
Mask ROM products only:
MD2: With pull-down resistor
MD1: With pull-up resistor
R
MD0: With pull-down resistor
Digital input
• COMS-level input with no standby control
MD2 of OTPROM products/EPROM products
only
R
Digital input
PP power supply
V
G
• CMOS-level hysteresis input
Standby control not provided
• With input analog filter (40 ns Typ.)
R
Analog filter
Digital input
H
• CMOS-level hysteresis input
Standby control not provided
• With input analog filter (40 ns Typ.)
• With pull-up resistor
Pull-up
resistor
R
MB90214: With or without pull-up/pull-down
resistor optional
MB90P214A/W214A/P214B/W214B:
With pull-up resistor
R
Analog filter
Digital input
: P-type transistor
: N-type transistor
Note: The pull-up and pull-down resistors are always connected, regardless of the state.
16
MB90210 Series
■ HANDLING DEVICES
1. Preventing Latchup
CMOS ICs may cause latchup when a voltage higher than VCC or lower than VSS is applied to input or output
pins, or when a voltage exceeding the rating is applied between VCC and VSS.
If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the
device. Use meticulous care not to let any voltage exceed the maximum rating.
Also, take care to prevent the analog power supply (AVCC and AVRH) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Pins when A/D is not Used
Connect to be AVCC = AVRH = VCC and AVSS = AVRL = VSS even if the A/D converter is not in use.
4. Precautions when Using an External Clock
To reset the internal circuit properly by the Low-level input to the RST pin, the “L” level input to the RST pin
must be maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input.
5. VCC and VSS Pins
Apply equal potential to the VCC and VSS pins.
6. Supply Voltage Variation
The operation assurance range for the VCC supply voltage is as given in the ratings. However, sudden changes
in the supply voltage can cause misoperation, even if the voltage remains within the rated range. Therefore, it
is important to supply a stable voltage to the IC. The recommended power supply control guidelines are that
the commercial frequency (50 to 60 Hz) ripple variation (P-P value) on VCC should be less than 10% of the
standard VCC value and that the transient rate of change during sudden changes, such as during power supply
switching, should be less than 0.1 V/ms.
7. Notes on Using an External Clock
When using an external clock, drive the X0 pin as illustrated below. When an external clock is used, oscillation
stabilization time is required even for power-on reset and wake-up from stop mode.
• Use of External Clock
MB90210
X0
X1
Note: When using an external clock, be sure to input external clock more than 6 machine cycles after
setting the HST pin to “L” to transfer to the hardware standby mode.
17
MB90210 Series
8. Power-on Sequence for A/D Converter Power Supplies and Analog Inputs
Be sure to turn on the digital power supply (VCC) before applying voltage to the A/D converter power supplies
(AVCC, AVRH, and AVRL) and analog inputs (AN0 to AN7).
When turning power supplies off, turn off the A/D converter power supplies (AVCC, AVRH, and AVRL) and analog
inputs (AN0 to AN7) first, then the digital power supply (VCC).
When turning AVRH on or off, be careful not to let it exceed AVCC.
18
MB90210 Series
■ PROGRAMMING FOR MB90P214A/P214B/W214A/W214B
In EPROM mode, the MB90P214A/P214B/W214A/W214B functions equivalent to the MBM27C1000. This
allows the EPROM to be programmed with a general-purpose EPROM programmer by using the dedicated
socket adapter (do not use the electronic signature mode).
1. Program Mode
When shipped from Fujitsu, and after each erasure, all bits (64 K × 8 bits) in the MB90P214A/P214B/W214A/
W214B are in the “1” state. Data is written to the ROM by selectively programming “0’s” into the desired bit
locations. Bits cannot be set to “1” electrically.
2. Programming Procedure
(1) Set the EPROM programmer to MBM27C1000.
(2) Load program data into the EPROM programmer at 10000H to 1FFFFH.
Note that ROM addresses FF0000H to FFFFFFH in the operation mode in the MB90P214A/P214B/W214A/
W214B series assign to 10000H to 1FFFFH in the EPROM mode (on the EPROM programmer).
FFFFFFH
1FFFFH*
FF0000H
10000H*
Operation mode
EPROM mode
(Corresponding addresses on the EPROM mode)
* : Be sure to set the programming, the start address and the stop address on the EPROM programmer to 10000H/1FFFFH.
(3) Mount the MB90P214A/P214B/W214A/W214B on the adapter socket, then fit the adapter socket onto the
EPROM programmer. When mounting the device and the adapter socket, pay attention to their mounting
orientations.
(4) Start programming the program data to the device.
(5) If programming has not successfully resulted, connect a capacitor of approx. 0.1 µF between VCC and GND,
between VPP and GND.
(6) Since the MB90P214A and MB90W214A have CMOS-level input, programming to them may be impossible
depending on the output level of the general-purpose programmer. In that case, connect a pull-up resistor
to the adapter socket side.
Note: The mask ROM products (MB90214) does not support EPROM mode. Data cannot, therefore, be read by
the EPROM programmer.
19
MB90210 Series
3. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer
Part No.
Package
MB90P214B
QFP-80
Compatible socket adapter
Sun Hayato Co., Ltd.
ROM-80QF-32DP-16F
Recommended
programmer
manufacturer
and programmer
name
R4945A
(main unit)
+
R49451A
(adapter)
Advantest corp.
Recommended
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
Advantest Corp.:
TEL: Except JAPAN (81)-3-3930-4111
4. Erase Procedure
Data written in the MB90W214A/W214B are erased (from “0” to “1”) by exposing the chip to ultraviolet rays with
a wavelength of 2,537 Å through the translucent cover.
Recommended irradiation dosage for exposure is 10 Wsec/cm2. This amount is reached in 15 to 20 minutes
with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface
illuminance is 1200 µW/cm2).
If the ultraviolet lamp has a filter, remove the filter before exposure. Attaching a mirrored plate to the lamp
increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. If the translucent
part of the package is stained with oil or adhesive, transmission of ultraviolet rays is degraded, resulting in a
longer erasure time. In that case, clean the translucent part using alcohol (or other solvent not affecting the
package).
The above recommended dosage is a value which takes the guard band into consideration and is a multiple of
the time in which all bits can be evaluated to have been erased. Observe the recommended dosage for erasure;
the purpose of the guard band is to ensure erasure in all temperature and supply voltage ranges. In addition,
check the life span of the lamp and control the illuminance appropriately.
Data in the MB90W214A/W214B are erased by exposure to light with a wavelength of 4000 Å or less.
Data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure
results in a much lower erasure rate than exposure to 2537 Å ultraviolet rays. Note that exposure to such lights
for an extended period will therefore affect system reliability. If the chip is used where it is exposed to any light
with a wavelength of 4000 Å or less, cover the translucent part, for example, with a protective seal to prevent
the chip from being exposed to the light.
Exposure to light with a wavelength of 4,000 to 5,000 Å or more will not erase data in the device. If the light
applied to the chip has a very high illuminance, however, the device may cause malfunction in the circuit for
reasons of general semiconductor characteristics. Although the circuit will recover normal operation when
exposure is stopped, the device requires proper countermeasures for use in a place exposed continuously to
such light even though the wavelength is 4,000 Å or more.
20
MB90210 Series
5. Recommended Screening Conditions
High temperature aging is recommended as the pre-assembly screening procedure.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
6. Programming Yeild
MB90P214A/P214B cannot be write-tested for all bits due to their nature. Therefore the write yield cannot always
be guaranteed to be 100%.
7. Pin Assignment in EPROM Mode
(1) Pins compatible with MBM27C1000
MB90P214A, MB90P214B,
MB90W214A, MB90W214B
MB90P214A, MB90P214B,
MB90W214A, MB90W214B
MBM27C1000
Pin no. Pin name
MBM27C1000
Pin no.
Pin name
MD2 (VPP)
P55
Pin no.
Pin name
VCC
Pin no.
Pin name
1
2
VPP
OE
43
59
19
16
10
9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PGM
N.C.
A14
A13
A08
A09
A11
A16
A10
60
P56
3
A15
A12
A07
A06
A05
A04
A03
A02
A01
A00
D00
D01
D02
GND
P37
4
P34
18
17
12
13
15
20
14
58
74
73
72
71
70
P36
P35
P30
P31
P33
P40
P32
P54
P07
P06
P05
P04
P03
5
P27
6
P26
7
8
P25
8
7
P24
9
6
P23
10
11
12
13
14
15
16
5
P22
4
P21
CE
3
P20
D07
D06
D05
D04
D03
67
68
69
P00
P01
P02
21
MB90210 Series
(2) Power supply and ground connection pins
Type
Power supply
Pin no.
Pin name
41
42
44
66
MD0
MD1
HST
VCC
GND
11
30
31
34
56
57
62
63
VSS
AVRL
AVSS
VSS
P52
P53
RST
VSS
(3) Pins other than MBM27C1000-compatible pins
Pin no.
64
Pin name
Treatment
X0
X1
Pull up to 4.7 kΩ.
65
Open
1
2
21
to
P16
P17
P41
to
27
28
29
32
33
35
to
40
45
to
P47
AVCC
AVRH
P60
P61
P62
to
P67
P70
to
Connect a pull-up resistor of approximately 1 MΩ to each pin.
50
51
to
53
54
55
61
75
to
P75
P80
to
P82
P50
P51
P57
P10
to
80
P15
22
MB90210 Series
■ BLOCK DIAGRAM
4
PWC0 to PWC3
/POUT0 to POUT3
X1
X0
7
PWC
timer
Clock controller
RST
HST
MD2
MD1
MD0
× 4
4
Write-inhibit
RAM
INT0 to INT3
WI
DTP/External
interrupt
× 4
CTS0
SCK3
SID3
D00 to D15
A00 to A23
CLK
RDY
HAK
HRQ
WRH
WRL
RD
SOD3
SCK2
SID2
SOD2
SCK1
SID1
SOD1
SCK0
SID0
13
47
UART × 3
External bus
interface
SOD0
F2MC-16F
CPU
16-bit
timer 1
× 4
TOUT0 to
TOUT3
TIN0 to
TIN3
8
RAM
ROM
TIN4 to
TIN7
4
16-bit
timer 2
× 4
ATG
AN0 to
AN7
AVCC
AVRH
AVRL
AVSS
13
10-bit
A/D converter
8 ch.
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P75
P80 to P82
65
I/O port
8-bit
PPG timer
PPG
23
MB90210 Series
■ PROGRAMMING MODEL
Dedicated Registers
AL
Accumulator
AH
USP
SSP
User stack pointer
System stack pointer
Processor status
PS
PC
Program counter
USPCU
SSPCU
USPCL
SSPCL
User stack upper register
System stack upper register
User stack lower register
System stack lower register
DPR
Direct page register
PCB
DTB
USB
SSB
ADB
8 bits
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
16 bits
32 bits
General-purpose Registers
Max.32 banks
Upper
R 7
R 5
R 3
R 1
R 6
R 4
R 2
R 0
RW 7
RW 6
RL 3
RL 2
RL 1
RL 0
RW 5
RW 4
RW3
RW 2
RW 1
RW 0
Lower
000180H + RP × 10H
16 bits
MSB
LSB
Processor Status (PS)
—
ILM
RP
I
S
T
N
Z
V
C
C C R
24
MB90210 Series
■ MEMORY MAP
Internal ROM
and external bus
External ROM
and external bus
Single chip
ROM area
FFFFFFH
ROM area
Address #1
010000H
Address #2
ROM area
ROM area
FF bank
image
FF bank
image
Address #3
Address #4
Write-inhibit RAM
Write-inhibit RAM
Write-inhibit RAM
Address #5
Address #6
000380H
: Internal
RAM
RAM
RAM
Registers
Registers
Registers
000180H
000100H
: External
: No access
0000C0H
Peripherals
Peripherals
Peripherals
000000H
Address #1
Address #2
Address #3
Address #4
Address #5
Address #6
Type
MB90214
FF0000H
004000H
004000H
004000H
001300H
001200H
001100H
001100H
001100H
000D00H
MB90P214A/P214B
MB90W214A/W214B
FF0000H
001300H
001300H
001200H
001300H
001100H
001100H
MB90V210
(FE0000H)
25
MB90210 Series
■ I/O MAP
Register
name
Resource
name
Address
Register
Access
Initial value
3
3
3
3
3
3
Port 0 data register
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
Port 5 data register
Port 6 data register
Port 7 data register
Port 8 data register
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
000000H
000001H
000002H
000003H
000004H
000005H
000006H
000007H
000008H
*
Port 0
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
11111111
––XXXXXX
–––––XXX
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
*
*
*
*
*
000009H
to 0FH
(Reserved area) *1
3
3
3
3
3
3
000010H
000011H
000012H
000013H
000014H
000015H
000016H
000017H
000018H
*
*
*
*
*
*
Port 0 data direction register
Port1 data direction register
Port 2 data direction register
Port 3 data direction register
Port 4 data direction register
Port 5 data direction register
Analog input enable register
Port 7 data direction register
Port 8 data direction register
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
ADER
DDR7
DDR8
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
00000000
00000000
00000000
00000000
00000000
00000000
11111111
––000000
–––––000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
000019H
to 1FH
(Reserved area) *1
000020H
000021H
Mode control register 0
Status register 0
UMC0
USR0
R/W
UART (ch.0)
00000100
00010000
R/W
R/W
Input data register 0/output data
register 0
UIDR0/
UODR0
000022H
XXXXXXXX
000023H
000024H
000025H
Rate and data register 0
Mode control register 1
Status register 1
URD0
UMC1
USR1
R/W
R/W
R/W
R/W
00000000
00000100
00010000
UART (ch.1)
Input data register 1/output data
register 1
UIDR1/
UODR1
000026H
000027H
XXXXXXXX
Rate and data register 1
URD1
R/W
00000000
(Continued)
26
MB90210 Series
Register
name
Resource
name
Address
Register
Access
Initial value
000028H
000029H
Mode control register 2
Status register 2
UMC2
USR2
R/W
R/W
R/W
UART (ch.2)
00000100
00010000
XXXXXXXX
Input data register 2/output data
register 2
UIDR2/
UODR2
00002AH
00002BH
00002CH
Rate and data register 2
URD2
URDR
R/W
R/W
00000000
–––00000
UART redirect control register
UART (ch.0/2)
00002DH
to 2FH
(Reserved area) *1
000030H
000031H
000032H
000033H
Interrupt/DTP enable register
Interrupt/DTP factor register
Request level setting register
ENIR
EIRR
ELVR
R/W
DTP/external
interrupt
––––0000
––––0000
00000000
R/W
R/W
(Reserved area) *1
000034H
000035H
AD control status register
ADCS
R/W
10-bit A/D
converter
00000000
00000000
000036H
to 37H
AD data register
ADCD
TMCSR0
TMCSR1
TMCSR2
TMCSR3
TMR0
R/W
*4
XXXXXXXX
0–––––XX
000038H
to 39H
Timer control status register 0
Timer control status register 1
Timer control status register 2
Timer control status register 3
Timer 0 timer register
R/W
R/W
R/W
R/W
R
16-bit reload
timer 1 (ch.0)
00000000
––––0000
00003AH
to 3BH
16-bit reload
timer 1 (ch.1)
00000000
––––0000
00003CH
to 3DH
16-bit reload
timer 1 (ch.2)
00000000
––––0000
00003EH
to 3FH
16-bit reload
timer 1 (ch.3)
00000000
––––0000
000040H
000041H
000042H
000043H
000044H
000045H
000046H
000047H
16-bit reload
timer 1 (ch.0)
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
(Continued)
Timer 0 reload register
Timer 1 timer register
Timer 1 reload register
TMRLR0
TMR1
W
R
16-bit reload
timer 1 (ch.1)
TMRLR1
W
27
MB90210 Series
Register
name
Resource
name
Address
Register
Access
Initial value
000048H
000049H
00004AH
00004BH
00004CH
00004DH
00004EH
00004FH
000050H
000051H
000052H
000053H
000054H
000055H
000056H
000057H
000058H
000059H
00005AH
00005BH
00005CH
00005DH
00005EH
00005FH
Timer 2 timer register
Timer 2 reload register
Timer 3 timer register
Timer 3 reload register
Timer 4 timer register
Timer 4 reload register
Timer 5 timer register
Timer 5 reload register
Timer 6 timer register
Timer 6 reload register
Timer 7 timer register
Timer 7 reload register
Timer control status register 4
TMR2
TMRLR2
TMR3
R
16-bit reload
timer 1 (ch.2)
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
W
R
16-bit reload
timer 1 (ch.3)
TMRLR3
TMR4
W
R
16-bit reload
timer 2 (ch.4)
TMRLR4
TMR5
W
R
16-bit reload
timer 2 (ch.5)
TMRLR5
TMR6
W
R
16-bit reload
timer 2 (ch.6)
TMRLR6
TMR7
W
R
16-bit reload
timer 2 (ch.7)
TMRLR7
TMCSR4
W
R/W
16-bit reload
timer 2 (ch.4)
000060H
000061H
000062H
000063H
000064H
000065H
00000000
(Reserved area) *1
Timer control status register 5
Timer control status register 6
TMCSR5
R/W
16-bit reload
timer 2 (ch.5)
00000000
(Reserved area) *1
TMCSR6
R/W
16-bit reload
timer 2 (ch.6)
00000000
(Continued)
(Reserved area) *1
28
MB90210 Series
Register
name
Resource
Address
Register
Access
R/W
Initial value
name
Timer control status register 7
TMCSR7
16-bit reload
timer 2 (ch.7)
000066H
000067H
000068H
000069H
00006AH
00006BH
00006CH
00006DH
00006EH
00000000
(Reserved area) *1
PWC0 divide ratio register
PWC1 divide ratio register
PWC2 divide ratio register
PWC3 divide ratio register
DIVR0
R/W
PWC timer
(ch.0)
––––––00
––––––00
––––––00
––––––00
(Reserved area) *1
DIVR1
R/W
PWC timer
(ch.1)
(Reserved area) *1
DIVR2
R/W
PWC timer
(ch.2)
(Reserved area) *1
DIVR3
R/W
PWC timer
(ch.3)
00006FH
000070H
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
00007FH
(Reserved area) *1
PWC0 control status register
PWC0 data buffer register
PWC1 control status register
PWC1 data buffer register
PWC2 control status register
PWC2 data buffer register
PWC3 control status register
PWC3 data buffer register
PWCSR0
PWCR0
PWCSR1
PWCR1
PWCSR2
PWCR2
PWCSR3
PWCR3
R/W
PWC timer
(ch.0)
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWC timer
(ch.1)
PWC timer
(ch.2)
PWC timer
(ch.3)
000080H
to 87H
(Reserved area) *1
000088H
000089H
PPG operation mode control register
PPGC
R/W
8-bit PPG timer 00000––1
(Continued)
(Reserved area) *1
29
MB90210 Series
Register
name
Resource
name
Address
Register
Access
Initial value
00008AH
00008BH
PPG reload register
WI control register
PRL
R/W
8-bit PPG timer
XXXXXXXX
XXXXXXXX
00008CH
to 8DH
(Reserved area) *1
Write-inhibit RAM
00008EH
WICR
R/W
–––X––––
00008FH
to 9EH
(Reserved area) *1
Delayed interrupt source generate/
release register
DIRR
R/W
R/W
Delayed interrupt
generation module
00009FH
0000A0H
–––––––0
0 00 1
Standby control register
STBYC
Low-power
consumption
mode
0000A1H
to A2H
(Reserved area) *1
0000A3H
0000A4H
0000A5H
Middle address control register
Upper address control register
External pin control register
MACR
HACR
EPCR
W
External pin
########
########
##0–0#00
W
W
0000A6H
to A7H
(Reserved area) *1
0000A8H
0000A9H
Watchdog timer control register
Timebase timer control register
WTC
R/W
R/W
Watchdog timer XXXXXXXX
TBTC
Timebase timer
1––00000
0000AAH
to AFH
(Reserved area) *1
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
Interrupt control register 00
Interrupt control register 01
Interrupt control register 02
Interrupt control register 03
Interrupt control register 04
Interrupt control register 05
Interrupt control register 06
Interrupt control register 07
Interrupt control register 08
Interrupt control register 09
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
R/W
Interrupt
controller
00000111
00000111
00000111
00000111
00000111
00000111
00000111
00000111
00000111
00000111
(Continued)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
30
MB90210 Series
(Continued)
Register
name
Resource
name
Address
Register
Access
Initial value
0000BAH
0000BBH
0000BCH
0000BDH
0000BEH
0000BFH
Interrupt control register 10
Interrupt control register 11
Interrupt control register 12
Interrupt control register 13
Interrupt control register 14
Interrupt control register 15
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt
controller
00000111
00000111
00000111
00000111
00000111
00000111
0000C0H
to FFH
(External area) *2
Initial value
0: The initial value of this bit is 0.
1: The initial value of this bit is 1.
X: The initial value of this bit is undefined.
–: This bit is not used. The initial value is undefined.
: The initial value of this bit varies with the reset source.
#: The initial value of this bit varies with the operation mode.
*1: Access inhibited
*2: The onlyareaavailablefortheexternalaccessbelow address0000FFH isthisarea. Accessestotheseaddresses
are handled as accesses to an external I/O area.
*3: When the external bus is enabled, do not access any register not serving as a general-purpose port in the areas
from address 000000H to 000005H and from 000010H to 000015H.
*4: Writing to bit 15 is possible. Writing to other bits is used as a test function.
31
MB90210 Series
■ INTERRUPT SOURCES AND INTERRUPT VECTORS/INTERRUPT
CONTROL REGISTERS
Interrupt vector
Interrupt control register
EI2OS
Interrupt source
support
No.
Address
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
ICR
—
Address
Reset
×
×
×
# 08
# 09
# 10
# 11
08H
09H
0AH
0BH
—
—
—
INT9 instruction
Exceptional
—
—
UART interrupt #0
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
000B0H
000B1H
000B2H
000B3H
000B4H
000B5H
000B6H
000B7H
000B8H
000B9H
000BAH
UART interrupt #1
# 12
# 13
# 14
# 15
# 16
# 17
# 18
# 19
# 20
# 21
# 22
# 23
# 24
# 25
# 26
# 27
# 28
# 29
# 30
# 31
# 32
# 33
# 34
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
UART interrupt #2
UART interrupt #3
PWC timer # 0 · count completed
PWC timer # 0 · overflow
PWC timer # 1 · count completed
PWC timer # 1 · overflow
PWC timer # 2 · count completed
PWC timer # 2 · overflow
PWC timer # 3 · count completed
PWC timer # 3 · overflow
16-bit reload timer 1 # 0 overflow
16-bit reload timer 1 # 1 overflow
16-bit reload timer 1 # 2 overflow
16-bit reload timer 1 # 3 overflow
16-bit reload timer 2 # 4 overflow
16-bit reload timer 2 # 5 overflow
16-bit reload timer 2 # 6 overflow
16-bit reload timer 2 # 7 overflow
A/D converter count completed
Timebase timer interval interrupt
UART2 · transmission completed
UART2 · reception completed
000BBH
(Continued)
32
MB90210 Series
(Continued)
Interrupt vector
No. Address
Interrupt control register
EI2OS
support
Interrupt source
ICR
Address
UART1 · transmission completed
# 35
23H
FFFF70H
FFFF6CH
ICR12
0000BCH
UART1 · reception completed
UART0 · transmission completed
UART0 · reception completed
Delayed interrupt generation module
Stack fault
# 36
# 37
# 39
# 42
24H
25H
27H
2AH
FFFF68H
FFFF60H
FFFF54H
FFFC00H
ICR13
ICR14
ICR15
—
0000BDH
0000BEH
0000BFH
—
×
×
# 255 FFH
: EI2OS is supported (with stop request).
: EI2OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI2OS is used
for one of the two, EI2OS and ordinary interrupt are not both available for the other (with stop request).
: EI2OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI2OS is used
for one of the two, EI2OS and ordinary interrupt are not both available for the other (with no stop request).
2
×
: EI OS is not supported.
33
MB90210 Series
■ PERIPHERAL RESOURCES
1. Parallel Ports
The MB90210 series has 57 I/O pins and 8 open-drain I/O pins.
Ports 0 to 5, 7, and 8 are I/O ports. Each of these ports serves as an input port when the data direction register
value is 0 and as an output port when the value is 1.
Port 6 is an open-drain port, which may be used as a port when the analog input enable register value is 0.
(1) Register Configuration
• Port data registers 0 to 8 (PDR0 to PDR8)
Port data register
Bit
15
14
13
12
11
10
9
8
Address: PDR1 000001 H
PDR3 000003H
PDR5 000005H
PDx7
PDx6
PDx5
PDx4
PDx3
PDx2
PDx1
PDx0
PDR7 000007H
Read/write
Initial value
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
→
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Port data register
Bit
7
6
5
4
3
2
1
0
Address: PDR0 000000 H
PDR2 000002H
PDx7
PDx6
PDx5
PDx4
PDx3
PDx2
PDx1
PDx0
PDRx
PDR4 000004H
PDR6 000006H
PDR8 000008H
Read/write
Initial value
→
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(1)
(X)
(1)
(X)
(1)
(X)
(1)
(X)
(1)
(X)
(1)
(X)
(1)
(X)
(1) ← Only for the PDR6
Note: No register bit is included in bits 7 and 6 of port 7 or bits 7 to 3 of port 8.
• Port direction registers 0 to 5, 7, and 8 (DDR0 to DDR5, DDR7, and DDR8)
Port direction register
Bit
15
14
13
12
11
10
9
8
Address: DDR1 000011 H
DDR3 000013H
DDR5 000015H
DDx7
DDx6
DDx5
DDx4
DDx3
DDx2
DDx1
DDx0
DDR7 000017H
Read/write
Initial value
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
( 0)
Port direction register
Bit
7
6
5
4
3
2
1
0
Address: DDR0 000010 H
DDR2 000012H
DDx7
DDx6
DDx5
DDx4
DDx3
DDx2
DDx1
DDx0
DDRx
DDR4 000014H
DDR8 000018H
Read/write
Initial value →
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0) (0) (0) (0) (0) (0)
Note: No register bit is included in bits 7 and 6 of port 7 or bits 7 to 3 of port 8.
Port 6 has no DDR.
34
MB90210 Series
• Analog input enable register (ADER)
Analog input enable register
Address: ADER 000016 H
Bit
7
6
5
4
3
2
1
0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
ADER
Read/write
Initial value →
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(1) (1) (1) (1) (1) (1) (1) (1)
(2) Block Diagram
• I/O port (Port 0 to 5, 7, and 8)
Port data register read
Port data register
Port data register write
Port direction register
Port direction register write
Pin
Port direction register read
• I/O port with an open-drain output (Port 6)
RMW
(Read-modify-write instruction)
Port data register read
Port data register
Pin
Port data register write
Analog input enable register
Analog input enable register write
Analog input enable register read
35
MB90210 Series
2. 16-bit Reload Timer 1 (with Event Count Function)
The 16-bit reload timer 1 consists of a 16-bit down counter, a 16-bit reload register, an input pin (TIN), an output
pin (TOUT), and a control register. The input clock can be selected from among three internal clocks and one
external clock. At the output pin (TOUT), the pulses in the toggled output waveform are output in the reload
mode; the rectangular pulses indicating that the timer is counting are in the single-shot mode. The input pin
(TIN) can be used for event input in the event count mode, and for trigger input or gate input in the internal clock
mode.
MB90210 series contains four channels for this timer.
(1) Register Configuration
• Timer control status register (TMCSR)
Timer control status register (Upper byte)
Bit
15
14
13
12
11
10
9
8
Address: ch.0
ch.1
000039H
00003BH
00003DH
00003FH
—
—
—
—
CSL1
CSL0
MOD2
MOD1
ch.2
ch.3
Read/write
Initial value
→
→
(
(
—
—
)
)
(
(
—
—
)
)
(
(
—
—
)
)
(
(
—
—
)
)
(R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
Timer control status register (Lower byte)
Bit
7
6
5
4
3
2
1
0
Address: ch.0
ch.1
000038 H
00003AH
00003CH
00003EH
MDO0
OUTE
OUTL
RELD
INTE
UF
CNTE
TRG
TMCSRx
ch.2
ch.3
Read/write
Initial value →
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0) (0) (0) (0) (0) (0)
• Timer register (TMR)
Timer register (Upper byte)
Bit
15
14
13
12
11
10
9
8
Address: ch.0
ch.1
000041H
000045H
000049H
00004DH
ch.2
ch.3
Read/write
Initial value
→
→
(
R
)
(
R
)
(
R
)
(
R
)
(
R
)
(
R
)
(
R
)
(R)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Timer register (Lower byte)
Bit
7
6
5
4
3
2
1
0
Address: ch.0
ch.1
000040H
000044H
000048H
TMRx
ch.2
ch.3
00004CH
Read/write
Initial value
→
→
(
R
)
(
R
)
(
R
)
(
R
)
(
R
)
(
R
)
(
R
)
(R)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
36
MB90210 Series
• Reload register (TMRLR)
Reload register (Upper byte)
Bit
15
14
13
12
11
10
9
8
Address: ch.0
ch.1
000043H
000047H
00004BH
00004FH
ch.2
ch.3
Read/write
Initial value
→
→
(
W
)
(
W
)
(
W
)
(
W
)
(
W
)
(
W
)
(
W
)
(W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Reroal register (Lower byte)
Bit
7
6
5
4
3
2
1
0
Address: ch.0
ch.1
000042H
000046H
00004AH
TMRLRx
ch.2
ch.3
00004EH
Read/write
Initial value
→
→
(
W
)
(
W
)
(
W
)
(
W
)
(
W
)
(
W
)
(
W
)
(W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(2) Block Diagram
16
8
16-bit reload register
16-bit down counter
Reload
RELD
OUTE
OUTL
I NTE
UF
16
2
OUT
CTL.
GATE
2
IRQ
UF
CSL 1
CSL 0
Clock selector
Clear
EI2 OSCLR
CNTE
TRG
Retrigger
2
IN CTL
Port (TIN)
EXCK
3
φ
φ
φ
Port (TOUT)
Prescaler clear
21 23 25
MOD 2
UART (timer 1 ch.2 output)
A/D (timer 1 ch.3 output)
MOD 1
MOD 0
Internal clock
3
37
MB90210 Series
3. 16-bit Reload Timer 2 (with Gate Mode)
The 16-bit reload timer 2 consists of a 16-bit down counter, a 16-bit reload register, an input pin (TIN), and an
8-bit control register. The input clock can be selected from among four internal clocks.
The MB90210 series contains four channels for this timer.
(1) Register Configuration
• Timer control status register (TMCSR)
Timer control status register
Bit
7
6
5
4
3
2
1
0
Address: ch.4
ch.5
000060 H
000062H
000064H
000066H
CSL1
CSL0
GATE
GATL
RELD
INTE
UF
STRT
TMCSRx
ch.6
ch.7
Read/write
Initial value
→
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0) (0) (0) (0) (0) (0)
• Timer register (TMR)
Timer register (Upper byte)
Bit
15
14
13
12
11
10
9
8
Address: ch.4
ch.5
000051H
000055H
000059H
00005DH
ch.6
ch.7
Read/write
Initial value
→
→
(
R
)
(
R
)
(
R
)
(
R
)
(
R
)
(
R
)
(
R
)
(R)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Timer register (Lower byte)
Bit
7
6
5
4
3
2
1
0
Address: ch.4
ch.5
000050H
000054H
000058H
00005CH
TMRx
ch.6
ch.7
Read/write
Initial value
→
→
(
R
)
(
R
)
(
R
)
(
R
)
(
R
)
(
R
)
(
R
)
(R)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
• Reload register (TMRLR)
Reload register (Upper byte)
Bit
15
14
13
12
11
10
9
8
Address: ch.4
ch.5
000053H
000057H
00005BH
00005FH
ch.6
ch.7
Read/write
Initial value
→
→
(
W
)
(
W
)
(
W
)
(
W
)
(
W
)
(
W
)
(
W
)
(W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Reload register (Lower byte)
Bit
7
6
5
4
3
2
1
0
Address: ch.4
ch.5
000052H
000056H
00005AH
00005EH
TMRLRx
ch.6
ch.7
Read/write
Initial value
→
→
(
W
)
(
W
)
(
W
)
(
W
)
(
W
)
(
W
)
(
W
)
(W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
38
MB90210 Series
(2) Block Diagram
16
4
16-bit reload register
16-bit down counter
Reload
UF
16
RELD
INTE
2
GATE
IRQ
UF
CSL 1
Clear
Clock selector
STRT
EI2 OSCLR
CSL 0
Clear (RELD = 0)
2
IN CTL
Port (TIN)
φ
φ
φ
φ
2 2 2 5 26 28
2
GATE
GATL
2
39
MB90210 Series
4. UART
The UART is a serial I/O port for synchronous or asynchronous communication with external resources. It has
the following features:
• Full duplex double buffer
• Data transfer synchronous or asynchronous with clock pulses
• Multiprocessor mode support (Mode 2)
• Built-in dedicated baud-rate generator (Nine types)
• Arbitrary baud-rate setting from external clock input or internal timer
(Use the 16-bit reroad timer 1 channel 2 for internal timer.)
• Variable data length (7 to 9 bits (without parity bit); 6 to 8 bits (with parity bit))
• Variable data length (7 to 9 bit no parity, 6 to 8 bit with parity)
• Error detection function (Framing, overrun, parity)
• Interrupt function (Two sources for transmission and reception)
• Transfer in NRZ format
The MB90210 series contains three channels for the UART.
UART channel 0 has the CTS function.
UART channel 2 provides dual I/O pin switching.
(1) Register Configuration
• Serial mode control register (UMC)
Serial mode control register
Bit
7
6
5
4
3
2
1
0
Address: ch.0
ch.1
000020 H
000024H
000028H
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
UMC
ch.2
Read/write
Initial value
→
→
(R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0) (0) (0)
(W)
(1)
(R/W) (R/W)
(0) (0)
• Status register (USR)
Status register
Bit
15
14
13
12
11
10
9
8
Address: ch.0
ch.1
000021 H
000025H
000029H
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
USR
ch.2
Read/write
Initial value
→
→
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(1)
(R/W) (R/W)
(R)
(0)
(R)
(0)
(0)
(0)
• Input data register (UIDR)/output data register (UODR)
Input data register/output data register
Bit
7
6
5
4
3
2
1
0
Address: ch.0
ch.1
000022 H
000026H
00002AH
D7
D6
D5
D4
D3
D2
D1
D0
UIDR (read)/
UODR (write)
ch.2
Read/write
Initial value
→
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X) (X) (X) (X) (X) (X) (X)
40
MB90210 Series
• Rate and data register (URD)
Rate and data register
Bit
15
14
13
12
11
10
9
8
Address: ch.0
ch.1
000023 H
000027H
00002BH
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
URDx
ch.2
Read/write
Initial value
→
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0) (0) (0) (0) (0) (0)
• UART redirect control register (URDR)
UART redirect control register
Bit
7
6
5
4
3
2
1
0
Address:
00002C H
—
—
—
CTE
CSP
CTSE
UDPE
SEL3
URDR
Read/write
Initial value
→
→
(—)
(—)
(—)
(—)
(—)
(—)
(R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0) (0) (0)
41
MB90210 Series
(2) Block Diagram
CONTROL BUS
Reception interrupt
(To CPU)
Dedicated baud-rate clock
16-bit reload timer 1 channel 2
SCK0 to SCK3
Transmitting clock pulse
Transmission interrupt
(To CPU)
(internally connected)
Clock
selector circuit
Receiving clock pulse
External clock
Reception control circuit
Transmission control circuit
SID0 to SID3
Transmission control
circuit
Start bit detector
Transmission bit
counter
Received bit counter
Recieved parity
bit counter
Transmission parity
counter
SOD0 to SOD3
Reception status
detection circuit
Reception shifter
Transmission shifter
Start of
End of reception
transmission
SIDR
UODR
Reception error
occurence signal for
EI2OS (To CPU)
Internal data bus
PEN
SBL
RDRF
ORFE
PE
TDRE
RIE
TIE
BCH
RC3
RC2
RC1
RC0
BCH0
P
MC1
MC0
SMDE
RFC
SCKE
SOE
UMC
register
USR
register
URD
register
RBF
TBF
D8
CONTROL BUS
42
MB90210 Series
5. 10-bit A/D Converter
The 10-bit A/D converter converts the analog input voltage to a digital value. It has the following features:
• Conversion time: min.6.125 µs per channel (at 16-MHz machine clock)
• RC-type successive approximation with built-in sample-and-hold circuit
• 10-bit or 8-bit resolution
• Eight analog input channels programmable for selection
Single conversion mode: Selects and converts one channel.
Scan conversion mode: Converts multiple consecutive channels (up to eight channels programmable).
Consecutive conversion mode: Converts a specified channel repeatedly.
Stop conversion mode: Converts one channel and suspends its own operation until the next activation (allowing
synchronized conversion start).
• On completion of A/D conversion, the converter can generate an interrupt request to the CPU. This interrupt
generation can activate the EI2OS to transfer the A/D conversion result to memory, making the converter
suitable for continuous operation.
• Conversion can be activated by software, external trigger (falling edge), and/or timer (rising edge) as selected.
Use the 16-bit reroad timer 1 channel 3 for the timer.
(1) Register Configuration
• A/D Control status register (ADCS1 and ADCS0)
A/D Control status register (Upper byte)
Bit 15
BUSY
14
13
12
11
10
9
8
Address:
000035 H
INT
INTE
PAUS
STS1
STS0
STRT
—
ADCS1
Read/write
Initial value
→
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0) (0) (0) (0)
(W)
(0)
(—)
(0)
A/D Control status register (Lower byte)
Bit
7
6
5
4
3
2
1
0
Address:
000034 H
MD1
MD0
ANS2
ANS1
ANS0
ANE2
ANE1
ANE0
ADCS0
Read/write
Initial value
→
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0) (0) (0) (0) (0) (0)
• A/D Data registers (ADCD1 and ADCD0)
A/D Data register (Upper byte)
Bit 15
S10
14
13
12
11
10
9
8
Address:
000037 H
—
—
—
—
—
D9
D8
ADCD1
Read/write
Initial value
→
→
(W)
(0)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R)
(X)
(R)
(X)
A/D Data register (Lower byte)
Address: 000036 H
Bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
ADCD0
Read/write
Initial value
→
→
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
43
MB90210 Series
(2) Block Diagram
AV CC
AVRH/AVRL
AV SS
D/A converter
MPX
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Successive
approximation register
Comparator
Sample-and-hold circuit
A/D data register
ADCD0, ADCD1
A/D control status register
Trigger activation
Timer activation
ADCS0, ADCS1
ATG
16-bit reload timer 1 channel 3
(internally connected)
Operation clock
Prescaler
Machine clock (φ)
44
MB90210 Series
6. PWC(Pulse Width Count) Timer
The PWC (pulse width count) timer is a 16-bit multifunction up-count timer with an input-signal pulse-width count
function and a reload timer function. The hardware configuration of this module is a 16-bit up-count timer, an
input pulse divider with divide ratio control register, four count input pins, and a 16-bit control register. Using
these components, the PWC timer provides the following features:
• Timer functions:
An interrupt request can be generated at set time intervals.
Pulse signals synchronized with the timer cycle can be output.
Thereference internalclockcanbeselectedfromamongthreeinternalclocks.
The time between arbitrary pulse input events can be counted.
The reference internal clock can be selected from among three internalclocks.
Various count modes:
• Pulse-width count functions:
“H” pulse width (↑ to ↓) /“L” pulse width (↑ to ↓)
Rising-edge cycle (↑ to ↑) /Falling-edge cycle (↓ to ↓)
Count between edges (↑ or ↓ to ↓ or ↑)
Cycle count can be performed by 22n division (n = 1, 2, 3, 4) of the input
pulse, with an 8 bit input divider.
An interrupt request can be generated once counting has been performed.
The number of times counting is to be performed (once or subsequently) can
be selected.
The MB90210 series contains four channels for the PWC timer.
(1) Register Configuration
• PWC control status register (PWCSR)
PWC control status register (Upper byte)
Bit
15
14
13
12
11
10
9
8
Address: ch.0
ch.1
000071 H
000075H
000079H
00007DH
STRT
ch.2
STOP
EDIR
EDIE
OVIR
OVIE
ERR
POUT
ch.3
Read/write
Initial value
→
(R/W) (R/W)
(R)
(0)
(R/W) (R/W) (R/W)
(R)
(0)
(R/W)
(0)
→
(0)
(0)
(0)
(0)
(0)
PWC control status register (Lower byte)
Bit
7
6
5
4
3
2
1
0
Address: ch.0
ch.1
000070 H
000074H
000078H
00007CH
CKS1
CKS0
PIS1
PIS0
S/C
MOD2
MOD1
MOD0
PWCSRx
ch.2
ch.3
Read/write
Initial value
→
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0) (0) (0) (0) (0) (0)
45
MB90210 Series
• PWC data buffer register (PWCR)
PWC data buffer register (Upper byte)
Bit
15
14
13
12
11
10
9
8
Address: ch.0
ch.1
000073 H
000077H
00007BH
00007FH
ch.2
ch.3
Read/write
Initial value
→
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
PWC data buffer register (Lower byte)
Bit
7
6
5
4
3
2
1
0
Address: ch.0
ch.1
000072 H
000076H
00007AH
00007EH
PWCR
ch.2
ch.3
Read/write
Initial value
→
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• PWC divide ratio control register (DIVR)
Divide ratio control register
Bit
7
6
5
4
3
2
1
0
Address: ch.0
ch.1
000068 H
00006AH
00006CH
00006EH
—
—
—
—
—
—
DIV1
DIV0
DIVR
ch.2
ch.3
Read/write
Initial value
→
→
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R/W) (R/W)
(0) (0)
46
MB90210 Series
(2) Block Diagram
PWCR read
16
Error detection
ERR
PWCR
16
16
Internal clock
(machine clock/4)
Reload
Data transfer
16
2 2
Clock
Overflow
Clock
16-bit up-count timer
divider
2 3
Timer clear
CKS 1
CKS 0
Count enable
Control circuit
Divider clear
Start edge
select
End edge Dividing
PWC0
PWC1
PWC2
PWC3
select
ON/OFF
Count start edge
Edge
detection
Count edge end
Count end interrupt edge
PIS 1
PIS 0
8-bit
divider
PIS 1
PIS 0
CKS 1
CKS 0
ERR
Overflow interrupt request
15
PWCSR
Divide ratio
select
Overflow
F.F.
POUT
*
2
DIVR
* : The POUT pins of the MB90210 series are assigned as follows:
Channel
ch.0
POUT pin
P44/A20/PWC0/POUT0
PWC
PWC
ch.1
P45/A21/PWC1/POUT1
P46/A22/PWC2/POUT2
P47/A23/PWC3/POUT3
PWC
PWC
ch.2
ch.3
47
MB90210 Series
7. 8-bit PPG Timer
This block is an 8-bit reload timer module for PPG output by controlling pulse output according to the timer
operation.
The hardware configuration of this block is an 8-bit down counter, two 8-bit reload registers, an 8-bit control
register, and an external pulse output pin. Using these components, the module provides the following features:
PPG output operation: The module outputs pulse waves of any period and duty factor. It can also be used as
a D/A converter using an external circuit.
(1) Register Configuration
• PPG operation mode control register (PPGC)
Bit
7
6
5
4
3
2
1
0
PPG operation mode control register
Address: 000088 H
PEN
PCKS
POE Reserved
PUF
—
—
Reserved
PPGC
Read/write
Initial value →
→
(R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0) (0) (0)
(—)
(—)
(—)
(—)
(R/W)
(1)
• PPG reload registers (PRLL and RRLH)
PPG reload register
Address:
Bit 15
14
13
12
11
10
9
8
00008B H
PRLH
Read/write
Initial value
→
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X) (X) (X) (X) (X) (X) (X)
Bit
7
6
5
4
3
2
1
0
PPG reload register
Address:
00008A H
PRLL
Read/write
Initial value →
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X) (X) (X) (X) (X) (X) (X)
48
MB90210 Series
(2) Block Diagram
PPG
output pin
(Port section)
Output enable
Output A of timebase counter
Output B of timebase counter
PPG
output latch
Clear
Invert
PEN
Count clock
selection
PCNT (Down counter)
Reload
L/H selector
PRLL
PRLBH
PRLH
Low-byte data bus
High-byte data bus
PPGC
Operation
mode control
49
MB90210 Series
8. DTP/External Interrupt
The data transfer peripheral (DTP) is located between external peripherals and the F2MC-16F CPU. It receives
a DMA request or an interrupt request generated by the external peripherals and reports it to the F2MC-16F
CPU to activate the extended intelligent I/O service or interrupt handler. The user can select two request levels
of “H” and “L” for extended intelligent I/O service or, and four request levels of “H,” “L,” rising edge and falling
edge for external interrupt requests.
(1) Register Configuration
• Interrupt/DTP enable register (ENIR)
Bit
7
6
5
4
3
2
1
0
Interrupt/DTP enable register
Address: 000030H
—
—
—
—
EN3
EN2
EN1
EN0
ENIR
Read/write
Initial value →
→
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
• Interrupt/DTP source register (EIRR)
Bit
15
14
13
12
11
10
9
8
Interrupt/DTP source register
Address: 000031 H
—
—
—
—
ER3
ER2
ER1
ER0
EIRR
Read/write
Initial value →
→
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
• Request level setting register (ELVR)
Bit
7
6
5
4
3
2
1
0
Request level setting register
Address: 000032 H
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
ELVR
Read/write
Initial value →
→
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0) (0) (0) (0) (0) (0)
50
MB90210 Series
(2) Block Diagram
4
Interrupt/DTP enable register
4
4
4
Gate
Source F/F
Edge detection circuit
INT
Interrupt/DTP source register
8
Request level setting register
51
MB90210 Series
9. Watchdog Timer and Timebase Timer
The watchdog timer consists of a 2-bit watchdog counter using carry signals from an 18-bit timebase timer as
the clock source, a control register, and a watchdog reset control section. The timebase timer consists of an 18-
bit timer and an interval interrupt control circuit.
(1) Register Configuration
• Watchdog timer control register (WTC)
Watchdog timer control register
Bit
7
6
5
4
3
2
1
0
Address:
0000A8H
PONR
STBR
WRST
ERST
SRST
WTE
WT1
WT0
WTC
Read/write
Initial value
→
→
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
• Timebase timer control register (TBTC)
Timebase timer control register
Bit 15
14
13
12
11
10
9
8
Reserved
Address:
0000A9H
—
—
TBIE
TBOF
TBR
TBC1
TBC0
TBTC
Read/write
Initial value
→
→
(W)
(1)
(—)
(—)
(—)
(—)
(R/W) (R/W)
(0) (0)
(R)
(0)
(R/W) (R/W)
(0) (0)
52
MB90210 Series
(2) Block Diagram
Oscillation clock
Clock input
Timebase timer
TBTC
TBC1
212
214
216
218
Selector
TBC0
TBR
TBTRES
214 216 217 218
S
R
TBIE
Q
AND
TBOF
Timebase
interrupt
WTC
WT1
Watchdog
reset
generator
2-bit counter
WDGRST
Selector
OF
To internal reset generator
WT0
WTE
CLR
CLR
PONR
STBR
WRST
ERST
SRST
From power-on occurence
From hardware standby
control circuit
RST pin
From RST bit in STBYC
register
53
MB90210 Series
10. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate an interrupt for task switching. Using this module
allows an interrupt request to the F2MC-16F CPU to generate or cancel by software.
(1) Register Configuration
• Delayed interrupt source generate/release register (DIRR)
Delayed interrupt source generate/release register
Bit 15
—
14
13
12
11
10
9
8
Address:
00009FH
—
—
—
—
—
—
R0
DIRR
Read/write
Initial value
→
→
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R/W)
(0)
(2) Block Diagram
Delayed interrupt source
generate/release register
Source latch
54
MB90210 Series
11. Write-inhibit RAM
The write-inhibit RAM is write-protectable with the WI pin input. Maintaining the “L” level input to the WI pin
prevents a certain area of RAM from being written. The WI pin has a 4-machine-cycle filter.
(1) Register Configuration
• WI control register (WICR)
WI control register
Address:
Bit
7
6
5
4
3
2
1
0
00008EH
—
—
—
WI
—
—
—
—
WICR
Read/write
Initial value
→
→
(—)
(—)
(—)
(—)
(—)
(—)
(R/W)
(1)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(2) Write-inhibit RAM Area
Write-inhibit RAM area
001100H to 0011FFH (MB90214/P214A/P214B/W214A/W214B)
001100H to 0012FFH (MB90V210)
(3) Block Diagram
Access to other area
Write-inhibit
circuit
WR
Write-
inhibit
RAM
4-machine-cycle
skew removal
4-machine-cycle
skew removal
S
Q
S
R
Q
Select
Preceded
L
W I
R
RAM
decoder
H
Internal data bus
55
MB90210 Series
12. Low-power Consumption Modes, Oscillation Stabilization Delay Time, and Gear Function
The MB90210 series has three low-power consumption modes: the sleep mode, the stop mode, the hardware
standby mode, and gear function.
Sleep mode is used to suspend only the CPU operation clock; the other components remain in operation. Stop
mode and hardware standby mode stop oscillation, minimizing the power consumption while holding data.
The clock gear function divides the external clock frequency, which is used usually as it is, to provide a lower
machine clock frequency. This function can therefore lower the overall operation speed without changing the
oscillation frequency. The function can select the machine clock as a division of the frequency of crystal oscillation
or external clock input by 1, 2, 4, or 16.
The OSC1 and OSC0 bits can be used to set the oscillation stabilization delay time for wake-up from stop mode
or hardware standby mode.
(1) Register Configuration
• Standby control register (STBYC)
Standby control register
Address:
Bit
7
6
5
4
3
2
1
0
0000A0H
STP
SLP
SPL
RST
OSC1
OSC0
CLK1
CLK0
STBYC
Read/write
Initial value
→
→
(W)
(0)
(W)
(0)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (1) (*) (*) (*) (*)
Note: The initial value(*) of bit0 to bit3 is changed by reset source.
56
MB90210 Series
(2) Block Diagram
Oscillation clock
CPU clock
Gear divider circuit
1/1 1/2 1/4 1/16
CPU clock
generator
STBYC
CLK1
CLK0
Selector
Peripheral clock
Peripheral clock
generator
SLP
STP
Standby control circuit
RST Clear HST start
HST pin
Interrupt request
or RST
20
Clock input
216
217
218
OSC1
OSC0
Selector
Timebase timer
214 216 217 218
SPL
RST
Pin high-impedance control circuit
Internal reset generator
Pin HI–Z
RST pin
Internal RST
To watchdog timer
WDGRST
57
MB90210 Series
■ ELECTRICAL CHARACTERISTICS (MB90V210, deviceused forevaluation, is excluded)
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V)
Value
Pin
Symbol
Unit
Remarks
Parameter
name
Min.
Max.
Power supply voltage
Program voltage
VCC
VPP
VCC
VSS – 0.3
VSS + 7.0
V
V
MB90P214A/W214A
MB90P214B/W214B
VPP
VSS – 0.3
VSS – 0.3
VSS – 0.3
13.0
VCC + 0.3
AVCC
Power supply voltage
for A/D converter
AVCC
AVCC
V
V
Analog power supply voltage
AVRH
AVRL
AVRH
AVRL
Reference voltage for A/D
converter
*1
Input voltage
—
*2
*3
*3
*2
*2
—
VSS – 0.3
VSS – 0.3
—
VCC + 0.3
VCC + 0.3
20
V
V
VI
Output voltage
VO
“L” level output current
“L” level total output current
“H” level output current
“H” level total output current
Power consumption
IOL
mA Rush current
mA Total output current
mA Rush current
mA Total output current
mW
ΣIOL
IOH
—
50
—
–10
ΣIOH
Pd
—
–48
—
650
–40
–40
–55
+105
+85
°C MB90214/P214B/W214B
°C MB90P214A/W214A
°C
Operating temperature
Storage temperature
TA
—
—
Tstg
+150
*1: VI and VO must not exceed VCC + 0.3 V.
*2: Output pins
P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P75, P80 to P82
*3: Output pins
P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P75, P80 to P82
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
58
MB90210 Series
2. Recommended Operating Conditions
Pin
(VSS = AVSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
name
Min.
Max.
4.5
5.5
V
V
When operating
Power supply voltage
VCC
VCC
Retains the RAM state in stop
mode
3.0
4.5
5.5
Power supply voltage for A/D
converter
AVCC
AVCC
VCC + 0.3
V
Analog power supply
voltage
AVRH
AVRL
FC
AVRH
AVRL
—
AVRL
AVSS
10
AVCC
AVRH
16
V
V
Reference voltage for A/D
converter
Clock frequency
MHz
Single-chip mode
MB90214/P214B/W214B
–40
+105
°C
Operating temperature TA*
—
Single-chip mode
MB90P214A/W214A
–40
–40
+85
+70
°C
°C
External bus mode
* : Excluding the temperature rise due to the heat produced.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
59
MB90210 Series
3. DC Characteristics
Single-chip mode MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P214A/W214A
External bus mode
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Parameter
Symbol Pin name
Condition
Unit
Remarks
Min.
Typ.
—
Max.
VCC + 0.3
VCC + 0.3
VCC + 0.3
0.3 VCC
0.2 VCC
VSS+ 0.3
VIH
*1
—
—
—
—
—
—
0.7 VCC
0.8 VCC
VCC – 0.3
VSS– 0.3
VSS – 0.3
VSS – 0.3
V
V
V
V
V
V
CMOS level input
Hysteresis input
“H” level input
voltage
VIHS
VIHM
VIL
*2
—
MD0 to MD2
—
*1
—
CMOS level input
Hysteresis input
“L” level input
voltage
VILS
VILM
*2
—
MD0 to MD2
—
VCC = 4.5 V
IOH = –4.0 mA
VCC – 0.5
VOH
VOH1
VOL
*3
—
—
—
—
VCC
VCC
V
V
V
V
“H” level output
voltage
VCC = 4.5 V
IOH = –2.0 mA
VCC – 2.3
X1
*4
VCC = 4.5 V
IOL = 4.0 mA
0
0
0.4
“L” level output
voltage
VCC = 4.5 V
IOL = 2.0 mA
VCC – 2.3
VOL1
X1
Except pins with
pull-up/pull-down
resistor and RST
pin
VCC =5.5 V
0.2 VCC <VI <0.8
VCC
*1
*2
II
—
—
±10
µA
Input leakage
current
VCC =5.5 V
II2
X0
—
—
—
—
—
3
±25
7
µA
mA
µA
pF
0.2 VCC < VIH < 0.8 VCC
IA
FC = 16 MHz
Analog power
supply voltage
AVCC
In stop mode,
TA = +25°C
IAH
—
—
—
10
5*5
—
Input capacitance CIN
*6
7
*
MB90214
RST
—
22
50
110
kΩ MB90P214A/
W214A/P214B/
W214B
Pull-up resistor
RpuIU
7
*
MD1
—
—
—
—
110
22
300
50
650
110
650
110
kΩ
MB90214
7
*
Generic pin
MD0, MD2
Generic pin
kΩ
MB90214
7
*
110
22
300
50
kΩ
MB90214
Pull-down resistor RpuID
7
*
kΩ
MB90214
(Continued)
60
MB90210 Series
(Continued)
Parameter
Value
Typ.
50*8
Symbol Pin name
Condition
Unit
Remarks
Min.
Max.
—
80
mA MB90214
MB90P214A/
ICC
VCC
FC = 16 MHz
W214A
MB90P214B/
W214B
—
—
70*8
—
100
40
mA
Power supply
voltage*9
ICCS
VCC
VCC
FC = 16 MHz
—
mA In sleep mode
TA = +25°C
In stop mode
µA In hardware
standby input
time
ICCH
—
5
10
*1: CMOS level input (P00 to P07, P10 to P17, X0)
*2: Hysteresis input pins (RST, HST, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67 P70 to P75, P80
to P82)
*3: Output pins (P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P75, P80 to P82)
*4: Output pins (P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to
P75, P80 to P82)
*5: The current value applies to the CPU stop mode with A/D converter inactive (VCC = AVCC = AVRH = +5.5 V).
*6: Other than VCC, VSS, AVCC and AVSS
*7: A list of availabilities of pull-up/pull-down resistors
Pin name
MB90214
MB90P214A/W214A MB90P214B/W214B
Availability of pull-up resistors is
optionally defined.
Pull-up resistors
available
Pull-up resistors
available
RST
MD1
Pull-up resistors available
Unavailable
Unavailable
Unavailable
Unavailable
MD0, MD2
Pull-down resistors available
Availability of pull-up/pull-down
resistors is optionally defined.
Generic pin
Unavailable
Unavailable
*8: VCC = +5.0 V, VSS = 0.0 V, TA = +25°C, FC = 16 MHz
*9: Measurement condition of power supply current; external clock pin and output pin are open.
Measurement condition of VCC; see the table above mentioned.
61
MB90210 Series
2. AC Characteristics
(1) Clock Timing Standards
Single-chip mode MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P214A/W214A
External bus mode
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
name
Symbol
Condition
Unit
Remarks
Parameter
Min. Typ. Max.
Clock frequency
FC
tC
X0, X1
X0, X1
—
—
10
—
—
16
MHz
ns
Clock cycle time
62.5
100
1/FC
PWH
PWL
Input clock pulse width
X0
X0
—
—
0.4 tC
—
—
—
0.6 tC
8
ns Duty ratio: 60%
ns
tcr
tcf
Input clock rising/falling time
tcr + tcf
• Clock Input Timings
tC
0.7 VCC
0.7 VCC
0.3 VCC
X0
PWH
PWL
tcr
tcf
• Clock Conditions
When a crystal
or
When an external clock is used
ceramic resonator is used
X0
X1
X0
X1
Open
C1
C2
C1 = C2 = 10 pF
Select the optimum capacity value for the resonator.
62
MB90210 Series
• Relationship between Clock Frequency and Power Supply Voltage
V CC
Single-chip mode
[V]
: (TA = –40°C to +105°C, FC = 10 to 16 MHz)
(MB90214/P214B/W214B)
: (TA = –40°C to +85°C, FC = 10 to 16 MHz)
: (TA = –40°C to +70°C, FC = 10 to 16 MHz)
(MB90P214A/W214A)
External bus mode
5.5
Operation assurance range
4.5
FC
[MHz]
0
10
16
(2) Clock Output Timing Standards
Pin
External mode: (VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Symbol
Condition
Unit Remarks
Parameter
name
Min.
Typ.
Max.
Machine cycle time
tCYC
62.5
—
1600
ns
ns
*
Load condition:
80 pF
CLK
tCYC/
2 – 20
CLK ↑ → CLK↓
tCHCL
—
tCYC/2
* : tCYC = n/FC, n gear ratio (1, 2, 4, 16)
tCYC
tCHCL
CLK
1/2 VCC
1/2 VCC
63
MB90210 Series
(3) Recommended Resonator Manufacturers
• Sample Application of Piezoelectric Resonator (FAR Series)
X 0
X 1
FAR*1
*2
*2
C1
C2
*1: Fujitsu Acoustic Resonator
Temperature
characteristics of
FAR frequency
Initial deviation of
FAR frequency
(TA = +25°C)
FAR part number
(built-in capacitor type)
Load
Frequency
capacitance*2
(TA = –20°C to +60°C)
±0.5%
±0.5%
±0.5%
±0.5%
FAR-C4C F-1 6000- 02
FAR-C4C F-1 6000- 12
16.00
Built-in
Inquiry: FUJITSU LIMITED
(4) Reset and Hardware Standby Input Standards
Single-chip mode MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P214A/W214A
External bus mode
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
Symbol
Condition
Unit Remarks
Parameter
name
Min.
5 tCYC
5 tCYC
Typ.
—
Max.
—
Reset input time
tRSTL
RST
HST
ns
—
Hardware standby input time tHSTL
—
—
ns
*
* : The machine cycle (tCYC) at hardware standby input is set to 1/16 divided oscillation.
tRSTL, tHSTL
RST
HST
0.2 VCC
0.2 VCC
64
MB90210 Series
(5) Power on Supply Specifications (Power-on Reset)
Single-chip mode MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P214A/W214A
External bus mode
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
Symbol
Condition
Unit Remarks
Parameter
name
Min.
—
Typ.
—
Max.
30
Power supply rising time
Power supply cut-off time
tR
VCC
VCC
—
—
ms
ms
*
tOFF
1
—
—
* : Before the power rising, VCC must be less than +0.2 V.
Notes: • The above specifications are for the power-on reset.
• Always apply power-on reset using these specifications, regardless of whether or not
the power-on reset is needed.
• There are some internal registers (such as STBYC) which are only initialized by the power-on reset.
• Power-on Reset
tR
4.5 V
0.2 V
VCC
0.2 V
0.2 V
tOFF
Note: Caution on switching power supply
Abrupt change of supply voltage may initiate power-on reset, even if the above requirements are not met.
It is, therefore, recommended to power up gradually during the instantaneous change of power supply as
shown in the figure below.
• Changing Power Supply
Main power
supply voltage
The rising edge should be 50 mV/ms or less.
Subpower
supply voltage
VSS
65
MB90210 Series
(6) Bus Read Timing
(VCC = +4.5 to +5.5 , VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
Symbol
Condition
Unit Remarks
Parameter
name
Min.
tCYC/2 – 20
tCYC – 25
—
Max.
—
Valid address → RD ↓ time
RD pulse width
tAVRL
tRLRH
tRLDV
tRHDX
A23 to A00
RD
ns
ns
ns
ns
—
RD ↓ → valid data input
RD ↑ → data hold time
tCYC – 30
—
0
D15 to D00
Load
condition:
80 pF
Valid address→ valid data
tAVDV
tRHAX
tAVCH
tRLCL
—
3 tCYC/2 – 40 ns
input
RD ↑ → address valid time
Valid address → CLK ↑ time
RD ↓ → CLK ↓ time
A23 to A00
tCYC/2 – 20
tCYC/2 – 25
tCYC/2 – 25
—
—
—
ns
ns
ns
A23 to A00
CLK
RD, CLK
tAVCH
tRLCL
0.7 VCC
CLK
RD
0.3 VCC
tRLRH
tAVRL
0.7 VCC
tRHAX
0.3 VCC
0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
A23 to A00
D15 to D00
tRHDX
tRLDV
tAVDV
0.7 VCC
0.7 VCC
0.3 VCC
Read data
0.3 VCC
66
MB90210 Series
(7) Bus Write Timing
Parameter
(VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
—
Valid address → WR ↓ time tAVWL
A23 to A00
WRL, WRH
tCYC/2 – 20
tCYC – 25
ns
ns
WR ↓ pulse width
tWLWH
tDVWH
tWHDX
—
Valid data output → WR ↑
time
Load
condition:
80 pF
tCYC – 40
—
ns
D15 to D00
WR ↑ → data hold time
tCYC/2 – 20
tCYC/2 – 20
tCYC/2 – 25
—
—
—
ns
ns
ns
WR ↑ → address valid time tWHAX
A23 to A00
WR ↓ → CLK ↓ time
tWLCH
WRL, WRH, CLK
tWLCL
0.3 VCC
CLK
WR
tWLWH
0.7 VCC
tWHAX
0.3 VCC
(WRL, WRH)
tAVWL
0.7 VCC
0.3 VCC
A23 to A00
D15 to D00
tWHDX
tDVWH
Write data
0.7 VCC
0.3 VCC
Un-
defined
67
MB90210 Series
(8) Ready Signal Input Timing
(VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Symbol Pin name
Condition
Unit
Remarks
Parameter
Min.
40
Max.
—
RDY setup time
RDY hold time
tRYHS
tRYHH
ns
ns
Load condition:
80 pF
RDY
0
—
Note: Use the auto-ready function if the RDY setup time is insufficient.
0.7 VCC
0.7 VCC
CLK
A23 to A00
RD/WR
(WRL, WRH)
tRYHS
tRYHH
tRYHS
tRYHH
RDY
No wait
0.8 VCC
0.8 VCC
Wait
0.8 VCC
0.8 VCC
0.2 VCC
(9) Hold Timing
Parameter
(VCC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin
Symbol
Condition
Unit
Remarks
name
Min.
30
Max.
tCYC
Pin floating → HAK ↓ time
HAK ↑ → pin valid time
tXHAL
tHAHV
ns
ns
Load condition:
80 pF
HAK
tCYC
2tCYC
Note: It takes at least one cycle for HAK to vary after HRQ is fetched.
HRQ
0.8 VCC
0.2 VCC
0.7 VCC
0.3 VCC
HAK
tXHAL
tHAHV
Each pin
High impedance
68
MB90210 Series
(10) UART Timing
Single-chip mode MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P214A/W214A
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
External bus mode
Value
Pin
name
Symbol
Condition
Unit
Remarks
Parameter
Min.
Max.
Serial clock cycle time tSCYC
8 tCYC
—
ns
ns
ns
ns
SCLK ↓ → SOUT
tSLOV
–80
100
60
80
—
—
Internal shift
clock mode
output pin
delay time
Valid SIN → SCLK ↑
tIVSH
tSHIX
SCLK ↑ → Valid SIN
hold time
Serial clock “H” pulse
width
tSHSL
tSLSH
Load condition:
80 pF
4 tCYC
4 tCYC
—
—
ns
ns
—
Serial clock “L” pulse
width
External shift
clock mode
output pin
SCLK ↓ → SOUT
delay time
tSLOV
tIVSH
tSHIX
—
60
60
150
—
ns
ns
ns
Valid SIN → SCLK ↑
SCLK ↑ → Valid SIN
hold time
—
Notes: • These AC characteristics assume the CLK synchronous mode.
• tCYC is the machine cycle (unit: ns).
69
MB90210 Series
• Internal Shift Clock Mode
tSCYC
0.7 VCC
SCK
0.3 VCC
0.3 VCC
tSLOV
0.7 VCC
0.3 VCC
SOD
SID
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• External Shift Clock Mode
tSLSH
tSHSL
0.8 VCC
SCK
0.2 VCC
0.2 VCC
0.2 VCC
tSLOV
0.7 VCC
0.3 VCC
SOD
SID
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
70
MB90210 Series
(11) Resource Input Timing
Single-chip mode MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P214A/W214A
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
External bus mode
Value
Symbol
Pin name
Condition
Unit
Remarks
Parameter
Min.
Typ.
Max.
External event
count input mode
4 tCYC
—
—
TIN0 to TIN3
TIN4 to TIN7
ns
Trigger input/
Gate input mode
2 tCYC
—
—
tTIWH
tTIWL
Load
condition:
2 tCYC
2 tCYC
3 tCYC
2 tCYC
4 tCYC
—
—
—
—
—
—
—
—
—
—
ns Gate input mode
Input pulse width
PWC0 to PWC3 80 pF
ns
ns
ns
ns
INT0 to INT3
ATG
WI
tWIWL
0.8 VCC
0.8 VCC
0.2 VCC
TIN0 to TIN7
PWC0 to PWC3
INT0 to INT3
WI
0.2 VCC
tTIWH
tTIWL, tWIWL
(12) Resource Output Timing
Single-chip mode MB90214/P214B/W214B : (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +105°C)
MB90P214A/W214A
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
: (VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)
External bus mode
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min. Max.
TOUT0 to TOUT3
PPG
POUT0 to POUT3
CLK ↑ →
TOUT transition time
Load condition:
80 pF
tTO
—
30
ns
0.7 VCC
CLK
TOUT0 to TOUT3
PPG
POUT0 to POUT3
0.7 VCC
0.3VCC
tTO
71
MB90210 Series
5. A/D Converter Electrical Characteristics
Single-chip mode MB90214/P214B/W214B:
≤
(AVCC = VCC = +5.0±10%, AVSS = VSS = 0.0 V, TA = –40°C to +105°C, +4.5 V
AVRH – AVRL)
Single-chip mode MBP90214A/W214A:
≤
≤
(AVCC = VCC = +5.0±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C, +4.5 V
External bus mode:
AVRH – AVRL)
AVRH – AVRL)
(AVCC = VCC = +5.0±10%, AVSS = VSS = 0.0 V, TA = –40°C to +70°C, +4.5 V
Value
Unit
Symbol Pin name
Condition
Remarks
Parameter
Resolution
Min.
—
Typ.
—
Max.
10
n
—
—
—
—
—
—
bit
Total error
—
—
–3.0
–2.0
—
+3.0
+2.0
LSB
LSB
Linearity error
—
Differential
linearity error
—
VOT
—
—
—
—
—
—
±1.5
LSB
LSB
Zero transition
voltage
AVRL – 1.5 AVRL + 0.5 AVRL + 2.5
AN0 to AN7
Full-scale
transition voltage
VFST
TCONV
TSAMP
IAIN
AVRH – 3.5 AVRH – 1.5 AVRH + 0.5 LSB
98 machine
cycles
Conversion time
—
—
—
—
—
—
6.125
3.75
—
—
—
µs
µs
µA
V
tCYC = 62.5 ns
60 machine
cycles
Sampling period
Analog port input
current
—
—
±0.1
AVRH
AN0 to AN7
Analog input
voltage
VAIN
AVRL
AVRH
AVRL
—
—
—
—
AVRL
AVSS
—
—
—
AVCC
AVRH
500
V
V
Analog reference
voltage
—
IR
200
—
µA
µA
Reference voltage
supply current
AVRH
IRH
—
5*
Interchannel
disparity
—
AN0 to AN7
—
—
—
4
LSB
* : The current value applies to the CPU stop mode with the A/D converter inactive (VCC = AVCC = AVRH = +5.5 V).
Notes: (1) The smaller the | AVRH – AVRL |, the greater the error would become relatively.
(2) Use the output impedance of the external circuit for analog input under the following conditions:
.
=
External circuit output impedance < approx. 10 kΩ (Sampling period 3.75 µs, tCYC = 62.5 ns)
.
(3) Precision values are standard values applicable to sleep mode.
(4) If VCC/AVCC or VSS/AVSS is caused by a noise to drop to below the analog input voltage, the analog input
current is likely to increase. In such cases, a bypasscapacitoror the like should be provided in the external
circuit to suppress the noise.
72
MB90210 Series
• Equivalent Circuit of Analog Input Circuit
C0
Analog input
Comparator
R ON2
R ON1
External impedance
RON1: Approx. 1.5 kΩ
C1
RON2: Approx. 1.5 kΩ
C0: Approx. 60 pF
C1: Approx. 4 pF
Note: The values shown here are reference values.
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
Total error: Difference between actual and logical values. This error is caused by a zero transition error,
full-scale transition error, linearity error, differential linearity error, or by noise.
Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00
0000 0001”) with the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual
conversion characteristics
Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value.
Digital output
11 1111 1111
11 1111 1110
11 1111 1101
•
Theoretical value V NT
Theoretical value
Actual conversion value
•
•
•
Total error
N + 1
N
N – 1
•
•
•
•
Linerity error
N × 1LSB + V 0T
00 0000 0010
00 0000 0001
00 0000 0000
AVRL
V NT
V(N–1)T
AVRH (V)
V FST
V 0T V 1T
V 2T
V(N+1)T
AVRH – AVRL
1022
VFST – V0T
1022
•
•
•
1LSB theoretical value
=
1LSB =
N = 0 to 1022
VNT (N = 0) = V0T
VNT (N = 1022) = VFST
VNT– (N × 1LSB + V0T)
Linearity error =
1LSB
VNT – V(N – 1) T
•
•
Differential linearity error
=
N = 1 to 1022
– 1
1LSB
VNT – { ( N + 0.5 ) × 1LSB theoretical value }
=
Total error
N = 0 to 1022
1LSB theoretical value
73
MB90210 Series
■ EXAMPLE CHARACTERISTICS
(1) Power Supply Current
I CC vs. T A example characteristics
I CCH vs. T A example characteristics
I CCH (µA)
I CC (mA)
100
40
30
20
10
0
F C = 16 MHz
External clock input
V CC = 5.5 V
V CC = 5.5 V
90
80
70
MB90P214A
60
MB90214
50
–10
40
–50
0
50
100
150
–50
0
50
100
150
T A (°C)
T A (°C)
Note: These are not assured value of characteristics but example characteristics.
(2) Output Voltage
V OL vs. I OL example characteristics
V OL (V)
V OH vs. I OH example characteristics
V OH (V)
5.5
2.0
T A = +25°C
V CC = 5.0 V
T A = +25°C
V CC = 5.0 V
1.5
5.0
4.5
4.0
3.5
1.0
0.5
0.0
–0.5
3.0
–15
–10
–5
0
5
–5
0
5
10
15
20
25
I OH (mA)
I OL (mA)
Note: These are not assured value of characteristics but example characteristics.
74
MB90210 Series
(3) Pull-up/Pull-down Resistor
Pull-down resistor example characteristics
Pull-up resistor example characteristics
R pul U (kΩ)
R pul D (kΩ)
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
V CC = 4.5 V
V CC = 5.0 V
V CC = 5.5 V
V CC = 4.5 V
V CC = 5.0 V
V CC = 5.5 V
20
–50
0
50
100
150
–50
0
50
100
150
T A (°C)
T A (°C)
Pull-up resistor example characteristics
Pull-down resistor example characteristics
R pul D (kΩ)
R pul U (kΩ)
500
400
300
200
100
500
V CC = 5.5 V
400
300
200
V CC = 5.5 V
100
–50
0
50
100
150
–50
0
50
100
150
T A (°C)
T A (°C)
Note: These are not assured value of characteristics but example characteristics.
(4) Analog Filter
Analog filter example characteristics
Input pulse width (ns)
80
T A = +25°C
70
60
50
40
30
20
10
Filtering enable
4.0
4.5
5.0
5.5
6.0
V CC (V)
Note: These are not assured value of characteristics but example characteristics.
75
MB90210 Series
■ INSTRUCTIONS (421 INSTRUCTIONS)
Table 1 Description of Items in Instruction List
Item
Description
Mnemonic
English upper case and symbol: Described directly in assembler code.
English lower case: Converted in assembler code.
Number of letters after English lower case: Describes bit width in code.
#
~
Describes number of bytes.
Describes number of cycles.
For other letters in other items, refer to table 4.
B
Describes correction value for calculating number of actual states.
Number of actual states is calculated by adding value in the ~section.
Operation
LH
Describes operation of instructions.
Describes a special operation to 15 bits to 08 bits of the accumulator.
Z : Transfer 0.
X : Sign-extend and transfer.
– : No transmission
AH
Describes a special operation to the upper 16-bit of the accumulator.
* : Transmit from AL to AH.
– : No transfer.
Z : Transfer 00H to AH.
X : Sign-extend AL and transfer 00H or FFH to AH.
I
S
Describes status of I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero),
V (overflow), and C (carry) flags.
* : Changes after execution of instruction.
– : No changes.
S : Set after execution of instruction.
R: Reset after execution of instruction.
T
N
Z
V
C
RMW
Describes whether or not the instruction is a read-modify-write type (a data is read out from
memory etc. in single cycle, and the result is written into memory etc.).
* : Read-modify-write instruction
– : Not read-modify-write instruction
Note: Not used to addresses having different functions for reading and writing operations.
76
MB90210 Series
Table 2 Description of Symbols in Instruction Table
Description
Item
A
32-bit accumlator
The bit length is dependent on the instructions to be used.
Byte : Lower 8-bit of AL
Word :16-bit of AL
Long : AL: 32-bit of AH
AH
AL
Upper 16-bit of A
Lower 16-bit of A
SP
Stack pointer (USP or SSP)
Program counter
PC
SPCU
SPCL
PCB
DTB
ADB
SSB
USB
SPB
DPR
brg1
brg2
Ri
Stack pointer upper limited register
Stack pointer lower limited register
Program bank register
Data bank register
Additional data bank register
System stack bank register
User stack bank register
Current stack bank register (SSB or USB)
Direct page register
DTB, ADB, SSB, USB, DPR, PCB
DTB, ADB, SSB, USB, DPR
R0, R1, R2, R3, R4, R5, R6, R7
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RW0, RW1, RW2, RW3
RWi
RWj
RLi
RL0, RL1, RL2, RL3
dir
addr16
Specify shortened direct address.
Specify direct address.
addr24
ad24 0 to 15
ad24 16 to 23
Specify physical direct address.
bit0 to bit15 of addr24
bit16 to bit 23 of addr24
io
I/O area (000000H to 0000FFH)
#imm4
#imm8
#imm16
#imm32
ext (imm8)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data calculated by sign-extending an 8-bit immediate data
disp8
disp16
8-bit displacement
16-bit displacement
bp
Bit offset value
vct4
vct8
Vector number (0 to 15)
Vector number (0 to 255)
( )b
Bit address
rel
ear
eam
Specify PC relative branch.
Specify effective address (code 00 to 07).
Specify effective address (code 08 to 1F).
rlst
Register allocation
77
MB90210 Series
Table 3 Effective Address Field
Address type
Number of bytes in address
extension block*
Code
Symbol
00
01
02
03
04
05
06
07
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
RL0 Register direct
(RL0) "ea" corresponds to byte, word, and
RL1 long word from left respectively.
(RL1)
RL2
(RL2)
RL3
(RL3)
—
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
Register indirect
0
0
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post increment
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
1
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacement
2
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
0
0
2
2
Note: Number of bytes for address extension corresponds to “+” in the # (number of bytes) part in the instruction
table.
78
MB90210 Series
Table 4 Number of Execution Cycles in Addressing Modes
(a)*
Code
Operand
Number of execution cycles for addressing modes
Ri
RWi
RLi
00 to 07
Listed in instruction table
08 to 0B
0C to 0F
10 to 17
18 to 1B
@RWj
1
4
1
1
@RWj +
@RWi + disp8
@RWj + disp16
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
2
2
2
1
Note: (a) is used for ~ (number of cycles) and B (correction value) in instruction table.
Table 5 Correction Value for Number of Cycles for Calculating Actual Number of Cycles
(b)*
byte
+0
(c)*
word
+0
(d)*
long
+0
Operand
Internal register
Internal RAM even address
Internal RAM odd address
+0
+0
+0
+1
+0
+2
Other than internal RAM even address
Other than internal RAM odd address
+1
+1
+1
+3
+2
+6
External data bus 8-bit
+1
+3
+6
Notes: (b), (c), (d) is used for ~ (number of cycles) and B (correction value) in instruction table.
79
MB90210 Series
Table 6 Transmission Instruction (Byte) [50 Instructions]
LH AH
Mnemonic
#
~
B
Operation
I
S
T
N
Z
V
C RMW
MOV A, dir
2
3
1
2
2
2
1
1
(b) byte (A) ← (dir)
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
*
*
*
*
*
*
*
–
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV A, addr16
MOV A, Ri
(b) byte (A) ← (addr16)
0
0
byte (A) ← (Ri)
byte (A) ← (ear)
MOV A, ear
MOV A, eam
2 + 2 + (a) (b) byte (A) ← (eam)
MOV A, io
2
2
2
3
3
5
2
1
2
2
2
6
3
3
2
1
(b) byte (A) ← (io)
byte (A) ← imm8
MOV A, #imm8
MOV A, @A
0
(b) byte (A) ← ((A))
byte (A) ← ((RLi) + disp8)
byte (A) ← ((SP) + disp8)
MOV A, @RLi + disp8
MOV A, @SP + disp8
MOVP A, addr24
MOVP A, @A
(b)
(b)
(b) byte (A) ← (addr24)
(b) byte (A) ← ((A))
MOVN A, #imm4
0
byte (A) ← imm4
MOVX A, dir
2
3
2
2
2
2
1
1
(b) byte (A) ← (dir)
X
X
X
X
X
X
X
X
X
*
*
*
*
*
*
*
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVX A, addr16
MOVX A, Ri
(b) byte (A) ← (addr16)
0
0
byte (A) ← (Ri)
byte (A) ← (ear)
MOVX A, ear
MOVX A, eam
2 + 2 + (a) (b) byte (A) ← (eam)
MOVX A, io
2
2
2
2
3
3
5
2
2
2
2
3
6
3
3
2
(b) byte (A) ← (io)
byte (A) ← imm8
(b) byte (A) ← ((A))
byte (A) ← ((RWi) + disp8)
(b)
MOVX A, #imm8
MOVX A, @A
0
MOVX A, @RWi + disp8
MOVX A, @RLi + disp8
MOVX A, @SP + disp8
MOVPX A, addr24
MOVPX A, @A
(b) byte (A) ← ((RLi) + disp8) X
byte (A) ← ((SP) + disp8)
(b) byte (A) ← (addr24)
(b) byte (A) ← ((A))
(b)
X
X
X
MOV dir, A
2
3
1
2
2
2
1
2
(b) byte (dir) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV addr16, A
MOV Ri, A
(b) byte (addr16) ← (A)
0
0
byte (Ri) ← (A)
byte (ear) ← (A)
MOV ear, A
MOV eam, A
2 + 2 + (a) (b) byte (eam) ← (A)
MOV io, A
2
3
3
5
2
6
3
3
(b) byte (io) ← (A)
(b)
(b)
byte ((RLi) + disp8) ← (A)
byte ((SP) + disp8) ← (A)
MOV @RLi + disp8, A
MOV @SP + disp8, A
MOVP addr24, A
(b) byte (addr24) ← (A)
MOV Ri, ear
2
2
0
byte (Ri) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV Ri, eam
MOVP @A, Ri
2 + 3 + (a) (b) byte (Ri) ← (eam)
2
2
3
3
(b) byte ((A)) ← (Ri)
byte (ear) ← (Ri)
*
*
MOV ear, Ri
0
*
*
MOV eam, Ri
MOV Ri, #imm8
MOV io, #imm8
MOV dir, #imm8
MOV ear, #imm8
MOV eam, #imm8
2 + 3 + (a) (b) byte (eam) ← (Ri)
*
*
2
3
3
3
2
3
3
2
0
byte (Ri) ← imm8
*
*
(b) byte (io) ← imm8
(b) byte (dir) ← imm8
–
–
*
–
–
*
0
byte (ear) ← imm8
3 + 2 + (a) (b) byte (eam) ← imm8
–
–
MOV @AL, AH
2
2
2
3
(b) byte ((A)) ← (AH)
byte (A) ↔ (ear)
–
–
–
–
–
*
*
–
–
–
XCH A, ear
XCH A, eam
XCH Ri, ear
XCH Ri, eam
0
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2 + 3 + (a) 2 × (b) byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
2 + 5 + (a) 2 × (b) byte (Ri) ↔ (eam)
2
4
0
Note: For (a) and (b), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
80
MB90210 Series
Table 7 Transmission Instruction (Word) [40 Instructions]
LH AH
Mnemonic
MOVW A, dir
MOVW A, addr16
MOVW A, SP
MOVW A, RWi
MOVW A, ear
MOVW A, eam
MOVW A, io
MOVW A, @A
MOVW A, #imm16
MOVW A, @RWi + disp8
MOVW A, @RLi + disp8
MOVW A, @SP + disp8
MOVPW A, addr24
MOVPW A, @A
#
~
B
Operation
I
S
T
N
Z
V
C RMW
2
3
1
1
2
2
2
2
1
1
(c) word (A) ← (dir)
(c) word (A) ← (addr16)
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
–
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
2 + 2 + (a) (c) word (A) ← (eam)
2
2
3
2
3
3
5
2
2
2
2
3
6
3
3
2
(c) word (A) ← (io)
(c) word (A) ← ((A))
0
(c)
(c)
(c)
word (A) ← imm16
word (A) ← ((RWi) +disp8)
word (A) ← ((RLi) +disp8)
word (A) ← ((SP) + disp8)
(c) word (A) ← (addr24)
(c) word (A) ← ((A))
MOVW dir, A
2
3
4
1
1
2
2
2
2
2
1
2
(c) word (dir) ← (A)
(c) word (addr16) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVW addr16, A
MOVW SP, #imm16
MOVW SP, A
MOVW RWi, A
MOVW ear, A
MOVW eam, A
MOVW io, A
MOVW @RWi + disp8, A
MOVW @RLi + disp8, A
MOVW @SP + disp8, A
MOVPW addr24, A
MOVPW @A, RWi
MOVW RWi, ear
MOVW RWi, eam
MOVW ear, RWi
MOVW eam, RWi
MOVW RWi, #imm16
MOVW io, #imm16
MOVW ear, #imm16
MOVW eam, #imm16
0
0
0
0
word (SP) ← imm16
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
2 + 2 + (a) (c) word (eam) ← (A)
2
2
3
3
5
2
2
2
3
6
3
3
3
2
(c) word (io) ← (A)
word ((RWi) +disp8) ← (A)
word ((RLi) +disp8) ← (A)
word ((SP) + disp8) ← (A)
(c)
(c)
(c)
(c) word (addr24) ← (A)
(c) word ((A)) ← (RWi)
0
word (RWi) ← (ear)
2 + 3 + (a) (c) word (RWi) ← (eam)
word (ear) ← (RWi)
2 + 3 + (a) (c) word (eam) ← (RWi)
2
3
0
3
4
4
2
3
2
0
word (RWi) ← imm16
(c) word (io) ← imm16
word (ear) ← imm16
0
4 + 2 + (a) (c) word (eam) ← imm16
MOVW @AL, AH
2
2
2
3
(c) word ((A)) ← (AH)
word (A) ↔ (ear)
–
–
–
–
–
*
*
–
–
–
XCHW A, ear
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
XCHW A, eam
XCHW RWi, ear
XCHW RWi, eam
2 + 3 + (a) 2 × (c) word (A) ↔ (eam)
word (RWi) ↔ (ear)
2 + 5 + (a) 2 × (c) word (RWi) ↔ (eam)
2
4
0
Note: For (a) and (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
81
MB90210 Series
Table 8 Transmission Instruction (Long) [11 Instructions]
LH AH
Mnemonic
MOVL A, ear
MOVL A, eam
MOVL A, #imm32
MOVL A, @SP + disp8
MOVPL A, addr24
MOVPL A, @A
#
2
2 +
5
3
5
~
2
B
0
Operation
long (A) ← (ear)
I
S
–
–
–
–
–
–
T
–
–
–
–
–
–
N
*
*
*
*
Z
*
*
*
*
*
*
V
–
–
–
–
–
–
C RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3 + (a)
(d) long (A) ← (eam)
long (A) ← imm32
3
4
4
3
0
(d) long (A) ← ((SP) + disp8)
(d) long (A) ← (addr24)
(d) long (A) ← ((A))
*
*
2
MOVPL @A, RLi
2
5
(d) long ((A)) ← (RLi)
–
–
–
–
–
*
*
–
–
–
MOVL @SP + disp8, A
MOVPL addr24, A
MOVL ear, A
3
5
2
4
4
2
(d) long ((SP) + disp8) ← (A)
(d) long (addr24) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
0
long (ear) ← (A)
MOVL eam, A
2 + 3 + (a) (d) long (eam) ← (A)
Note: For (a) and (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
82
MB90210 Series
Table 9 Add/Subtract (Byte, Word, Long) [42 Instructions]
LH AH
Mnemonic
ADD A,#imm8
#
~
B
Operation
I
S
T
N
Z
V
C RMW
2
2
2
2
3
2
0
byte (A) ← (A) +imm8
Z
Z
Z
Z
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
–
Z
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
ADD
ADD
ADD
ADD
ADD
ADDC
A, dir
A, ear
A, eam
ear, A
eam, A
A
(b) byte (A) ← (A) +(dir)
byte (A) ← (A) +(ear)
0
2 + 3 + (a) (b) byte (A) ← (A) +(eam)
byte (ear) ← (ear) + (A)
2 + 3 + (a) 2 × (b) byte (eam) ← (eam) + (A)
2
2
0
*
1
2
2
2
0
0
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear) + (C)
–
–
–
–
–
–
–
–
*
ADDC A, ear
ADDC A, eam
ADDDC A
2 + 3 + (a) (b) byte (A) ← (A) + (eam) + (C)
byte (A) ← (AH) + (AL) + (C) (decimal)
1
2
2
2
3
2
3
2
0
0
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
A, #imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
byte (A) ← (A) – imm8
(b) byte (A) ← (A) – (dir)
byte (A) ← (A) – (ear)
0
2 + 3 + (a) (b) byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
2 + 3 + (a) 2 × (b) byte (eam) ← (eam) – (A)
2
2
0
*
1
2
2
2
0
0
byte (A) ← (AH) – (AL) – (C)
byte (A) ← (A) – (ear) – (C)
–
–
–
–
SUBC A, ear
SUBC A, eam
SUBDC A
2 + 3 + (a) (b) byte (A) ← (A) – (eam) – (C)
1
byte (A) ← (AH) – (AL) – (C) (decimal)
3
0
ADDW
A
1
2
2
2
0
0
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
2 + 3 + (a) (c) word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) – (ear) + (A)
2 + 3 + (a) 2 × (c) word (eam) – (eam) + (A)
word (A) ← (A) + (ear) + (C)
2 + 3 + (a) (c) word (A) ← (A) + (eam) + (C)
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
2 + 3 + (a) (c) word (A) ← (A) – (eam)
word (A) ← (A) – imm16
word (ear) ← (ear) – (A)
2 + 3 + (a) 2 × (c) word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
2 + 3 + (a) (c) word (A) ← (A) – (eam) – (C)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
ADDW A, ear
ADDW A, eam
ADDW A, #imm16
ADDW ear, A
ADDW eam, A
ADDCW A, ear
ADDCW A, eam
3
2
2
2
0
0
*
2
2
0
–
–
–
–
–
–
*
*
–
–
1
2
2
2
0
0
SUBW
A
SUBW A, ear
SUBW A, eam
SUBW A, #imm16
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam
3
2
2
2
0
0
2
2
0
ADDL A, ear
ADDL A, eam
ADDL A, #imm32
SUBL A, ear
SUBL A, eam
SUBL A, #imm32
2
5
0
long (A) ← (A) + (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
2 + 6 + (a) (d) long (A) ← (A) + (eam)
5
2
4
5
0
0
long (A) ← (A) + imm32
long (A) ← (A) – (ear)
2 + 6 + (a) (d) long (A) ← (A) – (eam)
long (A) ← (A) – imm32
5
4
0
Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
83
MB90210 Series
Table 10 Increment/Decrement (Byte, Word, Long) [12 Instructions]
LH AH
Mnemonic
#
~
B
Operation
I
S
T
N
Z
V
C RMW
INC
INC
ear
eam
2
2
0
byte (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
2 + 3 + (a) 2 × (b) byte (eam) ← (eam) +1
DEC
DEC
ear
eam
2
2
0
byte (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
2 + 3 + (a) 2 × (b) byte (eam) ← (eam) –1
INCW ear
INCW eam
2
2
0
word (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
2 + 3 + (a) 2 × (c) word (eam) ← (eam) +1
DECW ear
DECW eam
2
2
0
word (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
*
*
*
*
2 + 3 + (a) 2 × (c) word (eam) ← (eam) –1
long (ear) ← (ear) +1
INCL
INCL
ear
eam
2
4
0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2 + 5 + (a) 2 × (d) long (eam) ← (eam) +1
DECL ear
DECL eam
2
4
0
long (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
2 + 5 + (a) 2 × (d) long (eam) ← (eam) –1
Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
Table 11 Compare (Byte, Word, Long) [11 Instructions]
LH AH
Mnemonic
#
~
B
Operation
I
S
T
N
Z
V
C RMW
CMP
CMP
CMP
CMP
A
1
2
1
2
0
0
byte (AH) – (AL)
byte (A) – (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
A, ear
A, eam
A, #imm8
2 + 3 + (a) (b) byte (A) – (eam)
2
2
0
byte (A) – imm8
CMPW A
1
2
1
2
0
0
word (AH) – (AL)
word (A) – (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW A, ear
CMPW A, eam
CMPW A, #imm16
2 + 3 + (a) (c) word (A) – (eam)
3
2
0
word (A) – imm16
CMPL A, ear
CMPL A, eam
CMPL A, #imm32
2
6
0
word (A) – (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
2 + 7 + (a) (d) word (A) – (eam)
word (A) – imm32
5
3
0
Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
84
MB90210 Series
Table 12 Unsigned Multiply/Division (Word, Long) [11 Instructions]
LH AH
Mnemonic
#
~
B
Operation
I
S
T
N
Z
V
C RMW
DIVU
A
1
*1
0
word (AH) /byte (AL)
Quotient → byte (AL)
Remainder → byte (AH)
word (A)/byte (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
DIVU
DIVU
A, ear
A, eam
2
*2
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
Quotient → byte (A)
Remainder → byte (ear)
2 + *3 *6 word (A)/byte (eam)
Quotient → byte (A)
Remainder → byte (eam)
long (A)/word (ear)
DIVUW A, ear
DIVUW A, eam
2
*4
0
Quotient → word (A)
Remainder → word (ear)
2+ *5 *7 long (A)/word (eam)
Quotient → word (A)
Remainder → word (eam)
MULU
MULU
MULU
MULUW A
MULUW A, ear
MULUW A, eam
A
1
2
*8
*9
0
0
byte (AH) byte (AL) → word (A)
byte (A) byte (ear) → word (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A, ear
A, eam
2 + *10 (b) byte (A) byte (eam) → word (A)
1
2
*11
*12
0
0
word (AH) word (AL) → long (A)
word (A) word (ear) → long (A)
2 + *13 (c) word (A) word (eam) → long (A)
Note: For (b) and (c), refer to “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of
Cycles.”
*1: Set to 3 when the division-by-0, 6 for an overflow, and 14 for normal operation.
*2: Set to 3 when the division-by-0, 6 for an overflow, and 13 for normal operation.
*3: Set to 5 + (a) when the division-by-0, 7 + (a) for an overflow, and 17 + (a) for normal operation.
*4: Set to 3 when the division-by-0, 5 for an overflow, and 21 for normal operation.
*5: Set to 4 + (a) when the division-by-0, 7 + (a) for an overflow, and 25 + (a) for normal operation.
*6: When the division-by-0, (b) for an overflow, and 2 × (b) for normal operation.
*7: When the division-by-0, (c) for an overflow, and 2 × (c) for normal operation.
*8: Set to 3 when byte (AH) is zero, 7 when byte (AH) is not zero.
*9: Set to 3 when byte (ear) is zero, 7 when byte (ear) is not zero.
*10:Set to 4 + (a) when byte (eam) is zero, 8 + (a) when byte (eam) is not zero.
*11:Set to 3 when word (AH) is zero, 11 when word (AH) is not zero.
*12:Set to 4 when word (ear) is zero, 11 when word (ear) is not zero.
*13:Set to 4 + (a) when word (eam) is zero, 12 + (a) when word (eam) is not zero.
85
MB90210 Series
Table 13 Signed multiplication/division (Word, Long) [11 Instructions]
LH AH
Mnemonic
#
~
B
Operation
I
S
T
N
Z
V
C RMW
DIV
DIV
DIV
A
2
*1
0
word (AH)/byte (AL)
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
Quotient → byte (AL)
Remainder → byte (AH)
word (A)/byte (ear)
A, ear
2
*2
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
Quotient → byte (A)
Remainder → byte (ear)
A, eam
2 + *3 *6 word (A)/byte (eam)
Quotient → byte (A)
Remainder → byte (eam)
long (A)/word (ear)
DIVW A, ear
DIVW A, eam
2
*4
0
Quotient → word (A)
Remainder → word (ear)
2 + *5 *7 long (A)/word (eam)
Quotient → word (A)
Remainder → word (eam)
MUL
MUL
MUL
MULW
MULW A, ear
MULW A, eam
A
2
2
*8
*9
0
0
byte (AH) × byte (AL) → word (A) –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A, ear
A, eam
A
byte (A) × byte (ear) → word (A)
byte (A) × byte (eam) → word (A)
word (AH) × word (AL) → long (A)
word (A) × word (ear) → long (A)
–
–
–
–
–
2 + *10 (b)
2
2
*11
*12
0
0
2 + *13 (b) word (A) × word (eam) → long (A)
For (b) and (c), refer to “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1: Set to 3 for divide-by-0, 8 or 18 for an overflow, and 18 for normal operation.
*2: Set to 3 for divide-by-0, 10 or 21 for an overflow, and 22 for normal operation.
*3: Set to 4 + (a) for divide-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation.
*4: Positive divided: Set to 4 for divide-by-0, 10 or 29 for an overflow, and 30 for normal operation.
Negative divided: Set to 4 for divide-by-0, 11 or 30 for an overflow, and 31 for normal operation.
*5: Positive divided: Set to 4 + (a) fordivide-by-0, 11 + (a) or 30 + (a)for an overflow, and 31 + (a) for normaloperation.
Negative divided: Set to 4 + (a) for divide-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal
operation.
*6: Set to (b) when the division-by-0 or an overflow, and 2 × (b) for normal operation.
*7: Set to (c) when the division-by-0 or an overflow, and 2 × (c) for normal operation.
*8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
*10:Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative.
*11:Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*12:Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
*13:Set to 4 +(a)when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result isnegative.
Note: When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two
values because of detection before and after an operation.
When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed.
86
MB90210 Series
Table 14 Logic 1 (Byte, Word) [39 Instructions]
LH AH
Mnemonic
#
~
B
Operation
I
S
T
N
Z
V
C RMW
AND
AND
AND
AND
AND
A, #imm8
A, ear
A, eam
ear, A
2
2
2
2
0
0
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
*
2 + 3 + (a) (b) byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
2
3
0
eam, A
2 + 3 + (a) 2 × (b) byte (eam) ← (eam) and (A) –
*
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
2
2
2
2
0
0
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
*
2 + 3 + (a) (b) byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
2 + 3 + (a) 2 × (b) byte (eam) ← (eam) or (A)
2
3
0
eam, A
*
XOR A, #imm8
XOR A, ear
XOR A, eam
XOR ear, A
XOR eam, A
2
2
2
2
0
0
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
2 + 3 + (a) (b) byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
2
3
0
2 + 3 + (a) 2 × (b) byte (eam) ← (eam) xor (A) –
1
2
NOT
NOT
NOT
A
ear
eam
2
2
0
0
byte (A) ← not (A)
byte (ear) ← not (ear)
–
–
–
2 + 3 + (a) 2 × (b) byte (eam) ← not (eam)
*
ANDW A
1
3
2
2
2
2
0
0
0
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
*
ANDW A, #imm16
ANDW A, ear
ANDW A, eam
ANDW ear, A
ANDW eam, A
2 + 3 + (a) (c) word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
2
3
0
2 + 3 + (a) 2 × (c) word (eam) ← (eam) and (A) –
*
ORW
A
1
3
2
2
2
2
0
0
0
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
*
ORW A, #imm16
ORW A, ear
ORW A, eam
ORW ear, A
2 + 3 + (a) (c) word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
2
3
0
ORW eam, A
2 + 3 + (a) 2 × (c) word (eam) ← (eam) or (A) –
*
XORW A
1
3
2
2
2
2
0
0
0
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
XORW A, #imm16
XORW A, ear
XORW A, eam
XORW ear, A
XORW eam, A
NOTW A
2 + 3 + (a) (c) word (A) ← (A) xor (eam)
2
2 + 3 + (a) 2 × (c) word (eam) ← (eam) xor (A) –
1
3
0
word (ear) ← (ear) xor (A)
2
3
0
0
word (A) ← not (A)
word (ear) ← not (ear)
–
–
–
NOTW ear
NOTW eam
2
*
*
2 + 3 + (a) 2 × (c) word (eam) ← not (eam)
Note: For (a) to (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
87
MB90210 Series
Table 15 Logic 2 (Long) [6 Instructions]
LH AH
Mnemonic
#
~
B
Operation
I
S
T
N
Z
V
C RMW
ANDL A, ear
ANDL A, eam
2
5
0
long (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2 + 6 + (a) (d) long (A) ← (A) and (eam)
ORL
ORL
A, ear
A, eam
2
5
0
long (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2 + 6 + (a) (d) long (A) ← (A) or (eam)
XORL A, ear
XORL A, eam
2
5
0
long (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2 + 6 + (a) (d) long (A) ← (A) xor (eam)
Note: For (a) and (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
Table 16 Sign Reverse (Byte, Word) [6 Instructions]
RG
LH AH
RMW
Mnemonic
#
~
B
Operation
I
S
T
N
Z
V
C
NEG
A
1
2
0
0
byte (A) ← 0 – (A)
X
–
–
–
–
*
*
*
*
–
NEG
NEG
ear
eam
2
3
2
0
byte (ear) ← 0 – (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
2 + 5 + (a) 0 2 × (b) byte (eam) ← 0 – (eam)
NEGW A
1
2
0
0
word (A) ← 0 – (A)
–
–
–
–
–
*
*
*
*
–
NEGW ear
NEGW eam
2
3
2
0
word (ear) ← 0 – (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
2 + 5 + (a) 0 2 × (c) word (eam) ← 0 – (eam)
Note: For (a) and (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
Table 17 Absolute Values (Byte, Word, Long) [3 Instructions]
LH AH
Mnemonic
#
~
B
Operation
I
S
T
N
Z
V
C RMW
ABS
ABSW
ABSL
A
A
A
2
2
2
2
2
4
0
0
0
byte (A) ← Absolute value (A)
word (A) ← Absolute value (A)
long (A) ← Absolute value (A)
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
Table 18 Normalize Instruction (Long) [1 Instruction]
LH AH
RMW
C
Mnemonic
#
~
RG
B
Operation
I
S
T
N
Z
V
NRML A, R0
2
*1
1
0
long (A) ← Shift to where “1”
is originally located
–
–
–
–
–
–
*
–
–
–
byte (R0) ← Number of shifts
in the operation
* : Set to 5 when the accumulator is all “0”, otherwise set to 5 + (R0).
88
MB90210 Series
Table 19 Shift Type Instruction (Byte, Word, Long) [27 Instructions]
LH AH
RMW
T N Z V C
Mnemonic
RORC A
#
~
B
Operation
I
S
2
2
2
2
0
0
byte (A) ← With right-rotate carry
byte (A) ← With left-rotate carry
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
*
*
–
–
ROLC A
RORC ear
RORC eam
ROLC ear
ROLC eam
2
2 +
2
2
0
byte (ear) ← With right-rotate carry
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
*
*
*
*
3 + (a)
2 × (b) byte (eam) ← With right-rotate carry
byte (ear) ← With left-rotate carry
2
3 + (a)
0
2 +
2 × (b) byte (eam) ← With left-rotate carry
byte (A) ← Arithmetic right barrel shift (A, R0)
ASR A, R0
LSR A, R0
2
2
2
*1
*1
*1
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
LSL
A, R0
byte (A) ← Arithmetic right barrel shift (A, imm8)
ASR A, #imm8
3
3
3
*3
*3
*3
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
byte (A) ← Logical right barrel shift (A, imm8)
LSR
LSL
A, #imm8
A, #imm8
byte (A) ← Logical left barrel shift (A, imm8)
word (A) ← Arithmetic right shift (A, 1 bit)
ASRW A
LSRW A/SHRW A 1
LSLW A/SHLW A
1
2
2
2
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
R
*
*
*
*
–
–
–
*
*
*
–
–
–
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
1
word (A) ← Arithmetic right barrel shift (A, R0)
ASRW A, R0
LSRW A, R0
LSLW A, R0
2
2
2
*1
*1
*1
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
word (A) ← Logical right barrel shift (A, R0)
word (A) ← Logical left barrel shift (A, R0)
word (A) ← Arithmetic right barrel shift (A, imm8)
ASRW A, #imm8
LSRW A, #imm8
LSLW A, #imm8
3
3
3
*3
*3
*3
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
word (A) ← Logical right barrel shift (A, imm8)
word (A) ← Logical left barrel shift (A, imm8)
long (A) ← Arithmetic right barrel shift (A, R0)
ASRL A, R0
LSRL A, R0
LSLL A, R0
2
2
2
*2
*2
*2
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
long (A) ← Logical right barrel shift (A, R0)
long (A) ← Logical left barrel shift (A, R0)
long (A) ← Arithmetic right barrel shift (A, imm8)
ASRL A, #imm8
LSRL A, #imm8
LSLL A, #imm8
3
3
3
*4
*4
*4
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
long (A) ← Logical right barrel shift (A, imm8)
long (A) ← Logical left barrel shift (A, imm8)
Note: For (a) and (b), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1: Set to 3 when R0 is 0, otherwise 3 + (R0).
*2: Set to 3 when R0 is 0, otherwise 4 + (R0).
*3: Set to 3 when imm8 is 0, otherwise 3 + imm8.
*4: Set to 3 when imm8 is 0, otherwise 4 + imm8.
89
MB90210 Series
Table 20 Branch 1 [31 Instructions]
LH AH
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
#
~
B
Operation
Branch if (Z) = 1
Branch if (Z) = 0
Branch if (C) = 1
Branch if (C) = 0
Branch if (N) = 1
Branch if (N) = 0
Branch if (V) = 1
Branch if (V) = 0
Branch if (T) = 1
Branch if (T) = 0
Branch if (V) xor (N) = 1
Branch if (V) xor (N) = 0
Branch if ((V) xor (N)) or (Z) = 1
Branch if ((V) xor (N)) or (Z) = 0
I
S
T N Z V C RMW
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
BN
BP
BV
BNV
BT
BNT
BLT
BGE
BLE
BGT
BLS
BHI
BRA
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
Branch if (C) or (Z) = 1
Branch if (C) or (Z) = 0
Branch unconditionally
JMP
JMP
JMP
JMP
JMPP
JMPP
JMPP
@A
addr16
@ear
@eam
@ear *3
@eam *3
addr24
1
3
2
2
2
3
0
0
0
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2 + 4 + (a) (c) word (PC) ← (eam)
2
2 + 4 + (a) (d)
4
word (PC) ← (ear), (PCB) ← (ear + 2)
word (PC) ← (eam), (PCB) ← (eam + 2)
word (PC) ← ad24 0 – 15,
(PCB) ← ad24 16 – 23
3
0
3
0
CALL
CALL
CALL
@ear *4
2
4
(c) word (PC) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
@eam *4
addr16 *5
2 + 5 + (a) 2 × (c) word (PC) ← (eam)
3
1
2
5
5
7
(c) word (PC) ← addr16
2 × (c) Vector call instruction
2 × (c) word (PC) ← (ear) 0 – 15
(PCB) ← (ear) 16 – 23
CALLV #vct4 *5
CALLP @ear *6
CALLP @eam *6
CALLP addr24 *7
2 + 8 + (a) *2 word (PC) ← (eam) 0 – 15
(PCB) ← (eam) 16 – 23
4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
7
2 × (c) word (PC) ← addr0 – 15,
(PCB) ← addr16 – 23
Note: For(a), (c) and (d), referto “Table 4 Number of Execution Cyclesin Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1: Set to 3 when branch is executed, and 2 when branch is not executed.
*2: 3 × (c) + (b)
*3: Reads (word) of the branch destination address.
*4: W pushes to stack (word), and R reads (word) of the branch destination address.
*5: Pushes to stack (word).
*6: W pushes to stack (long), and R reads (long) of the branch destination address.
*7: Pushes to stack (long).
90
MB90210 Series
Table 21 Branch 2 [20 Instructions]
LH AH
Mnemonic
#
~
B
Operation
I
S
T
N
Z
V
C RMW
CBNE A, #imm8, rel
CWBNE A, #imm16, rel
3 *1
4 *1
0
0
Branch if byte (A) ≠ imm8
Branch if word (A) ≠ imm16
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
Branch if byte (ear) ≠ imm8
Branch if byte (eam) ≠ imm8
Branch if word (ear) ≠ imm16
Branch if word (eam) ≠ imm16
CBNE ear, #imm8, rel
CBNE eam, #imm8, rel
CWBNE ear, #imm16, rel
4 *1
4 + *3 (b)
5 *1
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
0
CWBNE eam, #imm16, rel 5 + *3 (c)
DBNZ ear, rel
DBNZ eam, rel
3 *2
0
byte (ear) = (ear) – 1,
Branch if (ear) ≠ 0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
3 + *4 2 × (b) byte (eam) = (eam) – 1,
Branch if (eam) ≠ 0
DWBNZ ear, rel
DWBNZ eam, rel
3 *2
0
word (ear) = (ear) – 1,
Branch if (ear) ≠ 0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
3 + *4 2 × (c) word (eam) = (eam) – 1,
Branch if (eam) ≠ 0
INT
INT
INTP
INT9
RETI
RETIQ *6
#vct8
addr16
addr24
2 14 8 × (c) Software interrupt
3 12 6 × (c) Software interrupt
4 13 6 × (c) Software interrupt
1 14 8 × (c) Software interrupt
–
–
–
–
–
–
–
–
–
–
–
–
R
R
R
R
*
S
S
S
S
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
–
–
1
9 6 × (c) Return from interrupt
2 11 *5 Return from interrupt
*
*
*
*
*
*
*
2
1
6
5
(c) Stores old frame pointer in
the beginning of the
–
–
–
–
–
–
–
–
–
–
LINK
#imm8
function, set new frame
pointer, and reserves local
pointer area
(c) Restore old frame pointer
from stack in the end of
the function
–
–
–
–
–
–
–
–
–
–
UNLINK
RET *7
1
1
4
5
(c) Return from subroutine
(d) Return from subroutine
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
RETP *8
Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1: Set to 4 when branch is executed, and 3 when branch is not executed.
*2: Set to 5 when branch is executed, and 4 when branch is not executed.
*3: Set to 5 + (a) when branch is executed, and 4 + (a) when branch is not executed.
*4: Set to 6 + (a) when branch is executed, and 5 + (a) when branch is not executed.
*5: Set to 3 × (b) + 2 × (c) when an interrupt request is issued, and 6 × (c) for return.
*6: This is a high-speed interrupt return instruction. In the instruction, an interrupt request is detected. When an
interrupt occurs, stack operation is not performed, with this instruction branching to the interrupt vector.
*7: Return from stack (word).
*8: Return from stack (long).
91
MB90210 Series
Table 22 Miscellaneous Control Types (Byte, Word, Long) [36 Instructions]
LH AH
Mnemonic
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
#
~
B
Operation
I
S
T N Z V C RMW
1
1
1
2
3
3
(c) word (SP) ← (SP) – 2, ((SP)) ← (A) –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (SP) ← (SP) – 2, ((SP)) ← (AH)
word (SP) ← (SP) – 2, ((SP)) ← (PS)
(PS) ← (PS) – 2n, ((SP)) ← (rlst)
(c)
(c)
*4
–
–
–
3
*3
word (A) ← ((SP)), (SP) ← (SP) + 2
word (AH) ← ((SP)), (SP) ← (SP) + 2
word (PS) ← ((SP)), (SP) ← (SP) + 2
(rlst) ← ((SP)), (SP) ← (SP) + 2n
POPW
A
1
1
1
2
3
3
(c)
(c)
(c)
*4
–
–
–
–
*
–
–
*
–
–
*
–
–
*
–
–
*
–
–
*
–
–
*
–
–
*
–
–
–
–
POPW AH
POPW PS
POPW rlst
–
–
–
3
*2
–
–
–
–
–
–
–
JCTX
@A
1
9
6 × (c) Context switch instruction
–
–
*
*
*
*
*
*
*
–
AND
OR
CCR, #imm8
CCR, #imm8
2
2
3
3
0
0
byte (CCR) ← (CCR) and imm8 –
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
byte (CCR) ← (CCR) or imm8
–
MOV
MOV
RP, #imm8
ILM, #imm8
2
2
2
2
0
0
byte (RP) ← imm8
byte (ILM) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
2
3
0
0
0
0
word (RWi) ← ear
word (RWi) ← eam
word(A) ← ear
–
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2 + 2 + (a)
2
2
MOVEA A, eam
2 + 1 + (a)
word (A) ← eam
*
ADDSP #imm8
ADDSP #imm16
2
3
3
3
0
0
word (SP) ← (SP) + ext (imm8) –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (SP) ← (SP) + imm16
–
MOV
MOV
MOV
A, brgl
2
2
*1
1
2
0
0
0
byte (A) ← (brgl)
byte (brg2) ← (A)
byte (brg2) ← imm8
Z
–
–
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
brg2, A
brg2, #imm8 3
NOP
ADB
DTB
PCB
SPB
NCC
CMR
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
No operation
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no change in flag
Prefix for common register bank
MOVW SPCU, #imm16
MOVW SPCL, #imm16
SETSPC
4
4
2
2
2
2
2
2
0
0
0
0
word (SPCU) ← (imm16)
word (SPCL) ← (imm16)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Enables stack check operation.
CLRSPC
Disables stack check operation. –
Bit position of 1 in byte (A) from word (A)
Bit position (× 2) of 1 in byte (A) from word (A)
BTSCN A
BTSCNS A
BTSCND A
2
2
2
*5
*6
*7
0
0
0
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
Z
Bit position (× 4) of 1 in byte (A) from word (A)
Z
Note: For (a) and (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction
Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB
DPR
: 2 states
: 3 states
*2: 3 + 4 × (number of POPs)
*3: 3 + 4 × (number of PUSHes)
*4: (Number of POPs) × (c), or (number of PUSHes) × (c)
*5: Set to 3 when AL is 0, 5 when AL is not 0.
*6: Set to 4 when AL is 0, 6 when AL is not 0.
*7: Set to 5 when AL is 0, 7 when AL is not 0.
92
MB90210 Series
Table 23 Bit Manipulation Instruction [21 Instructions]
LH AH
Mnemonic
#
~
B
Operation
I
S
T N Z V C RMW
MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp
3
4
3
3
3
3
(b) byte (A) ← (dir:bp) b
(b) byte (A) ← (addr16:bp) b
(b) byte (A) ← (io:bp) b
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A
3
4
3
4
4
4
2 × (b) bit (dir:bp) b ← (A)
2 × (b) bit (addr16:bp) b ← (A)
2 × (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
SETB dir:bp
SETB addr16:bp
SETB io:bp
3
4
3
4
4
4
2 × (b) bit (dir:bp) b ← 1
2 × (b) bit (addr16:bp) b ← 1
2 × (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
CLRB dir:bp
CLRB addr16:bp
CLRB io:bp
3
4
3
4
4
4
2 × (b) bit (dir:bp) b ← 0
2 × (b) bit (addr16:bp) b ← 0
2 × (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
BBC dir:bp, rel
BBC addr16:bp, rel
BBC io:bp, rel
4
5
4
*1
*1
*1
(b) Branch if (dir:bp) b = 0
(b) Branch if (addr16:bp) b = 0
(b) Branch if (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
BBS
BBS
BBS
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*1
(b) Branch if (dir:bp) b = 1
(b) Branch if (addr16:bp) b = 1
(b) Branch if (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
Branch if (addr16:bp) b = 1, bit = 1
SBBS addr16:bp, rel
WBTS io:bp
5
3
3
*2 2 × (b)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
*
*3
*3
*4 Wait until (io:bp) b = 1
*4 Wait until (io:bp) b = 0
–
–
–
–
WBTC io:bp
Note: For (b), refer to “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1: Set to 5 when branch is executed, and 4 when branch is not executed.
*2: 7 if conditions are met, 6 when conditions are not met.
*3: Indeterminate times
*4: Until conditions are met
93
MB90210 Series
Table 24 Accumulator Manipulation Instruction (Byte, Word) [6 Instructions]
LH AH
Mnemonic
#
~
B
Operation
I
S
T
N
Z
V
C RMW
SWAP
SWAPW/XCHW AL, AH
EXT
EXTW
ZEXT
ZEXTW
1
1
1
1
1
1
3
2
1
2
1
1
0 byte (A) 0 – 7 ↔ (A) 8 – 15
0 word (AH) ↔ (AL)
0 byte sign-extension
0 word sign-extension
0 byte zero-extension
0 word zero-extension
–
–
X
–
Z
–
–
*
–
X
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
Table 25 String Instruction [10 Instructions]
LH AH
Mnemonic
#
~
B
Operation
I
S
T
N
Z
V
C RMW
MOVS/MOVSI
2
*2 *3 byte transfer @AH + ← @AL +,
Counter = RW0
*2 *3 byte transfer @AH – ← @AL –,
Counter = RW0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVSD
2
–
–
–
–
–
–
SCEQ/SCEQI
SCEQD
2
2
*1 *4 byte search (@AH +) – AL,
Counter = RW0
*1 *4 byte search (@AH –) – AL,
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
Counter = RW0
FISL/FILSI
2 5m + 6 *5 byte fill @AH + ← AL,
–
–
–
–
–
*
*
–
–
–
Counter = RW0
MOVSW/MOVSWI
MOVSWD
2
2
*2 *6 word transfer @AH + ← @AL +,
Counter = RW0
*2 *6 word transfer @AH – ← @AL –,
Counter = RW0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SCWEQ/SCWEQI
SCWEQD
2
2
*1 *7 word search (@AH +) – AL,
Counter = RW0
*1 *7 word search (@AH –) – AL,
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
Counter = RW0
FILSW/FILSWI
2 5m + 6 *8 word fill @AH + ← AL,
–
–
–
–
–
*
*
–
–
–
Counter = RW0
m: RW0 value (counter value)
*1: 3 when RW0 is 0, 2 + 6 × (RW0) when count out, and 6n + 4 when matched
*2: 4 when RW0 is 0, otherwise 2 + 6 × (RW0)
*3: (b) × (RW0)
*4: (b) × n
*5: (b) × (RW0)
*6: (c) × (RW0)
*7: (c) × n
*8: (c) × (RW0)
94
MB90210 Series
Table 26 Multiple Data Transfer Instructions [18 Instruction]
LH AH
Mnemonic
#
~
B
Operation
I
S
T
N
Z
V
C RMW
MOVM @A, @RLi, #imm8
3
*1 *3 Multiple data transfer
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
byte ((A)) ← ((RLi))
MOVM @A, eam, #imm8
MOVM addr16, @RLi, #imm8
3 + *2 *3 Multiple data transfer
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
byte ((A)) ← (eam)
*1 *3 Multiple data transfer
5
byte (addr16) ← ((RLi))
MOVM addr16, @eam, #imm8 5 + *2 *3 Multiple data transfer
byte (addr16) ← (eam)
*1 *4 Multiple data transfer
MOVMW@A, @RLi, #imm8
MOVMW@A, eam, #imm8
MOVMWaddr16, @RLi, #imm8
3
word ((A)) ← ((RLi))
3 + *2 *4 Multiple data transfer
word ((A)) ← (eam)
*1 *4 Multiple data transfer
5
word (addr16) ← ((RLi))
MOVMWaddr16, @eam, #imm8 5 + *2 *4 Multiple data transfer
word (addr16) ← (eam)
*1 *3 Multiple data transfer
MOVM @RLi, @A, #imm8
MOVM @eam, A, #imm8
MOVM @RLi, addr16, #imm8
3
byte ((RLi)) ← ((A))
3 + *2 *3 Multiple data transfer
byte (eam) ← ((A))
*1 *3 Multiple data transfer
5
byte ((RLi)) ← (addr16)
MOVM @eam, addr16, #imm8 5 + *2 *3 Multiple data transfer
byte (eam) ← (addr16)
*1 *4 Multiple data transfer
MOVMW@RLi, @A, #imm8
MOVMW@eam, A, #imm8
MOVMW@RLi, addr16, #imm8
3
word ((RLi)) ← ((A))
3 + *2 *4 Multiple data transfer
word (eam) ← ((A))
*1 *4 Multiple data transfer
5
word ((RLi)) ← (addr16)
MOVMW@eam, addr16, #imm8 5 + *2 *4 Multiple data transfer
word (eam) ← (addr16)
MOVM bnk: addr16,
bnk: addr16, #imm8*5
7
7
*1 *3 Multiple data transfer
byte (bnk: addr16) ←
(bnk: addr16)
*1 *4 Multiple data transfer
word (bnk: addr16) ←
(bnk: addr16)
MOVMWbnk: addr16,
bnk: addr16, #imm8*5
–
–
–
–
–
–
–
–
–
–
*1: 256 when 5 + imm8 × 5, imm8 is 0.
*2: 256 when 5 + imm8 × 5 + (a), imm8 is 0.
*3: (Number of transfer cycles) × (b) × 2
*4: (Number of transfer cycles) × (c) × 2
*5: The bank register specified by bnk is the same as that for the MOVS instruction.
95
MB90210 Series
■ ORDERING INFORMATION
Part number
Type
MB90214PF
MB90P214PF
MB90P214BPF
Package
Remarks
MB90214
MB90P214A
MB90P214B
80-pin Plastic QFP
(FPT-80P-M06)
MB90W214A
MB90W214B
MB90W214ZF
MB90W214BZF
80-pin Ceramic QFP
(FPT-80C-C02)
Only ES level
For evaluation
MB90V210
MB90V210CR
256-pin Ceramic PGA
(PGA-256C-A02)
96
MB90210 Series
■ PACKAGE DIMENSIONS
80-pin Plastic QFP
(FPT-80P-M06)
(Mounting height)
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
3.35(.132)MAX
0.05(.002)MIN
(STAND OFF)
64
41
65
40
12.00(.472)
16.30±0.40
14.00±0.20 17.90±0.40
(.551±.008) (.705±.016)
REF
(.642±.016)
INDEX
80
25
"A"
1
24
LEAD No.
0.80(.0315)TYP
0.35±0.10
(.014±.004)
0.15±0.05(.006±.002)
Details of "B" part
M
0.16(.006)
Details of "A" part
0.25(.010)
"B"
0.10(.004)
0.30(.012)
0.18(.007)MAX
0
10°
18.40(.724)REF
0.80±0.20
(.031±.008)
0.58(.023)MAX
22.30±0.40(.878±.016)
C
Dimensions in mm (inches)
1994 FUJITSU LIMITED F80010S-3C-2
80-pin Ceramic QFP
(FPT-80C-C02)
0.05(.002)MIN
(STAND OFF)
17.90±0.30
(.705±.012)
12.00(.472)
REF
16.30±0.25
(.642±.010)
14.00+–00..1455
Ø8.89(.350)TYP
+.018
.551–.006
INDEX AREA
0.80(.0315)TYP
0.35±0.10
(.014±.004)
18.40(.724) REF
0.15±0.05
(.006±.002)
1.45±0.20
(.057±.008)
+0.50
20.00–0.20
3.30(.130)MAX
+.020
.787–.008
23.90±0.30
(.941±.012)
(Mounting height)
22.30±0.25
(.878±.010)
0.80±0.20
(.0315±.008)
C
1994 FUJITSU LIMITED F80018SC-1-2
Dimensions in mm (inches)
97
MB90210 Series
MEMO
98
MB90210 Series
MEMO
99
MB90210 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
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The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: (044) 754-3329
http://www.fujitsu.co.jp/
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 922-9179
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
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Tel: (800) 866-8608
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Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9710
FUJITSU LIMITED Printed in Japan
相关型号:
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