MB91101_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-16301-2E

32-bit RISC Microcontroller

CMOS

FR30 Series

MB91101/MB91101A

■ DESCRIPTION

The MB91101 is a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family)

core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU

processing for embedded controller applications. To support the vast memory space accessed by the 32-bit

CPU, the MB91101 normally operates in the external bus access mode and executes instructions on the internal

1 Kbyte cache memory and 2 Kbytes RAM for enhanced performance.

The MB91101 is optimized for applications requiring high-performance CPU processing such as navigation

systems, high-performance FAXs and printer controllers.

*: FR Family stands for FUJITSU RISC controller.

■ FEATURES

FR CPU

• 32-bit RISC, load/store architecture, 5-stage pipeline

• Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)

• General purpose registers: 32 bits × 16

• 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle

• Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications

• Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems

supporting high level languages

• Register interlock functions, efficient assembly language coding

• Branch instructions with delay slots: Reduced overhead time in branch executions

(Continued)

■ PACKAGE

100-pin Plastic LQFP

100-pin Plastic QFP

(FPT-100P-M05)

(FPT-100P-M06)

MB91101/MB91101A

(Continued)

• Internal multiplier/supported at instruction level

Signed 32-bit multiplication: 5 cycles

Signed 16-bit multiplication: 3 cycles

• Interrupt (push PC and PS): 6 cycles, 16 priority levels

External bus interface

• Clock doubler: Internal 50 MHz, external bus 25 MHz operation

• 25-bit address bus (32 Mbytes memory space)

• 8/16-bit data bus

• Basic external bus cycle: 2 clock cycles

• Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 6

• Interface supported for various memory technologies

DRAM interface (area 4 and 5)

• Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area

• Unused data/address pins can be configured us input/output ports

• Little endian mode supported (Select 1 area from area 1 to 5)

DRAM interface

• 2 banks independent control (area 4 and 5)

• Normal mode (double CAS DRAM)/high-speed page mode (single CAS DRAM)/Hyper DRAM

• Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode

• Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles

• DRAM refresh

CBR refresh (interval time configurable by 6-bit timer)

Self-refresh mode

• Supports 8/9/10/12-bit column address width

• 2CAS/1WE, 2WE/1CAS selective

Cache memory

• 1-Kbyte instruction cache memory

• 32 block/way, 4 entry(4 word)/block

• 2 way set associative

• Lock function: For specific program code to be resident in cashe memory

DMA controller (DMAC)

• 8 channels

• Transfer incident/external pins/internal resource interrupt requests

• Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer

• Transfer data length: 8 bits/16 bits/32 bits selective

• NMI/interrupt request enables temporary stop operation

UART

• 3 independent channels

• Full-duplex double buffer

• Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity)

• Asynchronous (start-stop system), CLK-synchronized communication selective

• Multi-processor mode

• Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate

• Use external clock can be used as a transfer clock

• Error detection: Parity, frame, overrun

2

MB91101/MB91101A

(Continued)

10-bit A/D converter (successive approximation conversion type)

• 10-bit resolution, 4 channels

• Successive approximation type: Conversion time of 5.6 µs at 25 MHz

• Internal sample and hold circuit

• Conversion mode: Single conversion/scanning conversion/repeated conversion/stop conversion selective

• Start: Software/external trigger/internal timer selective

16-bit reload timer

• 3 channels

• Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective

Other interval timers

• 16-bit timer: 3 channels (U-TIMER)

• PWM timer: 4 channels

• Watchdog timer: 1 channel

Bit search module

First bit transition “1” or “0” from MSB can be detected in 1 cycle

Interrupt controller

• External interrupt input: Non-maskable interrupt (NMI), normal interrupt × 4 (INT0 to INT3)

• Internal interrupt incident:UART, DMA controller (DMAC), A/D converter, U-TIMER and delayed interrupt

module

• Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps)

Others

• Reset cause: Power-on reset/hardware standby/watchdog timer/software reset/external reset

• Low-power consumption mode: Sleep mode/stop mode

• Clock control

Gear function: Operating clocks for CPU and peripherals are independently selective

Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16)

However, operating frequency for peripherals is less than 25 MHz.

• Packages: LQFP-100 and QFP-100

• CMOS technology (0.35 µm)

• Power supply voltage

5 V: CPU power supply 5.0 V ±10% (internal regulator)

A/D power supply 2.7 V to 3.6 V

3 V: CPU power supply 2.7 V to 3.6 V (without internal regulator)

A/D power supply 2.7 V to 3.6 V

3

MB91101/MB91101A

■ PIN ASSIGNMENT

(Top view)

CS1L/PB5/DREQ2

CS1H/PB6/DACK2

DW1/PB7

V^CC3

CLK/PA6

CS5/PA5

CS4/PA4

CS3/PA3/EOP1

CS2/PA2

CS1/PA1

CS0

NMI

HST

RST

V^SS

MD0

MD1

MD2

1

2

3

4

5

6

7

8

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

AN3

AN2

AN1

AN0

AV^SS/AVRL

AVRH

AV^CC

A24/EOP0

A23/P67

A22/P66

V^SS

A21/P65

A20/P64

A19/P63

A18/P62

A17/P61

A16/P60

A15

A14

A13

A12

A11

A10

A09

A08

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

RDY/P80

BGRNT/P81

BRQ/P82

RD

WR0

WR1/P85

D16/P20

(FPT-100P-M05)

4

MB91101/MB91101A

(Top view)

CS0H/PB2

DW0/PB3

RAS1/PB4/EOP2

CS1L/PB5/DREQ2

CS1H/PB6/DACK2

DW1/PB7

VCC3

CLK/PA6

CS5/PA5

CS4/PA4

CS3/PA3/EOP1

CS2/PA2

CS1/PA1

CS0

NMI

HST

RST

VSS

MD0

MD1

MD2

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

SO0/TRG1/PF1

SI0/TRG0/PF0

AN3

AN2

AN1

AN0

AV^SS/AVRL

AVRH

AV^CC

A24/EOP0

A23/P67

A22/P66

V^SS

A21/P65

A20/P64

A19/P63

A18/P62

A17/P61

A16/P60

A15

A14

A13

A12

A11

A10

A09

A08

A07

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

RDY/P80

BGRNT/P81

BRQ/P82

RD

WR0

WR1/P85

D16/P20

D17/P21

D18/P22

A06

A05

(FPT-100P-M06)

5

MB91101/MB91101A

■ PIN DESCRIPTION

Pin no.

LQFP*¹QFP*²

Circuit

type

Pin name

Function

25 to 32 28 to 35 D16 to D23

P20 to P27

C

Bit 16 to bit 23 of external data bus

Can be configured as I/O ports when external data bus width is

set to 8-bit.

33 to 39, 36 to 42, D24 to D30,

C

F

Bit 24 to bit 31 of external data bus

Bit 00 to bit 15 of external address bus

Bit 16 to bit 23 of external address bus

41

44

D31

42,

45,

A00,

44 to 58 47 to 61 A01 to A15

59 to 64, 62 to 67, A16 to A21,

66,

67

69,

70

A22,

A23

P60 to P65,

P66,

Can be configured as I/O ports when not used as address bus.

P67

68

19

71

22

A24

L

Bit 24 of external address bus

EOP0

Can be configured as DMAC EOP output (ch. 0) when DMAC

EOP output is enabled.

RDY

C

External ready input

Inputs “0” when bus cycle is being executed and not

completed.

P80

Can be configured as a port when RDY is not used.

20

21

23

24

BGRNT

F

External bus release acknowledge output

Outputs “L” level when external bus is released.

P81

Can be configured as a port when BGRNT is not used.

BRQ

C

External bus release request input

Inputs “1” when release of external bus is required.

P82

RD

Can be configured as a port when BRQ is not used.

Read strobe output pin for external bus

22

23

25

26

L

WR0

Write strobe output pin for external bus

Relation between control signals and effective byte locations is

as follows:

16-bit bus width

WR0

8-bit bus width

WR0

D15 to D08

D07 to D00

24

27

WR1

P85

F

WR1

(I/O port enabled)

Note: WR1 is Hi-Z during resetting.

Attach an external pull-up resister when using at 16-bit

bus width.

Can be configured as a port when WR1 is not used.

(Continued)

*1: FPT-100P-M05

*2: FPT-100P-M06

6

MB91101/MB91101A

Pin no.

Circuit

type

Pin name

CS0

Function

LQFP*¹

QFP*²

11

10

14

L

F

Chip select 0 output (“L” active)

13

CS1

PA1

CS2

PA2

CS3

PA3

Chip select 1 output (“L” active)

Can be configured as a port when CS1 is not used.

Chip select 2 output (“L” active)

9

8

12

11

F

Can be configured as a port when CS2 is not used.

Chip select 3 output (“L” active)

Can be configured as a port when CS3 and EOP1 are not

used.

EOP1

EOP output pin for DMAC (ch. 1)

This function is available when EOP output for DMAC is

enabled.

7

6

5

10

9

CS4

PA4

CS5

PA5

CLK

F

Chip select 4 output (“L” active)

Can be configured as a port when CS4 is not used.

Chip select 5 output (“L” active)

Can be configured as a port when CS5 is not used.

8

System clock output

Outputs clock signal of external bus operating frequency.

PA6

Can be configured as a port when CLK is not used.

96

97

99

100

1

RAS0

F

RAS output for DRAM bank 0

Refer to the DRAM interface for details.

PB0

Can be configured as a port when RAS0 is not used.

CS0L

CASL output for DRAM bank 0

Refer to the DRAM interface for details.

PB1

Can be configured as a port when CS0L is not used.

98

CS0H

CASH output for DRAM bank 0

Refer to the DRAM interface for details.

PB2

Can be configured as a port when CS0H is not used.

99

2

DW0

WE output for DRAM bank 0 (“L” active)

Refer to the DRAM interface for details.

PB3

Can be configured as a port when DW0 is not used.

100

3

RAS1

RAS output for DRAM bank 1

Refer to the DRAM interface for details.

PB4

Can be configured as a port when RAS1 and EOP2 are not

used.

EOP2

DMAC EOP output (ch. 2)

This function is available when DMAC EOP output is enabled.

*1: FPT-100P-M05

*2: FPT-100P-M06

(Continued)

7

MB91101/MB91101A

Pin no.

Circuit

type

Pin name

CS1L

Function

CASL output for DRAM bank 1

LQFP*¹

QFP*²

1

4

F

Refer to the DRAM interface for details.

PB5

Can be configured as a port when CS1L and DREQ2 are not

used.

DREQ2

External transfer request input pin for DMA

This pin is used for input when external trigger is selected to

cause DMAC operation, and it is necessary to disable output for

other functions from this pin unless such output is made

intentionally.

2

5

CS1H

PB6

F

CASH output for DRAM bank 1

Refer to the DRAM interface for details.

Can be configured as a port when CS1H and DACK2 are not

used.

DACK2

External transfer request acknowledge output pin for DMAC (ch.

2)

This function is available when transfer request output for DMAC

is enabled.

3

6

DW1

PB7

F

WE output for DRAM bank 1 (“L” active)

Refer to the DRAM interface for details.

Can be configured as a port when DW1 is not used.

16 to 18 19 to 21 MD0 to MD2

G

Mode pins 0 to 2

MCU basic operation mode is set by these pins.

Directly connect these pins with V^CCor V^SSfor use.

92

91

14

13

12

95

94

17

16

15

X0

A

B

H

F

Clock (oscillator) input

X1

Clock (oscillator) output

RST

HST

NMI

External reset input

Hardware standby input (“L” active)

NMI (non-maskable interrupt pin) input (“L” active)

95,

94

98,

97

INT0,

INT1

External interrupt request input pins

These pins are used for input during corresponding interrupt is

enabled, and it is necessary to disable output for other functions

from these pins unless such output is made intentionally.

PE0,

PE1

Can be configured as a I/O port when INT0, INT1 are not used.

89

92

INT2

F

External interrupt request input pin

This pin is used for input during corresponding interrupt is

enabled, and it is necessary to disable output for other functions

from this pin unless such output is made intentionally.

SC1

PE2

Clock I/O pin for UART1

Clock output is available when clock output of UART1 is enabled.

Can be configured as a I/O port when INT2 and SC1 are not

used.

This function is available when UART1 clock output is disabled.

*1: FPT-100P-M05

*2: FPT-100P-M06

(Continued)

8

MB91101/MB91101A

Pin no.

Circuit

type

Pin name

INT3

Function

LQFP*¹

QFP*²

88

91

F

External interrupt request input pin

This pin is used for input during corresponding interrupt is enabled,

and it is necessary to disable output for other functions from this

pin unless such output is made intentionally.

SC2

PE3

UART2 clock I/O pin

Clock output is available when UART2 clock output is enabled.

Can be configured as a I/O port when INT3 and SC2 are not used.

This function is available when UART2 clock output is disabled.

87,

86

90,

89

DREQ0,

DREQ1

F

External transfer request input pins for DMA

These pins are used for input when external trigger is selected to

cause DMAC operation, and it is necessary to disable output for

other functions from these pins unless such output is made

intentionally.

PE4,

PE5

Can be configured as a I/O port when DREQ0, DREQ1 are not

used.

85

84

76

88

87

79

DACK0

F

External transfer request acknowledge output pin for DMAC (ch. 0)

This function is available when transfer request output for DMAC is

enabled.

PE6

Can be configured as a I/O port when DACK0 is not used.

This function is available when transfer request acknowledge

output for DMAC or DACK0 output is disabled.

DACK1

PE7

External transfer request acknowledge output pin for DMAC (ch. 1)

This function is available when transfer request output for DMAC is

enabled.

Can be configured as a I/O port when DACK1 is not used.

This function is available when transfer request output for DMAC or

DACK1 output is disabled.

SI0

UART0 data input pin

This pin is used for input during UART0 is in input operation, and it

is necessary to disable output for other functions from this pin

unless such output is made intentionally.

TRG0

PF0

PWM timer external trigger input pin

This pin is used for input during PWM timer external trigger is in

input operation, and it is necessary to disable output for other

functions from this pin unless such output is made intentionally.

Can be configured as a I/O port when SI0 and TRG0 are not used.

(Continued)

*1: FPT-100P-M05

*2: FPT-100P-M06

9

MB91101/MB91101A

Pin no.

Circuit

type

Pin name

SO0

Function

LQFP*¹

QFP*²

77

80

F

UART0 data output pin

This function is available when UART0 data output is enabled.

TRG1

PF1

PWM timer external trigger input pin

This function is available when serial data output of PF1, UART0

are disabled.

Can be configured as a I/O port when SO0 and TRG1 are not

used.

This function is available when serial data output of UART0 is

disabled.

78

79

81

82

SC0

F

UART0 clock I/O pin

Clock output is available when UART0 clock output is enabled.

OCPA3

PF2

PWM timer output pin

This function is available when PWM timer output is enabled.

Can be configured as a I/O port when SC0 and OCPA3 are not

used.

This function is available when UART0 clock output is disabled.

SI1

UART1 data input pin

This pin is used for input during UART1 is in input operation, and it

is necessary to disable output for other functions from this pin

unless such output is made intentionally.

TRG2

PWM timer external trigger input pin

This pin is used for input during PWM timer external trigger is in

input operation, and it is necessary to disable output for other

functions from this pin unless such output is made intentionally.

PF3

SO1

Can be configured as a I/O port when SI1 and TRG2 are not used.

80

83

F

UART1 data output pin

This function is available when UART1 data output is enabled.

TRG3

PF4

SI2

PWM timer external trigger input pin

This function is available when PF4, UART1 data outputs are

disabled.

Can be configured as a I/O port when SO1 and TRG3 are not

used.

This function is available when UART1 data output is disabled.

81

84

F

UART2 data input pin

This pin is used for input during UART2 is in input operation, and it

is necessary to disable output for other functions from this pin

unless such output is made intentionally.

OCPA1

PF5

PWM timer output pin

This function is available when PWM timer output is enabled.

Can be configured as a I/O port when SI2 and OCPA1 are not

used.

*1: FPT-100P-M05

*2: FPT-100P-M06

(Continued)

10

MB91101/MB91101A

(Continued)

Pin no.

Circuit

type

Pin name

SO2

Function

LQFP*¹

QFP*²

82

85

F

UART2 data output pin

This function is available when UART2 data output is enabled.

OCPA2

PF6

PWM timer output pin

This function is available when PWM timer output is enabled.

Can be configured as a I/O port when SO2 and OCPA2 are not

used.

This function is available when UART2 data output is disabled.

83

86

OCPA0

PF7

F

PWM timer output pin

This function is available when PWM timer output is enabled.

Can be configured as a I/O port when OCPA0 and ATG are not

used.

This function is available when PWM timer output is disabled.

ATG

External trigger input pin for A/D converter

This pin is used for input when external trigger is selected to

cause A/D converter operation, and it is necessary to disable

output for other functions from this pin unless such output is

made intentionally.

72 to 75 75 to 78 AN0 to AN3

D

Analog input pins of A/D converter

This function is available when AIC register is set to specify

analog input mode.

69

70

72

73

AV^CC

—

Power supply pin (V^CC) for A/D converter

AVRH

Reference voltage input (high) for A/D converter

Make sure to turn on and off this pin with potential of AVRH or

more applied to V^CC.

71

74

AV^SS/ AVRL

V^CC5

—

Power supply pin (V^SS) for A/D converter and reference voltage

input pin (low)

43,

93

46,

96

5 V power supply pin (V^CC) for digital circuit

Always two pins must be connected to the power supply

(connect to 3 V power supply when operating at 3 V).

4

7

V^CC3

V^SS

—

Bypass capacitor pin for internal capacitor.

Also connect this pin to 3 V power supply when operating at

3 V.

15,

40,

65,

90

18,

43,

68,

93

Earth level (V^SS) for digital circuit

*1: FPT-100P-M05

*2: FPT-100P-M06

Note: In most of the above pins, I/O port and resource I/O are multiplexed e.g. P82 and BRQ. In case of conflict

between output of I/O port and resource I/O, priority is always given to the output of resource I/O.

11

MB91101/MB91101A

■ DRAM CONTROL PIN

Data bus 16-bit mode

Pin name

Data bus 8-bit mode

—

Remarks

2CAS/1WR mode

1CAS/2WR mode

Correspondence of “L”

“H” to lower address 1

bit (A0) in data bus 16-

bit mode

“L”: “0”

“H”: “1”

CASL: CAS which A0

corresponds to

“0” area

CASH: CAS which A0

corresponds to

“1” area

WEL: WE which A0

corresponds to

“0” area

WEH: WE which A0

corresponds to

“1” area

RAS0

RAS1

CS0L

CS0H

CS1L

CS1H

CW0

Area 4 RAS

Area 5 RAS

Area 4 CAS

Area 4 WEL

Area 5 CAS

Area 5 WEL

Area 4 WEH

Area 5 WEH

Area 4 RAS

Area 5 RAS

Area 4 CAS

Area 5 CAS

Area 4 WE

Area 5 WE

Area 5 RAS

Area 4 CASL

Area 4 CASH

Area 5 CASL

Area 5 CASH

Area 4 WE

DW1

Area 5 WE

12

MB91101/MB91101A

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• Oscillation feedback resistance 1 MΩ

approx.

With standby control

X1

X0

Clock input

Standby control signal

B

• CMOS level

Hysteresis input

Without standby control

With pull-up resistance

V^CC

P-ch

R

N-ch

VSS

Digital input

C

• CMOS level I/O

With standby control

P-ch

N-ch

Digital output

R

Digital input

Standby control signal

D

• Analog input

P-ch

Digital output

Analog input

N-ch

R

(Continued)

13

MB91101/MB91101A

Type

Circuit

Remarks

E

• N-ch open-drain output

• CMOS level input

With standby control

P-ch

N-ch

Digital output

Digital input

R

Standby control signal

F

• CMOS level output

• CMOS level

Hysteresis input

With standby control

P-ch

Digital output

N-ch

R

Digital input

Standby control signal

G

• CMOS level input

Without standby control

P-ch

N-ch

R

Digital input

H

• CMOS level

Hysteresis input

Without standby control

P-ch

N-ch

R

Digital input

(Continued)

14

MB91101/MB91101A

(Continued)

Type

Circuit

Remarks

I

• CMOS level output

• CMOS level

Hysteresis input

Without standby control

P-ch

Digital output

N-ch

R

Digital input

J

• CMOS level output

• TTL level input

With standby control

P-ch

N-ch

Digital output

R

Digital input

TTL

Standby control signal

K

• CMOS level input/output

With standby control

• Large current drive

P-ch

Digital output

N-ch

R

Digital input

Standby control signal

L

• CMOS level output

P-ch

N-ch

Digital output

15

MB91101/MB91101A

■ HANDLING DEVICES

1. Preventing Latchup

In CMOS ICs, applying voltage higher than V^CCor lower than V^SSto input/output pin or applying voltage over

rating across V^CCand V^SSmay cause latchup.

This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the

device. Make sure to prevent the voltage from exceeding the maximum rating.

Take care that the analog power supply (AV^CC, AVR) and the analog input do not exceed the digital power

supply (V^CC) when the analog power supply turned on or off.

2. Treatment of Unused Pins

Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors.

3. External Reset Input

It takes at least 5 machine cycle to input “L” level to the RST pin and to ensure inner reset operation properly.

4. Remarks for External Clock Operation

When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to

X0 must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin stops

at “H” output in stop mode).

And can be used to supply only to X0 pin with 5 V power supply at 12.5 MHz and less than.

• Using an external clock

X0

X1

MB91101

Using an external clock (normal)

Note: Can not be used stop mode (oscillation stop mode).

X0

Open

X1

MB91101

Using an external clock (can be used at 12.5 MHz and less than.)

(5 V power supply only)

16

MB91101/MB91101A

5. Power Supply Pins

When there are several V^CCand V^SSpins, each of them is equipotentially connected to its counterpart inside

of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions,

to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and

to observe the total output current standard, connect all V^CCand V^SSpins to the power supply or GND.

It is preferred to connect V^CCand V^SSof MB91101 to power supply with minimal impedance possible.

It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 µF between V^CC

and V^SSat a position as close as possible to MB91101.

MB91101 has an internal regulator. When using with 5 V power supply, supply 5 V to V^CC5 pin and make sure

to connect about 0.1 µF bypass capacitor to V^CC3 pin for regulator. And another 3 V power supply is needed

for the A/D convertor. When using with 3 V power supply, connect both V^CC5 pin and V^CC3 pin to the 3 V power

supply.

• Connecting to a power supply

[Using with 3 V power supply]

[Using with 5 V power supply]

3 V

5 V

VCC3

VCC5

AV^CC

AVRH

AV^SS

VSS

VCC3

VCC5

AV^CC

AVRH

AVSS

VSS

3 V

About

0.1 µF

GND

6. Crystal Oscillator Circuit

Noises around X0 and X1 pins may cause malfunctions of MB91101. In designing the PC board, layout X0,

X1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible.

It is strongly recommended to design PC board so that X1 and X0 pins are surrounded by grounding area for

stable operation.

7. Turning-on Sequence of A/D Converter Power Supply and Analog Input

Make sure to turn on the digital power supply (V^CC) before turning on the A/D converter (AV^CC, AVRH) and

applying voltage to analog input (AN0 to AN3).

Make sure to turn off digital power supply after power supply to A/D converters and analog inputs have been

switched off. (There are no such limitations in turning on power supplies. Analog and digital power supplies

may be turned on simultaneously.) Make sure that AVRH never exceeds AV^CCwhen turning on/off power

supplies.

8. Treatment of N.C. Pins

Make sure to leave N.C. pins open.

17

MB91101/MB91101A

9. Fluctuation of Power Supply Voltage

Warranty range for normal operation against fluctuation of power supply voltage V^CCis as given in rating.

However, sudden fluctuation of power supply voltage within the warranty range may cause malfunctions. It is

recommended to make every effort to stabilize the power supply voltage to IC. It is also recommended that by

controlling power supply as a reference of stabilizing, V^CCripple fluctuation (P-P value) at the commercial

frequency (50 Hz to 60 Hz) should be less than 10% of the standard V^CCvalue and the transient regulation

should be less than 0.1 V/ms at instantaneous deviation like turning off the power supply.

10. Mode Setting Pins (MD0 to MD2)

Connect mode setting pins (MD0 to MD2) directly to V^CCor V^SS.

Arrange each mode setting pin and V^CCor V^SSpatterns on the printed circuit board as close as possible and

make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises.

11. Internal DC Regulator

Internal DC regulator stops in stop mode. When the regulator stops owing to the increase of inner leakage

current (ICCH) in stop mode, malfunction caused by noise or any troubles about power supply in normal

operation,theinternal3Vpowersupplyvoltagemaydecreaselessthanthewarrantyrangefornormaloperation.

So when using the internal regulator and stop mode with 5 V power supply, never fail to support externally so

that 3 V power supply voltage might not decrease. However, even in such a case, the internal regulator can be

restarted by inputting the reset procedure. (In this case, set the reset to “L” level within the oscillation stabilizing

waiting time.)

• Using STOP mode with 5 V power supply

5 V

VCC5

3.6 kΩ

V^CC3

6.8 kΩ

0.1 µF

approx.

V^SS

12. Turning on the Power Supply

When turning on the power supply, never fail to start from setting the RST pin to “L” level. And after the power

supply voltage goes to V^CClevel, at least after ensuring the time for 5 machine cycle, then set to “H” level.

13. Pin Condition at Turning on the Power Supply

The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning on

the power supply and then starting oscillation and then the operation of the internal regulator becomes stable.

So it takes about 42 ms for the pin to be initialized from the oscillation starting at the source oscillation 12.5

MHz. Take care that the pin condition may be output condition at initial unstable condition.

(With the MB91101A, however, initalization can be achieved in less than about 42 ms after turning on the

internal power supply by maintaining the RST pin at "L" level.)

18

MB91101/MB91101A

14. Source Oscillation Input at Turning on the Power Supply

At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing

waiting.

15. Hardware Stand-by at Turning on the Power Supply

When turning on the power supply with the HST pin being set to “L” level, the hardware doesn’t stand by.

However the HST pin becomes available after the reset cancellation, the HSTpin must once be back to “H” level.

16. Power on Reset

Make sure to make power on reset at turning on the power supply or returning on the power supply when the

power supply voltage is below the warranty range for normal operation.

19

MB91101/MB91101A

■ BLOCK DIAGRAM

FR CPU

RAM (2 Kbytes)

Bit search module

Instruction cache (1 Kbyte)

3

DREQ0 to

DREQ2

Bus converter

(Harvard↔Princeton)

3

DMA controller (DMAC)

(8 ch.)

DACK0 to

DACK2

EOP0 to

EOP2

Bus converter (32 bits↔16 bits)

16

25

D16 to D31

A00 to A24

RD

WR0, WR1

RDY

CLK

CS0 to CS5

BRQ

X0

X1

RST

HST

Clock control unit

(Watchdog timer)

2

6

Bus controller

4

INT0 to INT3

NMI

BGRNT

Interrupt control unit

4

AN0 to AN3

AV^CC

RAS0

RAS1

CS0L

CS0H

CS1L

CS1H

DW0

AVSS /AVRL

AVRH

10-bit A/D converter

(4 ch.)

DRAM controller

ATG

DW1

Reload timer (3 ch.)

Port 0 to port B

Port

3

SI0 to SI2

SO0 to SO2

SC0 to SC2

UART (3 ch.)

(Baud rate timer)

Other pins

MD0 to MD2, P20 to P27, P60 to P67,

P80 to P82, P85, PA1 to PA6,

PB0 to PB7, PE0 to PE7, PF0 to PF7,

V

CC3, VCC5, VSS

4

OCPA0 to OCPA3

TRG0 to TRG3

PWM timer (4 ch.)

Note: Pins are display for functions (Actually some pins are multiplexer).

When using REALOS, time control should be done by using external interrupt or inner timer.

20

MB91101/MB91101A

■ CPU CORE

1. Memory Space

The FR family has a logical address space of 4 Gbytes (2³²bytes) and the CPU linearly accesses the memory

space.

• Memory space

Address

External ROM/external bus mode

I/O area

0000 0000^H

Direct addressing area

0000 0400^H

See “■ I/O MAP”

I/O area

0000 0800^H

0000 1000^H

0000 1800^H

Access inhibited

Embedded RAM

Access inhibited

0001 0000^H

External area

FFFF FFFF^H

• Direct addressing area

The following areas on the memory space are assigned to direct addressing area for I/O. In these areas, an

address can be specified in a direct operand of a code.

Direct areas consists of the following areas dependent on accessible data sizes.

Byte data access: 000^Hto 0FF^H

Half word data access: 000^Hto 1FF^H

Word data access: 000^Hto 3FF^H

21

MB91101/MB91101A

2. Registers

The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose

registers on memory.

• Dedicated registers

Program counter (PC):

Program status (PS):

32-bit length, indicates the location of the instruction to be executed.

32-bit length, register for storing register pointer or condition codes

Table base register (TBR): Holds top address of vector table used in EIT (Exceptional/Interrupt/Trap)

processing.

Return pointer (RP):

Holds address to resume operation after returning from a subroutine.

System stack pointer (SSP): Indicates system stack space.

User's stack pointer (USP): Indicates user’s stack space.

Multiplication/division result register (MDH/MDL): 32-bit length, register for multiplication/division

32 bits

Initial value

Program counter

Program status

XXXX XXXX^H

Indeterminate

PC

PS

Table base register

Return pointer

000F FC00^H

XXXX XXXX^H

0000 0000^H

XXXX XXXX^H

TBR

RP

Indeterminate

System stack pointer

User’s stack pointer

SSP

USP

MDH

MDL

XXXX XXXX^H

Indeterminate

Multiplication/division result register

• Program status (PS)

The PS register is for holding program status and consists of a condition code register (CCR), a system condition

code register (SCR) and a interrupt level mask register (ILM).

31 to 21 20

19

18

17

16 11 to 15 10

D1

9

8

T

7

6

5

4

I

3

2

Z

1

0

PS

—

ILM4 ILM3 ILM2 ILM1 ILM0

ILM

—

D0

—

S

N

V

C

SCR

CCR

22

MB91101/MB91101A

• Condition code register (CCR)

S-flag:

I-flag:

Specifies a stack pointer used as R15.

Controls user interrupt request enable/disable.

N-flag:

Z-flag:

V-flag:

Indicates sign bit when division result is assumed to be in the 2’s complement format.

Indicates whether or not the result of division was “0”.

Assumes the operand used in calculation in the 2’s complement format and indicates whether

or not overflow has occurred.

C-flag:

Indicates if a carry or borrow from the MSB has occurred.

• System condition code register (SCR)

T-flag:

Specifies whether or not to enable step trace trap.

• Interrupt level mask register (ILM)

ILM4 to ILM0: Register for holding interrupt level mask value. The value held by this register is used as a

level mask. When an interrupt request issued to the CPU is higher than the level held by ILM,

the interrupt request is accepted.

ILM4

ILM3

ILM2

ILM1

ILM0

Interrupt level

High-low

0

High

:

0

1

0

1

0

1

15

:

1

31

Low

23

MB91101/MB91101A

■ GENERAL-PURPOSE REGISTERS

R0 to R15 are general-purpose registers embedded on the CPU. These registers functions as an accumulator

and a memory access pointer (field for indicating address).

• Register bank structure

32 bits

Initial value

R0

R1

XXXX XXXX^H

:

R12

R13

R14

R15

AC (accumulator)

FP (frame pointer)

SP (stack pointer)

XXXX XXXX^H

0 000 0 000^H

Of the above 16 registers, following registers have special functions. To support the special functions, part of

the instruction set has been sophisticated to have enhanced functions.

R13: Virtual accumulator (AC)

R14: Frame pointer (FP)

R15: Stack pointer (SP)

Upon reset, values in R0 to R14 are not fixed. Value in R15 is initialized to be 0000 0000^H(SSP value).

24

MB91101/MB91101A

■ SETTING MODE

1. Pin

• Mode setting pins and modes

Mode setting

Reset vector

access area

External data

bus width

pins

Mode name

Bus mode

MD2 MD1 MD0

0

1

0

1

External vector mode 0

External

—

8 bits

16 bits

—

External ROM/external bus

mode

External vector mode 1

1

0

—

Inhibited

1

Internal vector mode

—

Internal

—

(Mode register) Single-chip mode*

Inhibited

—

* : MB91101 does not support single-chip mode.

2. Registers

• Mode setting registers (MODR) and modes

Address

Initial value

Access

W

0000 07FF^H

M1

M0

XXXX XXXX^B

*

Bus mode setting bit

W : Write only

X : Indeterminate

: Always write “0” except for M1 and M0.

*

• Bus mode setting bits and functions

M1

0

M0

0

Functions

Note

Single-chip mode

Internal ROM/external bus mode

0

1

0

External ROM/external bus mode

—

1

Inhibited

Note: Because of without internal ROM, MB91101 allows “10^B” setting value only.

25

MB91101/MB91101A

■ I/O MAP

Register name

Address

Register name

(Vacancy)

Read/write

Initial value

(abbreviated)

0000^H

0001^H

PDR2

PDR6

Port 2 data register

R/W

X X X X X X X X ^B

0002^H

to

0004^H

(Vacancy)

0005^H

0006^H

0007^H

0008^H

0009^H

000A^H

000B^H

Port 6 data register

R/W

X X X X X X X X ^B

PDRB

PDRA

Port B data register

Port A data register

R/W

X X X X X X X X ^B

– X X X X X X – ^B

(Vacancy)

PDR8

Port 8 data register

R/W

– – X – – X X X ^B

000C^H

to

0011^H

0012^H

0013^H

PDRE

PDRF

Port E data register

Port F data register

R/W

X X X X X X X X ^B

0014^H

to

(Vacancy)

001B^H

001C^H

001D^H

001E^H

001F^H

0020^H

0021^H

0022^H

0023^H

0024^H

0025^H

0026^H

0027^H

SSR0

Serial status register 0

R/W

0 0 0 0 1 – 0 0 ^B

X X X X X X X X ^B

0 0 0 0 0 1 0 0 ^B

0 0 – – 0 – 0 0 ^B

0 0 0 0 1 – 0 0 ^B

X X X X X X X X ^B

0 0 0 0 0 1 0 0 ^B

0 0 – – 0 – 0 0 ^B

0 0 0 0 1 – 0 0 ^B

X X X X X X X X ^B

0 0 0 0 0 1 0 0 ^B

0 0 – – 0 – 0 0 ^B

SIDR0/SODR0

SCR0

Serial input register 0/serial output register 0

Serial control register 0

SMR0

Serial mode register 0

SSR1

Serial status register 1

SIDR1/SODR1

SCR1

Serial input register 1/serial output register 1

Serial control register 1

SMR2

Serial mode register 1

SSR2

Serial status register 2

SIDR2/SODR2

SCR2

Serial input register 2/serial output register 2

Serial control register 2

SMR2

Serial mode register 2

(Continued)

26

MB91101/MB91101A

Register name

(abbreviated)

Address

Register name

Read/write

Initial value

0028^H

0029^H

002A^H

002B^H

002C^H

002D^H

002E^H

002F^H

0030^H

0031^H

0032^H

0033^H

0034^H

0035^H

0036^H

0037^H

0038^H

0039^H

003A^H

003B^H

003C^H

003D^H

003E^H

003F^H

0040^H

0041^H

0042^H

0043^H

X X X X X X X X ^B

TMRLR0

TMR0

16-bit reload register ch. 0

W

16-bit timer register ch. 0

R

(Vacancy)

– – – – 0 0 0 0 ^B

0 0 0 0 0 0 0 0 ^B

X X X X X X X X ^B

16-bit reload timer control status register

ch. 0

TMCSR0

TMRLR1

TMR1

R/W

W

16-bit reload register ch. 1

16-bit timer register ch. 1

(Vacancy)

R

– – – – 0 0 0 0 ^B

0 0 0 0 0 0 0 0 ^B

– – – – – – X X ^B

X X X X X X X X ^B

0 0 0 0 0 0 0 0 ^B

X X X X X X X X ^B

16-bit reload timer control status register

ch. 1

TMCSR1

ADCR

R/W

R

A/D converter data register

A/D converter control status register

16-bit reload register ch. 2

16-bit timer register ch. 2

(Vacancy)

ADCS

R/W

W

TMRLR2

TMR2

R

– – – – 0 0 0 0 ^B

0 0 0 0 0 0 0 0 ^B

16-bit reload timer control status register

ch. 2

TMCSR2

R/W

0044^H

to

(Vacancy)

0077^H

(Continued)

27

MB91101/MB91101A

Register name

Address

Register name

Read/write

Initial value

(abbreviated)

0078^H

0 0 0 0 0 0 0 0 ^B

UTIM0/UTIMR0 U-TIMER register ch. 0/reload register ch. 0

R/W

0079^H

007A^H

007B^H

007C^H

007D^H

007E^H

007F^H

0080^H

0081^H

0082^H

0083^H

(Vacancy)

UTIMC0

U-TIMER control register ch. 0

R/W

0 – – 0 0 0 0 1 ^B

0 0 0 0 0 0 0 0 ^B

UTIM1/UTIMR1 U-TIMER register ch. 1/reload register ch. 1

(Vacancy)

UTIMC1

U-TIMER control register ch. 1

R/W

0 – – 0 0 0 0 1 ^B

0 0 0 0 0 0 0 0 ^B

UTIM2/UTIMR2 U-TIMER register ch. 2/reload register ch. 0

(Vacancy)

UTIMC2

U-TIMER control register ch. 2

(Vacancy)

R/W

0 – – 0 0 0 0 1 ^B

0084^H

to

0093^H

0094^H

0095^H

EIRR

ENIR

External interrupt cause register

Interrupt enable register

R/W

0 0 0 0 0 0 0 0 ^B

0096^H

to

(Vacancy)

0098^H

External interrupt request level setting

register

0099^H

ELVR

R/W

0 0 0 0 0 0 0 0 ^B

009A^H

to

(Vacancy)

00D1^H

00D2^H

00D3^H

DDRE

DDRF

Port E data direction register

Port F data direction register

W

0 0 0 0 0 0 0 0 ^B

00D4^H

to

(Vacancy)

00DB^H

00DC^H

00DD^H

00DE^H

00DF^H

0 0 1 1 0 0 1 0 ^B

0 0 0 1 0 0 0 0 ^B

GCN1

GCN2

General control register 1

R/W

(Vacancy)

General control register 2

0 0 0 0 0 0 0 0 ^B

(Continued)

28

MB91101/MB91101A

Register name

(abbreviated)

Address

Register name

Read/write

Initial value

00E0^H

00E1^H

00E2^H

00E3^H

00E4^H

00E5^H

00E6^H

00E7^H

00E8^H

00E9^H

00EA^H

00EB^H

00EC^H

00ED^H

00EE^H

00EF^H

00F0^H

00F1^H

00F2^H

00F3^H

00F4^H

00F5^H

00F6^H

00F7^H

00F8^H

00F9^H

00FA^H

00FB^H

00FC^H

00FD^H

00FE^H

00FF^H

1 1 1 1 1 1 1 1 ^B

X X X X X X X X ^B

0 0 0 0 0 0 0 – ^B

0 0 0 0 0 0 0 0 ^B

1 1 1 1 1 1 1 1 ^B

X X X X X X X X ^B

0 0 0 0 0 0 0 – ^B

0 0 0 0 0 0 0 0 ^B

1 1 1 1 1 1 1 1 ^B

X X X X X X X X ^B

0 0 0 0 0 0 0 – ^B

0 0 0 0 0 0 0 0 ^B

1 1 1 1 1 1 1 1 ^B

X X X X X X X X ^B

0 0 0 0 0 0 0 – ^B

0 0 0 0 0 0 0 0 ^B

(Continued)

PTMR0

PCSR0

PDUT0

Ch. 0 timer register

R

Ch. 0 cycle setting register

Ch. 0 duty setting register

W

PCNH0

PCNL0

Ch. 0 control status register H

Ch. 0 control status register L

R/W

PTMR1

PCSR1

PDUT1

Ch. 1 timer register

R

W

Ch. 1 cycle setting register

Ch. 1 duty setting register

PCNH1

PCNL1

Ch. 1 control status register H

Ch. 1 control status register L

R/W

PTMR2

PCSR2

PDUT2

Ch. 2 timer register

R

W

Ch. 2 cycle setting register

Ch. 2 duty setting register

PCNH2

PCNL2

Ch. 2 control status register H

Ch. 2 control status register L

R/W

PTMR3

PCSR3

PDUT3

Ch. 3 timer register

R

W

Ch. 3 cycle setting register

Ch. 3 duty setting register

PCNH3

PCNL3

Ch. 3 control status register H

Ch. 3 control status register L

R/W

29

MB91101/MB91101A

Register name

Address

Register name

Read/write

Initial value

(abbreviated)

0100^H

to

(Vacancy)

01FF^H

0200^H

0201^H

X X X X X X X X ^B

X 0 0 0 0 0 0 0 ^B

0 0 0 0 0 0 0 0 ^B

X X X X X X X X ^B

X X X X 0 0 0 0 ^B

DPDP

DMAC parameter descriptor pointer

DMAC control status register

R/W

0202^H

0203^H

0204^H

0205^H

0206^H

0207^H

0208^H

0209^H

020A^H

020B^H

DACSR

DATCR

DMAC pin control register

020C^H

to

(Vacancy)

03E3^H

03E4^H

03E5^H

03E6^H

03E7^H

– – – – – – – – ^B

– – 0 0 0 0 0 0 ^B

ICHCR

Instruction cache control register

R/W

03E8^H

to

(Vacancy)

03EF^H

03F0^H

03F1^H

03F2^H

03F3^H

03F4^H

03F5^H

03F6^H

03F7^H

X X X X X X X X ^B

(Continued)

BSD0

BSD1

Bit search module 0-detection data register

W

Bit search module 1-detection data register

R/W

30

MB91101/MB91101A

Register name

(abbreviated)

Address

Register name

Read/write

Initial value

03F8^H

03F9^H

03FA^H

03FB^H

03FC^H

03FD^H

03FE^H

03FF^H

0400^H

0401^H

0402^H

0403^H

0404^H

0405^H

0406^H

0407^H

0408^H

0409^H

040A^H

040B^H

040C^H

040D^H

040E^H

040F^H

0410^H

0411^H

0412^H

0413^H

0414^H

0415^H

0416^H

X X X X X X X X ^B

– – – 1 1 1 1 1 ^B

(Continued)

Bit search module transition-detection data

register

BSDC

BSRR

W

Bit search module detection result register

R

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

ICR16

ICR17

ICR18

ICR19

ICR20

ICR21

ICR22

Interrupt control register 0

Interrupt control register 1

Interrupt control register 2

Interrupt control register 3

Interrupt control register 4

Interrupt control register 5

Interrupt control register 6

Interrupt control register 7

Interrupt control register 8

Interrupt control register 9

Interrupt control register 10

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

Interrupt control register 14

Interrupt control register 15

Interrupt control register 16

Interrupt control register 17

Interrupt control register 18

Interrupt control register 19

Interrupt control register 20

Interrupt control register 21

Interrupt control register 22

R/W

31

MB91101/MB91101A

Register name

Address

Register name

Read/write

Initial value

(abbreviated)

0417^H

0418^H

0419^H

041A^H

041B^H

041C^H

041D^H

041E^H

041F^H

042F^H

0430^H

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

ICR47

DICR

Interrupt control register 23

Interrupt control register 24

Interrupt control register 25

Interrupt control register 26

Interrupt control register 27

Interrupt control register 28

Interrupt control register 29

Interrupt control register 30

Interrupt control register 31

Interrupt control register 47

Delayed interrupt control register

R/W

– – – 1 1 1 1 1 ^B

– – – – – – – 0 ^B

Hold request cancel request level setting

register

0431^H

HRCL

R/W

– – – 1 1 1 1 1 ^B

0432^H

to

(Vacancy)

047F^H

Reset cause register/

watchdog peripheral control register

0480^H

RSRR/WTCR

R/W

1XX X X – 0 0 ^B

0481^H

0482^H

0483^H

0484^H

STCR

PDRR

CTBR

GCR

Standby control register

R/W

W

0 0 0 1 1 1 – – ^B

– – – – 0 0 0 0 ^B

X X X X X X X X ^B

1 1 0 0 1 1 – 1 ^B

DMA controller request squelch register

Timebase timer clear register

Gear control register

R/W

Watchdog reset occurrence postpone

register

0485^H

WPR

W

R/W

W

X X X X X X X X ^B

0 0 – – 0 – – – ^B

0 0 0 0 0 0 0 0 ^B

0486^H

0487^H

0488^H

(Vacancy)

PCTR

DDR2

DDR6

PLL control register

0489^H

to

0600^H

(Vacancy)

Port 2 data direction register

(Vacancy)

0601^H

0602^H

to

0604^H

0605^H

0606^H

0607^H

Port 6 data direction register

(Vacancy)

W

0 0 0 0 0 0 0 0 ^B

(Continued)

32

MB91101/MB91101A

Register name

(abbreviated)

Address

Register name

Read/write

Initial value

0608^H

0609^H

060A^H

060B^H

060C^H

060D^H

060E^H

060F^H

0610^H

0611^H

0612^H

0613^H

0614^H

0615^H

0616^H

0617^H

0618^H

0619^H

061A^H

061B^H

061C^H

061D^H

061E^H

061F^H

0620^H

0621^H

0622^H

0623^H

0624^H

0625^H

0626^H

0627^H

DDRB

DDRA

Port B data direction register

Port A data direction register

W

0 0 0 0 0 0 0 0 ^B

– 0 0 0 0 0 0 – ^B

(Vacancy)

DDR8

ASR1

Port 8 data direction register

W

– – 0 – – 0 0 0 ^B

0 0 0 0 0 0 0 0 ^B

0 0 0 0 0 0 0 1 ^B

0 0 0 0 0 0 0 0 ^B

0 0 0 0 0 0 1 0 ^B

0 0 0 0 0 0 0 0 ^B

0 0 0 0 0 0 1 1 ^B

0 0 0 0 0 0 0 0 ^B

0 0 0 0 0 1 0 0 ^B

0 0 0 0 0 0 0 0 ^B

0 0 0 0 0 1 0 1 ^B

0 0 0 0 0 0 0 0 ^B

– – – 0 0 1 1 1 ^B

0 – – 0 0 0 0 0 ^B

0 0 0 0 0 0 0 0 ^B

0 – – 0 0 0 0 0 ^B

0 0 0 0 0 0 0 0 ^B

– – X X X X X X ^B

0 0 – – – 0 0 0 ^B

(Continued)

Area select register 1

AMR1

ASR2

AMR2

ASR3

AMR3

ASR4

AMR4

ASR5

AMR5

Area mask register 1

Area select register 2

Area mask register 2

Area select register 3

Area mask register 3

Area select register 4

Area mask register 4

Area select register 5

Area mask register 5

W

AMD0

AMD1

AMD32

AMD4

AMD5

DSCR

Area mode register 0

Area mode register 1

Area mode register 32

Area mode register 4

Area mode register 5

DRAM signal control register

R/W

W

RFCR

Refresh control register

R/W

33

MB91101/MB91101A

(Continued)

Register name

Address

Register name

Read/write

Initial value

(abbreviated)

0628^H

– – – – 1 1 0 0 ^B

– 1 1 1 1 1 1 1 ^B

EPCR0

External pin control register 0

(Vacancy)

W

0629^H

062A^H

062B^H

062C^H

062D^H

062E^H

062F^H

EPCR1

DMCR4

External pin control register 1

W

1 1 1 1 1 1 1 1 ^B

0 0 0 0 0 0 0 0 ^B

0 0 0 0 0 0 0 – ^B

0 0 0 0 0 0 0 0 ^B

0 0 0 0 0 0 0 – ^B

DRAM control register 4

R/W

DMCR5

DRAM control register 5

R/W

0630^H

to

(Vacancy)

07FD^H

07FE^H

07FF^H

LER

Little endian register

Mode register

W

– – – – – 0 0 0 ^B

X X X X X X X X ^B

MODR

Note: Do not use (vacancy).

34

MB91101/MB91101A

■ INTERRUPT CAUSES, INTERRUPT VECTORS

AND INTERRUPT CONTROL REGISTER ALLOCATIONS

Interrupt number

Interrupt causes

Interrupt level

Register

TBR default

address

Decimal

0

Hexadecimal

Offset

3FC^H

3F8^H

3F4^H

3F0^H

3EC^H

3E8^H

3E4^H

3E0^H

3DC^H

3D8^H

3D4^H

3D0^H

3CC^H

3C8^H

3C4^H

3C0^H

3BC^H

3B8^H

3B4^H

3B0^H

3AC^H

3A8^H

3A4^H

3A0^H

39C^H

398^H

394^H

390^H

38C^H

388^H

384^H

380^H

Reset

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

—

000FFFFC^H

000FFFF8^H

000FFFF4^H

000FFFF0^H

000FFFEC^H

000FFFE8^H

000FFFE4^H

000FFFE0^H

000FFFDC^H

000FFFD8^H

000FFFD4^H

000FFFD0^H

000FFFCC^H

000FFFC8^H

000FFFC4^H

000FFFC0^H

000FFFBC^H

000FFFB8^H

000FFFB4^H

000FFFB0^H

000FFFAC^H

000FFFA8^H

000FFFA4^H

000FFFA0^H

000FFF9C^H

000FFF98^H

000FFF94^H

000FFF90^H

000FFF8C^H

000FFF88^H

000FFF84^H

000FFF80^H

(Continued)

Reserved for system

Exception for undefined instruction

NMI request

1

2

—

3

—

4

—

5

—

6

—

7

—

8

—

9

—

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

—

F^Hfixed

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

External interrupt 0

External interrupt 1

External interrupt 2

External interrupt 3

UART0 receive complete

UART1 receive complete

UART2 receive complete

UART0 transmit complete

UART1 transmit complete

UART2 transmit complete

DMAC0 (complete, error)

DMAC1 (complete, error)

DMAC2 (complete, error)

DMAC3 (complete, error)

DMAC4 (complete, error)

DMAC5 (complete, error)

35

MB91101/MB91101A

Interrupt number

Interrupt level

TBR default

address

Interrupt causes

Decimal

32

Hexadecimal

Register

Offset

37C^H

378^H

DMAC6 (complete, error)

DMAC7 (complete, error)

20

21

ICR16

ICR17

000FFF7C^H

000FFF78^H

33

A/D converter (successive

approximation conversion type)

34

22

ICR18

374^H

000FFF74^H

16-bit reload timer 0

16-bit reload timer 1

16-bit reload timer 2

PWM 0

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

ICR32

ICR33

ICR34

ICR35

ICR36

ICR37

ICR38

ICR39

ICR40

ICR41

ICR42

ICR43

ICR44

ICR45

ICR46

ICR47

370^H

36C^H

368^H

364^H

360^H

35C^H

358^H

354^H

350^H

34C^H

348^H

344^H

340^H

33C^H

338^H

334^H

330^H

32C^H

328^H

324^H

320^H

31C^H

318^H

314^H

310^H

30C^H

308^H

304^H

300^H

000FFF70^H

000FFF6C^H

000FFF68^H

000FFF64^H

000FFF60^H

000FFF5C^H

000FFF58^H

000FFF54^H

000FFF50^H

000FFF4C^H

000FFF48^H

000FFF44^H

000FFF40^H

000FFF3C^H

000FFF38^H

000FFF34^H

000FFF30^H

000FFF2C^H

000FFF28^H

000FFF24^H

000FFF20^H

000FFF1C^H

000FFF18^H

000FFF14^H

000FFF10^H

000FFF0C^H

000FFF08^H

000FFF04^H

000FFF00^H

(Continued)

PWM 1

PWM 2

PWM 3

U-TIMER 0

U-TIMER 1

U-TIMER 2

Reserved for system

Delayed interrupt cause bit

36

MB91101/MB91101A

(Continued)

Interrupt causes

Interrupt number

Decimal Hexadecimal

Interrupt level

TBR default

address

Register

Offset

Reserved for system (used in

REALOS*)

64

40

—

2FC^H

000FFEFC^H

000FFEF8^H

Reserved for system (used in

REALOS*)

65

41

2F8^H

66

to

255

42

to

FF

2F4^H

to

000^H

000FFEF4^H

to

000FFC00^H

Used in INT instructions

—

* : When using in REALOS/FR, interrupt 0x40, 0x41 for system code.

37

MB91101/MB91101A

■ PERIPHERAL RESOURCES

1. I/O Ports

There are 2 types of I/O port register structure; port data register (PDR0 to PDRF) and data direction register

(DDR0 to DDRF), where bits PDR0 to PDRF and bits DDR0 to DDRF corresponds respectively. Each bit on

the register corresponds to an external pin. In port registers input/output register of the port configures input/

output function of the port, while corresponding bit (pin) configures input/output function in data direction

registers. Bit “0” specifies input and “1” specifies output.

• For input (DDR = “0”) setting;

PDR reading operation: reads level of corresponding external pin.

PDR writing operation: writes set value to PDR.

• For output (DDR = “1”) setting;

PDR reading operation: reads PDR value.

PDR writing operation: outputs PDR value to corresponding external pin.

• Block diagram

Resource input

0

1

PDR read

0

1

PDR

(Port data register)

Resource output

Resource output enable

DDR

(Data direction register)

38

MB91101/MB91101A

• Port data register

Address

000001^H

Initial value

bit 0

bit 7

X X X X X X X X ^B

- - X - - X X X ^B

(R/W)

PDR2

PDR6

PDR8

PDRA

PDRB

PDRE

PDRF

000005^H

00000B^H

000009^H

000008^H

000012^H

000013^H

- X X X X X X -

B

X X X X X X X X ^B

( ) : Access

R/W : Readable and writable

: Indeterminate

X

• Data direction register

Address

bit 7

Initial value

bit 0

000601^H

000605^H

00060B^H

000609^H

000608^H

0000D2^H

0000D3^H

0 0 0 0 0 0 0 0

- - 0 - - 0 0 0

- 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

B

(W)

DDR2

DDR6

DDR8

DDRA

DDRB

DDRE

DDRF

( ) : Access

W : Write only

– : Unused

39

MB91101/MB91101A

2. DMA Controller (DMAC)

The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access)

transfer.

DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to

enhanced performance of the system.

• 8 channels

• Mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer

• Transfer all through the area

• Max. 65536 of transfer cycles

• Interrupt function right after the transfer

• Selectable for address transfer increase/decrease by the software

• External transfer request input pin, external transfer request accept output pin, external transfer complete

output pin three pins for each

• Block diagram

3

5

3

Edge/level

detection circuit

DREQ0 to DREQ2

DACK0 to DACK2

EOP0 to EOP2

Interrupt request

3

8

Sequencer

Inner resource

Transfer request

Data buffer

Switcher

DPDP

DACSR

DATCR

Mode

BLK DEC

BLK

DMACT

SADR

DADR

INC / DEC

40

MB91101/MB91101A

• Registers (DMAC internal registers)

Address

Initial value

00000200^H

00000201^H

00000202^H

00000203^H

X X X X X X X X ^B

bit 0

bit 31

bit 16

X X X X X X X X ^B

DPDP

(R/W)

X X X X X X X X ^B

X 0 0 0 0 0 0 0

B

00000204^H

00000205^H

00000206^H

00000207^H

0 0 0 0 0 0 0 0

B

DACSR

DATCR

(R/W)

00000208^H

00000209^H

0000020A^H

0000020B^H

X X X X X X X X ^B

X X X X 0 0 0 0

B

( ) : Access

R/W : Readable and writable

: Indeterminate

X

• Registers (DMA descriptor)

Address

bit 31

bit 0

DMA

DPDP + 0^H

ch.0

Descriptor

DMA

DPDP + 0C^H

DPDP + 54^H

ch.1

Descriptor

DMA

ch.7

Descriptor

41

MB91101/MB91101A

3. UART

The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK

synchronous communication, and it has the following features.

The MB91101 consists of 3 channels of UART.

• Full double double buffer

• Both a synchronous (start-stop system) communication and CLK synchronous communication are available.

• Supporting multi-processor mode

• Perfect programmable baud rate

Any baud rate can be set by internal timer (refer to section “4. U-TIMER”).

• Any baud rate can be set by external clock.

• Error checking function (parity, framing and overrun)

• Transfer signal: NRZ code

• Enable DMA transfer/start by interrupt.

42

MB91101/MB91101A

• Block diagram

Control signals

Receive interrupt

(to CPU)

SC (clock)

Transmit interrupt

(to CPU)

Transmit clock

From U-TIMER

Clock select

circuit

Receive clock

From external clock

SC

Receive control circuit

Transmit control circuit

Start bit detect

circuit

Transmit start

circuit

SI

(receive data)

Receive bit counter

Transmit bit counter

Receive parity

counter

Transmit parity

counter

SO (transmit data)

Transmit shifter

Receive status

judge circuit

Receive shifter

Receive

complete

Transmit

start

Receive error

generate signal

for DMA

SODR

SIDR

(to DMAC)

R-bus

MD1

MD0

PEN

P

PE

ORE

SMR

register

SCR

register

SBL

CL

SSR

register

FRE

RDRF

TDRE

CS0

A/D

REC

RXE

TXE

SCKE

SOE

RIE

TIE

Control signals

43

MB91101/MB91101A

• Register configuration

Address

bit 15

Initial value

bit 8

bit 0

0000001E^H

00000022^H

00000026^H

0000001F^H

00000023^H

00000027^H

0000001C^H

00000020^H

00000024^H

0000001D^H

00000021^H

00000002^H

SCR0

SCR1

SCR2

0 0 0 0 0 1 0 0

0 0 - - 0 - 0 0

0 0 0 0 1 - 0 0

B

(R/W)

SMR0

SMR1

SMR2

SSR0

SSR1

SSR2

X X X X X X X X ^B(R/W)

SIDR0/SODR0

SIDR1/SIDR1

SIDR2/SIDR2

( ) : Access

R/W : Readable and writable

–

: Unused

X

: Indeterminate

44

MB91101/MB91101A

4. U-TIMER (16-bit Timer for UART Baud Rate Generation)

The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and

reload value of U-TIMER allows flexible setting of baud rate.

The U-TIMER operates as an interval timer by using interrupt issued on counter underflow.

The MB91101 has 3 channel U-TIMER embedded on the chip. An interval of up to 2¹⁶× φ can be counted.

• Block diagram

bit 15

bit 0

UTIMR (reload register)

Load

bit 15

bit 0

UTIM ( U-TIMER register)

Underflow

Clock

φ

Control

(Peripheral clock)

f.f.

To UART

• Register configuration

Address

Initial value

bit 15

bit 0

(R/W)

0 0 0 0 0 0 0 0

B

00000078^H

00000079^H

UTIM0/UTIMR0

UTIM1/UTIMR1

UTIM2/UTIMR2

0 0 0 0 0 0 0 0

B

0000007C^H

0000007D^H

0 0 0 0 0 0 0 0

B

00000080^H

00000081^H

(R/W)

0 - - 0 0 0 0 1

B

UTIMC0

UTIMC1

UTIMC2

0000007B^H

0000007F^H

00000083^H

( ) : Access

R/W : Readable and writable

–

: Unused

45

MB91101/MB91101A

5. PWM Timer

The PWM timer can output high accurate PWM waves efficiently.

MB91101 has inner 4-channel PWM timers, and has the following features.

• Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for scyde setting, a 16-

bit compare resister with a buffer for duty setting, and a pin controller.

• The count clock of a 16-bit down counter can be selected from the following four inner clocks.

Inner clock φ, φ/4, φ/16, φ/64

• The counter value can be initialized “FFFF^H” by the resetting or the counter borrow.

• PWM output (each channel)

• Resister description

• Block diagram (general construction)

16-bit reload timer

ch.0

TRG input

PWM timer ch.0

PWM0

PWM1

16-bit reload timer

ch.1

TRG input

PWM timer ch.1

General control

register 1

(cause selection)

4

General control

register 2

TRG input

PWM timer ch.2

PWM2

PWM3

TRG input

PWM timer ch.3

External TRG0 to TRG3

46

MB91101/MB91101A

• Block diagram (for one channel)

PCSR

PDUT

Prescaler

1 / 1

cmp

1 / 4

1 / 16

1 / 64

ck

Load

16-bit down counter

Start

Borrow

PPG mask

S

R

Q

PWM output

Peripheral clock

Reverse bit

Enable

IRQ

Edge detect

Soft trigger

TRG input

47

MB91101/MB91101A

• Register configuration

Address

bit 15

Initial value

bit 8

bit 0

000000DC^H

000000DD^H

0 0 1 1 0 0 1 0

0 0 0 1 0 0 0 0

B

(R/W)

(R)

GCN1

000000DF^H

0 0 0 0 0 0 0 0

B

GCN2

PCNL0

PCNL1

PCNL2

000000E0^H

000000E1^H

1 1 1 1 1 1 1 1

B

PTMR0

PCSR0

PDUT0

000000E2^H

000000E3^H

X X X X X X X X ^B

(W)

000000E4^H

000000E5^H

X X X X X X X X ^B

(W)

000000E6^H

000000E7^H

0 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

B

(R/W)

PCNH0

PCNH1

PCNH2

B

(R/W)

(R)

000000E8^H

000000E9^H

1 1 1 1 1 1 1 1

B

PTMR1

PCSR1

PDUT1

000000EA^H

000000EB^H

X X X X X X X X ^B

(W)

000000EC^H

000000ED^H

X X X X X X X X ^B

(W)

000000EE^H

000000EF^H

0 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

B

(R/W)

B

(R/W)

(R)

1 1 1 1 1 1 1 1

B

000000F0^H

000000F1^H

PTMR2

PCSR2

PDUT2

X X X X X X X X ^B

000000F2^H

000000F3^H

(W)

X X X X X X X X ^B

000000F4^H

000000F5^H

(W)

0 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

B

(R/W)

000000F6^H

000000F7^H

B

(R/W)

(R)

1 1 1 1 1 1 1 1

B

000000F8^H

000000F9^H

PTMR3

PCSR3

PDUT3

X X X X X X X X ^B

000000FA^H

000000FB^H

(W)

X X X X X X X X ^B

000000FC^H

000000FD^H

(W)

0 0 0 0 0 0 0 -

B

(R/W)

000000FE^H

000000FF^H

PCNH3

0 0 0 0 0 0 0 0

B

(R/W)

PCNL3

( ) : Access

R/W : Readable and writable

R

W

–

: Read only

: Write only

: Unused

X

: Indeterminate

48

MB91101/MB91101A

6. 16-bit Reload Timer

The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating

internal count clock and control registers.

Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock).

The DMA transfer can be started by the interruption.

The MB91101 consists of 3 channels of the 16-bit reload timer.

• Block diagram

16

16-bit reload register

8

Reload

RELD

16

16-bit down counter UF

OUTE

OUTL

INTE

UF

2

OUT

CTL.

GATE

2

IRQ

CSL1

Clock selector

CNTE

TRG

CSL0

2

Retrigger

IN CTL.

EXCK

PWM (ch.0, ch.1)

A/D (ch.2)

3

φ

Prescaler

clear

–

2¹2³2⁵

MOD2

MOD1

MOD0

Internal clock

3

49

MB91101/MB91101A

• Register configuration

Address

bit 15

Initial value

bit 0

- - - - 0 0 0 0

0 0 0 0 0 0 0 0

B

0000002E^H

0000002F^H

TMCSR0

TMCSR1

TMCSR2

TMR0

(R/W)

(R)

- - - - 0 0 0 0

0 0 0 0 0 0 0 0

B

00000036^H

00000037^H

- - - - 0 0 0 0

0 0 0 0 0 0 0 0

B

00000042^H

00000043^H

X X X X X X X X ^B

0000002A^H

0000002B^H

X X X X X X X X ^B

00000032^H

00000033^H

(R)

TMR1

X X X X X X X X ^B

0000003E^H

0000003F^H

TMR2

(R)

X X X X X X X X ^B

00000028^H

00000029^H

TMRLR0

TMRLR1

TMRLR2

(W)

X X X X X X X X ^B

00000030^H

00000031^H

X X X X X X X X ^B

0000003C^H

0000003D^H

( ) : Access

R/W : Readable and writable

R

W

–

: Read only

: Write only

: Unused

X

: Indeterminate

50

MB91101/MB91101A

7. Bit Search Module

The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and

returns locations of the transitions.

• Block diagram

Input latch

Address

decoder

Detection

mode

Single-detection data recovery

Bit search circuit

Search result

• Register configuration

Address

Initial value

bit 31

bit 16

BSD0

bit 0

000003F0^H

000003F1^H

000003F2^H

000003F3^H

XXXXXXXX^B

(W)

000003F4^H

000003F5^H

000003F6^H

000003F7^H

XXXXXXXX^B

BSD1

BSDC

BSRR

000003F8^H

000003F9^H

000003FA^H

000003FB^H

XXXXXXXX^B

(W)

000003FC^H

000003FE^H

000003FD^H

000003FF^H

XXXXXXXX^B

( ) : Access

R/W : Readable and writable

R

W

X

: Read only

: Write only

: Indeterminate

51

MB91101/MB91101A

8. 10-bit A/D Converter (Successive Approximation Conversion Type)

The A/D converter is the module which converts an analog input voltage to a digital value, and it has following

features.

• Minimum converting time: 5.6 µs/ch. (system clock: 25 MHz)

• Inner sample and hold circuit

• Resolution: 10 bits

• Analog input can be selected from 4 channels by program.

Single convert mode: 1 channel is selected and converted.

Scan convert mode: Converting continuous channels. Maximum 4 channels are programmable.

Continuous convert mode: Converting the specified channel repeatedly.

Stop convert mode: After converting one channel then stop and wait till next activation synchronising at

the beginning of conversion can be peformed.

• DMA transfer operation is available by interruption.

• Operating factor can be selected from the software, the external trigger (falling edge), and 16-bit reroad timer

(rising edge).

• Block diagram

AV^CC

AVR

AVSS

Internal voltage generator

MPX

AN0

AN1

AN2

AN3

Successive approximation

register

Comparator

Sample & hold circuit

Data register (ADCR)

A/D control register (ADCS)

Trigger start

ATG

Timer start

TIM0

(internal connection)

(16-bit reload timer ch.2)

Operating clock

Prescaler

φ

(Peripheral clock)

52

MB91101/MB91101A

• Register configuration

Address

Initial value

bit 0

bit 15

0000003A^H

0000003B^H

0 0 0 0 0 0 0 0

B

ADCS

ADCR

(R/W)

(R)

00000038^H

00000039^H

- - - - - - X X ^B

X X X X X X X X ^B

( ) : Access

R/W : Readable and writable

R

–

: Read only

: Unused

X

: Indeterminate

53

MB91101/MB91101A

9. Interrupt Controller

The interrupt controller processes interrupt acknowledgments and arbitration between interrupts.

• Block diagram

INT0*²

OR

IM

Priority judgment

5

LEVEL4 to

LEVEL0*⁴

NMI

NMI processing

4

HLDREQ

cancel

HLDCAN*³

request

Level judgment

Level

vector

generation

ICR00

RI00

6

VCT5 to

•

VCT0*⁵

Vector judgment

•

ICR47

RI47

DLYI*¹

(DLYIRQ)

R-bus

*1: DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section “11. Delayed Interrupt

Module” for detail).

*2: INT0 is a wake-up signal to clock control block in the sleep or stop status.

*3: HLDCAN is a bus release request signal for bus masters other than CPU.

*4: LEVEL5 to LEVEL0 are interrupt level outputs.

*5: VCT5 to VCT0 are interrupt vector outputs.

54

MB91101/MB91101A

• Register configuration

Address

bit 7

Initial value

Address

Initial value

bit 7

bit 0

00000400^H

00000401^H

00000402^H

00000403^H

00000404^H

00000405^H

00000406^H

00000407^H

00000408^H

00000409^H

0000040A^H

0000040B^H

0000040C^H

0000040D^H

0000040E^H

0000040F^H

00000410^H

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

ICR16

- - - 11111 ^B(R/W)

00000411^H

00000412^H

00000413^H

00000414^H

00000415^H

00000416^H

00000417^H

00000418^H

00000419^H

0000041A^H

0000041B^H

0000041C^H

0000041D^H

0000041E^H

0000041F^H

0000042F^H

00000431^H

00000430^H

ICR17

ICR18

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

ICR47

HRCL

DICR

- - - 11111 ^B(R/W)

- - - - - - - 0 ^B(R/W)

( ) : Access

R/W : Redable and writable

: Unused

–

55

MB91101/MB91101A

10. External Interrupt/NMI Control Block

The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INT0

to INT3 pins.

Detecting levels can be selected from “H”, “L”, rising edge and falling edge (not for NMI pin).

• Block diagram

8

Interrupt enable register

9

8

5

INT0 to INT3

NMI

Interrupt

request

Gate

Cause F/F

Edge detection circuit

Interrupt cause register

Request level setting register

• Register configuration

Address

Initial value

00000000 ^B

bit 15

bit 8

bit 0

00000095^H

00000094^H

ENIR

(R/W)

EIRR

ELVR

00000099^H

( ) : Access

R/W : Redable and writable

56

MB91101/MB91101A

11. Delayed Interrupt Module

Delayed interrupt module is a module which generates a interrupt for changing a task. By using this delayed

interrupt module, an interrupt request to CPU can be generated/cancelled by the software.

Refer to the section “9. Interrupt Controller” for delayed interrupt module block diagram.

• Register configuration

Address

Initial value

bit 7

bit 0

00000430^H

- - - - - - - 0

B

(R/W)

DICR

( ) : Access

R/W : Redable and writable

: Unused

–

57

MB91101/MB91101A

12. Clock Generation (Low-power consumption mechanism)

The clock control block is a module which undertakes the following functions.

• CPU clock generation (including gear function)

• Peripheral clock generation (including gear function)

• Reset generation and cause hold

• Standby function (including hardware standby)

• DMA request prohibit

• PLL (multiplier circuit) embedded

• Block diagram

[Gear control block]

Gear control register (GCR)

CPU gear

Peripheral

gear

PCTR register

CPU clock

X0

X1

PLL

1/2

Internal bus clock

Oscillator

circuit

Internal clock

generation

circuit

External bus clock

Peripheral

DMA clock

Internal

peripheral clock

[Stop/sleep control block]

Internal

interrupt request

Internal reset

Standby control

register (STCR)

STOP state

Status

SLEEP state

CPU hold request

Internal reset

CPU hold enable

HST pin

transition

control circuit

Reset

generation

F/F

[DMA prohibit circuit]

DMA

request

DMA request prohibit

register (PDRR)

[Reset cause circuit]

Power on sel

RST pin

Reset cause register (RSRR)

[Watchdog control block]

Watchdog reset generation

postpone register (WPR)

Watchdog reset

postpone register

Timebase timer clear

register (CTBR)

Timebase timer

Count clock

58

MB91101/MB91101A

• Register configuration

Address

Initial value

bit 0

bit 15

bit 8

(R/W)

(W)

00000480^H

00000481^H

00000482^H

00000483^H

00000484^H

00000485^H

00000488^H

RSRR/WTCR

PDRR

1 X X X X - 0 0

0 0 0 1 1 1 - -

- - - - 0 0 0 0

B

STCR

CTBR

WPR

X X X X X X X X ^B

1 1 0 0 1 1 - 1

X X X X X X X X ^B

0 0 - - 0 - - -

(R/W)

(W)

GCR

B

(R/W)

PCTR

B

( ) : Access

R/W : Redable and writable

W

–

: Write only

: Unused

X

: Indeterminate

59

MB91101/MB91101A

13. External Bus Interface

The external bus interface controls the interface between the device and the external memory and also the

external I/O, and has the following features.

• 25-bit (32 Mbytes) address output

• 6 independent banks owing to the chip select function.

Can be set to anywhere on the logical address space for minimum unit 64 Kbytes.

Total 32 Mbytes × 6 area setting is available by the address pin and the chip select pin.

• 8/16-bit bus width setting are available for every chip select area.

• Programmable automatic memory wait (max. for 7 cycles) can be inserted.

• DRAM interface support

Three kinds of DRAM interface: Double CAS DRAM (normally DRAM I/F)

Single CAS DRAM

Hyper DRAM

2 banks independent control (RAS, CAS, etc. control signals)

DRAM select is available from 2CAS/1WE and 1CAS/2WE.

Hi-speed page mode supported

CBR/self refresh supported

Programmable wave form

• Unused address/data pin can be used for I/O port.

• Little endian mode supported

• Clock doubler: Internal bus 50 MHz, external bus 25 MHz

60

MB91101/MB91101A

• Block diagram

A-OUT

Address bus

32

Data bus

32

External data bus

Write buffer

Read buffer

Switch

MUX

DATA BLOCK

ADDRESS BLOCK

+1 or +2

External address bus

Inpage

Shifter

Address buffer

6

8

ASR

AMR

CS0 to CS5

Comparator

RAS0, RAS1

CS0L, CS1L

CS0H, CS1H

DW0, DW1

DRAM control

Underflow

DMCR

Refresh counter

To TBT

3

4

RD

WR0, WR1

External pin control block

All blocks control

Registers and control

BRQ

BGRNT

CLK

RDY

61

MB91101/MB91101A

• Register configuration

Address

bit 31

Initial value

bit 16

bit 0

0000060C^H

ASR1

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1

B

(W)

0000060D^H

0000060E^H

0000060F^H

0 0 0 0 0 0 0 0

B

AMR1

00000610^H

00000611^H

0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 0

B

ASR2

00000612^H

00000613^H

0 0 0 0 0 0 0 0

B

AMR2

AMR3

00000614^H

0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 1

B

ASR3

ASR4

00000615^H

00000616^H

00000617^H

0 0 0 0 0 0 0 0

B

00000618^H

00000619^H

0 0 0 0 0 0 0 0

0 0 0 0 0 1 0 0

B

(W)

0000061A^H

0000061B^H

0 0 0 0 0 0 0 0

B

AMR4

AMR5

0000061C^H

0000061D^H

0 0 0 0 0 0 0 0

0 0 0 0 0 1 0 1

B

ASR5

0000061E^H

0000061F^H

0 0 0 0 0 0 0 0

B

(W)

00000620^H

00000621^H

00000622^H

00000623^H

00000624^H

00000625^H

AMD0

- - - 0 0 1 1 1

0 - - 0 0 0 0 0

0 0 0 0 0 0 0 0

0 - - 0 0 0 0 0

0 0 0 0 0 0 0 0

B

(R/W)

AMD1

B

(R/W)

(W)

AMD32

AMD4

B

AMD5

DSCR

00000626^H

00000627^H

- - X X X X X X ^B

RFCR

(R/W)

(W)

0 0 - - - 0 0 0

B

00000628^H

00000629^H

- - - - 1 1 0 0

- 1 1 1 1 1 1 1

B

EPCR0

DMCR4

1 1 1 1 1 1 1 1

B

0000062B^H

EPCR1

(W)

0000062C^H

0000062D^H

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 -

B

(R/W)

(W)

0000062E^H

0000062F^H

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 -

B

DMCR5

000007FE^H

- - - - - 0 0 0

B

LER

000007FF^H

X X X X X X X X ^B

MODR

(W)

( ) : Access

R/W : Redable and writable

W

–

: Write only

: Unused

X

: Indeterminate

62

MB91101/MB91101A

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(V^SS= AV^SS= 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

V^SS– 0.3

—

Max.

V^SS+ 6.5

—

V^CC5

V^CC3

V^CC5

V^CC3

AV^CC

AVRH

V^IA

V

At 5 V power supply

At 3 V power supply

Power supply

voltage

V^CC3 – 0.3

V^SS– 0.3

—

V^SS+ 6.5

V^SS+ 3.6

AV^CC+ 0.3

V^CC5 + 0.3

10

V

*1

*2

V

Analog supply voltage

V

Analog reference voltage

Analog pin input voltage

V

Input voltage

V^I

V

Output voltage

V^O

V

“L” level maximum output current

“L” level average output current

“L” level maximum total output current

“L” level average total output current

“H” level maximum output current

“H” level average output current

I^OL

mA

mW

°C

*3

*4

I^OLAV

ΣI^OL

ΣI^OLAV

I^OH

—

4

—

100

—

50

*5

*3

*4

—

–10

I^OHAV

—

–4

“H” level maximum total output current ΣI^OH

—

–50

“H” level average total output current

Power consumption

ΣI^OHAV

—

–20

*5

P^D

—

500

Operating temperature

Storage temperature

T^A

0

+70

Tstg

–55

+150

*1: V^CC5 must not be less than V^SS– 0.3 V.

*2: Make sure that the voltage does not exceed V^CC5 + 0.3 V, such as when turning on the device.

*3: Maximum output current is a peak current value measured at a corresponding pin.

*4: Average output current is an average current for a 100 ms period at a corresponding pin.

*5: Average total output current is an average current for a 100 ms period for all corresponding pins.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

63

MB91101/MB91101A

2. Recommended Operating Conditions

(1) At 5 V operation (4.5 V to 5.5 V)

(V^SS= AV^SS= 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

V^CC5

4.5

5.5

V

Normal operation

Retaining the RAM state in

stop mode

Power supply voltage

*1

—

*1

V^CC3

AV^CC

AVRH

T^A

—

V^CC+ 3.6

AV^CC

+70

V

*2

Analog supply voltage

Analog reference voltage

Operating temperature

Smoothing capacitor

V^SS+ 2.7

V^SS– 0.3

0

V

°C

µF

C^S

0.1

1.0

V^CC3 pin *2

*1: At V^CC5, the RAM state holding is not warranted in stop mode.

*2: V^CC3 is used for the bypass capacitor pin.

*3: Use the ceramic capacitor or the capacitor whose frequency characteristic is equivalent to that of the ceramic

capacitor.

And select the larger capacity smoothing condenser to connect to the power supply (V^CC5) than C^S.

(2) At 3 V operation (2.7 V to 3.6 V)

(V^SS= AV^SS= 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

V^CC5

2.7

3.6

V

Normal operation

Retaining the RAM state in

stop mode

Power supply voltage

2.7

3.6

V^CC3

AV^CC

AVRH

T^A

2.7

V^SS+ 2.7

AV^SS

3.6

V^CC+ 3.6

AV^CC

V

*

Analog power supply voltage

Analog reference voltage

Operating temperature

V

0

+70

°C

* : Connect to V^CC5 for the power supply pin.

• Connecting to a power supply

Using with 3 V power supply

Using with 5 V power supply

3 V

5 V

VCC3

VCC5

AV^CC

AVRH

AVSS

VSS

VCC3

VCC5

AV^CC

AVRH

AV^SS

VSS

3 V

About

0.1 µF

GND

64

MB91101/MB91101A

V^CC(V)

Normal operation warranty range (TA = 0°C to +70°C)

Net masked area are fCPP.

Power supply at 5 V

Power supply at 3 V

5.5

4.5

3.0 V ±0.3 V

3.6

3.3

3.0

2.7

3.3 V ±0.3 V

f^CP/fCPP

(MHz)

0

0.625

25

Internal clock

40

50

f^CP/fCPP

(MHz)

fCP

50

CPU

40

PLL system (4 multiplication)

fCPP

25

20

Peripheral

Divide-by-2 system

12.5

5

0

f^C

(MHz)

0

10 12.5

25

50

External clock

Self-oscillation

Source oscillating input clock

Notes: • When using PLL, the external clock must be used between 10.0 MHz to 12.5 MHz.

• PLL oscillation stabilizing period > 100 µs

• The setting of internal clock must be within above ranges.

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the

device’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

65

MB91101/MB91101A

3. DC Characteristics

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Parameter

Symbol

Pin name

Condition

Unit

Remarks

Min.

Typ.

Max.

Input pin except

for hysteresis

input

0.65 × V^CC3

V^CC5 + 0.3

V^IH

—

V

*

“H” level input

voltage

HST, NMI, RST,

PA1 to PA6,

PB0 to PB7,

PE0 to PE7,

PF0 to PF7

Hysteresis

input *

0.8 × V^CC3

V^CC5 + 0.3

0.25 × V^CC3

0.2 × V^CC3

V^IHS

—

V

Input other than

following

symbols

V^IL

V^SS– 0.3

*

“L” level input

voltage

HST, NMI, RST,

PA1 to PA6,

PB0 to PB7,

PE0 to PE7,

PF0 to PF7

Hysteresis

input *

V^SS– 0.3

V^ILS

D16 to D31,

A00 to A24,

P6 to PF

“H” level output

voltage

V^CC5 = 4.5 V

I^OH= –4.0 mA

V^OH

V

^CC– 0.5

—

V

D16 to D31,

A00 to A24,

P6 to PF

“L” level output

voltage

V^CC5 = 4.5 V

I^OL= 4.0 mA

V^OL

—

0.4

Input leakage

current

(Hi-Z output

leakage current)

D00 to D31,

A00 to A23,

P8 to PF

V^CC5 = 5.5 V

0.45 V < V^I

< V^CC

I^LI

–5

—

+5

µA

Pull-up

resistance

V^CC5 = 5.5 V

V^I= 0.45 V

R^PULL

RST

V^CC

25

—

50

75

100

kΩ

(4 multiplication)

Operation at

50 MHz

F^C= 12.5 MHz

V^CC5 = 5.5 V

I^CC

mA

Power supply

current

F^C= 12.5 MHz

V^CC5 = 5.5 V

I^CCS

I^CCH

V^CC

—

40

10

60

mA Sleep mode

T^A= +25°C

V^CC5 = 5.5 V

100

µA Stop mode

Except for

V^CC5, V^CC3,

AV^CC, AV^SS, V^SS

Input

capacitance

C^IN

—

10

—

pF

* : V^CC3 = 3.3 ±0.2 V (internal regulator output voltage) when using 5 V power supply, V^CC3 = power supply voltage

when using 3 V power supply (internal regulator unused)

66

MB91101/MB91101A

4. AC Characteristics

Measurement Conditions

• V^CC= 5.0 V ±10%

Value

Typ.

2.4

Parameter

Symbol

V^IH

Unit

Remarks

Min.

—

Max.

—

“H” level input voltage

“L” level input voltage

“H” level output voltage

“L” level output voltage

V

V^IL

—

0.8

—

V^OH

V^OL

—

2.4

—

0.8

—

Input

Output

VCC

VIH

VIL

VOH

VOL

0.0 V

• V^CC= 2.7 V to 3.6 V

Value

Typ.

Parameter

Symbol

V^IH

Unit

Remarks

Min.

—

Max.

—

“H” level input voltage

“L” level input voltage

“H” level output voltage

“L” level output voltage

1/2 × V^CC

V

V^IL

—

V^OH

V^OL

—

Input

Output

VCC

VIH

VIL

VOH

VOL

0.0 V

• Load conditions

Output pin

C = 50 pF

(V^CC= 5.0V ± 10%)

67

MB91101/MB91101A

• Load capacitance - Delay characteristics (Output delay with reference to the internal)

(ns)

35

5 V Fall

3 V Rise

30

25

20

15

5 V Rise

10

5

3 V Fall

0

20

40 50 60

80

100

120 C (pF)

68

MB91101/MB91101A

(1) Clock Timing Rating

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Max.

name

Symbol

Condition

Unit

Remarks

Parameter

Clock frequency

Clock cycle time

Min.

f^C

X0, X1 When using PLL

10

12.5

MHz

Self-oscillation

X0, X1

10

25

(divide-by-2 input)

External clock

X0, X1

f^C

25

MHz

(divide-by-2 input)

t^C

X0, X1 When using PLL

80

40

100

ns

X0, X1

—

Frequency shift ratio

(when locked)

∆f

—

When using PLL

—

5

%

*1

Input to X0

only, when

using 5 V

P^WH,

P^WL

X0, X1

25

—

ns

Input clock pulse width

power supply

—

P^WH,

P^WL

Input to X0,

X1

X0, X1

10

—

8

ns

t^CR,

t^CF

Input clock rising/falling time

(t^CR+ t^CF)

0.625*²

20

f^CP

—

CPU system

50

25*³

MHz

ns

Internal operating clock

frequency

f^CPB

f^CPP

t^CP

Bus system

Peripheral system

CPU system

25

1600*²

Internal operating clock

cycle time

t^CPB

t^CPP

Bus system

40*³

ns

Peripheral system

40

ns

*1: Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock

multiplication system.

+

+α

|α|

f⁰

Center frequency f 0

∆f =

× 100 (%)

–α

–

*2: These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation and

a 1/8 gear.

*3: Values when using the doubler and CPU operation at 50 MHz.

69

MB91101/MB91101A

• Clock timing rating measurement conditions

tC

0.8 VCC

0.2 VCC

PWH

PWL

tCR

tCF

70

MB91101/MB91101A

(2) Clock Output Timing

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Symbol Pin name Condition

Unit Remarks

Parameter

Min.

Max.

t^CYC

CLK

—

t^CP

—

ns *1

ns

Cycle time

t^CYC

Using the

doubler

t^CPB

—

CLK ↑ → CLK ↓

CLK ↓ → CLK ↑

t^CHCL

t^CLCH

CLK

1/2 × t^CYC– 10 1/2 × t^CYC+ 10

ns *2

ns *3

—

t^CP, t^CPB(internal operating clock cycle time): Refer to “(1) Clock Timing Rating.”

*1: t^CYCis a frequency for 1 clock cycle including a gear cycle.

Use the doubler when CPU frequency is above 25 MHz.

*2: Rating at a gear cycle of × 1.

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8,

respectively.

Min. : (1 – n/2) × t^CYC– 10

Max. : (1 – n/2) × t^CYC+ 10

Select a gear cycle of × 1 when using the doubler.

*3: Rating at a gear cycle of × 1.

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8,

respectively.

Min. : n/2 × t^CYC– 10

Max. : n/2 × t^CYC+ 10

Select a gear cycle of × 1 when using the doubler.

tCYC

tCLCH

tCHCL

VOH

CLK

VOL

71

MB91101/MB91101A

The relation between source oscillation input and CLK pin for configured by CHC/CCK1/CCK0 settings of GCR

(gear control register) is as follows:

However, in this chart source oscillation input means X0 input clock.

Source oscillation input

(when using the doublure)

(1) PLL system

(CHC bit of GCR set to “0”)

tCYC

(a) Gear × 1 CLK pin

CCK1/0: “00”

Source oscillation input

(2) 2 dividing system

(CHC bit of GCR set to “1”)

(a) Gear × 1 CLK pin

tCYC

CCK1/0: “00”

tCYC

(b) Gear × 1/2 CLK pin

CCK1/0: “01”

(c) Gear × 1/4 CLK pin

tCYC

CCK1/0: “10”

(d) Gear × 1/8 CLK pin

tCYC

CCK1/0: “11”

72

MB91101/MB91101A

• Ceramic oscillator applications

Recommended circuit (2 contacts)

Recommended circuit (3 contacts)

X0

X1

X0

X1

*

C1

C1, C2 internally

connected.

C2

C1

C2

* : Murata Mfg. Co., Ltd.

• Discreet type

Oscillation frequency

[MHz]

Load capacitance

C¹= C²[pF]

Power supply voltage

V^CC5 [V]

Model

30

(30)

30

CSA

MG

2.9 to 5.5

CST

CSA

CST

CSA

CST

CSA

CST

CSA

CST

CSA

CST

CSA

CST

MGW

5.00 to 6.30

6.31 to 10.0

MG093

MGW093

MTZ

2.7 to 5.5

2.9 to 5.5

2.7 to 5.5

3.0 to 5.5

2.9 to 5.5

3.2 to 5.5

(30)

30

(30)

30

MTW

MTZ093

MTW093

MTZ

(30)

30

(30)

30

MTW

10.1 to 13.0

MTZ093

MTW093

MXZ040

MXW0C3

(30)

15

13.01 to 15.00

(15)

( ): C¹and C²internally connected 3 contacts type.

73

MB91101/MB91101A

(3) Reset/Hardware Standby Input Ratings

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Symbol Pin name Condition

Unit Remarks

Parameter

Min.

Max.

—

Reset input time

Hardware standby input time

t^RSTL

t^HSTL

RST

HST

t^CP× 5

ns

—

t^CP(internal operating clock cycle time): Refer to “(1) Clock Timing Rating.”

tRSTL, tHSTL

RST

HST

0.2 VCC

74

MB91101/MB91101A

(4) Power on Supply Specifications (Power-on Reset)

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Min.

50

Max.

—

t^R

V^CC

µs

ms

µs

*

V^CC= 5.0 V

—

30

Power supply rising time

50

—

V^CC= 3.0/

3.3 V

—

18

ms

Repeated

operations

Power supply shut off time

Oscillation stabilizing time

t^OFF

t^OSC

V^CC

1

—

ms

ns

—

2 × t^C× 2²¹

+ 100 µs

—

t^C(clock cycle time): Refer to “(1) Clock Timing Rating.”

* : V^CC< 0.2 V before the power supply rising

t^R

0.9 × VCC

VCC

0.2 V

tOFF

Note: Sudden change in supply voltage during operation may initiate a power-on sequence.

To change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid

fluctuations in the supply voltage.

VCC

VSS

A voltage rising rate of 50 mV/ms or

less is recommended.

42 ms approx. 336 ms approx. (@12.5 MHz)

Regulator

(Oscillation stabilizing time)

VCC

tOSC

Stabilizing time *

RST

tRSTL + (tC × 2¹⁹)

t^RSTL: Reset input time

*: Reset can’t be done during regulator stabilizing time.

Note: Set RST pin to “L” level when turning on the device, at least the described above duration after the

supply voltage reaches Vcc is necessary before turning the RST to “H” level.

75

MB91101/MB91101A

(5) Normal Bus Access Read/write Operation

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Symbol

Pin name

CLK,

Condition

Unit

Remarks

Parameter

Min.

Max.

t^CHCSL

t^CHCSH

t^CHAV

—

15

ns

CS0 to CS5

CS0 to CS5 delay time

CLK,

CS0 to CS5

—

15

CLK,

A24 to A00

Address delay time

Data delay time

CLK,

D31 to D16

t^CHDV

t^CLRL

t^CLRH

CLK, RD

—

6

ns

RD delay time

CLK,

WR0, WR1

—

t^CLWL

t^CLWH

t^AVDV

—

10

0

6

ns

WR0, WR1 delay time

CLK,

WR0, WR1

Valid address → valid data

input time

A24 to A00,

D31 to D16

3/2 × t^CYC

*1

*2

– 25

RD,

D31 to D16

RD ↓→ valid data input time t^RLDV

t^CYC– 10

ns *1

ns

RD,

D31 to D16

Data set up → RD ↑ time

RD ↑→ data hold time

t^DSRH

t^RHDX

—

RD,

D31 to D16

ns

t^CYC(a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”

*1: When bus timing is delayed by automatic wait insertion or RDY input, add (t^CYC× extended cycle number for

delay) to this rating.

*2: Rating at a gear cycle of × 1.

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8,

respectively.

Equation: (2 – n/2) × t^CYC– 25

76

MB91101/MB91101A

BA2

BA1

tCYC

VOH

V^OH

VOH

CLK

VOL

tCHCSL

tCHCSH

VOH

CS0 to CS5

VOL

tCHAV

VOH

VOL

VOH

VOL

A24 to A00

tCLRL

tCLRH

VOH

RD

VOL

tRLDV

tRHDX

VIH

tAVDV

VIH

VIL

D31 to D16

WR0, WR1

Read

VIL

tDSRH

tCLWL

VOH

VOL

tCLWH

tCHDV

VOH

VOL

VOH

V^OL

D31 to D16

Write

77

MB91101/MB91101A

(6) Ready Input Timing

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Min.

15

Max.

—

RDY set up time → CLK ↓ t^RDYS

RDY, CLK

ns

—

CLK ↓→ RDY hold time

t^RDYH

0

—

tCYC

CLK

VOH

VOL

tRDYH

tRDYS

RDY

When wait(s)

is inserted.

VIH

VIL

VIH

VIL

VIH

VIL

RDY

When no wait

is inserted.

VIH

VIL

78

MB91101/MB91101A

(7) Hold Timing

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Min.

Max.

CLK,

t^CHBGL

—

6

ns

BGRNT

BGRNT delay time

CLK,

t^CHBGH

—

6

BGRNT

—

Pin floating → BGRNT ↓

time

t^XHAL

t^HAHV

t^CYC– 10

t^CYC+ 10

ns

BGRNT ↑→ pin valid time

t^CYC(a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”

Note: There is a delay time of more than 1 cycle from BRQ input to BGRNT change.

tCYC

VOH

CLK

BRQ

tCHBGH

tCHBGL

VOH

BGRNT

VOL

tXHAL

tHAHV

VOH

VOL

VOH

VOL

Each pin

High impedance

79

MB91101/MB91101A

(8) Normal DRAM Mode Read/Write Cycle

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Min.

—

Max.

t^CLRAH

t^CHRAL

t^CLCASL

t^CLCASH

CLK, RAS

CLK, CAS

6

ns

RAS delay time

—

CAS delay time

—

CLK,

A24 to A00

ROW address delay time

t^CHRAV

t^CHCAV

—

15

ns

COLUMN address delay

time

CLK,

A24 to A00

t^CHDWL

t^CHDWH

CLK, DW

—

15

ns

—

DW delay time

CLK,

D31 to D16

Output data delay time

t^CHDV1

t^RLDV

t^CLDV

t^CADH

—

0

15

ns

RAS ↓→ valid data input

time

RAS,

D31 to D16

5/2 × t^CYC

*1

*2

– 16

CAS ↓→ valid data input

time

CAS,

D31 to D16

t^CYC– 17

—

ns *1

ns

CAS,

D31 to D16

CAS ↑→ data hold time

t^CYC(a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”

CAS: CS0L to CS1H pins are for CAS signal outputs.

DW: DW0, DW1 and CS0H to CS1H are used for WE outputs.

*1: When Q1 cycle or Q4 cycle is extended for 1 cycle, add t^CYCtime to this rating.

*2: Rating at a gear cycle of × 1.

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8,

respectively.

Equation: (3 – n/2) × t^CYC– 16

80

MB91101/MB91101A

Q1

Q2

Q3

Q4

Q5

tCYC

VOH

CLK

RAS

CAS

VOL

VOH

VOL

tCLRAH

tCHRAL

tCLCASH

VOH

tCLCASH

VOL

tCHCAV

tCHRAV

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

ROW address

COLUMN address

A24 to A00

D31 to D16

tRLDV

tCADH

tCLDV

VIH

VIL

Read

VIL

VOH

DW

VOL

tCHDWH

tCHDWL

VOH

VOL

VOH

VOL

Write

D31 to D16

tCHDV1

81

MB91101/MB91101A

(9) Normal DRAM Mode Fast Page Read/Write Cycle

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

RAS delay time

Min.

—

Max.

t^CLRAH

CLK, RAS

CLK, CAS

6

ns

t^CLCASL

t^CLCASH

—

CAS delay time

—

COLUMN address delay

time

CLK,

A24 to A00

t^CHCAV

t^CHDWH

t^CHDV1

—

15

ns

DW delay time

CLK, DW

—

CLK,

D31 to D16

Output data delay time

CAS ↓→ valid data input

time

CAS,

D31 to D16

t^CLDV

t^CADH

—

0

t^CYC– 17

—

ns

*

CAS,

D31 to D16

CAS ↑→ data hold time

t^CYC(a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”

CAS: CS0L to CS1H pins are for CAS signal outputs.

DW: DW0, DW1 and CS0H to CS1H are used for WE outputs.

* : When Q4 cycle is extended for 1 cycle, add t^CYCtime to this rating.

82

MB91101/MB91101A

Q5

Q4

Q5

Q4

Q5

V^OH

VOH

CLK

VOL

tCLRAH

VOH

RAS

tCLCASL

tCLCASH

VOH

CAS

VOL

tCHCAV

VOH

VOL

VOH

VOL

VOH

VOL

A24 to A00

COLUMN address

tCLDV

VIH

tCADH

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

D31 to D16

Read

V^IL

VIL

tCHDWH

VOH

DW

tCHDV1

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

Write

D31 to D16

83

MB91101/MB91101A

(10) Single DRAM Timing

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Min.

Max.

t^CLRAH2

t^CHRAL2

t^CHCASL2

t^CHCASH2

CLK, RAS

CLK, CAS

—

6

ns

RAS delay time

6

n/2 × t^CYC

6

—

CAS delay time

CLK,

A24 to A00

ROW address delay time

t^CHRAV2

t^CHCAV2

—

15

ns

COLUMN address delay

time

CLK,

A24 to A00

—

t^CHDWL2

t^CHDWH2

CLK, DW

—

15

ns

DW delay time

CLK,

D31 to D16

Output data delay time

t^CHDV2

t^CLDV2

t^CADH2

—

0

15

ns

CAS ↓→ Valid data input

time

CAS,

D31 to D16

(1 – n/2) ×

t^CYC– 17

CLK,

D31 to D16

CAS ↑→ data hold time

—

t^CYC(a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”

84

MB91101/MB91101A

tCYC

*1

Q1

Q2

Q3

V^OH

Q4S

CLK

RAS

VOH

V^OL

VOH

VOL

tCHRAL2

tCLRAH2

tCHCASL2

tCHCASH2

VOH

CAS

VOL

VOH

VOL

VOH

VOL

VOH

VOL

ROW address

COLUMN-0

COLUMN-1

COLUMN-2

A24 to A00

tCHRAV2

tCHCAV2

tCADH2

tCLDV2

VIH

VIL

VIH

VIL

Read-0

Read-1

Read-2

D31 to D16

DW

VOH

VOL

tCHDWL2

tCHDWH2

*2

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

D31 to D16

Write-0

Write-2

Write-1

tCHDV2

*1: Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle.

*2: indicates the timing when the bus cycle begins from the high spead page mode.

85

MB91101/MB91101A

(11) Hyper DRAM Timing

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Min.

—

Max.

t^CLRAH3

t^CHRAL3

t^CHCASL3

t^CHCASH3

CLK, RAS

CLK, CAS

6

ns

RAS delay time

—

6

n/2 × t^CYC

6

—

CAS delay time

—

CLK,

A24 to A00

ROW address delay time

t^CHRAV3

t^CHCAV3

—

15

ns

COLUMN address delay

time

CLK,

A24 to A00

t^CHRL3

CLK, RD

CLK, DW

—

15

ns

—

RD delay time

t^CHRH3

t^CLRL3

t^CHDWL3

t^CHDWH3

DW delay time

CLK,

D31 to D16

Output data delay time

t^CHDV3

t^CLDV3

t^CADH3

—

0

15

t^CYC– 17

—

ns

CAS ↓→ valid data input

time

CAS,

D31 to D16

CLK,

D31 to D16

CAS ↓→ data hold time

t^CYC(a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”

86

MB91101/MB91101A

tCYC

*1

Q1

Q2

Q3

V^OH

Q4H

CLK

VOH

V^OL

VOL

RAS

CAS

VOH

VOL

tCHRAL3

tCLRAH3

tCHCASL3

tCHCASH3

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

ROW address

COLUMN-0

COLUMN-1

COLUMN-2

A24 to A00

tCHRAV3

tCHCAV3

*2

RD

VOH

VOL

tCHRL3

tCLRL3

tCHRH3

tCLDV3

tCADH3

VIH

VIL

VIH

VIL

Read-0

Read-1

D31 to D16

DW

V^OH

VOL

tCHDWL3

tCHDWH3

*2

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

D31 to D16

Write-0

Write-2

Write-1

tCHDV3

*1: Q4H indicates Q4HR (Read) of Single DRAM cycle or Q4HW (Write) cycle.

*2: indicates the timing when the bus cycle begins from the high spead page mode.

87

MB91101/MB91101A

(12) CBR Refresh

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Min.

—

Max.

t^CLRAH

t^CHRAL

t^CLCASL

t^CLCASH

CLK, RAS

CLK, CAS

6

ns

RAS delay time

—

CAS delay time

—

CAS: CS0L to CS1H pins are for CAS signal outputs.

tCYC

R1

R2

R3

R4

VOH

CLK

RAS

CAS

VOL

VOH

VOL

tCHRAL

tCLRAH

VOH

VOL

tCLCASL

tCLCASH

DW

88

MB91101/MB91101A

(13) Self Refresh

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

RAS delay time

CAS delay time

Min.

—

Max.

t^CLRAH

t^CHRAL

t^CLCASL

t^CLCASH

CLK, RAS

CLK, CAS

6

ns

—

CAS: CS0L to CS1H pins are for CAS signal outputs.

tCYC

SR1

SR2

SR3

VOH

CLK

RAS

CAS

VOL

tCLRAH

VOH

tCHRAL

V^OL

VOH

VOL

tCLCASH

tCLCASL

89

MB91101/MB91101A

(14) UART Timing

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Min.

Max.

Serial clock cycle time

SCLK ↓→ SCLK ↑

SCLK ↑→ SCLK ↓

t^SCYC

—

8 × t^CYCP

—

ns

t^SCLCH

t^SCHCL

4 × t^CYCP–10 4 × t^CYCP+10 ns

Internal

shift clock

mode

SCLK ↓→ SOUT delay time t^SLOV

—

–80

100

80

—

ns

Valid SIN → SCLK ↑

t^IVSH

SCLK ↑→ valid SIN hold

time

t^SHIX

—

60

—

ns

Serial clock “H” pulse width t^SHSL

Serial clock “L” pulse width t^SLSH

SCLK ↓→ SOUT delay time t^SLOV

—

4 × t^CYCP

—

ns

External

shift clock

mode

150

—

Valid SIN → SCLK ↑

t^IVSH

60

SCLK ↑→ valid SIN hold

time

t^SHIX

—

60

—

ns

t^CYCP: A cycle time of peripheral system clock

Notes: This rating is for AC characteristics in CLK synchronous mode.

• Internal shift clock mode

tSCYC

tSCLCH

tSCHCL

VOH

SCLK

SOUT

VOL

tSLOV

VOH

VOL

tIVSH

tSHIX

VIH

VIL

VIH

VIL

SIN

• External shift clock mode

tSLSH

tSHSL

VIH

SCLK

VIL

tSLOV

VOH

VOL

SOUT

SIN

tIVSH

tSHIX

VIH

VIL

VIH

VIL

90

MB91101/MB91101A

(15) Trigger System Input Timing

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Symbol

Pin name

ATG

TRG0 to TRG3

Condition

Unit

Remarks

Parameter

Min.

Max.

t^TRGH,

t^TRGL

A/D start trigger input time

5 × t^CYCP

—

ns

—

PWM external trigger input t^TRGH,

time t^TRGL

5 × t^CYCP

—

t^CYCP: A cycle time of peripheral system clock

tTRGH

tTRGL

VIH

ATG

VIL

TRG0 to TRG3

91

MB91101/MB91101A

(16) DMA Controller Timing

(V^CC5 = 5.0 V ±10%, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

(V^CC5 = V^CC3 = 2.7 V to 3.6 V, V^SS= AV^SS= 0.0 V, T^A= 0°C to +70°C)

Value

Symbol

DREQ input pulse width t^DRWH

Pin name

Condition

Unit Remarks

Parameter

Min.

Max.

DREQ0 to DREQ2

2 × t^CYC

—

ns

CLK,

DACK0 to DACK2

t^CLDL

t^CLDH

t^CLEL

t^CLEH

t^CHDL

t^CHDH

t^CHEL

t^CHEH

—

6

DACK delay time

(Normal bus)

(Normal DRAM)

CLK,

DACK0 to DACK2

6

ns

CLK,

EOP0 to EOP2

6

EOP delay time

(Normal bus)

(Normal DRAM)

CLK,

EOP0 to EOP2

6

—

CLK,

DACK0 to DACK2

n/2 × t^CYC

DACK delay time

(Single DRAM)

(Hyper DRAM)

CLK,

DACK0 to DACK2

6

n/2 × t^CYC

6

CLK,

EOP0 to EOP2

EOP delay time

(Single DRAM)

(Hyper DRAM)

CLK,

EOP0 to EOP2

t^CYC(a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”

tCYC

VOH

CLK

VOL

tCLDL

tCLEL

tCLDH

tCLEH

DACK0 to DACK2

EOP0 to EOP2

(Normal bus)

VOH

VOL

(Normal DRAM)

DACK0 to DACK2

EOP0 to EOP2

(Single DRAM)

(Hyper DRAM)

VOH

VOL

tCHDL

tCHEL

tCHDH

tDRWH

VIH

DREQ0 to DREQ2

92

MB91101/MB91101A

5. A/D Converter Block Electrical Characteristics

(AV^CC= 2.7 V to 3.6 V, AV^SS= 0.0 V, AVRH = 2.7 V, T^A= 0°C to +70°C)

Value

Symbol Pin name

Unit

Parameter

Min.

—

Typ.

10

Max.

10

Resolution

Total error

—

bit

—

±4.0

±3.5

±2.0

+2.5

LSB

Linearity error

—

Differentiation linearity error

Zero transition voltage

Full-scale transition voltage

Conversion time

—

V^OT

AN0 to AN3

–1.5

+0.5

V^FST

—

AN0 to AN3 AVRH – 4.5 AVRH – 1.5 AVRH + 0.5 LSB

5.6 *¹

—

AN0 to AN3

AVRH

—

0.1

—

10

µs

µA

V

Analog port input current

Analog input voltage

Reference voltage

I^AIN

V^AIN

—

AV^SS

—

AVRH

AV^CC

—

V

I^A

AV^CC

4

mA

µA

LSB

Power supply current

5 *²

I^AH

I^R

AV^CC

—

AVRH

—

200

—

Reference voltage supply current

AVRH

—

5 *²

4

I^RH

—

Conversion variance between channels

*1: AV^CC= 2.7 V – 3.6 V

AN0 to AN3

—

*2: Current value for A/D converters not in operation, CPU stop mode (V^CC= AV^CC= AVRH = 3.6 V)

Notes: • As the absolute value of AVRH decreases, relative error increases.

• Output impedance of external circuit of analog input under following conditions;

Output impedance of external circuit < 10 kΩ.

If output impedance of external circuit is too high, analog voltage sampling time may be too short for

accurate sampling (sampling time is 5.6 µs for a machine clock of 25 MHz).

• Analog input circuit model plan

Sample and hold circuit

Analog input

C0

Comparator

RON1

R^ON2

RON3

RON4

C1

RON1 : 0.2 kΩ

R^ON2: 1.4 kΩ

RON3 : 1.4 kΩ

R^ON4: 0.2 kΩ

C⁰: 16.6 pF

C¹: 4.0 pF

Note: Listed values are for reference purposes only.

93

MB91101/MB91101A

6. A/D Converter Glossary

• Resolution

The smallest change in analog voltage detected by A/D converter.

• Linearity error

A deviation of actual conversion characteristic from a line connecting the zero-traction point (between “00 0000

0000” ↔ “00 0000 0001”) to the full-scale transition point (between “11 1111 1110” ↔ “11 1111 1111”).

• Differential linearity error

A deviation of a step voltage for changing the LSB of output code from ideal input voltage.

Linearity error

Differential linearity error

3FF

3FE

3FD

Ideal characteristic

Actual conversion

characteristic

N+1

N

{1 LSB × (N – 1) + VOT}

Actual characteristic

VFST

(measured

value)

004

003

002

001

V^NT

(measured value)

Actual conversion

characteristic

N–1

N–2

V(N + 1)T

(measured value)

V^NT

(measured value)

Ideal characteristic

VOT (measured value)

Actual conversion characteristic

AVRL

AVRH

AVRL

AVRH

Analog input

VNT – {1 LSB × (N – 1) + VOT}

V(N + 1)T – VNT

Linearity error of

digital output N

Differential linearity error

of digital output N

=

[LSB]

– 1 [LSB]

1 LSB

VFST – VOT

1 LSB =

[V]

1022

V^OT: A voltage for causing transition of digital output from (000)H to (001)H

V^FST: A voltage for causing transition of digital output from (3FE)H to (3FF)H

VNT: A voltage for causing transition of digital output from (N – 1)H to N

(Continued)

94

MB91101/MB91101A

(Continued)

• Total error

A difference between actual value and theoretical value. The overall error includes zero-transition error, full-

scale transition error and linearity error.

Total error

3FF

1.5 LSB’

3FE

Actual conversion

characteristic

3FD

{1 LSB’ × (N – 1)

+ 0.5 LSB’}

004

V^NT

(measured value)

003

Actual conversion

characteristic

002

Ideal characteristic

001

0.5 LSB’

AVRL

AVRH

Analog input

VNT – {1 LSB’ × (N – 1) + 0.5 LSB’}

=

Total error of digital output N

[LSB]

1 LSB'

AVRH – AVRL

1024

1 LSB’ (ideal value) =

[V]

VOT’ (ideal value) = AVRL + 0.5 LSB’ [V]

V^FST’ (ideal value) = AVRL – 1.5 LSB’ [V]

VNT: A voltage for causing transition of digital output from (N – 1) to N

95

MB91101/MB91101A

■ REFERENCE DATA

1. Operating frequency vs. I^CCcharacteristics

Internal DC - DC regulator is not used (VCC = 3 V) Internal DC - DC regulator is used (VCC = 5 V)

I^CC(mA) I^CC(mA)

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

(VCC)

3.6 V

(VCC)

4.5 V to 5.5 V

3.3 V

3.0 V

2.7 V

0

10

20

30

40

50

0

10

20

30

40

50

f (MHz)

Operating conditions : Source oscillation 12.5 MHz (crystal), PLL is used (50 M, 25 M, 12.5 M)

Gear : CPU = 1/1, Peripherals = 1/1

(Doubler is used for 50MHz, Gear peripherals = 1/2)

2. V^CCvs. I^CCcharacteristics

Internal DC - DC regulator is not used (VCC = 3 V) Internal DC - DC regulator is used (VCC = 5 V)

ICC (mA)

Icc (mA)

18

16

14

18

16

14

Gear : 1/1

Gear : 1/2

12

14

10

8

12

14

10

8

Gear : 1/4

Gear : 1/8

Gear : 1/4

Gear : 1/8

(PLL : off)

4

Gear : 1/8

(PLL : off)

2

0

2

0

2.7

3.0

3.3 3.6

4.5

5.0

5.5

VCC (V)

Operating conditions : Source oscillation 12.5 MHz (crystal), divide-by-2 input, PLL : ON

Gear : CPU = Peripherals

96

MB91101/MB91101A

■ INSTRUCTIONS (165 INSTRUCTIONS)

1. How to Read Instruction Set Summary

Mnemonic

Type

OP

CYC

NZVC

Operation

Remarks

ADD Rj,

* ADD #s5, Ri

Ri

A

C

,

A6

A4

,

1

,

CCCC

Ri + Rj → Ri

Ri + s5 → Ri

,

↓

(1)

↓

(2)

↓

(3)

↓

(4)

↓

(5)

↓

(6)

↓

(7)

(1) Names of instructions

Instructions marked with * are not included in CPU specifications. These are extended instruction codes

added/extended at assembly language levels.

(2) Addressing modes specified as operands are listed in symbols.

Refer to “2. Addressing mode symbols” for further information.

(3) Instruction types

(4) Hexa-decimal expressions of instructions

(5) The number of machine cycles needed for execution

a: Memory access cycle and it has possibility of delay by Ready function.

b: Memory access cycle and it has possibility of delay by Ready function.

If an object register in a LD operation is referenced by an immediately following instruction, the interlock

function is activated and number of cycles needed for execution increases.

c: If an immediately following instruction operates to an object of R15, SSP or USP in read/write mode or

if the instruction belongs to instruction format A group, the interlock function is activated and number of

cycles needed for execution increases by 1 to make the total number of 2 cycles needed.

d: If an immediately following instruction refers to MDH/MDL, the interlock function is activated and number

of cycles needed for execution increases by 1 to make the total number of 2 cycles needed.

For a, b, c and d, minimum execution cycle is 1.

(6) Change in flag sign

• Flag change

C : Change

– : No change

0 : Clear

1 : Set

• Flag meanings

N : Negative flag

Z : Zero flag

V : Over flag

C : Carry flag

(7) Operation carried out by instruction

97

MB91101/MB91101A

2. Addressing Mode Symbols

Ri

: Register direct (R0 to R15, AC, FP, SP)

Rj

: Register direct (R0 to R15, AC, FP, SP)

R13

Ps

: Register direct (R13, AC)

: Register direct (Program status register)

Rs

: Register direct (TBR, RP, SSP, USP, MDH, MDL)

: Register direct (CR0 to CR15)

CRi

CRj

#i8

: Unsigned 8-bit immediate (–128 to 255)

Note: –128 to –1 are interpreted as 128 to 255

: Unsigned 20-bit immediate (–0X80000 to 0XFFFFF)

Note: –0X7FFFF to –1 are interpreted as 0X7FFFF to 0XFFFFF

: Unsigned 32-bit immediate (–0X80000000 to 0XFFFFFFFF)

Note: –0X80000000 to –1 are interpreted as 0X80000000 to 0XFFFFFFFF

: Signed 5-bit immediate (–16 to 15)

#i20

#i32

#s5

#s10

#u4

: Signed 10-bit immediate (–512 to 508, multiple of 4 only)

: Unsigned 4-bit immediate (0 to 15)

#u5

: Unsigned 5-bit immediate (0 to 31)

#u8

: Unsigned 8-bit immediate (0 to 255)

#u10

: Unsigned 10-bit immediate (0 to 1020, multiple of 4 only)

: Unsigned 8-bit direct address (0 to 0XFF)

@dir8

@dir9

@dir10

label9

label12

label20

label32

@Ri

: Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only)

: Unsigned 10-bit direct address (0 to 0X3FC, multiple of 4 only)

: Signed 9-bit branch address (–0X100 to 0XFC, multiple of 2 only)

: Signed 12-bit branch address (–0X800 to 0X7FC, multiple of 2 only)

: Signed 20-bit branch address (–0X80000 to 0X7FFFF)

: Signed 32-bit branch address (–0X80000000 to 0X7FFFFFFF)

: Register indirect (R0 to R15, AC, FP, SP)

@Rj

: Register indirect (R0 to R15, AC, FP, SP)

@(R13, Rj)

: Register relative indirect (Rj: R0 to R15, AC, FP, SP)

@(R14, disp10) : Register relative indirect (disp10: –0X200 to 0X1FC, multiple of 4 only)

@(R14, disp9) : Register relative indirect (disp9: –0X100 to 0XFE, multiple of 2 only)

@(R14, disp8) : Register relative indirect (disp8: –0X80 to 0X7F)

@(R15, udisp6) : Register relative (udisp6: 0 to 60, multiple of 4 only)

@Ri+

: Register indirect with post-increment (R0 to R15, AC, FP, SP)

@R13+

@SP+

@–SP

(reglist)

: Register indirect with post-increment (R13, AC)

: Stack pop

: Stack push

: Register list

98

MB91101/MB91101A

3. Instruction Types

MSB

LSB

16 bits

Type A

OP

8

Rj

4

Ri

4

Type B

Type C

Type *C’

Type D

Type E

Type F

OP

4

i8/o8

8

Ri

4

OP

8

u4/m4

4

Ri

4

ADD, ADDN, CMP, LSL, LSR and ASR instructions only

OP

7

s5/u5

5

Ri

4

OP

u8/rel8/dir/reglist

8

OP

8

SUB-OP

Ri

4

OP

5

rel11

11

99

MB91101/MB91101A

4. Detailed Description of Instructions

• Add/subtract operation instructions (10 instructions)

Type

Mnemonic

OP Cycle N Z V C

Operation

Remarks

ADD

* ADD

Rj, Ri

#s5, Ri

A

C’

A6

A4

1

C C C C Ri + Rj → Ri

C C C C Ri + s5 → Ri

MSB is interpreted as

a sign in assembly

language

ADD

ADD2

#i4, Ri

C

A4

A5

1

C C C C Ri + extu (i4) → Ri

Zero-extension

Sign-extension

ADDC

Rj, Ri

A

A7

1

C C C C Ri + Rj + c → Ri

Add operation with

sign

ADDN

* ADDN #s5, Ri

Rj, Ri

A

C’

A2

A0

1

– – – – Ri + Rj → Ri

– – – – Ri + s5 → Ri

MSB is interpreted as

a sign in assembly

language

ADDN

ADDN2 #i4, Ri

#i4, Ri

C

A0

A1

1

– – – – Ri + extu (i4) → Ri

Zero-extension

Sign-extension

SUB

Rj, Ri

A

AC

AD

1

C C C C Ri – Rj → Ri

SUBC

C C C C Ri – Rj – c → Ri

Subtract operation with

carry

SUBN

Rj, Ri

A

AE

1

– – – – Ri – Rj → Ri

• Compare operation instructions (3 instructions)

Type

Mnemonic

OP Cycle N Z V C

Operation

Remarks

CMP

* CMP

Rj, Ri

#s5, Ri

A

C’

AA

A8

1

C C C C Ri – Rj

C C C C Ri – s5

MSB is interpreted as

a sign in assembly

language

CMP

CMP2

#i4, Ri

C

A8

A9

1

C C C C Ri + extu (i4)

Zero-extension

Sign-extension

• Logical operation instructions (12 instructions)

Type

Mnemonic

OP Cycle N Z V C

Operation

Remarks

AND

ANDH

ANDB

Rj, Ri

A

82 C C – – Ri & = Rj

1

Word

Half word

Byte

Rj, @Ri

84 1 + 2a C C – – (Ri) & = Rj

85 1 + 2a C C – – (Ri) & = Rj

86 1 + 2a C C – – (Ri) & = Rj

OR

ORH

ORB

Rj, Ri

A

92

1

C C – – Ri | = Rj

Word

Half word

Byte

Rj, @Ri

94 1 + 2a C C – – (Ri) | = Rj

95 1 + 2a C C – – (Ri) | = Rj

96 1 + 2a C C – – (Ri) | = Rj

EOR

EORH

EORB

Rj, Ri

A

9A

1

C C – – Ri ^ = Rj

Word

Half word

Byte

Rj, @Ri

9C 1 + 2a C C – – (Ri) ^ = Rj

9D 1 + 2a C C – – (Ri) ^ = Rj

9E 1 + 2a C C – – (Ri) ^ = Rj

100

MB91101/MB91101A

• Bit manipulation arithmetic instructions (8 instructions)

Type

Mnemonic

OP Cycle N Z V C

Operation

Remarks

BANDL #u4, @Ri

C

80 1 + 2a – – – – (Ri) & = (F0^H+ u4)

Manipulate lower 4 bits

(u4: 0 to 0F^H)

BANDH #u4, @Ri

(u4: 0 to 0F^H)

* BAND #u8, @Ri

C

81 1 + 2a – – – – (Ri) & = ((u4<<4) + 0F^H) Manipulate upper 4 bits

– – – – (Ri) & = u8

1

2

3

–

*

BORL

BORH

* BOR

#u4, @Ri

(u4: 0 to 0F^H)

#u4, @Ri

(u4: 0 to 0F^H)

#u8, @Ri

C

90 1 + 2a – – – – (Ri) | = u4

Manipulate lower 4 bits

Manipulate upper 4 bits

91 1 + 2a – – – – (Ri) | = (u4<<4)

–

– – – – (Ri) | = u8

BEORL #u4, @Ri

(u4: 0 to 0F^H)

BEORH #u4, @Ri

(u4: 0 to 0F^H)

* BEOR #u8, @Ri

C

98 1 + 2a – – – – (Ri) ^ = u4

Manipulate lower 4 bits

Manipulate upper 4 bits

99 1 + 2a – – – – (Ri) ^ = (u4<<4)

–

– – – – (Ri) ^ = u8

BTSTL

BTSTH

#u4, @Ri

(u4: 0 to 0F^H)

#u4, @Ri

C

88

89

2 + a 0 C – – (Ri) & u4

Test lower 4 bits

Test upper 4 bits

2 + a C C – – (Ri) & (u4<<4)

(u4: 0 to 0F^H)

*1: Assembler generates BANDL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates

BANDH if “u8&0xF0” leaves an active bit. Depending on the value in the “u8” format, both BANDL and BANDH

may be generated.

*2: Assembler generates BORL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates

BORH if “u8&0xF0” leaves an active bit.

*3: Assembler generates BEORL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates

BEORH if “u8&0xF0” leaves an active bit.

• Add/subtract operation instructions (10 instructions)

Type

Mnemonic

OP Cycle N Z V C

Operation

Remarks

MUL

MULU

MULH

Rj, Ri

A

AF

AB

BF

BB

5

3

C C C – Rj × Ri → MDH, MDL

C C – – Rj × Ri → MDL

32-bit × 32-bit = 64-bit

Unsigned

16-bit × 16-bit = 32-bit

Unsigned

MULUH Rj, Ri

C C – – Rj × Ri → MDL

DIVOS

DIVOU

DIV1

DIV2

DIV3

DIV4S

* DIV

Ri

E

97 – 4

97 – 5

97 – 6

97 – 7

9F – 6

9F – 7

1

d

1

–

– – – –

– C – C

– – – –

– C – C MDL/Ri → MDL,

MDL%Ri → MDH

– C – C MDL/Ri → MDL,

MDL%Ri → MDH

Step calculation

32-bit/32-bit = 32-bit

1

2

Ri

*

–

Unsigned

* DIVU

*1: DIVOS, DIV1 × 32, DIV2, DIV3 and DIV4S are generated. A total instruction code length of 72 bytes.

*2: DIVOU and DIV1 × 32 are generated. A total instruction code length of 66 bytes.

101

MB91101/MB91101A

• Shift arithmetic instructions (9 instructions)

Type

Mnemonic

OP Cycle N Z V C

Operation

Remarks

Logical shift

LSL

* LSL

LSL

Rj, Ri

A

C’

C

B6

B4

B5

1

C C – C Ri<<Rj → Ri

#u5, Ri

#u4, Ri

C C – C Ri<<u5 → Ri

C C – C Ri<<u4 → Ri

C C – C Ri<<(u4 + 16) → Ri

LSL2

C

LSR

* LSR

LSR

Rj, Ri

A

C’

C

B2

B0

B1

1

C C – C Ri>>Rj → Ri

C C – C Ri>>u5 → Ri

C C – C Ri>>u4 → Ri

C C – C Ri>>(u4 + 16) → Ri

Logical shift

#u5, Ri

#u4, Ri

LSR2

C

ASR

* ASR

ASR

Rj, Ri

A

C’

C

BA

B8

B9

1

C C – C Ri>>Rj → Ri

C C – C Ri>>u5 → Ri

C C – C Ri>>u4 → Ri

C C – C Ri>>(u4 + 16) → Ri

#u5, Ri

#u4, Ri

ASR2

C

• Immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer

instruction) (3 instructions)

Type

Mnemonic

OP Cycle N Z V C

Operation

Remarks

LDI: 32

LDI: 20

#i32, Ri

#i20, Ri

E

C

9F – 8

9B

3

2

– – – – i32 → Ri

– – – – i20 → Ri

– – – – i8 → Ri

Upper 12 bits are zero-

extended

Upper 24 bits are zero-

extended

LDI: 8

* LDI

#i8, Ri

# {i8 | i20 | i32}, Ri

B

C0

1

{i8 | i20 | i32} → Ri

1

*

*1: If an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection.

If an immediate value contains relative value or external reference, assembler selects i32.

• Memory load instructions (13 instructions)

Type

Mnemonic

OP Cycle N Z V C

Operation

Remarks

LD

@Rj, Ri

A

B

C

E

04

00

20

03

07 – 0

07 – 8

b

– – – – (Rj) → Ri

– – – – (R13 + Rj) → Ri

– – – – (R14 + disp10) → Ri

– – – – (R15 + udisp6) → Ri

– – – – (R15) → Ri, R15 + = 4

– – – – (R15) → Rs, R15 + = 4 Rs: Special-purpose

register

@(R13, Rj), Ri

@(R14, disp10), Ri

@(R15, udisp6), Ri

@R15 +, Ri

@R15 +, Rs

1 + a + b

LD

@R15 +, PS

E

07 – 9

C C C C (R15) → PS, R15 + = 4

LDUH

@Rj, Ri

@(R13, Rj), Ri

@(R14, disp9), Ri

A

B

05

01

40

b

– – – – (Rj) → Ri

– – – – (R13 + Rj) → Ri

– – – – (R14 + disp9) → Ri

Zero-extension

LDUB

@Rj, Ri

@(R13, Rj), Ri

@(R14, disp8), Ri

A

B

06

02

60

b

– – – – (Rj) → Ri

– – – – (R13 + Rj) → Ri

– – – – (R14 + disp8) → Ri

Zero-extension

Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler

description from disp8 to disp10 are as follows:

disp8 → o8 = disp8

disp9 → o8 = disp9>>1

disp10 → o8 = disp10>>2

udisp6 → u4 = udisp6>>2

Each disp is a code extension.

udisp4 is a 0 extension.

102

MB91101/MB91101A

• Memory store instructions (13 instructions)

Type

Mnemonic

OP Cycle N Z V C

Operation

Remarks

ST

Ri, @Rj

A

B

C

E

14

10

30

13

17 – 0

17 – 8

a

– – – – Ri → (Rj)

– – – – Ri → (R13 + Rj)

– – – – Ri → (R14 + disp10)

– – – – Ri → (R15 + usidp6)

– – – – R15 – = 4, Ri → (R15)

– – – – R15 – = 4, Rs → (R15) Rs: Special-purpose

register

Word

Ri, @(R13, Rj)

Ri, @(R14, disp10)

Ri, @(R15, udisp6)

Ri, @–R15

Rs, @–R15

ST

PS, @–R15

E

17 – 9

a

– – – – R15 – = 4, PS → (R15)

STH

Ri, @Rj

Ri, @(R13, Rj)

Ri, @(R14, disp9)

A

B

15

11

50

a

– – – – Ri → (Rj)

– – – – Ri → (R13 + Rj)

– – – – Ri → (R14 + disp9)

Half word

STB

Ri, @Rj

Ri, @(R13, Rj)

Ri, @(R14, disp8)

A

B

16

12

70

a

– – – – Ri → (Rj)

– – – – Ri → (R13 + Rj)

– – – – Ri → (R14 + disp8)

Byte

Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler

description from disp8 to disp10 are as follows:

disp8 → o8 = disp8

disp9 → o8 = disp9>>1

disp10 → o8 = disp10>>2

udisp6 → u4 = udisp6>>2

Each disp is a code extension.

udisp4 is a 0 extension.

• Transfer instructions between registers/special-purpose registers transfer instructions

(5 instructions)

Type

Mnemonic

OP Cycle N Z V C

Operation

Remarks

MOV

Rj, Ri

A

8B

1

– – – – Rj → Ri

Transfer between

general-purpose

registers

MOV

Rs, Ri

Ri, Rs

A

B7

B3

1

– – – – Rs → Ri

– – – – Ri → Rs

Rs: Special-purpose

register

Rs: Special-purpose

register

MOV

PS, Ri

Ri, PS

E

17 – 1

07 – 1

1

c

– – – – PS → Ri

C C C C Ri → PS

103

MB91101/MB91101A

• Non-delay normal branch instructions (23 instructions)

Type

E

Mnemonic

@Ri

OP Cycle N Z V C

Operation

– – – – Ri → PC

– – – – PC + 2 → RP,

Remarks

JMP

97 – 0

D0

2

CALL

label12

F

PC + 2 + rel11 × 2 → PC

– – – – PC + 2 → RP, Ri → PC

CALL

RET

INT

@Ri

E

D

97 – 1

97 – 2

1F

2

– – – – RP → PC

Return

#u8

3+3a – – – – SSP – = 4, PS → (SSP),

SSP – = 4,

PC + 2 → (SSP),

0 → I flag,

0 → S flag,

(TBR + 3FC – u8 × 4) →

PC

INTE

RETI

E

9F – 3 3 + 3a – – – – SSP – = 4, PS → (SSP), For emulator

SSP – = 4,

PC + 2 → (SSP),

0 → S flag,

(TBR + 3D8 – u8 × 4) →

PC

97 – 3 2 + 2a C C C C (R15) → PC, R15 – = 4,

(R15) → PS, R15 – = 4

BNO

BRA

BEQ

BNE

BC

BNC

BN

label9

D

E1

E0

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

1

2

– – – – Non-branch

– – – – PC + 2 + rel8 × 2 → PC

– – – – PCif Z = = 1

– – – – PCif Z = = 0

– – – – PCif C = = 1

– – – – PCif C = = 0

– – – – PCif N = = 1

– – – – PCif N = = 0

– – – – PCif V = = 1

2/1

BP

BV

BNV

BLT

BGE

BLE

BGT

BLS

BHI

– – – – PCif V = = 0

– – – – PCif V xor N = = 1

– – – – PCif V xor N = = 0

– – – – PCif (V xor N) or Z = = 1

– – – – PCif (V xor N) or Z = = 0

– – – – PCif C or Z = = 1

– – – – PCif C or Z = = 0

Notes: • “2/1” in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch.

• The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and

assembler discription label9 and label12 are as follows.

label9 → rel8 = (label9 – PC – 2)/2

label12 → rel11 = (label12 – PC – 2)/2

• RETI must be operated while S flag = 0.

104

MB91101/MB91101A

• Branch instructions with delays (20 instructions)

Type

E

Mnemonic

OP Cycle N Z V C

Operation

– – – – Ri → PC

– – – – PC + 4 → RP,

Remarks

JMP:D

@Ri

9F – 0

D8

1

CALL:D label12

F

PC + 2 + rel11 × 2 → PC

– – – – PC + 4 → RP, Ri → PC

CALL:D @Ri

RET:D

E

9F – 1

9F – 2

1

– – – – RP → PC

Return

BNO:D

BRA:D

BEQ:D

BNE:D

BC:D

BNC:D

BN:D

label9

D

F1

F0

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

1

– – – – Non-branch

– – – – PC + 2 + rel8 × 2 → PC

– – – – PCif Z = = 1

– – – – PCif Z = = 0

– – – – PCif C = = 1

– – – – PCif C = = 0

– – – – PCif N = = 1

– – – – PCif N = = 0

– – – – PCif V = = 1

BP:D

BV:D

BNV:D

BLT:D

BGE:D

BLE:D

BGT:D

BLS:D

BHI:D

– – – – PCif V = = 0

– – – – PCif V xor N = = 1

– – – – PCif V xor N = = 0

– – – – PCif (V xor N) or Z = = 1

– – – – PCif (V xor N) or Z = = 0

– – – – PCif C or Z = = 1

– – – – PCif C or Z = = 0

Notes: • The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and

assembler discription label9 and label12 are as follows.

label9 → rel8 = (label9 – PC – 2)/2

label12 → rel11 = (label12 – PC – 2)/2

• Delayed branch operation always executes next instruction (delay slot) before making a branch.

• Instructions allowed to be stored in the delay slot must meet one of the following conditions. If the other

instruction is stored, this device may operate other operation than defined.

The instruction described “1” in the other cycle column than branch instruction.

The instruction described “a”, “b”, “c” or “d” in the cycle column.

105

MB91101/MB91101A

• Direct addressing instructions

Type

Mnemonic

OP Cycle N Z V C

Operation

Remarks

DMOV

@dir10, R13

D

08

18

0C

1C

0B

1B

b

a

2a

– – – – (dir10) → R13

– – – – R13 → (dir10)

– – – – (dir10) → (R13), R13 + = 4 Word

– – – – (R13) → (dir10), R13 + = 4 Word

– – – – R15 – = 4, (dir10) → (R15) Word

– – – – (R15) → (dir10), R15 + = 4 Word

Word

R13,

@dir10

@dir10, @R13+

@R13+, @dir10

@dir10, @–R15

@R15+, @dir10

DMOVH @dir9, R13

D

09

19

0D

1D

b

a

2a

– – – – (dir9) → R13

– – – – R13 → (dir9)

– – – – (dir9) → (R13), R13 + = 2 Half word

– – – – (R13) → (dir9), R13 + = 2 Half word

Half word

DMOVH R13,

@dir9

DMOVH @dir9, @R13+

DMOVH @R13+, @dir9

DMOVB @dir8, R13

D

0A

1A

0E

1E

b

a

2a

– – – – (dir8) → R13

– – – – R13 → (dir8)

– – – – (dir8) → (R13), R13 + + Byte

– – – – (R13) → (dir8), R13 + + Byte

Byte

DMOVB R13,

@dir8

DMOVB @dir8, @R13+

DMOVB @R13+, @dir8

Note: The relations between the dir field of TYPE-D in the instruction format and the assembler description from

disp8 to disp10 are as follows:

disp8 → dir + disp8

disp9 → dir = disp9>>1

Each disp is a code extension

disp10 → dir = disp10>>2

• Resource instructions (2 instructions)

Type

Mnemonic

OP Cycle N Z V C

Operation

Remarks

LDRES @Ri+, #u4

C

BC

a

– – – – (Ri) → u4 resource

u4: Channel number

Ri + = 4

STRES #u4,

@Ri+

C

BD

a

– – – – u4 resource → (Ri)

u4: Channel number

Ri + = 4

• Co-processor instructions (4 instructions)

Type

Mnemonic

OP Cycle N Z V C

Operation

Remarks

COPOP #u4, #CC, CRj, CRi

COPLD #u4, #CC, Rj, CRi

COPST #u4, #CC, CRj, Ri

COPSV #u4, #CC, CRj, Ri

E

9F – C 2 + a – – – – Calculation

9F – D 1 + 2a – – – – Rj → CRi

9F – E 1 + 2a – – – – CRj → Ri

9F – F 1 + 2a – – – – CRj → Ri

No error traps

106

MB91101/MB91101A

• Other instructions (16 instructions)

Type

Mnemonic

OP Cycle N Z V C

Operation

Remarks

NOP

E

9F – A

1

– – – – No changes

ANDCCR #u8

ORCCR #u8

D

83

93

c

C C C C CCR and u8 → CCR

C C C C CCR or u8 → CCR

STILM

#u8

D

87

1

– – – – i8 → ILM

Set ILM immediate

value

1

D

A3

1

– – – – R15 + = s10

ADD SP instruction

ADDSP #s10

EXTSB Ri

EXTUB Ri

EXTSH Ri

EXTUH Ri

*

E

97 – 8

97 – 9

97 – A

97 – B

1

– – – – Sign extension 8 → 32 bits

– – – – Zero extension 8 → 32 bits

– – – – Sign extension 16 → 32 bits

– – – – Zero extension 16 → 32 bits

4

LDM0

LDM1

(reglist)

D

8C

8D

– – – – (R15) → reglist,

R15 increment

– – – – (R15) → reglist,

R15 increment

Load-multi R0 to R7

Load-multi R8 to R15

*

4

(reglist)

*

3

– – – – (R15 + +) → reglist,

Load-multi R0 to R15

Store-multi R0 to R7

* LDM

STM0

(reglist)

*

–

6

D

8E

8F

– – – – R15 decrement,

reglist → (R15)

– – – – R15 decrement,

reglist → (R15)

*

6

STM1

(reglist)

Store-multi R8 to R15

Store-multi R0 to R15

*

5

2

– – – – reglist → (R15 + +)

* STM2 (reglist)

ENTER #u10

*

–

D

0F

1+a – – – – R14 → (R15 – 4),

R15 – 4 → R14,

Entrance processing

of function

R15 – u10 → R15

LEAVE

E

A

9F – 9

8A

b

– – – – R14 + 4 → R15,

(R15 – 4) → R14

Exit processing of

function

XCHB

@Rj, Ri

2a

– – – – Ri → TEMP,

(Rj) → Ri,

For SEMAFO

management

Byte data

TEMP → (Rj)

*1: In the ADDSP instruction, the reference between u8 of TYPE-D in the instruction format and assembler

description s10 is as follows.

s10 → s8 = s10>>2

*2: In the ENTER instruction, the reference between i8 of TYPE-C in the instruction format and assembler

description u10 is as follows.

u10 → u8 = u10>>2

*3: If either of R0 to R7 is specified in reglist, assembler generates LDM0. If either of R8 to R15 is specified,

assembler generates LDM1. Both LDM0 and LDM1 may be generated.

*4: The number of cycles needed for execution of LDM0 (reglist) and LDM1 (reglist) is given by the following

calculation; a × (n – 1) + b + 1 when “n” is number of registers specified.

*5: If either of R0 to R7 is specified in reglist, assembler generates STM0. If either of R8 to R15 is specified,

assembler generates STM1. Both STM0 and STM1 may be generated.

*6: The number of cycles needed for execution of STM0 (reglist) and STM1 (reglist) is given by the following

calculation; a × n + 1 when “n” is number of registers specified.

107

MB91101/MB91101A

• 20-bit normal branch macro instructions

Mnemonic

Operation

Remarks

1

* CALL20 label20, Ri

Next instruction address → RP, label20 → PC

Ri: Temporary register

*

2

3

* BRA20

* BEQ20

* BNE20

* BC20

* BNC20

* BN20

label20, Ri

label20 → PC

if (Z = = 1) then label20 → PC

ifs/Z = = 0

ifs/C = = 1

ifs/C = = 0

ifs/N = = 1

ifs/N = = 0

ifs/V = = 1

ifs/V = = 0

ifs/V xor N = = 1

ifs/V xor N = = 0

ifs/(V xor N) or Z = = 1

ifs/(V xor N) or Z = = 0

ifs/C or Z = = 1

ifs/C or Z = = 0

Ri: Temporary register

*

* BP20

* BV20

* BNV20

* BLT20

* BGE20

* BLE20

* BGT20

* BLS20

* BHI20

*1: CALL20

(1) If label20 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;

CALL label12

(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:20 #label20, Ri

CALL

*2: BRA20

(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;

BRA label9

@Ri

(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:20 #label20, Ri

JMP

@Ri

*3: Bcc20 (BEQ20 to BHI20)

(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;

Bcc

label9

(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

Bxcc

false

xcc is a revolt condition of cc

LDI:20 #label20, Ri

JMP

@Ri

false:

108

MB91101/MB91101A

• 20-bit delayed branch macro instructions

Mnemonic

Operation

Remarks

1

* CALL20:D label20, Ri

Next instruction address + 2 → RP, label20 → PC

Ri: Temporary register

*

2

3

* BRA20:D label20, Ri

* BEQ20:D label20, Ri

* BNE20:D label20, Ri

label20 → PC

if (Z = = 1) then label20 → PC

ifs/Z = = 0

ifs/C = = 1

ifs/C = = 0

ifs/N = = 1

ifs/N = = 0

ifs/V = = 1

ifs/V = = 0

ifs/V xor N = = 1

ifs/V xor N = = 0

ifs/(V xor N) or Z = = 1

ifs/(V xor N) or Z = = 0

ifs/C or Z = = 1

ifs/C or Z = = 0

Ri: Temporary register

*

* BC20:D

label20, Ri

* BNC20:D label20, Ri

* BN20:D

* BP20:D

* BV20:D

label20, Ri

* BNV20:D label20, Ri

* BLT20:D label20, Ri

* BGE20:D label20, Ri

* BLE20:D label20, Ri

* BGT20:D label20, Ri

* BLS20:D label20, Ri

* BHI20:D label20, Ri

*1: CALL20:D

(1) If label20 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;

CALL:D label12

(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:20 #label20, Ri

CALL:D @Ri

*2: BRA20:D

(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;

BRA:D label9

(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:20 #label20, Ri

JMP:D @Ri

*3: Bcc20:D (BEQ20:D to BHI20:D)

(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;

Bcc:D

label9

(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

Bxcc

false

xcc is a revolt condition of cc

LDI:20 #label20, Ri

JMP:D @Ri

false:

109

MB91101/MB91101A

• 32-bit normal macro branch instructions

Mnemonic

Operation

Remarks

1

* CALL32 label32, Ri

Next instruction address → RP, label32 → PC

Ri: Temporary register

*

2

3

* BRA32

* BEQ32

* BNE32

* BC32

* BNC32

* BN32

label32, Ri

label32 → PC

if (Z = = 1) then label32 → PC

ifs/Z = = 0

ifs/C = = 1

ifs/C = = 0

ifs/N = = 1

ifs/N = = 0

ifs/V = = 1

ifs/V = = 0

ifs/V xor N = = 1

ifs/V xor N = = 0

ifs/(V xor N) or Z = = 1

ifs/(V xor N) or Z = = 0

ifs/C or Z = = 1

ifs/C or Z = = 0

Ri: Temporary register

*

* BP32

* BV32

* BNV32

* BLT32

* BGE32

* BLE32

* BGT32

* BLS32

* BHI32

*1: CALL32

(1) If label32 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;

CALL label12

(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:32 #label32, Ri

CALL

*2: BRA32

(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;

BRA label9

@Ri

(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:32 #label32, Ri

JMP

@Ri

*3: Bcc32 (BEQ32 to BHI32)

(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;

Bcc

label9

(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

Bxcc

false

xcc is a revolt condition of cc

LDI:32 #label32, Ri

JMP

@Ri

false:

110

MB91101/MB91101A

• 32-bit delayed macro branch instructions

Mnemonic

Operation

Remarks

1

* CALL32:D label32, Ri

Next instruction address + 2 → RP, label32 → PC

Ri: Temporary register

*

2

3

* BRA32:D label32, Ri

* BEQ32:D label32, Ri

* BNE32:D label32, Ri

label32 → PC

if (Z = = 1) then label32 → PC

ifs/Z = = 0

ifs/C = = 1

ifs/C = = 0

ifs/N = = 1

ifs/N = = 0

ifs/V = = 1

ifs/V = = 0

ifs/V xor N = = 1

ifs/V xor N = = 0

ifs/(V xor N) or Z = = 1

ifs/(V xor N) or Z = = 0

ifs/C or Z = = 1

ifs/C or Z = = 0

Ri: Temporary register

*

* BC32:D

label32, Ri

* BNC32:D label32, Ri

* BN32:D

* BP32:D

* BV32:D

label32, Ri

* BNV32:D label32, Ri

* BLT32:D label32, Ri

* BGE32:D label32, Ri

* BLE32:D label32, Ri

* BGT32:D label32, Ri

* BLS32:D label32, Ri

* BHI32:D label32, Ri

*1: CALL32:D

(1) If label32 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;

CALL:D label12

(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:32 #label32, Ri

CALL:D @Ri

*2: BRA32:D

(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;

BRA:D label9

(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

LDI:32 #label32, Ri

JMP:D @Ri

*3: Bcc32:D (BEQ32:D to BHI32:D)

(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;

Bcc:D

label9

(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is

generated as follows;

Bxcc

false

xcc is a revolt condition of cc

LDI:32 #label32, Ri

JMP:D @Ri

false:

111

MB91101/MB91101A

■ ORDERING INFORMATION

Part number

MB91101APFV

MB91101APF

Package

Remarks

100-pin Plastic LQFP

(FPT-100P-M05)

100-pin Plastic QFP

(FPT-100P-M06)

112

MB91101/MB91101A

■ PACKAGE DIMENSIONS

100-pin Plastic LQFP

(FPT-100P-M05)

16.00±0.20(.630±.008)SQ

1.50 –⁺0⁰.^.1²0⁰

(Mouting height)

.059 –⁺.^.0⁰0⁰4⁸

75

51

14.00±0.10(.551±.004)SQ

76

50

12.00

(.472)

REF

15.00

(.591)

NOM

Details of "A" part

0.15(.006)

INDEX

0.15(.006)

100

26

0.15(.006)MAX

0.40(.016)MAX

"B"

1

25

LEAD No.

"A"

0.50(.0197)TYP

0.18 –⁺0⁰.^.0⁰3⁸

0.127 ⁺–0⁰.^.0⁰2⁵

.005 ⁺^–.^.⁰⁰⁰⁰¹²

M

Details of "B" part

0.08(.003)

.007 –⁺.^.0⁰0⁰1³

0.10±0.10

(.004±.004)

(STAND OFF)

0.50±0.20(.020±.008)

0.10(.004)

0~10°

C

Dimensions in mm (inches)

1995 FUJITSU LIMITED F100007S-2C-3

(Continued)

113

MB91101/MB91101A

(Continued)

100-pin Plastic QFP

(FPT-100P-M06)

23.90±0.40(.941±.016)

3.35(.132)MAX

(Mounting height)

20.00±0.20(.787±.008)

0.05(.002)MIN

(STAND OFF)

80

51

81

50

12.35(.486)

REF

14.00±0.20 17.90±0.40

(.551±.008) (.705±.016)

16.30±0.40

(.642±.016)

INDEX

31

100

"A"

1

30

LEAD No.

0.65(.0256)TYP

0.30±0.10

(.012±.004)

0.15±0.05(.006±.002)

Details of "B" part

M

0.13(.005)

Details of "A" part

0.25(.010)

0.30(.012)

"B"

0.10(.004)

0

10°

0.18(.007)MAX

0.53(.021)MAX

18.85(.742)REF

0.80±0.20

(.031±.008)

22.30±0.40(.878±.016)

Dimensions in mm (inches)

C

1994 FUJITSU LIMITED F100008-3C-2

Note: The design may be modified changed without notice, contact to Fujitsu sales division when using the device.

114

MB91101/MB91101A

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: 81(44) 754-3763

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

Fax: 81(44) 754-3329

http://www.fujitsu.co.jp/

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications,

and are not intended to be incorporated in devices for actual use.

Also, FUJITSU is unable to assume responsibility for

infringement of any patent rights or other rights of third parties

arising from the use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and

Fax: (408) 922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608

measurement equipment, personal or household devices, etc.).

CAUTION:

Fax: (408) 922-9179

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded

(such as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Any semiconductor devices have an inherent chance of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

Fax: (65) 281-0220

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for

export of those products from Japan.

http://www.fmap.com.sg/

F9907

FUJITSU LIMITED Printed in Japan

115


型号：	MB91101
厂家：	FUJITSU
描述：	32-bit RISC Microcontroller 32位RISC微控制器微控制器
文件：	总115页 (文件大小：1151K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB91101 [FUJITSU]

相关型号：

MB91101A

MB91101APF

MB91101APF-G-JNE1

MB91101APFV

MB91101APMC

MB91101PF-G-BND-R

MB91101PFV-G-BND-R

MB91106

MB91106PF

MB91106PF-XXX

MB91106PFV

MB91107