MB91133PMT2 [FUJITSU]
32-Bit RISC Microcontroller; 32位RISC微控制器
| 型号： | MB91133PMT2 |
| 厂家： | 
FUJITSU |
| 描述： | 32-Bit RISC Microcontroller |
| 文件： | 总123页 (文件大小：1268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16308-1E
32-Bit RISC Microcontroller
CMOS
FR30 Series
MB91133/MB91F133
■ DESCRIPTION
The MB91133/MB91F133, a standard single-chip microcontroller featuring various I/O resources and bus control
mechanisms to incorporate the control required for high-performance high-speed CPU processes, is the core unit
in the 32-bit RISC CPU (FR family) .
This unit has the optimal specifications for incorporating applications that require high-performance CPU pro-
cessing power by featuring peripheral I/O resources suitable for single-lens reflex cameras, digital video cameras,
etc.
■ FEATURES
1. CPU
• 32-bit RISC (FR30) , load/store architecture, 5-level pipeline
• Multi-purpose register : 32 bits × 16
• 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle
• Instructions for barrel shift, bit processing and inter-memory transfers : Instructions suited to loading purposes
• Function entry / exit instruction, multi load / store instruction of register details : High-level language handling
instruction
• Register interlock function : Simplification of assembler description
• Branch instruction with delay slot : Reduction in overheads in case of branching
• Multiplier is built-in / supported at instruction level.
• Signed 32-bit multiplication : 5 cycles
• Signed 16-bit multiplication : 3 cycles
• Interruption (saving PC and PS) : 6 cycles, 16 priority levels
(Continued)
■ PACKAGES
144-pin plastic FBGA
144-pin plastic LQFP
(BGA-144P-M01)
(FPT-144P-M08)
MB91133/MB91F133
(Continued)
2. Bus Interface
• 24-bit address output, 8/16-bit data input/output
• Basic bus cycle : 2 clock cycles
• Interface support for various memories
• Unused data and address pins can be used as input/output ports.
• Supports “little endian” mode
3. Built-in ROM
Mask device : 254 KB; FLASH device : 254 KB; EVA-FLASH device : 254 KB
4. Built-in RAM
Mask device : 8 KB; FLASH device : 8 KB; EVA-FLASH device : 8 KB
5. DMA Controller
This is a descriptor-type MA controller whose transfer parameters are arranged in the main memory.
A maximum of 8 factors in total (internal and external) can be transferred.
External factors are 3 channels.
6. Bit Search Module
Searches the first “1” / “0” change bit positions within 1 cycle from MSB in 1 word
7. Timer
• 16-bit reload timer × 5 channels
• 16-bit OCU × 8 channels, ICU × 4 channels, free-run timer × 1 channel
Output waveform adjusting function for AC motor waveforms is included in the above timer.
• 8/16-bit up/down timer/counter (8-bit × 2 channels or 16-bit × 1 channel)
External interruption and pin are shared for AIN and BIN.
• 16-bit down count timer × 5 channels; can also be used as the UART baud rate timer
• 16-bit PPG timer × 6 channels; out-pulse cycle / duty can be changed at random
8. D/A Converter
• 8-bit × 3 channels
9. A/D Converter (Sequential comparison type)
• 10-bit × 8 channels
• Sequential conversion method (conversion time 5.0 µs at 33 MHz)
• Setting for single conversion, scan conversion and repeat conversion is possible.
• Conversion starting function using hardware or software
10. Serial I/O
• UART × 5 channels; clock synchronous serial transfer with LSB / MSB switching function is possible for both.
• Serial data output or serial lock output can be selected using push-pull / open-drain software.
11. Level Comparator Input
• 1 channel; shared input and pins of A/D converter.
12. Clock Switching Function
• Base clock : Software can be used to select from two types of clock sources, namely 32 kHz and high-speed.
• Gear function : Four types of settings (1 : 1, 1 : 2, 1 : 4, 1 : 8) can be set individually as the operating clock
ratio to the basic clock per CPU and peripheral equipment.
2
MB91133/MB91F133
13. Interruption Controller
• External interruption input (total 24 channels)
• With pull up pin control / standby return function : 4 channels
(rising / falling / H level / L level settings are possible)
• With pull up pin control / standby return function; AIN / BIN pins of the up/down counter are shared : 4 channels
(rising / falling / H level / L level settings are possible)
• With pull up pin controln : 16 channels
(rising / falling / H level / L level settings are possible)
• Internal interruption factor
• Interruption / delay interruption by resource
14. Others
• Reset factors
Power on reset, watchdog timer, software reset, external reset
• Low power consumption mode
Sleep/stop mode
• Packages
FBGA-144, LQFP-144
• CMOS technology (0.35 µm)
• Power
Two power sources (5 V / 3 V)
1) 5 V system : 5 V ± 10% (A/D, D/A and level comparator included)
2) 3 V system : A) 3.0 V to 3.6 V : All functions guaranteed
B) 2.7 V to 3.0 V : All functions guaranteed for single-chip mode of mask devices only
■ PRODUCT LINEUP
MB91133
MB91F133
MB91FV130
Piggy/EVA device
(for evaluation /
development)
MASK ROM device
(mass production item)
FLASH ROM device
(for evaluation)
CLASSIFICATION
RAM capacity
CROM capacity
FLASH capacity
CRAM capacity
Others
6 KB
6 KB
6 KB
254 KB
254 KB
2 KB
254 KB
2 KB
2 KB
Mass production
Trial production
Provided
3
MB91133/MB91F133
■ PIN ASSIGNMENTS
• MB91FV130
(BOTTOM VIEW)
3
299 296 293 277 274 270 268 278 275 262 254 247 257 252 250 245 233 230 224
298 292 289 286 283 280 276 269 264 263 258 251 248 243 240 237 234 225 221
2
5
10
13
4
6
297 291 287 284 279 271 265 261 256 249 242 239 235 229 228 219 218
300 295 290 285 281 272 267 259 255 246 241 236 231 226 223 215 207
8
16 11
7
1
9
294 288 282 273 266 260 253 244 238 232 227 222 217 212 202
220 216 213 209 199
25
27 19 15 12
23 18 17 14
34 26 24 21 20
33 31 30 28
29 39 38 35 36
40 41 43 42
214 211 210 205 195
32
208 206 204 201 203
198 197 196 194 200
22
192 193 191 190 187
186 185 188 189 179
37
50 44 46 47 48
53 51 54 56 58
45 55 60 61 64
178 180 181 183 172
170 171 174 176 184
164 167 168 173 182
59 63 66 70
159 162 165 169 177
49
52
57
68
71
74
62 67 72 77 82 88 94 103 110 116 123 133 139 145 153 157 161 166 175
65 73 76 81 86 91 96 105 109 117 122 131 136 141 147 151 156 163 158
69 78 79 85 89 92 99 106 111 115 121 129 135 138 142 148 154 160 155
75 84 87 90 93 98 101 108 113 114 119 126 130 134 137 140 144 150 152
80 83 95 100 102 107 97 104 112 125 128 118 120 124 127 132 143 146 149
(PGA-299C-A01)
4
MB91133/MB91F133
• MB91F133/MB91133
(TOP VIEW)
108
14
107 106 102
99
96
92
93
91
94
89
88
90
87
85
84
86
82
81
83
79
78
80
75
76
77
68
65
62
55
54
50
47
44
41
33
34
74
73
69
67
64
61
57
52
48
45
42
40
37
35
72
71
70
66
63
60
56
53
49
46
43
39
38
36
110 109 105 103 100 97
111 112 113 104 101 98
13
12
11
10
9
115 114 116
95
118 117 119
121 120 122
59
58
51
125 124 126 123
128 129 127 130
132 133 134 131
135 136 137
8
7
6
5
15
18
16
17
22
19
21
20
23
26
25
24
4
138 139 140
3
142 141
5
4
3
8
6
7
11
9
14
12
13
29
28
27
32
31
30
2
143
144
1
2
1
10
A
B
C
D
E
F
G
H
J
K
L
M
N
P
INDEX
(BGA-144P-M01)
5
MB91133/MB91F133
• MB91F133/MB91133
(TOP VIEW)
1
108
107
106
105
104
103
102
101
100
99
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23
VSS
VCC5
2
PH0/SIN0
PH1/SOT0
PH2/SCK0
PI0/SIN1
PI1/SOT1
PI2/SCK1
PI3/SIN2
PI4/SOT2
PI5/SCK2
PJ0/SIN3
PJ1/SOT3
PJ2/SCK3
PJ3/SIN4
PJ4/SOT4
PJ5/SCK4
VCC3
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
P30/D24
P31/D25
P32/D26
P33/D27
P34/D28
P35/D29
P36/D30
P37/D31
P40/A00
P41/A01
P42/A02
P43/A03
P44/A04
P45/A05
P46/A06
P47/A07
VSS
98
97
96
95
94
93
92
91
VSS
90
PG5/PPG5
PG4/PPG4
PG3/PPG3
PG2/PPG2
PG1/PPG1
PG0/PPG0
PF7/RTO7
PF6/RTO6
PF5/RTO5
PF4/RTO4
PF3/RTO3
PF2/RTO2
PF1/RTO1
PF0/RTO0
PE7/DTTI
PE6/FRCK
PE5/IN3
89
88
87
86
85
84
83
82
VCC5
81
P50/A08
P51/A09
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
P60/A16/INT16
80
79
78
77
76
75
74
73
PE4/IN2
(FPT-144P-M08)
6
MB91133/MB91F133
■ PIN NUMBERS LIST
• Device : MB91FV130 Package : PGA-299C-A01
No.
1
Pin Name
P20/D16
VSS
No.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Pin Name
P54/A12
No.
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
Pin Name
N.C.
No.
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
Pin Name
PK3/AN3
VCC5
2
P55/A13
N.C.
3
OPEN
VCC5
VSS
PK4/AN4
PK5/AN5
PK6/AN6
PK7/AN7/CMP
DAVC
4
P21/D17
VCC5
P56/A14
N.C.
5
P57/A15
N.C.
6
P22/D18
P23/D19
VSS
P60/A16/INT16
P61/A17/INT17
P62/A18/INT18
P63/A19/INT19
P64/A20/INT20
P65/A21/INT21
P66/A22/INT22
P67/A23/INT23
P80/RDY
VCC5
7
N.C.
8
MD0
DAVS
9
P24/D20
P25/D21
P26/D22
P27/D23
P30/D24
P31/D25
P32/D26
P33/D27
P34/D28
P35/D29
P36/D30
P37/D31
P40/A00
VCC5
MD1
DA0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
MD2
VSS
VCC3
DA1
VSS
DA2
X0
PH0/SIN0
PH1/SOT0
PH2/SCK0
PI0/SIN1
PI1/SOT1
PI2/SCK1
PI3/SIN2
PI4/SOT2
PI5/SCK2
PJ0/SIN3
VCC5
X1
VCC3
VCC5
VSS
RST
P81/BGRNT
P82/BRQ
N.C.
ICLK
ICS0
ICS1
ICS2
ICD0
ICD1
ICD2
ICD3
BREAK
AVCC
AVRH
VSS
VCC5
P83/RD
P84/WR0
P85/WR1
P86/CLK
P41/A01
P42/A02
P43/A03
P44/A04
P45/A05
P46/A06
VSS
PL0/DREQ0
PL1/DACK0
PL2/DEOP0
PL3/DREQ1
PL4/DACK1
PL5/DEOP1
PL6/DREQ2
PL7/DACK2
N.C.
PJ1/SOT3
PJ2/SCK3
VSS
VCC3
X0A
X1A
P47/A07
P50/A08
P51/A09
P52/A10
P53/A11
AVRL
AVSS
PK0/AN0
PK1/AN1
PK2/AN2
VSS
PJ3/SIN4
PJ4/SOT4
PJ5/SCK4
PC0/INT0
N.C.
VCC5
(Continued)
7
MB91133/MB91F133
(Continued)
No.
137
138
139
140
141
142
143
144
145
146
147
Pin Name
PC1/INT1
No.
173
174
175
176
177
178
179
180
181
182
183
Pin Name
PF5/RTO5
PF6/RTO6
PF7/RTO7
PG0/PPG0
PG1/PPG1
PG2/PPG2
VSS
No.
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
Pin Name
TAD14
TAD15
VCC3
No.
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
Pin Name
TDT23
TDT24
VSS
No.
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
Pin Name
TDT53
TDT54
TDT55
TDT56
TDT57
VCC3
PC2/INT2
PC3/INT3
PC4/INT4/AIN0
PC5/INT5/BIN0
PC6/INT6/AIN1
VCC5
TOE
TDT25
TDT26
TDT27
TDT28
TDT29
TDT30
VCC5
TCE1
TADSC
TWR
TDT58
TDT59
TDT60
TDT61
TDT62
TDT63
VCC5
PC7/INT7/BIN1
PD0/INT8/TRG0
VSS
PG3/PPG3
PG4/PPG4
PG5/PPG5
N.C.
TDT00
TDT01
VSS
PD1/INT9/TRG1
TDT02
TDT03
VCC5
TDT31
TDT32
TDT33
TDT34
TDT35
TDT36
TDT37
VSS
148 PD2/INT10/TRG2 184
149 VCC5 185
N.C.
N.C.
150 PD3/INT11/TRG3 186
151 PD4/INT12/TRG4 187
N.C.
TDT04
TDT05
VSS
TDT64
TDT65
VSS
VCC5
152
VSS
188
EXRAM
TAD00
TAD01
TAD02
TAD03
VCC3
153 PD5/INT13/TRG5 189
154 PD6/INT14/DEOP2 190
TDT06
TDT07
TDT08
TDT09
TDT10
VCC5
TDT66
TDT67
VCC5
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
VCC5
PD7/INT15/ATG
PE0/ZIN0
VSS
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
TDT38
TDT39
TDT40
TDT41
TDT42
TDT43
VCC3
TDT68
TAD04
TAD05
TAD06
TAD07
TAD08
TAD09
VSS
PE1/ZIN1
PE2/IN0
TDT11
TDT12
VSS
PE3/IN1
PE4/IN2
TDT13
TDT14
TDT15
TDT16
TDT17
TDT18
VCC3
TDT44
TDT45
TDT46
TDT47
TDT48
VCC5
PE5/IN3
PE6/FRCK
PE7/DTTI
VCC3
TAD10
TAD11
VCC5
PF0/RTO0
PF1/RTO1
PF2/RTO2
PF3/RTO3
PF4/RTO4
VCC5
TAD12
TAD13
TAD14
TAD15
TCLK
TDT49
TDT50
VSS
TDT19
TDT20
TDT21
TDT22
TDT51
TDT52
8
MB91133/MB91F133
• Device : MB91F133/MB91133 Package : BGA-144P-M01/FPT-144P-M08
LQFP FBGA
Pin Name
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23
VSS
LQFP FBGA
Pin Name
P60/A16/INT16
P61/A17/INT17
P62/A18/INT18
P63/A19/INT19
P64/A20/INT20
P65/A21/INT21
P66/A22/INT22
P67/A23/INT23
VCC3
LQFP FBGA
Pin Name
PE2/IN0
1
B2
B1
C1
C2
C3
D2
D1
D3
E2
E1
E3
F2
F1
F3
G4
G2
G1
G3
H3
H1
H2
H4
J4
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
P1
N2
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
P13
P14
N13
N14
M14
M13
M12
L13
L14
L12
K13
K14
K12
J13
2
PE3/IN1
3
P2
PE4/IN2
4
P3
PE5/IN3
5
N3
PE6/FRCK
PE7/DTTI
PF0/RTO0
PF1/RTO1
PF2/RTO2
PF3/RTO3
PF4/RTO4
PF5/RTO5
PF6/RTO6
PF7/RTO7
PG0/PPG0
PG1/PPG1
PG2/PPG2
PG3/PPG3
PG4/PPG4
PG5/PPG5
VSS
6
M3
N4
7
8
P4
9
M4
N5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
P30/D24
P31/D25
P32/D26
P33/D27
P34/D28
P35/D29
P36/D30
P37/D31
P40/A00
P41/A01
P42/A02
P43/A03
P44/A04
P45/A05
P46/A06
P47/A07
VSS
P80/RDY
P5
P81/BGRNT
P82/BRQ
M5
N6
P83/RD
P6
P84/WR0
M6
L7
P85/WR1
J14
P86/CLK
J12
N7
VSS
H11
H13
H14
H12
G12
G14
G13
G11
F11
F14
F13
F12
E14
E13
E12
D14
D13
D12
C13
P7
PC0/INT0
M7
M8
P8
PC1/INT1
PC2/INT2
PC3/INT3
N8
PC4/AIN0/INT4
PC5/BIN0/INT5
PC6/AIN1/INT6
PC7/BIN1/INT7
PD0/INT8/TRG0
PD1/INT9/TRG1
PD2/INT10/TRG2
PD3/INT11/TRG3
PD4/INT12/TRG4
PD5/INT13/TRG5
PD6/DEOP2/INT14
PD7/ATG/INT15
PE0/ZIN0
VCC3
L8
PJ5/SCK4
PJ4/SOT4
PJ3/SIN4
PJ2/SCK3
PJ1/SOT3
PJ0/SIN3
PI5/SCK2
PI4/SOT2
PI3/SIN2
PI2/SCK1
PI1/SOT1
PI0/SIN1
PH2/SCK0
J1
L9
J2
P9
J3
N9
K1
K2
K3
L1
VCC5
M9
P10
N10
M10
P11
N11
M11
N12
P12
P50/A08
P51/A09
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
L2
L3
M2
M1
N1
PE1/ZIN1
(Continued)
9
MB91133/MB91F133
(Continued)
LQFP FBGA
Pin Name
PH1/SOT0
PH0/SIN0
VCC5
LQFP FBGA
Pin Name
PL0/DREQ0
PL1/DACK0
PL2/DEOP0
PL3/DREQ1
PL4/DACK1
PL5/DEOP1
PL6/DREQ2
PL7/DACK2
RST
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
C14
B14
A14
B13
A13
B12
A12
C12
B11
A11
C11
B10
A10
C10
B9
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
C8
C7
A7
B7
D7
D6
A6
B6
C6
A5
B5
C5
A4
B4
C4
B3
A3
A2
A1
DA2
DA1
DA0
DAVS
DAVC
AVCC
AVRH
VSS
AVRL
X0A
AVSS
X1A
PK0/AN0
PK1/AN1
PK2/AN2
PK3/AN3
PK4/AN4
PK5/AN5
PK6/AN6
PK7/AN7/CMP
VCC3
X0
X1
A9
VSS
C9
MD0
D8
MD1
B8
MD2
A8
10
MB91133/MB91F133
■ PIN DESCRIPTIONS
Circuit
type
Pin No.
Pin name
Function
1
2
3
4
5
6
7
8
D16/P20
D17/P21
D18/P22
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27
External data bus bits 16 to 23
Only valid for external bus 16-bit mode. Can be used as ports in
single-chip and external bus 8-bit modes.
C
10
11
12
13
14
15
16
17
D24/P30
D25/P31
D26/P32
D27/P33
D28P34
D29/P35
D30/P36
D31/P37
External data bus bits 24 to 31
Can be used as ports in single-chip mode.
C
18
19
20
21
22
23
24
25
28
29
30
31
32
33
34
35
A00/P40
A01/P41
A02/P42
A03/P43
A04/P44
A05/P45
A06/P46
A07/P47
A08/P50
A09/P51
A10/P52
A11/P53
A12/P54
A13/P55
A14/P56
A15/P57
External address bus bits 0 to 15
Valid for external bus mode. Can be used as ports in single-chip
mode.
F
36
37
38
39
40
41
42
43
A16/INT16/P60
A17/INT17/P61
A18/INT18/P62
A19/INT19/P63
A20/INT20/P64
A21/INT21/P65
A22/INT22/P66
A23/INT23/P67
External address bus bits 16 to 23
[ INT16 to 23 ] are external interruption request inputs 16 to 23.
These inputs are always used when dealing with external interrup-
tions is permitted, so output by ports should be stopped except
when carried out intentionally.
Can be used as ports when address bus and external interruption
request input are not used.
O
C
External RDY input
This function is valid when external RDY input is permitted. “0” is
input if the bus cycle being executed is not completed.
Can be used as a port when the external RDY input is not used.
45
RDY/P80
(Continued)
11
MB91133/MB91F133
Circuit
type
Pin No.
Pin name
Function
External bus open reception output
This function is valid when external bus open reception output is
permitted. “L” is output if the external bus is opened. Can be used
as a port when the external bus open reception output is prohibit-
ed.
46
BGRNT/P81
F
External bus open request input
This function is valid when external bus open request input is per-
mitted. “1” is input if the external bus requests to be opened.
Can be used as a port when the external bus open request input is
not used.
47
BRQ/P82
C
External bus read strobe output
This function is valid when external bus read strobe output is per-
mitted. Can be used as a port when the external bus read strobe
output is prohibited.
48
49
50
51
RD/P83
WR0/P84
WR1/P85
CLK/P86
F
F
F
F
External bus write strobe output
This function is valid in external bus mode. Can be used as a port
in single-chip mode.
External bus write strobe output
This function is valid in external bus mode and with 16-bit buses.
Can be used as a port in single-chip mode or with external 8-bit
bus.
System clock output
Outputs the same clock frequency as the external bus operation.
Can be used as a port when it is not otherwise used.
External interruption request inputs 0 to 3
These inputs are always used when dealing with external interrup-
tions is permitted, so output by ports should be stopped except
when carried out intentionally.
Can be used to reset standby as input is permitted in this port un-
der standby status.Can be used as ports when external interrup-
tion request input is not used.
53
54
55
56
INT0/PC0
INT1/PC1
INT2/PC2
INT3/PC3
H
External interruption request inputs 4 to 7
These inputs are always used when dealing with external interrup-
tions is permitted, so output by ports should be stopped except
when carried out intentionally. Can be used to reset standby as in-
put is permitted in these ports under standby status.
57
58
59
60
AIN0/INT4/PC4
BIN0/INT5/PC5
AIN1/INT6/PC6
BIN1/INT7/PC7
H
[ AIN, BIN ] Up/down timer input
This input is always used when input is permitted, so output by
ports should be stopped except when carried out intentionally.
Can be used as a port when external interruption request input and
up/down timer input are not used.
(Continued)
12
MB91133/MB91F133
Circuit
type
Pin No.
Pin name
Function
External interruption request inputs 8 to 15
These inputs are always used when dealing with external interrup-
tions is permitted, so output by ports should be stopped except
when carried out intentionally.
61
62
63
64
65
66
67
68
TRG0/INT8/PD0
TRG1/INT9/PD1
TRG2/INT10/PD2
TRG3/INT11/PD3
TRG4/INT12/PD4
TRG5/INT13/PD5
DEOP2/INT14/PD6
ATG/INT15/PD7
[ TRG0 to 5 ] These are external trigger inputs for PPG timers.
[ DEOP2 ] DMA external transfer termination output
This function is valid when external transfer termination output
specification of the DMA controller is permitted.
O
[ ATG ] A/D converter external trigger input
These inputs are always used when they are selected as A/D initi-
ation factors, so output by ports should be stopped except when
carried out intentionally. Can be used as ports when not otherwise
used.
Up/down timer input
69
70
ZIN0/PE0
ZIN1/PE1
These inputs are always used when input is permitted, so output
by ports should be stopped except when carried out intentionally.
Can be used as ports when up/down timer input is not used.
O
F
71
72
73
74
IN0/PE2
IN1/PE3
IN2/PE4
IN3/PE5
Input capture input
This function is valid when input capture activates input. Can be
used as ports when input capture input is not used.
External clock input pin of free-run timer
Can be used as a port when external clock input of free-run timer
is not used.
75
76
FRCK/PE6
DTTI/PE7
F
F
RTOn pin level fixed input
Invalid when input is permitted in the waveform generation area.
Can be used as a port when RTOn pin level fixed input is not used.
77
78
79
80
81
82
83
84
RTO0/PF0
RTO1/PF1
RTO2/PF2
RTO3/PF3
RTO4/PF4
RTO5/PF5
RTO6/PF6
RTO7/PF7
Output compare event pins/waveform output pins in the
waveform generation area
Can be used as ports when specification of the output compare
event pin/waveform output pin of the waveform generation area is
prohibited.
F
F
85
86
87
88
89
90
PPG0/PG0
PPG1/PG1
PPG2/PG2
PPG3/PG3
PPG4/PG4
PPG5/PG5
PPG timer output
This function is valid when output specification of the PPG timer is
permitted. Can be used as ports when output specification of the
PPG timer is prohibited.
111
110
109
DA0
DA1
DA2
D/A converter output
This function is valid when output specification of the D/A converter
is permitted.
(Continued)
13
MB91133/MB91F133
Circuit
type
Pin No.
Pin name
Function
UART0 data input
This input is always used when UART0 activates input, so output
by ports should be stopped except when carried out intentionally.
Can be used as a port when UART0 data input is not used.
107
SIN0/PH0
P
UART0 data output
This function is valid when UART0 data output specification is per-
mitted. Can be used as a port when UART0 data output specifica-
tion is prohibited.
106
105
104
103
102
101
100
99
SOT0/PH1
SCK0/PH2
SIN1/PI0
P
P
P
P
P
P
P
P
P
P
UART0 clock input/output
This function is valid when UART0 clock output specification is per-
mitted. Can be used as a port when UART0 clock output specifi-
cation is prohibited.
UART1 data input
This input is always used when UART1 activates input, so output
by ports should be stopped except when carried out intentionally.
Can be used as a port when UART1 data input is not used.
UART1 data output
This function is valid when UART1 data output specification is per-
mitted. Can be used as a port when UART1 data output specifica-
tion is prohibited.
SOT1/PI1
SCK1/PI2
SIN2/PI3
UART1 clock input/output
This function is valid when UART1 clock output specification is per-
mitted. Can be used as a port when UART1 clock output specifi-
cation is prohibited.
UART2 data input
This input is always used when UART2 activates input, so output
by ports should be stopped except when carried out intentionally.
Can be used as a port when UART2 data input is not used.
UART2 data output
This function is valid when UART2 data output specification is per-
mitted. Can be used as a port when UART2 data output specifica-
tion is prohibited.
SOT2/PI4
SCK2/PI5
SIN3/PJ0
SOT3/PJ1
UART2 clock input/output
This function is valid when UART2 clock output specification is per-
mitted. Can be used as a port when UART2 clock output specifi-
cation is prohibited.
UART3 data input
This input is always used when UART3 activates input, so output
by ports should be stopped except when carried out intentionally.
Can be used as a port when UART3 data input is not used.
98
UART3 data output
This function is valid when UART3 data output specification is per-
mitted. Can be used as a port when UART3 data output specifica-
tion is prohibited.
97
(Continued)
14
MB91133/MB91F133
Circuit
type
Pin No.
Pin name
Function
UART3 clock input/output
This function is valid when UART3 clock output specification is per-
mitted. Can be used as a port when UART3 clock output specifi-
cation is prohibited.
96
SCK3/PJ2
P
P
P
P
UART4 data input
This input is always used when UART4 activates input, so output
by ports should be stopped except when carried out intentionally.
Can be used as a port when UART4 data input is not used.
95
94
93
SIN4/PJ3
SOT4/PJ4
SCK4/PJ5
UART4 data output
This function is valid when UART4 data output specification is per-
mitted. Can be used as a port when UART4 data output specifica-
tion is prohibited.
UART4 clock input/output
This function is valid when UART4 clock output specification is per-
mitted. Can be used as a port when UART4 clock output specifi-
cation is prohibited.
118
119
120
121
122
123
124
125
AN0/PK0
AN1/PK1
AN2/PK2
AN3/PK3
AN4/PK4
A/D converter analog input
This is valid when the AICK register specification is analog input.
N
F
[ CMP ] level comparator input
Can be used as ports when A/D converter analog input is not used.
AN5/PK5
AN6/PK6
CMP/AN7/PK7
DMA external transfer request input
This input is always used if selected as the transfer factor for the
DMA controller, so output by ports should be stopped except when
carried out intentionally. Can be used as a port when DMA exter-
nal transfer request input is not used.
126
DREQ0/PL0
DMA external transfer request reception output
This function is valid when external transfer request reception out-
put specification of the DMA controller is permitted. Can be used
as a port when transfer request reception output specification of
the DMA controller is prohibited.
127
128
129
DACK0/PL1
DEOP0/PL2
DREQ1/PL3
F
F
F
DMA external transfer termination output
This function is valid when external transfer termination output
specification of the DMA controller is permitted.
DMA external transfer request input
This input is always used if selected as the transfer factor for the
DMA controller, so output by ports should be stopped except when
carried out intentionally. Can be used as a port when DMA exter-
nal transfer request input is not used.
(Continued)
15
MB91133/MB91F133
(Continued)
Circuit
type
Pin No.
Pin name
Function
DMA external transfer request reception output
This function is valid when external transfer request reception out-
put specification of the DMA controller is permitted. Can be used
as a port when transfer request reception output specification of
the DMA controller is prohibited.
130
DACK1/PL4
F
DMA external transfer termination output
131
132
DEOP1/PL5
DREQ2/PL6
F
F
This function is valid when external transfer termination output
specification of the DMA controller is permitted.
DMA external transfer request input
This input is always used if selected as the transfer factor for the
DMA controller, so output by ports should be stopped except when
carried out intentionally. Can be used as a port when DMA exter-
nal transfer request input is not used.
DMA external transfer request reception output
This function is valid when external transfer request reception out-
put specification of the DMA controller is permitted. Can be used
as a port when transfer request reception output specification of
the DMA controller is prohibited.
133
134
DACK2/PL7
RST
F
B
K
External reset input
136
137
X0A
X1A
Oscillation pin for low-speed clock (32 kHz)
139
140
X0
X1
A
Oscillation pin for high-speed clock (16.5 MHz)
142
143
144
MD0
MD1
MD2
Mode pins
G
Basic MCU operation mode is set by these pins. They should be
directly connected to VCC or VSS for use.
112
113
114
DAVS
DAVC
AVCC
Ground pin of D/A converter (connected to analog ground)
Power pin of D/A converter
Power pin for A/D converter
Reference voltage pin for A/D converter (high electric poten-
tial side)
When this pin is turned on/off, AVRH or more electric potential
must be supplied to VCC.
115
AVRH
Reference voltage pin for A/D converter (low electric potential
side)
116
117
AVRL
AVSS
VCC5
Ground pin for A/D converter (connected to analog ground)
5 V power of digital circuit
Power must be connected to all VCC5 pins for use.
27, 108
44, 92
138
3 V power of digital circuit
Power must be connected to all VCC3 pins for use.
VCC3
9, 26, 52,
91, 135,
141
VSS
Ground level of digital circuit
Note : In most of the above pins, the input/output of the I/O ports and resources are multiplexed, such as xxxx/Pxx.
If the output from ports and resources of those pins compete with each other, the resource is given priority.
16
MB91133/MB91F133
■ INPUT/OUTPUT CIRCUIT TYPES
Type
Circuit
Remarks
• High-speed oscillation circuit
(16.5 MHz)
X1
X0
Xout
Oscillation feedback resistance
= approximately 1 MΩ
A
3 V CMOS level input
Standby control signal
• With pull up resistance
CMOS level input
Pull-up resistance value
= approximately 25 kΩ (Typ.)
B
C
F
Digital input
• CMOS level input/output pin
Pout
Nout
CMOS level output
CMOS level input
(with standby control)
IOL = 4 mA
R
CMOS input
Standby control
• CMOS hysteresis input/output pin
CMOS level output
CMOS hysteresis input
(with standby control)
Pout
Nout
IOL = 4 mA
R
Hysteresis input
Standby control
(Continued)
17
MB91133/MB91F133
Type
Circuit
Remarks
• CMOS level input pin
CMOS level input
(without standby control)
G
IOL = 4 mA
R
Digital input
• CMOS hysteresis input/output pin
with pull- up control
Pull-up control
Pout
R
CMOS level output
CMOS hysteresis input
(without standby control)
Pull-up resistance value
= approximately 50 kΩ (Typ.)
H
Nout
R
Hysteresis input
IOL = 4 mA
• Clock oscillation circuit (32 kHz)
X1A
X0A
Oscillation feedback resistance
= approximately 4.5 MΩ/3 V
3 V CMOS level input
Xout
K
Standby control signal
• Analog/CMOS level input/output pin
CMOS level output
CMOS level input
(with standby control)
Analog input
Pout
Nout
N
(Analog input is valid when bit dealt
by AIC is “1”.)
R
CMOS input
IOL = 4 mA
Standby control
Analog input
(Continued)
18
MB91133/MB91F133
(Continued)
Type
Circuit
Remarks
• CMOS hysteresis input/output pin
with pull-up control
Pull-up control
Pout
R
CMOS level output
CMOS hysteresis input
(with standby control)
Pull-up resistance value
= approximately 50 kΩ (Typ.)
O
Nout
R
Hysteresis input
Standby control
IOL = 4 mA
• CMOS hysteresis input/output pin
with pull-up control
Pull-up control
Open-drain control
CMOS level output
R
(with open-drain control)
CMOS hysteresis input
(with standby control)
Pull-up resistance value
= approximately 50 kΩ (Typ)
P
Nout
R
Hysteresis input
Standby control
IOL = 4 mA
19
MB91133/MB91F133
■ HANDLING DEVICES
1. Points to Note on Handling Devices
(1) Latch-up prevention
Latch-up may occur by CMOS IC if a voltage in excess of VCC5 or lower than VSS is applied to the input/output
pins, or if the voltage exceeds the rating between VCC5 and VSS. If latch-up occurs, the electrical current increases
significantly and may destroy certain components due to excessive heat, so great care must be taken to ensure
that the maximum rating is not exceeded during use.
(2) Handling Pins
• Handling unused pins
Input pins that are not used should be pulled up or down as they may cause erroneous operations if left open.
• Handling N.C. pins
N.C. pins must be opened for use.
• Handling output pins
Excessive electric current may flow if the output pin is shorted by the power source or other output pins, or
connected to large loads. If such status is prolonged, the device is liable to be damaged, so great care must
be taken to ensure that the usage volume does not exceed the maximum rating.
• Mode pins (MD0 to MD2)
Those pins must be directly connected to VCC5 or VSS for use.
Pattern lengths between VCC5 or VSS and each mode pin on the printed-circuit board should be arranged to
be as short as possible to prevent the test mode from being erroneously turned on due to noise, and they
should be connected with low impedance.
• Power pins
When there are a number of VCC5/VCC3/VSS, those whose electrical potential must be the same within the
device are connected to prevent erroneous operation such as latch-up for device design purposes, but those
must be externally connected to a power source and earthed to follow the general output current standard and
prevent erroneous operation of strobe signals due to increased ground level and reduction in unnecessary
radiation.
Care must also be taken to ensure that they are connected to the VCC5/VSS or VCC3/VSS of this device at the
lowest possible impedance from the source of the electrical current supply.
Furthermore, it is recommended that a ceramic capacitor of around 0.1 µF be used to connect the VCC5 and
VSS, or VCC3 and VSS near the device as a bypass capacitor.
• Crystal oscillation circuits
Noise near the X0, X1, X0A or X1A pins can cause erroneous operation. The printed-circuit board must be
designed so that the X0, X1, X0A and X1A pins, crystal oscillator (or ceramic oscillator) and bypass capacitor
to the ground can be arranged as close as possible.
Also, a printed-circuit board with grounded artwork enclosing the X0, X1, X0A and X1A pins is strongly
recommended to ensure stable operation.
20
MB91133/MB91F133
(3) Points to note on usage
• External reset input
“L” level should be input to the RST pin, which is required for at least five machine cycles to ensure that the
internal status is reset.
• Oscillation pin
Oscillation pin is 3 V CMOS input level.
• External clock
Use with an external clock is prohibited. A crystal (or ceramic) oscillator should be used.
• Analog Power
The AVCC should always be used at the same electric potential as VCC5. If the VCC5 is larger than the AVCC,
electricity may flow through pins AN 0 to AN 7.
• Points to note for using level comparator
When the level comparator is used, a reference current (IR) flows even though it is stopped. The stop mode
must be turned on after prohibiting action of the level comparator.
2. Points to Note on Turning On Power
• RST pin handling
The RST pin must be started from “L” level when the power is turned on, and when the power is adjusted to
the VDD level, it should be changed to the “H” level after being left on for at least 5 cycles of the internal operation
clock.
• Original oscillation input
The clock must be input until the waiting status for oscillation stability is reset in the event that power is turned on.
• Power on reset
“Power on reset” must be executed if power is turned on, but the power voltage falls below the guaranteed
operating temperature and power is turned on again.
• Order for turning on power
Power should be turned on in the following order.
VCC3 → VCC5 → AVCC → AVRH
The opposite order should be used when turning off.
21
MB91133/MB91F133
■ BLOCK DIAGRAM
SIN0 to SIN4
SOT0 to SOT4
SCK0 to SCK4
FR30 CPU
15
UART × 5 ch
RAM 6 Kbyte
DREQ0 toDREQ 2
DACK0 toDACK 2
DEOP0 to DEOP2
DMAC 8 ch
Reload timer × 5 ch
9
Resource Bus
Controller
DA0 toDA2
DAVC, DAVS
8 bit 3 output D/A converter
5
PPG0 to PPG5
TRG0 to TRG5
Bus Converter
6
6
A23 to A00
RAM 2 Kbyte
D31 to D16
16 bit PPG × 6 ch
Multi-Function
Timer
RD
WR1, WR0
RDY
BRQ
ROM 254 Kbyte
IN0 to IN3
FRCK
BGRNT
CLK
4
16 bit ICU × 4 ch
47
Interrupt Controller
16 bit FRT
X0, X1, X0A, X1A
RST
Clock Generator
RTO0 (U)
RTO1 (X)
RTO2 (V)
RTO3 (Y)
RTO4 (W)
RTO5 (Z)
RTO6
MD0 to MD2
8
6
AIN0, 1
BIN0, 1
ZIN0, 1
Up/Down counter × 2 ch
24 ch external interrupt
16 bit OCU × 8 ch
RTO7
DTTI
INT0 to INT23 ( )
24
AN0 to AN7
AVRH, AVRL
AVCC, AVSS
Waveform Generator
10 bit 8 input A/D converter
12
CMP (AN7)
level comparator
* : INT23 to INT16 share pins with A23 to A16
* : INT15 shares pins with ATG
* : INT14 shares pins with DEOP2
* : INT13 to INT8 share pins with TRG5 to TRG0
* : INT7 to INT4 share pins with AIN0, BIN0, AIN1 and BIN1
The total number of above pins is 133. The remainder (144 − 133 = 11 pins) are VCC5 , VCC3 and VSS.
22
MB91133/MB91F133
■ CPU
1. Memory Space
The FR series has 4 Gbytes (232 addresses) of logic address space which the CPU accesses linearly.
• Memory Map
External ROM
external bus mode
Internal ROM
external bus mode
Single-chip mode
I/O
0000 0000H
0000 0400H
Direct
Madressing
area
I/O
I/O
I/O
I/O
Refer to "I/O MAP"
I/O
0000 0800H
Access is
prohibited
Access is
prohibited
Access is
prohibited
0000 1000H
0000 2800H
Built-in RAM 6 KB
Built-in RAM 6 KB
Built-in RAM 6 KB
Access is
prohibited
Access is
prohibited
Access is
prohibited
0001 0000H
0001 0000H
000C 0000H
Access is
prohibited
External area
External area
Built-in RAM 2KB
Built-in RAM 2KB
000C 0800H
010 0000H
Built-in ROM
254KB
Built-in ROM
254KB
Access is
prohibited
External area
FFFF FFFFH
FFFF FFFFH
* : It is impossible to access the external area on single-chip mode. When accessing the external area, select the
internal ROM external bus mode.
23
MB91133/MB91F133
2. Registers
There are two types of multi-purpose registers in the FR family. One is a dedicated purpose register that exists
within the CPU and the other is a multi-purpose register that exists in the memory.
• Dedicated Registers
Program Counter (PC)
: 32-bit length; indicates instruction storage position.
Program Status (PS)
: 32-bit length; stores register pointers and condition codes.
Table Base Register (TBR)
: Holds the starting address of the vector table to be used for Exception,
Interruption and Trapping (EIT) .
Return Pointer (RP)
: Holds the address to return to from the sub-routine.
System Stuck Pointer (SSP) : Indicates the system stuck position.
User Stuck Pointer (USP)
Multiplication and Division
: Indicates the user’s stuck position.
Results Resister (MDH/MDL) : 32-bit length; act as registers for multiplication and division.
32 bit
Initial values
Program Counter
XXXX XXXXH (Undecided)
PC
PS
Program Status
TBR
RP
Table Base Register
Return Pointer
000F FC00H
XXXX XXXXH (Undecided)
0000 0000H
SSP
USP
System Stuck Pointer
User Stuck Pointer
XXXX XXXXH (Undecided)
MDH
MDL
XXXX XXXXH (Undecided)
XXXX XXXXH (Undecided)
Multiplication and
Division Results Resister
• Program Status (PS)
PS is the register that holds the program status and is classified into three categories, namely, Condition Code
Register (CCR) , System Condition Code Register (SCR) and Interruption Level Master Register (ILM) .
31 20 19 18 17 16
ILM4 ILM3 ILM2 ILM1 ILM0
10
9
8
T
7
6
5
4
I
3
2
Z
1
0
PS
D1 D0
S
N
V
C
ILM
SCR
CCR
24
MB91133/MB91F133
• Condition Code Register (CCR)
S flag : Specifies the stuck pointer to be used as R15.
I flag : Controls permission and prohibition of user interruption requests.
N flag : Indicates codes when computation results are defined as integers that are expressed in comple-
ments of 2.
Z flag : Indicates whether or not a result of the computation is “0” .
V flag : Operands used for computation are defined as integers expressed in complements of 2, and indi-
cate whether or not an overflow is generated as a result of the computation.
C flag : Indicates whether carrying or borrowing is generated from the highest bit as a result of the compu-
tation.
• System Condition Code Register (SCR)
T flag : Specifies whether or not the step trace trap will be valid.
• Interruption Level Mask Register (ILM)
ILM4 to ILM0 : Holds the interruption level mask values, and those values that are held by the ILM are used
for the level mask. Interruption requests can be accepted only when the interruption levels
handled within the interruption requests to be input into the CPU are stronger than the levels
shown by the ILM.
ILM4
ILM3
ILM2
ILM1
ILM0
Interruption level Strength
0
0
0
0
0
0
Strong
0
1
1
1
0
1
0
1
0
1
15
31
Weak
25
MB91133/MB91F133
■ MULTI-PURPOSE REGISTERS
The multi-purpose registers are CPU registers R0 to R15 which are used as accumulators for various compu-
tations and memory access pointers (fields that indicate the address) .
• Register bank configuration
32-bit
Initial value
R0
R1
XXXX XXXXH
R12
R13
R14
R15
AC (Accumulator)
FP (Frame Pointer)
SP (Stack Pointer)
XXXX XXXXH
0000 0000H
Special purposes are assumed for the following 3 of the 16 registers. Thus, some instructions are emphasized.
R13 : Virtual accumulator (AC)
R14 : Frame Pointer (FP)
R15 : Stack Pointer (SP)
Initial values for R0 to R14 on resetting are unspecified. The initial value of R15 will be 0000 0000H (SSP value) .
26
MB91133/MB91F133
■ MODE SETTING
1. Pins
• Mode pins and set mode
Mode pins
Reset vector
access areas
External data
Bus modes
bus width
Mode name
MD2 MD1 MD0
0
0
0
0
1
0
0
1
1
0
1
0
1
External vector mode 0
External vector mode 1
External
External
8-bit
External ROM external
bus mode
16-bit
Setting is prohibited
Internal vector mode
Internal
(Mode register) Single chip mode
Usage is prohibited
2. Register
Mode register (MODR) and set mode
Address
Initial value Access
0000 07FFH
XXXX XXXXB
W
M1
M0
*
*
*
*
*
*
Bus mode set bit
W : Write only
X : Undecided
*
: “0” should always be written for bits other than M1 and M0.
• Bus mode set bit and its functions
M1
0
M0
0
Functions
Remarks
Single chip mode
0
1
Internal ROM external bus mode
External ROM external bus mode
1
0
1
1
Setting is prohibited
27
MB91133/MB91F133
■ I/O MAP
Register
Address
Block
+0
+1
+2
+3
PDR3
(R/W)
PDR2
XXXXXXXX
PDR6 (R/W)
XXXXXXXX
(R/W)
000000H
000004H
000008H
00000CH
000010H
000014H
000018H
00001CH
000020H
000024H
000028H
00002CH
000030H
000034H
000038H
00003CH
000040H
XXXXXXXX
PDR5
(R/W)
PDR4
XXXXXXXX
PDR8 (R/W)
-XXXXXXX
(R/W)
XXXXXXXX
Port Data
Register
PDRF
XXXXXXXX
PDRJ (R/W)
-- XXXXXX
LVLC (R/W)
XXXX0 0 0 0
SSR0 (R/W)
0 0 0 0 1 - 0 0
SSR1
0 0 0 0 1 - 0 0
(R/W)
PDRE
XXXXXXXX
PDRI (R/W)
(R/W)
PDRD
XXXXXXXX
PDRH (R/W)
- -- -- XXX
PDRL (R/W)
XXXXXXXX
SCR0 (R/W)
0 0 0 0 0 1 0 0
(R/W)
PDRC
XXXXXXXX
PDRG (R/W)
-- XXXXXX
PDRK (R/W)
XXXXXXXX
SMR0 (R/W)
0 0 0 0 0- 0 0
(R/W)
- -XXXXXX
Level Comparator
UART0
SIDR0/SODR0 (R/W)
XXXXXXXX
(R/W) SIDR1/SODR1 (R/W) SCR1
(R/W)
SMR1
(R/W)
UART1
XXXXXXXX
SIDR2/SODR2 (R/W)
XXXXXXXX
(W)
0 0 0 0 0 1 0 0
0 0 0 0 0- 0 0
SSR2
(R/W)
SCR2
(R/W)
SMR2
(R/W)
UART2
0 0 0 0 1 - 0 0
TMRLR
0 0 0 0 0 1 0 0
TMR
0 0 0 0 0- 0 0
(R)
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
Reload Timer 0
Reload Timer 1
TMCSR
(R/W)
-- -- 00 0 0 0 0 0 0 0 0 0 0
TMR (R)
XXXXXXXX XXXXXXXX
TMCSR (R/W)
-- -- 00 0 0 0 0 0 0 0 0 0 0
ADCS1 (R/W) ADCS0 (R/W)
TMRLR
(W)
XXXXXXXX XXXXXXXX
ADCR
0 0 1 0 1 -XX XXXXXXXX
TMRLR (W)
XXXXXXXX XXXXXXXX
(R/W)
A/D Converter
(Sequential type)
0 0 0 0 0 0 0 0
TMR
0 0 0 0 0 0 0 0
(R)
XXXXXXXX XXXXXXXX
Reload Timer 2
(Continued)
TMCSR
(R/W)
-- -- 00 0 0 0 0 0 0 0 0 0 0
28
MB91133/MB91F133
Register
Address
000044H
000048H
00004CH
000050H
000054H
000058H
00005CH
000060H
000064H
000068H
00006CH
000070H
000074H
000078H
00007CH
000080H
Block
+0
+1
+2
+3
IPCP1
(R)
IPCP0
(R)
XXXXXXXX XXXXXXXX
IPCP3 (R)
XXXXXXXX XXXXXXXX
IPCP2 (R)
XXXXXXXX XXXXXXXX
16-bit ICU
Reserved
XXXXXXXX XXXXXXXX
ICS23
(R/W)
ICS01
(R/W)
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
OCCP1
XXXXXXXX XXXXXXXX
OCCP3 (R/W)
XXXXXXXX XXXXXXXX
OCCP5 (R/W)
XXXXXXXX XXXXXXXX
OCCP7 (R/W)
XXXXXXXX XXXXXXXX
OCS32 (R/W)
XXX 0 0 0 0 0 0 0 0 0 XX 0 0
OCS76 (R/W)
XXX 0 0 0 0 0 0 0 0 0 XX 0 0
TCDT (R/W)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIDR3/SODR3 (R/W)
(R/W)
OCCP0
(R/W)
XXXXXXXX XXXXXXXX
OCCP2 (R/W)
XXXXXXXX XXXXXXXX
OCCP4 (R/W)
XXXXXXXX XXXXXXXX
OCCP6 (R/W)
XXXXXXXX XXXXXXXX
OCS10 (R/W)
XXX 0 0 0 0 0 0 0 0 0 XX 0 0
OCS54 (R/W)
XXX 0 0 0 0 0 0 0 0 0 XX 0 0
TCCS (R/W)
0- -- -- -- 0 0 0 0 0 0 0 0
(R/W) SMR3 (R/W)
0 0 0 0 0 1 0 0 0 0 0 0 0- 0 0
SCR4 (R/W)
0 0 0 0 0 1 0 0
16-bit OCU
16-bit
Free-run Timer
SSR3
0 0 0 0 1 0 00
SSR4 (R/W)
0 0 0 0 1 0 00
(R/W)
SCR3
UART3
UART4
XXXXXXXX
SIDR4/SODR4 (R/W)
XXXXXXXX
SMR4
(R/W)
0 0 0 0 0- 0 0
CDCR1
(R/W)
CDCR0
(R/W)
0 -- -0 0 0 0
0 - -- 0 0 0 0
CDCR3
(R/W)
CDCR2
CDCR4
(R/W)
Communication
Pre-scalar
0 -- -0 0 0 0
0 - -- 0 0 0 0
(R/W)
0 - -- 0 0 0 0
(Continued)
29
MB91133/MB91F133
Register
Address
Block
+0
+1
+2
UDCR1
0 0 0 0 0 0 0 0
+3
UDCR0
0 0 0 0 0 0 0 0
CSR0 (R/W)
0 0 0 0 0 0 0 0
CSR1 (R/W)
0 0 0 0 0 0 0 0
RCR1
(W)
RCR0
(W)
(R)
(R)
000084H
000088H
00008CH
000090H
000094H
000098H
00009CH
0000A0H
0000A4H
0000A8H
0000ACH
0000B0H
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
(R/W) CCRL0 (R/W)
CCRH0
8-/16-bit
U/D Counter
0 0 0 0 0 0 0 0
CCRH1
-0 0 0 1 0 0 0
(R/W) CCRL1
(R/W)
- 0 0 0 0 0 0 0
-0 0 0 1 0 0 0
Reserved
EIRR0
(R/W) ENIR0
(R/W) EIRR1
(R/W) ENIR1
(R/W)
0 0 0 0 0 0 0 0
(R/W)
0 0 0 0 0 0 0 0
ELVR0
0 0 0 0 0 0 0 0
(R/W)
0 0 0 0 0 0 0 0
ELVR1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EIRR2 (R/W) ENIR2 (R/W)
0 0 0 0 0 0 0 0
ELVR2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Ext Int
0 0 0 0 0 0 0 0
(R/W)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DACR2
(R/W) DACR1
(R/W) DACR0
- -- -- -- 0 - -- -- -- 0
(R/W) DADR0
XXXXXXXX
(R/W)
-- -- -- -0
D/A Converter
DADR2
XXXXXXXX
(R/W) TMRR1 (R/W) DTCR0
0 0 0 0 0 0 0 0 XXXXXXXX
SIGCR (R/W) DTCR2
0 0 0 0 0 0 0 0
(R/W) DADR1
(R/W)
(R/W)
XXXXXXXX
DTCR1
(R/W) TMRR0
0 0 0 0 0 0 0 0
XXXXXXXX
Waveform
Generator
(R/W) TMRR2
(R/W)
0 0 0 0 0 0 0 0
XXXXXXXX
0000B4H
to
Reserved
0000BCH
PCRE
(R/W)
(R/W)
PCRD
(R/W)
PCRC
(R/W)
0000C0H
0000C4H
0000C8H
0000CCH
- -- -- -0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Pull-up Control
PCRJ
- -0 0 0 0 0 0
OCRJ (R/W)
- -0 0 0 0 0 0
(R/W)
PCRI
PCRH
(R/W)
(R/W)
- -0 0 0 0 0 0
OCRI (R/W) OCRH
- -0 0 0 0 0 0
-- -- -0 0 0
Open-drain Control
-- -- -0 0 0
AICK
(R/W)
Analog
Input Control
0 0 0 0 0 0 0 0
(Continued)
30
MB91133/MB91F133
Register
Address
0000D0H
0000D4H
0000D8H
0000DCH
0000E0H
0000E4H
0000E8H
0000ECH
0000F0H
0000F4H
0000F8H
0000FCH
000100H
000104H
000108H
00010CH
Block
+0
+1
+2
+3
DDRF
0 0 0 0 0 0 0 0
DDRJ (R/W)
- -0 0 0 0 0 0
(R/W)
DDRE
0 0 0 0 0 0 0 0
DDRI (R/W)
(R/W)
DDRD
0 0 0 0 0 0 0 0
DDRH
-- -- -0 0 0
DDRL (R/W)
(R/W)
DDRC
(R/W)
0 0 0 0 0 0 0 0
(R/W)
(R/W) DDRG
Data Direction
Register
- -0 0 0 0 0 0
-- 0 0 0 0 0 0
DDRK
0 0 0 0 0 0 0 0
GCN2 (R/W)
(R/W)
0 0 0 0 0 0 0 0
PCSR0
GCN1
(R/W)
PPG ctl
PPG0
0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0
PTMR0 (R)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PDUT0 (W)
XXXXXXXX XXXXXXXX
PTMR1 (R)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PDUT1 (W)
XXXXXXXX XXXXXXXX
PTMR2 (R)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PDUT2 (W)
XXXXXXXX XXXXXXXX
PTMR3 (R)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PDUT3 (W)
XXXXXXXX XXXXXXXX
PTMR4 (R)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PDUT4 (W)
XXXXXXXX XXXXXXXX
PTMR5 (R)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PDUT5 (W)
XXXXXXXX XXXXXXXX
0 0 0 0 0 0 0 0
(W)
XXXXXXXX XXXXXXXX
PCNH0
(R/W) PCNL0
(R/W)
0 0 0 0 0 0 0 0
(W)
0 0 0 0 0 0 0 -
PCSR1
XXXXXXXX XXXXXXXX
PPG1
PPG2
PPG3
PPG4
PPG5
PCNH1
(R/W) PCNL1
(R/W)
0 0 0 0 0 0 0 0
(W)
0 0 0 0 0 0 0 -
PCSR2
XXXXXXXX XXXXXXXX
PCNH2
(R/W) PCNL2
(R/W)
0 0 0 0 0 0 0 0
(W)
0 0 0 0 0 0 0 -
PCSR3
XXXXXXXX XXXXXXXX
PCNH3
(R/W) PCNL3
(R/W)
0 0 0 0 0 0 0 0
(W)
0 0 0 0 0 0 0 -
PCSR4
XXXXXXXX XXXXXXXX
PCNH4
(R/W) PCNL4
(R/W)
0 0 0 0 0 0 0 0
(W)
0 0 0 0 0 0 0 -
PCSR5
XXXXXXXX XXXXXXXX
PCNH5
(R/W) PCNL5
(R/W)
0 0 0 0 0 0 0 -
0 0 0 0 0 0 0 0
(Continued)
31
MB91133/MB91F133
Register
Address
Block
+0
+1
+2
+3
TMRLR
(W)
TMR
(R)
000110H
000114H
000118H
00011CH
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMCSR (R/W)
- -- -0 0 0 0 0 0 0 0 0 0 0 0
TMR (R)
XXXXXXXX XXXXXXXX
TMCSR (R/W)
- -- -0 0 0 0 0 0 0 0 0 0 0 0
Reload Timer 3
TMRLR
(W)
XXXXXXXX XXXXXXXX
Reload Timer 4
Reserved
000120H
to
0001FCH
DPDP
(R/W)
000200H
000204H
000208H
00020CH
-- -- -- -- - - -- -- -- - -- -- -- - -0 0 0 0 0 0 0
DACSR (R/W)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMAC
DATCR
(R/W)
XXXXXXXX XXXX0 0 0 0 XXXX0 0 0 0 XXXX0 0 0 0
000210H
to
Reserved
0003ECH
BSD0
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSD1 (R/W)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSDC (W)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSRR (R)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(W)
0003F0H
0003E4H
0003F8H
0003FCH
000400H
000404H
000408H
Bit Search Module
ICR00
(R/W)
ICR01
(R/W)
ICR02
(R/W)
ICR03
(R/W)
(R/W)
- - -- 1 1 1 1
-- -- 1 1 1 1
-- - -1 1 1 1
- -- -1 1 1 1
ICR04
(R/W)
ICR05
(R/W)
ICR06
(R/W)
ICR07
Interrupt Control
Unit
- - -- 1 1 1 1
-- -- 1 1 1 1
-- - -1 1 1 1
- -- -1 1 1 1
ICR08
(R/W)
ICR09
(R/W)
ICR10
(R/W)
ICR11
(R/W)
- - -- 1 1 1 1
-- -- 1 1 1 1
-- - -1 1 1 1
- -- -1 1 1 1
(Continued)
32
MB91133/MB91F133
Register
Address
00040CH
000410H
000414H
000418H
00041CH
000420H
000424H
000428H
00042CH
000430H
Block
+0
+1
+2
+3
ICR12
- - -- 1 1 1 1
ICR16 (R/W)
- - -- 1 1 1 1
ICR20 (R/W)
- - -- 1 1 1 1
ICR24 (R/W)
- - -- 1 1 1 1
ICR28 (R/W)
- - -- 1 1 1 1
ICR32 (R/W)
- - -- 1 1 1 1
ICR36 (R/W)
- - -- 1 1 1 1
ICR40 (R/W)
- - -- 1 1 1 1
ICR44 (R/W)
- - -- 1 1 1 1
DICR (R/W)
(R/W)
ICR13
-- -- 1 1 1 1
ICR17 (R/W)
-- -- 1 1 1 1
ICR21 (R/W)
-- -- 1 1 1 1
ICR25 (R/W)
-- -- 1 1 1 1
ICR29 (R/W)
-- -- 1 1 1 1
ICR33 (R/W)
-- -- 1 1 1 1
ICR37 (R/W)
-- -- 1 1 1 1
ICR41 (R/W)
-- -- 1 1 1 1
ICR45 (R/W)
-- -- 1 1 1 1
HRCL (R/W)
- -- 1 1 1 1 1
(R/W)
ICR14
-- - -1 1 1 1
ICR18 (R/W)
-- - -1 1 1 1
ICR22 (R/W)
-- - -1 1 1 1
ICR26 (R/W)
-- - -1 1 1 1
ICR30 (R/W)
-- - -1 1 1 1
ICR34 (R/W)
-- - -1 1 1 1
ICR38 (R/W)
-- - -1 1 1 1
ICR42 (R/W)
-- - -1 1 1 1
ICR46 (R/W)
-- - -1 1 1 1
(R/W)
ICR15
(R/W)
(R/W)
- -- -1 1 1 1
ICR19
- -- -1 1 1 1
ICR23
(R/W)
(R/W)
- -- -1 1 1 1
ICR27
- -- -1 1 1 1
ICR31
(R/W)
Interrupt Control
Unit
- -- -1 1 1 1
ICR35
(R/W)
- -- -1 1 1 1
ICR39
(R/W)
- -- -1 1 1 1
ICR43
(R/W)
- -- -1 1 1 1
ICR47
(R/W)
- -- -1 1 1 1
Delay Int
Reserved
- - -- -- -0
000434H
to
00047CH
RSRR/WTCR(R/W)
1 XXXX- 0 0
STCR
0 0 0 1 1 1 - -
WPR (W)
XXXXXXXX
(R/W)
PDRR
(R/W)
CTBR
(W)
000480H
000484H
000488H
-- - -0 0 0 0
XXXXXXXX
Clock Control Unit
PLL Control
GCR
(R/W)
1 1 0 0 1 1 - 1
CT
(R/W)
0 0 -- 0- 0 0
00048CH
to
Reserved
0005FCH
(Continued)
33
MB91133/MB91F133
Register
Address
Block
+0
+1
+2
+3
DDR3
(W)
DDR2
0 0 0 0 0 0 0 0
DDR6 (W)
0 0 0 0 0 0 0 0
(W)
000600H
000604H
000608H
00060CH
000610H
000614H
000618H
00061CH
000620H
000624H
000628H
00062CH
000630H
0 0 0 0 0 0 0 0
DDR5
(W)
DDR4
0 0 0 0 0 0 0 0
DDR8 (W)
(W)
Data Direction
Register
0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0
(W)
ASR1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ASR2 (W)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
ASR3 (W)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
ASR4 (W)
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
ASR5 (W)
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
(W)
AMR1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AMR2 (W)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AMR3 (W)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AMR4 (W)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AMR5 (W)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(R/W) AMD32 (R/W) AMD4 (R/W)
0 - -0 0 0 0 0
T-unit
AMD0
(R/W)
AMD1
0 -- 0 0 0 0 0
-- -0 0 1 1 1
0 0 0 0 0 0 0 0
AMD5
(R/W)
0- -0 0 0 0 0
EPCR0
-- -- 1 1 0 0 -1 -- -- --
(W)
EPCR1
(W)
- - -- -- -- 1 1 1 1 1 1 1 1
PCR6
(R/W)
Pull-up Control
Reserved
0 0 0 0 0 0 0 0
000634H
to
0007BCH
FLCR
0 0 0 X 0 0 0 0
FWTC (R/W)
- -- -- 0 0 0
(R/W)
0007C0H
0007C4H
FLASH Control
Reserved
0007C8H
to
0007F8H
(Continued)
34
MB91133/MB91F133
(Continued)
Register
Address
Block
+0
+1
+2
+3
LER
(W)
MODR
(W)
Little Endian
Register
Mode Register
0007FCH
-- -- -0 0 0
XXXXXXXX
*1 : Do not execute RMW instructions to registers with write-only bits.
*2 : Do not execute write access to read-only or reserved registers except for particular requests.
*3 : Data in areas with “-” or reserved ones are unspecified.
*4 : RMW instructions (RMW : Read / Modify / Write)
AND
Rj, @Ri
OR
Rj, @Ri
EOR
Rj, @Ri
ANDH Rj, @Ri
ANDB Rj, @Ri
BANDL #u4, @Ri
BANDH #u4, @Ri
ORH Rj, @Ri
ORB Rj, @Ri
BORL #u4, @Ri
BORH #u4, @Ri
EORH Rj, @Ri
EORB Rj, @Ri
BEORL #u4, @Ri
BEORH #u4, @Ri
35
MB91133/MB91F133
■ INTERRUPTION VECTOR
Causes of MB91130 interruptions and allocation of interruption vectors and interruption control registers are
described in the interruption vector table.
Interruption number
Address *2
of TBR default
Interruption
Interruption sauce
Offset
*1
level
Decimal Hexadecimal
Reset
0
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
3C0H
3BCH
3B8H
3B4H
3B0H
3ACH
3A8H
3A4H
3A0H
39CH
398H
394H
390H
38CH
388H
384H
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
000FFFE4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
000FFFC0H
000FFFBCH
000FFFB8H
000FFFB4H
000FFFB0H
000FFFACH
000FFFA8H
000FFFA4H
000FFFA0H
000FFF9CH
000FFF98H
000FFF94H
000FFF90H
000FFF8CH
000FFF88H
System reservation
1
System reservation
2
System reservation
3
System reservation
4
System reservation
5
System reservation
6
System reservation
7
System reservation
8
System reservation
9
System reservation
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
System reservation
System reservation
System reservation
Exceptions to undefined instructions
System reservation
External interruption 0
External interruption 1
External interruption 2
External interruption 3
External interruption 4
External interruption 5
External interruption 6
External interruption 7
External interruption 8 to 15
External interruption 16 to 23
UART0 (Reception completion)
UART1 (Reception completion)
UART2 (Reception completion)
UART3 (Reception completion)
UART4 (Reception completion)
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
000FFF84H
(Continued)
36
MB91133/MB91F133
Interruption number
Address *2
of TBR default
Interruption
Interruption sauce
Offset
*1
level
Decimal Hexadecimal
UART0 (Transmission completion)
UART1 (Transmission completion)
UART2 (Transmission completion)
UART3 (Transmission completion)
UART4 (Transmission completion)
DMAC (end, error)
Reload timer 0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
ICR15
ICR16
ICR17
ICR18
ICR19
ICR20
ICR21
ICR22
ICR23
ICR24
ICR25
ICR26
ICR27
ICR28
ICR29
ICR30
ICR31
ICR32
380H
37CH
378H
374H
370H
36CH
368H
364H
360H
35CH
358H
354H
350H
34CH
348H
344H
340H
33CH
000FFF80H
000FFF7CH
000FFF78H
000FFF74H
000FFF70H
000FFF6CH
000FFF68H
000FFF64H
000FFF60H
000FFF5CH
000FFF58H
000FFF54H
000FFF50H
000FFF4CH
000FFF48H
000FFF44H
000FFF40H
000FFF3CH
Reload timer 1
Reload timer 2
Reload timer 3
Reload timer 4
A/D (sequential type)
PPG0
PPG1
PPG2
PPG3
PPG4/5
Waveform generator
U/D counter 0 (compare/
underflow-overflow, up/down invert)
49
50
31
32
ICR33
ICR34
338H
334H
000FFF38H
000FFF34H
U/D counter 1 (compare/
underflow-overflow, up/down invert)
ICU0 (load)
51
52
53
54
55
56
57
58
59
60
61
62
63
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
ICR35
ICR36
ICR37
ICR38
ICR39
ICR40
ICR41
ICR42
ICR43
ICR44
ICR45
ICR46
ICR47
330H
32CH
328H
324H
320H
31CH
318H
314H
310H
30CH
308H
304H
300H
000FFF30H
000FFF2CH
000FFF28H
000FFF24H
000FFF20H
000FFF1CH
000FFF18H
000FFF14
000FFF10H
000FFF0CH
000FFF08H
000FFF04H
ICU1 (load)
ICU2 (load)
ICU3 (load)
OCU0 (matched)
OCU1 (matched)
OCU2 (matched)
OCU3 (matched)
OCU4/5 (matched)
OCU6/7 (matched)
Level comparator
16-bit freerun timer
Delay interruption factor bit
000FFF00H
(Continued)
37
MB91133/MB91F133
(Continued)
Interruption number
Decimal Hexadecimal
Address *2
of TBR default
Interruption
Interruption sauce
Offset
*1
level
System reservation
64
65
40
41
2FCH
2F8H
000FFEFCH
000FFEF8H
(used under REALOS *3)
System reservation
(used under REALOS *3)
Used under INT instruction
Used under INT instruction
Used under INT instruction
Used under INT instruction
Used under INT instruction
Used under INT instruction
Used under INT instruction
Used under INT instruction
Used under INT instruction
Used under INT instruction
Used under INT instruction
Used under INT instruction
Used under INT instruction
Used under INT instruction
66
67
68
69
70
71
72
73
74
75
76
77
78
79
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
2F4H
2F0H
2ECH
2E8H
2E4H
2E0H
2DCH
2D8H
2D4H
2D0H
2CCH
2C8H
2C4H
2C0H
000FFEF4H
000FFEF0H
000FFEECH
000FFEE8H
000FFEE4H
000FFEE0H
000FFEDCH
000FFED8H
000FFED4H
000FFED0H
000FFECCH
000FFEC8H
000FFEC4H
000FFEC0H
80
to
50
to
2BCH
to
000FFEBCH
to
Used under INT instruction
255
FF
000H
000FFC00H
*1 :ICRsetstheinterruptionlevelforeachinterruptionrequestusingtheregisterbuiltintotheinterruptioncontroller.
ICR is prepared in accordance with each interruption request.
*2 : TBR is the register that indicates the starting address of the vector table for EIT.
Addresses with added offset values that are specified per TBR and EIT factor will be the vector addresses.
*3 : 0X40, 0X41 interruptions for system codes are used in the event that REALOS/FR is used.
38
MB91133/MB91F133
■ PERIPHERAL RESOURCES
1. Bus Interface
The bus interface controls the interface with external memory and external I/O.
• Bus Interface Characteristics
• 24-bit (16 MB) address output
• 16/8-bit bus width can be set.
• Insertion of programmable “automatic memory wait” (maximum of 7 cycles)
• Supports “little endian” mode
• Unused addresses / data pins can be used as I/O ports.
• Clock doubled should be used if the external bus exceeds 25 MHz. Bus speed is 1/2 of the CPU speed.
• Areas
A total of six types of chip selection areas are prepared for the bus interface. The position of each area can be
randomly arranged per 64 KB at least using area selection registers (ASR1 to ASR 5) and area mask registers
(AMR1 to AMR 5) in an area of 4 GB. The area 0 is allocated to space outside the area specified by ASR1 to
ASR5. External areas other than 00010000H to 0005FFFFH are deemed area 0 on resetting.
There is no chip selection output pin so no setting is required. Setting it has no effect on usage.
Figure 4.1-1 shows an example in which areas 1 to 5 are arranged from 00100000H to 0014FFFFH in 64 KB
units. Also, Figure 4.1-2 shows an example in which area 1 is arranged as 00000000H to 0007FFFFH in 512 KB
and areas 2 to 5 are arranged as 00100000H to 004FFFFFH in 1-MB units.
00000000H
00080000H
00000000H
CS1 (512 K)
CS0 (512 K)
00080000H
000FFFFFH
CS0 (1 Mbyte)
CS2 (1 Mbyte)
CS3 (1 Mbyte)
CS4 (1 Mbyte)
000FFFFFH
0010FFFFH
0011FFFFH
0012FFFFH
001FFFFFH
CS1 (64 Kbyte)
CS2 (64 Kbyte)
CS3 (64 Kbyte)
CS4 (64 Kbyte)
CS5 (64 Kbyte)
002FFFFFH
003FFFFFH
004FFFFFH
0013FFFFH
0014FFFFH
CS5 (1 Mbyte)
CS0
CS0
Figure 4.1-1
Area Arrangement Example 1
Figure 4.1-2
Area Arrangement Example 2
39
MB91133/MB91F133
• Block Diagram
A - Out
M
U
X
External
DATA Bus
write
buffer
switch
switch
read
buffer
DATA BLOCK
ADDRESS BLOCK
+1 or +2
address
buffer
External
Address Bus
shifter
inpage
CS0 - CS5
compa-
rator
ASR
AMR
RD
WR0. WR1
External pin control area
Controls all blocks
registers
&
Control
BRQ
BGRNT
RDY
40
MB91133/MB91F133
• Register List
15
8
7
0
Address
0000060CH
0000060EH
00000610H
00000612H
00000614H
00000616H
00000618H
0000061AH
0000061CH
0000061EH
00000620H
00000622H
00000624H
00000626H
ASR1
AMR1
ASR2
AMR2
ASR3
Area Select Register 1
Area Mask Register 1
Area Select Register 2
Area Mask Register 2
Area Select Register 3
AMR3
ASR4
AMR4
ASR5
AMR5
Area Mask Register 3
Area Select Register 4
Area Mask Register 4
Area Select Register 5
Area Mask Register 5
AMD0
AMD32
AMD5
AMD1
AMD4
Area Mode Register 0 / Area Mode Register 1
Area Mode Register 32 / Area Mode Register 4
Area Mode Register 5
ReFresh Control Register
RFCR
DMCR4
DMCR5
DRAM Control Register 4
DRAM Control Register 4
0000062CH
0000062EH
00000688H
000007FEH
EPCR0
LER
EPCR1
MODR
External Pin Control Register
Little Endian Register / MODe Register
Note : Functional pins have not been prepared in the shaded area for MB91133/MB91F133, so these
registers should not be accessed.
41
MB91133/MB91F133
2. I/O Port
MB91133/MB91F133 can be used as an I/O port when the setting for resources dealing with each pin does not
use the pin for input/output.
As regards the read value of the port (PDR) , the pin level is read out when input is set for the port. If output is
set, the data register value is read out. This is the same for reading under Read Modify Write.
If the input setting is changed to output setting, output data should be set first. If Read Modify Write instructions
(i.e. bit set) are used in this case, the data that is read out is the input data from the pin and is not the latch value
of the data register, so care must be taken.
• Basic I/O Port Block Diagram
Data bus
Resource input
0
1
PDR read
pin
0
PDR
Resource output
1
Resource output
permission
DDR
PDR : Port Data Register
DDR : Data Direction Register
• I/O Port Register
The I/O port consists of the Port Data Register (PDR) and Port Direction Register (DDR) .
• In case of input mode (DDR = “0”)
When PDR reads : Level of external pins handled is read out.
When PDR writes : Set value is written in PDR.
• In case of output mode (DDR = “1”)
When PDR reads : PDR values are read out.
When PDR writes : PDR values are output to the external pin handled.
• Switching control for resources and ports of the analog pin (A/D)
• Resources and ports of the analog pin (A/D) are switched using the Analog Input Control register on Port K
(AICK) .
This controls whether Port K is used as an analog or general-purpose port.
0 : General-purpose port
1 : Analog input (A/D)
42
MB91133/MB91F133
• Block Diagram of Input/Output Port (with Pull-up Resistance)
Data bus
Resource input
0
Pull up resistance
(approximately
50 kΩ)
1
PDR read
pin
0
PDR
Resource output
1
Resource output
permission
DDR
PCR
PDR : Port Data Register
DDR : Data Direction Register
PCR : Pull-up Control Register
• Pull-up resistance control register (PCR) R/W
Turns pull-up resistance ON/OFF.
0 : Pull-up resistance turned off
1 : Pull-up resistance turned on
Notes : • The pull-up resistance control register setting is handled as a priority in stop mode (HIZ = 1) as well.
• Use of the pull-up resistance control function is prohibited when the pin concerned is used as the external
bus pin. “1” should not be written in this register.
43
MB91133/MB91F133
• Block Diagram of Input / Output Port (Open-drain Output Function with Pull-up Resistance)
Data bus
Resource input
0
1
PDR read
pin
0
1
PDR
Resource output
Resource output
permission
DDR
ODCR
PCR
PDR : Port Data Register
DDR : Data Direction Register
ODCR : OpenDrain Control Register
PCR : Pull-up Control Register
• Pull-up resistance control register (PCR) R/W
Controls pull up resistance ON/OFF.
0 : Without pull-up resistance
1 : With pull-up resistance
• Open-drain control register (ODCR) R/W
Controls open-drain in output mode.
0 : Standard output port in output mode
1 : Open-drain output port in output mode
Notes : • This has no meaning in input mode (output Hi-Z) . Input/output mode is decided by the Direction Register
(DDR) .
• Pull-up resistance control register setting is handled as the priority in stop mode (HIZ = 1) as well.
• Use of both the pull-up resistance control function and open-drain control function are prohibited when the
pin concerned is used as an external bus pin. “1” should not be written in both registers.
44
MB91133/MB91F133
• Port Data Register (PDR)
PDR2
Initial value Access
7
6
5
4
3
2
1
0
Address : 000001H
XXXXXXXXB R/W
P27
P26
P25
P24
P23
P22
P21
P20
PDR3
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 000000H
P37
P36
P35
P34
P33
P32
P31
P30
PDR4
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 000007H
P47
P46
P45
P44
P43
P42
P41
P40
PDR5
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 000006H
P57
P56
P55
P54
P53
P52
P51
P50
PDR6
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 000005H
P67
P66
P65
P64
P63
P62
P61
P60
PDR8
Initial value Access
- XXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 00000BH
P86
P85
P84
P83
P82
P81
P80
PDRC
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 000013H
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PDRD
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 000012H
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PDRE
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 000011H
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PDRF
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 000010H
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PDRG
Initial value Access
- - XXXXXXB R/W
7
7
7
7
6
6
6
6
5
4
3
2
1
0
Address : 000017H
PG5
PG4
PG3
PG2
PG1
PG0
PDRH
Initial value Access
- - - - - XXXB R/W
5
4
3
2
1
0
Address : 000016H
PH2
PH1
PH0
PDRI
Initial value Access
- - XXXXXXB R/W
5
4
3
2
1
0
Address : 000015H
PI5
PI4
PI3
PI2
PI1
PI0
PDRJ
Initial value Access
- - XXXXXXB R/W
5
4
3
2
1
0
Address : 000014H
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
PDRK
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 00001BH
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
PDRL
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 00001AH
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
PDR2 to L are input/output data registers of the I/O port.
Input/output control is carried out by DDR2 to L that are handled.
45
MB91133/MB91F133
• Data Direction Register (DDR)
DDR2
Initial value Access
00000000B
Initial value Access
00000000B
Initial value Access
00000000B
Initial value Access
00000000B
Initial value Access
00000000B
Initial value Access
- 0000000B
7
6
5
4
3
2
1
0
Address : 000601H
W
P27
P26
P25
P24
P23
P22
P21
P20
DDR3
7
6
5
4
3
2
1
0
Address : 000600H
W
P37
P36
P35
P34
P33
P32
P31
P30
DDR4
7
6
5
4
3
2
1
0
Address : 000607H
W
P47
P46
P45
P44
P43
P42
P41
P40
DDR5
7
6
5
4
3
2
1
0
Address : 000606H
W
P57
P56
P55
P54
P53
P52
P51
P50
DDR6
7
6
5
4
3
2
1
0
Address : 000605H
W
P67
P66
P65
P64
P63
P62
P61
P60
DDR8
7
6
5
4
3
2
1
0
Address : 00060BH
W
P86
P85
P84
P83
P82
P81
P80
DDRC
Initial value Access
00000000B R/W
7
6
5
4
3
2
1
0
Address : 0000D3H
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
DDRD
Initial value Access
00000000B R/W
7
6
5
4
3
2
1
0
Address : 0000D2H
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
DDRE
Initial value Access
00000000B R/W
7
6
5
4
3
2
1
0
Address : 0000D1H
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
DDRF
Initial value Access
00000000B R/W
7
6
5
4
3
2
1
0
Address : 0000D0H
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
DDRG
Initial value Access
- - 000000B R/W
7
7
7
7
6
6
6
6
5
4
3
2
1
0
Address : 0000D7H
PG5
PG4
PG3
PG2
PG1
PG0
DDRH
Initial value Access
- - - - - 000B R/W
5
4
3
2
1
0
Address : 0000D6H
PH2
PH1
PH0
DDRI
Initial value Access
- - 000000B R/W
5
4
3
2
1
0
Address : 0000D5H
PI5
PI4
PI3
PI2
PI1
PI0
DDRJ
Initial value Access
- - 000000B R/W
5
4
3
2
1
0
Address : 0000D4H
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
DDRK
Initial value Access
00000000B R/W
7
6
5
4
3
2
1
0
Address : 0000DBH
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
DDRL
Initial value Access
00000000B R/W
7
6
5
4
3
2
1
0
Address : 0000DAH
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
DDR0 to L control input/output direction of the I/O ports handled per bit.
DDR = 0 : Port input DDR = 1 : Port output “0” must be written into the empty bit.
46
MB91133/MB91F133
• Pull up Control Register (PCR)
PCR6
Initial value Access
7
6
5
4
3
2
1
0
Address : 000631H
00000000B R/W
P67
P66
P65
P64
P63
P62
P61
P60
PCRC
Initial value Access
00000000B R/W
7
6
5
4
3
2
1
0
Address : 0000C3H
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PCRD
Initial value Access
00000000B R/W
7
6
5
4
3
2
1
0
Address : 0000C2H
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PCRE
Initial value Access
- - - - - - 00B R/W
7
7
7
7
6
6
6
6
5
5
4
4
3
3
2
1
0
Address : 0000C1H
PE1
PE0
PCRH
Initial value Access
- - - - - 000B R/W
2
1
0
Address : 0000C6H
PH2
PH1
PH0
PCRI
Initial value Access
- - 000000B R/W
5
4
3
2
1
0
Address : 0000C5H
PI5
PI4
PI3
PI2
PI1
PI0
PCRJ
Initial value Access
- - 000000B R/W
5
4
3
2
1
0
Address : 0000C4H
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
PCR6 to J carry out pull-up resistance control of the I/O ports handled.
PCR = 0 : Pull-up resistance turned off
PCR = 1 : Pull-up resistance turned on
• Open-drain Control Register (ODCR)
OCRH
Initial value Access
- - - - - 000B R/W
7
7
7
6
6
6
5
4
3
2
1
0
Address : 0000CAH
PH2
PH1
PH0
OCRI
Initial value Access
- - 000000B R/W
5
4
3
2
1
0
Address : 0000C9H
PI5
PI4
PI3
PI2
PI1
PI0
OCRJ
Initial value Access
- - 000000B R/W
5
4
3
2
1
0
Address : 0000C8H
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
OCRH to J carry out open-drain control in output mode of the I/O ports handled.
OCR = 0 : Standard output port in output mode
OCR = 1 : Open-drain output port in output mode
This has no meaning in input mode (output Hi-z) .
47
MB91133/MB91F133
• Analog Input Control Register (AICR)
AICK
Initial value Access
00000000B R/W
7
6
5
4
3
2
1
0
Address : 0000CFH
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
AICK controls each pin of the I/O ports handled as follows.
AIC = 0 : Analog input mode
AIC = 1 : Port input mode
Set to “0” when reset.
48
MB91133/MB91F133
3. 8/16-bit Up/Down Counter / Timer
8/16-bit up/down counter / timer is configured of event input pins × 6, 8-bit up/down counters × 2, 8-bit reload /
compare registers × 2 and their control circuits.
• Characteristics of 8/16-bit Up/Down Counter / Timer
• Counting from (0) d to (256) d is possible using an 8-bit counting register.
(Counting from (0) d to (65535) d is possible in 16-bit × 1 operation mode.)
• 4 types of counting mode can be selected by the count clock
• Selection can be made from two types of internal clock as the count clock in timer mode.
• Detection edge of the external pin input signals can be selected in up/down count mode.
• Phase difference count mode is suited to count encoders such as motors. Turning angle and turning number,
etc., can easily and accurately be counted by separately inputting phase A, B and Z outputs of the encoder.
• Selection can be made from two function types for the ZIN pin (valid for all modes) .
• Compare and reload functions are featured, and each function can be used alone or in combination.
Up/down counting with random width can be carried out using both functions in combination.
• The count direction directly before can be identified by the count direction flag.
• Generation of interruptions in case of compared match, reload (underflow) or overflow and in cases where the
count direction is changed can be controlled separately.
49
MB91133/MB91F133
• Block Diagram
8/16-bit Up/Down Counter / Timer (ch0)
Data bus
8 bit
Reload / Compare Register 0 (RCR0)
CGE1 CGE0 C/GS
RCUT
Reload control
ZIN0
Edge/level detection
UCRE
RLDE
Counter clear
8 bit
UDCC
Up/Down Count Register 0 (UDCR0)
Carry
CMPF
CES1 CES0
CMS1 CMS0
UDFF OVFF
CITE UDIE
Count clock
UDF1 UDF0 CDCF CFIE
AIN0
BIN0
Up/down count
clock selection
Interruption output
CSTR
Pre-scalar
CLKS
50
MB91133/MB91F133
8/16-bit Up/Down Counter / Timer (ch1)
Data bus
8 bit
Reload / Compare Register 1 (RCR1)
CGE1 CGE0 C/GS
RCUT
Reload control
RLDE
ZIN1
Edge/level detection
UCRE
UDCC
Counter clear
8 bit
Up/Down Count Register 1 (UDCR1)
CMPF
UDFF OVFF
CMS1 CMS0 CES1 CES0 M16E
Carry
CITE UDIE
Count clock
UDF1 UDF0 CDCF CFIE
Interruption output
AIN1
BIN1
Up/down count
clock selection
Pre-scalar
CSTR
CLKS
51
MB91133/MB91F133
• Register List
31
24 23
16 15
8
7
0
RCR1
CCRH0
CCRH1
RCR0
CCRL0
CCRL1
UDCR1
UDCR0
CSR0
CSR1
Up/down count register ch0 (UDCR0)
bit
7
6
5
4
3
D03
2
1
0
Address : 000087H
D07
D06
D05
D04
D02
D01
D00
Up/down count register ch1 (UDCR1)
bit
15
14
D16
13
12
11
10
9
8
Address : 000086H
D17
D15
D14
D13
D12
D11
D10
Reload compare register ch0 (RCR0)
bit
7
6
5
4
3
2
1
0
Address : 000085H
D07
D06
D05
D04
D03
D02
D01
D00
Reload compare register ch1 (RCR1)
bit
15
14
D16
13
12
11
10
9
8
Address : 000084H
D17
D15
D14
D13
D12
D11
D10
Counter Status register ch0, 1 (CSR0, 1)
bit
7
6
5
4
3
2
1
0
00008BH
Address :
CSTR
CITE
UDIE
CMPF OVFF
UDFF
UDF1
UDF0
00008FH
Counter control register ch0, 1 (CCRL0, 1)
bit
7
6
5
4
3
2
1
0
000089H
Address :
CTUT UCRE
RLDE UDCC CGSC CGE1
CGE0
00008DH
Counter control register ch0 (CCRH0)
bit
15
14
CDCF
13
12
11
10
9
8
Address : 000088H
M16E
CFIE
CLKS
CMS1 CMS0
CES1
CES0
Counter control register ch1 (CCRH1)
bit
15
14
CDCF
13
12
11
10
9
8
Address :00008CH
CFIE
CLKS
CMS1 CMS0
CES1
CES0
52
MB91133/MB91F133
4. 16-bit Reload Timer
The 16-bit timer is configured with a 16-bit down counter, 16-bit reload register, pre-scalar to prepare the internal
count clock and control register. Selection can be made from three types of internal clocks (machine clock 2 /
8 / 32 cycles) as the input clock. DMA transfer can be initiated by interruption. The MB91133/MB91F133 features
a 5-channel timer.
• Block Diagram
16
16-bit reload register
8
Reload
RELD
16
OUTE
OUTL
INTE
UF
16-bit down counter
2
UF
OUT
CTL.
GATE
2
IRQ
CSL1
CNTE
TRG
Clock selector
CSL0
Re-trigger
2
IN CTL.
EXCK
PWM (ch0, ch1)
A/D (ch2)
3
φ
φ
φ
Pre-scalar
clear
21 23 25
MOD2
MOD1
MOD0
3
Channel 2TO output of the reload timer is connected to the A/D converter inside the LSI. Thus, A/D conversion
can be started up at the cycle set in the reload register.
53
MB91133/MB91F133
5. PPG Timer
The PPG timer can efficiently output accurate PWM waveforms. The MB91130 series features a 6-channel
PPG timer.
• PPG Timer Characteristics
• Each channel is configured with a 16-bit down counter, 16-bit data register with cycle setting buffer, 16-bit
compare register with duty setting buffer and pin control area.
• Selection can be made from four types of count clocks for 16-bit down counters.
Internal clock φ, φ4, φ16, φ64
• Counter values can be initialized to “FFFFH” by resetting and counter borrowing.
• PWM output is available per channel.
• Register outline
Cycle setting register : Reloading register with buffer
Duty setting register : Compare register with buffer
Transfer from buffer is carried out by counter borrowing.
• Pin control outline
Set to “1” by duty match. (Priority)
Resets to “0” by counter borrowing.
All “L” (or “H”) can simply be output by using the output values fixing mode.
Polarization can also be specified.
• Interruption request can be generated by selecting from the following combinations.
Initiation of this timer
Counter borrow generation (cycle match)
Duty match generation
Counter borrow generation (cycle match) or duty match generation
DMA transfer can be initiated by the above interruption requests.
• Simultaneous initiation of a number of channels can be set by software or other interval timers. Re-start during
operation can also be set.
54
MB91133/MB91F133
• Block Diagram
Overall Block Diagram of PPG Time
TRG input
PWM timer ch0
16-bit reload timer
ch0
PWM0
16-bit reload timer
ch1
TRG input
PWM1
PWM timer ch1
General control
register 1
(factor selection)
TRG input
PWM2
4
PWM timer ch2
General control
register 2
TRG input
PWM3
4
PWM timer ch3
External TRG0 to 3
External TRG4
External TRG5
PWM timer ch4
PWM timer ch5
PWM4
PWM5
55
MB91133/MB91F133
Block Diagram of PPG Timer for 1 Channel
PCSR
PDUT
Pre-scalar
1 / 1
CMP
1 / 4
CK
Load
1 / 16
1 / 64
16-bit down counter
Start
Borrow
PPG mask
S
R
Q
PWM OUTPUT
Peripheral system clock
Reverse bit
Enable
IRQ
Interruption
selection
Edge
TRG input
detection
Soft trigger
56
MB91133/MB91F133
• Register list
Address
15
0
GCN1
R/W General control register 1
R/W General control register 2
000000DCH
000000DFH
GCN2
PCNL
PCNL
PCNL
PCNL
PTMR
PCSR
PDUT
R
ch0 Timer register
000000E0H
000000E2H
W
W
ch0 Peripheral setting register
ch0 Duty setting register
000000E4H
000000E6H
PCNH
PCNH
PCNH
PCNH
R/W ch0 Control status register
000000E8H
000000EAH
PTMR
PCSR
PDUT
R
ch1 Timer register
W
W
ch1 Peripheral setting register
ch1 Duty setting register
000000ECH
000000EEH
R/W ch1 Control status register
000000F0H
000000F2H
PTMR
PCSR
PDUT
R
ch2 Timer register
W
W
ch2 Peripheral setting register
ch2 Duty setting register
000000F4H
000000F6H
R/W ch2 Control status register
000000F8H
000000FAH
PTMR
PCSR
PDUT
R
ch3 Timer register
W
W
ch3 Peripheral setting register
ch3 Duty setting register
000000FCH
000000FEH
R/W ch3 Control status register
(Continued)
57
MB91133/MB91F133
(Continued)
Address
15
0
00000100H
PTMR
PCSR
PDUT
R
ch4 Timer register
W
W
ch4 Peripheral setting register
ch4 Duty setting register
00000102H
00000104H
00000106H
PCNL
PCNH
R/W ch4 Control status register
00000108H
0000010AH
PTMR
PCSR
PDUT
R
ch5 Timer register
W
W
ch5 Peripheral setting register
ch5 Duty setting register
0000010CH
0000010EH
PCNH
PCNL
R/W ch5 Control status register
58
MB91133/MB91F133
6. Multifunction Timer
The multifunction timer unit is configured of a 16-bit freerun timer × 1, 16-bit output compare × 8, 16-bit input
capture × 4, 16-bit PPG timer × 6 ch and waveform generation area modules. 12 independent waveform outputs
based on a 16-bit free-run timer are possible using this function and measurement of input pulse width and
external clock cycle is also possible.
• Multifunction Timer Configuration
• 16-bit free-run timer ( × 1)
The 16-bit free-run timer consists of a 16-bit up counter, control register, 16-bit compare clear register and
pre-scalar. Output values of this counter are used as the base timer for output compare and input capture.
• Counter operation clocks can be selected from six types.
Six types of internal clocks (φ2, φ4, φ8, φ16, φ32, φ64)
φ : Machine clock
• Interruption can be generated by overflow of the counter value and a compared match with compare
clear register. (Mode setting is required for a compared match.)
• Counter value can be initialized to “0000H” by a compared match with the reset, software clear or the
compare clear register.
• Output compare ( × 8)
Output compare is configured of 16-bit compare register × 8, latch for compare output and control register.
Interruptioncanbegeneratedaswellasreversingoutputlevelwhenthe16-bitfree-runtimervalueandcompare
register value match.
• 8 compare registers can be operated independently. Output pins and interruption flags support each
compare register.
• Output pins can be controlled by pairing two compare registers. Output pins are reversed using two
compare registers.
• Initial value of each output pin can be set.
• Interruption can be generated by matching compare.
• Input capture ( × 4)
Input capture is configured with four independent external input pins , supported capture and control register.
16-bit free-run timer value is held in the capture register by detecting the random edge of signals that are input
by the external input pin, and interruption can simultaneously be generated.
• Valid edges (rising edge, falling edge, both edges) of external input signals can be selected.
• Four input captures can be operated independently.
• Interruption can be generated by the valid edges of external input signals.
• 16-bit PPG timer ( × 6)
Refer to PPG timer
59
MB91133/MB91F133
• Waveform Generation Area
The waveform generation area is configured with 8-bit timer × 3, 8-bit reload register × 3, timer control register
× 3 and 8-bit waveform control register. This control circuit controls the waveform of the 16-bit PPG timer and
real-time output, and DC chopper output and non-overlapping 3-phase waveform output to be used for inverter
control are possible.
• Non-overlapping pulse output of the PPG timer is possible by setting dead time of the 8-bit timer (dead
time timer function) .
• Real timer output is operated by the 2-channel mode and non-overlapping output of the waveform is
possible by setting the dead time of the 8-bit timer (dead time timer function) .
• Operation of PPG timer can easily be started/stopped by generating a GATE signal for the PPG timer
operation through match detection of real-time output compare (GATE function).
• The 8-bit timer is operated by match detection of real-time output compare, and operation of the PPG timer
can easily be started/stopped by generating a GATE signal for the PPG timer until the 8-bit timer is stopped
(GATE function) .
• Pin output can be forcibly controlled by input to the DTTI pin. Pins can be controlled externally even if
oscillations stop due to lack of clocks for inputs to this pin. (Each pin level can be set by the program .)
If this function is used, the port should be set to output (DDR = 1) and the output value should be
described in the PDR beforehand.
60
MB91133/MB91F133
• Block Diagram
Block Diagram of PPG Timer for 1 Channel
φ
Interruption
IVFE STOP MODE SCLR CLK2
IVF
CLK1 CLK0
Cycle device
Clock
16-bit free-run timer
16-bit compare clear register
(Ch. 6 compare register)
Interruption
Compare circuit
Compare register 0/2/4
MS13
0
ICLR
Q
ICRE
T
T
RT0/2/4
Compare circuit
To waveform
generation area
Compare register 1/3/5
CMOD
Q
RT1/3/5
To waveform
generation area
Compare circuit
IOP1
IOP0
IOE1
IOE0
Interruption
Interruption
IN 0/2
Capture data register 0/2
Edge detection
EG11 EG10
EG01 EG00
Capture data register 1/3
IN 1/3
Edge detection
ICP0
ICP1
ICE0
ICE1
Interruption
Interruption
61
MB91133/MB91F133
Block Diagram of Waveform Generation Area
DCK2 DCK1
DCK0
TMD1 TMD0 NRSL
DTIL
DTIE
φ
DTTI control circuit
DTTI
Cycle device
Clock
GATE 0/1
Selector
TO0
RT0
Waveform
generation area
TO1
RT1
RTO0/U
Compare
circuit
RTO1/X
Selector
8-bit timer
U
X
Dead time
generation
8-bit timer register 0
GATE 2/3
Selector
TO2
TO3
Waveform
RT2
generation area
RT3
RTO2/V
RTO3/Y
Compare
circuit
8-bit timer
Selector
V
Y
Dead time
generation
8-bit timer register 1
GATE 4/5
Selector
TO4
TO5
Waveform
RT4
generation area
RT5
RTO4/W
RTO5/Z
Compare
circuit
8-bit timer
Selector
W
Z
Dead time
generation
8-bit timer register 2
62
MB91133/MB91F133
• Registers List
Address
15
8
7
0
000044H to 4BH
IPCP
(R)
00004DH, 4FH
000054H to 63H
000064H to 6BH
00006CH, 6DH
00006EH, 6FH
ICS
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
OCCP
OCS
TCDT
TCCS
0000ACH, AEH
B2H
DTCR
0000ADH, AFH
B3H
TMRR
0000B1H
STGCR
63
MB91133/MB91F133
7. External Interruption
The external interruption control area is the block that controls the external interruption requests input in INT0
to INT23. The level of request to be detected can be selected from “H”, “L”, “Rising edge” or “ Falling edge”.
• Block diagram
R-BUS
24
Interruption permission register
24
24
48
24
Interruption
requests
Gate
Factor F/F
Edge detection circuit
INT0 to INT23
Interruption factor register
Request level setting register
• Register List
External interruption permission register (ENIR)
15
14
13
12
11
10
9
8
bit
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
External interruption factor register (EIRR)
15
14
13
12
11
10
9
8
bit
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
Request level setting register (ELVR)
7
6
5
4
3
2
1
0
bit
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
15
14
13
12
11
10
9
8
bit
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
There are three sets of the above registers (for 8 channels) for a total of 24 channels.
64
MB91133/MB91F133
8. Delay Interruption Module
The delay interruption module generates interruptions for task switching. Interruption requests to the CPU can
be generated / cancelled using software with this module.
• Block Diagram
Refer to “9.(2) Block Diagram of Interruption Controller” for the block diagram of the delay interruption generation
area.
• Register List
bit 7
6
5
4
3
2
1
0
Address : 00000430H
DICR
DLYI
R/W
65
MB91133/MB91F133
9. Interruption Controller
The interruption controller carries out interruption reception and arbitration.
• Hardware configuration of the interruption controller
This module consists of the following items.
• ICR register
• Interruption priority judgement circuit
• Interruption level, interruption number (vector) generation area
• Cancellation request generation area for HOLD request
• Major interruption controller functions
This module has the following functions.
• Detection of interruption requests
• Priority grade judgement (depending on the level and number)
• Transferring interruption level of factors for the judgement results (to CPU)
• Transferring interruption number of factors for the judgement results (to CPU)
• Recovery instruction from stop mode by generating interruption
• Cancellation of HOLD request to the bus master
• Resetting Interruption Factors
There are restrictions between RETI instructions and those for resetting interruption factors in the interruption
routine.
66
MB91133/MB91F133
• Block Diagram
INT0
OR
IM
Priority grade judgement
5
LEVEL4 to 0
NMI
NMI processing
4
HLDREQ
HLDCAN
VCT5 to 0
(Holding
request)
LEVEL
Generation
of
LEVEL /
VECTOR
judgement
ICR00
RI00
6
VECTOR
judgement
ICR47
RI47
(DLYIRQ)
DLYI
R-BUS
Note : DLYIshowninthefigureindicatesdelayinterruptionarea.(Refertothechapteronthedelayinterruption
module for details.)
INTO is the wake-up signal to the clock control area in case of sleep or stop.
HLDCAN is the bus vacation request signal to bus masters other than the CPU.
There is no NMI function in this model.
67
MB91133/MB91F133
• Register List
bit 7
6
5
4
3
2
1
0
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
ICR3
ICR2
ICR1
ICR0
00000400H
00000401H
00000402H
00000403H
00000404H
00000405H
00000406H
00000407H
00000408H
00000409H
0000040AH
0000040BH
0000040CH
0000040DH
0000040EH
0000040FH
00000410H
00000411H
00000412H
00000413H
00000414H
00000415H
00000416H
00000417H
00000418H
00000419H
0000041AH
0000041BH
0000041CH
0000041DH
0000041EH
0000041FH
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
ICR16
ICR17
ICR18
ICR19
ICR20
ICR21
ICR22
ICR23
ICR24
ICR25
ICR26
ICR27
ICR28
ICR29
ICR30
ICR31
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
R/W
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
R/W
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
R/W
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
R/W
(Continued)
68
MB91133/MB91F133
(Continued)
bit 7
6
5
4
3
2
1
0
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
Address:
ICR3
ICR2
ICR1
ICR0
00000420H
00000421H
00000422H
00000423H
00000424H
00000425H
00000426H
00000427H
00000428H
00000429H
0000042AH
0000042BH
0000042CH
0000042DH
0000042EH
0000042FH
ICR32
ICR33
ICR34
ICR35
ICR36
ICR37
ICR38
ICR39
ICR40
ICR41
ICR42
ICR43
ICR44
ICR45
ICR46
ICR47
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
R/W
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
R/W
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
R/W
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
R/W
Address:
LVL3
R/W
LVL2
R/W
LVL1
R/W
LVL0
R/W
00000431H
HRCL
69
MB91133/MB91F133
10. Clock Generation Area (low power consumption mechanism)
Clock generation area is a module with the following functions.
• CPU clock generation (including gear function)
• Peripheral clock generation (including gear function)
• Reset generation and holding factors
• Standby function (including hardware standby)
• PLL (Phase Locked Loop) is built in
• Register list
Address
7
0
RSRR/WTCR
STCR
Reset factor / watchdog cycle control register
Standby control register
000480H
000481H
000482H
000483H
000484H
000485H
000488H
PDRR
CTBR
DMA request blocking register
Time base timer clear register
GCR
Gear control register
WPR
Watchdog reset generation postponement register
PLL / 32-K clock control register
PCTR
70
MB91133/MB91F133
• Block diagram
[ Gear control area ]
GCR register
CPU gear
Peripheral
gear
X0A
X1A
Oscillation
circuit
CPU clock
1/2
Internal clock
Internal
M
P
X
generation
bus clock
circuit
X0
X1
Oscillation
circuit
Internal
PLL
peripheral clock
32-kHz selection circuit
[ Stop/sleep control area ]
Internal interruption
Internal reset
STCR register
PDRR register
STOP status
SLEEP status
CPU hold request
DMA request
Status
transfer
control circuit
Reset
generation
F/F
Internal reset
Power on
detection circuit
[ Reset factor circuit ]
VCC3
R
RSRR register
[ Watchdog control area ]
WPP register
GND
RST pin
Watchdog F/F
Count clock
CTBR register
Time base timer
71
MB91133/MB91F133
11. 8-/10-bit A/D Converter
The 8-/10-bit A/D converter features functions that convert analog input voltages to 10- or 8-bit digital values
using the RC sequential comparison conversion method. The input signal is selected from 8-channel analog
input pins and three types of conversion initiation can be selected from software, internal clock, or external pin
trigger.
• characteristics of 8-/10-bit A/D converter
The A/D conversion function for converting analog voltages (input voltages) input into the analog input pins to
digital values has the following characteristics.
• Conversion time is minimum 5.0 µs (including sampling time when machine clock is 33 MHz) .
• Conversion method is RC sequential comparison conversion method with sample holding circuit.
• 10- or 8-bit resolution can be selected.
• Analog input pin can be selected from 8 channels using the program.
• interruption request can be generated when A/D conversion ends.
• Data is not lost even during continuous conversion as conversion data protection function works while inter-
ruptions are permitted.
• Initiation factors for conversion can be selected from software, 16-bit reload timer 2 (rising edge) , or external
pin trigger (L level detection) .
There are three types of conversion modes.
Table 13.1-1 Conversion Modes of 8-/10-bit A/D Converter
Conversion Modes
Single Conversion Operation
Scan Conversion Operation
Converts the specified channel (1 channel Converts a series of channels (up to 8
Single conversion mode
only) once and ends.
channels can be specified) once and ends.
Consecutive
Repeatedly converts the specified channel Repeatedly converts a series of channels
conversion mode
(1 channel only) .
(up to 8 channels can be specified) .
Converts a series of channels (up to 8
channels can be specified) but is suspend-
ed between each channel conversion and
waits until the next one is initiated.
Suspends after converting the specified
Stop conversion mode channel (1 channel only) once and waits
until the next one is initiated.
72
MB91133/MB91F133
• Block Diagram of 8-/10-bit A/D Converter
The 8-/10-bit A/D converter is configured with the following 9 blocks.
• A/D control status register (ADCS1, 2)
• A/D data register (ADCR)
• Clock selector (input clock selector to initiate A/D conversion)
• Decoder
• Analog channel selector
• Sample holding circuit
• D/A converter
• Comparator
• Control circuit
• Block Diagram
AVSS AVR± AVSS
MP
D/A converter
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Input
circuit
Sequential
comparison register
Comparator
Sample and
holding circuit
Data register
ADCR
Decoder
A/D control register 1
A/D control register 2
16-bit reload timer 2
External pin trigger
ADCS1, 2
Operation clock
Pre-scalar
φ
• Register List
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0000CFH
00003AH
000038H
AICK
ADCS1
ADCS0
ADCR
73
MB91133/MB91F133
12. 8-bit D/A Converter
The 8-bit D/A converter is an R-2R type D/A converter with 8-bit resolution.
• Characteristics of the 8-bit D/A converter
The MB81130 series features a 3-channel D/A converter and output control can be carried out individually by
the D/A control register.
• Block Diagram of 8-bit D/A Converter
The 8-bit D/A converter is configured with the following three blocks.
• 8-bit resistance ladder
• Data register
• Control register
• Block Diagram
R − BUS
DA27 to DA20
DA17 to DA10
DA07 to DA00
DAVC
DAVC
DAVC
DA27
DA17
DA07
DA20
DA10
DA00
DAE
Standby control
DAE
Standby control
DAE
Standby control
DA output
DA output
DA output
74
MB91133/MB91F133
• 8-bit D/A Converter Pins
D/A converter pins are dedicated pins.
• Registers of 8-bit D/A Converter
The 8-bit D/A converter has the following two registers.
D/A control register (DACR0, 1, 2)
D/A data register (DADR2, 1, 0)
• Register list
D/A converter data register 0
bit
7
6
5
4
3
2
1
0
DADR0
00000ABH
DA07
DA06
DA05
DA04
DA03
DA02
DA01
DA00
D/A converter data register 1
bit
15
14
13
12
11
10
9
8
DADR1
00000AAH
DA17
DA16
DA15
DA14
DA13
DA12
DA11
DA10
D/A converter data register 2
bit
bit
bit
bit
23
22
21
20
19
18
17
16
DADR2
00000A9H
DA27
DA26
DA25
DA24
DA23
DA22
DA21
DA20
D/A control register 0
7
6
5
4
3
2
1
9
0
DACR0
00000A7H
DAE0
D/A control register 1
15
23
14
22
13
21
12
20
11
19
10
18
8
DACR1
00000A6H
DAE1
D/A control register 2
17
16
DACR2
DAE2
00000A5H
75
MB91133/MB91F133
13. 4-bit Level Comparator
The 4-bit level comparator is the module that compares input levels (large/small) and compares the size of the
analog input voltage with 4-bit digital values.
• Functions of the 4-bit level comparator
Compares analog voltage that has been input to the analog input pins (input voltage) with 4-bit digital value and
has the following characteristics.
• Conversion time is minimum 1 µs (including sampling time) .
• Sampling time is minimum 0.5 µs.
• Interruption requests can be generated when analog comparison ends.
• Interruption of 4-bit level comparator
Table 15.1-1 Interruption and DMAC of 4-bit level comparator
Interruption control register
Interruption
number
TBR default
address
Offset
DMAC
Register name
Address
#61 (3DH)
ICR45
00042DH
308H
000FFF08H
×
× : Initiation is impossible
76
MB91133/MB91F133
• Block Diagram of 4-bit Level Comparator
The 4-bit level comparator is configured with the following three blocks.
• Comparator
• 4-bit resistance ladder
• Control register
• Block diagram
AVCC
AVR±
AVSS
4-bit D/A (resistance ladder)
RD3 - 0
Comparator
CPLV
AN7
Sample &
INT
INTE
CPEN
holding circuit
Interruption
Reload timer
φ
Operation clock
77
MB91133/MB91F133
• Registers of 4-bit Lev el Comparator
• Register list
bit 31
bit 24bit 23
bit 16
0000-0018H
LVLC
Control register (LVLC)
bit
31
30
29
28
27
26
25
24
RD3
RD2
RD1
RD0
CPLV
INT
INTE
CPEN
0000018H
Attribute
Initial value
R/W
( X )
R/W
( X )
R/W
( X )
R/W
( X )
R/W
( 0 )
R/W
( 0 )
R/W
( 0 )
R/W
( 0 )
78
MB91133/MB91F133
14. UART
UART is the general-purpose serial data communications interface to carry out synchronous or asynchronous
communication (start-stop synchronization) with external systems. It has a master/slave-type communications
function (multiprocessor mode: supporting only master side) as well as normal bi-directional communications
function (normal mode).
• UART Functions
UART is the general-purpose serial data communications interface that sends and receives serial data to/from
other CPUs and peripheral equipment, and has functions shown in Table 16.1-1.
Table 16.1-1 UART Functions
Functions
Data buffer
Full-duplex double buffer
• Clock synchronous (without start-stop bit)
• Clock asynchronous (start-stop cycle)
Transfer mode
• Dedicated baud rate generator is available. Can be selected from 8 types.
• External clock input is possible.
• Internal clock (Internal clocks that are provided from 16-bit reload timer support-
ing each channel can be used.)
Baud rate
• 7-bit (in case of asynchronous normal mode only)
• 8-bit
Data length
Signal method
Non Return to Zero (NRZ) method
• Framing error
Reception error detection
• Overrun error
• Parity error (impossible in case of multiprocessor mode)
• Reception interruption (reception completion, reception error detection)
• Transmission interruption (transmission completion)
Interruption request
Master/slave-type
communications function
(Multiprocessor mode)
Communication between 1 (master) and n (slaves) is possible
(Only supports master side)
Note : Start / stop bits are not added by UART and only data is transferred.
Table 16.1-2 UART Operations Mode
Data length
Synchronization
Operations mode
Stop bit length
method
Without parity
With parity
0
1
2
Normal mode
7-bit or 8-bit
Asynchronous
Asynchronous
Synchronous
1-bit or 2-bit *2
N/A
Multiprocessor mode
8 + 1*1
Normal mode
8
: Setting is impossible
*1 : “ + 1” is address / data selection bit (A/D) to be used to control communications.
*2 : 1-bit only can be detected for stop bit in case of reception.
79
MB91133/MB91F133
• UART Block Diagram
UART is configured with the following 11 blocks.
• Clock selector
• Mode register (SMR0 to 4)
• Reception control circuit
• Transmission control circuit
• Reception status judgement circuit
• Shift register for reception
• Sift register for transmission
• Control register (SCR0 to 4)
• Status register (SSR0 to 4)
• Input data register (SIDR0 to 4)
• Output data register (SODR0 to 4)
• Block Diagram
Control bus
Reception
interruption
signals
Dedicated baud rate
generator
#26 to 30 *
Reception
interruption
signals
Transmission
clock
Clock
16-bit reload timer
selector
#31 to 35 *
Reception clock
Reception
control circuit
Transmission
control circuit
Pin
Start bit
detection circuit
Transmission
start circuit
<SCK0 to SCK4>
Reception bit
counter
Transmission bit
counter
<SOT0 to SOT4 >
Pin
Reception parity
counter
Transmission parity
counter
<SIN0 to SIN4 >
Pin
Shift register
for reception
Shift register
for transmission
Reception
ends
Reception status
judgement circuit
Transmission starts
SIDR0
4
SODR0
4
Reception error
Generation signal
(to CPU)
Internal data bus
MD1
MD0
CS2
CS1
CS0
PEN
P
SBL
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
SMR0 to 4
registers
SCR0 to 4
registers
SSR0 to 4
registers
CL
A/D
REC
RXE
TXE
SCKE
SOE
TIE
* : Interruption number
80
MB91133/MB91F133
• Block Diagram of UART Pins
Data bus
Resource input
0
1
PDR read
PDR
pin
0
1
Resource output
Resource output
permission
DDR
ODCR
PCR
PDR : Port Data Register
DDR : Data Direction Register
ODCR : Open-drain Control Register
PCR : Pull-up Control Register
• Register List
Address
bit 15
bit 8
bit 7
bit 0
ch0 : 0000_001EH, 1FH
ch1 : 0000_0022H, 23H
ch2 : 0000_0026H, 27H
ch3 : 0000_0072H, 73H
ch4 : 0000_0076H, 77H
Control register
(SCR)
Mode register
(SMR)
ch0 : 0000_001CH, 1DH
ch1 : 0000_0020H, 21H
ch2 : 0000_0024H, 25H
ch3 : 0000_0070H, 71H
ch4 : 0000_0074H, 75H
Status register
(SSR)
Input/output data register
(SIDR/SODR)
ch0 : 0000_007AH
ch1 : 0000_0078H
ch2 : 0000_007EH
ch3 : 0000_007CH
ch4 : 0000_0082H
Communications pre-scalar control register
(CDCR)
Vacant
81
MB91133/MB91F133
15. DMA Controller
The DMA controller is the built-in module of the MB91130 series that carrie out direct memory access (DMA)
transfers.
• Characteristics of the DMA Controller
• 8 channels
• 3 transfer mode types : single/block transfer, burst transfer, continuous transfer
• Transfer between overall address areas
• Maximum 65,536 transfers
• Interruption function when transfer ends
• Increase/decrease in transfer addresses can be selected using software
• 3 external transfer request input/output pins and 3 external transfer end output pins
• Block Diagram
3
5
3
3
Edge / level
detection circuit
DREQ0 to DREQ2
DACK0 to DACK2
EOP0 to EOP2
3
8
Sequencer
Interruption request
Built-in resource
transfer request
Data buffer
Switcher
DPDP
DACSR
DATCR
Mode
BLK DEC
BLK
DMACT
INC / DEC
SADR
DADR
82
MB91133/MB91F133
• Register List
(In DMAC : DMAC internal registers)
31
0
00000200H
DPDP
00000204H
00000208H
DACSR
DATCR
(On RAM : DMA descriptors)
bit 31
bit 0
DMA
ch0
DPDP + 0H
Descriptor
DMA
DPDP + 0CH
ch1
Descriptor
DPDP + 54H
DMA
ch7
Descriptor
83
MB91133/MB91F133
16. Bit Search Module
The bit search module searches for 0, 1 or change points on data that has been written in the input register, and
returns the detected bit position.
• Block Diagram
D-BUS
Input latch
Address
decoder
Detection
mode
Changing to 1 detection data
Bit search circuit
Detection results
• Register List
31
0
Address:
Data register for 0 detection
BSD0
BSD1
BSDC
BSRR
000003F0H
Address:
Address:
Address:
Data register for 1 detection
000003F4H
000003F8H
000003FCH
Data register for change point detection
Detection results register
84
MB91133/MB91F133
17. FLASH Memory
The MB91FV130 / MB91F133 have a 254-KB (2 Mbit) capacity and feature a FLASH memory that can write
each half-word (16 bits) using the FR-CPU, delete individual sectors sector and delete groups of sectors together
using a single 3-V power source.
• Outline of FLASH Memory
This is a built-in 3-V 254-KB FLASH memory. This FLASH memory is the same as our 2-Mbit (256 K × 8 / 128
K × 16) FLASH memory MBM29LV400C and writing is possible from outside the device using a ROM writer. If
used as a built-in ROM of the FR-CPU, as well as having an equivalent function to the MBM29LV400C, instruc-
tions / data can be read per word (32 bits) and high-speed operation of the device can be realized.
Refer to the MBM29LV400C data sheet as well as this manual.
The following functions can be realised in MB91FV130 / MB91F133 by combining the FLASH memory macro
and FR-CPU interface circuits.
• Functioning as memory for CPU program / data storage
Access is possible with 32-bit bus width when used as ROM
Reading / writing and erasing (automatic program algorithm*) are possible using CPU
• MBM29LV400C-equivalent function of single FLASH memory products
Reading / writing and erasing (automatic program algorithm*) are possible using ROM writer
A case where this FLASH memory is used from FR-CPU is described in this section.
Refer to the ROM writer manual separately for details if this FLASH memory is used from ROM writer.
* : Automatic program algorithm = Embedded Algorithm TM
Embedded Algorithm TM is the trademark of Advanced Micro Device.
• Block Diagram
Rising edge detection
RDY/BUSY
RESET
Control signal
generation
BYTE
OE
FLASH memory
2 Mbit (254 K × 8/127 K × 16)
WE
CE
FA18 - 0
DI15 - 0 DO31 - 0
INTE
RDYINT
RDY
WE
Address buffer
CA18 - 0
Data buffer
CD31 - 0
FR-C bus (instruction / data)
85
MB91133/MB91F133
• Memory Map
FLASH memory mode and CPU mode for address mapping of FLASH memory are different. Mapping under
each mode is shown as follows.
• Memory map in FLASH memory mode
0FFFFFH
SA9
SA8
SA7
2 M-FLASH
Memory image
SA6
SA5
SA4
SA3
0C0000H
SA2
SA1
SA0
( SAn : sector address n )
010000H
000000H
• Memory map in CPU memory mode
0FFFFFH
0FFFFFH
0F8000H
SA4
SA9
SA3
SA2
SA1
SA8
SA7
SA6
0F4000H
0F0000H
FLASH memory area
0E0000H
0C0800H
0C0000H
SA0
SA5
RAM area
2 KByte
( SAn : sector address n )
Status register
0007C0H
000000H
0C0800H
0C0000H
CPU mode
86
MB91133/MB91F133
• Sector address table
Position of bit
Sector Capacity
handled
Sector Address
Address Area
SA5
SA6
SA7
SA8
SA9
SA0
SA1
SA2
SA3
SA4
000C0802, 3h to 000DFFFE, Fh (LSB side 16 bit)
000E0002, 3h to 000EFFFE, Fh (LSB side 16 bit)
000F0002, 3h to 000F3FFE, Fh (LSB side 16 bit)
000F4002, 3h to 000F7FFE, Fh (LSB side 16 bit)
000F8002, 3h to 000FFFFE, Fh (LSB side 16 bit)
000C0800, 1h to 000DFFFC, Dh (MSB side 16 bit)
000E0000, 1h to 000EFFFC, Dh (MSB side 16 bit)
000F0000, 1h to 000F3FFC, Dh (MSB side 16 bit)
000F4000, 1h to 000F7FFC, Dh (MSB side 16 bit)
000F8000, 1h to 000FFFFC, Dh (MSB side 16 bit)
bit 15 to 0
bit 15 to 0
bit 15 to 0
bit 15 to 0
bit 15 to 0
bit 31 to 16
bit 31 to 16
bit 31 to 16
bit 31 to 16
bit 31 to 16
63 Kbyte
32 Kbyte
8 Kbyte
8 Kbyte
16 Kbyte
63 Kbyte
32 Kbyte
8 Kbyte
8 Kbyte
16 Kbyte
• Registers of FLASH Memory
There are two types of FLASH memory registers, namely status register (FLCL) and wait register (FWTC).
• Status Register (FLCR) (CPU mode)
This register indicates the operation status of the FLASH memory. It controls interruption to the CPU and
writing to the FLASH memory.
Access is possible only in CPU mode. This register must not be accessed under Read / Modify / Write
instructions.
bit 7
bit 6
bit 5
WE
bit 4
bit 3
bit 2
bit 1
bit 0
LPM
INTE RDYINT
RDY
0007C0H
R/W
( 0 )
R/W
( 0 )
R/W
( 0 )
R
( X )
R/W
( 0 )
( X )
( X )
( X )
• Wait Register ( FWTC)
Carries out wait control of the FLASH memory in CPU mode. Also, controls access to high-speed reading
(33MHz) of FLASH memory. Configuration of Wait Register (FWTC) is as follows :
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FACH WTC1 WTC0
0007C4H
W
( 0 )
R/W
( 0 )
R/W
( 0 )
(
)
(
)
(
)
(
)
(
)
Note : FACH bit should be set to 1 or WTC1/0 should be set to 01b to operate machine clocks of CPUs exceeding
25 MHz.
87
MB91133/MB91F133
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V)
Rating
Parameter
Power voltage
Symbol
Unit
Remarks
Min.
Max.
VSS + 6.5
VSS + 3.8
VSS + 6.5
VSS + 6.5
VCC5 + 0.3
VCC3 + 0.3
AVCC + 0.3
VCC5 + 0.3
10
VCC5
VCC3
AVCC
AVRH
VI5
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
V
V
V
V
V
V
V
V
Power voltage
Analog power voltage
*1
*1
Standard analog voltage
Input voltage
Input voltage
VI3
X0, X1, X0A, X01A
Analog pin input voltage
Output voltage
VIA
VO
Maximum “L” level output current
Average “L” level output current
Maximum total “L” level output current
Average “L” level total output current
Maximum “H” level output current
Average “H” level output current
Maximum total “H” level output current
Average “H” level total output current
Electricity consumption
IOL
mA *2
mA *3
mA
IOLAV
ΣIOL
ΣIOLAV
IOH
4
100
50
mA *4
mA *2
mA *3
mA
−10
IOHAV
ΣIOH
ΣIOHAV
PD
−4
−50
−20
mA *4
mW
500
Storage temperature
Tstg
−55
+150
°C
*1 : Care must be taken that this does not exceed VCC5 + 0.3 V when the power is turned on. Also, care must be
taken that AVCC does not exceed VCC5 when the power is turned on. AVCC should be set at the same electrical
potential as VCC5.
*2 : Peak value of the pin concerned is regulated as the maximum output current.
*3 : Average current within 100 ms flowing in the pin concerned is regulated as the average output current.
*4 : Average current within 100 ms flowing in all pins concerned is regulated as the average total output current.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
88
MB91133/MB91F133
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Value
Parameter
Common
Symbol
VCC5
Unit
V
Remarks
Min.
4.5
3.0
3.0
2.7
2.7
Max.
5.5
Under normal operation
3.6
Under normal operation
EVA
VCC3
V
FLASH
Power voltage
3.6
RAM status kept in the case of stop
Under normal operation
3.6
V
V
V
V
MASK
ROM
VCC3
3.6
RAM status kept in the case of stop
Analog power voltage
AVCC
VSS + 4.5
VSS + 5.5
AVCC
Standard analog voltage
AVRH
AVSS − 0.3
In external ROM external bus /
internal ROM external bus modes
TA
0
+70
+70
°C
°C
Operating temperature
TA
−40
In single-chip mode
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
89
MB91133/MB91F133
3. DC Characteristics
(MASK Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
(FLASH Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
Value
Sym-
bol
Re-
marks
Parameter
Pin name
Conditions
Unit
Min.
Typ.
Max.
Input excluding
following (*1)
VIH
VIHS
VIL
0.7 VCC5
VCC5 + 0.3
V
V
“H” level input
voltage
*1 Hysteresis
input pin
VCC5 − 0.4
VSS − 0.3
VSS − 0.3
2.6
VCC5 + 0.3
0.2 VCC5
VSS + 0.4
Input excluding
following (*1)
V
“L” level input
voltage
*1 Hysteresis
input pin
VILS
VOH
VOL
ILI
V
“H” level output
voltage
VCC5 = 5.0 V,
IOH = −4.0 mA
V
“L” level output
voltage
VCC5 = 5.0 V,
IOL = 4.0 mA
0.6
5
V
Input leak
current
VCC5 = 5.0 V,
VSS < VI < VDD
− 5
µA
kΩ
Pull up
resistance value
RPULL
RST
50
ICC5
ICC3
VCC5
VCC3
VCC5
VCC3
VCC5 = 5.0 V
VCC3 = 3.0 V
VCC5 = 5.0 V
VCC3 = 3.0 V
15
50
15
24
20
100
20
mA *2
mA
ICCS5
ICCS3
mA *2
mA
85
Power current
VCC5 = 5.0 V,
TA = 25 °C
ICCH5
VCC5
VCC3
10
10
100
100
µA *3
µA
VCC3 = 3.0 V,
TA = 25 °C
ICCH3
Power current
(FLASH
models)
ICC3
VCC3
VCC3
VCC3 = 3.3 V
VCC3 = 3.3 V
80
50
120
90
mA
mA
ICCS3
Other than VCC,
AVCC, AVSS,
Input capacity
CIN
10
pF
AVRH and VSS
*1 : Refer to “PIN FUNCTION DESCRIPTIONS”
*2 : In case of CLK pin output only (CL = 80 pF)
*3 : Output pin OPEN
90
MB91133/MB91F133
4. AC Characteristics
(1) Clock Timing Standard
(MASK Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
(FLASH Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
Value
Sym-
bol
Condi-
tions
Parameter
Pin name
Unit
Remarks
Min.
Max.
Clock frequency
(high-speed, self-oscillation)
Self oscillation
available area
fC
X0, X1
9
16.5
MHz
Clock frequency
(high-speed, PLL usage)
PLL usable area by
self-oscillation input
Clock frequency (low-speed)
Clock cycle time
fCA
tC
X0A, X1A
32
kHz Self oscillation
ns
30.3
31250
10
Frequency fluctuation rate *1
(when PLL locked)
∆f
fCP
%
CPU
system
0.032
0.032
33
25
Bus
fCPB
Internal operation
system
MHz
clock frequency
Excluding analog
area*2
0.032
1
25
25
Peripheral
system
fCPP
Analog area*2
CPU
system
tCP
30.3
31250
Bus
tCPB
40
31250
Internal operation
system
ns
clock cycle time
Excluding analog
area*2
40
40
31250
1000
Peripheral
system
tCPP
Analog area *2
*1 : Frequency fluctuation rate indicates the maximum fluctuation ratio from the setting central frequency during
locking in case of doubling.
*2 : The targeted analog areas are the A/D and level comparator.
91
MB91133/MB91F133
−α
Central frequency fO
−α
| α |
fO
∆f =
×100 (%)
tC
VCC3
0.8 VCC3
0.2 VCC3
VSS
Peripheral system clock setting permitted area (A/D, D/A level comparator : 5 V ± 10%)
< FLASH model >
< MASK ROM model >
VCC3
VCC3
3.6
Guaranteed operating range
Guaranteed operating range
3.6
3.0
fCP
fCP
2.7
fCPP
fCPP
32 K1 M
25 M 33 M
32 K1 M
25 M 33 M
Frequency (Hz)
Frequency (Hz)
92
MB91133/MB91F133
The relationship between the internal clock set by the CHC/CCK1/CCK0 bit of the Gear Control Register (GCR)
and X0 input is as follows.
X0 input
• Original oscillation × 1
(CHC bit of GCR : 0 setting)
tCYC
(a) Gear × 1 Internal clock
CCK1/0 : 00
tCYC
(b) Gear × 1/2 Internal clock
CCK1/0 : 01
tCYC
(c) Gear × 1/4 Internal clock
CCK1/0 : 10
tCYC
(d) Gear × 1/8 Internal clock
CCK1/0 : 11
• Original oscillation × 1/2
(CHC bit of GCR : 1 setting)
tCYC
(a) Gear × 1 Internal clock
CCK1/0 : 00
tCYC
(b) Gear × 1/2 Internal clock
CCK1/0 : 01
tCYC
(c) Gear × 1/4 Internal clock
CCK1/0 : 10
tCYC
(d) Gear × 1/8 Internal clock
CCK1/0 : 11
93
MB91133/MB91F133
(2) Reset Input Standards
(MASK Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
(FLASH Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
Value
Pin
name
Condi-
tions
Parameter
Reset input time
Symbol
Unit
Remarks
Min.
Max.
tRSTL
RST
tCP × 5
ns
tRSTL
RST
0.2 VCC
(3) Power On Reset
(MASK Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
(FLASH Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
Value
Sym-
bol
Pin
name
Parameter
Conditions
Unit
Remarks
Min.
Max.
Power startup time
Power cut time
fR
20
ms
ms
VCC
tOFF
2
Waiting time for oscillation
stabilization
tOSC
213 tC
ns
tR
tOFF
0.9 × VCC3
VhhR
0.2 V
If the power voltage is changed rapidly, “Power On Reset” may be initiated. To start up smoothly,
controlling any voltage fluctuations that may occur during operation is recommended.
VCC
Controling inclination at initiation to 50
Holding RAM data
mV/ms or less is recommended.
VSS
VCC
tOSC (waiting for oscillation stabilization)
RST
When power is turned on, start while the RST pin
is set to “L” level, after which wait for tRSTL minutes
and change the level to “H” once the VCC power
level is reached.
tRSTL
94
MB91133/MB91F133
(4) Serial I/O (CH0 to 4)
(MASK Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
(FLASH Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
Value
Pin
Parameter
Symbol
Conditions
Unit Remarks
name
Min.
Max.
Serial clock cycle time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
tBUSY
tCLZO
tCLSL
tCHOZ
8 tCPP
ns
ns
ns
ns
SCK ↓ → SO delay time
Valid SI → SCK ↑
−10
50
Internal
clock
50
SCK ↑ → Valid SI holding time
Serial clock H pulse width
Serial clock L pulse width
SCK ↓ → SO delay time
Valid SI → SCK ↑
50
4 tCPP − 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
*
4 tCPP − 10
0
50
50
50
External
clock
SCK ↑ → Valid SI holding time
Serial busy period
6 tCPP
50
SCS ↓ → SCK, SO delay time
SCS ↓ → SCK input MASK time
SCS ↑ → SCK, SO Hi-Z time
3 tCPP
50
*: Will be Min. 1 tCPP − 10 if pre-scalar setting is CS2, 1, 0 = 000.
Internal shift clock mode
tSCYC
SCK
tSLOV
SO
SI
tSHIX
tIVSH
External shift clock mode
tCLZO
tSLSH
tSHSL
tBUSY
tCHOZ
SCK
tSLOV
SO
SI
tIVSH
tSHIX
SCS
tCLSL
95
MB91133/MB91F133
(5) External Bus Measurement Conditions
The following conditions apply to items without specific regulations.
• Alternating current standard measurement condition
VCC : 5.0 V ± 10%
Input
Output
VOH
VCC
VIH
VIL
VIH
VIL
2.4 V VOH 2.4V
0.8 V VOL 0.8V
VOL
0 V
(Rise/fall time of input is 10 ns or less)
• Load condition
Output pin
C = 50 pF
( VCC : 5.0 V ± 10% )
• Load capacity − Delay time characteristic (Internally-based output delay)
[nS]
35
30
25
20
15
10
5
5 V Fall
5 V Rise
0
0
20
40
50
60
80
100
120
C[pF]
96
MB91133/MB91F133
(6) Normal Bus Access Read/Write Operation
(MASK Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
(FLASH Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
Value
Sym-
bol
Parameter
Pin name Conditions
Unit Remarks
Min.
Max.
CLK
A23 to A00
Address delay time
tCHAV
15
ns
ns
CLK
D31 to D16
Data delay time
tCHDV
15
RD delay time
tCLRL
tCLRH
tCLWL
tCLWH
10
10
10
10
ns
ns
ns
ns
CLK
RD
RD delay time
WR0 to 1 delay time
WR0 to 1 delay time
CLK
WR0 to 1
A23 to A00
D31 to D16
3 / 2 ×
tCYC − 25
Valid address / valid data input time tAVDV
ns *1, *2
RD ↓ → valid data input time
Data setup → RD ↑ time
RD ↑ → Data holding time
tRLDV
tDSRH
tRHDX
tCYC − 15
ns *1
ns
RD
D31 to D16
15
0
ns
*1 : Time (tCYC × number of cycles extended) needs to be added to this standard if the bus is extended by automatic
waiting insertion and RDY input.
*2 : Values of this standard are in case of gear cycle × 1.
If the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing
n with 1/2, 1/4 or 1/8.
• Calculation formula : (2 − n / 2) × tCYC − 25
97
MB91133/MB91F133
tCYC
BA1
BA2
VOH
VOH
VOL
CLK
VOL
tCHAV
VOH
VOL
VOH
VOL
A24 - A00
tCLRL
VOL
tCLRH
VOH
RD
tRLDV
tRHDX
tAVDV
tDSRH
VIH
VIH
VIL
D31 - D16
WR0 - WR1
D31 - D16
Read
VIL
tCLWL
VOL
tCLWH
VOH
tCHDV
VOH
VOL
VOH
VOL
Write
98
MB91133/MB91F133
(7) Ready Input Timing
(MASK Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
(FLASH Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Min.
Max.
RDY
CLK
RDY setup time → CLK ↓
CLK ↓ → RDY holding time
tRDYS
15
ns
ns
RDY
CLK
tRDYH
0
tCYC
VOH
VOH
CLK
VOL
VOL
tRDYH
tRDYS tRDYH
tRDYS
RDY
If "wait" is
executed
VIH
VIL
RDY
If "wait" is
not executed
VIH
VIL
99
MB91133/MB91F133
(8) Holding timing
(MASK Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
(FLASH Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Min.
Max.
BGRNT delay time
tCHBGL
tCHBGH
tXHAL
6
6
ns
ns
ns
ns
CLK
BGRNT
BGRNT delay time
Pin floating → BGRNT ↓ time
BGRNT ↑ → Pin valid time
tCYC − 10 tCYC + 10
tCYC − 10 tCYC + 10
BGRNT
tHAHV
Note : It takes at least one cycle from loading the BRQ to when BGRNT is changed.
tcyc
VOH
VOH
VOH
VOH
CLK
BRQ
tCHBGL
tCHBGH
VOH
BGRNT
VOL
tHAHV
tXHAL
Each pin
High impedance
100
MB91133/MB91F133
(9) DMA Controller Timing
(MASK Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
(FLASH Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
Value
Parameter
Symbol
Pin name
Conditions
Unit Remarks
Min.
Max.
DREQ input pulse width
tDRWH
tCLDL
tCLDH
tCLEL
tCLEH
tCHDL
tCHDH
tCHEL
tCHEH
DREQ0 to DREQ2
2 tCYC
ns
ns
ns
ns
ns
6
6
6
6
DACK delay time
(Normal bus)
CLK
DACK0 to DACK2
EOP delay time
(Normal bus)
CLK
EOP0 to EOP2
n / 2 × tCYC ns
ns
n / 2 × tCYC ns
ns
CLK
DACK delay time
EOP delay time
DACK0 to DACK2
6
CLK
EOP0 to EOP2
6
tcyc
VOH
VOH
CLK
VOL
VOL
tCLDH
tCLDL
tCLEL
tCLEH
DACK0 - 2
EOP0 - 2
(Normal bus)
VOH
VOL
tCHDH
VOH
DACK0 - 2
EOP0 - 2
tCHDL
tCHEL
VOL
tDRWH
VIH
VIH
DREQ0 - 2
101
MB91133/MB91F133
5. A/D Transition
(MASK Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
(FLASH Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
Value
Sym-
bol
Pin
name
Re-
marks
Parameter
Resolution
Conditions
Unit
Min.
Typ.
Max.
10
Bit
µs
Conversion time
Total tolerance
5.0
−4.0
−3.5
4.0
3.5
LSB
LSB
Straight-line tolerance
AVCC = 5.0 V,
AVRH = 5.0 V
Differential straight-line
tolerance
−2.0
2.0
LSB
AN0 to
AN7
Zero transition tolerance
VOT
VFST
IAIN
AVSS−1.5 AVSS+0.5 AVSS+2.5 LSB
AVRH − 5.5 AVRH − 1.5 AVRH + 0.5 LSB
AVCC = 5.0 V,
AVRH = 5.0 V
Full-scale transition
tolerance
AN0 to
AN7
AN0 to
AN7
Analog input current
Analog input voltage
0.1
10
µA
AN0 to
AN7
VAIN
AVRH
IA
AVSS
AVRH
AVCC
5.0
V
V
Standard voltage
When conversion
AVRH
3.0
2.0
mA
is activated
Power
current
AVCC
AVCC = 5.0 V
When conversion
is stopped
IAH
IR
5.0
3.0
10
4
µA
mA
µA
When conversion
is activated
Standard
voltage
current
AVCC = 5.0 V,
AVRH = 5.0V
AVRH
When conversion
is stopped
IRH
supplied
Tolerance between
channels
AN0 to
AN7
LSB
Notes : • As the |AVRH| becomes smaller, the tolerance becomes larger.
• Output impedance of external circuits other than analog input must be used if output impedance of external
circuits < approx. 7 kΩ
If the output impedance of the external circuits is too high, the sampling time for the analog voltage may
be insufficient.
(Sampling time = 1.6 µs at 33 MHz)
102
MB91133/MB91F133
• Definition of A/D Converter Terms
• Resolution :
Analog changes that can be identified by A/D converter
• Straight-line tolerance :
Difference between the straight line linking the zero transition point (00 0000 0000 ←→ 00 0000 0001) to the
full-scale transition point (11 1111 1110 ←→ 11 1111 1111) and actual conversion characteristics.
• Differential straight-line tolerance :
Difference compared to the ideal input voltage value required to change the output code 1 LSB
• Total tolerance :
Indicates the difference between the actual and theoretical values and includes zero transition tolerance, full-
scale transition tolerance, and straight-line tolerance.
Total tolerance
3FF
1.5 LSB
3FE
3FD
Actual conversion
characteristics
{1 LSB ( N − 1 ) + 0.5 LSB}
004
003
002
001
VNT
(Actual
measured value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVRH
AVSS
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB’}
Total tolerance of digital output N =
1 LSB
AVRH − AVSS
1 LSB (Ideal value) =
[V]
[V]
VFST (Ideal value) = AVRH − 1.5 LSB’ [V]
1024
VOT (Ideal value) = AVSS + 0.5 LSB’
VNT : Voltage of digital output transferred from (N + 1) to N
(Continued)
103
MB91133/MB91F133
(Continued)
Straight-line tolerance
Differential straight-line tolerance
3FF
Actual conversion
characteristics
Actual conversion
characteristics
3FE
N + 1
{1 LSB ( N − 1 ) + VOT}
VFST
3FD
(Actual
measured
value)
Ideal characteristics
N
004
003
002
001
VNT
(Actual
measured value)
N − 1
VFST
(Actual
measured
value)
Actual conversion
characteristics
Ideal characteristics
VNT
(Actual
measured value)
N − 2
Actual conversion
characteristics
VOT
(Actual measured value)
AVSS
AVSS
AVRH
AVRH
Analog input
Analog input
VNT − {1 LSB × (N − 1) + VOT}
Straight-linetolerance
of digital output N
=
=
[LSB]
[LSB]
1 LSB
Differentialstraight-linetolerance
of digital output N
V (N + 1) T − VNT
−1
1 LSB
VFST − VOT
[V]
1LSB (Ideal value) =
1022
VOT : Voltage with digital output transferred from (000) H to (001) H
VFST : Voltage with digital output transferred from (3FE) H to (3FF) H
6. D/A Transition
(MASK Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
(FLASH Model VCC5 = AVCC = DAVC = 5.0 V ± 10%, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to +70 °C)
Value
Pin
name
Condi-
tions
Re-
marks
Parameter
Symbol
Unit
Min.
Typ.
Max.
8
Resolution
Bit
LSB
µs
Differential straight-line tolerance
Conversion time
±0.9
20
10
28
*
Analog output impedance
kΩ
*: CL = 20 PF
104
MB91133/MB91F133
■ INSTRUCTIONS (165 INSTRUCTIONS)
1. How to Read Instruction Set Summary
Mnemonic
Type
OP
CYC
NZVC
Operation
Remarks
ADD Rj,
* ADD #s5, Ri
Ri
A
C
,
A6
A4
,
1
1
,
CCCC
CCCC
Ri + Rj → Ri
Ri + s5 → Ri
,
,
,
,
,
,
,
,
,
↓
(1)
↓
(2)
↓
(3)
↓
(4)
↓
(5)
↓
(6)
↓
(7)
(1) Names of instructions
Instructions marked with * are not included in CPU specifications. These are extended instruction codes
added/extended at assembly language levels.
(2) Addressing modes specified as operands are listed in symbols.
Refer to “2. Addressing mode symbols” for further information.
(3) Instruction types
(4) Hexa-decimal expressions of instructions
(5) The number of machine cycles needed for execution
a: Memory access cycle and it has possibility of delay by Ready function.
b: Memory access cycle and it has possibility of delay by Ready function.
If an object register in a LD operation is referenced by an immediately following instruction, the interlock
function is activated and number of cycles needed for execution increases.
c: If an immediately following instruction operates to an object of R15, SSP or USP in read/write mode or
if the instruction belongs to instruction format A group, the interlock function is activated and number of
cycles needed for execution increases by 1 to make the total number of 2 cycles needed.
d: If an immediately following instruction refers to MDH/MDL, the interlock function is activated and number
of cycles needed for execution increases by 1 to make the total number of 2 cycles needed.
For a, b, c and d, minimum execution cycle is 1.
(6) Change in flag sign
• Flag change
C : Change
– : No change
0 : Clear
1 : Set
• Flag meanings
N : Negative flag
Z : Zero flag
V : Over flag
C : Carry flag
(7) Operation carried out by instruction
105
MB91133/MB91F133
2. Addressing Mode Symbols
Ri
: Register direct (R0 to R15, AC, FP, SP)
Rj
: Register direct (R0 to R15, AC, FP, SP)
R13
Ps
: Register direct (R13, AC)
: Register direct (Program status register)
Rs
: Register direct (TBR, RP, SSP, USP, MDH, MDL)
: Register direct (CR0 to CR15)
: Register direct (CR0 to CR15)
CRi
CRj
#i8
: Unsigned 8-bit immediate (–128 to 255)
Note: –128 to –1 are interpreted as 128 to 255
: Unsigned 20-bit immediate (–0X80000 to 0XFFFFF)
Note: –0X7FFFF to –1 are interpreted as 0X7FFFF to 0XFFFFF
: Unsigned 32-bit immediate (–0X80000000 to 0XFFFFFFFF)
Note: –0X80000000 to –1 are interpreted as 0X80000000 to 0XFFFFFFFF
: Signed 5-bit immediate (–16 to 15)
#i20
#i32
#s5
#s10
#u4
: Signed 10-bit immediate (–512 to 508, multiple of 4 only)
: Unsigned 4-bit immediate (0 to 15)
#u5
: Unsigned 5-bit immediate (0 to 31)
#u8
: Unsigned 8-bit immediate (0 to 255)
#u10
: Unsigned 10-bit immediate (0 to 1020, multiple of 4 only)
: Unsigned 8-bit direct address (0 to 0XFF)
@dir8
@dir9
@dir10
label9
label12
label20
label32
@Ri
: Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only)
: Unsigned 10-bit direct address (0 to 0X3FC, multiple of 4 only)
: Signed 9-bit branch address (–0X100 to 0XFC, multiple of 2 only)
: Signed 12-bit branch address (–0X800 to 0X7FC, multiple of 2 only)
: Signed 20-bit branch address (–0X80000 to 0X7FFFF)
: Signed 32-bit branch address (–0X80000000 to 0X7FFFFFFF)
: Register indirect (R0 to R15, AC, FP, SP)
@Rj
: Register indirect (R0 to R15, AC, FP, SP)
@(R13, Rj)
: Register relative indirect (Rj: R0 to R15, AC, FP, SP)
@(R14, disp10) : Register relative indirect (disp10: –0X200 to 0X1FC, multiple of 4 only)
@(R14, disp9) : Register relative indirect (disp9: –0X100 to 0XFE, multiple of 2 only)
@(R14, disp8) : Register relative indirect (disp8: –0X80 to 0X7F)
@(R15, udisp6) : Register relative (udisp6: 0 to 60, multiple of 4 only)
@Ri+
: Register indirect with post-increment (R0 to R15, AC, FP, SP)
@R13+
@SP+
@–SP
(reglist)
: Register indirect with post-increment (R13, AC)
: Stack pop
: Stack push
: Register list
106
MB91133/MB91F133
3. Instruction Types
MSB
LSB
16 bits
Type A
OP
8
Rj
4
Ri
4
Type B
Type C
Type *C’
Type D
Type E
Type F
OP
4
i8/o8
8
Ri
4
OP
8
u4/m4
4
Ri
4
ADD, ADDN, CMP, LSL, LSR and ASR instructions only
OP
7
s5/u5
5
Ri
4
OP
u8/rel8/dir/reglist
8
8
OP
8
SUB-OP
Ri
4
4
OP
5
rel11
11
107
MB91133/MB91F133
4. Detailed Description of Instructions
• Add/subtract operation instructions (10 instructions)
Type
Mnemonic
OP Cycle N Z V C
Operation
Remarks
ADD
* ADD
Rj, Ri
#s5, Ri
A
C’
A6
A4
1
1
C C C C Ri + Rj → Ri
C C C C Ri + s5 → Ri
MSB is interpreted as
a sign in assembly
language
ADD
ADD2
#i4, Ri
#i4, Ri
C
C
A4
A5
1
1
C C C C Ri + extu (i4) → Ri
C C C C Ri + extu (i4) → Ri
Zero-extension
Sign-extension
ADDC
Rj, Ri
A
A7
1
C C C C Ri + Rj + c → Ri
Add operation with
sign
ADDN
* ADDN #s5, Ri
Rj, Ri
A
C’
A2
A0
1
1
– – – – Ri + Rj → Ri
– – – – Ri + s5 → Ri
MSB is interpreted as
a sign in assembly
language
ADDN
ADDN2 #i4, Ri
#i4, Ri
C
C
A0
A1
1
1
– – – – Ri + extu (i4) → Ri
– – – – Ri + extu (i4) → Ri
Zero-extension
Sign-extension
SUB
Rj, Ri
Rj, Ri
A
A
AC
AD
1
1
C C C C Ri – Rj → Ri
SUBC
C C C C Ri – Rj – c → Ri
Subtract operation with
carry
SUBN
Rj, Ri
A
AE
1
– – – – Ri – Rj → Ri
• Compare operation instructions (3 instructions)
Type
Mnemonic
OP Cycle N Z V C
Operation
Remarks
CMP
* CMP
Rj, Ri
#s5, Ri
A
C’
AA
A8
1
1
C C C C Ri – Rj
C C C C Ri – s5
MSB is interpreted as
a sign in assembly
language
CMP
CMP2
#i4, Ri
#i4, Ri
C
C
A8
A9
1
1
C C C C Ri + extu (i4)
C C C C Ri + extu (i4)
Zero-extension
Sign-extension
• Logical operation instructions (12 instructions)
Type
Mnemonic
OP Cycle N Z V C
Operation
Remarks
AND
AND
ANDH
ANDB
Rj, Ri
A
A
A
A
82 C C – – Ri & = Rj
1
Word
Word
Half word
Byte
Rj, @Ri
Rj, @Ri
Rj, @Ri
84 1 + 2a C C – – (Ri) & = Rj
85 1 + 2a C C – – (Ri) & = Rj
86 1 + 2a C C – – (Ri) & = Rj
OR
OR
ORH
ORB
Rj, Ri
A
A
A
A
92
1
C C – – Ri | = Rj
Word
Word
Half word
Byte
Rj, @Ri
Rj, @Ri
Rj, @Ri
94 1 + 2a C C – – (Ri) | = Rj
95 1 + 2a C C – – (Ri) | = Rj
96 1 + 2a C C – – (Ri) | = Rj
EOR
EOR
EORH
EORB
Rj, Ri
A
A
A
A
9A
1
C C – – Ri ^ = Rj
Word
Word
Half word
Byte
Rj, @Ri
Rj, @Ri
Rj, @Ri
9C 1 + 2a C C – – (Ri) ^ = Rj
9D 1 + 2a C C – – (Ri) ^ = Rj
9E 1 + 2a C C – – (Ri) ^ = Rj
108
MB91133/MB91F133
• Bit manipulation arithmetic instructions (8 instructions)
Type
Mnemonic
OP Cycle N Z V C
Operation
Remarks
BANDL #u4, @Ri
C
80 1 + 2a – – – – (Ri) & = (F0H + u4)
Manipulate lower 4 bits
(u4: 0 to 0FH)
BANDH #u4, @Ri
(u4: 0 to 0FH)
* BAND #u8, @Ri
C
81 1 + 2a – – – – (Ri) & = ((u4<<4) + 0FH) Manipulate upper 4 bits
– – – – (Ri) & = u8
1
2
3
–
*
*
*
BORL
BORH
* BOR
#u4, @Ri
(u4: 0 to 0FH)
#u4, @Ri
(u4: 0 to 0FH)
#u8, @Ri
C
C
90 1 + 2a – – – – (Ri) | = u4
Manipulate lower 4 bits
Manipulate upper 4 bits
91 1 + 2a – – – – (Ri) | = (u4<<4)
–
– – – – (Ri) | = u8
BEORL #u4, @Ri
(u4: 0 to 0FH)
BEORH #u4, @Ri
(u4: 0 to 0FH)
* BEOR #u8, @Ri
C
C
98 1 + 2a – – – – (Ri) ^ = u4
Manipulate lower 4 bits
Manipulate upper 4 bits
99 1 + 2a – – – – (Ri) ^ = (u4<<4)
–
– – – – (Ri) ^ = u8
BTSTL
BTSTH
#u4, @Ri
(u4: 0 to 0FH)
#u4, @Ri
C
C
88
89
2 + a 0 C – – (Ri) & u4
Test lower 4 bits
Test upper 4 bits
2 + a C C – – (Ri) & (u4<<4)
(u4: 0 to 0FH)
*1: Assembler generates BANDL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates
BANDH if “u8&0xF0” leaves an active bit. Depending on the value in the “u8” format, both BANDL and BANDH
may be generated.
*2: Assembler generates BORL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates
BORH if “u8&0xF0” leaves an active bit.
*3: Assembler generates BEORL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates
BEORH if “u8&0xF0” leaves an active bit.
• Add/subtract operation instructions (10 instructions)
Type
Mnemonic
OP Cycle N Z V C
Operation
Remarks
MUL
MULU
MULH
Rj, Ri
Rj, Ri
Rj, Ri
A
A
A
A
AF
AB
BF
BB
5
5
3
3
C C C – Rj × Ri → MDH, MDL
C C C – Rj × Ri → MDH, MDL
C C – – Rj × Ri → MDL
32-bit × 32-bit = 64-bit
Unsigned
16-bit × 16-bit = 32-bit
Unsigned
MULUH Rj, Ri
C C – – Rj × Ri → MDL
DIVOS
DIVOU
DIV1
DIV2
DIV3
DIV4S
* DIV
Ri
Ri
Ri
Ri
E
E
E
E
E
E
97 – 4
97 – 5
97 – 6
97 – 7
9F – 6
9F – 7
1
1
d
1
1
1
–
– – – –
– – – –
– C – C
– C – C
– – – –
– – – –
– C – C MDL/Ri → MDL,
MDL%Ri → MDH
– C – C MDL/Ri → MDL,
MDL%Ri → MDH
Step calculation
32-bit/32-bit = 32-bit
1
2
Ri
Ri
*
*
–
Unsigned
* DIVU
*1: DIVOS, DIV1 × 32, DIV2, DIV3 and DIV4S are generated. A total instruction code length of 72 bytes.
*2: DIVOU and DIV1 × 32 are generated. A total instruction code length of 66 bytes.
109
MB91133/MB91F133
• Shift arithmetic instructions (9 instructions)
Type
Mnemonic
OP Cycle N Z V C
Operation
Remarks
Logical shift
LSL
* LSL
LSL
Rj, Ri
A
C’
C
B6
B4
B4
B5
1
1
1
1
C C – C Ri<<Rj → Ri
#u5, Ri
#u4, Ri
#u4, Ri
C C – C Ri<<u5 → Ri
C C – C Ri<<u4 → Ri
C C – C Ri<<(u4 + 16) → Ri
LSL2
C
LSR
* LSR
LSR
Rj, Ri
A
C’
C
B2
B0
B0
B1
1
1
1
1
C C – C Ri>>Rj → Ri
C C – C Ri>>u5 → Ri
C C – C Ri>>u4 → Ri
C C – C Ri>>(u4 + 16) → Ri
Logical shift
Logical shift
#u5, Ri
#u4, Ri
#u4, Ri
LSR2
C
ASR
* ASR
ASR
Rj, Ri
A
C’
C
BA
B8
B8
B9
1
1
1
1
C C – C Ri>>Rj → Ri
C C – C Ri>>u5 → Ri
C C – C Ri>>u4 → Ri
C C – C Ri>>(u4 + 16) → Ri
#u5, Ri
#u4, Ri
#u4, Ri
ASR2
C
• Immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer
instruction) (3 instructions)
Type
Mnemonic
OP Cycle N Z V C
Operation
Remarks
LDI: 32
LDI: 20
#i32, Ri
#i20, Ri
E
C
9F – 8
9B
3
2
– – – – i32 → Ri
– – – – i20 → Ri
– – – – i8 → Ri
Upper 12 bits are zero-
extended
Upper 24 bits are zero-
extended
LDI: 8
* LDI
#i8, Ri
# {i8 | i20 | i32}, Ri
B
C0
1
{i8 | i20 | i32} → Ri
1
*
*1: If an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection.
If an immediate value contains relative value or external reference, assembler selects i32.
• Memory load instructions (13 instructions)
Type
Mnemonic
OP Cycle N Z V C
Operation
Remarks
LD
LD
LD
LD
LD
LD
@Rj, Ri
A
A
B
C
E
E
04
00
20
03
07 – 0
07 – 8
b
b
b
b
b
b
– – – – (Rj) → Ri
– – – – (R13 + Rj) → Ri
– – – – (R14 + disp10) → Ri
– – – – (R15 + udisp6) → Ri
– – – – (R15) → Ri, R15 + = 4
– – – – (R15) → Rs, R15 + = 4 Rs: Special-purpose
register
@(R13, Rj), Ri
@(R14, disp10), Ri
@(R15, udisp6), Ri
@R15 +, Ri
@R15 +, Rs
1 + a + b
LD
@R15 +, PS
E
07 – 9
C C C C (R15) → PS, R15 + = 4
LDUH
LDUH
LDUH
@Rj, Ri
@(R13, Rj), Ri
@(R14, disp9), Ri
A
A
B
05
01
40
b
b
b
– – – – (Rj) → Ri
– – – – (R13 + Rj) → Ri
– – – – (R14 + disp9) → Ri
Zero-extension
Zero-extension
Zero-extension
LDUB
LDUB
LDUB
@Rj, Ri
@(R13, Rj), Ri
@(R14, disp8), Ri
A
A
B
06
02
60
b
b
b
– – – – (Rj) → Ri
– – – – (R13 + Rj) → Ri
– – – – (R14 + disp8) → Ri
Zero-extension
Zero-extension
Zero-extension
Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler
description from disp8 to disp10 are as follows:
disp8 → o8 = disp8:Each disp is a code extension.
disp9 → o8 = disp9>>1:Each disp is a code extension.
disp10 → o8 = disp10>>2:Each disp is a code extension.
udisp6 → u4 = udisp6>>2:udisp4 is a 0 extension.
110
MB91133/MB91F133
• Memory store instructions (13 instructions)
Type
Mnemonic
OP Cycle N Z V C
Operation
Remarks
ST
ST
ST
ST
ST
ST
Ri, @Rj
A
A
B
C
E
E
14
10
30
13
17 – 0
17 – 8
a
a
a
a
a
a
– – – – Ri → (Rj)
– – – – Ri → (R13 + Rj)
– – – – Ri → (R14 + disp10)
– – – – Ri → (R15 + usidp6)
– – – – R15 – = 4, Ri → (R15)
– – – – R15 – = 4, Rs → (R15) Rs: Special-purpose
register
Word
Word
Word
Ri, @(R13, Rj)
Ri, @(R14, disp10)
Ri, @(R15, udisp6)
Ri, @–R15
Rs, @–R15
ST
PS, @–R15
E
17 – 9
a
– – – – R15 – = 4, PS → (R15)
STH
STH
STH
Ri, @Rj
Ri, @(R13, Rj)
Ri, @(R14, disp9)
A
A
B
15
11
50
a
a
a
– – – – Ri → (Rj)
– – – – Ri → (R13 + Rj)
– – – – Ri → (R14 + disp9)
Half word
Half word
Half word
STB
STB
STB
Ri, @Rj
Ri, @(R13, Rj)
Ri, @(R14, disp8)
A
A
B
16
12
70
a
a
a
– – – – Ri → (Rj)
– – – – Ri → (R13 + Rj)
– – – – Ri → (R14 + disp8)
Byte
Byte
Byte
Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler
description from disp8 to disp10 are as follows:
disp8 → o8 = disp8:Each disp is a code extension.
disp9 → o8 = disp9>>1:Each disp is a code extension.
disp10 → o8 = disp10>>2:Each disp is a code extension.
udisp6 → u4 = udisp6>>2:udisp4 is a 0 extension.
• Transfer instructions between registers/special-purpose registers transfer instructions
(5 instructions)
Type
Mnemonic
OP Cycle N Z V C
Operation
Remarks
MOV
Rj, Ri
A
8B
1
– – – – Rj → Ri
Transfer between
general-purpose
registers
MOV
MOV
Rs, Ri
Ri, Rs
A
A
B7
B3
1
1
– – – – Rs → Ri
– – – – Ri → Rs
Rs: Special-purpose
register
Rs: Special-purpose
register
MOV
MOV
PS, Ri
Ri, PS
E
E
17 – 1
07 – 1
1
c
– – – – PS → Ri
C C C C Ri → PS
111
MB91133/MB91F133
• Non-delay normal branch instructions (23 instructions)
Type
E
Mnemonic
@Ri
OP Cycle N Z V C
Operation
Remarks
JMP
97 – 0
D0
2
2
– – – – Ri → PC
– – – – PC + 2 → RP,
CALL
label12
F
PC + 2 + rel11 × 2 → PC
– – – – PC + 2 → RP, Ri → PC
CALL
RET
INT
@Ri
E
E
D
97 – 1
97 – 2
1F
2
2
– – – – RP → PC
Return
#u8
3+3a – – – – SSP – = 4, PS → (SSP),
SSP – = 4,
PC + 2 → (SSP),
0 → I flag,
0 → S flag,
(TBR + 3FC – u8 × 4) → PC
INTE
RETI
E
E
9F – 3 3 + 3a – – – – SSP – = 4, PS → (SSP),
SSP – = 4,
For emulator
PC + 2 → (SSP),
0 → S flag,
(TBR + 3D8 – u8 × 4) → PC
97 – 3 2 + 2a C C C C (R15) → PC, R15 – = 4,
(R15) → PS, R15 – = 4
BNO
BRA
BEQ
BNE
BC
BNC
BN
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
E1
E0
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
1
2
– – – – Non-branch
– – – – PC + 2 + rel8 × 2 → PC
– – – – PCif Z = = 1
– – – – PCif Z = = 0
– – – – PCif C = = 1
– – – – PCif C = = 0
– – – – PCif N = = 1
– – – – PCif N = = 0
– – – – PCif V = = 1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
BP
BV
BNV
BLT
BGE
BLE
BGT
BLS
BHI
– – – – PCif V = = 0
– – – – PCif V xor N = = 1
– – – – PCif V xor N = = 0
– – – – PCif (V xor N) or Z = = 1
– – – – PCif (V xor N) or Z = = 0
– – – – PCif C or Z = = 1
– – – – PCif C or Z = = 0
Notes: • “2/1” in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch.
• The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and
assembler discription label9 and label12 are as follows.
label9 → rel8 = (label9 – PC – 2)/2
label12 → rel11 = (label12 – PC – 2)/2
• RETI must be operated while S flag = 0.
112
MB91133/MB91F133
• Branch instructions with delays (20 instructions)
Type
E
Mnemonic
OP Cycle N Z V C
Operation
– – – – Ri → PC
– – – – PC + 4 → RP,
Remarks
JMP:D
@Ri
9F – 0
D8
1
1
CALL:D label12
F
PC + 2 + rel11 × 2 → PC
– – – – PC + 4 → RP, Ri → PC
CALL:D @Ri
RET:D
E
E
9F – 1
9F – 2
1
1
– – – – RP → PC
Return
BNO:D
BRA:D
BEQ:D
BNE:D
BC:D
BNC:D
BN:D
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
F1
F0
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
– – – – Non-branch
– – – – PC + 2 + rel8 × 2 → PC
– – – – PCif Z = = 1
– – – – PCif Z = = 0
– – – – PCif C = = 1
– – – – PCif C = = 0
– – – – PCif N = = 1
– – – – PCif N = = 0
– – – – PCif V = = 1
BP:D
BV:D
BNV:D
BLT:D
BGE:D
BLE:D
BGT:D
BLS:D
BHI:D
– – – – PCif V = = 0
– – – – PCif V xor N = = 1
– – – – PCif V xor N = = 0
– – – – PCif (V xor N) or Z = = 1
– – – – PCif (V xor N) or Z = = 0
– – – – PCif C or Z = = 1
– – – – PCif C or Z = = 0
Notes: • The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and
assembler discription label9 and label12 are as follows.
label9 → rel8 = (label9 – PC – 2)/2
label12 → rel11 = (label12 – PC – 2)/2
• Delayed branch operation always executes next instruction (delay slot) before making a branch.
• Instructions allowed to be stored in the delay slot must meet one of the following conditions. If the other
instruction is stored, this device may operate other operation than defined.
The instruction described “1” in the other cycle column than branch instruction.
The instruction described “a”, “b”, “c” or “d” in the cycle column.
113
MB91133/MB91F133
• Direct addressing instructions
Type
Mnemonic
OP Cycle N Z V C
Operation
Remarks
DMOV
DMOV
DMOV
DMOV
DMOV
DMOV
@dir10, R13
D
D
D
D
D
D
08
18
0C
1C
0B
1B
b
a
2a
2a
2a
2a
– – – – (dir10) → R13
– – – – R13 → (dir10)
– – – – (dir10) → (R13), R13 + = 4 Word
– – – – (R13) → (dir10), R13 + = 4 Word
– – – – R15 – = 4, (dir10) → (R15) Word
– – – – (R15) → (dir10), R15 + = 4 Word
Word
Word
R13,
@dir10
@dir10, @R13+
@R13+, @dir10
@dir10, @–R15
@R15+, @dir10
DMOVH @dir9, R13
D
D
D
D
09
19
0D
1D
b
a
2a
2a
– – – – (dir9) → R13
– – – – R13 → (dir9)
– – – – (dir9) → (R13), R13 + = 2 Half word
– – – – (R13) → (dir9), R13 + = 2 Half word
Half word
Half word
DMOVH R13,
@dir9
DMOVH @dir9, @R13+
DMOVH @R13+, @dir9
DMOVB @dir8, R13
D
D
D
D
0A
1A
0E
1E
b
a
2a
2a
– – – – (dir8) → R13
– – – – R13 → (dir8)
– – – – (dir8) → (R13), R13 + + Byte
– – – – (R13) → (dir8), R13 + + Byte
Byte
Byte
DMOVB R13,
@dir8
DMOVB @dir8, @R13+
DMOVB @R13+, @dir8
Note: The relations between the dir field of TYPE-D in the instruction format and the assembler description from
disp8 to disp10 are as follows:
disp8 → dir + disp8:Each disp is a code extension
disp9 → dir = disp9>>1:Each disp is a code extension
disp10 → dir = disp10>>2:Each disp is a code extension
• Resource instructions (2 instructions)
Type
Mnemonic
OP Cycle N Z V C
Operation
Remarks
LDRES @Ri+, #u4
C
BC
a
– – – – (Ri) → u4 resource
u4: Channel number
Ri + = 4
STRES #u4,
@Ri+
C
BD
a
– – – – u4 resource → (Ri)
u4: Channel number
Ri + = 4
• Co-processor instructions (4 instructions)
Type
Mnemonic
OP Cycle N Z V C
Operation
Remarks
COPOP #u4, #CC, CRj, CRi
COPLD #u4, #CC, Rj, CRi
COPST #u4, #CC, CRj, Ri
COPSV #u4, #CC, CRj, Ri
E
E
E
E
9F – C 2 + a – – – – Calculation
9F – D 1 + 2a – – – – Rj → CRi
9F – E 1 + 2a – – – – CRj → Ri
9F – F 1 + 2a – – – – CRj → Ri
No error traps
114
MB91133/MB91F133
• Other instructions (16 instructions)
Type
Mnemonic
OP Cycle N Z V C
Operation
Remarks
NOP
E
9F – A
1
– – – – No changes
ANDCCR #u8
ORCCR #u8
D
D
83
93
c
c
C C C C CCR and u8 → CCR
C C C C CCR or u8 → CCR
STILM
#u8
D
87
1
– – – – i8 → ILM
Set ILM immediate
value
1
D
A3
1
– – – – R15 + = s10
ADD SP instruction
ADDSP #s10
EXTSB Ri
EXTUB Ri
EXTSH Ri
EXTUH Ri
*
E
E
E
E
97 – 8
97 – 9
97 – A
97 – B
1
1
1
1
– – – – Sign extension 8 → 32 bits
– – – – Zero extension 8 → 32 bits
– – – – Sign extension 16 → 32 bits
– – – – Zero extension 16 → 32 bits
4
LDM0
LDM1
(reglist)
D
D
8C
8D
– – – – (R15) → reglist,
R15 increment
– – – – (R15) → reglist,
R15 increment
Load-multi R0 to R7
Load-multi R8 to R15
*
4
(reglist)
*
3
– – – – (R15 + +) → reglist,
Load-multi R0 to R15
Store-multi R0 to R7
* LDM
STM0
(reglist)
(reglist)
*
–
6
D
D
8E
8F
– – – – R15 decrement,
reglist → (R15)
– – – – R15 decrement,
reglist → (R15)
*
6
STM1
(reglist)
Store-multi R8 to R15
Store-multi R0 to R15
*
5
2
– – – – reglist → (R15 + +)
* STM2 (reglist)
ENTER #u10
*
*
–
D
0F
1+a – – – – R14 → (R15 – 4),
R15 – 4 → R14,
Entrance processing
of function
R15 – u10 → R15
LEAVE
E
A
9F – 9
8A
b
– – – – R14 + 4 → R15,
(R15 – 4) → R14
Exit processing of
function
XCHB
@Rj, Ri
2a
– – – – Ri → TEMP,
(Rj) → Ri,
For SEMAFO
management
Byte data
TEMP → (Rj)
*1: In the ADDSP instruction, the reference between u8 of TYPE-D in the instruction format and assembler
description s10 is as follows.
s10 → s8 = s10>>2
*2: In the ENTER instruction, the reference between i8 of TYPE-C in the instruction format and assembler
description u10 is as follows.
u10 → u8 = u10>>2
*3: If either of R0 to R7 is specified in reglist, assembler generates LDM0. If either of R8 to R15 is specified,
assembler generates LDM1. Both LDM0 and LDM1 may be generated.
*4: The number of cycles needed for execution of LDM0 (reglist) and LDM1 (reglist) is given by the following
calculation; a × (n – 1) + b + 1 when “n” is number of registers specified.
*5: If either of R0 to R7 is specified in reglist, assembler generates STM0. If either of R8 to R15 is specified,
assembler generates STM1. Both STM0 and STM1 may be generated.
*6: The number of cycles needed for execution of STM0 (reglist) and STM1 (reglist) is given by the following
calculation; a × n + 1 when “n” is number of registers specified.
115
MB91133/MB91F133
• 20-bit normal branch macro instructions
Mnemonic
Operation
Remarks
1
* CALL20 label20, Ri
Next instruction address → RP, label20 → PC
Ri: Temporary register
*
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
* BRA20
* BEQ20
* BNE20
* BC20
* BNC20
* BN20
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20, Ri
label20 → PC
if (Z = = 1) then label20 → PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
* BP20
* BV20
* BNV20
* BLT20
* BGE20
* BLE20
* BGT20
* BLS20
* BHI20
*1: CALL20
(1) If label20 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL label12
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20 #label20, Ri
CALL
*2: BRA20
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA label9
@Ri
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20 #label20, Ri
JMP
@Ri
*3: Bcc20 (BEQ20 to BHI20)
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc
label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:20 #label20, Ri
JMP
@Ri
false:
116
MB91133/MB91F133
• 20-bit delayed branch macro instructions
Mnemonic
Operation
Remarks
1
* CALL20:D label20, Ri
Next instruction address + 2 → RP, label20 → PC
Ri: Temporary register
*
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
* BRA20:D label20, Ri
* BEQ20:D label20, Ri
* BNE20:D label20, Ri
label20 → PC
if (Z = = 1) then label20 → PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
* BC20:D
label20, Ri
* BNC20:D label20, Ri
* BN20:D
* BP20:D
* BV20:D
label20, Ri
label20, Ri
label20, Ri
* BNV20:D label20, Ri
* BLT20:D label20, Ri
* BGE20:D label20, Ri
* BLE20:D label20, Ri
* BGT20:D label20, Ri
* BLS20:D label20, Ri
* BHI20:D label20, Ri
*1: CALL20:D
(1) If label20 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL:D label12
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20 #label20, Ri
CALL:D @Ri
*2: BRA20:D
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA:D label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:20 #label20, Ri
JMP:D @Ri
*3: Bcc20:D (BEQ20:D to BHI20:D)
(1) If label20 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc:D
label9
(2) If label20 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:20 #label20, Ri
JMP:D @Ri
false:
117
MB91133/MB91F133
• 32-bit normal macro branch instructions
Mnemonic
Operation
Remarks
1
* CALL32 label32, Ri
Next instruction address → RP, label32 → PC
Ri: Temporary register
*
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
* BRA32
* BEQ32
* BNE32
* BC32
* BNC32
* BN32
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32, Ri
label32 → PC
if (Z = = 1) then label32 → PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
* BP32
* BV32
* BNV32
* BLT32
* BGE32
* BLE32
* BGT32
* BLS32
* BHI32
*1: CALL32
(1) If label32 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL label12
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:32 #label32, Ri
CALL
*2: BRA32
(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA label9
@Ri
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:32 #label32, Ri
JMP
@Ri
*3: Bcc32 (BEQ32 to BHI32)
(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc
label9
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:32 #label32, Ri
JMP
@Ri
false:
118
MB91133/MB91F133
• 32-bit delayed macro branch instructions
Mnemonic
Operation
Remarks
1
* CALL32:D label32, Ri
Next instruction address + 2 → RP, label32 → PC
Ri: Temporary register
*
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
* BRA32:D label32, Ri
* BEQ32:D label32, Ri
* BNE32:D label32, Ri
label32 → PC
if (Z = = 1) then label32 → PC
ifs/Z = = 0
ifs/C = = 1
ifs/C = = 0
ifs/N = = 1
ifs/N = = 0
ifs/V = = 1
ifs/V = = 0
ifs/V xor N = = 1
ifs/V xor N = = 0
ifs/(V xor N) or Z = = 1
ifs/(V xor N) or Z = = 0
ifs/C or Z = = 1
ifs/C or Z = = 0
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
Ri: Temporary register
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
* BC32:D
label32, Ri
* BNC32:D label32, Ri
* BN32:D
* BP32:D
* BV32:D
label32, Ri
label32, Ri
label32, Ri
* BNV32:D label32, Ri
* BLT32:D label32, Ri
* BGE32:D label32, Ri
* BLE32:D label32, Ri
* BGT32:D label32, Ri
* BLS32:D label32, Ri
* BHI32:D label32, Ri
*1: CALL32:D
(1) If label32 – PC – 2 is between –0x800 and +0x7fe, instruction is generated as follows;
CALL:D label12
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:32 #label32, Ri
CALL:D @Ri
*2: BRA32:D
(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
BRA:D label9
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
LDI:32 #label32, Ri
JMP:D @Ri
*3: Bcc32:D (BEQ32:D to BHI32:D)
(1) If label32 – PC – 2 is between –0x100 and +0xfe, instruction is generated as follows;
Bcc:D
label9
(2) If label32 – PC – 2 is outside of the range given in (1) or includes external reference symbol, instruction is
generated as follows;
Bxcc
false
xcc is a revolt condition of cc
LDI:32 #label32, Ri
JMP:D @Ri
false:
119
MB91133/MB91F133
■ ORDERING INFORMATION
Part number
Package
Remarks
144-pin plastic LQFP
(FPT-144P-M08)
MB91133PMT2-XXX
MB91133PBT-XXX
MB91F133PMT2
MB91F133PBT
144-pin plastic FBGA
(BGA-144P-M01)
144-pin plastic LQFP
(FPT-144P-M08)
144-pin plastic FBGA
(BGA-144P-M01)
299-pin ceramic PGA
(PGA-299)
MB91FV130CR-ES
120
MB91133/MB91F133
■ PACKAGE DIMENSIONS
144-pin plastic FBGA
(BGA-144P-M01)
Note) Corner shape may differ from the diagram.
10.40(.409)REF
0.80(.031)TYP
12.00±0.10(.472±.004)SQ
1.25 +–00..1200 .049 –+..000048
(Mounting height)
0.38±0.10(.015±.004)
(Stand off)
14
13
12
11
10
9
8
7
6
0.10(.004)
5
4
INDEX
3
2
1
P
N M L K J H G F E D C B A
C0.80(.031)
144-Ø0.45±0.10
(144-Ø.018±.004)
M
0.08(.003)
C
1998 FUJITSU LIMITED B144001S-2C-2
Dimensions in mm (inches)
121
MB91133/MB91F133
144-pin plastic LQFP
(FPT-144P-M08)
22.00±0.30(.866±.012)SQ
1.70(.67)MAX
20.00±0.10(.787±.004)SQ
0(0)MIN
(STAND OFF)
108
73
72
109
21.00
(.827)
Details of "A" part
0.15(.006)
17.50
NOM
(.686)
REF
0.15(.006)
INDEX
0.15(.006)MAX
0.40(.016)MAX
144
37
"A"
1
36
LEAD No.
Details of "B" part
0.50(.0197)TYP
0.20±0.10
(.008±.004)
0.15±0.05
(.006±.002)
M
0.08(.003)
0
10˚
0.50±0.20(.020±.008)
0.10(.004)
"B"
C
1995 FUJITSU LIMITED F144019S-1C-2
Dimensions in mm (inches)
122
MB91133/MB91F133
FUJITSU LIMITED
For further information please contact:
Japan
All Rights Reserved.
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
CAUTION:
Europe
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0101
FUJITSU LIMITED Printed in Japan
相关型号：
MB91133PMT2-XXX
RISC Microcontroller, 32-Bit, FLASH, FR30 CPU, 33MHz, CMOS, PQFP144, PLASTIC, LQFP-144
FUJITSU
MB91151APMC-G
RISC Microcontroller, 32-Bit, FLASH, FR30 CPU, 36MHz, CMOS, PQFP144, 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144
FUJITSU
©2020 ICPDF网 联系我们和版权申明