MB91154PFV-G-XXX [FUJITSU]
32-bit Proprietary Microcontrollers; 32位微控制器专用
| 型号： | MB91154PFV-G-XXX |
| 厂家： | 
FUJITSU |
| 描述： | 32-bit Proprietary Microcontrollers |
| 文件： | 总105页 (文件大小：932K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16306-3E
32-bit Proprietary Microcontrollers
CMOS
FR30 Family MB91150 Series
MB91F155A/MB91155/MB91154
■ DESCRIPTION
The MB91F155A/MB91155/MB91154 is a single-chip microcontroller using a RISC-CPU (FR 30 series) as its
core. It contains peripheral I/O resources suitable for audio, MD and so on which are required to operate at low
power consumption.
■ FEATURES
1. CPU
• 32-bit RISC (FR30) , load/store architecture, 5-stage pipeline
• General-purpose registers : 32 bits × 16
• 16-bit fixed-length instructions (basic instructions) , 1 instruction/ 1 cycle
• Memory-to-memory transfer, bit processing, barrel shift processing : Optimized for embedded applications
• Function entrance/exit instructions, and multiple load/store instructions of register contents, instruction systems
supporting high level languages
• Register interlock functions, efficient assembly language description
• Branch instructions with delay slots : Reduced overhead time in branching executions
• Internal multiplier/supported at instruction level
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interrupt (PC and PS saving) : 6 cycles, 16 priority levels
(Continued)
■ PACKAGE
144-pin plastic LQFP
144-pin plastic LQFP
(FPT-144P-M08)
(FPT-144P-M01)
MB91F155A/MB91155/MB91154
2. Bus Interface
• 16-bit address output, 8/16-bit data input and output
• Basic bus cycle : 2-clock cycle
• Support for interface for various types of memory
• Unused data/address pins can be configured us input/output ports
• Support for little endian mode
3. Internal ROM
MB91F155A
FLASH products : 510 Kbytes
MB91155
Mask product : 510 Kbytes
MB91154
Mask product : 384 Kbytes
4. Internal RAM
Mask, FLASH products : 2 Kbytes
5. Internal Data RAM
MB91F155, MB91155
FLASH, Mask products : 32 Kbytes
MB91154
FLASH, Mask product : 20 Kbytes
6. DMAC
DMAC in descriptor format for placing transfer parameters on to the main memory.
Capable of transferring a maximum of eight internal and external factors combined.
Three channels for external factors
7. Bit Search Module
Searches in one cycle for the position of the bit that changes from the MSB in one word to the initial I/O.
8. Timers
• 16-bit OCU × 8 channels, ICU × 4 channels, Free-run timer × 1 channel
• 8/16-bit up/down timer/counter (8-bit × 2 channels or 16-bit × 1 channel)
• 16-bit PPG timer × 6 channels. The output pulse cycle and duty can be varied as desired
• 16-bit reload timer × 4 channels
9. D/A Converter
• 8-bit × 3 channels
10. A/D Converter (Sequential Comparison Type)
• 10-bit × 8 channels
• Sequential conversion method (conversion time : 5.0 µs@33 MHz)
• Single conversion or scan conversion can be selected, and one-shot or continuous or stop conversion mode
can be set respectively.
• Conversion starting function by hardware/software.
(Continued)
2
MB91F155A/MB91155/MB91154
(Continued)
11. Serial I/O
• UART × 4 channels. Any of them is capable of serial transfer in sync with clock attached with the LSB/MSB
switching function.
• Serial data output and serial clock output are selectable by push-pull/open drain software.
• A 16-bit timer (U-timer) is contained as a dedicated baud rate generator allowing any baud rate to be generated.
12. I2C Bus Interface
• One channel master/slave send and receive
• Arbitration and clock synchronization functions
(The product is licensed with the Philips I2C patent to support those customers who intend to use this product
in an I2C system in compliance with the standard I2C specification stipulated by Philips.)
13. Clock Switching Function
• Gear function : Operating clock ratios to the basic clock can be set independently for the CPU and peripherals
from four types, 1 : 1, 1 : 2, 1 : 4 or 1 : 8.
14. Clock Function (Calendar Macro)
• Internal 32 kHz clock function
• It is possible to perform the clock function (oscillation frequency: 32 kHz) even in a stop mode. (The oscillation
does not suspend during a stop mode.)
15. Interrupt Controller
External interrupt input (16 channels in total) :
• Allows the rising edge/falling edge/H level/L level to be set.
Internal interrupt factors :
• Interrupt by resources and delay interrupt
16. Others
• Reset cause : Power on reset/watchdog timer/software reset/external reset
• Low power consumption mode : Sleep/stop
• Package : 144-pin LQFP
• CMOS technology (0.35 µm)
• Power supply voltage : 3.15 V to 3.6 V
• MB91F155 is to be MB91F155A.
3
MB91F155A/MB91155/MB91154
■ PIN ASSIGNMENT
(TOP VIEW)
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23
VSS
P30/D24
P31/D25
P32/D26
P33/D27
P34/D28
P35/D29
P36/D30
P37/D31
P40/A00
P41/A01
P42/A02
P43/A03
P44/A04
P45/A05
P46/A06
P47/A07
VSS
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PH5/SCK1/TO1
PI0/SIN2
PI1/SOT2
PI2/SCK2/TO2
PI3/SIN3
PI4/SOT3
PI5/SCK3/TO3
VSS
PJ0/SCL
PJ1/SDA
VSS
VCC
PG5/PPG5
PG4/PPG4
PG3/PPG3
PG2/PPG2
PG1/PPG1
PG0/PPG0
PF4
PF3/IN3
PF2/IN2
PF1/IN1
PF0/IN0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PE7/OC7
PE6/OC6
PE5/OC5
PE4/OC4
PE3/OC3
PE2/OC2
PE1/OC1
PE0/OC0
VCC
P50/A08
P51/A09
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
P60/A16
VCC
PD7/ATG/INT15
PD6/DEOP2/INT14
PD5/ZIN1/INT13/TRG5
PD4/ZIN0/INT12/TRG4
(FPT-144P-M08)
(FPT-144P-M01 : MB91F155A only)
4
MB91F155A/MB91155/MB91154
■ PIN DESCRIPTION
Circuit
type
Pin No.
Pin name
Function
1
2
3
4
5
6
7
8
D16/P20
D17/P21
D18/P22
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27
Bit 16 to bit 23 of external data bus
These pins are enabled only in 16-bit external bus mode.
These pins are available as ports in single-chip and 8-bit external bus
modes.
C
10
11
12
13
14
15
16
17
D24/P30
D25/P31
D26/P32
D27/P33
D28P34
D29/P35
D30/P36
D31/P37
Bit 24 to bit 31 of external data bus
These pins are available as ports in single-chip mode.
C
18
19
20
21
22
23
24
25
28
29
30
31
32
33
34
35
A00/P40
A01/P41
A02/P42
A03/P43
A04/P44
A05/P45
A06/P46
A07/P47
A08/P50
A09/P51
A10/P52
A11/P53
A12/P54
A13/P55
A14/P56
A15/P57
Bit 0 to bit 15 of external address bus
These pins are enabled in external bus mode.
These pins are available as ports in single-chip mode.
F
36
37
38
39
40
41
42
43
A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67
Bit 16 to bit 23 of external address bus
These pins are available as ports when the address bus is not in use.
O
C
External RDY input
This function is enabled when external RDY input is allowed.
Input “0” when the bus cycle being executed does not end.
This pin is available as a port when external RDY input is not in use.
45
RDY/P80
(Continued)
5
MB91F155A/MB91155/MB91154
Circuit
type
Pin No.
Pin name
Function
External bus release acceptance output
This function is enabled when external bus release acceptance output is
allowed.
Output “L” upon releasing of the external bus.
This pin is available as a port when external bus release acceptance out-
put is not allowed.
46
BGRNT/P81
F
External bus release request input
This function is enabled when external bus release request input is al-
lowed.
Input “1” when the release of the external bus is desired.
This pin is available as a port when external bus release request input is
not in use.
47
BRQ/P82
C
External bus read strobe output
This function is enabled when external bus read strobe output is allowed.
This pin is available as a port when external bus read strobe output is not
allowed.
48
49
RD/P83
F
F
External bus write strobe output
This function is enabled in external bus mode.
This pin is available as a port in single chip mode.
WR0/P84
External bus write strobe output
This function is enabled in external bus mode when the bus width is 16
50
51
WR1/P85
CLK/P86
F
bits.
This pin is available as a port in single chip mode or when the external bus
width is 8 bits.
System clock output
The pin outputs the same clock as the external bus operating frequency.
The pin is available as a port when it is not used to output the clock.
F
52
53
54
MD2
MD1
MD0
Mode pins
G
To use these pins, connect them directly to either VCC or VSS.
Use these pins to set the basic MCU operating mode.
55
RST
B
A
External reset input
57
58
X1
X0
High-speed clock oscillation pins (16.5 MHz)
External interrupt request input 0-3
Since this input is used more or less continuously when the corresponding
external interrupt is allowed, output by the port needs to be stopped ex-
cept when it is performed deliberately.
Since this port is allowed to input also in standby mode, it can be used to
reset the standby state.
60
61
62
63
INT0/PC0
INT1/PC1
INT2/PC2
INT3/PC3
H
These pins are available as ports when external interrupt request input is
not in use.
(Continued)
6
MB91F155A/MB91155/MB91154
Circuit
type
Pin No.
Pin name
Function
These pins also serve as the chip select output and external inter-
rupt request input 4-7.
When the chip select output is not allowed, these pins are available
as external interrupt requests or ports.
64
65
66
67
INT4/PC4/CS0
INT5/PC5/CS1
INT6/PC6/CS2
INT7/PC7/CS3
Since this input is used more or less continuously when the corre-
sponding external interrupt is allowed, output by the port needs to
be stopped except when it is performed deliberately.
Since this port is also allowed to input in standby mode, the port can
be used to reset the standby state.
H
These pins are available as ports when external interrupt request
input and chip select output are not in use.
External interrupt request input 8-13
Since this input is used more or less continuously when the corre-
sponding external interrupt is allowed, output by the port needs to
be stopped except when it is performed deliberately.
[AIN, BIN] Up/down timer input.
69
70
71
72
73
74
PD0/AIN0/INT8/TRG0
PD1/BIN0/INT9/TRG1
PD2/AIN1/INT10/TRG2
PD3/BIN1/INT11/TRG3
PD4/ZIN0/INT12/TRG4
PD5/ZIN1/INT13/TRG5
[TRG] PPG external trigger input.
H
Since this input is used more or less continuously while input is al-
lowed, output by the port needs to be stopped except when it is per-
formed deliberately.
These pins are available as ports when the external interrupt re-
quest input, up timer counter input, and PPG external trigger input
are not in use.
External interrupt request input 14
Since this input is used more or less continuously when the corre-
sponding external interrupt is allowed, output by the port needs to
be stopped except when it is performed deliberately.
[DEOP2] DMA external transfer end output.
75
PD6/DEOP2/INT14
H
This function is enabled when DMAC external transfer end output
is allowed.
This pin is available as a port when it is not in use as the external
interrupt request input or DMA external transfer end output.
External interrupt request input 15
Since this input is used more or less continuously when the corre-
sponding external interrupt is allowed, output by the port needs to
be stopped except when it is performed deliberately.
[ATG] A/D converter external trigger input.
Since this input is used more or less continuously when selected as
an A/D activation factor, output by the port needs to be stopped ex-
cept when it is performed deliberately.
76
PD7/ATG/INT15
H
This pin is available as a port when it is not in use as the external
interrupt request input or A/D converter external trigger input.
(Continued)
7
MB91F155A/MB91155/MB91154
Circuit
type
Pin No.
Pin name
Function
78
79
80
81
82
83
84
85
PE0/OC0
PE1/OC1
PE2/OC2
PE3/OC3
PE4/OC4
PE5/OC5
PE6/OC6
PE7/OC7
Output compare output
These pins are available as ports when output compare output is not al-
lowed.
F
86
87
88
89
PF0/IN0
PF1/IN1
PF2/IN2
PF3/IN3
Input capture input
This function is enabled when the input capture operation is input.
These pins are available as ports when input capture input is not in use.
F
F
90
PF4
General purpose I/O port
91
92
93
94
95
96
PG0/PPG0
PG1/PPG1
PG2/PPG2
PG3/PPG3
PG4/PPG4
PG5/PPG5
PPG timer output
F
This function is enabled when PPG timer output is allowed.
These pins are available as ports when PPG timer output is not allowed.
I2C interface I/O pin
This function is enabled when the I2C interface is allowed to operate.
While the I2C interface is in operation, keep the port output set to Hi-Z.
This pin is available as a port when the I2C interface is not in use.
99
PJ1/SDA
PJ0/SCL
Q
Q
I2C interface I/O pin
This function is enabled when the I2C interface is allowed to operate.
While the I2C interface is in operation, keep the port output set to Hi-Z.
This pin is available as a port when the I2C interface is not in use.
100
UART3 clock I/O, Reload timer 3 output
When UART3 clock output is not allowed, reload timer 3 can be output by
allowing it.
This pin is available as a port when neither UART3 clock output nor reload
timer output is allowed.
102
103
104
PI5/SCK3/TO3
PI4/SOT3
P
P
P
UART3 data output
This function is enabled when UART3 data output is allowed.
This pin is available as a port when UART3 clock output is not allowed.
UART3 data input
Since this input is used more or less continuously while UART3 is en-
gaged in input operations, output by the port needs to be stopped except
when it is performed deliberately.
PI3/SIN3
This pin is available as a port when UART3 output data input is not in use.
(Continued)
8
MB91F155A/MB91155/MB91154
Circuit
type
Pin No.
Pin name
Function
UART2 clock I/O, Reload timer 2 output
When UART2 clock output is not allowed, reload timer 2 can be output by
allowing it.
This pin is available as a port when neither UART2 clock output nor reload
timer output is allowed.
105
PI2/SCK2/TO2
P
P
P
UART2 data output
This function is enabled when UART2 data output is allowed.
This pin is available as a port when UART2 clock output is not allowed.
106
107
PI1/SOT2
PI0/SIN2
UART2 data input
Since this input is used more or less continuously while UART2 is en-
gaged in input operations, output by the port needs to be stopped except
when it is performed deliberately.
This pin is available as a port when UART2 data input is not in use.
UART1 clock I/O, Reload timer 1 output
When UART1 clock output is not allowed, reload timer 1 can be output by
allowing it.
This pin is available as a port when neither UART1 clock output nor reload
timer output is allowed.
108
109
110
PH5/SCK1/TO1
PH4/SOT1
P
P
P
UART1 data output
This function is enabled when UART1 data output is allowed.
This pin is available as a port when UART1 clock output is not allowed.
UART1 data input
Since this input is used more or less continuously while UART1 is en-
gaged in input operations, output by the port needs to be stopped except
when it is performed deliberately.
PH3/SIN1
This pin is available as a port when UART1 data input is not in use.
UART0 clock I/O, Reload timer 0 output
When UART0 clock output is not allowed, reload timer 0 can be output by
allowing it.
This pin is available as a port when neither UART0 clock output nor reload
timer output is allowed.
111
112
113
PH2/SCK0/TO0
PH1/SOT0
P
P
P
UART0 data output
This function is enabled when UART0 data output is allowed.
This pin is available as a port when UART0 clock output is not allowed.
UART0 data input
Since this input is used more or less continuously while UART0 is en-
gaged in input operations, output by the port needs to be stopped except
when it is performed deliberately.
PH0/SIN0
This pin is available as a port when UART0 data input is not in use.
DMA external transfer request input
Since this input is used more or less continuously when selected as a
DMAC transfer factor, output by the port needs to be stopped except when
it is performed deliberately.
114
DREQ0/PL0
F
This pin is available as a port when DMA external transfer request input is
not in use.
(Continued)
9
MB91F155A/MB91155/MB91154
Circuit
type
Pin No.
Pin name
Function
DMA external transfer request acceptance output
This function is enabled when the DMAC external transfer request accep-
tance is allowed to be output.
115
DACK0/PL1
F
This pin is available as a port when the DMAC transfer request accep-
tance is not allowed to be output.
DMA external transfer end output
116
117
DEOP0/PL2
DREQ1/PL3
F
F
This function is enabled when the end of DMAC external transfer is al-
lowed to be output.
DMA external transfer request input
Since this input is used more or less continuously when selected as a
DMAC transfer factor, output by the port needs to be stopped except when
it is performed deliberately.
This pin is available as a port when DMA external transfer request input is
not in use.
DMA external transfer request acceptance output
This function is enabled when the DMAC external transfer request accep-
tance is allowed to be output.
This pin is available as a port when DMAC transfer request acceptance
output is not allowed.
118
119
DACK1/PL4
DEOP1/PL5
F
F
DMA external transfer end output
This function is enabled when the end of DMAC external transfer is al-
lowed to be output.
DMA external transfer request input
Since this input is used more or less continuously when selected as a
DMAC transfer factor, output by the port needs to be stopped except when
it is performed deliberately.
This pin is available as a port when DMA external transfer request input is
not in use.
120
DREQ2/PL6
F
F
DMA external transfer request acceptance output
This function is enabled when the DMAC external transfer request accep-
tance is allowed to be output.
121
DACK2/PL7
This pin is available as a port when DMAC transfer request acceptance
output is not allowed.
123
124
125
DA2
DA1
DA0
D/A converter output
This function is enabled when D/A converter output is allowed.
126
127
128
DAVS
DAVC
AVCC
Power supply pin for the D/A converter
Power supply pin for the D/A converter
Vcc power supply for the A/D converter
A/D converter reference voltage (high potential side)
129
AVRH
Be sure to turn on/off this pin with potential higher than AVRH applied to
VCC.
130
131
AVRL
AVSS
A/D converter reference voltage (low potential side)
VSS power supply for the A/D converter
(Continued)
10
MB91F155A/MB91155/MB91154
(Continued)
Circuit
type
Pin No.
Pin name
Function
132
133
134
135
136
137
138
139
AN0/PK0
AN1/PK1
AN2/PK2
AN3/PK3
AN4/PK4
AN5/PK5
AN6/PK6
AN7/PK7
A/D converter analog input
These pins are enabled when the AIC register is designated for analog
input.
These pins are available as ports when A/D converter analog input is
not in use.
N
141
TEST
G
K
The TEST pin must be connected to the power supply (VCC)
Low-speed clock (32 kHz) oscillation pin
142
143
X0A
X1A
27, 56, 68,
77, 97,
122, 140
Power supply pin (VCC) for digital circuit
Always power supply pin (VCC) must be connected to the power
supply
VCC
9, 26, 44,
59, 98,
101, 144
Earth level (VSS) for digital circuit
Always power supply pin (VSS) must be connected to the power
supply
VSS
Note : On the majority of pins listed above, the I/O port and the resource I/O are multiplexed, such as XXXX/Pxx.
When the port and the resource output compete against each other on these pins, priority is given to the
resource.
11
MB91F155A/MB91155/MB91154
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• High-speed oscillation circuit
(16.5 MHz)
Oscillation feedback resistor
= approx. 1 MΩ
X1
X0
Xout
A
Standby control signal
• CMOS hysteresis input pin
CMOS hysteresis input
(standby control not attached)
Pullup resistor
B
Digital input
• CMOS level I/O pin
CMOS level output
CMOS level input
Pout
Nout
(attached with standby control)
IOL = 4 mA
C
R
CMOS input
Standby control
• CMOS hysteresis I/O pin
CMOS level output
Pout
Nout
CMOS hysteresis input
(attached with standby control)
IOL = 4 mA
F
R
Hysteresis input
Standby control
(Continued)
12
MB91F155A/MB91155/MB91154
Type
Circuit
Remarks
• CMOS level input pin
CMOS level input
(standby control not attached)
G
R
Digital input
• CMOS hysteresis I/O pin with pul-
lup control
CMOS level output
Pullup control
Pout
R
CMOS level input
(standby control not attached)
Pullup resistance
= approx. 50 kΩ (Typ.)
H
Nout
R
IOL = 4 mA
Hysteresis input
• Clock oscillation circuit (32 kHz)
X1A
X0A
Xout
K
• Analog/CMOS level I/O pin.
CMOS level output
Pout
Nout
CMOS level input
(attached with standby control)
Analog input (Analog input is en-
abled when AIC’s corresponding
bit is set to “1.”)
N
R
CMOS input
IOL = 4 mA
Standby control
Analog input
(Continued)
13
MB91F155A/MB91155/MB91154
(Continued)
Type
Circuit
Remarks
• CMOS hysteresis I/O pin
with pullup control
CMOS level output
CMOS hysteresis input
(attached with standby control)
Pullup resistance
Pullup control
Pout
R
O
Nout
= approx. 50 kΩ (Typ.)
R
IOL = 4 mA
Hysteresis input
Standby control
• CMOS hysteresis I/O pin
with pullup control.
Pullup control
CMOS level output
(attached with open drain con-
trol)
Open drain control
R
CMOS hysteresis input
(attached with standby control)
Pullup resistance
P
Nout
R
= approx. 50 kΩ (Typ.)
Hysteresis input
Standby control
IOL = 4 mA
• Open drain I/O pin
• 5 V tolerance of voltage
• CMOS hysteresis input
(attached with standby control)
Nout
Q
IOL = 15 mA
R
Hysteresis input
Standby control
14
MB91F155A/MB91155/MB91154
■ HANDLING DEVICES
1. Preventing Latchup
In CMOS ICs, applying voltage higher than VCC or lower than VSS to input/output pin or applying voltage over
rating across VCC and VSS may cause latchup.
This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the
device. Make sure to prevent the voltage from exceeding the maximum rating.
2. Treatment of Pins
• Treatment of unused pins
Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors.
• Treatment of open pins
Be sure to use open pins in open state.
• Treatment of output pins
Shortcircuiting an output pin with the power supply or with another output pin or connecting a large-capacity
load may causes a flow of large current. If this conditions continues for a lengthy period of time, the device
deteriorates. Take great care not to exceed the absolute maximum ratings.
• Mode pins (MD0-MD2)
These pins should be used directly connected to either VCC or VSS. In order to prevent noise from causing
accidental entry into test mode, keep the pattern length as short as possible between each mode pin and VCC
or VSS on the board and connect them with low impedance.
• Power supply pins
When there are several VCC and VSS pins, each of them is equipotentially connected to its counterpart inside
of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions,
to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and
to observe the total output current standard, connect all VCC and VSS pins to the power supply or GND.
It is preferred to connect VCC and VSS of MB91F155/MB91154 to power supply with minimal impedance possible.
It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 µF between VCC and
VSS at a position as close as possible to MB91F155/MB91154.
• Crystal oscillator circuit
Noises around X0, X1, X0A, and X1A pins may cause malfunctions of MB91F155/MB91154. In designing the
PC board, layout X0, X1 (X0A, X1A) and crystal oscillator (or ceramic oscillator) and bypass capacitor for
grounding as close as possible.
It is strongly recommended to design PC board so that X0, X1, X0A, and X1A pins are surrounded by grounding
area for stable operation.
The MB91F155A, MB91155 and MB91154 devices do not contain a feedback resistor. To use the clock function,
you need to connect an external resistor.
X0A
X1A
MB91F155A/MB91155/MB91154
3. Precautions
• External Reset Input
It takes at least 5 machine cycle to input “L” level to the RST pin and to ensure inner reset operation properly.
• External Clocks
When using an external clock, normally, a clock of which the phase is opposite to that of X0 must be supplied
to the X0 and X1 pins simultaneously. However, when using the clock along with STOP (oscillation stopped)
15
MB91F155A/MB91155/MB91154
mode, the X1 pin stops when “H” is input in STOP mode. To prevent one output from competing against another,
an external resistor of about 1 kΩ should be provided.
The following figure shows an example usage of an external clock.
Figure 2.1 An example usage of an external clock
X0
X1
MB91F155A/MB91155/MB91154
4. Care During Powering Up
• When powering up
When turning on the power supply, never fail to start from setting the RST pin to “L” level. And after the power
supply voltage goes to VCC level, at least after ensuring the time for 5 machine cycle, then set to “H” level.
• Source oscillation input
At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing
waiting.
• Power on resetting
When powering up or when turning the power back on after the supply voltage drops below the operation
assurance range, be sure to reset the power.
• Power on sequence
Turn on the power in the order of VCC, AVCC and AVRH. The power should be disconnected in inverse order.
• Even when an AD converter is not in use, connect AVCC to the VCC level and AVSS to the VSS level.
• Even when a DA converter is not in use, connect DAVC to the VCC level and DAVS to the VSS level.
5. When the Clock Function (Calendar Macro) Is Not in Use
Not using the clock function, the clock oscillation pin must be configured as shown below.
X0A
OPEN
X1A
MB91F155A/MB91155/MB91154
This product type does not allow the clock crystal oscillator to be stopped with software.
16
MB91F155A/MB91155/MB91154
■ BLOCK DIAGRAM
• MB91F155A, MB91155
M
O
D
E
MD0
FR30 CPU Core
MD1
MD2
RST
I - Bus
D - Bus
4
OSC
(2)
X0A
X1A
Clock
Calendar
P37/D31 (IO)
P
O
R
T
3
/
PE7/OC7
PE6/OC6
PE5/OC5
PE4/OC4
PE3/OC3
PE2/OC2
PE1/OC1
PE0/OC0
P
Data RAM
32 KB
O
R
T
P30/D24
P27/D23
DATA
Output
Compare
2
E
8
16
P20/D16
DMAC 8 ch
Bit Search
P
O
R
T
6
/
5
/
4
P67/A23 (O)
PG5/PPG5
PG4/PPG4
PG3/PPG3
PG2/PPG2
PG1/PPG1
PG0/PPG0
P
O
R
T
P60/A16
P57/A15
PPG
D - Bus
R - Bus
G
6
Address
P50/A8
P47/A7
PH0/SIN0
PH1/SOT0
PH2/SCK0/TO0
PH3/SIN1
PH4/SOT1
PH5/SCK1/TO1
I - Bus
D - Bus
C - Bus
P
O
R
T
P40/A0
24
UART 4 ch
UTIMER 4 ch
P86/CLK (O)
P85/WR1 (O)
P84/WR0
P83/RD (O)
P82/BRQ (I)
P81/BGRNT (O)
P80/RDY (I)
P
O
R
T
H
6
UART
TOX:
External
Bus CTL
Bus
Control
Reload
Timer
16 bit
Reload Timer
P
O
R
T
PI0/SIN2
PI1/SOT2
PI2/SCK2/TO2
PI3/SIN3
PI4/SOT3
8
7
4 ch
RAM
2 KB
I
16 bit
Free RUN Timer
PL7/DACK2
PL6/DREQ2
PL5/DEOP1
6
P
O
R
T
PI5/SCK3/TO3
1 ch
P
O
R
T
J
PL4/DACK1
PJ0/SCL
PJ1/SDA
ROM
16 bit PPG
6 ch
DMAC
I2C
PL3/DREQ1
PL2/DEOP0 (O)
PL1/DACK0 (O)
PL0/DREQ0 (I)
510 KB
L
8
2
PK0/AN0
PK1/AN1
PK2/AN2
PK3/AN3
PK4/AN4
PK5/AN5
PK6/AN6
PK7/AN7
16 bit
Input Capture
P
O
R
T
X0 (I)
X1 (I)
OSC
(2)
Clock
A/D
4 ch
Clock
Control
A/D
16 bit
Output Compare
PD7/INT15/ATG (I)
PD6/INT14/DEOP2
PD5/INT13/ZIN1
PD4/INT12/ZIN0
PD3/INT11/BIN1
PD2/INT10/AIN1
PD1/INT9/BIN0 (I)
PD0/INT8/AIN0 (I)
PC7/INT7/CS3
PC6/INT6/CS2
PC5/INT5/CS1
PC4/INT4/CS0
PC3/INT3
K
8
P
DMAC
O
R
T
8 ch
Interrupt
Controller
10 bit 8 input
A/D converter
Up/Down
Counter
P
O
R
T
D
8
PF4
PF3/IN3
PF2/IN2
PF1/IN1
PF0/IN0
8 bit
Up/Down
Counter
Input
Capture
External
Interrupt
F
5
P
O
R
T
2 ch
8 bit 3 output
D/A converter
External
Interrupt
D
A
DA2
DA1
DA0
C
8
I2C Interface
1 ch
PC2/INT2
PC1/INT1
3
16 ch
PC0/INT0 (I)
17
MB91F155A/MB91155/MB91154
• MB91154
M
MD0
O
FR30 CPU Core
MD1
MD2
RST
D
E
I - Bus
D - Bus
4
OSC
(2)
X0A
X1A
Clock
Calendar
P37/D31 (IO)
P
O
R
T
3
/
PE7/OC7
PE6/OC6
PE5/OC5
PE4/OC4
PE3/OC3
PE2/OC2
PE1/OC1
PE0/OC0
P
Data RAM
20 KB
O
R
T
P30/D24
P27/D23
DATA
Output
Compare
2
E
8
16
P20/D16
DMAC 8 ch
Bit Search
P
O
R
T
6
/
5
/
4
P67/A23 (O)
PG5/PPG5
PG4/PPG4
PG3/PPG3
PG2/PPG2
PG1/PPG1
PG0/PPG0
P
O
R
T
P60/A16
P57/A15
PPG
D - Bus
R - Bus
G
6
Address
P50/A8
P47/A7
PH0/SIN0
PH1/SOT0
PH2/SCK0/TO0
PH3/SIN1
PH4/SOT1
PH5/SCK1/TO1
I - Bus
D - Bus
C - Bus
P
O
R
T
P40/A0
24
UART 4 ch
UTIMER 4 ch
P86/CLK (O)
P85/WR1 (O)
P84/WR0
P83/RD (O)
P82/BRQ (I)
P81/BGRNT (O)
P80/RDY (I)
P
O
R
T
H
6
UART
TOX:
External
Bus CTL
Bus
Control
Reload
Timer
16 bit
Reload Timer
P
O
R
T
PI0/SIN2
PI1/SOT2
PI2/SCK2/TO2
PI3/SIN3
PI4/SOT3
8
7
4 ch
RAM
2 KB
I
16 bit
Free RUN Timer
PL7/DACK2
PL6/DREQ2
PL5/DEOP1
6
P
O
R
T
PI5/SCK3/TO3
1 ch
P
O
R
T
J
PL4/DACK1
PJ0/SCL
PJ1/SDA
ROM
16 bit PPG
6 ch
DMAC
I2C
PL3/DREQ1
PL2/DEOP0 (O)
PL1/DACK0 (O)
PL0/DREQ0 (I)
384 KB
L
8
2
PK0/AN0
PK1/AN1
PK2/AN2
PK3/AN3
PK4/AN4
PK5/AN5
PK6/AN6
PK7/AN7
16 bit
Input Capture
P
O
R
T
X0 (I)
X1 (I)
OSC
(2)
Clock
A/D
4 ch
Clock
Control
A/D
16 bit
Output Compare
PD7/INT15/ATG (I)
PD6/INT14/DEOP2
PD5/INT13/ZIN1
PD4/INT12/ZIN0
PD3/INT11/BIN1
PD2/INT10/AIN1
PD1/INT9/BIN0 (I)
PD0/INT8/AIN0 (I)
PC7/INT7/CS3
PC6/INT6/CS2
PC5/INT5/CS1
PC4/INT4/CS0
PC3/INT3
K
8
P
DMAC
O
R
T
8 ch
Interrupt
Controller
10 bit 8 input
A/D converter
Up/Down
Counter
P
O
R
T
D
8
PF4
PF3/IN3
PF2/IN2
PF1/IN1
PF0/IN0
8 bit
Up/Down
Counter
Input
Capture
External
Interrupt
F
5
P
O
R
T
2 ch
8 bit 3 output
D/A converter
External
Interrupt
D
A
DA2
DA1
DA0
C
8
I2C Interface
1 ch
PC2/INT2
PC1/INT1
3
16 ch
PC0/INT0 (I)
18
MB91F155A/MB91155/MB91154
■ CPU CORE
1. Memory Space
The FR family has a logical address space of 4 Gbytes (232 bytes) and the CPU linearly accesses the memory
space.
• Direct addressing area
The following area in the address space is used for I/O.
This area is called direct addressing area and an operand address can be specified directly in an instruction.
The direct addressing area varies with the data size to be accessed as follows :
→ byte data access :
→ half word data access : 0-1FFH
→ word data access : 0-3FFH
0-0FFH
2. Memory Map
• MB91F155, MB91155 Memory Space
External ROM-
external bus mode
Internal ROM-
external bus mode
Single-chip mode
0000 0000H
0000 0400H
Direct
addressing
area
I/O
I/O
I/O
I/O
I/O
I/O
See "■ I/O MAP"
0000 0800H
Not accessible
Not accessible
Not accessible
0000 1000H
0000 9000H
32 KB
internal RAM
32 KB
internal RAM
32 KB
internal RAM
Not accessible
Not accessible
Not accessible
0001 0000H
0001 0000H
External area
Not accessible
0008 0000H
0008 0800H
0010 0000H
2 KB internal RAM
2 KB internal RAM
External area
510 KB
internal ROM
510 KB
internal ROM
Not accessible
External area
FFFF FFFFH
FFFF FFFFH
Note : External areas are not accessible in single-chip mode.
19
MB91F155A/MB91155/MB91154
• MB91154 Memory Space
External ROM-
external bus mode
Internal ROM-
external bus mode
Single-chip mode
0000 0000H
0000 0400H
Direct
addressing
area
I/O
I/O
I/O
I/O
I/O
I/O
See "■ I/O MAP"
0000 0800H
Not accessible
Not accessible
Not accessible
0000 1000H
0000 6000H
20 KB
internal RAM
20 KB
internal RAM
20 KB
internal RAM
Not accessible
Not accessible
Not accessible
0001 0000H
0001 0000H
External area
Not accessible
0008 0000H
0008 0800H
000A 0000H
0010 0000H
2 KB internal RAM
2 KB internal RAM
Not accessible
Not accessible
External area
384 KB
internal ROM
384 KB
internal ROM
Not accessible
External area
FFFF FFFFH
FFFF FFFFH
Note : External areas are not accessible in single-chip mode.
20
MB91F155A/MB91155/MB91154
3. Registers
ThefamilyofFRmicrocontrollershastwotypesofregisters:theregistersresidingintheCPUwhicharededicated
to applications and the general-purpose registers residing in the memory.
• Dedicated registers :
Program counter (PC)
: A 32-bit register to indicate the location where an instructions is stored.
: A 32-bit register to store a register pointer or a condition code.
Program status (PS)
Tablebase register (TBR)
: Holds the vector table lead address used when EIT (exceptions/interrupt/
trap) is processed.
Return pointer (RP)
: Holds the address to return from a subroutine to.
System stack pointer (SSP) : Points to the system stack space.
User stack pointer (USP) : Points to the user stack space.
Multiplication and division result register (MDH/MDL) : A 32-bit multiplication and division register.
32 bit
PC
Initial value
XXXX XXXXH
Program counter
Program status
(Undefined)
PS
TBR
RP
Tablebase register
Return pointer
000F FC00H
XXXX XXXXH (Undefined)
0000 0000H
SSP
USP
System stack pointer
User stack pointer
(Undefined)
XXXX XXXXH
MDH
MDL
XXXX XXXXH (Undefined)
Multiplication and division register
XXXX XXXXH
(Undefined)
• Program status (PS)
The PS register holds program status and is further divided into three registers which are a Condition Code
Register (CCR) , a System condition Code Register (SCR) , and an Interrupt Level Mask register (ILM) .
31 20 19 18 17 16
ILM4 ILM3 ILM2 ILM1 ILM0
10
9
8
T
7
6
5
4
I
3
2
Z
1
0
PS
D1 D0
S
N
V
C
ILM
SCR
CCR
21
MB91F155A/MB91155/MB91154
• Condition Code Register (CCR)
S flag : Designates the stack pointer for use as R15.
I flag
: Controls enabling and disabling of user interrupt requests.
N flag : Indicates the sign when arithmetic operation results are considered to be an integer represented
by 2’s complement.
Z flag : Indicates if arithmetic results were “0.”
V flag : Considers the operand used for an arithmetic operation to be an integer represented by 2’s com-
plement and indicates if the operation resulted in an overflow.
C flag : Indicates whether or not an arithmetic operation resulted in a carry or a borrow from the most sig-
nificant bit.
• System condition Code Register (SCR)
T flag : Designates whether or not to enable step trace trap.
• Interrupt Level Mask register (ILM)
ILM4 to ILM0
: Holds an interrupt level mask value to be used for level masking.
An interrupt request is accepted only if the corresponding interrupt level among interrupt
requests input to the CPU is higher than the value indicated by the ILM register.
ILM4
ILM3
ILM2
ILM1
ILM0
Interrupt level
High-Low
0
0
0
0
0
0
Higher
0
1
1
1
0
1
0
1
0
1
15
31
Lower
22
MB91F155A/MB91155/MB91154
■ GENERAL-PURPOSE REGISTERS
General-purpose registers are CPU registers R0 through R15 and used as accumulators during various oper-
ations and as memory access pointers (fields indicating addresses) .
• Register Bank Configuration
32 bit
Initial value
R0
R1
XXXX XXXXH
R12
R13
R14
R15
AC (Accumulator)
FP (Frame Pointer)
SP (Stack Pointer)
XXXX XXXXH
0000 0000H
Of the 16 general-purpose registers, the following registers are assumed for specific applications. For this reason,
some instructions are enhanced.
R13 : Virtual accumulator (AC)
R14 : Frame pointer (FP)
R15 : Stack pointer (SP)
Initial values to which R0 through R14 are reset are not defined. The initial value of R15 is 0000 0000H (the SSP
value) .
23
MB91F155A/MB91155/MB91154
■ SETTING MODE
1. Mode Pins
As shown in Table 1 three pins, MD2, 1, and 0 are used to indicate an operation.
Table 1 Mode pins and set modes
Mode pin
Reset vector
access area
External data
bus width
Mode name
MD2 MD1 MD0
0
0
0
0
0
1
External vector mode 0
External vector mode 1
External
External
8 bits
External ROM bus mode
16 bits
Not available on this
product type
0
1
1
0
1
External vector mode 2
External vector mode
External
Internal
32 bits
0
1
(Mode register) Single-chip mode
Not available
2. Mode Data
The data which the CPU writes to “0000 07FFH” after reset is called mode data.
It is the mode register (MODR) that exists at “0000 07FFH.” Once a mode is set in this register, operations will
take place in that mode. The mode register can be written only once after reset.
The mode specified in the register is enabled immediately after it is written.
MODR
Address : 0000 07FFH
Initial value Access
XXXXXXXX
W
M1
M0
Bus mode setting bits
W : Write only, X : Undefined
[bits 7 and 6] : M1, M0
These are bus mode setting bits. Specify the bus mode to be set to after writing to the mode register.
M1
0
M0
0
Function
Single-chip mode
Remarks
0
1
Internal ROM-external bus mode
External ROM-external bus mode
1
0
1
1
Setting not allowed
[bits 5 to 0] :
These bits are reserved for the system.
“0” should be written to these bits at all times.
24
MB91F155A/MB91155/MB91154
[Precautions When Writing to the MODR]
Before writing to the MODR, be sure to set AMD0 through 5 and determine the bus width in each CS (Chip
Select) area.
The MODR does not have bus width setting bits.
The bus width value set with mode pins MD2 through 0 is enabled before writing to the MODR and the bus width
value set with BW1 and 0 of AMD0 through 5 is enabled after writing to the MODR.
For example, the external reset vector is normally executed with area 0 (the area where CS0 is active) and the
bus width at that time is determined by pins MD 2 through 0. Suppose that the bus width is set to 32 or 16 bits
in MD2 though 0 but no value is specified in AMD 0. If the MODR is written in this state, area 0 then switches
to 8-bit bus mode and operates the bus since the initial bus width in AMD0 is set to 8 bits. This causes a
malfunction.
In order to prevent this type of problem, AMD0 through 5 must always be set before writing to the MODR.
Writing to the MODR.
RST (Reset)
Designated bus width : MD2,1,0
AMD0 to AMD5 BW1, 0
25
MB91F155A/MB91155/MB91154
■ I/O MAP
Register
Address
Block
+0
+1
+2
+3
PDR3 (R/W)
XXXXXXXX
PDR2 (R/W)
XXXXXXXX
000000H
000004H
000008H
00000CH
000010H
000014H
000018H
PDR6 (R/W)
XXXXXXXX
PDR5 (R/W)
XXXXXXXX
PDR4 (R/W)
XXXXXXXX
PDR8 (R/W)
- XXXXXXX
Port Data Register
PDRF (R/W)
- - - XXXXX
PDRE (R/W)
XXXXXXXX
PDRD (R/W)
XXXXXXXX
PDRC (R/W)
XXXXXXXX
PDRJ (R/W)
- - - - - - 11
PDRI (R/W)
- - XXXXXX
PDRH (R/W)
- - XXXXXX
PDRG (R/W)
- - XXXXXX
PDRL (R/W)
XXXXXXXX
PDRK (R/W)
XXXXXXXX
SIDR0/SODR0
(R, W)
XXXXXXXX
SSR0 (R, R/W)
00001000
SCR0 (R/W, W)
00000100
SMR0 (R/W)
00000 - 00
00001CH
000020H
000024H
000028H
UART0
UART1
UART2
UART3
SIDR1/SODR1
(R, W)
XXXXXXXX
SSR1 (R, R/W)
00001000
SCR1 (R/W, W)
00000100
SMR1 (R/W)
00000 - 00
SIDR2/SODR2
(R, W)
XXXXXXXX
SSR2 (R, R/W)
00001000
SCR2 (R/W, W)
00000100
SMR2 (R/W)
00000 - 00
SIDR3/SODR3
(R, W)
XXXXXXXX
SSR3 (R, R/W)
00001000
SCR3 (R/W, W)
00000100
SMR3 (R/W)
00000 - 00
TMRLR0 (W)
XXXXXXXX XXXXXXXX
TMR0 (R)
XXXXXXXX XXXXXXXX
00002CH
000030H
000034H
000038H
00003CH
000040H
Reload Timer 0
Reload Timer 1
TMCSR0 (R/W)
- - - - 0000 00000000
TMRLR1 (W)
XXXXXXXX XXXXXXXX
TMR1 (R)
XXXXXXXX XXXXXXXX
TMCSR1 (R/W)
- - - - 0000 00000000
TMRLR2 (W)
XXXXXXXX XXXXXXXX
TMR2 (R)
XXXXXXXX XXXXXXXX
Reload Timer 2
(Continued)
TMCSR2 (R/W)
- - - - 0000 00000000
26
MB91F155A/MB91155/MB91154
Address
Register
Block
TMRLR3 (W)
XXXXXXXX XXXXXXXX
TMR3 (R)
XXXXXXXX XXXXXXXX
000044H
Reload Timer 3
TMCSR3 (R/W)
000048H
00004CH
000050H
- - - - 0000 00000000
CDCR1 (R/W)
0 - - - 0000
CDCR0 (R/W)
0 - - - 0000
Communications
prescaler 1
CDCR3 (R/W)
0 - - - 0000
CDCR2 (R/W)
0 - - - 0000
000054H
to
Reserved
000058H
RCR1 (W)
00000000
RCR0 (W)
00000000
UDCR1 (R)
00000000
UDCR0 (R)
00000000
00005CH
000060H
000064H
000068H
00006CH
000070H
000074H
000078H
00007CH
000080H
000084H
000088H
00008CH
000090H
000094H
CCRH0 (R/W)
00000000
CCRL0 (R/W, W)
- 000X000
CSR0 (R/W, R)
00000000
8/16 bit U/D Counter
CCRH1 (R/W)
- 0000000
CCRL1 (R/W, W)
- 000X000
CSR1 (R/W, R)
00000000
IPCP1 (R)
XXXXXXXX XXXXXXXX
IPCP0 (R)
XXXXXXXX XXXXXXXX
IPCP3 (R)
XXXXXXXX XXXXXXXX
IPCP2 (R)
XXXXXXXX XXXXXXXX
16 bit ICU
ICS23 (R/W)
00000000
ICS01 (R/W)
00000000
OCCP1 (R/W)
XXXXXXXX XXXXXXXX
OCCP0 (R/W)
XXXXXXXX XXXXXXXX
OCCP3 (R/W)
XXXXXXXX XXXXXXXX
OCCP2 (R/W)
XXXXXXXX XXXXXXXX
OCCP5 (R/W)
XXXXXXXX XXXXXXXX
OCCP4 (R/W)
XXXXXXXX XXXXXXXX
16 bit OCU
OCCP7 (R/W)
XXXXXXXX XXXXXXXX
OCCP6 (R/W)
XXXXXXXX XXXXXXXX
OCS2, 3 (R/W)
XXX00000 0000XX00
OCS0, 1 (R/W)
XXX00000 0000XX00
OCS6, 7 (R/W)
XXX00000 0000XX00
OCS4, 5 (R/W)
XXX00000 0000XX00
TCDT (R/W)
00000000 00000000
TCCS (R/W)
0 - - - - - - - 00000000
16 bit Freerun Timer
Stop Register 0, 1, 2
STPR0 (R/W)
0000 - - - -
STPR1 (R/W)
00000000
STPR2 (R/W)
000000 - -
GCN1 (R/W)
00110010 00010000
GCN2 (R/W)
00000000
PPG ctl
(Continued)
27
MB91F155A/MB91155/MB91154
Address
Register
Block
PTMR0 (R)
11111111 11111111
PCSR0 (W)
XXXXXXXX XXXXXXXX
000098H
PPG0
PDUT0 (W)
XXXXXXXX XXXXXXXX
PCNH0 (R/W)
0000000 -
PCNL0 (R/W)
00000000
00009CH
0000A0H
0000A4H
0000A8H
0000ACH
0000B0H
0000B4H
0000B8H
0000BCH
0000C0H
0000C4H
0000C8H
0000CCH
PTMR1 (R)
11111111 11111111
PCSR1 (W)
XXXXXXXX XXXXXXXX
PPG1
PPG2
PPG3
PPG4
PPG5
PDUT1 (W)
XXXXXXXX XXXXXXXX
PCNH1 (R/W) PCNL1 (R/W)
0000000 - 00000000
PCSR2 (W)
XXXXXXXX XXXXXXXX
PCNH2 (R/W) PCNL2 (R/W)
0000000 - 00000000
PCSR3 (W)
XXXXXXXX XXXXXXXX
PCNH3 (R/W) PCNL3 (R/W)
0000000 - 00000000
PCSR4 (W)
XXXXXXXX XXXXXXXX
PCNH4 (R/W) PCNL4 (R/W)
0000000 - 00000000
PCSR5 (W)
XXXXXXXX XXXXXXXX
PCNH5 (R/W) PCNL5 (R/W)
0000000 - 00000000
PTMR2 (R)
11111111 11111111
PDUT2 (W)
XXXXXXXX XXXXXXXX
PTMR3 (R)
11111111 11111111
PDUT3 (W)
XXXXXXXX XXXXXXXX
PTMR4 (R)
11111111 11111111
PDUT4 (W)
XXXXXXXX XXXXXXXX
PTMR5 (R)
11111111 11111111
PDUT5 (W)
XXXXXXXX XXXXXXXX
EIRR0 (R/W)
00000000
ENIR0 (R/W)
00000000
EIRR1 (R/W)
00000000
ENIR1 (R/W)
00000000
Ext int
ELVR0 (R/W)
00000000 00000000
ELVR1 (R/W)
00000000 00000000
0000D0H
to
Reserved
0000D8H
DACR2 (R/W)
- - - - - - - 0
DACR1 (R/W)
- - - - - - - 0
DACR0 (R/W)
- - - - - - - 0
0000DCH
0000E0H
0000E4H
0000E8H
D/A Converter
DADR2 (R/W)
XXXXXXXX
DADR1 (R/W)
XXXXXXXX
DADR0 (R/W)
XXXXXXXX
ADCR (R, W)
00101- XX XXXXXXXX
ADCS1 (R/W, W)
00000000
ADCS0 (R/W)
00000000
A/D Converter
(Sequential type)
AICK (R/W)
00000000
Analog Input Control
0000ECH
to
Reserved
0000F0H
(Continued)
28
MB91F155A/MB91155/MB91154
Address
Register
PCRH (R/W)
Block
PCRI (R/W)
- - 000000
PCRD (R/W)
00000000
PCRC (R/W)
00000000
0000F4H
Pull Up Control
- - 000000
OCRI (R/W)
- - 000000
OCRH (R/W)
- - 000000
0000F8H
0000FCH
000100H
000104H
Opendrain Control
DDRF (R/W)
- - - 00000
DDRE (R/W)
00000000
DDRD (R/W)
00000000
DDRC (R/W)
00000000
DDRI (R/W)
- 0000000
DDRH (R/W)
- - 000000
DDRG (R/W)
- - 000000
Data Direction
Register
DDRL (R/W)
00000000
DDRK (R/W)
00000000
000108H
to
00011CH
Reserved
I2C Interface
Reserved
IBCR (R/W)
00000000
IBSR (R)
00000000
IADR (R/W)
- XXXXXXX
ICCR (R/W)
- - 0XXXXX
000120H
000124H
IDAR (R/W)
XXXXXXXX
000128H
to
0001FCH
DPDP (R/W)
- - - - - - - - - - - - - - - - - - - - - - - - - 0000000
000200H
000204H
000208H
00020CH
000210H
000214H
000218H
00021CH
DACSR (R/W)
00000000 00000000 00000000 00000000
DMAC
DATCR (R/W)
XXXXXXXX XXXX0000 XXXX0000 XXXX0000
Reserved
Calendar
CAC (R/W)
00000000
CA1 (R/W)
- - XXXXXX
CA2 (R/W)
- - XXXXXX
CA3 (R/W)
- - - XXXXX
CA4 (R/W)
- - - XXXXX
CA5 (R/W)
- - - - - XXX
CA6 (R/W)
- - - - XXXX
CA7 (R/W)
- XXXXXXX
Reserved
Calendar
CAS (R/W)
0 - - - - - - 0
000220H
to
Reserved
0003ECH
(Continued)
29
MB91F155A/MB91155/MB91154
Address
Register
Block
BSD0 (W)
0003F0H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSD1 (R/W)
0003E4H
0003F8H
0003FCH
000400H
000404H
000408H
00040CH
000410H
000414H
000418H
00041CH
000420H
000424H
000428H
00042CH
000430H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Bit Search Module
BSDC (W)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSRR (R)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ICR00 (R/W)
- - - - 1111
ICR01 (R/W)
- - - - 1111
ICR02 (R/W)
- - - - 1111
ICR03 (R/W)
- - - - 1111
ICR04 (R/W)
- - - - 1111
ICR05 (R/W)
- - - - 1111
ICR06 (R/W)
- - - - 1111
ICR07 (R/W)
- - - - 1111
ICR08 (R/W)
- - - - 1111
ICR09 (R/W)
- - - - 1111
ICR10 (R/W)
- - - - 1111
ICR11 (R/W)
- - - - 1111
ICR12 (R/W)
- - - - 1111
ICR13 (R/W)
- - - - 1111
ICR14 (R/W)
- - - - 1111
ICR15 (R/W)
- - - - 1111
ICR16 (R/W)
- - - - 1111
ICR17 (R/W)
- - - - 1111
ICR18 (R/W)
- - - - 1111
ICR19 (R/W)
- - - - 1111
ICR20 (R/W)
- - - - 1111
ICR21 (R/W)
- - - - 1111
ICR22 (R/W)
- - - - 1111
ICR23 (R/W)
- - - - 1111
Interrupt Control unit
ICR24 (R/W)
- - - - 1111
ICR25 (R/W)
- - - - 1111
ICR26 (R/W)
- - - - 1111
ICR27 (R/W)
- - - - 1111
ICR28 (R/W)
- - - - 1111
ICR29 (R/W)
- - - - 1111
ICR30 (R/W)
- - - - 1111
ICR31 (R/W)
- - - - 1111
ICR32 (R/W)
- - - - 1111
ICR33 (R/W)
- - - - 1111
ICR34 (R/W)
- - - - 1111
ICR35 (R/W)
- - - - 1111
ICR36 (R/W)
- - - - 1111
ICR37 (R/W)
- - - - 1111
ICR38 (R/W)
- - - - 1111
ICR39 (R/W)
- - - - 1111
ICR40 (R/W)
- - - - 1111
ICR41 (R/W)
- - - - 1111
ICR42 (R/W)
- - - - 1111
ICR43 (R/W)
- - - - 1111
ICR44 (R/W)
- - - - 1111
ICR45 (R/W)
- - - - 1111
ICR46 (R/W)
- - - - 1111
ICR47 (R/W)
- - - - 1111
DICR (R/W)
- - - - - - - 0
HRCL (R/W)
- - - - 1111
Delay int
000434H
to
Reserved
00047CH
RSRR/WTCR
(R, W)
1-XXX-00
STCR (R/W, W)
000111- -
PDRR (R/W)
- - - - 0000
CTBR (W)
XXXXXXXX
000480H
000484H
Clock Control unit
(Continued)
GCR (R/W, R)
110011-1
WPR (W)
XXXXXXXX
30
MB91F155A/MB91155/MB91154
Address
Register
Block
PTCR (R/W)
00XX0XXX
000488H
PLL Control
00048CH
to
Reserved
0005FCH
DDR3 (W)
00000000
DDR2 (W)
00000000
000600H
000604H
000608H
00060CH
000610H
000614H
000618H
00061CH
000620H
000624H
000628H
00062CH
000630H
DDR6 (W)
00000000
DDR5 (W)
00000000
DDR4 (W)
00000000
Data Direction
Register
DDR8 (W)
- 0000000
ASR1 (W)
00000000 00000001
AMR1 (W)
00000000 00000000
ASR2 (W)
00000000 00000010
AMR2 (W)
00000000 00000000
ASR3 (W)
00000000 00000011
AMR3 (W)
00000000 00000000
ASR4 (W)
00000000 00000100
AMR4 (W)
00000000 00000000
T-unit
ASR5 (W)
00000000 00000101
AMR5 (W)
00000000 00000000
AMD0 (R/W)
- - - 00111
AMD1 (R/W)
0 - - 00000
AMD32 (R/W)
00000000
AMD4 (R/W)
0 - - 00000
AMD5 (R/W)
0 - - 00000
EPCR0 (W)
- - - - 1100 -1111111
EPCR1 (W)
- - - - - - - - 11111111
Reserved
PCR6 (R/W)
00000000
Pull Up Control
000634H
to
0007BCH
Reserved
FLASH Control
Reserved
FLCR (R/W, R)
000XXXX0
0007C0H
0007C4H
FWTC (R/W, W)
- - - - - 000
0007C8H
to
0007F8H
(Continued)
31
MB91F155A/MB91155/MB91154
(Continued)
Address
Register
Block
Little Endian
Register
Mode Register
LER (W)
- - - - - 000
MODR (W)
XXXXXXXX
0007FCH
Note : Do not execute RMW instructions on registers having a write-only bit.
RMW instructions (RMW : Read Modify Write)
AND
Rj, @Ri
OR
Rj, @Ri
EOR
Rj, @Ri
ANDH Rj, @Ri
ANDB Rj, @Ri
BANDL #u4, @Ri
BANDH #u4, @Ri
ORH Rj, @Ri
ORB Rj, @Ri
BORL #u4, @Ri
BORH #u4, @Ri
EORH Rj, @Ri
EORB Rj, @Ri
BEORL #u4, @Ri
BEORH #u4, @Ri
Data is undefined in “Reserved” or ( ) areas.
( ) : Access
R/W : Read/Write enabled
R :
W :
:
Read only
Write only
Not in use
Undefined
X :
32
MB91F155A/MB91155/MB91154
■ INTERRUPT FACTORS AND ASSIGNMENT OF INTERRUPT VECTORS AND RESISTERS
Interrupt No.
Interrupt
level
Default TBR
address
Factor
Offset
Decimal Hex.
Reset
0
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
3C0H
3BCH
3B8H
3B4H
3B0H
3ACH
3A8H
3A4H
3A0H
39CH
398H
394H
390H
38CH
388H
384H
380H
37CH
378H
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
000FFFE4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
000FFFC0H
000FFFBCH
000FFFB8H
000FFFB4H
000FFFB0H
000FFFACH
000FFFA8H
000FFFA4H
000FFFA0H
000FFF9CH
000FFF98H
000FFF94H
000FFF90H
000FFF8CH
000FFF88H
000FFF84H
000FFF80H
000FFF7CH
000FFF78H
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Undefined instruction exception
Reserved for the system
External interrupt 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
External interrupt 7
External interrupts 8 - 15
Reserved for the system
UART0 (receiving complete)
UART1 (receiving complete)
UART2 (receiving complete)
UART3 (receiving complete)
Reserved for the system
UART0 (sending complete)
UART1 (sending complete)
UART2 (sending complete)
ICR10
ICR11
ICR12
ICR13
ICR15
ICR16
ICR17
(Continued)
33
MB91F155A/MB91155/MB91154
Interrupt No.
Interrupt
level
Default TBR
address
Factor
Offset
Decimal Hex.
UART3 (sending complete)
I2C
34
35
36
37
38
39
40
42
43
44
45
46
47
48
22
23
24
25
26
27
28
2A
2B
2C
2D
2E
2F
30
ICR18
ICR19
ICR20
ICR21
ICR22
ICR23
ICR24
ICR26
ICR27
ICR28
ICR29
ICR30
ICR31
ICR32
374H
370H
36CH
368H
364H
360H
35CH
354H
350H
34CH
348H
344H
340H
33CH
000FFF74H
000FFF70H
000FFF6CH
000FFF68H
000FFF64H
000FFF60H
000FFF5CH
000FFF54H
000FFF50H
000FFF4CH
000FFF48H
000FFF44H
000FFF40H
000FFF3CH
DMAC (End, Error)
Reload timer 0
Reload timer 1
Reload timer 2
Reload timer 3
A/D (sequential type)
PPG0
PPG1
PPG2
PPG3
PPG4
PPG5
U/Dcounter 0
(compare/underflow, overflow, up-down
inversion)
49
50
31
32
ICR33
ICR34
338H
334H
000FFF38H
000FFF34H
U/Dcounter 1
(compare/underflow, overflow, up-down
inversion
ICU0 (Read)
51
52
53
54
55
56
57
58
59
60
61
62
63
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
ICR35
ICR36
ICR37
ICR38
ICR39
ICR40
ICR41
ICR42
ICR43
ICR44
330H
32CH
328H
324H
320H
31CH
318H
314H
310H
30CH
308H
304H
300H
000FFF30H
000FFF2CH
000FFF28H
000FFF24H
000FFF20H
000FFF1CH
000FFF18H
000FFF14
000FFF10H
000FFF0CH
000FFF08H
000FFF04H
000FFF00H
ICU1 (Read)
ICU2 (Read)
ICU3 (Read)
OCU0 (Match)
OCU1 (Match)
OCU2 (Match)
OCU3 (Match)
OCU4/5 (Match)
OCU6/7 (Match)
Reserved for the system
16-bit free-run timer
Delay interrupt factor bit
ICR46
ICR47
(Continued)
34
MB91F155A/MB91155/MB91154
(Continued)
Interrupt No.
Interrupt
level
Default TBR
address
Factor
Offset
Decimal Hex.
Reserved for the system
(used by REALOS*)
64
65
40
41
2FCH
2F8H
000FFEFCH
000FFEF8H
Reserved for the system
(used by REALOS*)
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
Reserved for the system
66
67
68
69
70
71
72
73
74
75
76
77
78
79
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
2F4H
2F0H
2ECH
2E8H
2E4H
2E0H
2DCH
2D8H
2D4H
2D0H
2CCH
2C8H
2C4H
2C0H
000FFEF4H
000FFEF0H
000FFEECH
000FFEE8H
000FFEE4H
000FFEE0H
000FFEDCH
000FFED8H
000FFED4H
000FFED0H
000FFECCH
000FFEC8H
000FFEC4H
000FFEC0H
80
to
50
to
2BCH
to
000FFEBCH
to
Used with the INT instruction
255
FF
000H
000FFC00H
* : REALOS/FR uses 0X40 and 0X41 interrupts for system codes.
35
MB91F155A/MB91155/MB91154
■ PERIPHERAL RESOURCES
1. I/O Port
(1) Port Block Diagram
This LSI is available as an I/O port when the resource associated with each pin is set not to use a pin for input/
output.
The pin level is read from the port (PDR) when it is set for input. When the port is set for output, the value in the
data register is read. The same also applies to reload by read modify write.
When switching from input to output, output data is set in the data register beforehand. However, if a read modify
write instruction (such as bit set) is used at that time, keep in mind that it is the input data from the pin that is
read, not the latch value of the data register.
• Basic I/O Port
Data bus
Resource input
0
1
PDR read
pin
0
PDR
Resource output
1
Resource output
allowed
DDR
PDR : Port Data Register
DDR : Data Direction Register
Figure PORT-1 Basic port block
The I/O port consists of the PDR (Port Data Register) and the DDR (Data Direction Register) .
In input mode (DDR = “0”) → PDR read : Reads the level of the corresponding external pin.
PDR write : Writes the set value to the PDR.
In output mode (DDR = “1”) → PDR read : Reads the PDR value.
PDR write : Outputs the PDR value to the corresponding external pin.
Notes : AIC controls switching between the resource and port of the analog pin (A/D) .
AICK (Analog Input Control register on port-K)
The register controls whether port K should be used for analog input or as a general-purpose port.
0 : General-purpose port
1 : Analog input (A/D)
36
MB91F155A/MB91155/MB91154
• I/O Port (attached with a pullup resistor)
Data bus
Resource input
0
1
Pull-up resister (approx. 50 kΩ)
PDR read
PDR
pin
0
1
Resource output
Resource output
allowed
DDR
PCR
PDR : Port Data Register
DDR : Data Direction Register
PCR : Pull-up Control Register
Figure PORT-2 Port block attached with a pullup resistor
Notes : • Pullup resistor control register (PCR) R/W
Controls turning the pullup resistor on/off.
0 : Pullup resistor disabled
1 : Pullup resistor enabled
• In stop mode priority is also given to the setting of the pullup resistor control register.
• This function is not available when a relevant pin is in use as an external bus pin. Do not write “1” to this
register.
37
MB91F155A/MB91155/MB91154
• I/O Port (attached with the open drain output function and a pullup resistor)
Data bus
Resource input
0
1
PDR read
pin
0
PDR
Resource output
1
Resource output
allowed
DDR
ODCR
PCR
PDR : Port Data Register
DDR : Data Direction Register
ODCR : OpenDrain Control Register
PCR : Pull-up Control Register
Figure PORT-3 Port block attached with the open drain output function and a pullup resistor
Notes : • Pullup resistor setup register (PCR) R/W
Controls turning the pullup resistor on/off.
0 : Pullup resistor disabled
1 : Pullup resistor enabled
• Open drain control register (ODCR) R/W
Controls open drain in output mode.
0 : Standard output port during output mode
1 : Open-drain output port during output mode
This register has no significance in input mode (output Hi-Z) . Input/output mode is determined by the
direction register (DDR) .
• Priority is also given to the setting of the pullup resistor control register in stop mode.
• When a relevant pin is used as an external bus pin, neither function is available. Do not write “1” to either
register.
38
MB91F155A/MB91155/MB91154
• I/O Port (open drain)
Data bus
RMW
Resource output
RMW = 0
Resource input
RMW = 1
pin
PDR read
PDR
PDR : Port Data Register
Figure PORT-4 Port block attached with a pullup resistor
Notes : • When using as an input port or for resource input, set the PDR and resource output to “1.”
• During read by RMW, it is the PDR value that is read, not the pin value.
39
MB91F155A/MB91155/MB91154
(2) Register Descriptions
• Port Data Register (PDR)
PDR2
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 000001H
P27
P26
P25
P24
P23
P22
P21
P20
PDR3
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 000000H
P37
P36
P35
P34
P33
P32
P31
P30
PDR4
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 000007H
P47
P46
P45
P44
P43
P42
P41
P40
PDR5
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 000006H
P57
P56
P55
P54
P53
P52
P51
P50
PDR6
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 000005H
P67
P66
P65
P64
P63
P62
P61
P60
PDR8
Initial value Access
- XXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 00000BH
P86
P85
P84
P83
P82
P81
P80
PDRC
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 000013H
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PDRD
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 000012H
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PDRE
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 000011H
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PDRF
Initial value Access
- - - XXXXXB R/W
7
7
7
7
7
6
6
6
6
6
5
4
3
2
1
0
Address : 000010H
PF4
PF3
PF2
PF1
PF0
PDRG
Initial value Access
- - XXXXXXB R/W
5
4
3
2
1
0
Address : 000017H
PG5
PG4
PG3
PG2
PG1
PG0
PDRH
Initial value Access
- - XXXXXXB R/W
5
4
3
2
1
0
Address : 000016H
PH5
PH4
PH3
PH2
PH1
PH0
PDRI
Initial value Access
- - XXXXXXB R/W
5
4
3
2
1
0
Address : 000015H
PI5
PI4
PI3
PI2
PI1
PI0
PDRJ
Initial value Access
5
4
3
2
1
0
Address : 000014H
- - - - - - 11B
R/W
PJ1
PJ0
PDRK
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 00001BH
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
PDRL
Initial value Access
XXXXXXXXB R/W
7
6
5
4
3
2
1
0
Address : 00001AH
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
PDR2 to PDRL are the I/O data registers of the I/O port.
Input/output is controlled with corresponding DDR2 to DDRL.
R/W : Read/Write enabled, X : Undefined,
: Not in use
40
MB91F155A/MB91155/MB91154
• Data Direction Register (DDR)
DDR2
Initial value Access
7
6
5
4
3
2
1
0
Address : 000601H
00000000B
Initial value Access
00000000B
Initial value Access
00000000B
Initial value Access
00000000B
Initial value Access
00000000B
Initial value Access
- 0000000B
Initial value Access
00000000B R/W
Initial value Access
00000000B R/W
Initial value Access
00000000B R/W
Initial value Access
- - - 00000B R/W
Initial value Access
- - 000000B R/W
Initial value Access
- - 000000B R/W
Initial value Access
- 0000000B R/W
Initial value Access
00000000B R/W
Initial value Access
00000000B R/W
W
P27
P26
P25
P24
P23
P22
P21
P20
DDR3
7
6
5
4
3
2
1
0
Address : 000600H
W
P37
P36
P35
P34
P33
P32
P31
P30
DDR4
7
6
5
4
3
2
1
0
Address : 000607H
W
P47
P46
P45
P44
P43
P42
P41
P40
DDR5
7
6
5
4
3
2
1
0
Address : 000606H
W
P57
P56
P55
P54
P53
P52
P51
P50
DDR6
7
6
5
4
3
2
1
0
Address : 000605H
W
P67
P66
P65
P64
P63
P62
P61
P60
DDR8
7
6
5
4
3
2
1
0
Address : 00060BH
W
P86
P85
P84
P83
P82
P81
P80
DDRC
7
6
5
4
3
2
1
0
Address : 0000FFH
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
DDRD
7
6
5
4
3
2
1
0
Address : 0000FEH
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
DDRE
7
6
5
4
3
2
1
0
Address : 0000FDH
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
DDRF
7
7
7
7
6
6
6
5
4
3
2
1
0
Address : 0000FCH
PF4
PF3
PF2
PF1
PF0
DDRG
5
4
3
2
1
0
Address : 000103H
PG5
PG4
PG3
PG2
PG1
PG0
DDRH
5
4
3
2
1
0
Address : 000102H
PH5
PH4
PH3
PH2
PH1
PH0
DDRI
6
5
4
3
2
1
0
Address : 000101H
TEST
PI5
PI4
PI3
PI2
PI1
PI0
DDRK
7
6
5
4
3
2
1
0
Address : 000107H
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
DDRL
7
6
5
4
3
2
1
0
Address : 000106H
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
DDR2 to DDRL control the I/O direction of the I/O port by bit.
DDR = 0 : Port input
DDR = 1 : Port output
Note : DDRI’s bit 6 is a test bit. Be sure to write “0” to the bit.
“0” is the value that is read.
R/W : Read/Write enabled, W : Write only,
: Not in use
41
MB91F155A/MB91155/MB91154
• Pull-up Control Register (PCR)
PCR6
Initial value Access
00000000B R/W
7
6
5
4
3
2
1
0
Address : 000631H
P67
P66
P65
P64
P63
P62
P61
P60
PCRC
Initial value Access
00000000B R/W
7
6
5
4
3
2
1
0
Address : 0000F7H
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PCRD
Initial value Access
00000000B R/W
7
6
5
4
3
2
1
0
Address : 0000F6H
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PCRH
Initial value Access
- - 000000B R/W
7
7
6
6
5
4
3
2
1
0
Address : 0000F5H
PH5
PH4
PH3
PH2
PH1
PH0
PCRI
Initial value Access
- - 000000B R/W
5
4
3
2
1
0
Address : 0000F4H
PI5
PI4
PI3
PI2
PI1
PI0
PCR6 to PCRI control the pullup resistor when the corresponding I/O port is in input mode.
PCR = 0 : Pullup resistor not available in input mode
PCR = 1 : Pullup resistor available in input mode
The register has no significance in output mode (a pullup resistor not available) .
• Open Drain Control Register (ODCR)
OCRH
Initial value Access
7
6
5
4
3
2
1
0
Address : 0000F9H
- - 000000B R/W
PH5
PH4
PH3
PH2
PH1
PH0
OCRI
Initial value Access
- - 000000B R/W
7
6
5
4
3
2
1
0
Address : 0000F8H
PI5
PI4
PI3
PI2
PI1
PI0
OCRH and OCRI control open drain when the corresponding I/O port is in output mode.
OCR = 0 : Standard output port during output mode
OCR = 1 : Open drain output port during output mode
The register has no significance in input mode (output Hi-z) .
• Analog Input Control Register (AICR)
AICK
Initial value Access
00000000B R/W
7
6
5
4
3
2
1
0
Address : 0000EBH
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
The AICK controls each pin of a corresponding I/O port as follows :
AIC = 0 : Port input mode
AIC = 1 : Analog input mode
The register is reset to “0.”
R/W : Read/Write enabled,
: Not in use
42
MB91F155A/MB91155/MB91154
2. DMA Controller (DMAC)
The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access)
transfer.
DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to en-
hanced performance of the system.
• 8 channels
• Mode : single/block transfer, burst transfer and continuous transfer : 3 kinds of transfer
• Transfer all through the area
• Max. 65536 of transfer cycles
• Interrupt function right after the transfer
• Selectable for address transfer increase/decrease by the software
• External transfer request input pin, external transfer request accept output pin, external transfer complete
output pin three pins for each
• Block Diagram
3
5
3
3
Edge/level
detection circuit
DREQ0 to DREQ2
DACK0 to DACK2
DEOP0 to DEOP2
Interrupt request
3
8
Sequencer
Internal resource
transfer request
Data buffer
Switcher
DPDP
DACSR
DATCR
Mode
BLK DEC
BLK
DMACT
SADR
DADR
INC / DEC
43
MB91F155A/MB91155/MB91154
• Registers (DMAC internal registers)
Address
Initial value
bit 31
bit 16
DPDP
bit 0
00000200H
00000201H
00000202H
00000203H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB (R/W)
X0000000B
00000204H
00000205H
00000206H
00000207H
00000000B
00000000B
DACSR
DATCR
(R/W)
00000000B
00000000B
XXXXXXXXB
00000208H
00000209H
0000020AH
0000020BH
XXXX0000B
(R/W)
XXXX0000B
XXXX0000B
(
) : Access
R/W : Read/Write enabled
: Undefined
X
• Register (DMA descriptor)
Address
bit 31
bit 0
DMA
ch0
DPDP + 0H
Descriptor
DMA
DPDP + 0CH
ch1
Descriptor
DPDP + 54H
DMA
ch7
Descriptor
44
MB91F155A/MB91155/MB91154
3. UART
The UART is a serial I/O port for asynchronous (start and stop synchronization) communication or CLK syn-
chronous communication. This product type contains this UART for four channels. Its features are as follows :
• Full-duplex double buffer
• Capable of asynchronous (start and stop synchronization) and CLK synchronous communication.
• Support for multiprocessor mode
• Baud rate by a dedicated baud rate generator
• Baud rate by an internal timer
The baud rate can be set with a 16-bit reload timer.
• Any baud rate can be set using an external clock.
• Error detection function (parity, framing, and overrun)
• NRZ-encoded transfer signals
• DMA transfer can be invoked by interrupt.
45
MB91F155A/MB91155/MB91154
• Block Diagram
Control bus
Receive
interrupt signal
#26 to 29 *
Dedicated baud rate
generator
Send
interrupt signal
#31 to 34 *
Send clock
Clock
16-bit reload timer
selector
Receive clock
(SCK0 to SCK3)
Pin
Receiving
control circuit
Sending
control circuit
Start bit
Sending start
detection circuit
circuit
Receive bit
counter
Send bit
counter
(SOT0 to SOT3)
Pin
Receive parity
counter
Send parity
counter
(SIN0 to SIN3)
Pin
Receive
shift register
Send
shift register
Received status
determination circuit
Sending start
Reception
error
SIDR0 to SIDR3
SODR0 to SODR3
Generated signals
(to the CPU)
Internal data bus
MD1
MD0
CS2
CS1
CS0
PEN
P
SBL
CL
A/D
REC
RXE
TXE
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
SMR 0 - 3
registers
SCR 0 - 3
registers
SSR 0 - 3
registers
SCKE
SOE
TIE
* : Interrupt numbers
46
MB91F155A/MB91155/MB91154
• Register List
Address
Initial value
bit 15
bit 8
bit 0
0000001EH
00000022H
00000026H
0000002AH
0000001FH
00000023H
00000027H
0000002BH
0000001CH
00000020H
00000024H
00000028H
0000001DH
00000021H
00000025H
00000029H
SCR0
SCR1
SCR2
SCR3
00000100B (R/W, W)
00000100B (R/W, W)
00000100B (R/W, W)
00000100B (R/W, W)
00000-00B (R/W)
00000-00B (R/W)
00000-00B (R/W)
00000-00B (R/W)
00001000B (R, R/W)
00001000B (R, R/W)
00001000B (R, R/W)
00001000B (R, R/W)
XXXXXXXXB (R, W)
XXXXXXXXB (R, W)
XXXXXXXXB (R, W)
XXXXXXXXB (R, W)
SMR0
SMR1
SMR2
SMR3
SSR0
SSR1
SSR2
SSR3
SIDR0/SODR0
SIDR1/SIDR1
SIDR2/SIDR2
SIDR3/SIDR3
(
) : Access
R/W : Read/Write enabled
R : Read only
W : Write only
: Not in use
X : Undefined
47
MB91F155A/MB91155/MB91154
4. PPG Timer
The PPG timer can output highly accurate PWM waveforms efficiently.
This device contains six PPG timer channels and its features are as follows :
• Each channel consists of a 16-bit down counter, a 16-bit data register attached with a frequency setting buffer,
a 16-bit compare register attached with a duty setting buffer, and a pin controller.
• The count clock for the 16-bit down counter can be selected from the following four types :
Internal clocks φ, φ/4, φ/16, and φ/64
• The counter value can be initialized by reset or counter borrow to “FFFFH.”
• PWM output (by channel)
• DMA transfer can be invoked by interrupt.
• Block Diagram (Entire configuration)
TRG input
PWM timer channel 0
16-bit reload timer
channel 0
PWM0
PWM1
TRG input
PWM timer channel 1
16-bit reload timer
channel 1
General control
register 1
(Factor selection)
TRG input
PWM2
4
4
PWM timer channel 2
General control
register 2
TRG input
PWM timer channel 3
PWM3
PWM4
External TRG 0 to 3
External TRG4
TRG input
PWM timer channel 4
TRG input
PWM timer channel 5
PWM5
External TRG5
48
MB91F155A/MB91155/MB91154
• Block Diagram (for one channel)
PCSR
PDUT
Prescaler
1 / 1
cmp
Load
1 / 4
1 / 16
1 / 64
ck
16-bit down counter
Start
Borrow
PPG mask
S
R
Q
PWM output
Peripheral system clock
Inverse bit
Enable
IRQ
Interrupt
selection
Edge
TRG input
detection
Soft trigger
49
MB91F155A/MB91155/MB91154
• Register List
Address
Initial value
bit 15
bit 8
bit 0
00000094H
00000095H
00110010B
00010000B
GCN1
(R/W)
00000097H
00000000B (R/W)
GCN2
PCNL0
PCNL1
PCNL2
PCNL3
00000098H
00000099H
11111111B
(R )
PTMR0
PCSR0
PDUT0
11111111B
0000009AH
0000009BH
XXXXXXXXB
(W)
XXXXXXXXB
0000009CH
0000009DH
XXXXXXXXB
(W)
XXXXXXXXB
0000009EH
0000009FH
PCNH0
PCNH1
PCNH2
PCNH3
0000000-B (R/W)
00000000B (R/W)
000000A0H
000000A1H
11111111B
(R)
PTMR1
PCSR1
PDUT1
11111111B
000000A2H
000000A3H
XXXXXXXXB
(W)
XXXXXXXXB
000000A4H
000000A5H
XXXXXXXXB
(W)
XXXXXXXXB
000000A6H
000000A7H
0000000-B (R/W)
00000000B (R/W)
000000A8H
000000A9H
11111111B
(R)
PTMR2
PCSR2
PDUT2
11111111B
000000AAH
000000ABH
XXXXXXXXB
(W)
XXXXXXXXB
000000ACH
000000ADH
XXXXXXXXB
(W)
XXXXXXXXB
000000AEH
000000AFH
0000000-B (R/W)
00000000B (R/W)
000000B0H
000000B1H
11111111B
(R)
PTMR3
PCSR3
PDUT3
11111111B
000000B2H
000000B3H
XXXXXXXXB
(W)
XXXXXXXXB
000000B4H
000000B5H
XXXXXXXXB
(W)
XXXXXXXXB
000000B6H
0000000-B (R/W)
000000B7H
00000000B (R/W)
(
) : Access R/W : Read/Write enabled R : Read only W : Write only
: Not in use X : Undefined
(Continued)
50
MB91F155A/MB91155/MB91154
(Continued)
Address
Initial value
bit 15
bit 8
bit 0
000000B8H
000000B9H
11111111B
11111111B
PTMR4
(R )
(W)
(W)
000000BAH
000000BBH
XXXXXXXXB
XXXXXXXXB
PCSR4
PDUT4
000000BCH
000000BDH
XXXXXXXXB
XXXXXXXXB
000000BEH
000000BFH
PCNH4
0000000-B (R/W)
00000000B (R/W)
PCNL4
000000C0H
000000C1H
11111111B
(R)
PTMR5
PCSR5
PDUT5
11111111B
000000C2H
000000C3H
XXXXXXXXB
(W)
XXXXXXXXB
000000C4H
000000C5H
XXXXXXXXB
(W)
XXXXXXXXB
000000C6H
000000C7H
PCNH5
0000000-B (R/W)
00000000B (R/W)
PCNL5
(
) : Access
R : Read only
: Not in use
R/W : Read/Write enabled
W : Write only
X : Undefined
51
MB91F155A/MB91155/MB91154
5. 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a prescaler for creating internal
count clocks, and a control register.
The input clock can be selected from three internal clock types (2/8/32 machine clock divisions) .
DMA transfer can be invoked by interrupt.
This product type contains this 16-bit reload timer for four channels.
• Block Diagram
16
16-bit reload register
8
Reload
RELD
16
OUTE
OUTL
INTE
UF
16-bit down counter
UF
2
OUT
CTL.
GATE
2
IRQ
CSL1
Clock selector
CNTE
TRG
CSL0
2
Retrigger
IN CTL.
EXCK
PWM (ch0, ch1)
A/D (ch2)
3
φ
φ
φ
Clear
prescaler
21 23 25
MOD2
MOD1
MOD0
Internal clocks
3
52
MB91F155A/MB91155/MB91154
• Register List
Address
Initial value
bit 15
bit 0
00000032H
00000033H
- - - - 0 0 0 0 B
00000000B
TMCSR0
TMCSR1
TMCSR2
TMCSR3
TMR0
(R/W)
(R/W)
(R/W)
(R/W)
(R)
0000003AH
0000003BH
- - - - 0 0 0 0 B
00000000B
00000042H
00000043H
- - - - 0 0 0 0 B
00000000B
0000004AH
0000004BH
- - - - 0 0 0 0 B
00000000B
0000002EH
0000002FH
XXXXXXXXB
XXXXXXXXB
00000036H
00000037H
XXXXXXXXB
XXXXXXXXB
TMR1
(R)
0000003EH
0000003FH
XXXXXXXXB
XXXXXXXXB
TMR2
(R)
00000046H
00000047H
XXXXXXXXB
XXXXXXXXB
TMR3
(R)
0000002CH
0000002DH
XXXXXXXXB
XXXXXXXXB
TMRLR0
TMRLR1
TMRLR2
TMRLR3
(W)
00000034H
00000035H
XXXXXXXXB
XXXXXXXXB
(W)
0000003CH
0000003DH
XXXXXXXXB
XXXXXXXXB
(W)
00000044H
00000045H
XXXXXXXXB
XXXXXXXXB
(W)
(
) : Access
R/W : Read/Write enabled
R : Read only
W : Write only
: Not in use
X : Undefined
53
MB91F155A/MB91155/MB91154
6. Bit Search Module
The module searches data written to the input register for “0” or “1” or a “change” and returns the detected bit
position.
• Block Diagram
Input latch
Address
decoder
Detection
mode
Changing one detection into data
Bit search circuit
Search results
• Register List
Address
Initial value
bit 31
bit 16
BSD0
bit 0
000003F0H
000003F1H
000003F2H
000003F3H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB (W)
XXXXXXXXB
000003F4H
000003F5H
000003F6H
000003F7H
XXXXXXXXB
XXXXXXXXB
BSD1
BSDC
BSRR
(R/W)
XXXXXXXXB
XXXXXXXXB
000003F8H
000003F9H
000003FAH
000003FBH
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(W)
(R)
000003FCH
000003FDH
000003FEH
000003FFH
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(
) : Access
W : Write only
R/W : Read/Write enabled R : Read only
X : Undefined
54
MB91F155A/MB91155/MB91154
7. 8/10-bit A/D Converter (Sequential Conversion Type)
The A/D converter is a module that converts analog input voltage into a digital value. Its features are as follows :
• A minimum conversion time of 5.0 µs/ch. (Including sampling time at a 33 MHz machine clock)
• Contains a sample and hold circuit.
• Resolution : 10 or 8 bits selectable.
• Selection of analog input from eight channels by program
Single conversion mode :
Continuous conversion mode : Converts a specified channel repeatedly.
Stop and convert mode : Stops after converting one channel and stands by until invoked the next time.
(Conversion invoking can be synchronized.)
Selects and converts one channel.
• DMA transfer can be invoked by interrupt.
• Selection of an invoking factor from software, external pin trigger (falling edge) , and 16-bit reload timer (rising
edge) .
• Block Diagram
AVSS AVR± AVSS
MP
D/A converter
AN0
AN1
AN2
Sequential compare
register
AN3
AN4
AN5
AN6
AN7
Input
circuit
Comparator
Sample & hold circuit
Data register
ADCR
A/D control register 1
A/D control register 2
16-bit reload timer 2
External pin trigger
ADCS1, 2
Operating clock
Prescaler
φ
55
MB91F155A/MB91155/MB91154
• Register List
bit 15
bit 0
000000E4H
000000E5H
00101-XXB (W, R)
XXXXXXXXB (R)
ADCR
000000E6H
000000E7H
000000EBH
ADCS1
00000000B (R/W, W)
00000000B (R/W)
00000000B (R/W)
ADCS0
AICK
(
) : Access
R/W : Read/Write enabled
R : Read only
W : Write only
: Not in use
X : Undefined
56
MB91F155A/MB91155/MB91154
8. Interrupt Controller
The interrupt controller accepts and arbitrates interrupts.
• Block Diagram
INT0*2
OR
IM
Priority determination
5
5
LEVEL4
NMI*6
NMI processing
to LEVEL0*4
4
Request to
withdraw
HLDREQ
HLDCAN*3
Level
determination
ICR00
RI00
6
6
VCT5
Vector
determination
.
.
.
.
.
.
.
.
to VCT0*5
ICR47
RI47
DLYI*1
(DLYIRQ)
R bus
*1 : DLY1 represents the delay interrupt module (delay interrupt generator) . (For detailed information, see
section 10, “Delay Interrupt Module.”
*2 : INT0 is a wake-up signal for the clock controller in sleep or stop mode.
*3 : HLDCAN is a bus surrender request signal for bus masters except for the CPU.
*4 : LEVEL 4 - 0 are interrupt level outputs.
*5 : VCT 5 - 0 are interrupt vector outputs.
*6 : This product type does not have the NMI function.
57
MB91F155A/MB91155/MB91154
• Register List
Address
Initial value
Address
Initial value
bit 7
bit 0
bit 7
bit 0
00000400H
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
ICR16
ICR17
ICR18
ICR19
- - - - 1 1 1 1 B (R/W) 00000414H
- - - - 1 1 1 1 B (R/W) 00000415H
- - - - 1 1 1 1 B (R/W) 00000416H
- - - - 1 1 1 1 B (R/W) 00000417H
- - - - 1 1 1 1 B (R/W) 00000418H
- - - - 1 1 1 1 B (R/W) 00000419H
- - - - 1 1 1 1 B (R/W) 0000041AH
- - - - 1 1 1 1 B (R/W) 0000041BH
- - - - 1 1 1 1 B (R/W) 0000041CH
- - - - 1 1 1 1 B (R/W) 0000041DH
- - - - 1 1 1 1 B (R/W) 0000041EH
- - - - 1 1 1 1 B (R/W) 0000041FH
- - - - 1 1 1 1 B (R/W) 00000420H
- - - - 1 1 1 1 B (R/W) 00000421H
- - - - 1 1 1 1 B (R/W) 00000422H
- - - - 1 1 1 1 B (R/W) 00000423H
- - - - 1 1 1 1 B (R/W) 00000424H
- - - - 1 1 1 1 B (R/W) 00000425H
- - - - 1 1 1 1 B (R/W) 00000426H
- - - - 1 1 1 1 B (R/W) 00000427H
ICR20
ICR21
ICR22
ICR23
ICR24
ICR25
ICR26
ICR27
ICR28
ICR29
ICR30
ICR31
ICR32
ICR33
ICR34
ICR35
ICR36
ICR37
ICR38
ICR39
- - - - 1 1 1 1 B (R/W)
00000401H
00000402H
00000403H
00000404H
00000405H
00000406H
00000407H
00000408H
00000409H
0000040AH
0000040BH
0000040CH
0000040DH
0000040EH
0000040FH
00000410H
00000411H
00000412H
00000413H
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
(
) : Access
R/W : Read/Write enabled
: Not in use
(Continued)
58
MB91F155A/MB91155/MB91154
(Continued)
Address
Initial value
bit 7
bit 0
00000428H
ICR40
ICR41
ICR42
ICR43
ICR44
ICR45
ICR46
ICR47
HRCL
DICR
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - 1 1 1 1 B (R/W)
- - - - - - - 0 B (R/W)
00000429H
0000042AH
0000042BH
0000042CH
0000042DH
0000042EH
0000042FH
00000431H
00000430H
(
) : Access
R/W : Read/Write enabled
: Not in use
59
MB91F155A/MB91155/MB91154
9. External Interrupt
The external interrupt controller controls external interrupt requests input to INT pins 0 through 15.
The level of requests to be detected can be selected from “H, ” “L, ” rising edge, and falling edge.
• Block Diagram
16
Interrupt permission register
16
16
32
16
Interrupt
request
Edge detection
circuit
Gate
Factor F/F
INT0 to INT15
Interrupt factor register
Request level setting register
• Register List
Address
Initial value
bit 15
bit 8
bit 0
000000C8H
000000C9H
00000000B
00000000B
EIRR0
EIRR1
ENIR0
ENIR1
(R/W)
(R/W)
(R/W)
(R/W)
000000CAH
000000CBH
00000000B
00000000B
000000CCH
000000CDH
00000000B
00000000B
ELVR0
ELVR1
000000CEH
000000CFH
00000000B
00000000B
(
) : Access
R/W : Read/Write enabled
10. Delay Interrupt Module
The delay interrupt is a module that generates task switching interrupts. The use of this module allows the
software to generate/cancel interrupt requests to the CPU.
For the block diagram of the delay interrupt module, see section 8, “Interrupt Controller.”
• Register List
Address
Initial value
bit 7
bit 0
00000430H
- - - - - - - 0 B (R/W)
DICR
(
) : Access
R/W : Read/Write enabled
: Not in use
60
MB91F155A/MB91155/MB91154
11. Clock Generator (Low power consumption mechanism)
The clock generator is responsible for the following functions :
• CPU clock generation (including the gear function)
• Peripheral clock generation (including the gear function)
• Reset generation and holding factors
• Standby function (including hardware standby)
• Contains PLL (multiplication circuit)
• Block Diagram
[Gear controller]
GCR register
CPU gear
Peripheral
gear
CPU Clock
Internal bus clock
1/2
Internal clock
generating
circuit
M
P
X
X0
X1
Internal
peripheral clock
Oscillator
circuit
PLL
[Stop/sleep controller]
Internal interrupt
Internal reset
STCR register
PDRR register
Stop state
Sleep state
CPU Hold request
DMA request
Status
transition
control
circuit
Reset
generating
F/F
Internal reset
Power on
detection circuit
VCC
[Reset factor circuit]
RSRR register
R
GND
RST pin
[Watchdog controller]
WPR register
Watchdog F/F
Count clock
CTBR register
Timebase timer
61
MB91F155A/MB91155/MB91154
• Register List
Address
Initial value
bit 15
RSRR/WTCH
bit 8
bit 0
00000480H
1-XXX-00B (R, W)
00000481H
00000482H
000111--B
----0000B
(R/W, W)
(R/W)
STCR
CTBR
WPR
PDRR
GCR
00000483H
00000484H
00000485H
XXXXXXXXB (W)
110011-1B (R/W, R)
XXXXXXXXB (W)
(
) : Access
R/W : Read/Write enabled
R : Read only
W : Write only
: Not in use
X : Undefined
62
MB91F155A/MB91155/MB91154
12. External Bus Interface
The external bus interface controls the interface between the external memory and the external I/O. Its features
are as follows :
• 24-bit (16 MB) address output
• An 8/16-bit bus width can be set by chip select area.
• Inserts an automatic and programmable memory wait (for seven cycles at maximum) .
• Unused addresses/data pins are available as I/O ports.
• Support for little endian mode
• Use of a clock doubler, 33 MHz internal and 16.5 MHz external bus operations
• Block Diagram
A-Out
M
U
X
External DATA Bus
Write
buffer
Switch
Switch
Read
buffer
DATA BLOCK
ADDRESS BLOCK
+1 or +2
Address
buffer
External
Address Bus
Shifter
Inpage
4
CS0 to CS3
Comparator
ASR
AMR
3
4
RD
WR0, WR1
External pin controller
Controls all blocks.
Registers
&
Control
BRQ
BGRNT
RDY
CLK
63
MB91F155A/MB91155/MB91154
• Register List
Address
Initial value
bit 31
bit 16
bit 0
0000060CH
0000060DH
00000000B
00000001B
ASR1
ASR2
ASR3
ASR4
ASR5
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
0000060EH
0000060FH
00000000B
00000000B
AMR1
AMR2
AMR3
AMR4
AMR5
00000610H
00000611H
00000000B
00000010B
00000612H
00000613H
00000000B
00000000B
00000614H
00000615H
00000000B
00000011B
00000616H
00000617H
00000000B
00000000B
00000000B
00000100B
00000618H
00000619H
0000061AH
0000061BH
00000000B
00000000B
00000000B
00000101B
0000061CH
0000061DH
(W)
(W)
0000061EH
0000061FH
00000000B
00000000B
00000620H
00000621H
00000622H
00000623H
00000624H
AMD0
- - - 0 0 1 1 1 B (R/W)
0 - - 0 0 0 0 0 B (R/W)
00000000B (R/W)
0 - - 0 0 0 0 0 B (R/W)
0 - - 0 0 0 0 0 B (R/W)
AMD1
AMD32
AMD4
AMD5
00000628H
00000629H
- - - - 1 1 0 0 B
(W)
EPCR0
-1111111B
0000062AH
0000062BH
- - - - - - - - B
(W)
EPCR1
11111111B
000007FEH
000007FFH
LER
- - - - - 0 0 0 B (W)
XXXXXXXXB (W)
MODR
(
) : Access
R/W : Read/Write enabled
W : Write only
: Not in use
X : Undefined
64
MB91F155A/MB91155/MB91154
13. Multifunction Timer
The multifunction timer unit consists of one 16-bit free-run timer, eight 16-bit output compare registers, four 16-
bit input capture registers, and six 16-bit PPG timer channels. By using this function waveforms can be output
based on the 16-bit free-run timer and the input pulse width and external clock cycle can also be measured.
• Timer Components
• 16-bit free-run timer ( × 1)
The 16-bit free-run timer consists of a 16-bit up counter, a control register, a 16-bit compare clear register,
and a prescaler. The output value of this counter is used as the basic time (base timer) for output compare
and input capture.
• Output compare ( × 8)
The output compare consists of eight 16-bit compare registers, a compare output latch, and a control register.
When the 16-bit free-run timer value agrees to the compare register value, the output level can be inverted
and an interrupt can also be generated.
• Input capture ( × 4)
The input capture consists of capture registers corresponding to four independent external input pins and a
control register. By detecting any edge of signals input from external input pins, the 16-bit free-run timer value
can be held in the capture register and an interrupt can be generated at the same time.
• 16-bit PPG timer ( × 6)
See the section on the PPG Timer.
65
MB91F155A/MB91155/MB91154
• Block Diagram
φ
Interrupt
IVF
IVFE STOP MODE SCLR CLK2
CLK1 CLK0
Divider
Clock
16-bit free-run timer
16-bit compare clear register
(Channel 6's compare register)
Interrupt
Compare circuit
Compare register 0/2/4/6
MS13 to 0
ICLR
Q
ICRE
T
T
OC0/2/4/6
Compare circuit
Compare register 1/3/5/7
CMOD
Select
Q
OC1/3/5/7
Compare circuit
IOP1
IOP0
IOE1
IOE0
Interrupt
Interrupt
IN 0/2
Capture register 0/2
Edge detection
EG11 EG10
EG01 EG00
Capture register 1/3
IN 1/3
Edge detection
ICP0
ICP1
ICE0
ICE1
Interrupt
Interrupt
66
MB91F155A/MB91155/MB91154
• Register List
Address
Initial value
bit15
bit8 bit7
IPCP1
bit0
000068H
000069H
XXXXXXXXB ( R )
XXXXXXXXB ( R )
00006AH
00006BH
XXXXXXXXB ( R )
XXXXXXXXB ( R )
IPCP0
IPCP3
IPCP2
00006CH
00006DH
XXXXXXXXB ( R )
XXXXXXXXB ( R )
00006EH
00006FH
XXXXXXXXB ( R )
XXXXXXXXB ( R )
000071H
000073H
00000000B ( R/W )
00000000B ( R/W )
ICS23
ICS01
000074H
000075H
XXXXXXXXB ( R/W )
XXXXXXXXB ( R/W )
OCCP1
OCCP0
OCCP3
OCCP2
000076H
000077H
XXXXXXXXB ( R/W )
XXXXXXXXB ( R/W )
000078H
000079H
XXXXXXXXB ( R/W )
XXXXXXXXB ( R/W )
00007AH
00007BH
XXXXXXXXB ( R/W )
XXXXXXXXB ( R/W )
00007CH
00007DH
XXXXXXXXB ( R/W )
XXXXXXXXB ( R/W )
OCCP5
OCCP4
OCCP7
OCCP6
OCS3,2
OCS1,0
OCS7,6
OCS5,4
TCDT
00007EH
00007FH
XXXXXXXXB ( R/W )
XXXXXXXXB ( R/W )
000080H
000081H
XXXXXXXXB ( R/W )
XXXXXXXXB ( R/W )
000082H
000083H
XXXXXXXXB ( R/W )
XXXXXXXXB ( R/W )
000084H
000085H
XXX00000B ( R/W )
0000XX00B ( R/W )
000086H
000087H
XXX00000B ( R/W )
0000XX00B ( R/W )
000088H
000089H
XXX00000B ( R/W )
0000XX00B ( R/W )
00008AH
00008BH
XXX00000B ( R/W )
0000XX00B ( R/W )
00008CH
00008DH
00000000B ( R/W )
00000000B ( R/W )
00008EH
00008FH
0 - - - - - - - B ( R/W )
00000000B ( R/W )
TCCS
(
) : Access R/W : Read/Write enabled R : Read only
: Not in use X : Undefined
67
MB91F155A/MB91155/MB91154
14. Calendar Macro
This macro is a calendar macro with a basic clock of 32.768 kHz.
The macro accomplishes clock functions including, year, month, date, hour, minutes, seconds, day of the week,
and leap years.
The macro counts the last two digits of calendar years 0 through 99.
• Block Diagram
Oscillator
Calendar circuit
32 kHz
D
Bus
controller
b
u
s
• Register List
Address
Initial value
bit15
bit8
bit17
bit0
000210H
000211H
00000000B ( R/W )
- - XXXXXXB ( R/W )
CAC
CA2
CA4
CA6
CA1
000212H
000213H
- - XXXXXXB ( R/W )
- - - XXXXXB ( R/W )
CA3
CA5
CA7
CAS
000214H
000215H
- - -XXXXXB ( R/W )
- - - - - XXXB ( R/W )
000216H
000217H
- - - - XXXXB ( R/W )
- XXXXXXXB ( R/W )
00021FH
0 - - - - - - 0B ( R/W )
(
) : Access
R/W : Read/Write enabled
: Not in use
X : Undefined
68
MB91F155A/MB91155/MB91154
15. I2C Interface
The I2C interface is a serial I/O port that supports the Inter IC BUS and operates as a master/slave device on
the I2C bus.
• Features of the I2C Interface
Contains one I2C interface channel.
The interface has the following features :
• Master/slave send and receive
• Arbitration function
• Clock synchronization function
• Slave address/general call address detection function
• Transfer direction detection function
• Repeated generation and detection of start conditions
• Bus error detection function
• Register List
• Bus control register (IBCR)
Address
Initial value
00000000B
bit 15
BER
bit 14
BEIE
bit 13
SCC
bit 12
MSS
bit 11
ACK
bit 10
bit 9
bit 8
INT
0000-0120H
GCAA
INTE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Bus status register (IBSR)
Address
Initial value
00000000B
bit 7
bit 6
bit 5
AL
bit 3
TR
bit 2
AAS
bit 1
bit 0
FBT
bit 4
LRB
0000-0121H
BB
RSC
GCA
R
R
R
R
R
R
R
R
• Address register (IADR)
Address
Initial value
bit 15
bit 14
A6
bit 13
A5
bit 12
A4
bit 11
A3
bit 10
A2
bit 9
A1
bit 8
A0
0000-0122H
- XXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Clock control register (ICCR)
Address
Initial value
- -0XXXXXB
bit 7
bit 6
bit 5
EN
bit 4
CS4
bit 3
CS3
bit 2
CS2
bit 1
CS1
bit 0
CS0
0000-0123H
R/W
R/W
R/W
R/W
R/W
R/W
• Data register (IDAR)
Address
Initial value
bit 7
bit 6
D6
bit 5
D5
bit 4
D4
bit 3
D3
bit 2
D2
bit 1
D1
bit 0
D0
0000-0125H
XXXXXXXXB
D7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Read/Write enabled, R : Read only,
: Not in use, X : Undefined
69
MB91F155A/MB91155/MB91154
• Block Diagram
ICCR
I2C enable
EN
Peripheral clock
Clock division 1
5
6
7
8
ICCR
Clock selection 1
CS4
CS3
Clock division 2
8 16 32 64 128 256
CS2
CS1
CS0
2
4
Sync
Shift clock generation
Clock selection 2
Shift clock
edge variation timing
IBSR
BB
Bus busy
Repeat start
Last Bit
RSC
LRB
TR
Start/stop condition detection
Error
Send/Receive
First Byte
FBT
AL
Arbitration lost detection
IBCR
BER
SCL
SDA
BEIE
INTE
INT
Interrupt request
IRQ
IBCR
SCC
End
Start
Master
MSS
ACK
Start/stop condition detection
ACK permission
GC-ACK permission
GCAA
IDAR
IBSR
AAS
Slave
Slave address
comparison
Global call
GCA
IADR
70
MB91F155A/MB91155/MB91154
16. FLASH Memory
The MB91F155A contains a 510-Kbyte (4 Mbits) flash memory. The sectors can be erased all at once or sector
by sector and that can be written with the FR-CPU by half word (16 bits) using a single 0.3 V power supply.
The MB91F155 accomplishes the following functions by a combination of the flash memory macro and the FR-
CPU interface circuit :
• Functions as the CPU program/data storage memory :
When used as a ROM, the memory is accessible with a 32-bit bus width.
Allows the CPU to read from/write to/erase the memory (automatic program algorithm*) .
• Functions equivalent to the stand-alone MBM29LV400C flash memory product :
Allows a ROM programmer to read from/write to/erase the memory (automatic program algorithm*)
At this time, using the flash memory from the FR-CPU is described. For detailed information about using the
flash memory from the ROM programmer, refer to the ROM programmer instruction manual.
* : Automatic program algorithm = Embedded AlgorithmTM
Embedded AlgorithmTM is a trademark of Advanced Micro Devices, Inc.
• Block Diagram
RDY/BUSY
RESET
Rising edge detection
Control signal
generation
BYTE
OE
Flash memory
WE
CE
FA18 - 0
DI15 - 0 DO31 - 0
Address buffer
Data buffer
CD31 - 0
INTE
RDYINT
RDY
WE
CA18 - 0
FR-C bus (instructions/data)
71
MB91F155A/MB91155/MB91154
• Memory Map
Flash memory address mapping varies between FLASH memory mode and CPU mode. Mapping in each mode
is shown next.
Memory mapping in FLASH memory mode of MB91F155A :
0FFFFFH
SA13
SA12
SA11
FLASH
memory image
SA10
SA9
SA8
SA7
07FFFFH
SA6
SA5
SA4
FLASH memory mode
SA3
SA2
010000H
SA1
SA0
( SAn : sector address n )
000000H
Memory mapping in CPU mode of MB91F155A :
0FFFFFH
0FFFFFH
SA6
SA5
SA13
SA12
0F8000H
0F4000H
0F0000H
SA4
SA3
SA11
SA10
FLASH memory area
0E0000H
SA2
SA1
SA0
SA9
SA8
SA7
0C0000H
080800H
080000H
RAM area 2 Kbytes
Status register
0A0000H
CPU mode
0007C0H
000000H
080800H
080000H
( SAn : sector address n )
72
MB91F155A/MB91155/MB91154
• Sector Address Table
Corresponding bit
Sector address
Address range
080802, 3H to 09FFFE, FH (16 bits on LSB side)
Sector capacity
positions
bit15 to 0
bit15 to 0
bit15 to 0
bit15 to 0
bit15 to 0
bit15 to 0
bit15 to 0
bit31 to 16
bit31 to 16
bit31 to 16
bit31 to 16
bit31 to 16
bit31 to 16
bit31 to 16
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA0
SA1
SA2
SA3
SA4
SA5
SA6
64 Kbyte
64 Kbyte
64 Kbyte
32 Kbyte
8 Kbyte
0A0002, 3H to 0BFFFE, FH (16 bits on LSB side)
0C0002, 3H to 0DFFFE, FH (16 bits on LSB side)
0E0002, 3H to 0EFFFE, FH (16 bits on LSB side)
0F0002, 3H to 0F3FFE, FH (16 bits on LSB side)
0F4002, 3H to 0F7FFE, FH (16 bits on LSB side)
0F8002, 3H to 0FFFFE, FH (16 bits on LSB side)
080800, 1H to 09FFFC, DH (16 bits on MSB side)
0A0000, 1H to 0BFFFC, DH (16 bits on MSB side)
0C0000, 1H to 0DFFFC, DH (16 bits on MSB side)
0E0000, 1H to 0EFFFC, DH (16 bits on MSB side)
0F0000, 1H to 0F3FFC, DH (16 bits on MSB side)
0F4000, 1H to 0F7FFC, DH (16 bits on MSB side)
0F8000, 1H to 0FFFFC, DH (16 bits on MSB side)
8 Kbyte
16 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
32 Kbyte
8 Kbyte
8 Kbyte
16 Kbyte
• Registers
FLCR : Status register (CPU mode)
This register indicates the FLASH memory operating status. The register controls interrupts to the CPU as well
as writing to the FLASH memory.
This register is accessible only in CPU mode. Do not access this register with read modify write instructions.
bit 7
bit 6
bit 5
WE
bit 4
bit 3
bit 2
bit 1
bit 0
LPM
INTE RDYINT
RDY
0007C0H
R/W
( 0 )
R/W
( 0 )
R/W
( 0 )
R
( X )
R/W
( 0 )
( X )
( X )
( X )
R/W : Read/Write enabled, R : Read only,
: Not in use, X : Undefined
FWTC : Wait register
This register controls waiting for the FLASH memory in CPU mode.
The register also controls accessing to read from the FLASH memory (33 MHz operations) at high speeds.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FACH WTC1 WTC0
0007C4H
W
( 0 )
R/W
( 0 )
R/W
( 0 )
(
)
(
)
(
)
(
)
(
)
R/W : Read/Write enabled, W : Write only,
: Not in use, X : Undefined
73
MB91F155A/MB91155/MB91154
17. 8-bit D/A Converter
This block is of an 8-bit resolution, R-2R D/A converter. The block contains three D/A converter channels and
each D/A control register can control output independently.
The D/A converter pin is a dedicated pin.
• Block Diagram
R − BUS
DA27 DA20
DA17 DA10
DA07 DA00
DAVC
DAVC
DAVC
DA27
DA17
DA07
DA20
DA10
DA00
DAE2
Standby control
DAE1
Standby control
DAE0
Standby control
D/A output channel 2
D/A output channel 1
D/A output channel 0
74
MB91F155A/MB91155/MB91154
• Register List
Initial value
bit
DADR0
00000E3H
7
6
5
4
3
2
1
0
DA07
DA06
DA05
DA04
DA03
DA02
DA01
DA00
XXXXXXXXB ( R/W )
bit
DADR1
15
14
13
12
11
10
9
8
DA17
DA16
DA15
DA14
DA13
DA12
DA11
DA10
XXXXXXXXB ( R/W )
XXXXXXXXB ( R/W )
00000E2H
bit
DADR2
00000E1H
23
22
21
20
19
18
17
16
DA27
DA26
DA25
DA24
DA23
DA22
DA21
DA20
bit
DACR0
7
6
5
4
3
2
1
9
0
DAE0
- - - - - - - 0B ( R/W )
- - - - - - - 0B ( R/W )
00000DFH
bit
DACR1
00000DEH
15
23
14
22
13
21
12
20
11
19
10
18
8
DAE1
bit
DACR2
00000DDH
17
16
DAE2
- - - - - - - 0B ( R/W )
( ) : Access, R/W : Read/Write enabled,
: Not in use, X : Undefined
75
MB91F155A/MB91155/MB91154
18. 8/16-bit Up/Down Counters/Timers
This is the up/down counter/timer block consisting of six event input pins, two 8-bit up/down counters, two 8-bit
reload/compare registers, and their control circuits.
The features of this module are as follows :
• Capable of counting in the (0) d- (256) d range by the 8-bit count register.
(In 16-bit × 1 operating mode, the register can count in the (0) d- (65535) d range.)
• Four count modes to choose from by the count clock.
• In timer mode the count clock can be selected from two internal clock types.
• In up/down count mode an external pin input signal detection edge can be selected.
• The phase-difference count mode is suitable for encoder counting, such as of motors. Rotation angles, rotating
speeds, and so on can be counted accurately and easily by inputting the output of phases A, B, and Z.
• Two types of function to choose from for the ZIN pin. (Enabled in all modes)
• Equippedwithcompareandreloadfunctionswhichcanbeusedindividuallyorincombination. Whencombined,
these functions can count up/down at any width.
• The immediately preceding count direction can be identified by the count direction flag.
• Capable of individually controlling interrupt generation when comparison results match, at occurrence of reload
(underflow) or overflow, or when the count direction changes.
76
MB91F155A/MB91155/MB91154
• Block Diagram
• 8/16-bit Up/Down Counter/Timer (channel 0)
Data bus
8 bit
RCR0
(Reload/compare register 0)
CGE1
CGE0
C/GS
RCUT
Reload control
RLDE
Edge/level detection
ZIN0
UCRE
UDCC
Counter clear
8 bit
UDCR0
(Up/down count register 0)
Carry
CMPF
UDFF
OVFF
CES1
CMS1
CES0
CMS0
CITE
UDIE
Counter clock
CFIE
AIN0
BIN0
Up/down count
clock selection
UDF1
CSTR
UDF0
CDCF
Prescaler
Interrupt output
CLKS
77
MB91F155A/MB91155/MB91154
• 8/16-bit Up/Down Counter/Timer (channel 1)
Data bus
8 bit
RCR1
CGE1
CGE0
C/GS
(Reload/compare register 1)
RCUT
Reload control
RLDE
Edge/level detection
ZIN1
UCRE
Counter clear
8 bit
UDCC
UDCR1
(Up/down count register 1)
CMPF
UDFF
OVFF
CMS1
CMS0
CES1
Carry
CES0
M16E
CITE
UDIE
Counter clock
AIN1
BIN1
Up/down count
clock selection
UDF1
UDF0
CDCF
CFIE
CSTR
Prescaler
Interrupt output
CLKS
78
MB91F155A/MB91155/MB91154
• Register List
Initial value
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
7
15
7
6
14
6
5
13
5
4
12
4
3
2
10
2
1
9
1
9
1
1
1
1
9
9
0
8
0
8
0
0
0
0
8
8
Address : 00005FH
Address : 00005EH
Address : 00005DH
Address : 00005CH
Address : 000063H
Address : 000067H
Address : 000061H
Address : 000065H
Address : 000060H
Address : 000064H
00000000B
(R)
(R)
(W)
(W)
UDCR0
Initial value
00000000B
11
UDCR1
Initial value
00000000B
3
11
3
RCR0
RCR1
CSR0
CSR1
Initial value
00000000B
15
7
14
6
13
5
12
4
10
2
Initial value
00000000B (R/W)
Initial value
7
6
5
4
3
2
00000000B (R/W)
Initial value
7
6
5
4
3
2
-000X000B (R/W,W)
CCRL0
Initial value
7
6
5
4
3
2
-000X000B (R/W,W)
CCRL1
Initial value
15
15
14
14
13
13
12
12
11
CCRH0
10
10
00000000B (R/W)
Initial value
11
CCRH1
-0000000B (R/W)
( ) : Access, R/W : Read/Write enabled, R : Read only, W : Write only,
: Not in use, X : Undefined
79
MB91F155A/MB91155/MB91154
19. Peripheral STOP Control
This function can be used to stop the clock of unused resources in order to conserve more power.
• Register List
Address
Initial value
bit7
bit0
000090H
STPR0
0000 - - - - B ( R/W )
000091H
000092H
STPR1
STPR2
00000000B ( R/W )
000000 - - B ( R/W )
( ) : Access, R/W : Read/Write enabled,
: Not in use
80
MB91F155A/MB91155/MB91154
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V)
Value
Parameter
Symbol
Unit
Remarks
Min
Max
Power supply voltage
Analog supply voltage
Analog reference voltage
Input voltage
VCC
AVCC
AVRH
VI
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS + 3.6
VSS + 3.6
VSS + 3.6
VCC + 0.3
V
V
V
V
*1
*1
Input voltage
(open drain port J)
VI2
VSS − 0.3
VSS + 5.5
V
Analog pin input voltage
VIA
VO
VSS − 0.3
VSS − 0.3
AVCC + 0.3
VCC + 0.3
10
V
Output voltage
V
“L” level maximum output current
“L” level average output current
“L” level total maximum output current
“L” level total average output current
“H” level maximum output current
“H” level average output current
“H” level total maximum output current
“H” level total average output current
Power consumption
IOL
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
*2
*3
IOLAV
ΣIOL
ΣIOLAV
IOH
4
100
50
*4
*2
*3
−10
IOHAV
ΣIOH
ΣIOHAV
PD
−4
−50
−20
*4
500
Operating temperature
TA
0
+70
Storage temperature
Tstg
−55
+150
°C
*1 : Take care not to exceed VCC + 0.3 V when turning on the power, for example.
Take care also to prevent AVCC from exceeding VCC when turning on the power, for example.
*2 : The maximum output current stipulates the peak value of a single concerned pin.
*3 : The average output current stipulates the average current flowing through a single concerned pin over a period
of 100 ms.
*4 : The total average output current stipulates the average current flowing through all concerned pins over a period
of 100 ms.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
81
MB91F155A/MB91155/MB91154
2. Recommended Operating Conditions
Value
(VSS = AVSS = 0.0 V)
Parameter
Symbol
Unit
Remarks
Min
Max
3.15
3.6
During normal operations.
Power supply voltage
Analog supply voltage
VCC
V
The RAM state is retained
when stopped.
2.0
3.6
AVCC
VSS + 3.15
AVCC − 0.3
VSS + 3.6
AVCC
V
V
Analog reference voltage
(High potential side)
AVRH
Analog reference voltage
(Low potential side)
AVRL
TA
AVSS
AVSS + 0.3
+70
V
Operating temperature
0
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
82
MB91F155A/MB91155/MB91154
3. DC Characteristics
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Value
Symbol
Parameter
Pin name
Condition
Unit
Remarks
Min
Typ
Max
Input except for
hysteresis input pin*
0.65 ×
VCC
VIH
VCC + 0.3
V
V
V
V
V
“H” level input
voltage
VIHS Hysteresis input pin*
0.8 × VCC
VSS − 0.3
VSS − 0.3
VCC − 0.5
VCC + 0.3
Input except for
VIL
0.25 ×
VCC
“L” level input
voltage
hysteresis input pin*
VILS Hysteresis input pin*
0.2 × VCC
“H”leveloutput
voltage
VCC = 3.15 V
IOH = 4.0 mA
VOH Except for port J.
“L” level output
voltage
VCC = 3.15 V
IOL = 4.0 mA
VOL
ILI
VOL2 Port J
Port J
RPULL RST, pullup pin
Except for port J.
0.4
±5
V
µA
V
Input leakage
current
VCC = 3.6 V,
VSS <VI < VCC
“L” level output
voltage
VCC = 3.15 V
IOL = 15 mA
0.4
Open drain
Open drain
Output appli-
cation voltage
VD
VCC − 0.3
VSS + 5.0
V
Pullup
resistance
50
85
60
kΩ
External
VCC = 3.3 V,
33 MHz
ICC
VCC
VCC
120
100
mA buss access
available
VCC = 3.3 V,
33 MHz
During sleep
mode
ICCS
mA
Power supply
current
When
stopped and
µA calender is
not use (32
VCC = 3.3 V,
TA = +25 °C
ICCH
VCC
15
10
150
kHz stopped)
Other than Vcc, Vss,
AVcc, AVss, and
AVRH
Input capacity
CIN
pF
* : Refer to “■I/O CIRCUIT TYPE”.
83
MB91F155A/MB91155/MB91154
4. Flash Memory Erase and Programming Performance
Value
Parameter
Unit
Remarks
Min
Typ
Max
Sector Erase Time
1 *
15 *
s
Excludes programming time prior to erasure
Half Word Programming
Time
16 *
3600 *
µs Excludes system-level overhead
Chip Programming Time
Erase/Program Cycle
2.1 *
s
Excludes system-level overhead
10000
cycle
* : TA = +25 °C, VCC = 3.3 V
84
MB91F155A/MB91155/MB91154
5. AC Characteristics
(1) Clock Timing Ratings
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Value
Sym-
bol
Pin
name
Parameter
Condition
Unit
Remarks
Min
Max
Clock frequency
(High speed and self
oscillation)
Range in which self
oscillation is allowed
Range in which self
oscillation and the
use of the PLL for
external clock input
are allowed
10
16.5
MHz
Clock frequency
(High speed and PLL in use)
fC
X0, X1
Clock frequency
(High speed an 1/2 division
input)
Range in which
MHz external clocks can
be input
10
18
100
8
Clock frequency
(For calendar macro)
X0A,
X1A
Self oscillation and
kHz
fCA
32
external clocks
Clock cycle time
tC
PWH
PWL
tcr
X0, X1
55.6
25
Clock pulse width
X0, X1
15
ns
Input clock rising
Input clock falling
X0, X1
(tcr + tcf)
tcf
CPU
system
fCP
0.625*3
0.625*3
33
Bus
system
Internal
fCPB
25*2
operating clock
frequency
MHz
Analog section
excluded. *1
Analog section *1
0.625*3
1
33
33
Peripheral
system
fCPP
One wait is
set with the
wait
CPU
system
tCP
30.3
1600*3
controller.
Bus
system
Internal operat-
ing clock cycle
time
tCPB
40*2
1600*3
ns
Analog section
excluded. *1
section *1
30.3
30.3
1600*3
1000
Peripheral
system
tCPP
*1 : The target analog section is the A/D.
*2 : The maximum external bus operating frequency allowed is 25 MHz.
*3 : The value when a minimum clock frequency of 10 MHz is input to X0 and half a division of the oscillator circuit
and the 1/8 gear are in use.
85
MB91F155A/MB91155/MB91154
tC
PWH
PWL
tcf
tcr
VCC
Operation assurance range
3.6
fCPP
fCP
3.15
0.625 M
Frequency (Hz)
33 M
86
MB91F155A/MB91155/MB91154
The relationship between the X0 input and the internal clock set with the CHC/CCK1/CCK0 bit of the GCR (Gear
Control Register) is as shown next.
X0 input
• Source oscillation × 1
(GCR CHC bit : 0)
tCYC
(a) Gear × 1 internal clock
CCK1/0 : 00
tCYC
(b) Gear × 1/2 internal clock
CCK1/0 : 01
tCYC
(c) Gear × 1/4 internal clock
CCK1/0 : 10
tCYC
(d) Gear × 1/8 internal clock
CCK1/0 : 11
• Source oscillation × 1/2
(GCR CHC bit : 1)
tCYC
(a) Gear × 1 internal clock
CCK1/0 : 00
tCYC
(b) Gear × 1/2 internal clock
CCK1/0 : 01
tCYC
(c) Gear × 1/4 internal clock
CCK1/0 : 10
tCYC
(d) Gear × 1/8 internal clock
CCK1/0 : 11
87
MB91F155A/MB91155/MB91154
(2) Clock Output Timing
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Value
Pin
name
Parameter
Symbol
Condition
Unit
Remarks
Min
tCP
Max
*1
On using doubla
Cycle time
tCYC
CLK
ns
tCPB
CLK↑→CLK↓
CLK↓→CLK↑
tCHCL
tCLCH
CLK
CLK
tCYC/2−10
tCYC/2−10
tCYC/2+10
tCYC/2+10
ns *2
ns *3
tCYC
tCHCL
tCLCH
VOH
VOH
VOL
CLK
*1 : tCYC is a frequency for 1clock cycle including a gear cycle.
Use the doublur when CPU frequency is above 25 MHz.
*2 : Rating at a gear cycle of × 1
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations wiht 1/2, 1/4, 1/8,
respectively.
• Min : (1−n/2) × tCYC−10
• Max : (1−n/2) × tCYC+10
Select a gear sysle of × 1 when using the doublur.
*3 : Rating at a gear cycle of × 1
When a gear cycle of 1/2, 1/4, 1/8 selected, substitute “n” in the following equations wiht 1/2, 1/4, 1/8,
respectively.
• Min : n/2 × tCYC−10
• Max : n/2 × tCYC+10
Select a gear sysle of × 1 when using the doublur.
88
MB91F155A/MB91155/MB91154
(3) Reset Input Ratings
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Value
Pin
Parameter
Symbol
Condition
Unit
Remarks
name
Min
Max
Reset input time
tRSTL
RST
tCP × 5
ns
tRSTL
RST
0.2 VCC
(4) Power On Reset
Parameter
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Value
Pin
name
Symbol
Condition
Unit
Remarks
Min
Max
VCC < 0.2 V before
turning up the power.
Power supply rising time
Power supply cutoff time
fR
20
ms
ms
VCC
tOFF
2
tR
tOFF
0.9 × VCC
VCC
0.2 V
A rapid change in supply voltage might activate power on reset.
When the supply voltage needs to be varied while operating, it is recommended to minimize
fluctuations to smoothly start up the voltage.
VCC
It is recommended to keep the rising
inclination less than 50 mV/ms.
Holding RAM data.
VSS
VCC
RST
When turning on the power, start the RST pin in
“L” level state, allow as much time as for tRSTL after
reaching the VCC power supply level and then set
the pin to the H level.
tRSTL
89
MB91F155A/MB91155/MB91154
(5) Serial I/O (CH0-4)
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Value
Pin
name
Parameter
Symbol
Condition
Unit Remarks
Min
8 tCPP
−10
50
Max
Serial clock cycle time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
tBUSY
tCLZO
tCLSL
tCHOZ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK ↓ → SO delay time
Valid SI → SCK ↑
50
Internal
clock
SCK ↑ → valid SI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↓ → SO delay time
Valid SI → SCK ↑
50
4 tCPP − 10
4 tCPP − 10
0
50
50
50
External
clock
SCK ↑ → valid SI hold time
Serial busy period
6 tCPP
50
SCS ↓ → SCK and SO delay time
SCS ↓ → SCK input mask time
SCS ↑ → SCK and SO Hi-Z time
3 tCPP
50
Internal shift clock mode
tSCYC
SCK
tSLOV
SO
SI
tSHIX
tIVSH
External shift clock mode
tCLZO
tSLSH
tSHSL
tBUSY
tCHOZ
SCK
tSLOV
SO
SI
tIVSH
tSHIX
SCS
tCLSL
90
MB91F155A/MB91155/MB91154
(6) External Bus Measurement Conditions
The following conditions apply to items that are not specifically stipulated.
• AC characteristics measurement conditions
VCC : 3.3 V
Input
Output
VOH
VCC
0 V
VIH
VIL
VIH
2.4 V
0.8 V
VOH
VOL
1/2VCC
1/2VCC
VIL
VOL
(The input rise/fall time is less
than 10 ns.)
• Load condition
Output pin
C = 50 pF
( VCC : 3.3 V )
91
MB91F155A/MB91155/MB91154
(7) Normal Bus Access and Read/Write Operations
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Value
Parameter
Symbol Pin name Condition
Unit
Remarks
Min
Max
15
CS 0 - CS3 delay time
CS 0 - CS3 delay time
tCHCSL
tCHCSH
ns
ns
CLK
CS0 to CS3
15
CLK
A23 to A00
Address delay time
Data delay time
tCHAV
15
15
ns
ns
CLK
D31 to D16
tCHDV
RD delay time
tCLRL
tCLRH
tCLWL
tCLWH
10
10
10
10
ns
ns
ns
ns
CLK
RD
RD delay time
WR0 - WR1 delay time
WR0 - WR1 delay time
CLK
WR0 to WR1
Valid address →
valid data input time
A23 to A00
D31 to D16
3 / 2 ×
tCYC − 40
tAVDV
ns *1, *2
RD ↓ → valid data input time
Data setup → RD ↑ time
RD ↑ → Rdata hold time
tRLDV
tDSRH
tRHDX
tCYC − 25
ns *1
ns
RD
D31 to D16
25
0
ns
*1 : If the bus is extended with either automatic wait insertion or RDY input, add the (tCYC × the number of extended
cycles) time to this value.
*2 : This is the value at the time of (gear cycle × 1) .
When the gear cycle is set to 1/2, 1/4 or 1/8, substitute “n” in the following formula with 1/2, 1/4 or 1/8 respectively.
Formula : (2 − n / 2) × tCYC − 40
92
MB91F155A/MB91155/MB91154
tCYC
BA1
BA2
VOH
VOH
VOH
VOL
CLK
VOL
tCHCSH
VOH
tCHCSL
VOL
CS0 to CS3
tCHAV
VOH
VOL
A23 to A00
tCLRL
VOL
tCLRH
VOH
RD
tRLDV
tRHDX
tAVDV
tDSRH
VIH
VIL
VIH
VIL
D31 to D16
WR0 to WR1
D31 to D16
Read
tCLWL
VOL
tCLWH
VOH
tCHDV
VOH
VOL
Write
93
MB91F155A/MB91155/MB91154
(8) Ready Input Timing
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Value
Pin
name
Parameter
Symbol
Condition
Unit
Remarks
Min
Max
RDY
CLK
RDY setup time → CLK ↓
CLK ↓ → RDY hold time
tRDYS
tRDYH
20
ns
ns
RDY
CLK
0
tCYC
VOH
VOH
VOL
VOL
CLK
tRDYS tRDYH
tRDYS tRDYH
When
RDY wait
is applied
VIH
VIH
VIL
VIL
When
RDY wait
is not applied
VIH
VIH
VIL
VIL
94
MB91F155A/MB91155/MB91154
(9) Hold Timing
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Value
Pin
Parameter
Symbol
Condition
Unit
Remarks
name
Min
Max
10
BGRNT delay time
tCHBGL
tCHBGH
tXHAL
ns
ns
ns
ns
CLK
BGRNT
BGRNT delay time
10
Pin floating → BGRNT ↓ time
BGRNT ↑ → Pin valid time
tCYC − 10
tCYC − 10
tCYC + 10
tCYC + 10
BGRNT
tHAHV
Note : More than one cycle exist after BRQ is fetched and before BGRNT changes.
tcyc
VOH
VOH
VOH
CLK
BRQ
tCHBGL
tCHBGH
VOH
BGRNT
VOL
tXHAL
tHAHV
Each pin
High impedance
95
MB91F155A/MB91155/MB91154
(9) DMA Controller Timing
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Value
Parameter
Symbol
Pin name
Condition
Unit Remarks
Min
Max
DREQ input pulse width
tDRWH
tCLDL
DREQ0 to DREQ2
2 tCYC
ns
ns
DACK delay time
(typical bus)
(typical DRAM)
6
6
6
6
CLK
DACK0 to DACK2
tCLDH
tCLEL
tCLEH
tCHDL
tCHDH
tCHEL
tCHEH
ns
ns
ns
DEOP delay time
(typical bus)
(typical DRAM)
CLK
DEOP0 to DEOP2
DACK delay time
(Single Dram)
(Hyper Dram)
n / 2 × tCYC ns
CLK
DACK0 to DACK2
6
ns
n / 2 × tCYC ns
ns
DEOP delay time
(Single Dram)
(Hyper Dram)
CLK
DEOP0 to DEOP2
6
tcyc
VOH
VOH
VOL
VOL
CLK
tCLDH
tCLEH
tCLDL
tCLEL
DACK0 to DACK2
DEOP0 to DEOP2
(Typical bus)
VOH
(Typical DRAM)
VOL
tCHDH
VOH
DACK0 to DACK2
DEOP0 to DEOP2
( Single DRAM )
( Hyper DRAM )
tCHDL
tCHEL
VOL
tDRWH
VIH
VIH
DREQ0 to DREQ2
96
MB91F155A/MB91155/MB91154
6. A/D Converter Electrical Characteristics
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Value
Re-
Sym-
bol
Pin
name
Parameter
Resolution
Condition
Unit
marks
Min
Typ
Max
10
Bit
µs
Conversion time
Total error
5.1
±4.0
±3.5
±2.0
LSB
LSB
LSB
AVCC = 3.3 V,
AVRH = 3.3 V
Linearity error
Differential linearity error
AN0 to
AN7
Zero transition error
Full-scale transition error
Analog input current
Analog input voltage
VOT
VFST
IAIN
AVSS − 1.5 AVSS + 0.5 AVSS + 2.5 LSB
AVRH − 5.5 AVRH − 1.5 AVRH + 0.5 LSB
AVCC = 3.3 V,
AVRH = 3.3 V
AN0 to
AN7
AN0 to
AN7
0.1
10
µA
AN0 to
AN7
VAIN
AVRH
IA
AVSS
AVRH
AVCC
5.0
V
V
Reference voltage
Conversion
AVRH
3.0
2.0
mA
in operation
Supply
current
AVCC
AVCC = 3.3 V
Conversion
stopped
IAH
IR
5.0
3.0
10
4
µA
mA
µA
Conversion
in operation
Reference
voltage
supply
AVCC = 3.3 V,
AVRH = 3.3 V
AVRH
Conversion
stopped
IRH
current
AN0 to
AN7
Interchannel variation
LSB
Notes : • The smaller the |AVRH| is, the greater the error is in general.
• The external circuit output impedance of analog input should be used in compliance with the following
requirements :
External circuit output impedance ≤ 2 (kΩ)
If the output impedance of the external circuit is too high, an analog voltage sampling duration shortage
might occur. (Sampling duration = 1.4 µs : @33 MHz)
97
MB91F155A/MB91155/MB91154
• A/D Converter Glossary
• Resolution
: Analog changes that are identifiable by the A/D converter.
• Linearity error
: The deviation of the straight line connecting the zero transition point
(00 0000 0000 ←→ 00 0000 0001) with the full-scale transition point
(11 1111 1110 ←→ 11 1111 1111) from actual conversion characteristics.
• Differential linearity error : The deviation of input voltage needed to change the output code by one LSB
from the theoretical value.
• Total error
: The difference between actual and theoretical conversion values including a
zero transition/full-scale transition/linearity error.
Total error
3FF
1.5 LSB'
3FE
3FD
Actual conversion
characteristics
{1 LSB' ( N − 1 ) + 0.5 LSB'}
004
003
002
001
VNT
(Actual measurement)
Actual conversion
characteristics
Theoretical characteristics
0.5 LSB'
AVRH
AVSS
Analog input
AVRH − AVSS
1 LSB’ (theoretical value) =
[V]
[V]
1024
VOT’ (theoretical value) = AVSS + 0.5 LSB’
VFST’ (theoretical value) = AVRH − 1.5 LSB’ [V]
VNT − {1 LSB’ × (N − 1) + 0.5 LSB’}
Total error of digital output N =
1 LSB’
VNT : Voltage at which digital output changes from (N + 1) to N.
(Continued)
98
MB91F155A/MB91155/MB91154
(Continued)
Differential linearity error
Linearity error
3FF
3FE
3FD
Actual conversion
Actual conversion
characteristics
characteristics
N + 1
{1 LSB ( N − 1 ) + VOT}
Theoretical
characteristics
VFST
(Actual
measurement)
N
004
003
002
001
VNT
(Actual
N − 1
VFST
measurement)
Actual conversion
(Actual
measurement)
characteristics
VNT
(Actual
Theoretical characteristics
measurement)
N − 2
Actual conversion
characteristics
VOT
(Actual measurement)
AVSS
AVSS
AVRH
AVRH
Analog input
Analog input
VNT − {1 LSB × (N − 1) + VOT}
Linearity error of digital
output N
=
=
[LSB]
1 LSB
V (N + 1) T − VNT
Differential linearity error
of digital output N
−1
[LSB]
1 LSB
VFST − VOT
[V]
1 LSB =
1022
VOT : Voltage at which digital output changes from (000) H to (001) H.
VFST : Voltage at which digital output changes from (3FE) H to (3FF) H.
7. D/A Converter Electrical Characteristics
(VCC = 3.15 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Value
Pin
name
Condi-
tion
Re-
marks
Parameter
Resolution
Symbol
Unit
Min
Typ
Max
8
Bit
LSB
µs
Differential linearity error
Conversion time
1
20
*
Analog output impedance
29
kΩ
* : CL = 20 pF
99
MB91F155A/MB91155/MB91154
■ EXAMPLE CHARACTERISTICS
(1) “H” level output voltage
(2) “L” level output voltage
“H” level output voltage vs. Power supply voltage
“L” level output voltage vs. Power supply voltage
400
350
300
250
200
150
100
50
5
4
3
2
1
0
0
2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2
2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2
VCC [V]
VCC [V]
(3) “L” level output voltage (Open drain)
(4) Pull-up resistance
“L” level output voltage (Open drain) vs.
Power supply voltage
Pull-up resistance vs. Power supply voltage
400
350
300
250
200
150
100
50
80
70
60
50
40
30
20
10
0
0
2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2
2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2
VCC [V]
VCC [V]
100
MB91F155A/MB91155/MB91154
(5) Power supply
Power supply vs. Voltage
(6) Power supply at sleeping
Power supply (Sleeping) vs. Voltage
120
100
80
60
40
20
0
100
90
80
70
60
50
40
30
MB91154
MB91155
MB91F155A
MB91154
MB91155
MB91F155A
20
10
0
2.8
2.8
3.0
3.2
3.4
3.6
3.8
3.0
3.2
3.4
3.6
3.8
VCC [V]
VCC [V]
(7) Power supply at stopping
(8) A/D conversion power supply
A/D conversion power supply current vs.
Power supply voltage
Power supply (Stopping) vs. Voltage
5
4
3
2
1
0
120
100
80
60
40
20
0
2.8
3.0
3.2
3.4
3.6
3.8
2.8
3.0
3.2
3.4
3.6
3.8
VCC [V]
VCC [V]
(9) A/D conversion reference voltage supply current
(33 MHz)
(10) D/A conversion power supply current (33 MHz)
A/D conversion reference voltage supply current vs.
Voltage
D/A conversion power supply current vs.
Power supply voltage
2.0
1.5
1.0
0.5
0.0
1.0
0.8
0.6
0.4
0.2
0.0
2.8
3.0
3.2
3.4
3.6
3.8
2.8
3.0
3.2
3.4
3.6
3.8
VCC [V]
VCC [V]
101
MB91F155A/MB91155/MB91154
■ ORDERING INFORMATION
Part number
Package
Remarks
MB91F155APFV-G
MB91155PFV-G-XXX
MB91154PFV-G-XXX
144-pin plastic LQFP
(FPT-144P-M08)
144-pin plastic LQFP
(FPT-144P-M01)
MB91F155APF-G
102
MB91F155A/MB91155/MB91154
■ PACKAGE DIMENSION
144-pin plastic LQFP
(FPT-144P-M08)
*Pins width and pins thickness include plating thickness.
22.00±0.20(.866±.008)SQ
20.00±0.10(.787±.004)SQ
0.145±0.055
(.006±.002)
108
73
109
72
0.08(.003)
Details of "A" part
1.50 +–00..1200
(Mounting height)
.059 +–..000048
0.10±0.10
(.004±.004)
(Stand off)
0°~8°
INDEX
144
37
0.25(.010)
0.50±0.20
(.020±.008)
"A"
0.60±0.15
(.024±.006)
1
36
LEAD No.
0.50(.020)
0.22±0.05
(.009±.002)
M
0.08(.003)
C
2000 FUJITSU LIMITED F144019S-c-2-4
Dimensions in mm (inches)
(Continued)
103
MB91F155A/MB91155/MB91154
(Continued)
144-pin plastic LQFP
(FPT-144P-M01)
*Pins width and pins thickness include plating thickness.
(MB91F155A only)
32.00±0.40(1.260±.016)SQ
28.00±0.20(1.102±.008)SQ
0.17±0.06
(.007±.002)
108
73
109
72
0.10(.004)
Details of "A" part
3.65±0.20
(.144±.008)
(Mounting height)
0.25(.010)
INDEX
0~8°
144
37
0.80±0.20
(.031±.008)
0.30 +–00..2150
.012 +–..001004
"A"
1
36
0.88±0.15
(Stand off)
(.035±.006)
0.65(.026)
0.32±0.05
(.013±.002)
M
0.13(.005)
C
2001 FUJITSU LIMITED F144002S-c-4-4
Dimensions in mm (inches)
104
MB91F155A/MB91155/MB91154
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0206
FUJITSU LIMITED Printed in Japan
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