MB91306RPFV_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-16314-2E

32-Bit Microcontroller

CMOS

FR60 MB91307 Series

MB91306R/MB91307R

■ DESCRIPTION

The FUJITSU FR family of single-chip microcontrollers using a 32-bit high-performance RISC CPU, with a variety

of built-in I/O resources and bus control mechanisms for built-in control applications requiring high-capability,

high-speed CPU processing. External bus access is assumed in order to support the expanded address space

accessible by the 32-bit CPU, and a 1K bytes cache memory plus large RAM are provided for high-speed execution

of CPU instructions.

This microcontroller is ideal for built-in applications such as DVD players, navigation systems, high-capability FAX

and printer control that demand high-capability CPU processing power.

The MB91307 series is a FR60 family product based on the FR30/40 family CPU with enhanced bus access for

higher speed operation.

■ FEATURES

FR CPU

• 32-bit RISC, load/store architecture, 5-stage pipeline

• Operating frequency 66MHz [with PLL: base frequency 16.5 MHz]

• 16-bit fixed length instructions (basic instructions), 1 instruction per cycle

• Instructions for built-in applications: memory-to-memory transfer, bit processing, barrel shift etc.

• Instructions adapted for high-level languages: function input/output instructions, register contents multi-load/

store instructions

(Continued)

■ PACKAGE

120-pin, plastic LQFP

(FPT-120P-M21)

MB91307 Series

• Easier assembler notation: register interlock function

• Built-in multiplier/instruction level support

Signed 32-bit multiplication: 5 cycles

Signed 16-bit multiplication: 3 cycles

• Interrupt (PC, PS removal): 6 cycles, 16 priority levels

• Harvard architecture for simultaneous execution of program access and data access

• CPU hold 4-word queue allows advanced instruction fetch function

• 4G bytes expanded memory space enables linear access

• Instruction compatible with FR30/40 family

Bus Interface

• Operating frequency: Max 33 MHz

• 8- or 16-bit data output

• Built-in pre-fetch buffer

• Unused data/address pins can be used as general-0purpose input/output ports

• Fully independent 8-area chip select outputs, can be set in minimum 64K bytes units

• Interface support for many memory types

SRAM, ROM/Flash

Page mode flash ROM, page mode ROM interface

Burst mode flash ROM (select burst length 1, 2, 4, 8)

• Basic bus cycle: 2 cycles

• Programmable by area with automatic wait cycle generation to enable wait insert

• RDY input for external wait cycles

• DMA supports fly-by transfer with independent I/O wait control

Built-in RAM

• 128K bytes (MB91307R), 64K bytes (MB91306R)

• Accepts writing of data and instruction codes, enabling use as instruction RAM

Instruction cache

• 1K bytes capacity

• 2-way set associative

• 4-words (16 bytes) per set

• Lock function enables permanent program storage

• Areas not used for instruction cache can be used for RAM

DMAC (DMA controller)

• 5-channel (3-channel external-to-external)

• 3 transfer sources (external pin, internal peripheral, software)

• Addressing mode with 32-bit full address indication (increment, decrement, fixed)

• Transfer mode (demand transfer / burst transfer / step transfer / block transfer)

• Fly-by transfer support (3 channels between external I/O and external memory)

• Transfer data size selection 8/16/32-bit

Bit search module (using REALOS)

• Searches words from MSB for first bit position of a 1/0 change

Reload timer (includes 1 channel for REALOS)

• 16-bit timer: 3 channels

• Internal clock multiplier choice of x2, x8, x32

(Continued)

2

MB91307 Series

(Continued)

UART

• Full duplex double buffer

• 3-channel

• Parity/no parity selection

• Asynchronous (start-stop synchronized), CLK-synchronized communications selection

• Built-in exclusive baud rate timer

• External clock can be used as transfer clock

• Variety of error detection functions (parity, frame, overrun)

I²C* interface

• Master/slave sending and receiving

• Clock synchronization function

• Transfer direction detection function

• Bus error detection function

• Arbitration function

• Slave address/general call address detection function

• Start condition repeat generator and detection function

• 10-bit/7-bit slave address

• Operates in standard mode (Max 100 Kbps) or high speed mode (Max 400 Kbps)

Interrupt controller

• Total of 9 external interrupts: 1 non-maskable interrupt pin (NMI) and 8 normal interrupt pins INT7-INT0

• Interrupt from internal peripheral devices

• Programmable priority settings (16 levels) enabled, except for non-maskable interrupt

• Can be used for wake-up from stop mode

A/D converter

• 10-bit resolution, 4-channel

• Sequential comparator type, conversion time approx. 5.4 µs

• Conversion modes: single conversion mode, continuous conversion mode

• Startup source: software / external trigger / timer output signal

Other interval timers

• 16-bit timer with 3 channels (U-timer)

• Watchdog timer

I/O port

• Maximum 69 ports

Other features

• Built-in oscillator circuit for clock source, PLL multiplier selection enabled

• INIT reset pin

• Also included: watchdog timer reset, software reset

• Power-saving modes: stop mode, sleep mode supported

• Gear functions

• Built-in time base timer

• Packages: LQFP-120 (FPT-120P-M21) : MB91306R, MB91307R

: MB91V307R (Evaluation products)

• CMOS technology

: 0.25 µm : MB91V307R, 0.18 µm : MB91306R, MB91307R

• Supply voltage : MB91V307R : 3.3 V 0.3 V (built-in regulator 3.3 V → 2.5 V)

: MB91306R, MB91307R : 3.3 V 0.3 V, 1.8V 0.15 V dual power supplies

*:PurchaseofFujitsuI²CcomponentsconveysalicenseunderthePhilipsI²CPatentrightstouse,thesecomponents

in an I²C system provided that the system conforms to the I²C Standard Specification as defined by Philips.

3

MB91307 Series

■ PIN ASSIGNMENT

PA3/CS3

PA4/CS4

PA5/CS5

V^CCI

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

PI5/SC1

PI4/SO1

PI3/SI1

PI2/SC0

PI1/SO0

PI0/SI0

PA6/CS6

PA7/CS7

P80/RDY

P81/BGRNT

P82/BRQ

RD

UUB/WR0

P85/ULB/WR1

NMI

V^CC

PJ7/INT7/ATG

PJ6/INT6/TIN2

PJ5/INT5/TIN1

PJ4/INT4/TIN0

PJ3/INT3

PJ2/INT2

PJ1/INT1

PJ0/INT0

AN3

AN2

AN1

AN0

AV^SS/AVRL

AVRH

V^CCI

VSS

INIT

P90/SYSCLK

P91

P92/MCLK

P93

P94/LBA/AS

P95/BAA

P96

AV^CC

8

7

6

5

4

3

2

1

A24/P70

A23/P67

A22/P66

A21/P65

A20/P64

A19/P63

A18/P62

A17/P61

P97/WE

P20/D16

P21/D17

P22/D18

P23/D19

P24/D20

P25/D21

FPT-120P-M21

* : “L” level output after initialization and reset

4

MB91307 Series

■ PIN DESCRIPTIONS

I/O

circuit type

Pin no.

Pin name

Description

External data bus bit 16 to bit 23

Valid only in external bus 16-bit mode.

D16 to D23

P20 to P27

85 to 92

C

These pins can be used as ports in external bus 8-bit mode

External data bus bit 24 to bit 31

93 to 100 D24 to D31

102 to 109 A00 to A07

111 to 118 A08 to A15

C

F

External address output bit0 to bit7

External address output bit8 to bit15

A16 to A23

120, 1 to 7

External address output bit16 to bit23

F

P60 to P67

These pins can be used as ports according to setting

External data bus output bit24

A24

8

P70

This pin can be used as a port according to setting

Power supply pin. Analog power supply for A/D converter

A/D converter reference voltage supply

9

AV^CC

AVRH

⎯

D

10

11

AV^SS/AVRL

Power supply pin. Analog power supply for A/D converter

A/D converter reference voltage supply. Analog input pin.

12 to 15 AN0 to AN3

External interrupt input. When the corresponding external interrupt is en-

abled, this input is in use at all times, so that output from other functions

must be stopped unless used intentionally

INT0 to INT3

16 to 19

I

PJ0 to PJ3

General purpose input/output port

Reload timer input. When the corresponding timer input is enabled, this

input is in use at all times, so that output from other functions must be

stopped unless used intentionally.

TIN0 to TIN2

20 to 22

I

External interrupt input. When the corresponding external interrupt is en-

abled, this input is in use at all times, so that output from other functions

must be stopped unless used intentionally.

INT4 to INT6

PJ4 to PJ6

ATG

General purpose input/output port

A/D converter external trigger input. When selected as an A/D start

source, this input is in use at all times, so that output from other functions

must be stopped unless used intentionally.

23

I

External interrupt input. When the corresponding external interrupt is en-

abled, this input is in use at all times, so that output from other functions

must be stopped unless used intentionally.

INT7

PJ7

General purpose input/output port

UART0 data input. When the UART0 channel is in input operation, this

input is in use at all times, so that output from other functions must be

stopped unless used intentionally.

SI0

25

F

PI0

General purpose input/output port.

UART0 data output. This function is valid when the UART0 data output

function setting is disabled.

SO0

26

General purpose input/output port. This function is valid when the

UART0 data output function setting is disabled.

PI1

(Continued)

5

MB91307 Series

I/O

circuit type

Pin no.

Pin name

SC0

Description

UART0 clock output. The clock output is valid when the UART0 clock

output function setting is enabled.

27

F

General purpose input/output port. This function is valid when the

UART0 clock output function is disabled.

PI2

UART1 data input. When UART1 is set for input operation, this input is

in use at all times, so that output from other functions must be stopped

unless used intentionally.

SI1

28

29

30

31

32

33

35

F

C

PI3

General purpose input/output port.

UART1 data output. This function is enabled when the UART1 data out-

put function setting is enabled.

SO1

General purpose input/output port. This function is valid when the

UART1 data output function setting is disabled.

PI4

SC1

PI5

UART1 clock input/output. The clock output is enabled when the UART1

clock output function setting is enabled.

General purpose input/output port. This function is valid when the

UART1 clock output function setting is disabled.

UART2 data input. When UART2 is set for input operation, this input is

in use at all times, so that output from other functions must be stopped

unless used intentionally.

SI2

PH0

SO2

General purpose input/output port.

UART2 data output. This function is enabled when the UART2 data out-

put function setting is enabled.

General purpose input/output port This function is enabled when the

UART2 data output function setting is disabled.

PH1

SC2

UART2 clock input/output. The clock output is enabled when the UART2

clock output function setting is enabled.

General purpose input/output port This function is enabled when the

UART2 clock output function is disabled.

PH2

Timer output port. This function is valid when the timer output setting is

enabled.

TOT0

PH3

General purpose input/output port.This pin outputs an “L” level signal at

reset.

Timer output port. This function is valid when the timer output setting is

enabled.

TOT1

PH4

36

37

C

General purpose input/output port.This pin outputs an “L” level signal at

reset.

TOT2

PH5

Timer output port. This function is valid when the timer output is enabled.

General purpose input/output port.

(Continued)

6

MB91307 Series

I/O

circuit type

Pin no.

Pin name

Description

I²C bus input/output port. This function is valid when I²C operation is en-

abled. When the I²C bus is in use, the port output must be set to Hi-Z

level. When the I²C bus is in use, this is an open drain pin.

SDA

PH6

38

Q

F

General purpose input/output port.

I²C bus input/output port. This function is valid when I²C operation is en-

abled. When the I²C bus is in use, the port output must be set to Hi-Z

level. When the I²C bus is in use, this is an open drain pin.

SCL

39

40

41

PH7

General purpose input/output port.

DMA external transfer request input. When selected as a DMA startup

source, this input is in use at all times, so that output from other functions

must be stopped unless used intentionally.

DREQ2

PG0

General purpose input/output port.

DMA external transfer request acknowledge output. This function is valid

when the DMA transfer request acknowledge output setting is enabled.

DACK2

F

General purpose input/output port. This function is valid when the DMA

transfer request acknowledge output setting is enabled.

PG1

DMA external transfer end output. This function is valid when the DMA

external transfer end output setting is enabled.

DEOP2

DSTP2

DMA external transfer stop input. This function is valid when the DMA ex-

ternal transfer stop input setting is enabled.

42

F

General purpose input/output port. This function is valid when the DMA

external transfer end output selection and the DMA external transfer stop

input selection are disabled.

PG2

Mode pins 2 to 0. The setting of these two pins determines the basic

operating mode. They should be connected to V^ccor V^ss.

43 to 45 MD2 to MD0

G

F

DMA external transfer request input. When selected as a DMA startup

source, this input is in use at all times, so that output from other functions

must be stopped unless used intentionally.

DREQ0

46

PB0

General purpose input/output port.

DMA external transfer request acknowledge output. This function is valid

when the DMA transfer request acknowledge output setting is enabled.

DACK0

47

F

General purpose input/output port. This function is enabled when the

DMA transfer request acknowledge output setting is disabled.

PB1

DMA external transfer end output. This function is valid when the DMA

external transfer end output setting is enabled.

DEOP0

DMA external transfer stop input. This function is valid when the DMA ex-

ternal transfer stop input setting is enabled.

DSTP0

48

General purpose input/output port. This function is valid when the DMA

external transfer end output selection and the DMA external transfer stop

input selection are disabled.

PB2

(Continued)

7

MB91307 Series

I/O

circuit type

Pin no.

Pin name

Description

DMA external transfer request input. When selected as a DMA startup

source, this input is in use at all times, so that output from other functions

must be stopped unless used intentionally.

DREQ1

49

F

PB3

General purpose input/output port.

DMA external transfer request acknowledge output. This function is valid

when the DMA transfer request acknowledge output setting is enabled.

DACK1

50

51

F

General purpose input/output port. This function is enabled when the

DNA transfer request acknowledge output setting is disabled.

PB4

DMA external transfer end output. This function is valid when the DMA

external transfer end output setting is enabled.

DEOP1

DSTP1

DMA external transfer stop input. This function is valid when the DMA ex-

ternal transfer stop input setting is enabled.

General purpose input/output port. This function is valid when the DMA

external transfer end output selection and the DMA external transfer stop

input selection are disabled.

PB5

53

54

X1

X0

Clock (oscillator) output

Clock (oscillator) input

A

F

Write strobe output for DMA fly-by transfer. This function is valid when

the DMA fly-by transfer write strobe output setting is enabled.

IOWR

PB6

IORD

PB7

CS0

PA1

CS1

PA1

CS2

PA2

CS3

PA3

56

57

58

59

60

61

General purpose input/output port. This function is valid when the DMA

fly-by transfer write strobe output setting is disabled.

Read strobe output for DMA fly-by transfer. This function is valid when

the DMA fly-by transfer read strobe output setting is enabled.

F

General purpose input/output port. This function is valid when the DMA

fly-by transfer read strobe output setting is disabled.

Chip select output. This function is valid when the chip select 0 output

setting is enabled.

General purpose input/output port. This function is valid when the chip

select 0 output setting is disabled.

Chip select output. This function is valid when the chip select 1 output

setting is enabled.

General purpose input/output port. This function is valid when the chip

select 1 output setting is disabled.

Chip select output. This function is valid when the chip select 2 output

setting is enabled.

General purpose input/output port. This function is valid when the chip

select 2 output setting is disabled.

Chip select output. This function is valid when the chip select 3 output

setting is enabled.

General purpose input/output port. This function is valid when the chip

select 3 output setting is disabled.

(Continued)

8

MB91307 Series

I/O

circuit type

Pin no.

Pin name

CS4

Description

Chip select output. This function is valid when the chip select 4 output set-

ting is enabled.

62

F

General purpose input/output port. This function is valid when the chip se-

lect 4 output setting is disabled.

PA4

Chip select output. This function is valid when the chip select 5 output set-

ting is enabled.

CS5

63

64

65

F

⎯

F

General purpose input/output port. This function is valid when the chip se-

lect 5 output setting is disabled.

PA5

V^CCI

CS6

Internal Power supply pin (1.8 V power supply) .

Chip select output. This function is valid when the chip select 6 output set-

ting is enabled.

General purpose input/output port. This function is valid when the chip

select 6 output setting is disabled.

PA6

CS7

PA7

RDY

P80

Chip select output. This function is valid when the chip select 7 output set-

ting is enabled.

66

67

F

General purpose input/output port. This function is valid when the chip

select 7 output setting is disabled.

External ready signal input. This function is valid when the external ready

input setting is enabled.

C

General purpose input/output port. This function is valid when the exter-

nal ready input setting is disabled.

External bus open acknowledge output. This pin outputs an L level signal

when the external bus is open. This function is valid when the output set-

ting is enabled.

BGRNT

68

69

F

P

General purpose input/output port. This function is valid when the output

setting is disabled.

P81

External bus open request input. The input value is “1” when the external

bus is open. This function is valid when the input setting is enabled.

BRQ

General purpose input/output port. This function is valid when the input

setting is disabled.

P82

RD

70

71

M

F

External bus read strobe output.

External bus write strobe output.

WR0

UUB

Upper side of the 16-bit SRAM input/output mask enable signal.

It is valid when the external bus is set to SRAM use. (WE/P97 function as

the write strobe.)

External bus write strobe output.

WR1

ULB

Lower side of the 16-bit SRAM input/output mask enable signal.

It is valid when the external bus is set to SRAM use. (WE/P97 function as

the write strobe.)

72

F

General purpose input/output port. This function is valid when the enable

output setting is disabled.

P85

(Continued)

9

MB91307 Series

(Continued)

I/O

circuit type

Pin no.

Pin name

Description

73

74

76

NMI

VCCI

INIT

H

B

NMI request input

Internal Power supply pin(1.8 V power supply)

External reset input

System clock output. This function is valid when the system clock output

setting is enabled. The clock signal output is at the same frequency as the

external bus operating frequency. Clock output halts in the stop mode or

the hardware standby mode.

SYSCLK

77

F

General purpose input/output port. This function is enabled when the sys-

tem clock output setting is disabled.

P90

P91

MCLK

P92

P93

AS

General purpose input/output port. This function is enabled when the

SDRAM clock enable output setting is disabled.

78

79

80

F

Memory clock output. Clock output halts in the sleep mode, the stop mode

or the hardware standby mode.

General purpose input/output port. This function is enabled when the

clock output setting is disabled.

General purpose input/output port. This function is enabled when the

SDRAM clock re-input setting is disabled.

Address strobe output. This function is valid when the address strobe out-

put setting is disabled.

Burst flash ROM address load output. This function is valid when the ad-

dress load output setting is enabled.

81

LBA

P94

BAA

P95

P96

WE

F

General purpose input/output port. This function is valid when the address

load output and address strobe output settings are disabled.

Burst flash ROM address advance output. This function is valid when the

address advance output setting is enabled.

82

83

84

General purpose input/output port. This function is valid when the address

advance output and column address strobe output settings are disabled.

General purpose input/output port. This function is enabled when the col-

umn address strobe output setting is disabled.

F

Write strobe output for 16-bit SRAM. This function is enabled when the

write strobe output setting is enabled.

General purpose input/output port. This function is enabled when the write

strobe output setting is prohibited.

P97

9

AV^CC

AVRH

⎯

A/D converter power supply

A/D converter power supply (GND)

10

11

AV^SS/AVRL

24, 55,

110

V^CC

V^SS

⎯

Power supply pins

34, 52,

75, 101

Power supply pins (GND)

10

MB91307 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Oscillator feedback resistance

approx. 1 MΩ

X1

clock input

X0

A

STANDBY

CONTROL

• CMOS hysteresis input

with pull-up resistance (25 kΩ)

B

digital input

• CMOS level input/output

with standby control

digital output

C

digital input

STANDBY CONTROL

• Analog input with switch

D

analog input

CONTROL

(Continued)

11

MB91307 Series

Type

Circuit

Remarks

• CMOS level output

• CMOS level hysteresis input

with standby control

digital output

F

digital input

STANDBY CONTROL

• CMOS level input

without standby control

G

digital input

• CMOS level hysteresis input

without standby control

H

digital input

• CMOS level input

• CMOS level hysteresis input

without standby control

digital output

I

digital input

• CMOS level input

digital output

M

(Continued)

12

MB91307 Series

(Continued)

Type

Circuit

Remarks

• CMOS level input/output

with standby control

withpull-downresistance (25kΩ)

digital output

CONTROL

P

digital input

STANDBY CONTROL

• Open drain output

CMOS level hysteresis input

with standby control

Open drain control

digital output

Q

digital input

STANDBY CONTROL

13

MB91307 Series

■ HANDLING DEVICES

■MB91307 Series

• Preventing Latchup

When CMOS integrated circuit devices are subjected to applied voltages higher than V^CCat input and output

pins (other than medium- and high-withstand voltage pins), or to voltages lower than V^SS, as well as when voltages

in excess of rated levels are applied between V^CCand V^SS, a phenomenon known as latchup can occur. When

a latchup condition occurs, supply current can increase dramatically and may destroy semiconductor elements.

In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings.

• Treatment of unused pins

Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or

pull-down resistor.

• About power supply pins

In products with multiple V^CCor V^SSpins, the pins of the same potential are internally connected in the device

to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply

and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals

caused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the V^CCand V^SSpins of this device at the low impedance.

It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 mF between V^CCand V^SSnear

this device.

• Notes on Power-ON/shut-down

Cautions to take when turning on/off V^CCI(1.8-V internal power supply) and V^SS(3.3-V external-pin power

supply)

Do not apply V^SS(external) alone continuously (for over an indication of one minute) with V^CCI(internal) discon-

nected not to cause a reliability problem with the LSI.

When V^SS(external) returns from the OFF state to the ON state, the circuit may fail to hold its internal state, for

example, due to power supply noise.

When the power is turned on

When the power is turned off

V^CCI(internal) → V^SS(external) → Signal

Signal → V^SS(external) → V^CCI(internal)

• Precautions for use of stop mode

The built-in regulator in this device stops operating when the device is in stop mode. In such cases as when

increased leak current (I^CCH) in stop mode, or abnormal operation or power fluctuation due to noise while in

operating mode cause the regulator to stop, the internal 2.5 V power supply can ball below the voltage at which

operation is assured. Therefore it is necessary when using the internal regulator and stop mode to assure that

the external power supply does not fall below 3.3 V. And even if this should occur, the internal regulator can be

set to restart when a reset is applied. (In this case the oscillator stabilization wait period should also be set to

“L” level.)

14

MB91307 Series

• Sample use of Stop Mode with 3.3 V power supply

3.3 V

VCC

C

2.4 k

7.6 k

0.1

F

VSS

GND

• About crystal oscillator circuit

Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that

X0, X1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to

the device as possible.

It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane

because stable operation can be expected with such a layout.

• Treatment of NC pins

Any pins marked “NC” (not connected) must be left open.

• About mode pins (MD0 to MD2)

Mode pins (MD0 to MD2) should be connected directly to V^CCor V^SS.

To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that

the distance between the mode pins and V^CCor V^SSis as short as possible and the connection impedance is low.

• Operation at startup

Immediately after a power-on startup, always apply a reset initialization (INIT) at the INIT pin. Also, in order to

assure a wait period for the oscillator circuits to stabilize immediately after startup, be sure that the “L” level input

to the INIT pin continues for the required stabilization wait interval. (The INIT cycle for the INIT pin includes only

the minimum setting for the stabilization wait period.)

• Base oscillator input at startup

At power-on startup, always input a clock signal until the oscillator stabilization wait period is ended.

• Caution on Operations during PLL Clock Mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even

when there is no external oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed.

• Precaution on using ports 6 and 7

If one of P60/A15 to P70/A24, which are shared for output of external bus interface addresses, is used as a port,

a grid voltage is applied to the port instantaneously when the status of another address output pin is changed.

Therefore, add resistors or capacitors to those ports to prevent application of the grid voltage.

15

MB91307 Series

• Clock control block

For L-level input to the INIT pin, allow for the regulator settling time or oscillation settling time.

• Bit search module

The 0-detection, 1-detection, and transition-detection data registers (BSD0, BSD1, and BSDC) are only word-

accessible.

• Prefetch

When accessing a prefetch-enabled little endian area, use word access only (access in 32 bits).

Byte or halfword access results in wrong data read.

• Setting of external bus

The MB91307 series is guaranteed at an external bus frequency of 33 MHz. As the external bus is capable of

supporting 66 MHz for future enhancements, the initial value is the same rate as the base clock (determined by

the PLL setting) . The external bus is set to 66 MHz if you set the base clock to 66 MHz with the external-bus

base clock division setting register (DIVR1) containing the initial value. To change the base clock frequency, set

the external bus frequency not exceeding 33 MHz and set the new base clock frequency.

• MCLK and SYSCLK

MCLK causes a stop in SLEEP/STOP mode while SYSCLK causes a stop only in STOP mode. Use either

depending on each application.

• I²C input/output pin

The SDA and SCL pins of the MB91307 series are pseudo open-drain pins with the P-ch transistor turned off

to prevent the “H” level from being output. As the circuit configuration has a diode added to the V^CCside, therefore,

the communication voltage must be adjusted to the 3.3-V power supply of this model (pulled up to a voltage of

3.3 V) .

• Shared port function switching

To switch a pin that also serves as a port, use the port function register (PFR). Note, however, that bus pins are

switched depending on external bus settings.

• Pull-up control

Connecting a pull-up resistor to the pin serving as an external bus pin cannot a guarantee the AC standard.

Even the port for which a pull-up resistor has been set is invalid in stop mode with HIZ = 1 or in hardware standby

mode.

• I/O port access

Byte access only for access to port

• Remarks for the external clock operation

When selecting the external clock, active X0 pin generally. Also simultaneously the opposite phase clock to X0

must be supplied to X1 pin. When using the clock along with STOP (oscillation stopped) mode, the X1 pin stops

when “H” is input in STOP mode. To prevent one output from competing against another, in this case, the stop

mode must not be used.

16

MB91307 Series

X0

X1

MB91307 series

Using external clock (normal)

Note : Stop mode (oscillation stop mode) cannot be used.

• Low-power consumption modes

• To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the

TBCR, or time-base counter control register) and be sure to use the following sequence:

(LDI

STB

#value_of_standby, R0)

#_STCR, R12)

R0, @R12

; Write to standby control register (STCR)

; Read STCR for synchronous standby

; Read STCR again for dummy read

; NOP x 5 for timing adjustment

LDUB @R12, R0

NOP

Set the I-flag and the ILM and ICR registers to branch to an interrupt handler when the interrupt handler

triggers the microcontroller to return from the standby mode.

• If you use the monitor debugger, follow the precautions below:

Do not set a breakpoint within the above array of instructions.

Do not single-step the above array of instructions.

• Current at power-on (only for MB91V307R)

About 300 mA of power supply current flows when the power is turned on with INIT set to 0.

Set INIT to 1 to stop the overcurrent flowing. After that, the overcurrent will not flow even if INIT is set to 0.

• Watchdog timer

The watchdog timer function of this model monitors that a program delays a reset within a certain period of time

and resets the CPU if the program fails to delay it, for example, because the program runs out of control. Once

the watchdog timer function is enabled, therefore, the watchdog timer countinues to operate until a reset takes

place.

An exception, for example during stop, sleep and DMA transfer modes, is the automatic delaying of a reset under

a condition in which the CPU stops program execution.

Note, however, that a watchdog reset may not occur in the above state caused when the system runs out of

control. If this is the case, use the external INIT pin to cause a reset (INIT).

17

MB91307 Series

• Terminal and timing control register (TCR) (0x00000683)

The terminal and timing control register (TCR) is a write-only register. Therefore, do not access TCR with a bit

manipulation instruction.

If you intend to disable sharing of the bus by writing “0” to Bit 7 (BREN bit) of TCR when the bit is “1”, be sure

to follow the procedure below. If the procedure is not followed, the device may hang up.

1. Write “0” to Bit 2 (BRQE bit) of the port 8 function register (PFR8).

2. Write “0” to Bit 7 (BREN bit) of TCR.

• RD/WR → CS hold extension cycle

Assume that use of the RD/WR → CS hold extension cycle is specified (Bit 0 of AWR is 1) for an

area for which the normal memory/IO access type is set (the TYPE3 to TYPE0 bits of ACR are

0xxx). Even in this case, the hold extension cycle might not be inserted when the operation and

settings are specified in a specific combination.

The hold extension cycle will not be inserted when the following conditions are met:

• Use of the RD/WR → CS hold extension cycle is specified.

(Bit 0 [W00 bit] of AWR is 1.)

• A normal memory/IO access type is set for the area.

(Bits 3 to 0 [TYPE3 to TYPE0 bits] of ACR are 0xxx.)

Note: The MB91307 series allows only this type to be set.

• Disuse of the address → CS delay cycle is specified.

(Bit 2 [W02 bit] of AWR is 0.)

• A setting (recovery enabled) other than 0 cycle is made for the write recovery cycle.

(Bits 5 and 4 [W05 and W04 bits] of AWR are other than 00.)

(Example: First word writing to an external bus 16-bit area)

• If an access is made to write data larger than the bus width to the relevant area under the above conditions,

the RD/WR-CS hold extension cycle is not inserted in any cycle other than the last cycle to write divisions of

the data. Therefore, the hold time becomes insufficient.

Note : This problem does not occur in the read cycle.

To use this function, make either of the following settings:

• Specify the use of the address → CS delay cycle.

(Set 1 for Bit 2 [W02 bit] of AWR.)

• Specify 0 cycle for the write recovery cycle.

(Set 00 for Bits 5 and 4 [W05 and W04 bits] of AWR.)

• Signed DIVIDE statement (DIVOS)

When the instruction immediately before the instruction of DIVOS is an instruction by which the memory access

is done, a correct calculation result might not be obtained.

This is generated under the following conditions.

• When the instruction performs memory accesses just before a DIVOS instruction.

Note : Instructions that performs relevant memory accesses (a total of 58 instructions)

ST Ri, @- R15

ST Rs, @- R15

ST PS, @- R15

STB Ri, @Rj

STB Ri, @ (R13, Rj)

LDUB @Rj, Ri

LDUB @ (R13, Rj), Ri

DMOVB @dir8, R13

DMOVB R13, @dir8

LD @ (R13, Rj), Ri

DMOV @dir10, R13

LD @ (R14, disp10), Ri

STB Ri, @ (R14, disp8)

LDUH @ (R13, Rj), Ri

DMOVH @dir9, R13

18

MB91307 Series

LDUH @ (R14, disp9), Ri

ANDH Rj, @Ri

LDUB @ (R14, disp8), Ri

ANDB Rj, @Ri

AND Rj, @Ri

ORB Rj, @Ri

EORB Rj, @Ri

DMOVB @R13+, @dir8

DMOVB @dir8, @R13+

DMOV @R13+, @dir10

DMOV @dir10, @R13+

DMOV @R15+, @dir10

DMOVH @R13+, @dir9

DMOVH @dir9, @R13+

DMOV @dir10, @- R15

• When full trace mode is specified as trace mode and the DIVOS and DIV1 instructions are not 4-byte aligned.

• Even if the DIVOS and DIV1 instructions are 4-byte aligned, perform a D-bus DMA transfer or specify the full

trace mode as trace mode if a breakpoint is set in the DIV1 instruction.

Avoid this notes as follows:

(1) Do not place an instruction that performs memory access before a DIVOS instruction.

(2) Do not perform a DMA transfer to the D-bus or set full trace mode as trace made when a DIVOS instruction

is specified.

To output the code for avoiding above (1) condition, specify "-@div0s 1" as the compiler option.

SOFTUNE compiler:

• In case of using the SOFTUNE V3: after the SOFTUNE compiler V30L07R07

• In case of using the SOFTUNE V5: after the SOFTUNE compiler V50L04

• In case of using the SOFTUNE V6: after the SOFTUNE compiler V60L01

• DMA demand transfer

In sleep mode, demand transfer is executed only once and processing does not go further. During normal

operation, the efficiency of demand transfers may seem to be lowered.

This action occurs only in demand transfers (it does not occur in DREQ edge detection mode or the like).

This is occurred in the following cases:

• A demand transfer by DMAC is performed in sleep mode.

- After a demand transfer is performed once, processing does not go further although DREQ is input

successively.

- A subsequent transfer is started if the device is released from sleep mode and an external bus operation

other than a DMA transfer occurs.

• A demand transfer by DMAC is performed during normal operation.

- After a demand transfer is performed once, a subsequent transfer is not performed until an external bus

access other than a DMA transfer occurs.

- A demand transfer does not progress while there is no external bus access because cache hitting is

performed continuously or internal ROM operation continues.

• A subsequent demand transfer is not started even if an external bus access for prefetching occurs.

Avoid this notes as follows:

• Do not perform a demand transfer by DMAC in sleep mode.

• Do not use sleep mode during a demand transfer by DMAC.

19

MB91307 Series

• RMW instructions using R15

If one of the instructions listed below is executed, the value of SSP or USP* is not used as the value of R15 and,

as a result, an incorrect value is written to memory. Therefore, the compiler does not generate the following

instructions:

AND

OR

EOR

R15,@Rj

ANDH R15,@Rj

ORH R15,@Rj

EORH R15,@Rj

ANDB

ORB

EORB R15,@Rj

R15,@Rj

XCHB @Rj,R15

* : R15 is an insubstantial register. If R15 is accessed by a program, SSP or USP is accessed according to the

state of the S flag of the PS register.

Avoid this notes as follows:

• When programming any of the above 10 instructions by an assembler, specify a general-purpose register in

place of R15.

• Executing instructions on RAM

• If instruction codes are placed in RAM, they should not be placed in the last 8 address bytes 0005 FFF8^Hto

0005 FFFF^H. (Instruction code prohibited area)

• Notes on the PS register

Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt

handler to break or the PS flag to update its display setting when the debugger is being used. As the microcon-

troller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs oper-

ations before and after the EIT as specified in either case.

• The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS

instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data

event or emulator menu:

(1) D0 and D1 flags are updated earlier.

(2) The EIT handler (user interrupt/NMI or emulator) is executed.

(3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are

updated to the same values as those in (1) above.

• The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed

to enable interruptions when a user interrupt or NMI trigger event has occurred.

(1) The PS register is updated earlier.

(2) The EIT handler (user interrupt/NMI or emulator) is executed.

(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the

same value as that in (1) above.

• Notes on I-bus Memory

Do not access data in the instruction cache control register or the instruction cache RAM immediately before

the RETI instruction.

20

MB91307 Series

■Unique to the evaluation chip MB91V307R

• Simultaneous occurrences of a software break and a user interrupt/NMI

When a software break and a user interrupt /NMI take place at the same time, the emulator debugger can cause

the following phenomena:

• The debugger stops pointing to a location other than the programmed breakpoints.

• The halted program is not re-executed correctly.

If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has

been used, avoid setting any break at the relevant location.

• Single-stepping the RETI instruction

If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly

after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being

executed. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant

interrupt routine becomes unnecessary, perform debugging with that interrupt disabled.

• Break function

• If the address of a current system stack pointer or an area that includes a stack pointer is specified as an

object address of a hardware break (including an event break), a break occurs after one instruction is executed.

The break occurs although the relevant user program does not include an actual data access instruction. To

avoid this problem, do not set the (word) access to an area that includes the address of a system stack pointer

as a target of a hardware break (including an event break).

• If an instruction that causes a wait is executed between an instruction to read a branch destination address

from memory and a branch instruction, an instruction alignment error occurs at a point where an instruction

alignment error cannot occur originally. Then, an ICE break (CPU error break) occurs, and execution of

instructions stops. Furthermore, even if an instruction break is set for the branch destination address at the

point where the above error occurs, a break might not occur.

Example: LD

LD

@R1,R0 ; read F-bus RAM

@R2,R3 ; read F-bus RAM

CALL @R0

; An incorrect alignment error may occur or a break might not occur.

To avoid the incorrect alignment error as described above, turn off the alignment error function in debugger

function setup.

To perform the instruction break correctly, do not specify use of a hardware break, but specify use of a software

break in debugger function setup.

• Trace mode

If the trace mode for debugging is set to full trace mode, which uses internal FIFO memory as the output buffer,

the current may increase or DMA access to the D-bus may be lost.

This is occurred if:

• A DMA transfer to the D-bus or standby mode occurs in full trace mode.

Use internal trace mode to avoid this notes.

21

MB91307 Series

• Alignment error (emulator debugger)

Assume that instruction alignment error break is enabled and an instruction that causes a wait is executed

between an instruction to read a branch destination address from memory and a branch instruction. Under these

conditions, an instruction alignment error occurs at a point where an instruction alignment error cannot occur

originally, an ICE break occurs, and execution of instructions stops. Then, a message indicating an unknown

break factor or a CPU error break is output.

Furthermore, even if an instruction break is set for the branch destination address at the point where the above

error occurs, a break might not occur.

This problem occurs if the following three types of instructions are executed successively:

(1) LD or DMOV instructions causing a wait (reading a branch destination address)

LD

@Rj,Ri

@(R13,Rj)Ri

LDUH @Rj,RI

LDUH @(R13,Rj),Ri

LDUB @(R13,Rj),Ri

@(R14,disp10),Ri LDUH @(R14,disp9),Ri LDUB @(R14,disp8),Ri

@R15+,Ri

LD @R15+,Rs

LD @R15+,PS

DMOV @dir10,R13

DMOVH @dir9,R13

DMOVB @dir8,R13

(2) Instructions causing a wait (reading F-bus RAM or external memory)

(3) Branch instructions such as JMP @Ri, JMP: D @Ri, CALL @Ri, CALL: D @Ri, RET, and RET: D

Example:

LD@R1,R0 ;read F-bus RAM

LD@R2,R3 ;read F-bus RAM

CALL @R0

Avoid this notes as follows:

Assume that instruction alignment error break is enabled and an instruction that causes a wait is executed

between an instruction to read a branch destination address from memory and a branch instruction. Under these

conditions, an instruction alignment error occurs at a point where an instruction alignment error cannot occur

originally, an ICE break occurs, and execution of instructions stops. Then, a message indicating an unknown

break factor or a CPU error break is output.

Furthermore, even if an instruction break is set for the branch destination address at the point where the above

error occurs, a break might not occur.

Avoid this problem as follows:

• To avoid the incorrect alignment error as described above, turn off the alignment error function in debugger

function setup.

• To perform the instruction break correctly, set the break point in an address other than the branch destination

address.

• Operand break

A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data

event break to access to the area containing the address of a system stack pointer.

22

MB91307 Series

■ BLOCK DIAGRAM

CPU Core

32

Instruction

32

cache

1K bytes

Bit search

RAM*

DMAC

5 channels

Bus Converter

32

External

memory

interface

32 16

Adapter

16

Clock control

UART

U-TIMER

I²C

3 channels

1 channel

Interrupt

controller

External

interrupt

Reload

timer

A/D

4 channels

Port

3 channels

* : Internal RAM 128K bytes for MB91307R

64K bytes for MB91306R

23

MB91307 Series

■ CPU AND CONTROL BLOCK

Internal Architecture

The FR series CPU is a high-performance core using RISC architecture with a high-capability instruction set

intended for built-in applications.

1. Features

• Uses of RISC Architecture

Basic instruction set: 1 instruction to 1 cycle.

• 32-bit architecture

General-purpose registers: 32-bits × 16 registers

• 4G bytes linear memory space

• Built-in multipliers

32-bit × 32-bit multiplication: 5 cycles

16-bit × 16-bit multiplication: 3 cycles

• Enhanced interrupt processing

High-speed response (6 cycles)

Multiple interrupt support

Level masking functions (16 levels)

• Enhanced I/O operating instructions

Memory-to-memory transfer instructions

Bit processing instructions

• High code efficiency

Basic instruction length: 16 bits

• Low power consumption

Sleep mode, stop mode

• Gear function

24

MB91307 Series

2. Internal Architecture

The FR series CPU uses a Harvard architecture with independent instruction bus and data bus. The instruction

bus (I-bus) is connected to an on-chip instruction cache. a 32-bit ←→16-bit bus converter is connected to the

bus (F-bus) to provide an interface between the CPU and peripheral resources. The Harvard ←→ Princeton bus

converter is connected to the both the I-bus and D-bus as an interface between the CPU and bus controller.

FRex CPU

D-bus

I-bus

32

I address

I data

Instruction

cache

32

Harvard

D address

D data

Princeton

bus

converter

32

F address

F data

RAM

32 bit

16 bit

Bus converter

16

R-bus

X-bus

Bus controller

Peripherals resource

25

MB91307 Series

3. Programming Model

• Basic Programming Model

32 bits

[Default values]

XXXX XXXX

H

R0

R1

General-purpose register

R12

R13

AC

FP

SP

R14

R15

XXXX XXXX

H

0000 0000

H

PC

Program counter

Program status

PS

⎯

ILM

⎯

SCR

CCR

TBR

RP

Table base register

Return pointer

SSP

USP

System stack pointer

User stack pointer

MDH

MDL

Multiplier result registers

26

MB91307 Series

4. Registers

• General Purpose Register

32 bits

[Default values]

XXXX XXXX^H

R0

R1

R12

R13

AC

XXXX XXXXH

0000 0000H

FP

SP

R14

R15

Registers R 0 to R 15 are general-purpose registers. These registers can be used as accumulators for compu-

tation operations, or as pointers for memory access.

Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular

applications.

R13: Virtual accumulator

R14: Frame pointer

R15: Stack pointer

Default values at reset are undefined for R0 to R14. The value for R15 is 00000000^H(SSP value).

• PS (Program Status Register)

This register holds the program status, and is divided into three parts, ILM, SCR, and CCR.

All bits not defined in the diagram are reserved bits with read value “0” at all times. Write access to these bits

is not enabled.

31

20

16

10

0

Bit position→

8 7

⎯

ILM

SCR

CCR

PS Register

• CCR (Condition Code Register)

7

6

5

4

I

3

2

1

0

[Default value]

- - 00XXXX^B

⎯

S

N

Z

V

C

CCR Register

S : Stack flag, cleared to “0” at reset.

: Interrupt flag, cleared to “0” at reset.

I

N : Negative flag, default value at reset undefined.

Z : Zero flag, default value at reset undefined.

V : Overflow flag, default value at reset undefined.

C : Carry flag, default value at reset undefined.

27

MB91307 Series

• SCR (System Condition code Register)

10

9

8

T

[Default value]

XX0^B

D1 D0

SCR Register

Stepwise division flags

These flags store interim data during execution of stepwise division.

Step trace trap flag

Indicates whether the step trace trap is enabled or disabled.

The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution

of user programs.

• ILM(Interrupt Level Mask Register)

20

19

18

17

16

[Defaultvalue]

01111^B

ILM4 ILM3 ILM2 ILM1 ILM0

ILM Register

This register stores interrupt level mask values, for use in level masking.

The register is initialized to value 15 (01111^B) at reset.

• PC (Program Counte Registerr)

31

0

[Default value]

XXXXXXXX^H

PC

PC Register

The program counter indicates the address of the instruction that is executing.

The default value at reset is undefined.

• TBR (Table Base Register)

31

0

[Defaultvalue]

000FFC00^H

TBR

TBR Register

The table base register stores the starting address of the vector table used in EIT processing.

The default value at reset is 000FFC00^H.

28

MB91307 Series

• RP (Return Pointer)

31

0

[Default value]

XXXXXXXX^H

RP

RP Register

The return register stores the address for return from subroutines.

During execution of a CALL instruction, the PC value is transferred to this RP register.

During execution of a RET instruction, the contents of the RP register are transferred to this PC register.

The default value at reset is undefined.

• SSP (System Stack Pointer)

31

0

[Defaultvalue]

00000000^H

SSP

SSP Register

The SSP register is the system stack pointer.

When the S flag is “0,” this register functions as the R15 register.

The SSP register can also be explicitly specified.

This register is also used as a stack pointer to indicate the stack to which the PS and PC are removed when an

EIT occurs.

The default value at reset is 00000000^H.

• USP (User Stack Pointer)

31

0

[Defaultvalue]

XXXXXXXX^H

USP

USP Register

The USP register is the user stack pointer.

When the S flag is “1,” this register functions as the R15 register.

The USP register can also be explicitly specified.

The default value at reset is undefined.

This register cannot be used with RETI instructions.

• Multiply & Divide registers

31

0

MDH

MDL

Multiply & Divide Registers

The multiply and divide registers are each 32 bits in length.

The default value at reset is undefined.

29

MB91307 Series

■ SETTING MODE

In the FR family, the mode pins (MD2, MD1, MD0) and the mode register (MODR) are used to set the operating

mode.

1. Mode Pins

ThethreepinsMD2, MD1, MD0areusedinmodevectorfetchinstructions, andalsotomakesettingsintestmode.

Mode pin

Mode name

Reset vector access area

Remarks

MD2 MD1 MD0

0

1

External ROM mode vector

Outside

Bus width is set by mode register.

2. Mode Register (MODR)

The mode data fetch instruction writes data to the address “0000 07FD^H” called the mode data.

The area “0000 07FD^H” is the mode register (MODR). When a setting is made to this register, the device will

operate the mode corresponding to that setting.

The mode register can only be set by a reset source at the INIT level. It is not possible to write to this register

from a user program.

Note : No data exists at the FR family mode register address (0000 07FF^H).

< ^{Detailed register description >}

MODR

Default

7

6

0

5

0

4

0

3

0

2

1

0

Address

XXXXXXXX^B

0

ROMA WTH1 WTH0

Operating mode setting bits

0000 07FD^H

[bit7 to bit3] Reserved bits

These bits should always be set to “00000.” If set to any other value, stable operation is not assured.

[bit2] ROMA (Internal RAM enable bit)

This bit indicates whether internal RAM is enabled.

ROMA

Function

External ROM mode

Remarks

0

The built-in RAM area functions as external area.

The built-in RAM area is enabled.

The 128K bytes built-in RAM can be used.

1

Internal RAM mode

[bit1, 0] WTH1, WTH0 (Bus width indicator bits)

In external bus mode, these bits determine the bus width setting.

In external bus mode, the value of these bits sets the BW1, 0 bits in the AMD0 register (CS0 area).

WTH1

WTH0

Bus width

0

1

0

1

0

1

8-bit

16-bit

Setting prohibited

30

MB91307 Series

■ MEMORY SPACE

1. Memory Space

The FR family has 4G bytes (2³²addresses) of logical address space with linear access from the CPU.

•Direct Addressing Areas

The following areas of address space are used for I/O operations.

These areas are called direct addressing areas, in which the address of an operand can be specified directly

during an instruction.

The direct areas differ according to the size of the data accessed, as follows.

→ byte data access

: 000^Hto 0FF^H

→ half word data access : 000^Hto 1FF^H

→ word data access

: 000^Hto 3FF^H

2. Memory Map

The following diagram illustrates memory space in the FR family.

MB91307R

MB91306R/MB91307R

External bus mode

MB91306R

Internal ROM

external bus mode

Internal ROM

external bus mode

0000 0000H

0000 0400H

0000 0000H

Direct addressing

area

I/O

0000 0400H

0001 0000H

Refer to I/O map

0001 0000H

Access

prohibited

Access

prohibited

Access

prohibited

0004 0000H

0005 0000H

0006 0000H

0004 0000H

0006 0000H

Internal RAM

128K bytes

Internal RAM

128K bytes

External area

Access

prohibited

0010 0000H

External area

FFFF FFFFH

31

MB91307 Series

•Use of Built-in RAM

The MB91307R contains 128K bytes of internal RAM, and MB91306R contains 64K bytes of internal RAM. To

enable use of this RAM, the mode register must be set to internal ROM external bus mode (ROMA=1).

Precautions for use of this model

• The reset vector is fixed at 000F FFFC^H.

• For the MB91307R, the 128K bytes RAM area is from 0004 0000^Hto 0005 FFFF^Hand for the MB91306R, the

64K bytes RAM area is from 0004 0000^Hto 0004 FFFF^H. The area from 0006 0000^Hto 000F FFFF^His access

prohibited.

• In order to use RAM the mode register must be set to internal ROM external bus mode.

• In internal ROM external bus mode the built-in RAM area can be used, but the vector area 000F FFXX^His an

internal area and cannot be accessed externally. Please refer to the following explanation.

• When placing instruction code in RAM, nothing should be placed in the last 8 bytes of the area 0005 FFF8^H

to 0005 FFFF^H. (This is an instruction code prohibited area.)

After mode setting

Internal ROM external bus mode

After reset release

0000 0000

0000 0400

H

Direct addressing

area

I/O

Refer to I/O map

0001 0000

H

Access

prohibited

Access

prohibited

Access

prohibited

0004 0000

Internal RAM

64K bytes

Internal RAM

128K bytes

External area

0005 0000

H

0006 0000

H

Access

prohibited

Access

prohibited

0010 0000

External area

FFFF FFFF

H

: The shaded portion is an internal area.

After mode register setting the vector area is an internal area. Therefore before writing to the mode register

it is necessary to rewrite the TBR register so that the vector area is changed to an external area.

32

MB91307 Series

■ USER PROGRAM INITIALIZATION

The following sequence describes an example using built-in RAM.

For the MB91306R, only the internal RAM area is different but the setting is same.

1. Hardware Setting Conditions

MB91307 series

External

ROM

CS0

A19 to A1

1) Assume that 1M bytes of external ROM is placed beginning at 0010 0000^H. Place the program at this location

in the linker. (The following description can apply to other addresses than this one as well.)

2) Connect addresses A19 to A1 (1M bytes) to ROM, other addresses will use CS0.

3) Set the mode pins (MD2, MD1, MD0) to external vectors.

4) Write the reset vector to 001F FFFC^H. Likewise write the mode vector to 001F FFF8^H.

2. Immediately After Reset Release

0000 0000H

MB91307 series

0004 0000H

External

CS0

ROM

External

ROM

FFFF FFFFH

1M bytes of ROM can

be viewed again on the

address map.

After reset release, the CPU will attempt to load a mode vector from 000F FFF8^H, a reset vector from 000F

FFFC^H, however because this will be an external vector, the CPU will have to go externally. However the

1)

CS0 default value causes 1M bytes of external ROM to be repeated in external space, so that the mode

vector and the reset vector itself will load the contents written at 001F FFF8^Hand 001F FFFC^Hin external

ROM.

2) The branch destination is set in the linker to an address in the area 001X XXXX^H, so that subsequent pro-

gram execution will be in this area.

33

MB91307 Series

3. User Program Initialization Steps

0000 0000H

MB91307 series

CS0

0004 0000H

0010 0000H

External

ROM

External

ROM

001F FFFFH

FFFF FFFFH

1M bytes of ROM space

matches 1M bytes of the

address map.

1) Set the TBR register so that the interrupt table is 001F FFXX^H, then perform initialization. This process also

includes a chip select setting, and at the same time the CS0 address is set to be valid at 001X XXXX^H. The

CS0 decoding result is the same before and after the setting, so that the CPU can continue to run programs

on external ROM.

2) If necessary, initialize the contents of RAM.

3) Now initialization is complete, and the application program can be executed.

34

MB91307 Series

■ I/O MAP

This map shows the correlation between areas of memory space and individual registers in peripheral resources.

[How to read the map]

Register

Address

Block

+0

+1

+2

+3

PDR0 [R/W] PDR1 [R/W] PDR2 [R/W] PDR3 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

T-unit

Port Data Register

000000^H

Read/write attributes

Register default value after reset

Register name

^{(1-column registers at address 4n, 2-column registers at address 4n + 2}…⁾

Left most register address

(for word access, the first column of the register contains the MSB end of the data)

Note: Default register bit values are indicated as follows:

“1” : Default value “1”

“0” : Default value “0”

“X” : Default value “X”

“-“ : No physical register at this location

35

MB91307 Series

Register

Address

Block

+0

+1

+2

+3

PDR2 [R/W]

XXXXXXXX

000000^H

000004^H

000008^H

00000C^H

000010^H

⎯

PDR6 [R/W] PDR7 [R/W]

XXXXXXXX -------X

⎯

T-unit

Port Data Register

PDR8 [R/W] PDR9 [R/W] PDRA [R/W] PDRB [R/W]

--X--XXX XXXXXXX- XXXXXXXX XXXXXXXX

⎯

PDRG [R/W] PDRH [R/W] PDRI [R/W]

PDRJ [R/W]

XXXXXXXX

-----XXX

XXX00XXX

---XXXXX

R-bus

Port Data Register

000018^H

to

00001C^H

⎯

000020^H

to

00003C^H

Reserved

EIRR [R/W]

00000000

ENIR [R/W]

00000000

ELVR [R/W]

000040^H

000044^H

000048^H

00004C^H

000050^H

000054^H

000058^H

00005C^H

000060^H

000064^H

000068^H

Ext int

00000000

DICR [R/W] HRCL [R/W]

-------0 0--11111

TMRLR [W]

⎯

DLYI/I-unit

TMR [R]

XXXXXXXX XXXXXXXX

TMCSR [R/W]

XXXXXXXX XXXXXXXX

Reload Timer 0

Reload Timer 1

Reload Timer 2

⎯

----0000 00000000

TMR [R]

TMRLR [W]

XXXXXXXX XXXXXXXX

TMCSR [R/W]

⎯

----0000 00000000

TMR [R]

TMRLR [W]

XXXXXXXX XXXXXXXX

TMCSR [R/W]

⎯

----0000 00000000

SSR [R/W]

00001-00

SIDR [R/W]

XXXXXXXX

SCR [R/W]

00000100

DRCL [W]

--------

SMR [R/W]

00--0-0-

UART0

U-TIMER 0

UART1

UTIM [R] (UTIMR [W] )

00000000 00000000

UTIMC [R/W]

0--00001

SSR [R/W]

00001-00

SIDR [R/W]

XXXXXXXX

SCR [R/W]

00000100

SMR [R/W]

00--0-0-

(Continued)

36

MB91307 Series

Register

Address

00006C^H

000070^H

000074^H

000078^H

00007C^H

000080^H

000084^H

000088^H

00008C^H

000090^H

000094^H

000098^H

00009C^H

0000A0^H

0000A4^H

0000A8^H

0000AC^H

0000B0^H

Block

+0

+1

+2

+3

UTIM [R] (UTIMR [W] )

00000000 00000000

DRCL [W]

--------

UTIMC [R/W]

0--00001

SMR [R/W]

00--0-0-

U-TIMER 1

UART2

SSR [R/W]

00001-00

SIDR [R/W]

XXXXXXXX

SCR [R/W]

00000100

DRCL [W]

--------

UTIM [R] (UTIMR [W] )

00000000 00000000

UTIMC [R/W]

0--00001

[R/W]

U-TIMER 2

ADCR

[R]

ADCS

A/D Converter

sequential comparator

------XX XXXXXXXX

00000000 00000000

⎯

Reserved

IBCR [R/W]

00000000

IBSR [R/W]

00000000

ITBA [R/W]

------00 00000000

ITMK [R/W]

ISMK [R/W]

01111111

ICCR [R/W]

0-011111

ISBA [R/W]

00000000

IDBL [R/W]

-------0

I²C interface

00----11 11111111

IDAR [R/W]

⎯

00000000

⎯

Reserved

(Continued)

37

MB91307 Series

Register

Address

Block

+0

+1

+2

+3

DMACA0 [R/W]

000200^H

000204^H

000208^H

00020C^H

000210^H

000214^H

000218^H

00021C^H

000220^H

000224^H

000228^H

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB4 [R/W]

00000000 00000000 00000000 00000000

DMACA1 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB4 [R/W]

00000000 00000000 00000000 00000000

DMACA2 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB4 [R/W]

DMAC

00000000 00000000 00000000 00000000

DMACA3 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB4 [R/W]

00000000 00000000 00000000 00000000

DMACA4 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB4 [R/W]

00000000 00000000 00000000 00000000

⎯

00022C^H

to

00023C^H

Reserved

DMAC

DMACR [R/W]

000240^H

0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX

000244^H

to

000274^H

⎯

Reserved

000278^H

00027C^H

⎯

Reserved

000280^H

to

0002FC^H

⎯

Reserved

(Continued)

38

MB91307 Series

Register

Address

000300^H

000304^H

Block

+0

+1

+2

+3

⎯

Reserved

ISIZE [R/W]

------00

⎯

Instruction Cache

000308^H

to

0003E0^H

⎯

Reserved

Instruction Cache

Reserved

ICHRC [R/W]

0 - 000000

0003E4^H

⎯

0003E8^H

to

0003EC^H

⎯

BSD0 [W]

0003F0^H

0003F4^H

0003F8^H

0003FC^H

000400^H

000404^H

000408^H

00040C^H

000410^H

000414^H

000418^H

00041C^H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSD1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSDC [W]

Bit Search Module

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSRR [R]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DDRG [R/W] DDRH [R/W] DDRI [R/W] DDRJ [R/W]

----000

00011000

--000000

00000000

⎯

R-bus

Port Direction Register

PFRG [R/W] PFRH [R/W]

----0000 0000000-

PFRI [R/W]

--00-00-

⎯

R-bus

Port Function Register

000420^H

to

00043C^H

⎯

Reserved

(Continued)

39

MB91307 Series

Register

Address

Block

+0

ICR00 [R/W] ICR01 [R/W] ICR02 [R/W] ICR03 [R/W]

---11111 ---11111 ---11111 ---11111

ICR04 [R/W] ICR05 [R/W] ICR06 [R/W] ICR07 [R/W]

---11111 ---11111 ---11111 ---11111

ICR08 [R/W] ICR09 [R/W] ICR10 [R/W] ICR11 [R/W]

---11111 ---11111 ---11111 ---11111

ICR12 [R/W] ICR13 [R/W] ICR14 [R/W] ICR15 [R/W]

---11111 ---11111 ---11111 ---11111

ICR16 [R/W] ICR17 [R/W] ICR18 [R/W] ICR19 [R/W]

---11111 ---11111 ---11111 ---11111

ICR20 [R/W] ICR21 [R/W] ICR22 [R/W] ICR23 [R/W]

---11111 ---11111 ---11111 ---11111

ICR24 [R/W] ICR25 [R/W] ICR26 [R/W] ICR27 [R/W]

---11111 ---11111 ---11111 ---11111

ICR28 [R/W] ICR29 [R/W] ICR30 [R/W] ICR31 [R/W]

---11111 ---11111 ---11111 ---11111

ICR32 [R/W] ICR33 [R/W] ICR34 [R/W] ICR35 [R/W]

---11111 ---11111 ---11111 ---11111

ICR36 [R/W] ICR37 [R/W] ICR38 [R/W] ICR39 [R/W]

---11111 ---11111 ---11111 ---11111

ICR40 [R/W] ICR41 [R/W] ICR42 [R/W] ICR43 [R/W]

---11111 ---11111 ---11111 ---11111

ICR44 [R/W] ICR45 [R/W] ICR46 [R/W] ICR47 [R/W]

+1

+2

+3

000440^H

000444^H

000448^H

00044C^H

000450^H

000454^H

000458^H

00045C^H

000460^H

000464^H

000468^H

00046C^H

Interrupt Control unit

---11111

000470^H

to

00047C^H

⎯

RSRR [R/W] STCR [R/W] TBCR [R/W]

10000000 *²00110011 *²00XXXX00 *¹XXXXXXXX

CTBR [W]

000480^H

000484^H

CLKR [R/W] WPR [W] DIVR0 [R/W] DIVR1 [R/W]

Clock Control unit

Reserved

⎯

00000000 *¹XXXXXXXX 00000011 *¹00000000 *¹

000488^H

to

0005FC^H

⎯

*1: These registers have different default values at reset level. The value shown is the INIT level value.

*2: These registers have different default values at reset level. The value shown is the INIT level value from the INIT

pin.

(Continued)

40

MB91307 Series

Register

Address

000600^H

000604^H

000608^H

Block

+0

+1

+2

+3

DDR2 [R/W]

00000000

⎯

DDR6 [R/W] DDR7 [R/W]

00000000 00000000

⎯

T-unit

Port Direction Register

DDR8 [R/W] DDR9 [R/W] DDRA [R/W] DDRB [R/W]

--0--000

00000000

00060C^H

000610^H

000614^H

⎯

PFR6 [R/W] PFR7 [R/W]

11111111 -------1

PFR8 [R/W] PFR9 [R/W] PFRA [R/W] PFRB1 [R/W]

000618^H

00061C^H

000620^H

000624^H

--1--0--

PFRB2 [R/W]

00------

1111111-

0-001101

00000000

T-unit

Port Function Register

⎯

000628^H

to

00063F^H

⎯

Reserved

ASR0 [R/W]

ACR0 [R/W]

000640^H

000644^H

000648^H

00064C^H

000650^H

000654^H

00000000 00000000

ASR1 [R/W]

1111XX00 00000000

ACR1 [R/W]

XXXXXXXX XXXXXXXX

ASR2 [R/W]

XXXXXXXX XXXXXXXX

ACR2 [R/W]

XXXXXXXX XXXXXXXX

ASR3 [R/W]

XXXXXXXX XXXXXXXX

ACR3 [R/W]

T-unit

XXXXXXXX XXXXXXXX

ASR4 [R/W]

XXXXXXXX XXXXXXXX

ACR4 [R/W]

XXXXXXXX XXXXXXXX

ASR5 [R/W]

XXXXXXXX XXXXXXXX

ACR5 [R/W]

XXXXXXXX XXXXXXXX

(Continued)

41

MB91307 Series

Register

Address

Block

+0

ASR6 [R/W]

+1

+2

ACR6 [R/W]

+3

000658^H

00065C^H

000660^H

000664^H

000668^H

00066C^H

000670^H

000674^H

000678^H

00067C^H

000680^H

000684^H

XXXXXXXX XXXXXXXX

ASR7 [R/W]

XXXXXXXX XXXXXXXX

ACR7 [R/W]

XXXXXXXX XXXXXXXX

AWR0 [R/W]

XXXXXXXX XXXXXXXX

AWR1 [R/W]

011111111 11111111

AWR2 [R/W]

XXXXXXXX XXXXXXXX

AWR3 [R/W]

XXXXXXXX XXXXXXXX

AWR4 [R/W]

XXXXXXXX XXXXXXXX

AWR5 [R/W]

XXXXXXXX XXXXXXXX

AWR6 [R/W]

XXXXXXXX XXXXXXXX

AWR7 [R/W]

XXXXXXXX XXXXXXXX

T-unit

⎯

IOWR0 [R/W] IOWR1 [R/W] IOWR2 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX

⎯

CSER [R/W] CHER [R/W]

TCR [R/W]

00000000

⎯

000000001

11111111

⎯

000684^H

to

0007F8^H

⎯

Reserved

⎯

0007FC^H

000800^H

to

000AFC^H

Reserved

ESTS0 [R/W] ESTS1 [R/W] ESTS2 [R]

X0000000 XXXXXXXX 1XXXXXXX

000B00^H

000B04^H

⎯

DSU

ECTL0 [R/W] ECTL1 [R/W] ECTL2 [W] ECTL3 [R/W]

0X000000 00000000 000X0000 00X00X11

(Continued)

42

MB91307 Series

Register

Address

000B08^H

000B0C^H

000B10^H

Block

+0

+1

ECNT1 [W]

+2

+3

ECNT0 [W]

EUSA [W]

XXX00000

EDTC [W]

0000XXXX

XXXXXXXX XXXXXXXX

EWPT [R]

⎯

00000000 00000000

EDTR0 [W]

EDTR1 [W]

XXXXXXXX XXXXXXXX

000B14^H

to

000B1C^H

⎯

EIA0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA1 [W]

000B20^H

000B24^H

000B28^H

000B2C^H

000B30^H

000B34^H

000B38^H

000B3C^H

000B40^H

000B44^H

000B48^H

000B4C^H

000B50^H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA2 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA3 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA4 [W]

DSU

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA5 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA6 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA7 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EDTA [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EDTM [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOA0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOA1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EPCR [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

(Continued)

43

MB91307 Series

(Continued)

Register

Address

Block

+0

+1

+2

+3

EPSR [R/W]

000B54^H

000B58^H

000B5C^H

000B60^H

000B64^H

000B68^H

000B6C^H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIAM0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIAM1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOAM0/EODM0 [W]

DSU

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOAM1/EODM1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOD0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOD1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B70^H

to

000FFC^H

⎯

Reserved

DMASA0 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMADA0 [R/W]

001000^H

001004^H

001008^H

00100C^H

001010^H

001014^H

001018^H

00101C^H

001020^H

001024^H

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMASA1 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMADA1 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMASA2 [R/W]

DMAC

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMADA2 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMASA3 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMADA3 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMASA4 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMADA4 [R/W]

DMAC

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

44

MB91307 Series

■ INTERRUPT SOURCES AND INTERRUPT VECTORS

Interrupt number

Interrupt source

Interrupt level Offset TBR default address

Decimal

0

Hex

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

Reset

⎯

3FC^H

3F8^H

3F4^H

3F0^H

3EC^H

3E8^H

3E4^H

3E0^H

3DC^H

3D8^H

3D4^H

3D0^H

3CC^H

3C8^H

3C4^H

3C0^H

3BC^H

3B8^H

3B4^H

3B0^H

3AC^H

3A8^H

3A4^H

3A0^H

39C^H

398^H

394^H

390^H

38C^H

388^H

384^H

380^H

37C^H

378^H

000FFFFC^H

000FFFF8^H

000FFFF4^H

000FFFF0^H

000FFFEC^H

000FFFE8^H

000FFFE4^H

000FFFE0^H

000FFFDC^H

000FFFD8^H

000FFFD4^H

000FFFD0^H

000FFFCC^H

000FFFC8^H

000FFFC4^H

000FFFC0^H

000FFFBC^H

000FFFB8^H

000FFFB4^H

000FFFB0^H

000FFFAC^H

000FFFA8^H

000FFFA4^H

000FFFA0^H

000FFF9C^H

000FFF98^H

000FFF94^H

000FFF90^H

000FFF8C^H

000FFF88^H

000FFF84^H

000FFF80^H

000FFF7C^H

000FFF78^H

Mode vector

1

System reserved

2

⎯

System reserved

3

⎯

System reserved

4

⎯

System reserved

5

⎯

System reserved

6

⎯

Coprocessor absent trap

Coprocessor error trap

INTE instruction

7

⎯

8

⎯

9

⎯

Instruction break exception

Operand break trap

Step trace trap

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

⎯

NMI request (tool)

Undefined instruction exception

NMI requ

⎯

15 (F^H)

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

ICR16

ICR17

External interrupt 0

External interrupt 1

External interrupt 2

External interrupt 3

External interrupt 4

External interrupt 5

External interrupt 6

External interrupt 7

Reload timer 0

Reload timer 1

Reload timer 2

UART0(RX completed)

UART1(RX completed)

UART2(RX completed)

UART0(TX completed)

UART1(TX completed)

UART2(TX completed)

DMAC0(end, error)

(Continued)

45

MB91307 Series

Interrupt number

Interrupt source

Interrupt level Offset TBR default address

Decimal

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

Hex

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

43

44

DMAC1(end, error)

DMAC2(end, error)

DMAC3(end, error)

DMAC4(end, error)

A/D

ICR18

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

ICR32

ICR33

ICR34

ICR35

ICR36

ICR37

ICR38

ICR39

ICR40

ICR41

ICR42

ICR43

ICR44

ICR45

ICR46

ICR47

⎯

374^H

370^H

36C^H

368^H

364^H

360^H

35C^H

358^H

354^H

350^H

34C^H

348^H

344^H

340^H

33C^H

338^H

334^H

330^H

32C^H

328^H

324^H

320^H

31C^H

318^H

314^H

310^H

30C^H

308^H

304^H

300^H

2FC^H

2F8^H

2F4^H

2F0^H

2EC^H

000FFF74^H

000FFF70^H

000FFF6C^H

000FFF68^H

000FFF64^H

000FFF60^H

000FFF5C^H

000FFF58^H

000FFF54^H

000FFF50^H

000FFF4C^H

000FFF48^H

000FFF44^H

000FFF40^H

000FFF3C^H

000FFF38^H

000FFF34^H

000FFF30^H

000FFF2C^H

000FFF28^H

000FFF24^H

000FFF20^H

000FFF1C^H

000FFF18^H

000FFF14^H

000FFF10^H

000FFF0C^H

000FFF08^H

000FFF04^H

000FFF00^H

000FFEFC^H

000FFEF8^H

000FFEF4^H

000FFEF0^H

000FFEEC^H

I²C

System reserved

U-TIMER0

U-TIMER1

U-TIMER2

Time base timer overflow

System reserved

Delay interrupt source bit

System reserved (REALOS use)

System reserved

⎯

(Continued)

46

MB91307 Series

(Continued)

Interrupt source

Interrupt number

Interrupt level Offset TBR default address

Decimal

69

Hex

45

System reserved

⎯

2E8^H

2E4^H

2E0^H

2DC^H

2D8^H

2D4^H

2D0^H

2CC^H

2C8^H

2C4^H

2C0^H

000FFEE8^H

000FFEE4^H

000FFEE0^H

000FFEDC^H

000FFED8^H

000FFED4^H

000FFED0^H

000FFECC^H

000FFEC8^H

000FFEC4^H

000FFEC0^H

70

46

71

47

72

48

73

49

74

4A

4B

4C

4D

4E

4F

75

76

77

78

79

80

to

255

50

to

FF

2BC^H

to

000^H

000FFEBC^H

to

000FFC00^H

Used by INT instructions

⎯

47

MB91307 Series

■ PERIPHERAL RESOURCES

1. Interrupt Controller

(1) Overview

The interrupt controller receives and processes arbitration of interrupts.

•Hardware Configuration

This module is configured from the following elements.

• ICR register

• Interrupt priority determination circuit

• Interrupt level and interrupt number (vector) generator

• Hold request removal request generator

•Principal Functions

This module primarily provides the following functions.

• NMI request / interrupt request detection

• Order of priority determination (according to level and number)

• Notification (to CPU) of interrupt level of source according to determination

• Notification (to CPU) of interrupt number of source according to determination

• Instruction (to CPU) to recover from stop mode when an interrupt other than NMI/interrupt level “11111” is

generated

• Generation of hold request removal requests to the bus master

48

MB91307 Series

(2) Register List

bit 7

6

5

4

3

2

1

0

Address:

⎯

ICR4

ICR3

ICR2

ICR1

R/W

ICR0

R/W

00000440

H

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

ICR16

ICR17

ICR18

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

Address:

⎯

ICR4

R

ICR3

R/W

ICR2

R/W

00000441

00000442

00000443

00000444

00000445

00000446

00000447

00000448

00000449

0000044A

0000044B

0000044C

0000044D

0000044E

0000044F

00000450

00000451

00000452

00000453

00000454

00000455

00000456

00000457

00000458

00000459

0000045A

0000045B

0000045C

0000045D

0000045E

0000045F

(Continued)

49

MB91307 Series

(Continued)

bit 7

6

5

4

3

2

1

0

Address:

⎯

ICR4

ICR3

ICR2

ICR1

ICR0

00000460H

00000461H

00000462H

00000463H

00000464H

00000465H

00000466H

00000467H

00000468H

00000469H

0000046AH

0000046BH

0000046CH

0000046DH

0000046EH

0000046FH

ICR32

ICR33

ICR34

ICR35

ICR36

ICR37

ICR38

ICR39

ICR40

ICR41

ICR42

ICR43

ICR44

ICR45

ICR46

ICR47

⎯

ICR4

R

ICR3

R/W

ICR2

R/W

ICR1

R/W

ICR0

R/W

Address:

MHALTI

R/W

⎯

LVL4

R

LVL3

R/W

LVL2

R/W

LVL1

R/W

LVL0

R/W

00000045H

HRCL

50

MB91307 Series

(3) Block Diagram

(“1” when LEVEL ≠ 11111)

WAKEUP

UNMI

Determine order of priority

5

LEVEL4 to LEVEL0

NMI

processing

HLDREQ

MHALTI

hold

request

LEVEL

determination

LEVEL,

VECTOR

generation

6

ICR00

RI00

VCT5 to VCT0

VECTOR

determination

ICR47

RI47

(DLYIRQ)

R-bus

51

MB91307 Series

2. External Interrupt - NMI Control Block

(1) Overview

The External Interrupt-control block controls external interrupt requests input at the NMI and INT0 to INT7 pins.

The request level can be selected from “H,” “L,” “rising edge,” or “falling edge” detection (except for NMI).

(2) Register List

• External interrupt enable register (ENIR)

bit

7

6

5

4

3

2

1

0

EN7

EN6

EN5

EN4

EN3

EN2

EN1

EN0

• External interrupt source register (EIRR)

bit

15

14

13

12

11

10

9

8

ER7

ER6

ER5

ER4

ER3

ER2

ER1

ER0

• Request level setting register (ELVR)

bit

15

14

13

12

11

10

9

8

LB7

LA7

LB6

LA6

LB5

LA5

LB4

LA4

bit

7

6

5

4

3

2

1

0

LB3

LA3

LB2

LA2

LB1

LA1

LB0

LA0

(3) Block Diagram

R-bus

8

9

8

Interrupt enable register

Source F/F

Interrupt

request

9

INT0 to INT7

NMI

Gate

Edge detection circuit

Interrupt source register

Interrupt level setting register

52

MB91307 Series

3. REALOS Related Hardware

REALOS related hardware is used by the REALOS operating system. Therefore, when REALOS is in use, these

resources cannot be used by user programs.

• Delay Interrupt Module

(1) Overview

The delay interrupt module is a module that generates interrupts for task switching. This module can be used

with software instructions to generate and cancel interrupts to the CPU.

(2) Register List

bit

7

6

5

4

3

2

1

0

Address :

⎯

DLYI

[R/W]

00000044H

DICR

(3) Block Diagram

R-bus

DLYI

Interrupt request

53

MB91307 Series

• Bit Search Module

(1) Overview

Searches data written to input registers for “0” or “1” or change points, and outputs the value of the detected bits.

(2) Register List

31

0

Address :

0 detection data register

1 detection data register

Change point detection register

Detection results register

BSD0

BSD1

BSDC

BSRR

000003F0

000003F4

000003F8

000003FC

H

(3) Block Diagram

D-bus

Input latch

Detection

mode

Address

decoder

1 detection data capture

Bit search circuit

Search results

54

MB91307 Series

4. 16-bit Reload Timer

(1) Overview

The 16-bit timer is configured from a 16-bit down-counter, 16-bit reload register, prescaler for internal count clock

generation, and a control register.

For the input clock signal, a selection of three internal clock signals (machine clock multiplied by 2, 8, or 32) or

external clock is provided.

The output pin (TOUT) produces a toggle output waveform at every underflow in reload mode, and a square

wave indicating counting in progress in one-shot mode.

The input pin (TIN) can be used for event input in external event count mode, and trigger input or gate input in

internal clock mode.

The external event count function can be used in reload mode or as a frequency multiplier in external clock mode.

The MB91306R/MB91307R contain 3 channels (0 to 2) of this timer.

(2) Register List

• Control status register (TMCSR)

15

14

13

12

11

10

9

8

⎯

CSL1

CSL0

MOD2 MOD1

7

6

5

4

3

2

1

0

MOD0

⎯

OUTL

RELD

INTE

UF

CNTE

TRG

• 16-bit timer register (TMR)

15

0

• 16-bit reload register (TMRLR)

15

55

MB91307 Series

(3) Block Diagram

16

16-bit reload register

8

Reload

RELD

OUTE

OUTL

INTE

UF

16-bit down counter

16

2

OUT

CTL.

GATE

2

IRQ

CSL1

Clock selector

CNTE

TRG

CSL0

Re-trigger

2

Port (TIN)

Port (TOT)

IN CTL.

EXCK

3

Prescaler

clear

φ

2¹2³2⁵

MOD2

MOD1

MOD0

Internal clock

3

56

MB91307 Series

5. U-TIMER (16 bit timer for UART baud rate generation)

(1) Overview

The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Any desired baud rate can be set

using the combination of chip operating frequency and U-TIMER reload value.

The U-TIMER can also be used as an interval timer by generating an interrupt from a count underflow event.

This device features a 3-channel built-in U-TIMER. By connecting two U-TIMER channels used as interval timers

in a cascade connection, it is possible to count intervals up to a maximum of 2³²× φ.

The available case connections are channel 0 to channel 1, and channel 1 to channel 2.

(2) Register List

15

8

7

0

UTIM

UTIMR

(R)

(W)

UTIMC

(R/W)

(3) Block Diagram

15

0

UTIMR (reload register)

Load

UTIM (timer)

Clock

Underflow

control

φ

MUX

(Peripheral clock)

Channel 0 only

f.f.

To UART

Under flow U-TIMER 1

57

MB91307 Series

6. UART

(1) Overview

The UART is an I/O port for asynchronous (start-stop synchronized) or CLK synchronized transmission, providing

the following features. This device features a 3-channel built-in UART.

• Full duplex double buffer

• Asynchronous (start-stop synchronized) or CLK synchronized transmission enabled

• Supports multi-processor mode

• Fully programmable baud rate

Built-in timer can be set to any desired baud rate (see U-TIMER description)

• Independent baud rate setting from external clock enabled.

• Error detection functions (parity, framing, overrun)

• Transfer signal NRZ encoded

• DMA transfer start from interrupt enabled

• DMAC interrupt source cleared by write operation to DRCL register.

(2) Register List

15

8

7

0

SCR

SSR

SMR

(R/W)

SIDR (R)/SODR (W)

DRCL

8 bit

(W)

8 bit

• Serial input register/Serial output registe (SIDR/SODR)

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

• Serial status register (SSR)

7

6

5

4

3

2

1

0

PE

ORE

FRE

RDRF TDRE

⎯

RIE

TIE

• Serial mode register (SMR)

7

6

5

4

3

2

1

0

MD1

MD0

⎯

CS0

⎯

SCKE

⎯

• Serial control register (SCR)

7

6

5

4

3

2

1

0

PEN

P

SBL

CL

A/D

REC

RXE

TXE

• DRCL register (DRCL)

7

6

5

4

3

2

1

0

⎯

58

MB91307 Series

(3) Block Diagram

Control signal

RX interrupt

(to CPU)

SC (clock)

TX clock

TX interrupt

(to CPU)

From U-TIMER

Clock select

circuit

RX clock

External clock

SC

RX control circuit

TX control circuit

SI (receiving data)

Start bit detect

circuit

Sent start

circuit

Receiving bit

counter

Sending bit

counter

Receiving parity

counter

Sending parity

counter

SO (Sending data)

Receiving status

decision circuit

Receiving shifter

Sending shifter

Receiving

end

Sending

start

SIDR

SODR

DMA receiving

error signal

(to DMAC)

R-bus

MD1

MD0

PEN

P

PE

ORE

FRE

SBL

SMR

register

SCR

register

SSR

register

CL

RDRF

TDRE

CS0

A/D

REC

RXE

TXE

SCKE

SOE

RIE

TIE

Control signal

59

MB91307 Series

7. A/D Converter (Sequential comparison type)

(1) Overview

This A/D converter is a module that coverts analog input voltages to digital values, and provides the following

features.

• Minimum conversion time 5.4 µs/ch (at machine clock 33 MHz-CKLP)

• Built-in sample & hold circuit

• Resolution 10 bits (8-bit accuracy)

• Analog input: 4 channels by program selection

Single conversion mode: Conversion on 1 select channel

Scan conversion mode: Select continuous multiple channels. Up to 4 channels can be selected by program.

Continuous conversion mode: Continuous conversion on selected channel

Stop conversion mode: 1-channel conversion then pause and wait until the next start is applied

(enables synchronized conversion start)

• DMA transfer start from interrupt enabled

• Start sources can be selected from software, external trigger (falling edge), reload timer (rising edge).

(2) Register List

• Control status register (ADCS)

bit

15

14

13

12

11

10

9

8

BUSY

INT

INTE

PAUS

STS1

STS0

STRT

⎯

bit

7

6

5

4

3

2

1

0

MD1

MD0

ANS2

ANS1

ANS0

ANE2

ANE1

ANE0

• Data register (ADCR)

bit

15

14

13

12

11

10

9

8

⎯

bit

7

6

5

4

3

2

1

0

60

MB91307 Series

(3) Block Diagram

AVCC AVRH AVSS

Internal voltage

Sample & hold circuit

Sequential

Data register (ADCR)

AD control register

Channel decoder

Timing generator

Clock (CLKP)

Prescaler

ATG (External pin trigger)

Reload timer ch1 (Internal connection)

(4) Precautions for Use:

When the A/D converter is started from an external trigger or internal timer, the ADCS register A/D start source

bits STS1, STS0 are set, and at this time the input values for the external trigger and internal timer should be

set to the inactive side. If these values are set to the active side, abnormal operation may result.

When setting the STS1, STS0 bits, set ATG = “1” input, reload timer (channel 2) = “0” output.

Note : If internal impedance is higher than the specified value, it may not be possible to obtain analog input

value sampling within the specified sampling time, so that proper results will not be obtained.

61

MB91307 Series

8. I²C Interface

(1) Overview

The I²C interface operates as a master/slave device on the I²C bus at serial I/O ports with IC bus support. The

following features are provided.

• Master/slave sending and receiving

• Arbitration function

• Clock synchronization function

• Slave address/general call address detection function

• Transfer direction detection function

• Start condition repeat generation and detection function

• Bus error detection function

• 10-bit/7-bit master/slave addressing

• Compatible with standard mode (Max 100 Kbps) or high speed mode (Max 400 Kbps)

• Transfer end interrupt/bus error interrupt generation

(2) Register List

• Bus Control Register (IBCR)

15

14

13

12

11

10

9

8

Address : 000094^H

Default value →

BER

BEIE

SCC

MSS

ACK

GCAA

INTE

INT

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bus Status Register (IBSR)

Address : 000095^H

Default value →

7

6

5

4

3

2

1

0

BB

RSC

AL

LRB

TRX

AAS

GCA

ADT

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• 10-Bit Slave Address Register

Address : 000096^H

15

14

13

12

11

10

9

8

⎯

TA9

TA8

R/W

0

R/W

0

Default value →

⎯

7

6

5

4

3

2

1

0

Address : 000097^H

TA7

TA6

TA5

TA4

TA3

TA2

TA1

TA0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Default value →

(Continued)

62

MB91307 Series

(Continued)

• 10-Bit Slave Address Mask Register (ITMK)

15

14

13

12

11

10

9

8

Address : 000098^H

ENTB

RAL

⎯

TM9

TM8

R/W

0

R

0

R/W

1

R/W

1

Default value →

⎯

7

6

5

4

3

2

1

0

Address : 000099^H

TM7

TM6

TM5

TM4

TM3

TM2

TM1

TM0

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Default value →

• 7-Bit Slave Address Register (ISBA)

7

6

5

4

3

2

1

0

Address : 00009B^H

⎯

SA6

SA5

SA4

SA3

SA2

SA1

SA0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Default value →

⎯

• 7-Bit Slave Address Mask Register (ISMK)

15

14

13

12

11

10

9

8

Address : 00009A^H

ENSB

SM6

SM5

SM4

SM3

SM2

SM1

SM0

R/W

0

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Default value →

• Data Register (IDAR)

7

6

5

4

3

2

1

0

Address : 00009D^H

D7

D6

D5

D4

D3

D2

D1

D0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Default value →

• Clock Control Register (ICCR)

15

14

13

12

11

10

9

8

Address : 00009E^H

TEST

⎯

EN

CS4

CS3

CS2

CS1

CS0

W

0

R/W

0

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Default value →

⎯

• Clock Disable Register (IDBL)

7

6

5

4

3

2

1

0

Address : 00009F^H

⎯

DBL

R/W

0

Default value →

⎯

63

MB91307 Series

(3) Block Diagram

ICCR

EN

I²C operation enabled

Clock enabled

IDBL

DBL

ICCR

Clock multiplier 2

2 3 4 5

CS4

CS3

CS2

CS1

CS0

Sync

32

Shift clock generator

Clock select 2 (1/12)

Shift clock

edge change

IBSR

Bus busy

BB

Repeat start

RSC

LRB

TRX

Start - stop

condition detector

Last Bit

TX/RX

Error

First Byte

ADT

AL

Arbitration lost detector

IBCR

BER

SCL

BEIE

INTE

INT

SDA

Interrupt request

IRQ

End

IBCR

SCC

Start

Master

MSS

ACK

Start - stop

condition generator

ACK OK

GC-ACK OK

GCAA

IDAR

IBSR

AAS

Slave

Global call

Slave address

compare

GCA

ENTB

ISMK

RAL

ITBA

ITMK

ISBA

ISMK

64

MB91307 Series

9. DMAC (DMA Controller)

(1) Overview

This module is used to accomplish DMA (Direct Memory Access) transfer on FR family devices.

DMA transfer controlled by this module increases system performance by enabling high speed transfer of many

types of data without going through the CPU.

•Hardware Configuration

This module is principally configured from the following units:

• Five independent DMA channels

• 5 channels independent access control circuit

• 32-bit address registers (reload enabled: 2 per channel)

• 16-bit transfer count registers (reload enabled: 2 per channel)

• 4-bit block count registers (1 per channel)

• External transfer request input pins: DREQ0,DREQ1,DREQ2 (ch0, ch1, ch2 only)

• External transfer request acknowledge output pins: DACK0,DACK1,DACK2 (ch0, ch1, ch2 only)

• DMA output completed pins: DEOP0,DEOP1,DEOP2 (ch0, ch1, ch2 only)

• Fly-by transfer (memory to I/O, memory to memory) (ch0, ch1, ch2 only)

• Two-cycle transfer

•Principal Functions

Data transfer using the DMAC module primarily involves the following functions:

• Supports independent data transfer on multiple channels (5 channels)

(1) Order of priority (ch0 > ch1 > ch2 > ch3 > ch4)

(2) The order can be reversed between ch0 and ch1.

(3) DMAC startup sources

• Input from an external-only pin (edge detection/level detection, ch0, ch1, ch2 only)

• Request from a built-in peripheral (shared interrupt request, including external interrupts)

• Software request (register write)

(4) Transfer modes

• Demand transfer / burst transfer / step transfer / block transfer

• Addressing mode 32-bit full address designation (increment/decrement/fixed)

(address increment can be specified up to -255 to +255)

• Data type, byte / half-word / word length

• Single-shot / reload selection available

65

MB91307 Series

(2) Register Descriptions

(bit) 31

24 23 16 15 08 07

00

DMACA0 0000200

H

ch0 Control/status register A

ch0 Control/status register B

ch1 Control/status register A

ch1 Control/status register B

ch2 Control/status register A

ch2 Control/status register B

ch3 Control/status register A

ch3 Control/status register B

ch4 Control/status register A

ch4 Control/status register B

Overall control register

DMACB0 0000204

DMACA1 0000208

DMACB1 000020C

DMACA2 0000210

DMACB2 0000214

DMACA3 0000218

DMACB3 000021C

DMACA4 0000220

DMACB4 0000224

DMACR 0000240

DMASA0 0001000

DMADA0 0001004

DMASA1 0001008

DMADA1 000100C

DMASA2 0001010

DMADA2 0001014

DMASA3 0001018

DMADA3 000101C

DMASA4 0001020

DMADA4 0001024

H

ch0 Transfer source address register

ch1 Transfer source address register

ch2 Transfer source address register

ch3 Transfer source address register

ch4 Transfer source address register

66

MB91307 Series

(3) Block Diagram

Counter

Peripheral start request/stop

input

DMA start

source selection

circuit & request

acceptance

DMA transfer request to

bus controller

Buffer

Selector

External pin start request/stop

input

control

DTC two-stage register

DTCR

Counter

Buffer

DSS3 to DSS0

Priority

circuit

IRQ4 to

IRQ0

To interrupt controller

ERIR, EDIR

Read/write

control

Selector

Read

Write

MCLREQ

BLK register

Peripheral interrupt clear

Status

transition

circuit

TYPE, MOD, WS

DDNO register

DDNO

To bus

controller

DMA controller

DDAD two-stage register

SDAM, SASZ7 to SASZ0 SADR

Write back

Access

address

DDAD two-stage register

DADM, DASZ7 to DASZ0 DADR

Write back

DMAC 5-channel Block Diagram

67

MB91307 Series

10. External Interface

(1) Overview

The external interface controller controls the interface between the LSI’s internal bus and external memory or I/

O devices.

This section describes the functions of the external interface.

(2) Features

• Up to 32 bit-length (4G bytes space) address output.

• Connects directly to many external memory (8 bit/16 bit) devices, allows control of multiple access timings.

Asynchronous SRAM, asynchronous ROM/Flash memory (multiple write strobe type or byte enable type)

Page mode ROM/flash memory (2/4/8 page size enabled)

Burst ROM/Flash memory (MBM29BL160D/161D/162D etc.)

Address/data multiplexed bus (8 bit/16 bit width only)

Synchronous memory* (ASIC built-in memory etc.)

*: Does not connect to synchronous SRAM.

• 8 independent bank (chip select area) settings, each with corresponding chip select output available

Each area size can be set in multiples of 64K bytes (from 64K bytes to 2G bytes per chip select area).

Each area can be set in any desired area of logic address space (boundaries limited by area size).

• The following functions can be independently set for each chip select area.

Chip select area enable/disable (no access to prohibited areas)

Access timing type for each area, etc.

Detailed access timing settings (individual access type settings for wait cycle, etc.)

Data bus width setting (8 bit/16 bit)

Byte ordering endian setting* (big or little).

*: CS0 area available with big endian only.

Write prohibited setting (read-only areas)

Internal cache loading enable/disable settings

Pre-fetch function enable/disable settings

Maximum burst length setting (1,2,4,8)

• Different detailed timing settings for each access timing type

Different settings can be used for each chip select area even for the same access timing type.

Auto wait setting up to 15 cycles (asynchronous SRAM, ROM, Flash, I/O areas)

Bus cycle extension with external RDY input enabled (asynchronous SRAM, ROM, Flash, I/O areas)

First access wait and page wait settings enabled (burst, page mode ROM/FLASH areas)

Different idle, recovery cycles setup delay insertion etc. enabled

• Fly-by transfer with DMA enabled

Transfer between memory and I/O with 1 access

Memory wait cycle can be synchronized with I/O wait cycle during fly-by

Hold time can be obtained by delaying transfer access only

Specific idle/recovery cycles can be set for fly-by transfer

• External bus arbitration using BRQ and BGRNT enabled

• Pins not used in external interface can be set for use as general purpose I/O ports

68

MB91307 Series

(3) Block Diagram

Internal

address bus

Internaldata

bus

32

External data bus

Switch

Write buffer

Read buffer

MUX

Data block

Address block

+1 or +2

External address bus

Address buffer

ASR

ASZ

CS0 to CS7

Comparator

RD

External pin control block

WR0, WR1

AS, BAA

All block control

BRQ

BGRNT

RDY

Resisters &

controls

(4) I/O Pins

These are the external interface pins. (Some pins have dual functions.)

< Normal bus interface >

A24 to A0, D31 to D16

CS0, CS1, CS2, CS3, CS4, CS5, CS6, CS7

AS, SYSCLK, MCLK

RD

WE, WR0 (UUB) , WR1 (ULB)

RDY, BRQ, BGRNT

< Memory interface >

MCLK

LBA ( = AS) , BAA*

*: For burst ROM, Flash use

69

MB91307 Series

< DMA interface >

IOWR, IORD

DACK0, DACK1, DACK2

DREQ0, DREQ1, DREQ2

DEOP0/DSTP0, DEOP1/DSTP1, DEOP2/DSTP2

(5) Register List

Address 31

00000640^H

00000644^H

00000648^H

0000064C^H

00000650^H

00000654^H

00000658^H

0000065C^H

00000660^H

00000664^H

00000668^H

0000066C^H

24 23

16 15

08 07

ACR0

ACR1

ASR2

ACR3

ACR4

ACR5

ACR6

ACR7

AWR1

AWR3

AWR5

AWR7

00

ASR0

ASR1

ASR2

ASR3

ASR4

ASR5

ASR6

ASR7

AWR0

AWR2

AWR4

AWR6

00000670^HReserved Reserved Reserved Reserved

00000674^HReserved Reserved Reserved Reserved

00000678^H

0000067C^HReserved Reserved Reserved Reserved

00000680^HCSER CHER Reserved TCR

IOWR0

IOWR1

IOWR2

Reserved

00000684^HReserved Reserved Reserved Reserved

00000688^HReserved Reserved Reserved Reserved

0000068C^HReserved Reserved Reserved Reserved

• • •

000007F8^HReserved Reserved Reserved Reserved

000007FC^HReserved (MODR) Reserved Reserved

• • •

Reserved: This address is reserved, and should always be set to “0.”

MODR: Cannot be accessed from user programs.

70

MB91307 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Parameter

Supply voltage*¹

Symbol

Unit

Remarks

Min

Max

V^CC

V^CCI

V^SS− 0.5

V^SS+ 4.0

V^SS+ 2.2

V^SS+ 4.0

V^CC+ 0.3

V

*2

*3

*8

Internal supply voltage

V^SS− 0.5

Analog supply voltage

AV^CC

AVRH

V^I

V^SS− 0.5

V

Analog reference voltage

Input voltage*¹

V^SS− 0.5

V

V^SS− 0.3

V

Analog pin input voltage

V^IA

V^SS− 0.3

AV^CC+ 0.3

V^CC+ 0.3

2.0

V

Output voltage*¹

V^O

V^SS− 0.3

− 2.0

⎯

V

*8

*7

*4

*5

Maximum clamp current

I^CLAMP

Σ⏐ICLAMP⏐

I^OL

mA

mW

°C

Total maximum clamp current

L level maximum output current

L level average output current

L level maximum total output current

L level average total output current

H level maximum output current

H level average output current

H level maximum total output current

H level average total output current

Power consumption

20

⎯

10

I^OLAV

ΣI^OL

⎯

8

⎯

100

50

ΣI^OLAV

I^OH

⎯

*6

*4

*5

⎯

−10

−4

I^OHAV

ΣI^OH

ΣI^OHAV

P^D

⎯

−50

−20

750

+70

+150

⎯

*6

⎯

Operating temperature

T^A

0

Storage temperature

T^STG

⎯

*1 : The parameter is based on V^SS= AV^SS= 0 V.

*2 : V^CCmust not be lower than V^SS− 0.3 V.

*3 : AV^CCand AVRH shall never exceed V^CC+ 0.3 V. Also AVRH shall never exceed AV^CC.

*4 : Maximum output current determines the peak value of any one of the corresponding pins.

*5 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the

corresponding pins.

*6 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the

corresponding pins.

*7 : • Applicable to pins : P20 to P27, P60 to P67, P70, PJ0 to PJ7, PI0 to PI5, PH0 to PH7, PB0 to PB5, PA0 to

PA7, P80 to P82, P85, P90 to P97, AN0 to AN3

• Use within recommended operating conditions.

• Use at DC voltage (current) .

• The +B signal should always be applied with a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

71

MB91307 Series

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect

other devices.

• Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V), the power supply is

provided from the pins, so that incomplete operation may result.

•Note that if the +B input is applied during power-on, the power supply is provided from the pins and the

resulting supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input

pins, etc.) cannot accept +B signal input.

• Sample recommended circuits :

•Input/Output Equivalent circuits

Protective diode

VCC

P-ch

N-ch

Limiting

resistance

+B input (0 V to 16 V)

R

*8 : V^Iand V^Omust never exceed V^CC+ 0.3 V. However if the maximum current to/from an input is limited by some

means with external components, the I^CLAMPrating supersedes the V^Irating.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

72

MB91307 Series

2. Recommended Operating Conditions

(V^SS= AV^SS= 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

3.0

Max

3.6

V^CC

V^CCI

V

Supply voltage

1.65

V^SS− 0.3

AV^SS

0

1.95

Analog supply voltage

Analog reference voltage

Operating temperature

AV^CC

AVRH

T^A

V^SS+ 3.6

AV^CC

+70

V

°C

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

73

MB91307 Series

3. DC Characteristics

(V^CCI= 1.65 V to 1.95 V, V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, T^A= 0 °C to +70 °C)

Value

Typ

⎯

Parameter

Symbol Pin name

Condition

Unit Remarks

Min

Max

V^IH

See note *

⎯

0.7 × V^CC

V^CC+ 0.3

V

“H” level input

voltage

Input pins

other than *

Hysteresis

input

V^HIS

0.8 × V^CC

V^SS

⎯

V^CC+ 0.3

V

0.25 ×

V^CC

V^IL

See note *

⎯

V

“L” level input

voltage

Input pins

other than *

Hysteresis

input

V^ILS

V^SS

0.2 × V^CC

V

D16 to D31

A00 to A25

P6 to PH

“H” level output

voltage

V^CC= 3.0 V

V^OH

V^CC− 0.5

⎯

V^CC

V

I^OH= − 4.0 mA

D16 to D31

A00 to A25

P6 to PH

“L” level output

voltage

V^CC= 3.0 V

I^OL= 8.0 mA

V^OL

V^SS

0.4

Input leak

current

(Hi-Z output leak

current)

D16 to D31

A00 to A25

P8 to PH

V^CC= 3.6 V

I^LI

−5

⎯

+5

µA

kΩ

0.45 V<V^I<V^CC

V^CC= 3.6 V

V^I= 0.45 V

Pull-up resistance

R^UP

INIT

12

25

100

Pull-down

resistance

V^CC= 3.6 V

V^I= 3.3 V

R^DOWN

P82/BRQ

kΩ

(4x

multiplied)

66 MHz

operation

f^C= 16.5 MHz

V^CC= 3.3 V

V^CCI= 1.8 V

I^CC

⎯

150

⎯

mA

f^C= 16.5 MHz

V^CC= 3.3 V

Supply current

V^CC+V^CCI(

I^CCS

⎯

50

⎯

mA Sleep mode

V^CCI= 1.8 V

T^A= 25 °C

V^CC= 3.3 V

V^CCI= 1.8 V

I^CCH

150

µA Stop mode

Other than:

V^CC

Input capacitance

C^IN

V^SS

AV^CC

⎯

5

15

pF

AV^SS

* : Pins without hysteresis input pins: D16 to D31, RDY, BRQ, INIT

74

MB91307 Series

4. AC Characteristics

(1) Clock Timing Standards

(V^CCI= 1.65 V to 1.95 V, V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, T^A= 0 °C to +70 °C)

Value

name

Condi-

tion

Parameter

Clock frequency (1)

Clock cycle time

Symbol

Unit

Remarks

PLL system*¹

Min

Max

X0

X1

f^C

12.5

16.5 MHz

(self oscillation

⎯

16.5MHz,multiplied

x4,maximum internal

operation 66MHz)

X0

X1

t^C

⎯

60.6

ns

X0

X1

Self oscillation (x1/2

frequency input)

Clock frequency (2)

Clock frequency (3)

Clock cycle time

f^C

t^C

10

40

16

⎯

33

100

⎯

MHz

X0

X1

X0

X1

ns External clock

ns

P^WH

P^WL

X0

X1

Input clock pulse width

Input clock rise, fall time

t^CR

t^CF

X0

X1

8

ns

(t^CR+ t^CF)

f^CP

f^CPP

f^CPT

t^CP

0.78^*2

15.2

66

33

66

MHz CPU system

Internal operating clock frequency

Internal operating clock cycle time

MHz Peripheral system

MHz External bus system

⎯

1280^*2ns CPU system

t^CPP

t^CPT

30.3

1280^*2ns Peripheral system

1280^*2ns External bus system

15.2

*1 : When using the PLL, the clock frequency should be around 12.5 to 16.5 MHz.

*2 : The values shown represent a minimum clock frequency of 12.5 MHz input at the X0 pin, using the oscillator

circuit PLL and a gear ratio of 1/16.

75

MB91307 Series

• Clock timing measurement conditions:

tC

0.8 VCC

0.2 VCC

Output pin

C = 50 pF

PWL

PWH

tCR

tCF

• Warranted operating range

V^CC(V)

Warranted operating temperature:

(T^A=0 °C to +70 °C)

f^CPPis represented by the shaded area

1.95

1.65

fCP / fCPP

(MHz)

0

0.78

33

Internal clock

66

• External/internal clock setting range

(MHz)

f

CP

,

CPT

66

CPU, external bus systems

f

CPP

33

Peripheral system

16.5

CPU: Divided ratio for peripherals

4 : 4

2 : 2

1 : 2

Notes : • When using the PLL, the external clock input should be around 16.5 MHz.

• Set PLL oscillator stabilization time > 300 µs.

• The internal clock gear setting should be within the values shown in (1) clock timing standards.

76

MB91307 Series

(2) Clock Output Timing

(V^CCI= 1.65 V to 1.95 V, V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, T^A= 0 °C to +70 °C)

Value

name

Parameter

Symbol

Conditions

Unit Remarks

Min

Max

MCLK,

SYSCLK

Cycle time

t^CYC

t^CHCL

t^CLCL

t^CPT

⎯

ns *1

ns *2

ns *3

MCLK↑→MCLK↓

SYSCLK↑→SYSCLK↓

MCLK,

SYSCLK

⎯

1/2 × t^CYC− 3 1/2 × t^CYC+ 3

MCLK↓→MCLK↑

SYSCLK↓→SYSCLK↑

MCLK,

SYSCLK

t

CYC

t

CHCL

tCLCH

V

OH

VOH

MCLK,

SYSCLK

V

OL

*1 : t^CYCrepresents the frequency of one clock cycle including the gear period.

*2 : The values shown represent standards for × 1 gear period.

For gear period settings of 1/2, 1/4, 1/8, use the following formula replacing n with the value 1/2, 1/4, 1/8

respectively.

(1/2 × 1/n) × t^CYC− 10

*3 : The values shown represent standards for × 1 gear period.

Note : t^CPTindicates the internal operating clock time. See “ (1) Clock Timing Standards”.

77

MB91307 Series

(3) Reset and Hardware Standby Input Standards

(V^CCI= 1.65 V to 1.95 V, V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, T^A= 0 °C to +70 °C)

Value

name

Parameter

Symbol

Conditions

Unit Remarks

Min

Max

Hardware standby input time

t^HSTL

V^CCI

t^CP× 5

⎯

ns

INIT input time

(power-on)

*

⎯

t^INTL

INIT

INIT input time

(other than power-on)

t^CP× 5

ns

tRSTL, tHSTL, tINTL

HST

INIT

0.2 VCC

* : INIT input time (at power-on)

FAR, Ceralock : φ × 2¹⁵or greater recommended

Crystal

φ

: φ × 2²¹or greater recommended

: Power on → X0/X1 period × 2

Note : t^CPindicates the clock cycle time. See “ (1) Clock Timing Standards”.

78

MB91307 Series

(4) Normal Bus Access Read/Write Operation

(V^CCI= 1.65 V to 1.95 V, V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, T^A= 0 °C to +70 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min

3

Max

⎯

CS0 to CS7 setup

CS0 to CS7 hold

t^CSLCH

t^CSHCH

ns

MCLK, SYSCLK,

CS0 to CS7

⎯

3

t^CYC/2 + 6

MCLK, SYSCLK,

A23 to A00

Address setup

Address hold

t^ASCH

t^CHAX

t^AVDV

3

⎯

ns

MCLK, SYSCLK,

A23 to A00

t^CYC/2 + 6

Valid address →

valid data input time

A23 to A00,

D31 to D16

3/2 ×

t^CYC− 11

⎯

ns

*

t^CHWL

t^CHWH

⎯

6

ns

MCLK, SYSCLK,

WR0 to WR1

WR0 to WR1 delay time

WR0 to WR1 minimum pulse

width

t^WLWH

WR0 to WR1

t^CYC− 3

⎯

ns

Data setup → WRx↑

t^DSWH

t^WHDX

t^CHRL

t^CHRH

t^RLDV

t^DSRH

t^RHDX

t^RLRH

t^ASLCH

t^ASHCH

t^CYC

⎯

ns

⎯

WR0 to WR1,

D31 to D16

WRx↑ → data hold time

5

⎯

6

MCLK, SYSCLK,

RD

RD delay time

⎯

6

t^CYC− 10

⎯

RD↓ → valid data input time

Data setup → RD↑time

RD↑ → data hold time

RD minimum pulse width

AS setup

⎯

*

RD,

D31 to D16

10

0

⎯

RD

t^CYC− 3

⎯

3

⎯

MCLK, SYSCLK,

AS

AS hold

⎯

* : To extend bus time by automatic wait insertion or RDY input, add to this value (t^CYC× number of extended cycles).

Note : t^CYCindicates the cycle time. See “ (2) Clock Output Timing”.

79

MB91307 Series

t

CYC

BA1

V

OH

V

OH

V

OH

VOH

MCLK,

SYSCLK

t

ASLCH

t

ASHCH

V

OH

AS

LBA

V

OL

t

CSLCH

t

CSHCH

V

OH

CS0 to CS7

V

OL

t

ASCH

t

CHAX

V

OH

OL

V

OH

OL

A23 to A00

t

CHRL

t

CHRH

t

RLRH

RD

V

OH

V

OL

t

RHDX

t

RLDV

t

DSRH

t

AVDV

D31 to D16

V

OH

OL

V

OH

OL

t

CHWL

tCHWH

t

WLWH

V

OH

WR0 to WR1

V

OL

t

WHDX

t

DSWH

V

OH

OL

V

OH

OL

Write

D31 to D16

80

MB91307 Series

(5) Ready Input Timing

Parameter

(V^CCI= 1.65 V to 1.95 V, V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, T^A= 0 °C to +70 °C)

Value

Symbol

Pin name

Condition

Unit Remarks

Min

Max

RDY setup time →

MCLK↑, SYSCLK↑

MCLK, SYSCLK,

RDY

tRDYS

⎯

10

⎯

ns

MCLK↑, SYSCLK↑

RDY hold time

MCLK, SYSCLK,

RDY

t^RDYH

0

⎯

t

CYC

V

OH

V

OH

MCLK,

V

OL

VOL

SYSCLK

t

RDYH

t

CHASL

t

RDYS

tRDYS

tRDYH

RDY

Wait applied

V

OH

VOH

V

OL

VOL

RDY

Wait not applied

V

OH

VOH

V

OL

VOL

81

MB91307 Series

(6) Hold Timing

(V^CCI= 1.65 V to 1.95 V, V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, T^A= 0 °C to +70 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min

3

Max

13.5

t^CHBGL

t^CHBGH

ns

MCLK, SYSCLK,

BGRNT

BGRNT delay time

3

⎯

Pin floating

→ BGRNT↓time

t^XHAL

t^HAHV

t^CYC− 10

t^CYC+ 10

ns

BGRNT

BGRNT↑ → valid time

Note: After a BRQ is accepted, a minimum of 1 cycle is required before BGRNT changes.

tCYC

VOH

MCLK,

SYSCLK

BRQ

tCHBGH

tCHBGL

VOH

BGRNT

Pins

VOL

tHXAL

tHAHV

High-Z

82

MB91307 Series

(7) UART Timing

(V^CCI= 1.65 V to 1.95 V, V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, T^A= 0 °C to +70 °C)

Value

Parameter

Symbol Pin name Condition

Unit Remarks

Min

Max

SC0 to SC2

Serial clock cycle time

t^SCYC

t^SLOV

t^IVSH

t^SHIX

8 t^CPP

⎯

ns

SC0 to SC2,

SO0 to SO2

SCLK↓ → SOUT delay time

−80

100

60

80

⎯

Internal

shift lock

mode

SC0 to SC2,

SI0 to SI2

Valid SIN → SCLK↑

ns

SC0 to SC2,

SI0 to SI2

SCLK↑ → valid SIN hold time

SC0 to SC2

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

t^SLSH

4 t^CPP

⎯

ns

SC0 to SC2,

SO0 to SO2

External

shift lock

mode

SCLK↓ → SOUT delay time

Valid SIN → SCLK↑

t^SLOV

t^IVSH

t^SHIX

⎯

60

150

⎯

ns

SC0 to SC2,

SI0 to SI2

SC0 to SC2,

SI0 to SI2

SCLK↑ → valid SIN hold time

⎯

Notes: • Above ratings are for operation in CLK synchronized mode.

• t^CPPis the cycle time of the peripheral system clock.

• Internal Shift Clock Mode

tSCYC

VOH

SC0, SC1

SO0, SO1

VOL

tSLOV

VOL

VOH

VOL

tIVSH

tSHIX

VOH

VOL

VOH

VOL

SI0, SI1

• External Shift Clock Mode

SC0, SC1

tSLSH

tSHSL

VOH

VOL

tSLOV

VOH

VOL

SO0, SO1

SI0, SI1

tIVSH

tSHIX

VOH

VOL

VOH

VOL

83

MB91307 Series

(8) Timer Clock Input Timing

(V^CCI= 1.65 V to 1.95 V, V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, T^A= 0 °C to +70 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min

Max

t^TIWH

t^TIWL

Input pulse width

TIN0 to TIN2

⎯

2 t^CYCP

⎯

ns

Note: t^CYCPis the cycle time of the peripheral system clock.

TIN0 to TIN2

tTIWL

tTIWH

(9) Trigger Input Timing

(V^CCI= 1.65 V to 1.95 V, V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, T^A= 0 °C to +70 °C)

Value

Parameter

Symbol Pin name Condition

t^ATGXATG

Unit Remarks

Min

Max

A/D startup trigger input time

⎯

5 t^CYCP

⎯

ns

Note: t^CYCPis the cycle time of the peripheral system clock.

tATGX, tINP, tPTG

ATG

84

MB91307 Series

(10) DMA Controller Timing

(V^CCI= 1.65 V to 1.95 V, V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, T^A= 0 °C to +70 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min

5 t^CYC

⎯

Max

⎯

6

DREQ 0 to DREQ2

DSTP 0 to DSTP2

DREQ input pulse width

DSTP input pulse width

tDRWH

t^DSWH

t^CLDL

ns

MCLK, SYSCLK,

DACK0 to DACK2

DACK delay time

DEOP delay time

IORD delay time

IOWR delay time

ns

t^CLDH

t^CLEL

⎯

6

⎯

6

MCLK, SYSCLK,

DEOP 0 to DEOP2

⎯

t^CLEH

t^CLIRL

t^CLIRH

t^CLIWL

t^CLIWH

⎯

6

⎯

6

MCLK, SYSCLK

⎯

6

⎯

6

⎯

6

85

MB91307 Series

tCYC

BA1

BA2

VOH

MCLK,

VOL

SYSCLK

tCLDL

tCLDH

VOH

VOL

DACK0 to DACK2

DEOP0 to DEOP2

tCLEL

tCLEH

VOH

VOL

tCLIRL

tCLIRH

IORD

tCLIWL

tCLIWH

IOWR

tDRWH

VOH

DREQ0 to DREQ2

VOL

tDSWH

VOH

DSTP0 to DSTP2

VOL

86

MB91307 Series

(11) I²C Timing

(V^CCI= 1.65 V to 1.95 V, V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, T^A= 0 °C to +70 °C)

High-speed mode*⁴

Standard mode

Parameter

Symbol Condition

Unit

Min

Max

Min

Max

SCL clock frequency

f^SCL

0

100

0

400

kHz

(Repeat) “start” condition hold time

SDA ↓ → SCL ↓

t^HDSTA

4.0

⎯

0.6

⎯

µs

SCL clock “L” width

SCL clock “H” width

t^LOW

t^HIGH

4.7

4.0

⎯

1.3

0.6

⎯

µs

Repeat “start” condition setup time

SCL ↑ → SDA ↓

t^SUSTA

4.7

0

⎯

3.45*²

⎯

0.6

0

⎯

0.9*³

⎯

µs

ns

µs

R = 1.0 kΩ,

C = 50 pF*¹

Data hold time

SCL ↓ → SDA ↓ ↑

t^HDDAT

Data setup time

SDA ↓ ↑ → SCL ↑

t^SUDAT

t^SUSTO

t^BUS

250

4.0

4.7

100

0.6

1.3

“Stop” condition setup time

SCL ↑ → SDA ↑

⎯

Bus free time between “stop” and

“start” conditions

⎯

*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : The maximum t^HDDATonly has to be met if the device does not stretch the “L” width (t^LOW) of the SCL signal.

*3 : A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement

t^SUDAT≥ 250 ns must then be met.

*4 : For use at over 100 kHz, set the resource clock to at least 6 MHz.

SDA

t

BUS

t

SUDAT

t

LOW

t

HDSTA

SCL

t

HDSTA

t

HDDAT

t

HIGH

t

SUSTA

tSUSTO

87

MB91307 Series

5. A/D Converter Electrical Characteristics

(V^CCI= 1.65 V to 1.95 V, V^CC= +3.0 V to +3.6 V, V^SS= AV^SS= 0 V, T^A= 0 °C to +70 °C)

Value

Typ

10

Parameter

Symbol Pin name

Unit

Min

⎯

Max

10

Resolution

Total error

Linear error

⎯

BIT

LSB

µs

⎯

4.5

⎯

3.0

Differential linear error

Zero transition error

Full scale transition error

Conversion time

⎯

2.5

V^OT

V^FST

⎯

AN0 to AN3

− 1.5

+ 0.5

+ 4.5

AN0 to AN3 AVRH − 4.5 AVRH − 1.5 AVRH + 4.5

⎯

5.4 *¹

⎯

0.1

⎯

10

Analog port input current

Analog input voltage

Reference voltage

I^AIN

V^AIN

⎯

AN0 to AN3

AVRH

⎯

µA

AVss

⎯

AVRH

AV^CC

⎯

V

⎯

V

I^A

600

⎯

µA

Supply current

AV^CC

I^AH

I^R

⎯

10 *²

µA

⎯

600

⎯

10 *²

5

µA

Reference voltage supply current

Inter-channel variation

AVRH

I^RH

⎯

µA

AN0 to AN3

⎯

LSB

*1 : At V^CC= AV^CC= 3.0 V to 3.6 V, V^CCI= 1.65 V to 1.95 V machine clock 33 MHz.

*2 : Current in CPU stop mode with A/D converter not operating (at V^CC= AV^CC= AVRH = 3.6 V, V^CCI= 1.95 V)

• About the external impedance of the analog input and its sampling time

• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion precision.

• Analog input circuit model

R

Analog input

Comparator

C

During sampling : ON

R

C

MB91307R/306R 5.0 kΩ (Max) 15 pF (Max)

MB91V307R 8.1 kΩ (Max) 10 pF (Max)

Note : The values are reference values.

88

MB91307 Series

• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance

and minimum sampling time and either adjust the operating frequency or decrease the external impedance

so that the sampling time is longer than the minimum value.

• The relationship between external impedance and minimum sampling time

External impedance = 0 kΩ to 20 kΩ

External impedance = 0 kΩ to 100 kΩ

MB91V307R

100

20

18

16

14

12

10

8

90

80

70

60

50

40

30

20

10

0

MB91307R

MB91306R

MB91307R

MB91306R

6

4

2

0

5

10

15

20

25

30

35

0

1

2

3

4

5

6

7

8

Minimum sampling time [µs]

• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 mF to the analog input pin.

• About errors

As | AVRH | becomes smaller, values of relative errorsgrow larger.

89

MB91307 Series

Definition of A/D Converter Terms

• Resolution

Indicates the ability of the A/D converter to discriminate analog variation

• Linear error

Expresses the deviation between actual conversion characteristics and a straight line connecting the device’s

zero transition point (00 0000 0000←→00 0000 0001) and full scale transition point (11 1111 1110←→11

1111 1111)

• Differential linear error

Expresses the deviation of the logical value of input voltage required to create a variation of 1 LSB in output

code.

[Differential linear error]

[Linear Error]

3FFH

3FEH

3FDH

Actual variation

Theoretical

N − 1

N − 2

N − 1

N − 2

{1 LSB × (N − 1) + VTO}

VFST

Actual variation

(measured

value)

V^NT

(measured

value)

004H

003H

002H

001H

V(N − 1)T

(measured

value)

Actual variation

V^NT

(measured value)

Theoretical values

Actual variation

(measured value)

VTO

AVRL

AVRH

AVRL

AVRH

Analog input

[LSB]

Analog input

V^NT− {1 LSB × (N − 1) + V^OT}

Linear error in digital output N

=

1 LSB

V (^N+ ¹) ^T− V^NT

Differential linear error in digital output N =

V^FST− V^OT

−1

[LSB]

1 LSB

1 LSB =

[V]

1022

AVRH − AVRL

1 LSB” =

[V]

(theoretical value)

1024

V^OT: Voltage at which the digital output transitions from “000”^Hto “001”^H.

V^FST: Voltage at which the digital output transitions from “3FE”^Hto “3FF”^H.

V^NT: Voltage at which the digital output transitions from (N-1) to N.

90

MB91307 Series

• Total error

Expresses the difference between actual and theoretical values as error, including zero transition error, full-

scale error, and linearity error.

[Total error]

3FFH

Actual variation

1.5 LSB

3FEH

{1 LSB × (N − 1) + 0.5 LSB

3FDH

VNT

(measured

value)

004H

003H

002H

001H

Actual variation

theoretical value

0.5 LSB

AVRL

AVRH

Analog input

V^NT− {1 LSB” × (N − 1) + 0.5 LSB”}

Total error in digital output N

=

[LSB]

1 LSB”

V^OT” (theoretical value) = AVRL + 0.5 LSB” [V]

V^FST” (theoretical value) = AVRH − 1.5 LSB” [V]

V^NT: Voltage at which digital output transitions from (N-1) to N.

91

MB91307 Series

■ EXAMPLE CHARACTERISTICS

(1) Sample output voltage characteristics (T^A= +25 °C)

Sample output H voltage (V^OH) characteristics

Sample output L voltage (V^OL) characteristics

3.6

3.4

3.2

3.0

2.8

0.4

0.3

0.2

0.1

0.0

3.0

3.2

3.4

3.6

3.0

3.2

3.4

3.6

Supply voltage (V)

Supplyvoltage(V)

(2) Sample input voltage characteristics (T^A= +25 °C)

Sample input H/L level characteristics (hysteresis)

Sample input H/L level characteristics (CMOS)

3.0

2.0

V

IH

2.0

1.0

0.0

V

IH

IL

1.0

0.0

V

IL

3.0

3.2

3.4

3.6

3.0

3.2

3.4

3.6

Supply voltage (V)

Supplyvoltage(V)

(3) Sample supply current characteristics

Sample supply current (I^CC) characteristics

(T^A= +25 °C, 66 MHz)

(V^CC= 3.3 V, 66 MHz)

200

150

100

50

200

150

100

50

0

0.0

3.0

3.2

3.4

3.6

0

25

70

Supply voltage (V)

Temperature ( °C)

(Continued)

92

MB91307 Series

(Continued)

Sample sleep current (I^CCS) characteristics

(T^A= +25 °C, 33 MHz)

Sample sleep current (I^CCS) characteristics

(V^CC= 3.3 V, 33 MHz)

50

40

30

20

50

40

30

20

3.0

3.2

3.4

3.6

0

25

70

Supply voltage (V)

Temperature ( °C)

Sample A/D supply current (I^A) characteristics

Sample A/D reference current (I^R) characteristics

(T^A= +25 °C, 33 MHz)

500

400

300

200

500

400

300

200

3.0

3.2

3.4

3.6

3.0

3.2

3.4

3.6

Supply voltage (V)

(4) Port resistance characteristics

Sample pull-up resistance characteristics

Sample pull-down resistance characteristics

(T^A= +25 °C)

30

25

20

15

30

25

20

15

3.0

3.2

3.4

3.6

3.0

3.2

3.4

3.6

Supply voltage (V)

93

MB91307 Series

■ ORDERING INFORMATION

Part number

Package

Remarks

Lead-free package

For development tool use

MB91306RPFV

MB91307RPFV

120-pin, Plastic LQFP

(FPT-120P-M21)

135-pin, Ceramic PGA

(PGA-135C-A02)

MB91V307RCR

94

MB91307 Series

■ PACKAGE DIMENSION

120-pin, Plastic LQFP

(FPT-120P-M21)

Note 1) * : These dimensions do not include resin protrusion.

Resin protrusion is +0.25(.010) MAX(each side).

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

18.00±0.20(.709±.008)SQ

+0.40

16.00 –0.10

.630 ⁺^–.^.⁰⁰⁰¹⁴⁶SQ

*

90

61

91

60

0.08(.003)

Details of "A" part

1.50 –⁺0⁰.^.1²0⁰

(Mounting height)

.059 –⁺.^.0⁰0⁰4⁸

INDEX

0~8˚

"A"

120

31

0.10±0.05

(.004±.002)

(Stand off)

1

30

LEAD No.

0.145 ⁺–0⁰.^.0⁰3⁵

.006 ⁺^–.^.⁰⁰⁰⁰¹²

0.60±0.15

(.024±.006)

0.22±0.05

(.009±.002)

M

0.50(.020)

0.08(.003)

0.25(.010)

C

2002 FUJITSU LIMITED F120033S-c-4-4

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

95

MB91307 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0502


型号：	MB91306RPFV
厂家：	FUJITSU
描述：	32-Bit Microcontroller 32位微控制器微控制器
文件：	总96页 (文件大小：898K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB91306RPFV [FUJITSU]

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