MB95R203APF-G-JNE2 [FUJITSU]
8-bit Proprietary Microcontrollers; 8位微控制器专用
| 型号： | MB95R203APF-G-JNE2 |
| 厂家： | 
FUJITSU |
| 描述： | 8-bit Proprietary Microcontrollers |
| 文件： | 总56页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12630-2E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95R203A
MB95R203A
■ DESCRIPTION
The MB95R203A is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Selectable Main clock source
Main OSC clock (Up to 10 MHz, Maximum Machine clock frequency is 5 MHz)
External clock (Up to 20 MHz, Maximum Machine clock frequency is 10 MHz)
Internal main CR clock (Typ 1/8 MHz, Maximum Machine clock frequency is 8 MHz)
• Selectable Sub clock source
Sub OSC clock (32 kHz)
Sub internal CR clock (Typ : 100 kHz, Min : 50 kHz, Max : 200 kHz)
(Continued)
Copyright©2010-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.3
MB95R203A
(Continued)
• Timer
• 8/16-bit compound timer
• Time-base timer
• Watch prescaler
• UART/SIO
• Offers clock asynchronous (UART) or clock synchronous (SIO) serial data transfer
• Full duplex double buffer
• I2C
• Built-in wake-up function
• External interrupt
• Interrupt by the edge detection (Select rising edge/falling edge/both edges)
• Can be used to recover from low-power consumption modes (also called standby mode)
• 8/10-bit A/D converter
• 8-bit or 10-bit resolutions can be selected
• Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
• I/O port : 16
• General-purpose I/O ports :
CMOS I/O : 12, N-ch open drain : 4
• On-chip debug
• 1 wire serial control
• Support serial writing. (Asynchronous mode)
• Hardware/Software watch dog timer
• Built-in Hardware watchdog timer
• Low voltage detection circuit (LVD)
• Low voltage detection reset circuit
• Low voltage detection interrupt circuit
• Circuit to monitor FRAM power supply
• Clock supervisor counter (CSV)
• Built-in Clock supervise function
• Programmable input voltage levels of port
• CMOS input level / hysteresis input level
• FRAM
• Non-volatile memory
• 8 Kbytes of FRAM integrated on-chip
• FRAM memory security function
• Protects the content of FRAM memory
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MB95R203A
■ PRODUCT OVERVIEW
Part number
Parameter
MB95R203A
ROM (FRAM) capacity
RAM capacity
8 Kbytes
496 bytes
Yes
Reset output
Low voltage detection reset
Yes
Number of basic instructions
: 136 instructions
Instruction bit length
Instruction length
Data bit length
: 8 bits
: 1 to 3 bytes
: 1, 8, and 16 bits
CPU function
Minimum instruction execution time : 100 ns (at machine clock 10 MHz)
Interrupt processing time
: 0.9 μs (at machine clock 10 MHz)
General-purpose I/O ports : 16
CMOS I/O : 12, N-ch open drain : 4
Port
Time-base timer
Interrupt cycle : 0.256 ms to 8.3 s (at external 4 MHz)
Reset generation cycle
Main clock at 10 MHz : 105 ms (Min)
Sub clock CR can be used as the Watch dog source clock.
Hardware/software
Watchdog timer
Wild registers
UART/SIO
It can be used to replace three bytes of data.
Able to transfer data using UART/SIO
Variable data length (5/6/7/8-bit) , built-in baud rate generator
Transfer rate (2400 bps to 125000 bps at 10 MHz) , full-duplex transfers with
built-in double buffers
NRZ type transfer format, error detection function
LSB-first or MSB-first can be selected
Capable of clock synchronous (SIO) or clock asynchronous (UART) serial data
transfer
Transmit and receive master/slave
Bus function, arbitration function, transfer direction detection function
Start condition repeated generation and detection functions
Built-in timeout detection function
I2C bus
6 ch
8/10-bit A/D converter
8-bit or 10-bit resolution can be selected
2 ch
Can be configured as a 2 ch × 8-bit timer or 1 ch × 16-bit timer
Built-in timer function, PWC function, PWM function and capture function
Count clock : available from internal clocks (7 types) or external clocks
With square wave output
8/16-bit compound timer
6 ch
External interrupt
Interrupt by edge detection (Select rising edge/falling edge/both edges)
Can be used to recover from standby modes
Selectable from 4 kinds of low voltage detection levels
Usable as a release function from standby mode
Low voltage interrupt
(Continued)
DS07-12630-2E
3
MB95R203A
(Continued)
Part number
MB95R203A
Parameter
1 wire serial control
Support serial writing. (Asynchronous mode)
On-chip debug
Watch prescaler
Eight different time intervals can be selected.
Non-volatile memory
Number of read/write cycles : 1015 times
Data retention characteristics : 10 years ( + 55 °C)
Read security function
FRAM
Function to monitor FRAM power supply
Standby Mode
Package
Sleep mode, Stop mode, Watch mode, time-base timer mode
DIP-24, SOP-20
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MB95R203A
■ PIN ASSIGNMENT
(TOP VIEW)
X0
NC
X1
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
P12/EC0/DBG
NC
P07/INT07
P06/INT06/TO01
P05/INT05/AN05/TO00/HCLK2
P04/INT04/AN04/UI/HCLK1/EC0
P03/INT03/AN03/UO
P02/INT02/AN02/UCK
P01/AN01
24pin
(DIP-24)
Vss
X1A/PG2
X0A/PG1
Vcc
SCL/P65
RST/PF2
TO10/P62
NC
10
11
12
P00/AN00
NC
P64/EC1/SDA
TO11/P63
*The number of usable pins is 20.
(DIP-24P-M07)
(TOP VIEW)
X0
X1
Vss
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
P12/EC0/DBG
P07/INT07
P06/INT06/TO01
P05/INT05/AN05/TO00/HCLK2
P04/INT04/AN04/UI/HCLK1/EC0
P03/INT03/AN03/UO
P02/INT02/AN02/UCK
P01/AN01
20pin
(SOP-20)
X1A/PG2
X0A/PG1
Vcc
SCL/P65
RST/PF2
TO10/P62
TO11/P63
P00/AN00
P64/EC1/SDA
10
(FPT-20P-M09)
DS07-12630-2E
5
MB95R203A
■ PIN DESCRIPTION
Pin no.
I/O
Circuit
type*
Pin name
Function
Main clock input oscillation pin
DIP24 SOP20
1
3
4
1
2
3
X0
X1
B
B
Main clock input/output oscillation pin
Power supply pin (GND)
Vss
⎯
General-purpose I/O port
This pin is also used as Sub clock input/output oscillation pin.
5
4
PG2/X1A
C
General-purpose I/O port
This pin is also used as Sub clock input oscillation pin.
6
7
8
5
6
7
PG1/X0A
Vcc
C
⎯
I
Power supply pin
General-purpose I/O port
P65/SCL
This pin is also used as I2C clock I/O.
General-purpose I/O port
This pin is also used as reset pin
9
8
9
PF2/RST
A
D
General-purpose I/O port
High current port
10
P62/TO10
This pin is also used as 8/16-bit compound timer ch.1 output.
General-purpose I/O port
12
13
10
11
P63/TO11
D
I
High current port
This pin is also used as 8/16-bit compound timer ch.1 output.
General-purpose I/O port
P64/SDA/EC1
This pin is also used as I2C data I/O.
This pin is also used as 8/16-bit compound timer ch.1 clock input.
General-purpose I/O port
This pin is also used as A/D converter analog input.
15
16
12
13
P00/AN00
P01/AN01
E
E
General-purpose I/O port
This pin is also used as A/D converter analog input.
General-purpose I/O port
P02/INT02/AN02/
UCK
This pin is also used as external interrupt input.
This pin is also used as A/D converter analog input.
This pin is also used as UART/SIO clock I/O.
17
18
14
15
E
E
General-purpose I/O port
P03/INT03/AN03/
UO
This pin is also used as external interrupt input.
This pin is also used as A/D converter analog input.
This pin is also used as UART/SIO data output.
General-purpose I/O port
This pin is also used as external interrupt input.
This pin is also used as A/D converter analog input.
This pin is also used as UART/SIO data input.
This pin is also used as 8/16-bit compound timer ch.0 clock input.
P04/INT04/AN04/
UI/HCLK1/EC0
19
16
F
(Continued)
6
DS07-12630-2E
MB95R203A
(Continued)
Pin no.
I/O
Circuit
type*
Pin name
Function
DIP24 SOP20
General-purpose I/O port
High current port
P05/INT05/AN05/
TO00/HCLK2
This pin is also used as external interrupt input.
20
17
E
This pin is also used as A/D converter analog input.
The pins are also used as 8/16-bit compound timer ch.0 output.
This pin is also used as the external clock input.
General-purpose I/O port
High current port
This pin is also used as external interrupt input.
This pin is also used as 8/16-bit compound timer ch.0 output.
21
22
24
18
19
20
⎯
P06/INT06/TO01
P07/INT07
P12/EC0/DBG
NC
G
G
H
General-purpose I/O port
This pin is also used as external interrupt input.
General-purpose I/O port
This pin is also used as DBG input pin.
This pin is also used as 8/16-bit compound timer ch.0 clock
input.
2, 11,
14,23
⎯
Internal connect pin. Be sure this pin is left open.
* : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
DS07-12630-2E
7
MB95R203A
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• N-ch open drain output
• Hysteresis input
• Reset output
Reset input / Hysteresis input
Reset output / Digital output
N-ch
B
• Oscillation circuit
• High-speed side
Feedback resistance : approx. 1 MΩ
• Hysteresis input
Clock input
X1
X0
Standby control
C
• Oscillation circuit
• Low-speed side
Feedback resistance : approx. 10 MΩ
• CMOS output
• Hysteresis input
Port select
R
Pull-up control
P-ch
P-ch
Digital output
Digital output
• With pull-up control
N-ch
Standby control
Hysteresis input
Clock input
X1A
X0A
Standby control / Port select
Clock input
Port select
R
Pull-up control
Digital
output
P-ch
Digital output
Digital output
N-ch
Standby control
Hysteresis input
D
• CMOS output
• Hysteresis input
P-ch
Digital output
Digital output
N-ch
Standby control
Hysteresis input
(Continued)
8
DS07-12630-2E
MB95R203A
(Continued)
Type
Circuit
Remarks
E
• CMOS output
Pull-up control
• Hysteresis input
R
• With pull-up control
P-ch
Digital output
Digital output
P-ch
N-ch
Analog input
A/D control
Standby control
Hysteresis input
F
• CMOS output
Pull-up control
• Hysteresis input
• CMOS input
• With pull-up control
R
P-ch
N-ch
Digital output
Digital output
P-ch
Analog input
A/D control
Standby control
Hysteresis input
CMOS input
G
• CMOS output
• Hysteresis input
• With pull-up control
Pull-up control
R
P-ch
Digital output
Digital output
P-ch
N-ch
Standby control
Hysteresis input
H
I
• N-ch open drain output
• Hysteresis input
Hysteresis input
Digital output
N-ch
• N-ch open drain output
• CMOS input
• Hysteresis input
Digital output
N-ch
CMOS input
Hysteresis input
Standbycontrol
DS07-12630-2E
9
MB95R203A
■ NOTES ON DEVICE HANDLING
• Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output
pinsotherthanmedium-andhigh-withstandvoltagepinsorifhigherthantheratingvoltageisappliedbetween
VCC pin and VSS pin.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
• Stable Supply Voltage
Supply voltage should be stabilized.
A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating
range of the Vcc power-supply voltage.
For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range
(50 Hz / 60 Hz) not to exceed 10% of the standard Vcc value and suppress the voltage variation so that the
transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power
supply is switched.
• Precautions for Use of External Clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-
up from sub clock mode or stop mode.
• Do not use a sample used in program development as mass-produced product.
10
DS07-12630-2E
MB95R203A
■ PIN CONNECTION
• Treatment of Unused Input Pin
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent
damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any
unused input/output pins may be set to output mode and left open, or set to input mode and treated the same
as unused input pins. If there is unused output pin, make it to open.
• Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power
supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of
strobe signals caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC and VSS
near this device.
• DBG Pin
Connect the DBG pin directly to external Pull-up.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as
to minimize the distance from the DBG pin to VCC or VSS pins.
The DBG pin should not stay at “L” level after power-on until the reset output is released.
• RST Pin
Connect the RST pin directly to Pull-up.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as
to minimize the distance from the RST pin to VCC or VSS pins.
The RST/PF2 pin functions as the reset input/output pin after power-on. In addition, the reset output can be
enabled by the RSTOE bit of the SYSC register, and the reset input function or the general purpose I/O
function can be selected by the RSTEN bit of the SYSC register.
• Example of DBG / RST connection diagram
R
DBG
R
RST
Pull-up resistor recommended
resistance
For DBG pin : R = 4.7 kΩ
For RST pin : R = 10 kΩ
DS07-12630-2E
11
MB95R203A
■ NOTES ON ON-CHIP DEBUG
• Although the [Upload Flash Memory] button on SOFTUNETM* Workbench is enabled, clicking it does not start
the actual processing.
• When you click on the [Erase Flash Memory] button on SOFTUNE Workbench, data is overwritten into the
FRAM area, as shown below.
Address
Data to be overwritten
F554H
55H
A0H
FAAAH
FFBCH
Indeterminate
Indeterminate
FFH
FFBDH
Entire FRAM except the above
• When you click on the [Erase Flash Memory] and the [Target load] button on SOFTUNE Workbench, data in
the I/O area described below is undefined.
Address
0070H
Data to be overwritten
Indeterminate
0071H
Indeterminate
• Be very careful not to apply voltages to the pins PF2/RST in excess of the absolute maximum ratings.
Especially when handling devices in the environment compatible to the package, such as MB95200H/
210H and so on, the voltage may be erroneously applied to the pins PF2/RST in excess of the maximum
rating and it may cause thermal breakdown of the device.
* : SOFTUNE is a trademark of Fujitsu Semiconductor Limited, Japan.
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MB95R203A
■ BLOCK DIAGRAM
F2MC-8FX CPU
PF2*1/RST*2
Reset
LVD
X1
X0
FRAM (8 Kbytes)
with security
Oscillator
circuit
CR
Oscillator
PG2/X1A*2
PG1/X0A*2
RAM (496 bytes)
Clock control
(P05*3/TO00)
(P06*3/TO01)
8/16-bit
compound timer (0)
P12*1/DBG
On-chip debug
P12/EC0(P04/EC0)
Wild register
P62*3/TO10
P63*3/TO11
(P64/EC1)
8/16-bit
compound timer (1)
External interrupt
P02/INT02 to P07/INT07
P65*1/SCL*1
P64*1/SDA*1
I2C
8/10-bit A/D converter
(P00/AN00 to P05/AN05)
(P02/UCK)
(P04/UI)
UART/SIO
Port
(P03/UO)
Port
VCC
VSS
*1 : P12, P64, P65 and PF2 are N-ch open drain.
*2 : Software option
*3 : P05, P06, P62 and P63 are high current ports.
DS07-12630-2E
13
MB95R203A
■ CPU CORE
Memory space
Memory space of the MB95R203A is 64 Kbytes and consists of I/O area, data area, and program area. The
memory space includes special-purpose areas such as the general-purpose registers and vector table.
Memory map of the MB95R203A shown below.
• Memory Map
MB95R203A
0000H
I/O
0080H
0090H
-
RAM 496 Byte
0100H
Register
0200H
0280H
-
0F80H
Extension I/O
1000H
-
E000H
FRAM 8 KB
FFFFH
14
DS07-12630-2E
MB95R203A
■ I/O MAP
Register
Address
Register name
R/W Initial value
abbreviation
PDR0
DDR0
PDR1
DDR1
⎯
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
Port 0 data register
Port 0 direction register
R/W
R/W
R/W
R/W
⎯
00000000B
00000000B
00000000B
00000000B
⎯
Port 1 data register
Port 1 direction register
(Disabled)
WATR
⎯
Oscillation stabilization wait time setting register
(Disabled)
R/W
⎯
11111111B
⎯
SYCC
STBC
RSRR
TBTC
WPCR
WDTC
SYCC2
System clock control register
Standby control register
Reset source register
R/W XXXXXX11B
R/W
R
00000XXXB
XXXXXXXXB
00000000B
00000000B
00000000B
XX100011B
Time-base timer control register
Watch timer control register
Watchdog timer control register
System clock control register 2
R/W
R/W
R/W
R/W
000EH
to
0015H
⎯
(Disabled)
⎯
⎯
0016H
0017H
PDR6
DDR6
Port 6 data register
R/W
R/W
00000000B
00000000B
Port 6 direction register
0018H
to
0027H
⎯
(Disabled)
⎯
⎯
0028H
0029H
002AH
002BH
002CH
PDRF
DDRF
PDRG
DDRG
PUL0
Port F data register
Port F direction register
Port G data register
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
Port G direction register
Port 0 pull-up register
002DH
to
0034H
⎯
(Disabled)
⎯
⎯
0035H
0036H
0037H
0038H
0039H
PULG
Port G pull-up register
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
T01CR1
T00CR1
T11CR1
T10CR1
8/16-bit compound timer 01 control status register 1 ch.0 R/W
8/16-bit compound timer 00 control status register 1 ch.0 R/W
8/16-bit compound timer 11 control status register 1 ch.1 R/W
8/16-bit compound timer 10 control status register 1 ch.1 R/W
(Continued)
DS07-12630-2E
15
MB95R203A
Register
Address
Register name
R/W Initial value
abbreviation
003AH
to
0046H
⎯
(Disabled)
⎯
⎯
0047H
0048H
0049H
004AH
004BH
LVDCR
⎯
Low voltage detection interrupt control register
(Disabled)
R/W
⎯
00000000B
⎯
EIC10
EIC20
EIC30
External interrupt circuit control register ch.2/ch.3
External interrupt circuit control register ch.4/ch.5
External interrupt circuit control register ch.6/ch.7
R/W
R/W
R/W
00000000B
00000000B
00000000B
004CH
to
0055H
⎯
(Disabled)
⎯
⎯
0056H
0057H
0058H
0059H
005AH
SMC10
SMC20
SSR0
UART/SIO serial mode control register 1
UART/SIO serial mode control register 2
UART/SIO serial status and data register
UART/SIO serial output data register
UART/SIO serial input data register
R/W
R/W
R/W
R/W
R/W
00000000B
00100000B
00000001B
00000000B
00000000B
TDR0
TDR0
005BH
to
005FH
⎯
(Disabled)
⎯
⎯
0060H
0061H
0062H
0063H
0064H
0065H
0066H
0067H
0068H
0069H
006AH
006BH
006CH
006DH
006EH
006FH
0070H
0071H
IBCR00
IBCR10
IBSR0
IDDR0
IAAR0
ICCR0
FSCR
FRAC
FABH
FABL
I2C bus control register 0
I2C bus control register 1
I2C bus status register
I2C data register
I2C address register
I2C clock control register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
11111111B
11111111B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
(Continued)
FRAM status/control register
FRAM register access control register
FRAM write permit start address register (H)
FRAM write permit start address register (L)
FRAM write permit area size register (H)
FRAM write permit area size register (L)
8/10-bit A/D converter control register 1
8/10-bit A/D converter control register 2
8/10-bit A/D converter data register (upper byte)
8/10-bit A/D converter data register (lower byte)
FRAM violation address register (H)
FRAM violation address register (L)
FASH
FASL
ADC1
ADC2
ADDH
ADDL
FVAH
FVAL
R
16
DS07-12630-2E
MB95R203A
Register
abbreviation
Address
Register name
R/W Initial value
0072H
to
0075H
⎯
(Disabled)
⎯
⎯
0076H
0077H
WREN
WROR
Wild register address compare enable register
Wild register data test setting register
R/W
R/W
00000000B
00000000B
Register bank pointer (RP) ,
Mirror of direct bank pointer (DP)
0078H
⎯
⎯
⎯
0079H
007AH
007BH
007CH
007DH
007EH
007FH
0F80H
0F81H
0F82H
0F83H
0F84H
0F85H
0F86H
0F87H
0F88H
ILR0
ILR1
Interrupt level setting register 0
Interrupt level setting register 1
R/W
R/W
R/W
R/W
R/W
R/W
⎯
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
⎯
ILR2
Interrupt level setting register 2
ILR3
Interrupt level setting register 3
ILR4
Interrupt level setting register 4
ILR5
Interrupt level setting register 5
⎯
(Disabled)
WRARH0
WRARL0
WRDR0
WRARH1
WRARL1
WRDR1
WRARH2
WRARL2
WRDR2
Wild register address setting register (upper byte) ch.0
Wild register address setting register (lower byte) ch.0
Wild register data setting register ch.0
Wild register address setting register (upper byte) ch.1
Wild register address setting register (lower byte) ch.1
Wild register data setting register ch.1
Wild register address setting register (upper byte) ch.2
Wild register address setting register (lower byte) ch.2
Wild register data setting register ch.2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
0F89H
to
0F91H
⎯
(Disabled)
⎯
⎯
0F92H
0F93H
0F94H
0F95H
T01CR0
T00CR0
T01DR
T00DR
8/16-bit compound timer 01 control status register 0 ch.0 R/W
8/16-bit compound timer 00 control status register 0 ch.0 R/W
00000000B
00000000B
00000000B
00000000B
8/16-bit compound timer 01 data register ch.0
8/16-bit compound timer 00 data register ch.0
R/W
R/W
8/16-bit compound timer 00/01 timer mode control
register ch.0
0F96H
TMCR0
R/W
00000000B
0F97H
0F98H
T11CR0
T10CR0
8/16-bit compound timer 11 control status register 0 ch.1 R/W
8/16-bit compound timer 10 control status register 0 ch.1 R/W
00000000B
00000000B
(Continued)
DS07-12630-2E
17
MB95R203A
(Continued)
Register
abbreviation
Address
Register name
R/W Initial value
0F99H
0F9AH
T11DR
T10DR
8/16-bit compound timer 11 data register ch.1
8/16-bit compound timer 10 data register ch.1
R/W
R/W
00000000B
00000000B
8/16-bit compound timer 10/11 timer mode control
register ch.1
0F9BH
TMCR1
R/W
00000000B
0F9CH
to
0FBDH
⎯
(Disabled)
⎯
⎯
0FBEH
0FBFH
PSSR0
BRSR0
UART/SIO prescaler select register
UART/SIO baud rate setting register
R/W
R/W
00000000B
00000000B
0FC0H
to
0FC2H
⎯
AIDRL
⎯
(Disabled)
A/D input disable register lower
(Disabled)
⎯
R/W
⎯
⎯
00000000B
⎯
0FC3H
0FC4H
to
0FE3H
0FE4H
0FE5H
0FE6H
0FE7H
0FE8H
0FE9H
0FEAH
0FEBH
0FECH
0FEDH
0FEEH
CRTH
CRTL
LVDCR2
⎯
CR-trimming register upper
CR-trimming register lower
Low voltage detection control register
(Disabled)
R/W 1XXXXXXXB
R/W
R/W
⎯
000XXXXXB
00000010B
⎯
SYSC
CMCR
CMDR
WDTH
WDTL
⎯
System control register
Clock monitor control register
Clock monitor data register
Watchdog ID register upper
Watchdog ID register lower
(Disabled)
R/W
R/W
R/W
11000-11B
--000000B
00000000B
R/W XXXXXXXXB
R/W XXXXXXXXB
⎯
⎯
ILSR
Input level select register
R/W
--00-0--B
0FEFH
to
0FFFH
⎯
(Disabled)
⎯
⎯
• R/W access symbols
R/W : Readable / Writable
R
W
: Read only
: Write only
• Initial value symbols
0
1
X
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is undefined.
Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
18
DS07-12630-2E
MB95R203A
■ INTERRUPT SOURCE TABLE
Vector table
address
Priority order of
interrupt sources
Interrupt
request
number
Bit name of
interrupt level
setting register
Interrupt source
of the same level
Upper
Lower
(occurringsimultaneously)
External interrupt ch.4
External interrupt ch.5
External interrupt ch.2
External interrupt ch.6
External interrupt ch.3
External interrupt ch.7
UART/SIO (transmit)
UART/SIO (receive)
IRQ00
IRQ01
FFFAH
FFF8H
FFFBH
FFF9H
L00 [1 : 0]
L01 [1 : 0]
High
IRQ02
IRQ03
IRQ04
FFF6H
FFF4H
FFF2H
FFF7H
FFF5H
FFF3H
L02 [1 : 0]
L03 [1 : 0]
L04 [1 : 0]
8/16-bit compound timer
ch.0 (Lower)
IRQ05
IRQ06
FFF0H
FFEEH
FFF1H
FFEFH
L05 [1 : 0]
L06 [1 : 0]
8/16-bit compound timer
ch.0 (Upper)
⎯
IRQ07
RQ08
IRQ09
IRQ10
IRQ11
IRQ12
IRQ13
FFECH
FFEAH
FFE8H
FFE6H
FFE4H
FFE2H
FFE0H
FFEDH
FFEBH
FFE9H
FFE7H
FFE5H
FFE3H
FFE1H
L07 [1 : 0]
L08 [1 : 0]
L09 [1 : 0]
L10 [1 : 0]
L11 [1 : 0]
L12 [1 : 0]
L13 [1 : 0]
⎯
FRAM (UDEF, PROT)
⎯
⎯
⎯
⎯
8/16-bit compound timer
ch.1 (Upper)
IRQ14
IRQ15
FFDEH
FFDCH
FFDFH
FFDDH
L14 [1 : 0]
L15 [1 : 0]
⎯
I2C complete/error
I2C stop/AL/wakeup
IRQ16
IRQ17
FFDAH
FFD8H
FFDBH
FFD9H
L16 [1 : 0]
L17 [1 : 0]
Low voltage detection
interrupt
8/10-bit A/D converter
Time-base timer
Watch prescaler
⎯
IRQ18
IRQ19
IRQ20
IRQ21
FFD6H
FFD4H
FFD2H
FFD0H
FFD7H
FFD5H
FFD3H
FFD1H
L18 [1 : 0]
L19 [1 : 0]
L20 [1 : 0]
L21 [1 : 0]
8/16-bit compound timer
ch.1 (Lower)
IRQ22
IRQ23
FFCEH
FFCCH
FFCFH
FFCDH
L22 [1 : 0]
L23 [1 : 0]
Low
FRAM (AREA)
DS07-12630-2E
19
MB95R203A
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Max
Parameter
Symbol
Unit
Remarks
Min
Power supply voltage*1
Input voltage*1
Output voltage*1
Vcc
VI
Vss − 0.3 Vss + 4.0
Vss − 0.3 Vss + 4.0
Vss − 0.3 Vss + 4.0
V
V
V
*2
*2
VO
IOL1
IOL2
15
Other than P05, P06, P62 and P63
P05, P06, P62 and P63
“L” level maximum output
current
⎯
mA
15
Other than P05, P06, P62 and P63
Average output current =
operating current × operating ratio
(1pin)
IOLAV1
4
“L” level average current
⎯
mA
mA
P05, P06, P62 and P63
Average output current =
operating current × operating ratio
(1pin)
IOLAV2
12
“L” level total maximum output
current
ΣIOL
⎯
⎯
100
50
Total average output current =
“L” level total average output
current
ΣIOLAV
mA operating current × operating ratio
(Total of pins)
IOH1
IOH2
−15
−15
Other than P05, P06, P62 and P63
“H” level maximum output
current
⎯
mA
P05, P06, P62 and P63
Other than P05, P06, P62 and P63
Average output current =
IOHAV1
−4
−8
operating current × operating ratio
(1pin)
“H” level average current
⎯
mA
P05, P06, P62 and P63
Average output current =
operating current × operating ratio
(1pin)
IOHAV2
“H” level total maximum output
current
ΣIOH
⎯
⎯
−100
−50
mA
Total average output current =
mA operating current × operating ratio
(Total of pins)
“H” level total average output
current
ΣIOHAV
Power consumption
Operating temperature
Storage temperature
Pd
TA
⎯
320
mW
°C
−40
−40
+ 85
+ 85
Tstg
°C
*1 : The parameter is based on VSS = 0.0 V.
*2 : VI and Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
20
DS07-12630-2E
MB95R203A
2. Recommended Operating Conditions
(VSS = 0.0 V)
Value
Parameter
Symbol
Vcc
Unit
Remarks
Min
1.8*
2.7
2.7
−40
+5
Max
3.6
In normal operating
Power supply voltage
Operating temperature
3.6
V
In A/D converter operating
On-chip debug mode
3.6
+85
+35
°C
°C
Other than on-chip debug mode
On-chip debug mode
TA
* : The normal operation is performed from 1.8 V to the low voltage detection of the FRAM power supply monitor,
or from the release voltage of the FRAM power supply monitor to 1.8 V. Reset is generated during the period
that the low voltage detection reset has been detected. As for the low voltage detection, see “(8) Low Voltage
Detection” in “4. AC Characteristics”.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
onthedatasheet.Usersconsideringapplicationoutsidethelistedconditionsareadvisedtocontact
their representatives beforehand.
DS07-12630-2E
21
MB95R203A
3. DC Characteristics
(Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol Pin name
Condition
Unit
Remarks
Min
Typ
Max
When CMOS input
level (Hysteresis
input) is selected
VIH1
P04
*1
0.7 VCC
⎯
VCC + 0.3
V
When CMOS input
level (Hysteresis
input) is selected
VIH2
P64, P65
*1
*1
0.7 VCC
0.8 VCC
⎯
⎯
VCC + 0.3
VCC + 0.3
V
V
“H” level
input voltage
P00 to P07,
P12,
P62, P63,
PG1, PG2
VIHS1
Hysteresis input
VIHS2
VIHM
P64, P65
PF2
*1
0.8 VCC
0.8 VCC
⎯
⎯
VCC + 0.3
VCC + 0.3
V
V
Hysteresis input
Hysteresis input
⎯
When CMOS input
level (Hysteresis
input) is selected
P04, P64,
P65
VIL
*1
VSS − 0.3
⎯
0.3 VCC
V
“L” level
input voltage
P00 to P07,
P12,
P62 to P65,
PG1, PG2
VILS
VILM
VD
*1
⎯
⎯
VSS − 0.3
VSS − 0.3
VSS − 0.3
⎯
⎯
⎯
0.2 VCC
0.2 VCC
V
V
V
Hysteresis input
Hysteresis input
PF2
Open-drain
output
application
voltage
P12, P64,
P65, PF2
VCC + 0.3
Output pins
other than
P05, P06,
P62 to P65,
PF2, P12
VOH1
IOH = −4.0 mA
2.4
⎯
⎯
V
“H” level
output
voltage
P05, P06,
P62, P63
VOH2
VOL1
VOL2
IOH = −8.0 mA
IOL = 4.0 mA
IOL = 12.0 mA
2.4
⎯
⎯
⎯
⎯
⎯
V
V
V
Output pins
other than
P05, P06,
P62, P63
0.4
0.4
“L” level
output
voltage
P05, P06,
P62, P63
⎯
(Continued)
22
DS07-12630-2E
MB95R203A
(Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol
Pin name
Condition
Unit
Remarks
Min
Typ Max
Input leak
current (Hi-Z
output leak
current)
Other than
ports
P64, P65
When pull-up
ILI
0.0 V < VI < VCC
−5
⎯
+ 5
μA resistance is
disabled
Open-drain
output leak
current
0.0 V < VI <
ILIOD
P64, P65
−4
⎯
+ 10 μA
VCC
When pull-up
Pull-up
resistance
P00 to P07,
PG1, PG2
RPULL
VI = 0.0 V
f = 1 MHz
16.5
33
80
kΩ resistance is
enabled
Input
capacitance
Other than
Vcc, Vss
CIN
⎯
⎯
5
15
pF
FCH = 20 MHz,
FMP = 10 MHz
Main clock mode
(divided by 2)
2.3
3.1
mA
ICC
At A/D
mA
⎯
4.5
1.1
6
conversion
FCH = 20 MHz,
FMP = 10 MHz
Main sleep mode
(divided by 2)
TA = +25 °C
ICCS*3
⎯
1.7
mA
μA
μA
FCL = 32 kHz,
FMPL = 16 kHz
Sub clock mode
(divided by 2)
TA = +25 °C
Vcc
(External
clock
ICCL
⎯
52
280
operation)
Power supply
current*2
FCL = 32 kHz,
FMPL = 16 kHz
Sub sleep mode
(divided by 2)
TA = +25 °C
ICCLS*3
⎯
⎯
15
15
260
240
FCL = 32 kHz,
Watch mode
Main stop mode
TA = +25 °C
ICCT*3
μA
FCRH = 1 MHz,
FMP = 1 MHz
ICCMCR
⎯
⎯
0.55
62
⎯
mA
Main CR clock mode
Vcc
Sub CR clock mode
(divided by 2)
ICCSCR
320
μA
TA = +25 °C
(Continued)
DS07-12630-2E
23
MB95R203A
(Continued)
(Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol Pin name
Condition
Unit
Remarks
Min
Typ
Max
FCH = 10 MHz,
Time-base timer
mode
Vcc
(External
clock
ICCTS*3
⎯
0.5
0.9
mA
μA
μA
TA = +25 °C
operation)
Sub stop mode
TA = +25 °C
ICCH*3
⎯
⎯
11
5
110
10
Consumption
current using a low
voltage interrupt
circuit only
ILVD1
Current
consumption using
a low voltage
detection reset
circuit and an
FRAM power
supply monitor
circuit only
Power supply
current*2
ILVD2
⎯
25
50
μA
VCC
Current
consumption of
internal main CR
oscillator
ICRH
⎯
⎯
70
9
100
20
μA
μA
At oscillating
100 kHz current
consumption of
internal sub CR
oscillator
ICRL
*1 : P04, P64, P65 can switch the input level to either the “CMOS input level” or “hysteresis input level”.
The switching of the input level can be set by the input level selection register (ILSR) .
*2 : • The power-supply current is determined by the external clock. when Internal CR are selected, the power-
supply current will be a value of adding current consumption of internal CR oscillator (ICRH, ICRL) to the
specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit are
always enabled, and current consumption therefore increases accordingly.
• Refer to “(1) Clock Timing” in “4. AC Characteristics” for FCH and FCL.
• Refer to “(2) Source Clock/Machine Clock” in “4. AC Characteristics” for FMP and FMPL.
*3 : When a low voltage detection circuit stop bit (LVDCR2: LVDSTP set) is not set to “1”, the power supply
current will be the sum of the current consumption value for a low voltage detection circuit (ILVD2) and the
specified value.
24
DS07-12630-2E
MB95R203A
4. AC Characteristics
(1) Clock Timing
(Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C)
Value
Sym-
Parameter
Condi-
tion
Pin name
Unit
Remarks
bol
Min
Typ
Max
When the main
oscillation circuit is used
X0, X1
1
⎯
10
MHz
FCH
X0, X1,
HCLK1,
HCLK2
When the main external
clock is used
1
⎯
20
MHz
0.96
1
1.04
When the main internal
FCRH
⎯
MHz CR clock is used
( + 5 °C ≤ TA ≤ + 35 °C)
7.2
(TBD)
8.8
(TBD)
Clock frequency
⎯
When the sub oscillation
circuit is used
⎯
⎯
32.768
32.768
100
⎯
⎯
MHz
kHz
kHz
ns
FCL
X0A, X1A
When the sub external
clock is used
When the sub internal
CR clock is used
FCRL
⎯
50
200
1000
When the main
oscillation circuit is used
X0, X1
100
⎯
⎯
tHCYL
X0, X1,
HCLK1,
HCLK2
Clock cycle time
When the main external
clock is used
50
⎯
20
⎯
30.5
⎯
1000
⎯
ns
tLCYL X0A, X1A
μs When using sub clock
tWH1
X0,
HCLK1,
HCLK2
When the external clock
is used, the duty ratio
should range between
40% and 60%
⎯
ns
μs
ns
tWL1
Input clock pulse
width
tWH2
tWL2
tCR
X0A
⎯
⎯
15.2
⎯
X0, X0A,
HCLK1,
HCLK2
Input clock rise
time and fall time
When the external clock
is used
⎯
5
tCF
When the main internal
CR clock is used
tCRHWK
⎯
⎯
⎯
⎯
⎯
⎯
10
50
μs
μs
Internal CR
oscillation start time
When the sub internal
CR clock is used
tCRLWK
DS07-12630-2E
25
MB95R203A
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0, HCLK1, HCLK2
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When using a crystal or
Ceramic oscillator
When using external clock
X0
X1
X0
X1
Open
FCH
FCH
t
LCYL
t
WH2
tWL2
t
CR
tCF
0.8 VCC 0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of sub clock input port external connection
When using a crystal
or
Ceramic oscillator
When using external clock
X0A
X1A
FCL
X0A
X1A
Open
FCL
26
DS07-12630-2E
MB95R203A
(2) Source Clock/Machine Clock
Pin
(Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C)
Value
Typ
Parameter
Symbol
Unit
Remarks
name
Min
Max
When using main external clock
100
⎯
⎯
2000
ns Min : FCH = 20 MHz, divided by 2
Max : FCH = 1 MHz, divided by 2
When using main CR oscillation clock
ns Min : FCRH = 8 MHz
Source clock
cycle time*1
(Clock before
division)
125
1000
tSCLK
⎯
Max : FCRH = 1 MHz
When using sub oscillation clock
μs
⎯
⎯
61
20
⎯
⎯
FCL = 32.768 kHz, divided by 2
When using sub oscillation clock
μs
FCRL = 100 kHz, divided by 2
0.5
1
⎯
⎯
10
8
MHz When using main oscillation clock
MHz When using main CR oscillation clock
kHz When using sub oscillation clock
kHz When using sub CR clock
FSP
Source clock
frequency
⎯
⎯
⎯
⎯
⎯
16.384
50
⎯
⎯
FSPL
When using main oscillation clock
100
100
61
⎯
⎯
⎯
⎯
32000 ns Min : FSP = 10 MHz, no division
Max : FSP = 0.5 MHz, divided by 16
When using main CR clock
16000 ns Min : FSP = 10 MHz, no division
Max : FSP = 1 MHz, divided by 16
Machine clock
cycle time*2
(Minimum
instruction
execution time)
tMCLK
When using sub oscillation clock
976.5
320
μs Min : FSPL = 16.384 kHz, no division
Max : FSPL = 16.384 kHz, divided by 16
When using sub CR clock
μs Min : FSPL = 50 kHz, no division
Max : FSPL = 50 kHz, divided by 16
20
0.031
0.0625
1.024
3.125
⎯
⎯
⎯
⎯
10
8
MHz When using main oscillation clock
MHz When using main CR clock
FMP
Machine clock
frequency
16.384 kHz When using sub oscillation clock
50 kHz When using sub CR clock
FMPL
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) .
This source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) ,
and it becomes the machine clock. Further, the source clock can be selected as follows.
• Main clock divided by 2
• Main CR clock
• Sub clock divided by 2
• Sub CR clock divided by 2
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
DS07-12630-2E
27
MB95R203A
• Outline of clock generation block
Divided
by 2
FCH
(main oscillation)
Division
Circuit
x 1
x 1/4
x 1/8
FCRH
(Internal main
CR clock)
SCLK
(source clock)
MCLK
(machine clock)
Divided
by 2
FCL
x 1/16
(sub oscillation)
FCRL
(Internal sub
CR clock)
Divided
by 2
Clock mode select bit
(SYCC2:RCS1, RCS0)
• Operating voltage - Operating frequency (When TA = − 40 °C to + 85 °C)
(Without on chip debug function)
3.6
A/D converter operation range
2.7
1.8
16 kHz
10 MHz
Source clock frequency (FSP/FSPL)
• Operating voltage - Operating frequency ( TA = + 5 °C to + 35 °C)
(With on chip debug function)
3.6
A/D converter operation range
2.7
10 MHz
16 kHz
Source clock frequency (FSP)
28
DS07-12630-2E
MB95R203A
(3) External Reset
Parameter
(Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Unit
Remarks
Min
Max
2 tMCLK*1
⎯
ns
At normal operating
At stop mode, sub clock mode,
sub sleep mode, and watch
mode
RST “L” level pulse
width
Oscillation time of
tRSTL
⎯
⎯
μs
μs
oscillator*2 + 100
100
At time-base timer mode
*1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
*2 : Oscillationtimeofoscillatoristhetimethattheamplitudereaches90%. Inthecrystaloscillator, theoscillation
time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds
of μs and several ms. In the external clock, the oscillation time is 0 ms.
• At normal operating
t
RSTL
RST
0.2 VCC
0.2 VCC
• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
t
RSTL
RST
90% of
amplitude
0.2 VCC
0.2 VCC
X0
Internal
operating
clock
100 μs
Oscillation stabilization wait time
Oscillation time of
oscillator
Execute instruction
Internal reset
DS07-12630-2E
29
MB95R203A
(4) Power-on Reset
Parameter
(Vss = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Conditions
Unit
Remarks
Min
Max
Power supply rising time
Power supply cutoff time
tR
⎯
⎯
0.1
50
ms
ms
Waiting time until
power-on
tOFF
1
⎯
t
R
t
OFF
1.6 V
0.2 V
0.2 V
0.2 V
VCC
Note: A sudden change the power supply voltage may activate the power-on reset function. When changing
power supply voltages during operation, set the slope of rising within 30 mV/ms.
• Time from Power-on to User programing operation (reset release)
Value
Parameter
Symbol
Conditions
Unit
Min
Typ
Max
Reset release time
TRST
⎯
⎯
21
⎯
ms
Low voltage detection reset
release voltage
VDL+
VCC
Instruction execution
Internal reset
Power-on reset
Reset release time
T
RST
30
DS07-12630-2E
MB95R203A
(5) Peripheral Input Timing
Parameter
(Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C)
Value
Unit
Symbol
Pin name
Min
Max
⎯
Peripheral input “H” pulse
Peripheral input “L” pulse
tILIH
2 tMCLK*
2 tMCLK*
ns
ns
INT02 to INT07,
EC0, EC1
tIHIL
⎯
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
t
ILIH
tIHIL
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
INT02 to INT07,
EC0, EC1
DS07-12630-2E
31
MB95R203A
(6) UART/SIO, Serial I/O Timing
Parameter
(Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name
Conditions
Unit
Min
Max
⎯
Serial clock cycle time
UCK ↓ → UO time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
UCK
UCK, UO
UCK,UI
UCK, UI
UCK
4 tMCLK*
−190
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
+190
⎯
Valid UI → UCK ↑
2 tMCLK*
2 tMCLK*
4 tMCLK*
4 tMCLK*
0
UCK ↑→ valid UI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
UCK ↓ → UO time
⎯
⎯
UCK
⎯
External clock
operation output pin :
CL = 80 pF + 1 TTL.
UCK, UO
UCK, UI
UCK, UI
190
⎯
Valid UI → UCK ↑
2 tMCLK*
2 tMCLK*
UCK ↑→ valid UI hold time
⎯
* : Refer to “ (2) Source Clock/Machine Clock” for details on tMCLK.
• Internal shift clock mode
t
SCYC
2.4 V
UCK
UO
UI
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
t
IVSH
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
• External shift clock mode
UCK
t
SLSH
t
SHSL
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tSLOV
UO
UI
2.4 V
0.8 V
t
IVSH
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
32
DS07-12630-2E
MB95R203A
(7) I2C Timing
(Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C)
Value
Pin
name
Standard-
mode
Parameter
Symbol
Conditions
Fast-mode
Unit
Min
Max
Min
Max
SCL clock frequency
tSCYC
SCL
0
100
0
400
kHz
(Repeat) Start condition hold time
SDA ↓ → SCL ↓
SCL
SDA
tHD;STA
4.0
⎯
0.6
⎯
μs
SCL clock “L” width
SCL clock “H” width
tLOW
tHIGH
SCL
SCL
4.7
4.0
⎯
⎯
1.3
0.6
⎯
⎯
μs
μs
(Repeat) Start condition setup time
SCL ↑ → SDA ↓
SCL
SDA
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
4.7
0
⎯
3.45*2
⎯
0.6
0
⎯
0.9*2
⎯
μs
μs
μs
μs
μs
R = 1.7 kΩ,
C = 50 pF*1
SCL
SDA
Data hold time SCL ↓ → SDA ↓ ↑
Data setup time SDA ↓ ↑ → SCL ↑
SCL
SDA
0.25
4.0
4.7
0.1
0.6
1.3
Stop condition setup time
SCL ↑ → SDA ↓
SCL
SDA
⎯
⎯
Bus free time between stop
condition and start condition
SCL
SDA
⎯
⎯
*1 : R, C : Pull-up resistance and load capacitance of the SCL and SDA lines.
*2 : The maximum value of tHD;DAT is applicable only if the device does not extend the “L” width (tLOW) of the SCL
signal.
*3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥
250 ns must then be met.
t
WAKEUP
SDA
SCL
t
HD;STA
t
HD;DAT
tBUF
t
LOW
tHIGH
t
SU;STO
t
HD;STA
tSU;DAT
t
SU;STA
DS07-12630-2E
33
MB95R203A
(Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C)
Value*2
Pin
name
Condi-
tions
Parameter
Symbol
Unit
Remarks
Min
Max
SCL clock
“L” width
(2 + nm / 2) tMCLK
− 20
tLOW
tHIGH
SCL
SCL
⎯
ns Master mode
SCL clock
“H” width
(nm / 2) tMCLK −
(nm / 2) tMCLK +
ns Master mode
Master mode
20
20
maximum value is
applied when m, n
ns = 1, 8.
Start condition
hold time
SCL
SDA
(−1 + nm / 2)
tMCLK − 20
(−1 + nm / 2)
tMCLK + 20
tHD;STA
Otherwise, the
minimum value is
applied.
Stop condition
setup time
SCL
SDA
(1 + nm / 2) tMCLK (1 + nm / 2) tMCLK
tSU;STO
tSU;STA
ns Master mode
ns Master mode
− 20
+ 20
Start condition
setup time
SCL
SDA
(1 + nm / 2) tMCLK (1 + nm / 2) tMCLK
− 20
+ 20
Bus free time
between stop
condition and
start condition
SCL
SDA
(2 nm + 4) tMCLK
− 20
tBUF
⎯
ns
SCL
SDA
Data hold time
tHD;DAT
3 tMCLK − 20
⎯
ns Master mode
R = 1.7 kΩ,
C = 50 pF*1
Master mode
When assuming
that “L” of SCL is
not extended, the
SCL
SDA
(−2 + nm / 2)
tMCLK − 20
(−1 + nm / 2)
tMCLK + 20
minimum value is
applied to first bit of
Data setup time tSU;DAT
ns
continuous data.
Otherwise, the
maximum value is
applied.
Minimum value is
applied to interrupt
at 9th SCL↓.
Maximum value is
applied to interrupt
at 8th SCL↓.
Setup time
between
cleaning
interrupt and
SCL rising
(nm / 2) tMCLK − (1 + nm / 2) tMCLK
tSU;INT
SCL
ns
20
+ 20
SCL clock
“L” width
tLOW
tHIGH
SCL
SCL
4 tMCLK − 20
4 tMCLK − 20
⎯
⎯
ns At reception
ns At reception
SCL clock
“H” width
Undetected when
ns 1 tMCLK is used at
reception
Start condition
detection
SCL
SDA
tHD;STA
4 tMCLK − 20
⎯
(Continued)
34
DS07-12630-2E
MB95R203A
(Continued)
(Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to +85 °C)
Value*2
Pin
name
Condi-
tions
Parameter
Symbol
Unit
Remarks
Min
Max
Undetected when 1
ns tMCLK is used at
reception
Stop condition
detection
SCL
SDA
tSU;STO
4 tMCLK − 20
⎯
Undetected when 1
ns tMCLK is used at
reception
Restart condition
detection condition
SCL
SDA
tSU;STA
2 tMCLK − 20
⎯
SCL
SDA
Bus free time
tBUF
2 tMCLK − 20
2 tMCLK − 20
⎯
⎯
⎯
⎯
⎯
ns During reception
SCL
SDA
In slave transmission
mode
Data hold time
Data setup time
Data hold time
Data setup time
SDA ↓ → SCL ↑
tHD;DAT
tSU;DAT
tHD;DAT
tSU;DAT
ns
R = 1.7 kΩ,
C = 50 pF*1
SCL
SDA
tLOW − 3 tMCLK −
In slave transmission
mode
ns
20
SCL
SDA
0
ns During reception
ns During reception
SCL
SDA
tMCLK − 20
Oscillation sta-
bilization wait
time + 2 tMCLK −
20
SCL
SDA
(whenusingwakeup tWAKEUP
function)
⎯
ns
*1 : R, C : Pull-up resistance and load capacitance of the SCL and SDA lines.
*2 : • Refer to “ (2) Source Clock/Machine Clock” for details on tMCLK.
• m is the CS4 and CS3 bits (bit4 and bit3) of the I2C clock control register (ICCR0) .
• n is the CS2 to CS0 bits (bit2 to bit0) of the I2C clock control register (ICCR0) .
• The actual I2C timing is determined by the machine (tMCLK) and the values of m and n configured in bits
CS4 to CS0 of the I2C clock control register (ICCR0) .
• Standard-mode :
m and n can be set in the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.
The machine clock to be used is determined by the settings of m and n as follows.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) , : 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) , : 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98)
• Fast-mode :
: 0.9 MHz < tMCLK ≤ 1 MHz
m and n can be set in the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.
The machine clock to be used is determined by the settings of m and n as follows.
(m, n) = (1, 8)
(m, n) = (1, 22) , (5, 4)
(m, n) = (6, 4)
: 3.3 MHz < tMCLK ≤ 4 MHz
: 3.3 MHz < tMCLK ≤ 8 MHz
: 3.3 MHz < tMCLK ≤ 10 MHz
DS07-12630-2E
35
MB95R203A
(8) Low Voltage Detection
Parameter
(VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Unit
Remarks
Min Typ Max
1.75 1.85 1.95
1.65 1.75 1.85
Release voltage
VDL+
VDL−
VHYS
VDL+
VDL−
VHYS
V
V
At power-supply rise
At power-supply fall
Low voltage
Detection voltage
Hysteresis width
Release voltage
Detection voltage
Hysteresis width
detection reset
70
1.8
1.7
70
100
1.9
1.8
100
⎯
2.0
1.9
⎯
mV
V
At power-supply rise
At power-supply fall
FRAM power
V
supply monitor
mV
At LS1 = 0, LS0 = 0, power-
2.2
2.4
2.6
2.8
2.1
2.3
2.5
2.7
2.3
2.5
2.7
2.9
2.2
2.4
2.6
2.8
2.4
2.6
2.8
3.0
2.3
2.5
2.7
2.9
V
V
V
V
V
V
V
V
supply rise*
At LS1 = 0, LS0 = 1, power-
supply rise*
Release voltage
VDL+
At LS1 = 1, LS0 = 0, power-
supply rise*
At LS1 = 1, LS0 = 1, power-
supply rise*
Low voltage
detection
interrupt
At LS1 = 0, LS0 = 0, power-
supply fall*
At LS1 = 0, LS0 = 1, power-
supply fall*
Detection voltage
Hysteresis width
VDL−
At LS1 = 1, LS0 = 0, power-
supply fall*
At LS1 = 1, LS0 = 1, power-
supply fall*
VHYS
Voff
70
⎯
100
⎯
⎯
1.2
⎯
mV
V
Power-supply start voltage
Power-supply end voltage
Von
2.0
⎯
V
Slope of power supply that
reset release signal generates
0.3
⎯
200
⎯
⎯
⎯
⎯
⎯
μs
Power-supply voltage
change time
tr
Slope of power supply that
(at power supply rise)
⎯
μs reset release signal generates
within rating (V1DL+, V2DL+)
Slope of power supply that
μs
0.3
⎯
reset detection signal generates
Power-supply voltage
change time
tf
Slope of power supply that
μs reset detection signal generates
within rating (V1DL−, V2DL−)
(at power supply fall)
200
Reset release delay time
Reset detection delay time
td1
td2
⎯
⎯
⎯
⎯
300
20
μs
μs
* : LS1 and LS0 mean the LS1 bit and the LS0 bit (bit1 and bit0) for the low voltage detection interrupt control
register (LVDCR) respectively.
36
DS07-12630-2E
MB95R203A
V
CC
V
V
on
off
time
t
f
tr
V
DL+
DL-
VHYS
V
Internal reset
signal
time
t
d1
t
d2
DS07-12630-2E
37
MB95R203A
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(Vcc = 2.7 V to 3.6 V, Vss = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter
Resolution
Symbol
Unit
Remarks
Min
⎯
Typ
⎯
Max
10
bit
Total error
− 5.0
− 3.5
⎯
+ 5.0
+ 3.5
LSB
LSB
⎯
Linearity error
⎯
Differential linear
error
− 3.0
⎯
+ 3.0
LSB
V
Zero transition
voltage
VOT
VSS − 1.5 LSB VSS + 0.5 LSB VSS + 4.0 LSB
VCC − 4.0 LSB VCC − 1.5 LSB VCC + 0.5 LSB
Full-scale transition
voltage
VFST
V
Compare time
⎯
1.1
0.4
VSS
⎯
⎯
⎯
27.5
∞
μs
2.7 V ≤ Vcc ≤ 3.6 V
Sampling time
⎯
μs At external impedance
< 1.8 kΩ
Analog input voltage
VAIN
VCC
V
38
DS07-12630-2E
MB95R203A
(2) Notes on Using A/D Converter
• About the external impedance of analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relation-
ship between the external impedance and minimum sampling time and either adjust the register value and
operatingfrequencyordecreasetheexternalimpedancesothatthesamplingtimeislongerthantheminimum
value. Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input
pin.
• Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling : ON
2.7 V ≤ Vcc ≤ 3.6 V : R =: 5.3 kΩ (Max) , C =: 8.5 pF (Max)
Note : The values are reference values.
• The relationship between external impedance and minimum sampling time.
[External impedance = 0 kΩ to 20 kΩ]
[External impedance = 0 kΩ to 100 kΩ]
100
90
80
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
6
4
2
0
0
5
10 15 20 25 30 35 40
0
1
2
3
4
Minimum sampling time [μs]
Minimum sampling time [μs]
• About errors
|VCC − VSS| becomes smaller, values of relative errors grow larger.
DS07-12630-2E
39
MB95R203A
(3) Definition of A/D Converter Terms
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000” ←→ “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1111” ←→ “11 1111 1110”) compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit : LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition
error, linearity error, quantum error, and noise.
Ideal I/O characteristics
Total error
VFST
3FF
3FE
3FD
3FF
3FE
3FD
Actual conversion
characteristic
1.5 LSB
{1 LSB × (N − 1) + 0.5 LSB}
004
003
002
001
004
003
002
001
V
NT
V
OT
Actual conversion
characteristic
1 LSB
0.5 LSB
Ideal characteristics
VSS
V
CC
VSS
VCC
Analog input
Analog input
Total error of
digital output N
VCC − VSS
VNT − {1 LSB × (N − 1) + 0.5 LSB}
=
1 LSB =
(V)
[LSB]
1024
1 LSB
N
: A/D converter digital output value
VNT : A voltage at which digital output transits from (N - 1) to N
(Continued)
40
DS07-12630-2E
MB95R203A
(Continued)
Full-scale transition error
Zero transition error
Ideal
004
003
002
001
characteristics
Actual conversion
characteristic
3FF
3FE
3FD
3FC
Actual conversion
characteristic
Ideal
characteristics
VFST
(measurement
value)
Actual conversion
characteristic
Actual conversion
characteristic
VOT (measurement value)
VSS
VCC
VSS
VCC
Analog input
Analog input
Linearity error
Differential linear error
Actual conversion
characteristic
Ideal characteristics
3FF
3FE
3FD
N+1
N
Actual conversion
characteristic
{1 LSB × N + VOT}
V (N+1) T
VFST
(measure-
ment value)
VNT
004
003
002
001
N-1
N-2
VNT
Actual conversion
characteristic
Actual conversion
characteristic
Ideal characteristics
VOT (measurement value)
VSS
VCC
VSS
VCC
Analog input
Analog input
Linearity error in
digital output N
VNT − {1 LSB × N + VOT}
V (N + 1) T − VNT
Differential linear error
In digital output N
=
=
− 1
1 LSB
1 LSB
N
: A/D converter digital output value
VNT : A voltage at which digital output transits from (N - 1) to N.
VOT (Ideal value) = VSS + 0.5 LSB [V]
VFST (Ideal value) = VCC − 2.0 LSB [V]
DS07-12630-2E
41
MB95R203A
6. FRAM Characteristics
Parameter
Value
Typ
Unit
Remarks
Min
Max
Number of read/write cycle
⎯
1015*
⎯
cycle
*: TA = +25 °C
42
DS07-12630-2E
MB95R203A
■ EXAMPLE CHARACTERISTICS
• Power supply current and temperature characteristics
ICC-VCC
ICC-TA
TA = + 25 °C, FMP = 2, 4, 8, 10 MHz (divided by 2)
Main clock mode with external clock operating
VCC = 3.6 V, FMP = 10 MHz (divided by 2)
Main clock mode with external clock operating
5
4
3
2
1
0
5
4
3
10 MHz
8 MHz
2
4 MHz
2 MHz
1
0
-50
0
+50
+100
1.5
2
2.5
VCC [V]
3
3.5
4
TA [°C]
ICCS-VCC
ICCS-TA
VCC = 3.6V, FMP = 10 MHz (divided by 2)
Main sleep mode with the external clock operating
TA = + 25 °C, FMP = 2, 4, 8, 10 MHz (divided by 2)
Main sleep mode with the external clock operating
5
5
4
3
4
3
2
1
0
2
10MHz
8MHz
4MHz
2MHz
1
0
1.5
2
2.5
3
3.5
4
-50
0
+50
+100
V
CC [V]
TA [°C]
ICCL-VCC
ICCL-TA
VCC = 3.6 V,FMPL = 16kHz (divided by 2)
Sub clock mode with the external clock operating
TA = + 25 °C, FMPL = 16 kHz (divided by 2)
Sub clock mode with the external clock operating
200
200
150
100
50
150
100
50
0
0
-50
0
+50
+100
1.5
2
2.5
VCC [V]
3
3.5
4
TA [°C]
(Continued)
DS07-12630-2E
43
MB95R203A
ICCLS-VCC
ICCLS-TA
TA = + 25 °C, FMP = 16 kHz (divided by 2)
Sub sleep mode with external clock operating
VCC = 3.6 V,FMPL = 16 kHz (divided by 2)
Sub sleep mode with external clock operating
200
150
100
50
200
150
100
50
0
0
1.5
2
2.5
3
3.5
4
-50
0
+50
+100
V
CC [V]
TA [°C]
ICCT-VCC
ICCT-TA
TA = + 25 °C, FMPL = 16 kHz (divided by 2)
Watch mode with external clock operating
200
VCC = 3.6 V,FMPL = 16 kHz (divided by 2)
Watch mode with external clock operating
200
150
100
50
150
100
50
0
0
1.5
2
2.5
3
3.5
4
-50
0
+50
+100
VCC [V]
TA [°C]
ICTS-VCC
ICTS-TA
TA = + 25 °C, FMP = 16 kHz (divided by 2)
Timebase timer mode with external clock operating
VCC = 3.6 V,FMP = 10MHz (divided by 2)
Timebase timer mode with external clock operating
2
1.5
1
2
1.5
1
0.5
0.5
0
10MHz
8MHz
4MHz
2MHz
0
1.5
2
2.5
CC [V]
3
3.5
4
-50
0
+50
+100
V
TA [°C]
(Continued)
44
DS07-12630-2E
MB95R203A
(Continued)
ICCH-VCC
ICCH-TA
TA = + 25 °C, FMP = (stop)
Sub stop mode with the external clock operating
VCC = 3.6 V,FMPL = (stop)
Sub stop mode with the external clock stopping
200
150
100
50
200
150
100
50
0
0
1.5
2
2.5
3
3.5
4
-50
0
+50
+100
V
CC [V]
TA [°C]
ICCMCR-VCC
ICCMCR-TA
TA = + 25 °C, FMP = 1 MHz (no division)
Main clock mode with
VCC = 3.6 V,FMP = 1 MHz (no division)
Main clock mode with
internal main CR clock operating
internal main CR clock operating
5
5
4
3
2
1
0
4
3
2
1
0
1.5
2
2.5
VCC [V]
3
3.5
4
-50
0
+50
+100
TA [°C]
ICCSCR-VCC
ICCSCR-TA
VCC=3.6V,FMPL = 50 kHz (divided by 2)
Sub clock mode with internal sub CR clock operating
TA = + 25 °C, FMP = 50 kHz (divided by 2)
Sub clock mode with internal main CR clock operating
200
200
150
100
50
150
100
50
0
0
1.5
2
2.5
VCC [V]
3
3.5
4
-50
0
+50
+100
TA [°C]
DS07-12630-2E
45
MB95R203A
• Input voltage characteristics
VIHS-VCC and VILS-VCC
VIHI-VCC and VILI-VCC
TA = + 25 °C
TA = + 25 °C
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
1.5
2
2.5
CC [V]
3
3.5
4
V
1.5
2
2.5
CC [V]
3
3.5
4
V
46
DS07-12630-2E
MB95R203A
• Output voltage characteristics
(VCC-VOH1)-IOH
(VCC-VOH2)-IOH
TA = + 25 °C
TA = + 25 °C
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
0
-2
-4
-6
IOH [μA]
-8
-10
0
-2
-4
-6
OH [μA]
-8
-10
I
VCC
1.8V
VCC
1.8V
2.0V
2.7V
3V
2.0V
2.7V
3.0V
3.6V
3.6V
VOL1-IOL
VOL2-IOL
TA = + 25 °C
TA = + 25 °C
1
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10 12
0
2
4
6
8
10 12
IOL [μA]
IOL [μA]
VCC
1.8V
VCC
1.8V
2.0V
2.7V
3.0V
3.6V
2.0V
2.7V
3.0V
3.6V
DS07-12630-2E
47
MB95R203A
• Pull-up characteristics
RPULL-VCC
TA = + 25 °C
100
80
60
40
20
0
1.5
2
2.5
VCC [V]
3
3.5
4
48
DS07-12630-2E
MB95R203A
■ ORDERING INFORMATION
Part number
Package
Remarks
24-pin plastic DIP
(DIP-24P-M07)
MB95R203AP-G-SH-JNE2
MB95R203APF-G-JNE2
20-pin plastic SOP
(FPT-20P-M09)
DS07-12630-2E
49
MB95R203A
■ PACKAGE DIMENSIONS
24-pin plastic SDIP
Lead pitch
1.778 mm
6.40 mm × 22.86 mm
Plastic mold
Package width
package length
×
Sealing method
Mounting height
4.80 mm Max
(DIP-24P-M07)
24-pin plastic SDIP
(DIP-24P-M07)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
#22.86 0.10(.900 .004)
24
13
BTM E-MARK
INDEX
6.40 0.10
(.252 .004)
7.62(.300)
1
12
TYP.
0.50(.020)
MIN
4.80(.189)MAX
0.25 –+00..0140
.010–+..000024
.118 +–..001028
3.00–+00..3200
0.43 +–00..0049
1.778(.070)
1.00 0.10
(.039 .004)
.017+–..000024
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED D24066S-c-1-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
50
DS07-12630-2E
MB95R203A
(Continued)
20-pin plastic SOP
Lead pitch
1.27 mm
7.50 mm × 12.70 mm
Gullwing
Package width
package length
×
Lead shape
Lead bend
direction
Normal bend
Plastic mold
Sealing method
Mounting height
2.65 mm Max
(FPT-20P-M09)
20-pin plastic SOP
(FPT-20P-M09)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
0.25 +–00..0027
#12.70 0.10(.500 .004)
.010 –+..000013
20
11
BTM E-MARK
+0.40
#7.50 0.10
(.295 .004)
10.2 –0.20
.402 +–..000186
INDEX
Details of "A" part
+0.13
2.52 –0.17
(Mounting height)
.099 –+..000075
"A"
1
10
0.40 –+00..0059
.016 –+..000024
0~8°
1.27(.050)
M
0.25(.010)
0.80–+00..3407
0.20 0.10
(.008 .004)
(Stand off)
.031–+..001129
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED F20030S-c-1-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-12630-2E
51
MB95R203A
■ MAJOR CHANGES IN THIS EDITION
Page
Section
Change Results
■ NOTES ON ON-CHIP DEBUG
Corrected the title.
DEBUG → ON-CHIP DEBUG
Added the sentence as follows.
12
“When you click on the [Erase Flash Memory] and the
[Target load] button on SOFTUNE Workbench,data in the I/O
area described below is undefined.”.
Added the table of address 0070H, 0071H.
■ ELECTRICAL
Corrected the condition and the value of “Open-drain output
CHARACTERISTICS
3. DC Characteristics
leak current”.
23
Corrected the maximum value of “Pull-up resistance”.
66 → 80
23, 24
30
Corrected the power supply current.
4. AC Characteristics
(4) Power-on Reset
Added “• Time from Power-on to User programing operation
(reset release)”.
5. A/D Converter
(1) A/D Converter Electrical
Characteristics
Corrected the value of Total error.
Min : − 3.0→ − 5.0
Max : + 3.0→ + 5.0
Corrected the value of Linearity error.
Min : − 2.5→ − 3.5
Max : + 2.5→ + 3.5
Corrected the value of Differential linear error.
Min : − 1.9→ − 3.0
Max : + 1.9→ + 3.0
38
Corrected the maximum value of Zero transition voltage.
VSS + 2.5 LSB → VSS + 4.0 LSB
Corrected the minimum value of Full-scale transition voltage.
VCC − 3.5 LSB → VCC − 4.0 LSB
Corrected the value of Compare time.
Min : 0.6 → 1.1
Max : 140 → 27.5
Deleted the item of Analog input current.
6. FRAM Characteristics
Corrected the value.
Min:1015 → “ − ”
42
Typ: “ − ”→ 1015
Added the footnote.
43 to 48 ■ EXAMPLE CHARACTERISTICS
Added a new section.
The vertical lines drawn on the left side of the page indicate the changes.
52
DS07-12630-2E
MB95R203A
MEMO
DS07-12630-2E
53
MB95R203A
MEMO
54
DS07-12630-2E
MB95R203A
MEMO
DS07-12630-2E
55
MB95R203A
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fss/
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
FUJITSU SEMICONDUCTOR KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-
ing in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-
current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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