MB95R203PF-G-JNE2_技术文档

FUJITSU MICROELECTRONICS

DATA SHEET

DS07-12625-3E

8-bit Proprietary Microcontrollers

CMOS

F²MC-8FX MB95R203

MB95R203

■ DESCRIPTION

The MB95R203 is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the

microcontrollers contain a variety of peripheral functions.

Note : F²MC is the abbreviation of FUJITSU Flexible Microcontroller.

■ FEATURES

• F²MC-8FX CPU core

Instruction set optimized for controllers

• Multiplication and division instructions

• 16-bit arithmetic operations

• Bit test branch instruction

• Bit manipulation instructions etc.

• Clock

• Selectable Main clock source

Main OSC clock (Up to 10 MHz, Maximum Machine clock frequency is 5 MHz)

External clock (Up to 20 MHz, Maximum Machine clock frequency is 10 MHz)

Internal main CR clock (Typ 1 MHz, Machine clock frequency is 1 MHz)

• Selectable Sub clock source

Sub OSC clock (32 kHz)

Sub internal CR clock (Typ : 100 kHz, Min : 50 kHz, Max : 200 kHz)

(Continued)

2009.8

MB95R203

(Continued)

• Timer

• 8/16-bit composite timer

• Timebase timer

• Watch prescaler

• UART/SIO

• Offers clock asynchronous (UART) or clock synchronous (SIO) serial data transfer

• Full duplex double buffer

• I²C

• Built-in wake-up function

• External interrupt

• Interrupt by the edge detection (Select rising edge/falling edge/both edges)

• Can be used to recover from low-power consumption modes (also called standby mode)

• 8/10-bit A/D converter

• 8-bit or 10-bit resolutions can be selected

• Low-power consumption (standby) mode

• Stop mode

• Sleep mode

• Watch mode

• Timebase timer mode

• I/O port : Max 16

• General-purpose I/O ports (Max) :

CMOS I/O : 12, N-ch open drain : 4

• On-chip debug

• 1 wire serial control

• Support serial writing. (Asynchronous mode)

• Hardware/Software watchdog timer

• Built-in Hardware watchdog timer

• Low voltage detection circuit (LVD)

• Low voltage detection reset circuit

• Circuit to monitor FRAM power supply

• Clock supervisor counter (CSV)

• Built-in Clock supervise function

• Programmable input voltage levels of port

• CMOS input level / hysteresis input level

• FRAM

• Non-volatile memory

• 8 Kbytes of FRAM integrated on-chip

• FRAM memory security function

• Protects the content of FRAM memory

2

DS07-12625-3E

MB95R203

■ PRODUCT OVERVIEW

Part number

Parameter

MB95R203

ROM (FRAM) capacity

RAM capacity

8 Kbytes

496 bytes

Yes

Reset output

Low voltage detection

Yes

Number of basic instructions

Instruction bit length

Instruction length

: 136 instructions

: 8 bits

: 1 to 3 bytes

: 1, 8, and 16 bits

CPU function

Data bit length

Minimum instruction execution time : 300 ns (at machine clock 10 MHz)

Interrupt processing time

: 1.7 μs (at machine clock 10 MHz)

General-purpose I/O ports (Max) : 16

CMOS I/O : 12, N-ch open drain : 4

Port

Timebase timer

Interrupt cycle : 0.256 ms to 8.3 s (at external 4 MHz)

Reset generation cycle

Main clock at 10 MHz : 105 ms (Min)

Subclock CR can be used as the Watchdog source clock.

Hardware/software

Watchdog timer

Wild registers

UART/SIO

It can be used to replace three bytes of data.

Able to transfer data using UART/SIO

Variable data length (5/6/7/8-bit) , built-in baud rate generator

Transfer rate (2400 bps to 125000 bps at 10 MHz) , full-duplex transfers with

built-in double buffers

NRZ type transfer format, error detection function

LSB-first or MSB-first can be selected

Capable of clock synchronous (SIO) or clock asynchronous (UART) serial data

transfer

Transmit and receive master/slave

Bus function, arbitration function, transfer direction detection function

Start condition repeated generation and detection functions

Built-in timeout detection function

I²C bus

6 ch

8/10-bit A/D converter

8-bit or 10-bit resolution can be selected

2 ch

Can be configured as a 2 ch × 8-bit timer or 1 ch × 16-bit timer

Built-in timer function, PWC function, PWM function and capture function

Count clock : available from internal clocks (7 types) or external clocks

With square wave output

8/16-bit composite timer

6 ch

External interrupt

On-chip debug

Interrupt by edge detection (Select rising edge/falling edge/both edges)

Can be used to recover from standby modes

1 wire serial control

Support serial writing. (Asynchronous mode)

(Continued)

DS07-12625-3E

3

MB95R203

(Continued)

Part number

MB95R203

Parameter

Watch prescaler

Eight different time intervals can be selected.

Non-volatile memory

Number of read/write cycles : (Min)10¹⁰times (Typ)10¹¹times

Data retention characteristics : 10 years ( + 55 °C)

Read security function

FRAM

Function to monitor FRAM power supply

Standby Mode

Package

Sleep mode, Stop mode, Watch mode, timebase timer mode

SDIP-24, SOP-20

4

DS07-12625-3E

MB95R203

■ PIN ASSIGNMENT

(TOP VIEW)

X0

NC

X1

1

2

3

4

5

6

7

8

9

24

23

22

21

20

19

18

17

16

15

14

13

P12/EC0/DBG

NC

P07/INT07

P06/INT06/TO01

P05/INT05/AN05/TO00/HCLK2

P04/INT04/AN04/UI/HCLK1/EC0

P03/INT03/AN03/UO

P02/INT02/AN02/UCK

P01/AN01

24pin

(DIP-24)

Vss

X1A/PG2

X0A/PG1

Vcc

SCL/P65

RST/PF2

TO10/P62

NC

10

11

12

P00/AN00

NC

P64/EC1/SDA

TO11/P63

*The number of usable pins is 20.

(DIP-24P-M07)

(TOP VIEW)

X0

X1

Vss

1

2

3

4

5

6

7

8

9

20

19

18

17

16

15

14

13

12

11

P12/EC0/DBG

P07/INT07

P06/INT06/TO01

P05/INT05/AN05/TO00/HCLK2

P04/INT04/AN04/UI/HCLK1/EC0

P03/INT03/AN03/UO

P02/INT02/AN02/UCK

P01/AN01

20pin

(SOP-20)

X1A/PG2

X0A/PG1

Vcc

SCL/P65

RST/PF2

TO10/P62

TO11/P63

P00/AN00

P64/EC1/SDA

10

(FPT-20P-M09)

DS07-12625-3E

5

MB95R203

■ PIN DESCRIPTION

Pin no.

I/O

Circuit

type*

Pin name

Function

Main clock input oscillation pin

SDIP24 SOP20

1

3

4

1

2

3

X0

X1

B

Main clock input/output oscillation pin

Power supply pin (GND)

Vss

⎯

General-purpose I/O port

This pin is also used as Sub clock input/output oscillation pin.

5

4

PG2/X1A

C

General-purpose I/O port

This pin is also used as Sub clock input oscillation pin.

6

7

8

5

6

7

PG1/X0A

Vcc

C

⎯

I

Power supply pin

General-purpose I/O port

This pin is also used as I²C clock I/O.

P65/SCL

General-purpose I/O port

This pin is also used as reset pin

9

8

9

PF2/RST

A

D

General-purpose I/O port

High current port

10

P62/TO10

This pin is also used as 8/16-bit composite timer ch.1 output.

General-purpose I/O port

12

13

10

11

P63/TO11

D

I

This pin is also used as 8/16-bit composite timer ch.1 output.

High current port

General-purpose I/O port

This pin is also used as I²C data I/O.

P64/SDA/EC1

This pin is also used as 8/16-bit composite timer ch.1 clock input.

General-purpose I/O port

This pin is also used as A/D converter analog input.

15

16

12

13

P00/AN00

P01/AN01

E

General-purpose I/O port

This pin is also used as A/D converter analog input.

General-purpose I/O port

P02/INT02/AN02/

UCK

This pin is also used as external interrupt input.

This pin is also used as A/D converter analog input.

This pin is also used as UART/SIO clock I/O.

17

18

14

15

E

General-purpose I/O port

P03/INT03/AN03/

UO

This pin is also used as external interrupt input.

This pin is also used as A/D converter analog input.

This pin is also used as UART/SIO data output.

General-purpose I/O port

This pin is also used as external interrupt input.

This pin is also used as A/D converter analog input.

This pin is also used as UART/SIO data input.

This pin is also used as 8/16-bit composite timer ch.0 clock input.

P04/INT04/AN04/

UI/HCLK1/EC0

19

16

F

(Continued)

6

DS07-12625-3E

MB95R203

(Continued)

Pin no.

I/O

Circuit

type*

Pin name

Function

SDIP24 SOP20

General-purpose I/O port

This pin is also used as external interrupt input.

P05/INT05/AN05/

TO00/HCLK2

20

21

17

18

E

This pin is also used as A/D converter analog input.

The pins are also used as 8/16-bit compound timer ch.0 output.

This pin is also used as the external clock input.

General-purpose I/O port

High current port

This pin is also used as external interrupt input.

This pin is also used as 8/16-bit compound timer ch.0 output.

P06/INT06/TO01

G

General-purpose I/O port

This pin is also used as external interrupt input.

22

24

19

20

⎯

P07/INT07

P12/EC0/DBG

NC

G

H

General-purpose I/O port

This pin is also used as DBG input pin.

This pin is also used as 8/16-bit composite timer ch.0 clock input.

2, 11,

14, 23

⎯

Internal connect pin. Be sure this pin is left open.

* : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.

DS07-12625-3E

7

MB95R203

■ I/O CIRCUIT TYPE

Type

Circuit

Reset input / Hysteresis input

Reset output / Digital output

Remarks

A

• N-ch open drain output

• Hysteresis input

• Reset output

N-ch

B

• Oscillation circuit

• High-speed side

Feedback resistance : approx. 1 MΩ

• CMOS output

• Hysteresis input

Clock input

X1

X0

Standby control

C

• Oscillation circuit

• Low-speed side

Feedback resistance : approx. 10 MΩ

• CMOS output

• Hysteresis input

Port select

R

Pull-up control

P-ch

N-ch

P-ch

Digital output

• With pull-up control

Standby control

Hysteresis input

Clock input

X1A

X0A

Standby control / Port select

Clock input

Port select

R

Pull-up control

Digital

output

P-ch

Digital output

N-ch

Standby control

Hysteresis input

D

• CMOS output

• Hysteresis input

P-ch

Digital output

N-ch

Standby control

Hysteresis input

(Continued)

8

DS07-12625-3E

MB95R203

(Continued)

Type

Circuit

Remarks

E

• CMOS output

Pull-up control

• Hysteresis input

R

• With pull-up control

P-ch

N-ch

Digital output

P-ch

Analog input

A/D control

Standby control

Hysteresis input

F

• CMOS output

Pull-up control

• Hysteresis input

• CMOS input

• With pull-up control

R

P-ch

N-ch

Digital output

P-ch

Analog input

A/D control

Standby control

Hysteresis input

CMOS input

G

• Hysteresis input

• CMOS output

• With pull-up control

Pull-up control

R

P-ch

N-ch

Digital output

P-ch

Standby control

Hysteresis input

H

I

• N-ch open drain output

• Hysteresis input

Hysteresis input

Digital output

N-ch

• N-ch open drain output

• CMOS input

• Hysteresis input

Digital output

N-ch

CMOS input

Hysteresis input

Standbycontrol

DS07-12625-3E

9

MB95R203

■ NOTES ON DEVICE HANDLING

• Preventing Latch-up

Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.

Latch-up may occur on CMOS ICs if voltage higher than V^CCor lower than VSS is applied to input and output pins

other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between V^CC

pin and VSS pin.

When latch-up occurs, power supply current increases rapidly and might thermally damage elements.

• Stable Supply Voltage

Supply voltage should be stabilized.

A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range

of the Vcc power-supply voltage.

For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range

(50 Hz / 60 Hz) not to exceed 10% of the standard Vcc value and suppress the voltage variation so that the

transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply

is switched.

• Precautions for Use of External Clock

Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up

from sub clock mode or stop mode.

• Do not use a sample used in program development as mass-produced product.

10

DS07-12625-3E

MB95R203

■ PIN CONNECTION

• Treatment of Unused Input Pin

Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent dam-

age. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused

input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused

input pins. If there is unused output pin, make it to open.

• Power Supply Pins

In products with multiple V^CCor VSS pins, the pins of the same potential are internally connected in the device

to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply

and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals

caused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the V^CCand VSS pins of this device at the low impedance. It

is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between V^CCand VSS near this

device.

• DBG Pin

Connect the DBG pin directly to external Pull-up.

To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to

minimize the distance from the DBG pins to V^CCor VSS pins.

The DBG pin should not stay at “L” level after power-on until the reset output is released.

• RST Pin

Connect the RST pin directly to Pull-up.

To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to

minimize the distance from the RST pins to VCC or VSS pins.

The RST/PF2 pin functions as the reset input/output pin after power-on. In addition, the reset output can be

enabled by the RSTOE bit of the SYSC register, and the reset input function or the general purpose I/O function

can be selected by the RSTEN bit of the SYSC register.

• Example of DBG / RST connection diagram

R

DBG

R

RST

Pull-up resistor recommended

resistance

For DBG pin : R = 4.7 kΩ

For RST pin : R = 10 kΩ

DS07-12625-3E

11

MB95R203

■ RESTRICTIONS

• Data written to FRAM before IR reflow is not guaranteed to retain after IR reflow.

(Data written to FRAM might be broken by heart processing at IR reflow.)

■ NOTES ON DEBUG

• Although the [Upload Flash Memory] button is enabled, clicking it does not start the actual processing.

• When you click on the [Erase Flash Memory] button on S^OFTUNEWorkbench, data is overwritten into the FRAM

area, as shown below.

Address

Data to be overwritten

F554^H

55H

A0H

FAAAH

FFBCH

Indeterminate

FF^H

FFBD^H

Entire FRAM except the above

• Be very careful not to apply voltages to the pins PF2/RST in excess of the absolute maximum ratings. Especially

when handling devices in the environment compatible to the package, such as MB95F200H/210H and so on,

the voltage may be erroneously applied to the pins PF2/RST in excess of the maximum rating and it may cause

thermal breakdown of the device.

12

DS07-12625-3E

MB95R203

■ BLOCK DIAGRAM

F²MC-8FX CPU

PF2^*1/RST^*2

Reset

LVD

X1

X0

PG2/X1A^*2

PG1/X0A^*2

FRAM (8 Kbytes)

with security

Oscillator

circuit

CR

Oscillator

RAM (496 bytes)

Clock control

(P05/TO00)

8/16-bit

composite timer (0)

P12^*1/DBG

(P06/TO01)

On-chip debug

P12/EC0(P04/EC0)

Wild register

P62/TO10

P63/TO11

(P64/EC1)

8/16-bit

composite timer (1)

External interrupt

P02/INT02 to P07/INT07

P65^*1/SCL^*1

P64^*1/SDA^*1

I²C

8/10-bit A/D converter

(P00/AN00 to P05/AN05)

(P02/UCK)

(P04/UI)

UART/SIO

(P03/UO)

Port

VCC

VSS

*1 : P12, P64, P65, PF2 is N-ch open drain

*2 : Software option

DS07-12625-3E

13

MB95R203

■ CPU CORE

1. Memory space

Memory space of the MB95R203 is 64 Kbytes and consists of I/O area, data area, and program area. The

memory space includes special-purpose areas such as the general-purpose registers and vector table. Memory

map of the MB95R203 shown below.

• Memory Map

MB95R203

0000^H

I/O

0080H

0090H

-

RAM 496 B

0100H

Register

0200H

0280H

-

0F80H

Extension I/O

1000H

-

E000H

FRAM 8 KB

FFFFH

14

DS07-12625-3E

MB95R203

■ I/O MAP

Register

abbreviation

Address

Register name

R/W

Initial value

0000^H

0001H

0002H

0003H

0004H

0005^H

0006H

0007^H

0008H

0009H

000AH

000BH

000CH

000DH

PDR0

DDR0

PDR1

DDR1

⎯

Port 0 data register

Port 0 direction register

R/W

⎯

00000000B

⎯

Port 1 data register

Port 1 direction register

(disabled)

WATR

⎯

Oscillation stabilization wait time setting register

(disabled)

R/W

⎯

11111111B

⎯

SYCC

STBC

RSRR

TBTC

WPCR

WDTC

SYCC2

System clock control register

Standby control register

Reset source register

R/W

R

XXXXXX11B

00000XXXB

XXXXXXXXB

00000000B

XX100011B

Timebase timer control register

Watch prescaler control register

Watchdog timer control register

System clock control register 2

R/W

000EH

to

0015^H

⎯

(disabled)

⎯

0016^H

0017H

PDR6

DDR6

Port 6 data register

R/W

00000000B

Port 6 direction register

0018H

to

0027^H

⎯

(disabled)

⎯

0028^H

0029H

002AH

002BH

002CH

PDRF

DDRF

PDRG

DDRG

PUL0

Port F data register

Port F direction register

Port G data register

R/W

00000000B

Port G direction register

Port 0 pull-up register

002DH

to

0034^H

⎯

(disabled)

⎯

0035^H

0036H

0037H

0038H

0039H

PULG

Port G pull-up register

R/W

00000000B

T01CR1

T00CR1

T11CR1

T10CR1

8/16-bit compound timer 01 control status register 1 ch.0 R/W

8/16-bit compound timer 00 control status register 1 ch.0 R/W

8/16-bit compound timer 11 control status register 1 ch.1 R/W

8/16-bit compound timer 10 control status register 1 ch.1 R/W

(Continued)

DS07-12625-3E

15

MB95R203

Register

Address

Register name

R/W

Initial value

abbreviation

003A^H

to

0048^H

⎯

(disabled)

⎯

0049^H

004AH

004BH

EIC10

EIC20

EIC30

External interrupt circuit control register ch.2/ch.3

External interrupt circuit control register ch.4/ch.5

External interrupt circuit control register ch.6/ch.7

R/W

00000000B

004CH

to

0055^H

⎯

(disabled)

⎯

0056^H

0057H

0058H

0059H

005AH

SMC1

SMC2

SSR

UART/SIO serial mode control register 1

UART/SIO serial mode control register 2

UART/SIO serial status and data register

UART/SIO serial output data register

UART/SIO serial input data register

R/W

00000000B

00100000B

00000001B

00000000B

TDR

RDR

005BH

to

005F^H

⎯

(disabled)

⎯

0060^H

0061H

0062H

0063H

0064H

0065H

0066H

0067H

0068H

0069H

006AH

006BH

006CH

006DH

006EH

006FH

0070H

0071H

IBCR00

IBCR10

IBSR0

IDDR0

IAAR0

ICCR0

FSCR

FRAC

FABH

FABL

I²C bus control register 0

I²C bus control register 1

R/W

R

00000000B

11111111B

00000000B

XXXXXXXXB

I²C bus status register

I²C data register

I²C address register

I²C clock control register

FRAM status/control register

FRAM register access control register

FRAM write permit start address register (H)

FRAM write permit start address register (L)

FRAM write permit area size register (H)

FRAM write permit area size register (L)

8/10-bit A/D converter control register 1

8/10-bit A/D converter control register 2

8/10-bit A/D converter data register (upper byte)

8/10-bit A/D converter data register (lower byte)

FRAM violation address register (H)

FRAM violation address register (L)

FASH

FASL

ADC1

ADC2

ADDH

ADDL

FVAH

FVAL

R

XXXXXXXXB

(Continued)

16

DS07-12625-3E

MB95R203

Register

abbreviation

Address

Register name

R/W

Initial value

0072^H

to

0075^H

⎯

(disabled)

⎯

0076^H

0077H

WREN

WROR

Wild register address compare enable register

Wild register data test setting register

R/W

00000000B

Register bank pointer (RP) ,

Mirror of direct bank pointer (DP)

0078H

⎯

0079^H

007AH

007BH

007CH

007DH

007EH

007FH

0F80^H

0F81H

0F82H

0F83H

0F84H

0F85H

0F86H

0F87H

0F88H

ILR0

ILR1

Interrupt level setting register 0

Interrupt level setting register 1

R/W

⎯

11111111B

⎯

ILR2

Interrupt level setting register 2

ILR3

Interrupt level setting register 3

ILR4

Interrupt level setting register 4

ILR5

Interrupt level setting register 5

⎯

(disabled)

WRARH0

WRARL0

WRDR0

WRARH1

WRARL1

WRDR1

WRARH2

WRARL2

WRDR2

Wild register address setting register (upper byte) ch.0

Wild register address setting register (lower byte) ch.0

Wild register data setting register ch.0

Wild register address setting register (upper byte) ch.1

Wild register address setting register (lower byte) ch.1

Wild register data setting register ch.1

Wild register address setting register (upper byte) ch.2

Wild register address setting register (lower byte) ch.2

Wild register data setting register ch.2

R/W

00000000B

0F89H

to

0F91^H

⎯

(disabled)

⎯

0F92^H

0F93H

0F94H

0F95H

T01CR0

T00CR0

T01DR

T00DR

8/16-bit compound timer 01 control status register 0 ch.0 R/W

8/16-bit compound timer 00 control status register 0 ch.0 R/W

00000000B

8/16-bit compound timer 01 data register ch.0

8/16-bit compound timer 00 data register ch.0

R/W

8/16-bit compound timer 00/01 timer mode control

register ch.0

0F96H

TMCR0

R/W

00000000^B

0F97H

0F98H

T11CR0

T10CR0

8/16-bit compound timer 11 control status register 0 ch.1 R/W

8/16-bit compound timer 10 control status register 0 ch.1 R/W

00000000B

(Continued)

DS07-12625-3E

17

MB95R203

(Continued)

Register

Address

Register name

R/W

Initial value

abbreviation

0F99^H

0F9AH

T11DR

T10DR

8/16-bit compound timer 11 data register ch.1

8/16-bit compound timer 10 data register ch.1

R/W

00000000B

8/16-bit compound timer 10/11 timer mode control

register ch.1

0F9BH

TMCR1

R/W

00000000^B

0F9CH

to

0FBD^H

⎯

(disabled)

⎯

0FBE^H

0FBFH

PSSR0

BRSR0

UART/SIO prescaler select register

UART/SIO baud rate setting register

R/W

00000000B

0FC0H

to

0FC2^H

⎯

AIDRL

⎯

(disabled)

A/D input disable register lower

(disabled)

⎯

R/W

⎯

00000000B

⎯

0FC3^H

0FC4H

to

0FE3^H

0FE4^H

0FE5H

CRTH

CRTL

CR-trimming register upper

CR-trimming register lower

R/W

1XXXXXXXB

000XXXXXB

0FE6H,

0FE7^H

⎯

(disabled)

⎯

0FE8^H

0FE9H

0FEAH

0FEBH

0FECH

0FEDH

0FEE^H

SYSC

CMCR

CMDR

WDTH

WDTL

⎯

System control register

Clock monitor control register

Clock monitor data register

Watchdog ID register upper

Watchdog ID register lower

(disabled)

R/W

⎯

11000-11B

--000000B

00000000B

XXXXXXXXB

⎯

ILSR

Input level select register

R/W

-----0--B

0FEFH

to

0FFF^H

⎯

(disabled)

⎯

• R/W access symbols

R/W : Readable / Writable

R

: Read only

: Write only

W

• Initial value symbols

0

1

X

: The initial value of this bit is “0”.

: The initial value of this bit is “1”.

: The initial value of this bit is undefined.

Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.

18

DS07-12625-3E

MB95R203

■ INTERRUPT SOURCE TABLE

Vector table

address

Priority order of

interrupt sources

of the same level

Interrupt

request

number

Bit name of

interrupt level

setting register

Interrupt source

Upper

Lower

(occurring simultaneously)

External interrupt ch.4

External interrupt ch.5

External interrupt ch.2

External interrupt ch.6

External interrupt ch.3

External interrupt ch.7

UART/SIO (transmit)

UART/SIO (receive)

IRQ00

IRQ01

FFFAH

FFF8H

FFFBH

FFF9H

L00 [1 : 0]

L01 [1 : 0]

High

IRQ02

IRQ03

IRQ04

FFF6H

FFF4H

FFF2H

FFF7H

FFF5H

FFF3H

L02 [1 : 0]

L03 [1 : 0]

L04 [1 : 0]

8/16-bit composite timer

ch.0 (Lower)

IRQ05

IRQ06

FFF0H

FFEEH

FFF1H

FFEFH

L05 [1 : 0]

L06 [1 : 0]

8/16-bit composite timer

ch.0 (Upper)

⎯

IRQ07

RQ08

IRQ09

IRQ10

IRQ11

IRQ12

IRQ13

FFECH

FFEAH

FFE8H

FFE6H

FFE4H

FFE2H

FFE0H

FFEDH

FFEBH

FFE9H

FFE7H

FFE5H

FFE3H

FFE1H

L07 [1 : 0]

L08 [1 : 0]

L09 [1 : 0]

L10 [1 : 0]

L11 [1 : 0]

L12 [1 : 0]

L13 [1 : 0]

⎯

FRAM (UDEF, PROT)

⎯

8/16-bit composite timer

ch.1 (Upper)

IRQ14

IRQ15

FFDEH

FFDCH

FFDFH

FFDDH

L14 [1 : 0]

L15 [1 : 0]

⎯

I²C complete/error

I²C stop/AL/wakeup

⎯

IRQ16

FFDAH

FFDBH

L16 [1 : 0]

IRQ17

IRQ18

IRQ19

IRQ20

IRQ21

FFD8H

FFD6H

FFD4H

FFD2H

FFD0H

FFD9H

FFD7H

FFD5H

FFD3H

FFD1H

L17 [1 : 0]

L18 [1 : 0]

L19 [1 : 0]

L20 [1 : 0]

L21 [1 : 0]

8/10-bit A/D converter

Timebase timer

Watch prescaler

⎯

8/16-bit composite timer

ch.1 (Lower)

IRQ22

IRQ23

FFCEH

FFCCH

FFCFH

FFCDH

L22 [1 : 0]

L23 [1 : 0]

Low

FRAM (AREA)

DS07-12625-3E

19

MB95R203

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Max

Parameter

Power supply voltage^*1

Input voltage^*1

Symbol

Unit

Remarks

Min

Vcc

VI1

Vss − 0.3 Vss + 4.0

Vss − 0.3 Vss + 6.0

Vss − 0.3 Vss + 4.0

V

Other than P64, P65*²

P64, P65

VI2

Output voltage^*1

VO

*2

I^OL1

I^OL2

15

Other than P05, P06, P62 and P63

P05, P06, P62 and P63

“L” level maximum output current

⎯

mA

15

Other than P05, P06, P62 and P63

Average output current =

operating current × operating ratio

(1pin)

I^OLAV1

4

“L” level average current

⎯

mA

P05, P06, P62 and P63

Average output current =

operating current × operating ratio

(1pin)

I^OLAV2

12

“L” level total maximum output

current

ΣI^OL

⎯

100

50

Total average output current =

“L” level total average output

current

ΣI^OLAV

mA operating current × operating ratio

(Total of pins)

I^OH1

I^OH2

−15

Other than P05, P06, P62 and P63

“H” level maximum output current

“H” level average current

⎯

mA

P05, P06, P62 and P63

Other than P05, P06, P62 and P63

Average output current =

operating current × operating ratio

(1 pin)

I^OHAV1

−4

−8

⎯

mA

P05, P06, P62 and P63

Average output current =

operating current × operating ratio

(1pin)

I^OHAV2

“H” level total maximum output

current

ΣI^OH

⎯

−100

−50

mA

Total average output current =

mA operating current × operating ratio

(Total of pins)

“H” level total average output

current

ΣI^OHAV

Power consumption

Operating temperature

Storage temperature

Pd

T^A

⎯

320

mW

−20

+ 70

+ 85

°C

Tstg

°C

(Continued)

20

DS07-12625-3E

MB95R203

(Continued)

*1 : The parameter is based on V^SS= 0.0 V.

*2 : V^I1and Vo should not exceed VCC + 0.3 V. VI1 must not exceed the rating voltage.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

DS07-12625-3E

21

MB95R203

2. Recommended Operating Conditions

(VSS = 0.0 V)

Rating

Parameter

Symbol

Vcc

Unit

Remarks

Min

2.7

3.0

2.6

−20

+5

Max

3.6

In normal operating

On-chip debug mode

Power supply voltage

Operating temperature

3.6

V

3.6

Hold condition in STOP mode

Other than on-chip debug mode

On-chip debug mode

+70

+35

°C

T^A

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

22

DS07-12625-3E

MB95R203

3. DC Characteristics

(Vcc = 3.3 V, Vss = 0.0 V, TA = −20 °C to +70 °C)

Value

Parameter Symbol Pin name

Condition

Unit

Remarks

Min

Typ

Max

When CMOS input

level (Hysteresis

input) is selected

V^IH1

P04

*1

0.7 VCC

⎯

VCC + 0.3

V

When CMOS input

level (Hysteresis

input) is selected

V^IH2

P64, P65

*1

0.7 VCC

0.8 V^CC

⎯

VSS + 5.5

VCC + 0.3

V

“H” level

input voltage

P00 to P07,

P12,

P62, P63,

PG1, PG2

V^IHS1

Hysteresis input

V^IHS2

V^IHM

P64, P65

PF2

*1

0.8 VCC

⎯

VSS + 5.5

VCC + 0.3

V

Hysteresis input

⎯

When CMOS input

level (Hysteresis

input) is selected

P04, P64,

P65

V^IL

*1

V^SS− 0.3

⎯

0.3 VCC

V

“L” level

input voltage

P00 to P07,

P12,

P62 to P65,

PG1, PG2

V^ILS

⎯

0.2 VCC

V

Hysteresis input

V^ILM

V^D1

PF2

⎯

VSS − 0.3

⎯

0.3 VCC

V

Open-drain

P64, P65

VSS + 5.5

output applica-

tion voltage

V^D2

PF2, P12

⎯

VSS − 0.3

⎯

0.2 VCC

V

Output pins

other than

P05, P06,

P62 to P65,

PF2, P12

V^OH1

I^OH= −4.0 mA

2.4

⎯

V

“H” level

output voltage

P05, P06,

P62, P63

V^OH2

V^OL1

V^OL2

I^OH= −8.0 mA

I^OL= 4.0 mA

I^OL= 12.0 mA

2.4

⎯

V

Output pins

other than

P05, P06,

P62, P63

0.4

“L” level

output voltage

P05, P06,

P62, P63

⎯

(Continued)

DS07-12625-3E

23

MB95R203

(Vcc = 3.3 V, Vss = 0.0 V, TA = −20 °C to +70 °C)

Value

Parameter Symbol Pin name

Condition

Unit

Remarks

Min

Typ

Max

Input leak

Other than

current (Hi-Z

When pull-up

I^LI

ports

0.0 V < V^I< VCC

−5

⎯

+ 5

μA resistance is

output leak

current)

P64, P65

disabled

Open-drain

output leak

current

0.0 V < V^I<

V^SS+ 5.5 V

I^LIOD

P64, P65

⎯

+ 5

μA

When pull-up

kΩ resistance is

enabled

Pull-up

resistance

P00 to P07,

PG1, PG2

R^PULL

V^I= 0.0 V

f = 1 MHz

25

50

100

Input

capacitance

Other than

Vcc, Vss

C^IN

⎯

5

6

15

9

pF

F^CH= 20 MHz,

F^MP= 10 MHz

Main clock mode

(divided by 2)

mA

ICC

At A/D

mA

⎯

8

12

conversion

FCH = 20 MHz,

F^MP= 10 MHz

Main sleep mode

(divided by 2)

I^CCS

⎯

3

5

mA

FCL = 32 kHz,

F^MPL= 16 kHz

Sub clock mode

(divided by 2)

T^A= +25 °C

Vcc

(External

clock

I^CCL

⎯

30

5

70

40

μA

operation)

FCL = 32 kHz,

F^MPL= 16 kHz

Sub sleep mode

(divided by 2)

T^A= +25 °C

Power supply

current^*2

I^CCLS

μA

FCL = 32 kHz,

Watch mode

Main stop mode

T^A= +25 °C

I^CCT

⎯

3

2

18

⎯

μA

F^CRH= 1 MHz,

F^MP= 1 MHz

Main CR clock

mode

I^CCMCR

mA

Vcc

Sub CR clock

mode

(divided by 2)

T^A= +25 °C

I^CCSCR

80

300

μA

(Continued)

24

DS07-12625-3E

MB95R203

(Continued)

(Vcc = 3.3 V, Vss = 0.0 V, T^A= −20 °C to +70 °C)

Value

Parameter Symbol Pin name

Condition

Unit

Remarks

Min

Typ

Max

F^CH= 10 MHz,

Timebase timer

mode

Vcc

(External

clock

ICCTS

⎯

1

3

mA

μA

T^A= +25 °C

operation)

Sub stop mode

T^A= +25 °C

I^CCH

⎯

1

10

Current

consumption of

internal main CR

oscillator

Power supply

current^*2

I^CRH

0.2

0.3

mA

VCC

At oscillating

100 kHz current

consumption of

internal sub CR

oscillator

I^CRL

⎯

20

72

μA

*1 : P04, P64, P65 can switch the input level to either the “CMOS input level” or “hysteresis input level”.

The switching of the input level can be set by the input level selection register (ILSR) .

*2 : • The power-supply current is determined by the external clock. when Internal CR are selected, the power-

supply current will be a value of adding current consumption of internal CR oscillator (I^CRL) to the specified

value.

• Refer to “4. AC Characteristics (1) Clock Timing” for F^CHand FCL.

• Refer to “4. AC Characteristics (2) Source Clock/Machine Clock” for F^MPand FMPL.

DS07-12625-3E

25

MB95R203

4. AC Characteristics

(1) Clock Timing

(Vcc = 3.3 V, Vss = 0.0 V, T^A= −20 °C to +70 °C)

Value

Sym-

bol

Condi-

tion

Parameter

Pin name

Unit

Remarks

Min

Typ

Max

When the main

oscillation circuit is used

X0, X1

1

⎯

10

MHz

F^CH

X0, X1,

HCLK1,

HCLK2

When the main external

clock is used

1

⎯

20

MHz

When the main internal

CR clock is used

(3.0 V ≤ V^CC≤ 3.6 V,

+ 5 °C ≤ T^A≤ + 35 °C)

F^CRH

⎯

0.95

1

1.05

Clock frequency

When the sub oscillation

circuit is used

⎯

32.768

100

⎯

MHz

kHz

ns

F^CL

X0A, X1A

When the sub external

clock is used

When the sub internal

CR clock is used

F^CRL

⎯

50

200

1000

When the main

oscillation circuit is used

X0, X1

100

⎯

t^HCYL

X0, X1,

HCLK1,

HCLK2

Clock cycle time

When the main external

clock is used

50

⎯

20

⎯

30.5

⎯

1000

⎯

ns

t^LCYLX0A, X1A

μs When using sub clock

t^WH1

t^WL1

X0,

HCLK1,

HCLK2

When the external clock

is used, the duty ratio

should range between

40% and 60%

⎯

ns

μs

ns

Input clock pulse

width

tWH2

t^WL2

t^CR

X0A

⎯

15.2

⎯

X0, X0A,

HCLK1,

HCLK2

Input clock rise

time and fall time

When the external clock

is used

⎯

5

t^CF

When the main-internal

CR clock is used

t^CRHWK

⎯

10

μs

Internal CR

oscillation start time

When the sub-internal

CR clock is used

t^CRLWK

26

DS07-12625-3E

MB95R203

t

HCYL

t

WH1

tWL1

t

CR

tCF

0.8 VCC 0.8 VCC

X0, HCLK1, HCLK2

0.2 VCC

• Figure of main clock input port external connection

When using a crystal or

Ceramic oscillator

When using external clock

X0

X1

X0

X1

Open

F^CH

tLCYL

tWH2

tWL2

tCR

tCF

0.8 VCC 0.8 VCC

X0A

0.2 VCC

• Figure of sub clock input port external connection

When using a crystal

or

Ceramic oscillator

When using external clock

X0A

X1A

F^CL

X0A

X1A

Open

F^CL

DS07-12625-3E

27

MB95R203

(2) Source Clock/Machine Clock

(Vcc = 3.3 V, Vss = 0.0 V, T^A= −20 °C to +70 °C)

Value

Typ

Parameter

Symbol

Unit

Remarks

name

Min

Max

When using main external clock

100

⎯

2000

ns Min : F^CH= 20 MHz, divided by 2

Max : F^CH= 1 MHz, divided by 2

Source clock

cycle time^*1

(Clock before

division)

When using main CR oscillation clock

F^CRH= 1 MHz

⎯

1

⎯

μs

t^SCLK

⎯

When using sub oscillation clock

μs

61

20

F^CL= 32.768 kHz, divided by 2

When using sub oscillation clock

F^CRL= 100 kHz, divided by 2

μs

0.5

⎯

1

10

⎯

MHz When using main oscillation clock

MHz When using main CR oscillation clock

kHz When using sub oscillation clock

kHz When using sub CR clock

F^SP

Source clock

frequency

⎯

16.384

50

F^SPL

When using main oscillation clock

ns Min : F^SP= 10 MHz, no division

Max : F^SP= 0.5 MHz, divided by 16

100

1

⎯

32000

16

When using main CR clock

μs Min : F^SP= 1 MHz, no division

Max : F^SP= 1 MHz, divided by 16

Machine clock

cycle time^*2

(Minimum

instruction

execution time)

tMCLK

When using sub oscillation clock

μs Min : F^SPL= 16.384 kHz, no division

Max : F^SPL= 16.384 kHz, divided by 16

61

20

976.5

320

When using sub CR clock

μs Min : F^SPL= 50 kHz, no division

Max : F^SPL= 50 kHz, divided by 16

0.031

0.0625

1.024

3.125

⎯

10

1

MHz When using main oscillation clock

MHz When using main CR clock

F^MP

Machine clock

frequency

16.384 kHz When using sub oscillation clock

F^MPL

50

kHz When using sub CR clock

When using main oscillation clock

ns Min : F^SP= 10 MHz, divided by 3

Max : F^SP= 0.5 MHz, divided by 48

300

3

⎯

96000

When using main CR clock

μs Min : F^SP=1 MHz, divided by 3

Max : F^SP=1 MHz, divided by 48

FRAM clock

cycle time^*3

(Minimum

instruction

execution time)

48

t^FCLK

When using sub oscillation clock

183

60

2929.7 μs Min : F^SPL= 16.384 kHz, divided by 3

Max : F^SPL= 16.384 kHz, divided by 48

When using sub CR clock

μs Min : F^SPL= 50 kHz, divided by 3

Max : F^SPL= 50 kHz, divided by 48

960

(Continued)

28

DS07-12625-3E

MB95R203

(Continued)

Value

Typ

⎯

name

Parameter

Symbol

F^FCLK

Unit

Remarks

Min

0.010

0.0208

0.341

1.042

Max

3.3

MHz When using main oscillation clock

⎯

0.3333 MHz When using main CR clock

5.461 kHz When using sub oscillation clock

16.667 kHz When using sub CR clock

FRAM clock

frequency

⎯

F^FCLKL

⎯

*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) .

This source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) ,

and it becomes the machine clock. Further, the source clock can be selected as follows.

• Main clock divided by 2

• Main CR clock

• Sub clock divided by 2

• Sub CR clock divided by 2

*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.

• Source clock (no division)

• Source clock divided by 4

• Source clock divided by 8

• Source clock divided by 16

*3 : The clock in case of operating code on FRAM, or Read/Write access to FRAM. Its value is machine clock

divided by 3.

• Outline of clock generation block

Divided

by 2

F

CH

(main oscillation)

Division

Circuit

x 1

x 1/4

x 1/8

F

CRH

(Internal main

SCLK

(source clock)

MCLK

(machine clock)

CR clock)

Divided

by 2

F

CL

x 1/16

(sub oscillation)

F

CRL

(Internal sub

Divided

by 2

FCLK

Divided

(FRAM clock)

CR clock)

by 3

Clock mode select bit

(SYCC2:RCS1, RCS0)

DS07-12625-3E

29

MB95R203

• Operating voltage - Operating frequency (When TA = − 20 °C to + 70 °C)

3.6

3.3

A/D converter operation range

3.0

2.7

2.4

16 kHz

3 MHz

10 MHz

Source clock frequency (F^SP)

30

DS07-12625-3E

MB95R203

(3) External Reset

Parameter

(Vcc = 3.3 V, Vss = 0.0 V, T^A= −20 °C to +70 °C)

Value

Symbol

Unit

Remarks

Min

Max

*1

2 tMCLK

⎯

ns

At normal operating

At stop mode, sub clock mode,

sub sleep mode, and watch

mode

RST “L” level pulse

width

Oscillation time of

t^RSTL

⎯

μs

oscillator^*2+ 100

100

At time-base timer mode

*1 : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

*2 : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation

time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of

μs and several ms. In the external clock, the oscillation time is 0 ms.

• At normal operating

tRSTL

RST

0.2 VCC

• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on

tRSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal

operating

clock

100 μs

Oscillation stabilization wait time

Oscillation time of

oscillator

Execute instruction

Internal reset

DS07-12625-3E

31

MB95R203

(4) Power-on Reset

Parameter

(Vss = 0.0 V, T^A= −20 °C to +70 °C)

Value

Symbol

Conditions

Unit

Remarks

Min

Max

Power supply rising time

Power supply cutoff time

t^R

⎯

50

ms

Waiting time until

power-on

t^OFF

1

⎯

t

R

tOFF

2.5 V

0.2 V

V

CC

Note: Sudden change of power supply voltage may activate the power-on reset function. When changing power

supply voltages during operation, set the slope of rising within 30 mV/ms as shown below.

VCC

Limiting the slope of rising within

30 mV/ms is recommended.

2.6 V

Hold Condition in stop mode

VSS

32

DS07-12625-3E

MB95R203

(5) Peripheral Input Timing

Parameter

(Vcc = 3.3 V, Vss = 0.0 V, T^A= −20 °C to +70 °C)

Value

Unit

Symbol

Pin name

Min

Max

Peripheral input “H” pulse

Peripheral input “L” pulse

t^ILIH

t^IHIL

2 t^MCLK*

2 tMCLK*

⎯

ns

INT02 to INT07,

EC0, EC1

⎯

* : Refer to “ (2) Source Clock/Machine Clock” for t^MCLK.

tILIH

tIHIL

0.8 VCC 0.8 VCC

0.2 VCC

INT02 to INT07,

EC0, EC1

DS07-12625-3E

33

MB95R203

(6) UART/SIO, Serial I/O Timing

(Vcc = 3.3 V, Vss = 0.0 V, T^A= −20 °C to +70 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Min

Max

⎯

Serial clock cycle time

UCK ↓ → UO time

t^SCYC

t^SLOV

t^IVSH

t^SHIX

t^SHSL

t^SLSH

t^SLOV

t^IVSH

t^SHIX

UCK

UCK, UO

UCK,UI

UCK, UI

UCK

4 t^MCLK*

−190

ns

Internal clock

operation output pin :

C^L= 80 pF + 1 TTL.

+190

⎯

Valid UI → UCK ↑

2 tMCLK*

4 t^MCLK*

4 tMCLK*

0

UCK ↑→ valid UI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

UCK ↓ → UO time

⎯

UCK

⎯

External clock

operation output pin :

C^L= 80 pF + 1 TTL.

UCK, UO

UCK, UI

190

⎯

Valid UI → UCK ↑

2 tMCLK*

UCK ↑→ valid UI hold time

⎯

* : Refer to “ (2) Source Clock/Machine Clock” for details on t^MCLK.

• Internal shift clock mode

tSCYC

2.4 V

UCK

UO

UI

0.8 V

tSLOV

2.4 V

0.8 V

tIVSH

tSHIX

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

• External shift clock mode

UCK

tSLSH

tSHSL

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

tSLOV

UO

UI

2.4 V

0.8 V

tIVSH

tSHIX

0.8 V^CC0.8 VCC

0.2 VCC 0.2 VCC

34

DS07-12625-3E

MB95R203

(7) I²C Timing

(Vcc = 3.3 V, Vss = 0.0 V, T^A= −20 °C to +70 °C)

Value

name

Standard-

mode

Parameter

Symbol

Conditions

Fast-mode

Unit

Min

Max

Min

Max

SCL clock frequency

t^SCYC

SCL

0

100

0

400

kHz

(Repeat) Start condition hold time

SDA ↓ → SCL ↓

SCL

SDA

t^HD;STA

4.0

⎯

0.6

⎯

μs

SCL clock “L” width

SCL clock “H” width

t^LOW

t^HIGH

SCL

4.7

4.0

⎯

1.3

0.6

⎯

μs

(Repeat) Start condition setup time

SCL ↑ → SDA ↓

SCL

SDA

t^SU;STA

t^HD;DAT

t^SU;DAT

t^SU;STO

t^BUF

4.7

0

⎯

3.45^*2

⎯

0.6

0

⎯

0.9^*3

⎯

μs

R = 1.7 kΩ,

C = 50 pF^*1

SCL

SDA

Data hold time SCL ↓ → SDA ↓ ↑

Data setup time SDA ↓ ↑ → SCL ↑

SCL

SDA

0.25

4.0

4.7

0.1

0.6

1.3

Stop condition setup time

SCL ↑ → SDA ↓

SCL

SDA

⎯

Bus free time between stop

condition and start condition

SCL

SDA

⎯

*1 : R, C : Pull-up resistance and load capacitance of the SCL and SDA lines.

*2 : The maximum value of t^HD;DATis applicable only if the devicedoesnotextend the “L” width (tLOW) of the SCL signal.

*3 : A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement tSU;DAT ≥ 250

ns must then be met.

t^WAKEUP

SDA

tHD;STA

tHD;DAT

tBUF

tLOW

tHIGH

SCL

tSU;STO

tHD;STA

tSU;DAT

tSU;STA

DS07-12625-3E

35

MB95R203

(Vcc = 3.3 V, Vss = 0.0 V, TA = −20 °C to +70 °C)

Value^*2

name

Condi-

tions

Parameter

SCL clock

Symbol

t^LOW

t^HIGH

Unit

Remarks

Min

Max

(2 + nm / 2) tMCLK

− 20

SCL

⎯

ns Master mode

“L” width

SCL clock

“H” width

(nm / 2) t^MCLK−

(nm / 2) tMCLK +

ns Master mode

Master mode

20

maximum value is

applied when m, n

ns = 1, 8.

Start condition

hold time

SCL

SDA

(−1 + nm / 2)

t^MCLK− 20

(−1 + nm / 2)

tMCLK + 20

t^HD;STA

Otherwise, the min-

imum value is ap-

plid.

Stop condition

setup time

SCL

SDA

(1 + nm / 2) tMCLK (1 + nm / 2) tMCLK

t^SU;STO

t^SU;STA

ns Master mode

− 20

+ 20

Start condition

setup time

SCL

SDA

(1 + nm / 2) tMCLK (1 + nm / 2) tMCLK

ns Master mode

ns

− 20

+ 20

Bus free time

between stop

condition and

start condition

SCL

SDA

(2 nm + 4) tMCLK

− 20

t^BUF

⎯

SCL

SDA

Data hold time

Data setup time

t^HD;DAT

3 t^MCLK− 20

⎯

ns Master mode

R = 1.7 kΩ,

C = 50 pF^*1

Master mode

When assuming

that “L” of SCL is

not extended, the

SCL

SDA

(−2 + nm / 2)

t^MCLK− 20

(−1 + nm / 2)

tMCLK + 20

minimum value is

applied to first bit of

t^SU;DAT

ns

continuous data.

Otherwise, the

maximum value is

applied.

Minimum value is

applied to interrupt

at 9th SCL↓.

Maximum value is

applied to interrupt

at 8th SCL↓.

Setup time

between

cleaning

interrupt and

SCL rising

(nm / 2) t^MCLK− (1 + nm / 2) tMCLK

t^SU;INT

SCL

ns

20

+ 20

SCL clock

“L” width

t^LOW

t^HIGH

SCL

4 tMCLK − 20

⎯

ns At reception

SCL clock

“H” width

Undetected when 1

ns tMCLK is used at re-

ception

Start condition

detection

SCL

SDA

t^HD;STA

4 t^MCLK− 20

⎯

(Continued)

36

DS07-12625-3E

MB95R203

(Continued)

(Vcc = 3.3 V, Vss = 0.0 V, T^A= −20 °C to +70 °C)

Value^*2

name

Condi-

tions

Parameter

Symbol

Unit

Remarks

Min

Max

Stop condition

detection

SCL

SDA

Undetected when 1 t^M-

CLK is used at reception

t^SU;STO

t^SU;STA

t^BUF

4 tMCLK − 20

⎯

ns

Restart condition

detection condition

SCL

SDA

Undetected when 1 t^M-

CLK is used at reception

2 t^MCLK− 20

⎯

SCL

SDA

Bus free time

ns During reception

SCL

SDA

In slave transmission

mode

Data hold time

Data setup time

Data hold time

Data setup time

t^HD;DAT

t^SU;DAT

t^HD;DAT

t^SU;DAT

ns

R = 1.7 kΩ,

C = 50 pF^*1

SCL

SDA

tLOW − 3 tMCLK −

In slave transmission

mode

ns

20

SCL

SDA

0

ns During reception

SCL

SDA

t^MCLK− 20

Oscillation sta-

bilization wait

time + 2 t^MCLK−

20

SDA ↓ → SCL ↑

(when using wakeup

function)

SCL

SDA

t^WAKEUP

⎯

ns

*1 : R, C : Pull-up resistance and load capacitance of the SCL and SDA lines.

*2 : • Refer to “ (2) Source Clock/Machine Clock” for details on t^MCLK.

• m is the CS4 and CS3 bits (bit 4 and bit 3) of the I²C clock control register (ICCR0) .

• n is the CS2 to CS0 bits (bit 2 to bit0) of the I²C clock control register (ICCR0) .

• The actual I²C timing is determined by the machine (tMCLK) and the values of m and n configured in bits

CS4 to CS0 of the I²C clock control register (ICCR0) .

• Standard-mode :

m and n can be set in the range : 0.9 MHz < t^MCLK(machine clock) < 10 MHz.

The machine clock to be used is determined by the settings of m and n as follows.

(m, n) = (1, 8)

: 0.9 MHz < t^MCLK≤ 1 MHz

: 0.9 MHz < t^MCLK≤ 2 MHz

: 0.9 MHz < t^MCLK≤ 4 MHz

: 0.9 MHz < t^MCLK≤ 1 MHz

(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4)

(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8)

(m, n) = (1, 98)

• Fast-mode :

m and n can be set in the range : 3.3 MHz < t^MCLK(machine clock) < 10 MHz.

The machine clock to be used is determined by the settings of m and n as follows.

(m, n) = (1, 8)

(m, n) = (1, 22) , (5, 4)

(m, n) = (6, 4)

: 3.3 MHz < t^MCLK≤ 4 MHz

: 3.3 MHz < t^MCLK≤ 8 MHz

: 3.3 MHz < t^MCLK≤ 10 MHz

DS07-12625-3E

37

MB95R203

(8) Low Voltage Detection

Parameter

(V^SS= 0.0 V, TA = −20 °C to +70 °C) )

Value

Typ

2.8

2.7

100

2.9

2.8

100

⎯

Symbol

Unit

Remarks

Min

2.7

2.6

70

Max

2.9

2.8

⎯

Release voltage

V1^DL+

V1^DL−

V1^HYS

V2^DL+

V2^DL−

V2^HYS

V^off

V

At power-supply rise

At power-supply fall

Low voltage

detection reset

Detection voltage

Hysteresis width

Release voltage

Detection voltage

Hysteresis width

mV

V

2.8

2.7

70

3.0

2.9

⎯

At power-supply rise

At power-supply fall

FRAM power

supply monitor

V

mV

V

Power-supply start voltage

Power-supply end voltage

⎯

2.2

⎯

V^on

3.3

⎯

V

Slope of power supply that

reset release signal generates

0.3

⎯

200

⎯

μs

Power-supply voltage

change time

t^r

Slope of power supply that

μs reset release signal generates

within rating (V1^DL+, V2DL+)

(at power supply rise)

⎯

Slope of power supply that

μs

0.3

⎯

reset detection signal generates

Power-supply voltage change

time

t^f

Slope of power supply that

μs reset detection signal generates

within rating (V1^DL−, V2DL−)

(at power supply fall)

200

Reset release delay time

Reset detection delay time

t^d1

t^d2

⎯

300

20

μs

38

DS07-12625-3E

MB95R203

V

CC

V

on

off

time

t

f

tr

V

DL+

DL-

VHYS

V

Internal reset

signal

time

t

d1

t

d2

DS07-12625-3E

39

MB95R203

5. A/D Converter

(1) A/D Converter Electrical Characteristics

(Vcc = 2.7 V to 3.6 V, Vss = 0.0 V, T^A= −20 °C to +70 °C)

Value

Parameter

Resolution

Symbol

Unit

Remarks

Min

⎯

Typ

⎯

Max

10

bit

Total error

−3.0

−2.5

⎯

+3.0

+2.5

LSB

⎯

Linearity error

⎯

Differential linear

error

−1.9

⎯

+1.9

LSB

V

Zero transition

voltage

V^OT

VSS − 1.5 LSB VSS + 0.5 LSB VSS + 2.5 LSB

VCC − 3.5 LSB VCC − 1.5 LSB VCC + 0.5 LSB

Full-scale transition

voltage

V^FST

V

Compare time

⎯

0.6

0.4

⎯

140

μs

3.0 V ≤ Vcc ≤ 3.6 V

μs At external impedance

< 1.8 kΩ

Sampling time

⎯

∞

Analog input current

Analog input voltage

I^AIN

−0.3

⎯

+0.3

μA

V^AIN

VSS

VCC

V

40

DS07-12625-3E

MB95R203

(2) Notes on Using A/D Converter

• About the external impedance of analog input and its sampling time

A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship

between the external impedance and minimum sampling time and either adjust the register value and operating

frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also,

if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.

• Analog input equivalent circuit

Analog input

Comparator

R

C

During sampling : ON

2.7 V ≤ Vcc ≤ 3.6 V : R =: 1.7 kΩ (Max) , C =: 14.5 pF (Max)

Note : The values are reference values.

• The relationship between external impedance and minimum sampling time.

[External impedance = 0 kΩ to 20 kΩ]

[External impedance = 0 kΩ to 100 kΩ]

100

90

80

70

60

50

40

30

20

10

0

20

18

16

14

12

10

8

6

4

2

0

5

10 15 20 25 30 35 40

0

1

2

3

4

Minimum sampling time [μs]

• About errors

|V^CC− VSS| becomes smaller, values of relative errors grow larger.

DS07-12625-3E

41

MB95R203

(3) Definition of A/D Converter Terms

• Resolution

The level of analog variation that can be distinguished by the A/D converter.

When the number of bits is 10, analog voltage can be divided into 2¹⁰= 1024.

• Linearity error (unit : LSB)

The deviation between the value along a straight line connecting the zero transition point

(“00 0000 0000” ←→ “00 0000 0001”) of a device and the full-scale transition point

(“11 1111 1111” ←→ “11 1111 1110”) compared with the actual conversion values obtained.

• Differential linear error (Unit : LSB)

Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.

• Total error (unit : LSB)

Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,

linearity error, quantum error, and noise.

Ideal I/O characteristics

Total error

VFST

3FF

3FE

3FD

3FF

3FE

3FD

Actual conversion

characteristic

1.5 LSB

{1 LSB × (N − 1) + 0.5 LSB}

004

003

002

001

004

003

002

001

VNT

V^OT

Actual conversion

characteristic

1 LSB

0.5 LSB

Ideal characteristics

VSS

VCC

VSS

VCC

Analog input

Total error of

digital output N

V^CC− VSS

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

=

1 LSB =

(V)

[LSB]

1024

1 LSB

N

: A/D converter digital output value

V^NT: A voltage at which digital output transits from (N - 1) to N

(Continued)

42

DS07-12625-3E

MB95R203

(Continued)

Full-scale transition error

Zero transition error

Ideal

004

characteristics

Actual conversion

characteristic

3FF

3FE

3FD

3FC

Actual conversion

characteristic

003

002

001

Ideal

characteristics

VFST

(measurement

value)

Actual conversion

characteristic

Actual conversion

characteristic

VOT (measurement value)

VSS

VCC

VSS

VCC

Analog input

Linearity error

Differential linear error

Actual conversion

characteristic

Ideal characteristics

3FF

3FE

3FD

N+1

N

Actual conversion

characteristic

{1 LSB × N + VOT}

V (N+1) T

V^FST

(measure-

ment value)

V^NT

004

003

002

001

N-1

N-2

VNT

Actual conversion

characteristic

Actual conversion

characteristic

Ideal characteristics

VOT (measurement value)

VSS

VCC

VSS

VCC

Analog input

Linearity error in

digital output N

V^NT− {1 LSB × N + VOT}

V (N + 1) T − VNT

Differential linear error

In digital output N

=

− 1

1 LSB

N

: A/D converter digital output value

V^NT: A voltage at which digital output transits from (N - 1) to N.

V^OT(Ideal value) = VSS + 0.5 LSB [V]

V^FST(Ideal value) = VCC − 2.0 LSB [V]

DS07-12625-3E

43

MB95R203

6. FRAM Characteristics

Parameter

Value

Typ

Unit

Remarks

Min

Max

Number of read/write cycle

10¹⁰

10¹¹

⎯

cycle

44

DS07-12625-3E

MB95R203

■ EXAMPLE CHARACTERISTICS

• Power supply current and temperature

ICC − VCC

ICC − TA

TA = + 25 °C, FMP = 2, 3, 8, 10 MHz (divided by 2)

Main clock mode, at external clock operating

VCC = 3.6 V, FMP = 10 MHz (divided by 2)

Main clock mode, at external clock operating

10

8

6

10 MHz

8 MHz

4

4 MHz

2 MHz

2

0

-40

0

+40

+80

2.5

3

3.5

4

V^CC[V]

T

A

[°C]

I^CCS− TA

I^CCS− VCC

TA = + 25 °C, FMP = 2, 3, 8, 10 MHz (divided by 2)

VCC = 3.6 V, FMP = 10 MHz(divided by 2)

Main sleep mode, at external clock operating

10

8

6

4

2

0

6

4

10 MHz

8 MHz

2

4 MHz

2 MHz

0

-40

0

+40

+80

2.5

3

3.5

4

T

A

[°C]

I^CCL− TA

VCC = 3.6 V, FMPL = 16 kHz (divided by 2)

Sub clock mode, at external clock operating

80

V^CC[V]

I^CCL− VCC

TA = + 25 °C, FMPL = 16 kHz (divided by 2)

Sub clock mode, at external clock operating

80

60

40

20

0

60

40

20

0

2.5

3

3.5

4

-40

0

+40

+80

VCC [V]

T^A[°C]

(Continued)

DS07-12625-3E

45

MB95R203

ICCLS − VCC

I^CCLS− TA

TA = + 25 °C, FMPL = 16 kHz (divided by 2)

VCC = 3.6 V, FMPL = 16 kHz (divided by 2)

Sub sleep mode, at external clock operating

50

40

30

20

10

0

50

40

30

20

10

0

-40

0

+40

+80

3

3.5

2.5

4

V

CC [V]

TA [°C]

I^CCT− VCC

I^CCT

TA = + 25 °C, FMPL = 16 kHz (divided by 2)

VCC = 3.6 V, FMPL = 16 kHz (divided by 2)

Clock mode, at external clock operating

20

15

10

5

15

10

5

0

-40

0

+40

+80

3

3.5

2.5

4

V

CC [V]

T

A

[°C]

I^CTS− VCC

I^CTS− TA

TA = + 25 °C, FMP = 2, 4, 8, 10 MHz (divided by 2)

VCC = 3.6 V, FMP = 10 kHz (divided by 2)

Time-base timer mode, at external clock operating

2

1.5

1

1.5

1

10MHz

8MHz

0.5

0

0.5

4MHz

2MHz

0

-40

0

+40

+80

VCC [V]

TA [°C]

(Continued)

46

DS07-12625-3E

MB95R203

(Continued)

ICCH − VCC

I^CCH− TA

TA = + 25 °C, FMPL = (stop)

VCC = 3.6 V, FMPL = (stop)

Sub stop mode, at external clock stopping

20

15

10

5

20

15

10

5

0

3

3.5

2.5

4

-40

0

+40

+80

V

CC [V]

TA [°C]

I^CCMCR− VCC

I^CCMCR− TA

VCC = 3.6 V, FMP = 1 MHz (No divided)

Main clock mode, at internal main CR clock operating Main clock mode, at internal main CR clock operating

TA = + 25 °C, FMP = 1 MHz (No divided)

2

1.5

1

1.5

1

0.5

0

0.5

0

3

3.5

2.5

4

-40

0

+40

+80

VCC [V]

T^A[°C]

I^CCSCR− VCC

I^CCSCR− TA

TA = + 25 °C, FMPL = 50 kHz (divided by 2)

VCC = 3.6 V, FMPL = 50 kHz (divided by 2)

Sub clock mode, at internal sub CR clock operating Sub clock mode, at internal sub CR clock operating

200

150

100

50

200

150

100

50

0

3

3.5

2.5

4

-40

0

+40

+80

VCC [V]

TA [°C]

DS07-12625-3E

47

MB95R203

• Input voltage

VIHI1, VIH2, VIHS1, VIHS2, VIHM − VCC and

V^IL, VILS, VILM − VCC

TA = + 25 °C

3.5

3

2.5

2

VIH

VIL

1.5

1

0.5

0

2.5

3

3.5

4

V^CC[V]

48

DS07-12625-3E

MB95R203

• Output voltage

(VCC − VOH1) − IOH

TA = + 25 °C

V^OL1− IOL

TA = + 25 °C

1.000

0.800

0.600

0.400

0.200

0.000

1.000

0.800

0.600

0.400

0.200

0.000

VCC

2.7 V

3.0 V

3.3 V

3.6 V

2.7 V

3.0 V

3.3 V

3.6 V

0

2

4

6

8

10 12

0

-2

-4

-6

-8

-10

IOL [mA]

I^OH[mA]

(V^CC− VOH2) − IOH

TA = + 25 °C

V^OL2− IOL

TA = + 25 °C

1.000

0.800

0.600

0.400

0.200

0.000

1.000

0.800

0.600

0.400

0.200

0.000

VCC

2.7 V

3.0 V

3.3 V

3.6 V

2.7 V

3.0 V

3.3 V

3.6 V

0

2

4

6

8

10 12

0

-2

-4

-6

-8

-10

I^OL[mA]

I^OH[mA]

DS07-12625-3E

49

MB95R203

• Pull-up

RPULL − VCC

TA = + 25 °C

80

60

40

20

0

2.5

3

3.5

4

V^CC[V]

50

DS07-12625-3E

MB95R203

■ ORDERING INFORMATION

Part number

Package

Remarks

24-pin plastic SDIP

(DIP-24P-M07)

MB95R203P-G-SH-JNE2

MB95R203PF-G-JNE2

20-pin plastic SOP

(FPT-20P-M09)

DS07-12625-3E

51

MB95R203

■ PACKAGE DIMENSIONS

24-pin plastic DIP

Lead pitch

1.778 mm

6.40 mm × 22.86 mm

Plastic mold

Package width

package length

×

Sealing method

Mounting height

4.80 mm Max

(DIP-24P-M07)

24-pin plastic DIP

(DIP-24P-M07)

Note 1) Pins width and pins thickness include plating thickness.

Note 2) Pins width do not include tie bar cutting remainder.

Note 3) # : These dimensions do not include resin protrusion.

#22.86±0.10(.900±.004)

24

13

BTM E-MARK

INDEX

6.40±0.10

(.252±.004)

7.62(.300)

1

12

TYP.

0.50(.020)

MIN

4.80(.189)MAX

0.25 ^+0.10

.010^+.004

–0.04

.118 ^+.008

–0.30

–.012

3.00^+0.20

–.002

0.43 ^+0.09

.017^+.004

–0.04

1.778(.070)

1.00±0.10

(.039±.004)

–.002

Dimensions in mm (inches).

Note: The values in parentheses are reference values

C

2008 FUJITSU MICROELECTRONICS LIMITED D24066S-c-1-1

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

(Continued)

52

DS07-12625-3E

MB95R203

(Continued)

20-pin plastic SOP

Lead pitch

1.27 mm

7.50 mm × 12.70 mm

Gullwing

Package width

package length

×

Lead shape

Lead bend

direction

Normal bend

Plastic mold

Sealing method

Mounting height

2.65 mm Max

(FPT-20P-M09)

20-pin plastic SOP

(FPT-20P-M09)

Note 1) Pins width and pins thickness include plating thickness.

Note 2) Pins width do not include tie bar cutting remainder.

Note 3) # : These dimensions do not include resin protrusion.

+0.07

0.25

–0.02

#12.70±0.10(.500±.004)

.010 ^+.003

–

.001

20

11

BTM E-MARK

+0.40

0.20

#7.50±0.10

(.295±.004)

10.2

–

.402 ^+.016

–.008

INDEX

Details of "A" part

+0.13

0.17

+.005

.007

2.52

.099

–

(Mounting height)

–

"A"

1

10

0.40 ^+0.09

.016 ^+.004

–

0.05

0~8°

1.27(.050)

M

0.25(.010)

–

.002

0.80^+0.47

.031^+.019

–

0.30

0.20±0.10

(.008±.004)

(Stand off)

–.012

0.10(.004)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2008 FUJITSU MICROELECTRONICS LIMITED F20030S-c-1-1

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

DS07-12625-3E

53

MB95R203

■ MAIN CHANGES IN THIS EDITION

Page

Section

Change Results

Preliminary Data Sheet → Data Sheet

⎯

■ PRODUCT OVERVIEW

Corrected number of read/write cycles for FRAM.

10¹¹times →

4

(Min)10¹⁰times (Typ)10¹¹times

■ I/O CIRCUIT TYPE

■ NOTES ON DEBUG

■ I/O MAP

Corrected the remarks of Type G.

CMOS input → CMOS output

9

Corrected the address.

F555^H→ F554H

12

Corrected the register abbreviation and the register name for

address 000B^H.

15

WTCR → WPCR

Watch timer control register →

Watch prescaler control register

Changed the register name for address 0F89^H, 0F8AH, and

0F8B^Hto (disabled).

17

24

32

■ ELECTRICAL CHARACTERISTICS

3. DC Characteristics

Added “T^A= + 25 °C” to the condition for “Power supply

current (I^CCLS)”.

4. AC Characteristics

(4) Power-on Reset

Corrected the voltage for “Hold Condition in stop mode”.

2.3 V → 2.6 V

45 to 50 ■ EXAMPLE CHARACTERISTICS

Added the section.

The vertical lines marked in the left side of the page show the changes.

54

DS07-12625-3E

MB95R203

MEMO

DS07-12625-3E

55

MB95R203

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,

Shinjuku-ku, Tokyo 163-0722, Japan

Tel: +81-3-5322-3329

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

Asia Pacific

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://www.fmal.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.

Rm. 3102, Bund Center, No.222 Yan An Road (E),

Shanghai 200002, China

Tel : +86-21-6146-3688 Fax : +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

Korea

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road,

Tsimshatsui, Kowloon, Hong Kong

Tel : +852-2377-0226 Fax : +852-2376-3269

http://cn.fujitsu.com/fmc/en/

FUJITSU MICROELECTRONICS KOREA LTD.

206 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fmk/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating

the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or

other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to

the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear

facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon

system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Sales Promotion Department


型号：	MB95R203PF-G-JNE2
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontrollers 8位微控制器专用微控制器
文件：	总56页 (文件大小：302K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB95R203PF-G-JNE2 [FUJITSU]

相关型号：

MB961

MB961F

MB961RF

MB96300

MB96310

MB96320

MB96330

MB96336RSAPMC-GSE2

MB96336RWAPMC-GSE2

MB96336YSAPMC-GSE2

MB96336YWAPMC-GSE2

MB96338RSAPMC-GSE2