MB96338RSAPMC-GSE2_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

FME-MB96330 rev 2

16-bit Proprietary Microcontroller

CMOS

F²MC-16FX MB96330 Series

MB96336/338^*1

MB96F338^*1

■ DESCRIPTION

MB96330 series is based on Fujitsu’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like

performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy

migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation

include signiﬁcantly improved performance - even at the same operation frequency, reduced power consumption

and faster start-up time.

For highest processing speed at optimized power consumption an internal PLL can be selected to supply the

CPU with up to 48MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction

cycle time of 20.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit signiﬁcantly

reduces emission peaks in the frequency spectrum. The emitted power is minimized by the on-chip voltage

regulator that reduces the internal CPU voltage. A ﬂexible clock tree allows to select suitable operation frequencies

for peripheral resources independent of the CPU speed.

*1: These devices are under development. All information in this datasheet is preliminary for the devices under

development.

2008-2-7

MB96330 Series

FME-MB96330 rev 2

2

2008-2-7

MB96330 Series

FME-MB96330 rev 2

■ FEATURES

Feature

Description

Technology

• 0.18µm CMOS

• F2MC-16FX CPU

• Up to 48 MHz internal, 20.8 ns instruction cycle time

• Optimized instruction set for controller applications (bit, byte, word and long-word

data types; 23 different addressing modes; barrel shift; variety of pointers)

CPU

• 8-byte instruction execution queue

• Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available

• On-chip PLL clock multiplier (x1..25, x1 when PLL stop)

• 3-16 MHz external quartz clock

• Up to 48 MHz external clock

• 32-100 kHz subsystem quartz clock

• 100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection,

watchdog

System clock

• Clock source selectable from main- and subclock oscillator (part number suffix “W”)

and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals.

• Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes,

Stop mode)

• Clock modulator

• Internal voltage regulator supports reduced internal MCU voltage, offering low EMI

and low power consumption figures

On-chip voltage regula-

tor

Low voltage reset

Code Security

• Reset is generated when supply voltage is below minimum.

• Protects ROM content from unintended read-out

• Replaces ROM content

Memory Patch Function

DMA

• Can also be used to implement embedded debug support

• Automatic transfer function independent of CPU, can be assigned freely to resources

• Fast Interrupt processing

Interrupts

Timers

• 8 programmable priority levels

• Non-Maskable Interrupt (NMI)

• Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit

Sub clock timer)

• Watchdog Timer

2008-2-7

3

MB96330 Series

FME-MB96330 rev 2

Feature

Description

• Supports CAN protocol version 2.0 part A and B

• ISO16845 certified

• Bit rates up to 1 Mbit/s

• 32 message objects

CAN

• Each message object has its own identifier mask

• Programmable FIFO mode (concatenation of message objects)

• Maskable interrupt

• Disabled Automatic Retransmission mode for Time Triggered CAN applications

• Programmable loop-back mode for self-test operation

• Full duplex USARTs (SCI/LIN)

• Wide range of baud rate settings using a dedicated reload timer

• Special synchronous options for adapting to different synchronous serial protocols

• LIN functionality working either as master or slave LIN device

• Up to 400 kbit/s

USART

I2C

• Master and Slave functionality, 8-bit and 10-bit addressing

• SAR-type

• 10-bit resolution

A/D converter

• Signals interrupt on conversion end, single conversion mode, continuous conversion

mode, stop conversion mode, activation by software, external trigger or reload timer

• 16-bit wide

• Prescaler with 1/2¹, 1/2², 1/2³, 1/2⁴, 1/2⁵, 1/2⁶of peripheral clock frequency

• Event count function

Reload Timers

Free Running Timers

Input Capture Units

• Signals an interrupt on overflow, supports timer clear upon match with Output

Compare (0, 4), Prescaler with 1, 1/2¹, 1/2², 1/2³, 1/2⁴, 1/2⁵, 1/2⁶, 1/2⁷,1/2⁸of

peripheral clock frequency

• 16-bit wide

• Signals an interrupt upon external event

• Rising edge, falling edge or rising & falling edge sensitive

• 16-bit wide

Output Compare Units • Signals an interrupt when a match with 16-bit I/O Timer occurs

• A pair of compare registers can be used to generate an output signal.

• 16-bit down counter, cycle and duty setting registers

• Interrupt at trigger, counter borrow and/or duty match

• PWM operation and one-shot operation

Programmable Pulse

Generator

• Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and

Reload timer overflow as clock input

• Can be triggered by software or reload timer

4

2008-2-7

MB96330 Series

FME-MB96330 rev 2

Feature

Description

• Can be clocked either from sub oscillator (devices with part number suffix “W”), main

oscillator or from the RC oscillator

• Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock

calibration)

Real Time Clock

• Read/write accessible second/minute/hour registers

• Can signal interrupts every half second/second/minute/hour/day

• Internal clock divider and prescaler provide exact 1s clock

• Edge sensitive or level sensitive

• Interrupt mask and pending bit per channel

• Each available CAN channel RX has an external interrupt for wake-up

• Selected USART channels SIN have an external interrupt for wake-up

• Disabled after reset

External Interrupts

• Once enabled, can not be disabled other than by reset.

• Level high or level low sensitive

Non Maskable Interrupt

• Pin shared with external interrupt 0.

• 8-bit or 16-bit bidirectional data

• Up to 24-bit addresses

• 6 chip select signals

• Multiplexed address/data lines

External bus interface

• Non-multiplexed address/data lines

• Wait state request

• External bus master possible

• Timing programmable

• Monitors an external voltage and generates an interrupt in case of a voltage lower or

higher than the defined thresholds

Alarm comparators

• Threshold voltages defined externally or generated internally

• Status is readable, interrupts can be masked separately

• Virtually all external pins can be used as general purpose I/O

• All push-pull outputs (except when used as I2C SDA/SCL line)

• Bit-wise programmable as input/output or peripheral signal

• Bit-wise programmable input enable

I/O Ports

Package

• Bit-wise programmable input levels (Automotive / CMOS-Schmitt trigger / TTL)

• Bit-wise programmable pull-up resistor

• Bit-wise programmable output driving strength for EMI optimization

• 144-pin plastic LQFP M08

2008-2-7

5

MB96330 Series

FME-MB96330 rev 2

Feature

Description

• Supports automatic programming, Embedded Algorithm^TM*1

• Write/Erase/Erase-Suspend/Resume commands

• A flag indicating completion of the algorithm

• Number of erase cycles: 10,000 times

• Data retention time: 20 years

Flash Memory

• Erase can be performed on each sector individually

• Sector protection

• Flash Security feature to protect the content of the Flash

• Low voltage detection during Flash erase

• USB function (corresponds to USB Full Speed)

• USB Mini-HOST function

USB

• Supports up to 6 endpoints

^*1: Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

6

2008-2-7

MB96330 Series

FME-MB96330 rev 2

■ PRODUCT LINEUP

Features

MB96V300

Evaluation sample

MB9633xY/R / MB96F33xY/R

MB96F33xU

Flash product: MB96F33x

Product type

Mask ROM product: MB9633x

LVD persistently on / Single clock devices

LVD can be disabled / Single clock devices

LVD persistently on / Dual clock devices

LVD can be disabled / Dual clock devices

USB / LVD can be disabled / Single clock devices

USB / LVD can be disabled / Dual clock devices

YS

RS

YW

RW

US

NA

UW

Flash/

ROM

RAM

16kB

MB96336Y ^*1, MB96336R^*1

ROM/Flash

288kB

memory emulation

by external RAM,

92kB internal RAM

MB96F338Y ^*1, MB96F338R^*1

MB96338Y ^*1, MB96338R^*1

544kB

32kB

MB96F338U ^*1

Package

BGA416

FPT-144P-M08

DMA

USART

I2C

16 channels

10 channels

8 channels

2 channels

40 channels

A/D Converter

40 channels

yes

36 channels

A/D Converter Reference

Voltage switch

No

6 channels + 1

channel (for PPG)

16-bit Reload Timer

4 channels + 1 channel (for PPG)

4 channels

16-bit Free-Running

Timer

16-bit Output Compare

16-bit Input Capture

12 channels

10 channels

16-bit Programmable

Pulse Generator

20 channels

3 channels

CAN Interface

USB

5 channels

No

1 channel

External Interrupts

Non-Maskable Interrupt

Real Time Clock

16 channels

1 channel

1

2008-2-7

7

MB96330 Series

FME-MB96330 rev 2

Features

I/O Ports

MB96V300

MB9633xY/R / MB96F33xY/R

MB96F33xU

122 for part number with sufﬁx

"W", 124 for part number with

sufﬁx "S"

118 for part number with sufﬁx

"W", 120 for part number with

sufﬁx "S"

136

Alarm comparator

External bus interface

Chip select

2 channels

Yes

6 signals

2 channels

Yes

Clock output function

Low voltage reset

On-chip RC-oscillator

Yes

*1: These devices are under development. All information in this datasheet is preliminary for the devices under

development.

8

2008-2-7

MB96330 Series

FME-MB96330 rev 2

■ BLOCK DIAGRAM

Block diagram of MB96(F)33xY/R

AD00 ... AD15

CKOT0, CKOT0_R, CKOT1, CKOT1_R

A0 ... A23

CKOTX0, CKOTX1, CKOTX1_R

ALE

RDX

X0, X1

X0A, X1A ¹⁾

WRLX/WRX, WRHX

HRQ

RSTX

MD0...MD2

HAKX

NMI, NMI_R

RDY

ECLK

LBX, UBX

CS0 ... CS5, CS0_R ...CS5_R

Memory Patch

Flash

Clock &

Mode Controller

Interrupt

Controller

External Bus

Interface

16FX

CPU

Unit

Memory A

16FX Core Bus (CLKB)

DMA

Controller

10ch

Voltage

Regulator

Peripheral

Bus Bridge

Peripheral

Bus Bridge

Watchdog

RAM

Boot ROM

SDA0, SDA1

SCL0, SCL1

VCC

VSS

C

I2C

2 ch.

AV^CC

AVSS

AVRH

CAN

Interface

3 ch.

TX0 ... TX2, TX2_R

RX0 ... RX2, RX2_R

10-bit ADC

40 ch.

AVRL

AN0 ... AN39

ADTG, ADTG_R

TIN0 ... TIN3

TIN0_R, TIN2_R

TIN3_R

TOT0 ... TOT3

TOT0_R, TOT2_R

TOT3_R

16-bit Reload

Timer

4 ch.

SIN0...SIN3, SIN5, SIN9

SIN2_R, SIN7_R ... SIN9_R

SOT0...SOT3, SOT5, SOT9

SOT2_R, SOT7_R ... SOT9_R

SCK0...SCK3, SCK5

SCK2_R, SCK7_R ... SCK9_R

I/O Timer 0

ICU 0-3

FRCK0

IN0 ... IN3

USART

8 ch.

OUT0 ... OUT3

OCU 0-3

FRCK1

IN4 ... IN7

I/O Timer 1

ICU 4-7

OCU 4-7

ALARM0

ALARM1

Alarm

Comparator

2 ch.

IN4_R, IN5_R

OUT4 ... OUT7

OUT6_R, OUT7_R

I/O Timer 2

ICU 8,9

FRCK2_R

IN8, IN9

TTG0 ... TTG15, TTG18

16-bit PPG

20 ch.

OCU 8,9

OUT8, OUT9

TTG8_R ... TTG11_R, TTG16_R ... TTG19_R

PPG0 ... PPG19

I/O Timer 3

OCU 10,11

RLT6

PPG0_R ... PPG11_R, PPG16R ... PPG19_R

OUT10_R, OUT11

INT0...INT15

INT0_R...INT15_R

INT3_R1, INT5_R1

External

Interrupt

Real Time

Clock

WOT

¹⁾Available only on devices with suffix , “W”

2008-2-7

9

MB96330 Series

FME-MB96330 rev 2

Block diagram of MB96(F)33xU

AD00 ... AD15

CKOT0, CKOT0_R, CKOT1, CKOT1_R

A0 ... A23

CKOTX0, CKOTX1, CKOTX1_R

ALE

RDX

X0, X1

X0A, X1A ¹⁾

WRLX/WRX, WRHX

HRQ

RSTX

MD0...MD2

HAKX

NMI, NMI_R

RDY

ECLK

LBX, UBX

CS0 ... CS5, CS0_R ...CS5_R

Memory Patch

Flash

Clock &

Mode Controller

Interrupt

Controller

External Bus

Interface

16FX

CPU

Unit

Memory A

16FX Core Bus (CLKB)

DMA

Controller

10ch

Voltage

Regulator

Peripheral

Bus Bridge

Peripheral

Bus Bridge

Peripheral

Bus Bridge

Watchdog

RAM

Boot ROM

SDA0, SDA1

SCL0, SCL1

VCC

VSS

C

I2C

2 ch.

AV^CC

AVSS

AVRH

UDP

UDM

HCONX

USB

10-bit ADC

36 ch.

AVRL

AN0 ... AN35

ADTG, ADTG_R

VCC3

TIN0 ... TIN3

TIN0_R, TIN2_R

TIN3_R

TOT0 ... TOT3

TOT0_R, TOT2_R

TOT3_R

CAN

Interface

3 ch.

TX0 ... TX2, TX2_R

RX0 ... RX2, RX2_R

16-bit Reload

Timer

4 ch.

SIN0...SIN3, SIN5, SIN9

SIN2_R, SIN7_R ... SIN9_R

SOT0...SOT3, SOT5, SOT9

SOT2_R, SOT7_R ... SOT9_R

SCK0...SCK3, SCK5

SCK2_R, SCK7_R ... SCK9_R

I/O Timer 0

ICU 0-3

FRCK0

IN0 ... IN3

USART

8 ch.

OUT0 ... OUT3

OCU 0-3

FRCK1

IN4 ... IN7

I/O Timer 1

ICU 4-7

OCU 4-7

ALARM0

ALARM1

Alarm

Comparator

2 ch.

IN4_R, IN5_R

OUT4 ... OUT7

OUT6_R, OUT7_R

I/O Timer 2

ICU 8,9

FRCK2_R

IN8, IN9

TTG0 ... TTG15, TTG18

16-bit PPG

20 ch.

OCU 8,9

OUT8, OUT9

TTG8_R ... TTG11_R, TTG16_R ... TTG19_R

PPG0 ... PPG19

I/O Timer 3

OCU 10,11

RLT6

PPG0_R ... PPG11_R, PPG16R ... PPG19_R

OUT10_R, OUT11

INT0...INT15

INT0_R...INT15_R

INT3_R1, INT5_R1

External

Interrupt

Real Time

Clock

WOT

¹⁾Available only on devices with suffix , “W”

10

2008-2-7

MB96330 Series

FME-MB96330 rev 2

■ PIN ASSIGNMENTS

Pin assignment of M96F338Y/R (FPT-144P-M08)

108

109

106

104

102

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

72

107

105

103

101

Vcc

Vss

P00_1/AD01/INT9/SOT7_R/TTG9_R

P00_2/AD02/INT10/SIN7_R/TTG10_R

P00_3/AD03/INT11/SCK8_R/TTG11_R

P00_4/AD04/INT12/SOT8_R/PPG8_R

P00_5/AD05/INT13/SIN8_R/PPG9_R

P00_6/AD06/INT14/PPG10_R

P00_7/AD07/INT15/PPG11_R

P01_0/AD08/TIN1/CKOT1/TTG16_R

P01_1/AD09/TOT1/CKOTX1/TTG17_R

P01_2/AD10/SIN3/INT11_R/TTG18_R

P01_3/AD11/SOT3/TTG19_R

P01_4/AD12/SCK3/PPG16_R

P01_5/AD13/SIN2_R/INT7_R/PPG17_R

P01_6/AD14/SOT2_R/PPG18_R

P01_7/AD15/SCK2_R/PPG19_R

P02_0/A16/PPG12/CKOT1_R

P02_1/A17/PPG13

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

P15_7/AN39

P15_6/AN38

P15_5/AN37

P15_4/AN36

P15_3/AN35

P15_2/AN34

P15_1/AN33

P15_0/AN32

P14_7/AN31

P14_6/AN30

P14_5/AN29

P14_4/AN28

P14_3/AN27

P14_2/AN26

P14_1/AN25

P14_0/AN24

LQFP - 144

P07_7/AN23/INT7/SIN9_R

P07_6/AN22/INT6/SOT9_R

P02_2/A18/PPG14/CKOT0_R

P02_3/A19/PPG15

P07_5/AN21/INT5/SCK9_R

P07_4/AN20/INT4

Package code (mold)

FPT-144P-M08

P02_4/A20/IN0/TTG0/TTG8

P07_3/AN19/INT3

P02_5/A21/IN1/TTG1/TTG9/ADTG_R

P02_6/A22/IN2/TTG2/TTG10

P02_7/A23/IN3/TTG3/TTG11

P03_0/ALE/IN4/TTG4/TTG12/TOT0_R

P03_1/RDX/IN5/TTG5/TTG13/TOT2_R

P03_2/WR(L)X/INT10_R/RX2

P03_3/WRHX/TX2

P07_2/AN18/INT2

P07_1/AN17/INT1

P07_0/AN16/INT0/NMI

AVss

AVRL

AVRH

AVcc

P03_4/HRQ/OUT4

43

42

P03_5/HAKX/OUT5

P06_7/AN7/PPG7

P06_6/AN6/PPG6

P06_5/AN5/PPG5/CS5_R

P06_4/AN4/PPG4/CS4_R

P06_3/AN3/PPG3/CS3_R

P06_2/AN2/PPG2/CS2_R

Vss

P03_6/RDY/OUT6

P03_7/ECLK/OUT7

P11_4/OUT6_R/A0

P11_5/OUT7_R/A1

P11_6/IN4_R/A2

Vcc

41

40

39

38

37

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

1)

Devices with sufﬁx W: X0A/X1A

Devices with sufﬁx S: P04_0, P04_1

(FPT-144P-M08)

2008-2-7

11

MB96330 Series

FME-MB96330 rev 2

Pin assignment of MB96F338U (FPT-144P-M08) USB device

108

109

106

104

102

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

72

107

105

103

101

Vcc

Vss

P00_1/AD01/INT9/SOT7_R/TTG9_R

P00_2/AD02/INT10/SIN7_R/TTG10_R

P00_3/AD03/INT11/SCK8_R/TTG11_R

P00_4/AD04/INT12/SOT8_R/PPG8_R

P00_5/AD05/INT13/SIN8_R/PPG9_R

P00_6/AD06/INT14/PPG10_R

P00_7/AD07/INT15/PPG11_R

P01_0/AD08/TIN1/CKOT1/TTG16_R

P01_1/AD09/TOT1/CKOTX1/TTG17_R

P01_2/AD10/SIN3/INT11_R/TTG18_R

P01_3/AD11/SOT3/TTG19_R

P01_4/AD12/SCK3/PPG16_R

P01_5/AD13/SIN2_R/INT7_R/PPG17_R

P01_6/AD14/SOT2_R/PPG18_R

P01_7/AD15/SCK2_R/PPG19_R

P02_0/A16/PPG12/CKOT1_R

P02_1/A17/PPG13

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

UDM

UDP

Vcc3

HCONX

P15_3/AN35

P15_2/AN34

P15_1/AN33

P15_0/AN32

P14_7/AN31

P14_6/AN30

P14_5/AN29

P14_4/AN28

P14_3/AN27

P14_2/AN26

P14_1/AN25

P14_0/AN24

LQFP - 144

P07_7/AN23/INT7/SIN9_R

P07_6/AN22/INT6/SOT9_R

P02_2/A18/PPG14/CKOT0_R

P02_3/A19/PPG15

P07_5/AN21/INT5/SCK9_R

P07_4/AN20/INT4

Package code (mold)

FPT-144P-M08

P02_4/A20/IN0/TTG0/TTG8

P07_3/AN19/INT3

P02_5/A21/IN1/TTG1/TTG9/ADTG_R

P02_6/A22/IN2/TTG2/TTG10

P02_7/A23/IN3/TTG3/TTG11

P03_0/ALE/IN4/TTG4/TTG12/TOT0_R

P03_1/RDX/IN5/TTG5/TTG13/TOT2_R

P03_2/WR(L)X/INT10_R/RX2

P03_3/WRHX/TX2

P07_2/AN18/INT2

P07_1/AN17/INT1

P07_0/AN16/INT0/NMI

AVss

AVRL

AVRH

AVcc

P03_4/HRQ/OUT4

43

42

P03_5/HAKX/OUT5

P06_7/AN7/PPG7

P06_6/AN6/PPG6

P06_5/AN5/PPG5/CS5_R

P06_4/AN4/PPG4/CS4_R

P06_3/AN3/PPG3/CS3_R

P06_2/AN2/PPG2/CS2_R

Vss

P03_6/RDY/OUT6

P03_7/ECLK/OUT7

P11_4/OUT6_R/A0

P11_5/OUT7_R/A1

P11_6/IN4_R/A2

Vcc

41

40

39

38

37

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

1)

Devices with sufﬁx W: X0A/X1A

Devices with sufﬁx S: P04_0, P04_1

(FPT-144P-M08)

12

2008-2-7

MB96330 Series

FME-MB96330 rev 2

■ PIN FUNCTION DESCRIPTION

Pin Function description (1 / 3)

Pin name

ADn

Feature

Description

External bus interface (non multiplexed mode) data input/

output. External bus interface (multiplexed mode) address

output and data input/output

External bus

ADTG

ADTG_R

ALARMn

ALE

ADC

A/D converter trigger input

Relocated A/D converter trigger input

Alarm Comparator n input

Alarm comparator

External bus

ADC

External bus Address Latch Enable output

External bus non-multiplexed address output

A/D converter channel n input

An

ANn

AV^CC

Supply

Analog circuits power supply

AVRH

AVRL

ADC

A/D converter high reference voltage input

A/D converter low reference voltage input

Analog circuits power supply

ADC

AVSS

Supply

C

Voltage regulator

Clock output function

External bus

Free Running Timer

External bus

USB

Internally regulated power supply stabilization capacitor pin

Clock Output function n output

CKOTn

CKOTn_R

CKOTXn

CKOTXn_R

ECLK

Relocated Clock Output function n output

Clock Output function n inverted output

Relocated Clock Output function n inverted output

External bus clock output

CSn

External bus chip select n output

Relocated External bus chip select n output

Free Running Timer n input

CSn_R

FRCKn

FRCKn_R

HAKX

HCONX

HRQ

Relocated Free Running Timer n input

External bus Hold Acknowledge

USB connection to host or hub

External bus

ICU

External bus Hold Request

INn

Input Capture Unit n input

INn_R

INTn

ICU

Relocated Input Capture Unit n input

External Interrupt n input

External Interrupt

INTn_R

Relocated External Interrupt n input

2008-2-7

13

MB96330 Series

FME-MB96330 rev 2

Pin Function description (2 / 3)

Pin name

Feature

Description

LBX

MDn

External bus

Core

External Bus Interface Lower Byte select strobe output

Input pins for specifying the operating mode.

Non-Maskable Interrupt input

NMI

External Interrupt

OCU

NMI_R

OUTn

OUTn_R

Pxx_n

PPGn

PPGn_R

RDX

Relocated Non-Maskable Interrupt input

Output Compare Unit n waveform output

Relocated Output Compare Unit n waveform output

General purpose IO

OCU

GPIO

PPG

Programmable Pulse Generator n output

Relocated Programmable Pulse Generator n output

External bus interface read strobe output

External bus interface external wait state request input

Reset input

PPG

External bus

Core

RDY

RSTX

RXn

CAN

CAN interface n RX input

RXn_R

SCKn

SCKn_R

SCLn

CAN

Relocated CAN interface n RX input

USART n serial clock input/output

USART

I2C

Relocated USART n serial clock input/output

I2C interface n clock I/O input/output

I2C interface n serial data I/O input/output

USART n serial data input

SDAn

SINn

I2C

USART

Reload Timer

PPG

SINn_R

SOTn

SOTn_R

TINn

Relocated USART n serial data input

USART n serial data output

Relocated USART n serial data output

Reload Timer n event input

TINn_R

TOTn

Relocated Reload Timer n event input

Reload Timer n output

TOTn_R

TTGn

Relocated Reload Timer n output

Programmable Pulse Generator n trigger input

Relocated Programmable Pulse Generator n trigger input

CAN interface n TX output

TTGn_R

TXn

PPG

CAN

TXn_R

CAN

Relocated CAN interface n TX output

14

2008-2-7

MB96330 Series

FME-MB96330 rev 2

Pin Function description (3 / 3)

Pin name

Feature

Description

UBX

UDM

UDP

VCC

External bus

USB

External Bus Interface Upper Byte select strobe output

USB minus

USB

USB plus

Supply

RTC

Power supply

VCC3

USB Power supply

VSS

Power supply

WOT

WRHX

WRLX/WRX

X0

Real Timer clock output

External bus

Clock

External bus High byte write strobe output

External bus Low byte / Word write strobe output

Oscillator input

X0A

Clock

Subclock Oscillator input (only for devices with sufﬁx "W")

Oscillator output

X1

Clock

X1A

Clock

Subclock Oscillator output (only for devices with sufﬁx "W")

2008-2-7

15

MB96330 Series

FME-MB96330 rev 2

16

2008-2-7

MB96330 Series

■ PIN CIRCUIT TYPE

Pin no.

FME-MB96330 rev 2

FPT-144P-M08

Circuit type¹⁾

MB96(F)33xY/R

MB96(F)33xU (USB device)

1

2

Supply

F

3 to 21

22 to 25

26 to 35

36, 37

38 to 43

44

H

N

I

Supply

I

Supply

G

45

46 to 47

48 to 67

68

Supply

I

O

69

Supply (3.3V)

P

70, 71

72, 73

74 to 76

77, 78

79

Supply

C

A

Supply

B²⁾

80, 81

82

H³⁾

E

83 to 107

108, 109

110 to 143

144

H

Supply

H

Supply

¹⁾About each circuit type, please refer to IO circuit type below

²⁾Devices with sufﬁx ”W”

³⁾Devices without sufﬁx ”W”

2008-2-7

17

MB96330 Series

FME-MB96330 rev 2

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

High-speed oscillation circuit:

• Programmable between oscillation mode (ex-

ternal crystal or resonator connected to X0/X1

pins) and Fast external Clock Input (FCI) mode

(external clock connected to X0 pin)

X1

R

• Programmable feedback resistor = approx.

2 * 0.5 MΩ. Feedback resistor is grounded in

the center when the oscillator is disabled or in

FCI mode

0

1

Xout

MRFBE

FCI

R

X0

FCI or osc disable

B

Low-speed oscillation circuit:

• Programmable feedback resistor = approx.

2 * 5 MΩ. Feedback resistor is grounded in the

center when the oscillator is disabled

Xout

X1A

R

SRFBE

R

X0A

osc disable

C

E

• Mask ROM and EVA device:

CMOS Hysteresis input pin

• Flash device:

R

Hysteresis

inputs

CMOS input pin

• CMOS Hysteresis input pin

• Pull-up resistor value: approx. 50 kΩ

Pull-up

Resistor

R

Hysteresis

inputs

18

2008-2-7

MB96330 Series

FME-MB96330 rev 2

Type

Circuit

Remarks

F

• Power supply input protection circuit

G

• A/D converter ref+ (AVRH) power supply input

pin with protection circuit

ANE

AVR

• Flash devices do not have a protection circuit

against VCC for pins AVRH

ANE

H

• CMOS level output (programmable IOL = 5mA,

IOH = -5mA and IOL = 2mA, IOH = -2mA)

• 2 different CMOS hysteresis inputs with input

shutdown function

• Automotive input with input shutdown function

• TTL input with input shutdown function

• Programmable pull-up resistor: 50kΩ approx.

pull-up control

Pout

Nout

R

Hysteresis input

Standby control

for input shutdown

Hysteresis input

Automotive input

TTL input

Standby control

for input shutdown

Standby control

for input shutdown

Standby control

for input shutdown

2008-2-7

19

MB96330 Series

FME-MB96330 rev 2

Type

Circuit

Remarks

I

• CMOS level output (programmable IOL = 5mA,

IOH = -5mA and IOL = 2mA, IOH = -2mA)

• 2 different CMOS hysteresis inputs with input

shutdown function

Pull-up control

Pout

Nout

• Automotive input with input shutdown function

• TTL input with input shutdown function.

• Programmable pull-up resistor: 50kΩ approx.

• Analog input

R

Hysteresis input

Standby control

for input shutdown

Hysteresis input

Automotive input

Standby control

for input shutdown

Standby control

for input shutdown

TTL input

Standby control

for input shutdown

Analog input

N

• CMOS level output (I^OL= 3mA, IOH = -3mA)

• 2 different CMOS hysteresis inputs with input

shutdown function

• Automotive input with input shutdown function

• TTL input with input shutdown function

• Programmable pull-up resistor: 50kΩ approx.

pull-up control

Pout

Nout

R

Hysteresis input

Standby control

for input shutdown

Standby control

for input shutdown

Hysteresis input

Automotive input

TTL input

Standby control

for input shutdown

Standby control

for input shutdown

20

2008-2-7

MB96330 Series

FME-MB96330 rev 2

Type

Circuit

Remarks

O

HCONX

• Available only for device with sufﬁx “U”

pull-up control

Pout (Always disabled)

Nout

R

Hysteresis input

Automotive inputs

Standby control

for input shutdown

Standby control

for input shutdown

Standby control

for input shutdown

TTL input

Standby control

for input shutdown

Analog input

P

USB IO cell: UDP and UDM

• Available only for device with sufﬁx “U”

D+ Input

D- Input

D+

D-

Differential

Input

Direction

D+ output

D- output

2008-2-7

21

MB96330 Series

FME-MB96330 rev 2

22

2008-2-7

MB96330 Series

FME-MB96330 rev 2

2008-2-7

23

MB96330 Series

FME-MB96330 rev 2

24

2008-2-7

MB96330 Series

FME-MB96330 rev 2

■ MEMORY MAP

MB96V300B

MB96(F)3xx

FF:FFFFH

DE:0000H

USER ROM /

Emulation ROM

*4

External Bus

Boot-ROM

Reserved

10:0000H

0F:E000H

Boot-ROM

Reserved

0E:0000H

02:0000H

External RAM

Reserved

Internal RAM

RAMEND1^*2

Internal RAM

bank 1

RAM availability de-

pending on the device

RAMSTART1²

bank 1

01:0000H

00:8000H

Reserved

ROM/RAM MIRROR

Internal RAM

bank 0

RAMSTART0^*2

Internal RAM

bank 0

Reserved

External Bus end

*2

address

RAMSTART0^*3

00:0C00H

External Bus

Peripherals

00:0380H

00:0180H

00:0100H

00:00F0H

00:0000H

GPR^*1

DMA

GPR^*1

DMA

External Bus

Peripheral

External Bus

Peripheral

*1: Unused GPR banks can be used as RAM area

*2: For External Bus end address and RAMSTART/END addresses, please refer to the table on the next page.

*3: For EVA device, RAMSTART0 depends on the conﬁguration of the emulated device.

*4: For details about USER ROM area, see the USER ROM MEMORY MAP on the following pages.

The External Bus area and DMA area are only available if the device contains the corresponding resource.

The available RAM and ROM area depends on the device.

2008-2-7

25

MB96330 Series

FME-MB96330 rev 2

■ RAMSTART/END AND EXTERNAL BUS END ADDRESSES

Bank 0

Bank 1 External Bus

Devices

RAMSTART0 RAMSTART1 RAMEND1

RAM size RAM size end address

MB96336

16kB

28kB

-

00:11FFH

00:4240H

00:1240H

-

MB96F338,

MB96338

4kB

01:8000H

01:8FFFH

26

2008-2-7

MB96330 Series

FME-MB96330 rev 2

■ USER ROM MEMORY MAP FOR FLASH DEVICES

MB96F338Y

MB96F338R

MB96F338U

Flash size

544kByte

Alternative mode Flash memory

CPU address

mode address

FF:FFFFH

FF:0000H

FE:FFFFH

FE:0000H

FD:FFFFH

FD:0000H

FC:FFFFH

FC:0000H

FB:FFFFH

FB:0000H

FA:FFFFH

FA:0000H

F9:FFFFH

F9:0000H

F8:FFFFH

F8:0000H

F7:FFFFH

F7:0000H

F6:FFFFH

F6:0000H

F5:FFFFH

F5:0000H

F4:FFFFH

F4:0000H

F3:FFFFH

F3:0000H

F2:FFFFH

F2:0000H

F1:FFFFH

F1:0000H

F0:FFFFH

F0:0000H

E0:FFFFH

3F:FFFFH

3F:0000H

3E:FFFFH

3E:0000H

3D:FFFFH

3D:0000H

3C:FFFFH

3C:0000H

3B:FFFFH

3B:0000H

3A:FFFFH

3A:0000H

39:FFFFH

39:0000H

38:FFFFH

38:0000H

37:FFFFH

37:0000H

36:FFFFH

36:0000H

35:FFFFH

35:0000H

34:FFFFH

34:0000H

33:FFFFH

33:0000H

32:FFFFH

32:0000H

31:FFFFH

31:0000H

30:FFFFH

30:0000H

S39 - 64K

S38 - 64K

S37 - 64K

S36 - 64K

S35 - 64K

S34 - 64K

S33 - 64K

S32 - 64K

Flash A

External bus

Reserved

E0:0000H

DF:FFFFH

DF:8000H

DF:7FFFH

DF:6000H

DF:5FFFH

DF:4000H

DF:3FFFH

DF:2000H

DF:1FFFH

DF:0000H

DE:FFFFH

1F:7FFFH

1F:6000H

1F:5FFFH

1F:4000H

1F:3FFFH

1F:2000H

1F:1FFFH

1F:0000H

SA3 - 8K

SA2 - 8K

SA1 - 8K

SA0 - 8K ^*1

Flash A

Reserved

DE:0000H

*1:SectorSA0containstheROMConﬁgurationBlockRCBAatCPUaddress

DF:0000H - DF:007FH

2008-2-7

27

MB96330 Series

FME-MB96330 rev 2

■ USER ROM MEMORY MAP FOR MASK ROM DEVICES

MB96336Y

MB96336R

MB96338Y

MB96338R

ROM size

288kByte

ROM size

544kByte

CPU address

FF:FFFFH

FF:0000H

FE:FFFFH

FE:0000H

FD:FFFFH

256K ROM

FD:0000H

FC:FFFFH

FC:0000H

FB:FFFFH

512K ROM

FB:0000H

FA:FFFFH

FA:0000H

F9:FFFFH

Reserved

F9:0000H

F8:FFFFH

F8:0000H

F7:FFFFH

External bus

E0:0000H

DF:FFFFH

Reserved

32K ROM

Reserved

32K ROM

DF:8000H

DF:7FFFH

DF:0080H

DF:007FH

DF:0000H

ROM conﬁguration

block RCB

ROM conﬁguration

block RCB

DE:FFFFH

Reserved

DE:0000H

28

2008-2-7

MB96330 Series

FME-MB96330 rev 2

■ SERIAL PROGRAMMING COMMUNICATION INTERFACE

USART pins for Flash serial programming (MD[2:0] = 010)

MB96F33x

Pin number

Normal function

USART Number

LQFP-144

85

86

87

88

89

90

26

27

28

SIN0

SOT0

SCK0

SIN1

USART0

USART1

USART2

SOT1

SCK1

SIN2

SOT2

SCK2

Note: For handshaking pin, please use for this device the default port P00_1 on pin 110. If any other pin is

required, please contact the Flash programmer device vendor.

2008-2-7

29

MB96330 Series

FME-MB96330 rev 2

■ I/O MAP

I/O map MB96(F)33x (1 / 41)

Abbreviation

8-bit access

Abbreviation

Access

Address

Register

16-bit access

000000H

000001H

000002H

000003H

000004H

000005H

000006H

000007H

000008H

000009H

00000AH

00000BH

00000CH

00000DH

00000EH

00000FH

000010H

000011H

I/O Port P00 - Port Data Register

I/O Port P01 - Port Data Register

I/O Port P02 - Port Data Register

I/O Port P03 - Port Data Register

I/O Port P04 - Port Data Register

I/O Port P05 - Port Data Register

I/O Port P06 - Port Data Register

I/O Port P07 - Port Data Register

I/O Port P08 - Port Data Register

I/O Port P09 - Port Data Register

I/O Port P10 - Port Data Register

I/O Port P11 - Port Data Register

I/O Port P12 - Port Data Register

I/O Port P13 - Port Data Register

I/O Port P14 - Port Data Register

I/O Port P15 - Port Data Register

Reserved

PDR00

PDR01

PDR02

PDR03

PDR04

PDR05

PDR06

PDR07

PDR08

PDR09

PDR10

PDR11

PDR12

PDR13

PDR14

PDR15

RW

-

I/O Port P17 - Port Data Register

PDR17

RW

000012H-

000017H

Reserved

-

000018H

000019H

00001AH

00001BH

00001CH

00001DH

00001EH

00001FH

000020H

ADC0 - Control Status register Low

ADC0 - Control Status register High

ADC0 - Data Register Low

ADCSL

ADCSH

ADCRL

ADCRH

ADCS

ADCR

ADSR

RW

R

ADC0 - Data Register High

ADC0 - Setting Register

R

RW

-

ADC0 - Setting Register

ADC0 - Extended Conﬁguration Register

Reserved

ADECR

FRT0 - Data register of free-running timer

TCDT0

RW

30

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (2 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000021H

000022H

FRT0 - Data register of free-running timer

RW

FRT0 - Control status register of free-running timer

Low

TCCSL0

TCCSH0

TCCS0

RW

FRT0 - Control status register of free-running timer

High

000023H

000024H

000025H

FRT1 - Data register of free-running timer

TCDT1

TCCS1

RW

FRT1 - Control status register of free-running timer

Low

000026H

000027H

TCCSL1

TCCSH1

RW

FRT1 - Control status register of free-running timer

High

000028H

000029H

00002AH

00002BH

00002CH

00002DH

00002EH

00002FH

000030H

000031H

000032H

000033H

000034H

000035H

000036H

000037H

000038H

000039H

00003AH

00003BH

OCU0 - Output Compare Control Status

OCU1 - Output Compare Control Status

OCU0 - Compare Register

OCS0

OCS1

RW

OCCP0

OCCP1

OCU0 - Compare Register

OCU1 - Compare Register

OCU2 - Output Compare Control Status

OCU3 - Output Compare Control Status

OCU2 - Compare Register

OCS2

OCS3

OCCP2

OCCP3

OCU2 - Compare Register

OCU3 - Compare Register

OCU4 - Output Compare Control Status

OCU5 - Output Compare Control Status

OCU4 - Compare Register

OCS4

OCS5

OCCP4

OCCP5

OCU4 - Compare Register

OCU5 - Compare Register

OCU6 - Output Compare Control Status

OCU7 - Output Compare Control Status

OCS6

OCS7

2008-2-7

31

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (3 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

00003CH

00003DH

00003EH

00003FH

000040H

000041H

000042H

000043H

000044H

000045H

000046H

000047H

000048H

000049H

00004AH

00004BH

00004CH

00004DH

00004EH

00004FH

000050H

000051H

000052H

000053H

000054H

000055H

000056H

000057H

000058H

OCU6 - Compare Register

OCCP6

RW

R

OCU7 - Compare Register

OCCP7

OCU7 - Compare Register

ICU0/ICU1 - Control Status Register

ICU0/ICU1 - Edge register

ICS01

ICE01

ICU0 - Capture Register Low

ICU0 - Capture Register High

ICU1 - Capture Register Low

ICU1 - Capture Register High

ICU2/ICU3 - Control Status Register

ICU2/ICU3 - Edge register

IPCPL0

IPCPH0

IPCPL1

IPCPH1

ICS23

IPCP0

IPCP1

R

RW

R

ICE23

ICU2 - Capture Register Low

ICU2 - Capture Register High

ICU3 - Capture Register Low

ICU3 - Capture Register High

ICU4/ICU5 - Control Status Register

ICU4/ICU5 - Edge register

IPCPL2

IPCPH2

IPCPL3

IPCPH3

ICS45

IPCP2

IPCP3

R

RW

R

ICE45

ICU4 - Capture Register Low

ICU4 - Capture Register High

ICU5 - Capture Register Low

ICU5 - Capture Register High

ICU6/ICU7 - Control Status Register

ICU6/ICU7 - Edge register

IPCPL4

IPCPH4

IPCPL5

IPCPH5

ICS67

IPCP4

IPCP5

R

RW

R

ICE67

ICU6 - Capture Register Low

ICU6 - Capture Register High

ICU7 - Capture Register Low

ICU7 - Capture Register High

EXTINT0 - External Interrupt Enable Register

IPCPL6

IPCPH6

IPCPL7

IPCPH7

ENIR0

IPCP6

IPCP7

R

RW

32

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (4 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

EXTINT0 - External Interrupt Interrupt request

Register

000059H

EIRR0

RW

00005AH

00005BH

00005CH

EXTINT0 - External Interrupt Level Select Low

EXTINT0 - External Interrupt Level Select High

EXTINT1 - External Interrupt Enable Register

ELVRL0

ELVRH0

ENIR1

ELVR0

RW

EXTINT1 - External Interrupt Interrupt request

Register

00005DH

EIRR1

RW

00005EH

00005FH

000060H

000061H

000062H

000063H

000064H

000065H

000066H

000067H

000068H

000069H

00006AH

00006BH

00006CH

00006DH

00006EH

2008-2-7

EXTINT1 - External Interrupt Level Select Low

EXTINT1 - External Interrupt Level Select High

RLT0 - Timer Control Status Register Low

RLT0 - Timer Control Status Register High

RLT0 - Reload Register - for writing

RLT0 - Reload Register - for reading

RLT0 - Reload Register - for writing

RLT0 - Reload Register - for reading

RLT1 - Timer Control Status Register Low

RLT1 - Timer Control Status Register High

RLT1 - Reload Register - for writing

RLT1 - Reload Register - for reading

RLT1 - Reload Register - for writing

RLT1 - Reload Register - for reading

RLT2 - Timer Control Status Register Low

RLT2 - Timer Control Status Register High

RLT2 - Reload Register - for writing

RLT2 - Reload Register - for reading

RLT2 - Reload Register - for writing

RLT2 - Reload Register - for reading

RLT3 - Timer Control Status Register Low

RLT3 - Timer Control Status Register High

RLT3 - Reload Register - for writing

RLT3 - Reload Register - for reading

ELVRL1

ELVRH1

ELVR1

RW

W

TMCSRL0

TMCSRH0

TMCSR0

TMRLR0

TMR0

R

W

R

TMCSRL1

TMCSRH1

TMCSR1

RW

W

TMRLR1

TMR1

R

W

R

TMCSRL2

TMCSRH2

TMCSR2

RW

W

TMRLR2

TMR2

R

W

R

TMCSRL3

TMCSRH3

TMCSR3

RW

W

TMRLR3

TMR3

R

33

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (5 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

00006FH

RLT3 - Reload Register - for writing

RLT3 - Reload Register - for reading

W

R

RLT6 - Timer Control Status Register Low (dedic.

RLT for PPG)

000070H

000071H

000072H

000073H

TMCSRL6

TMCSRH6

TMCSR6

RW

W

RLT6 - Timer Control Status Register High (dedic.

RLT for PPG)

RLT6 - Reload Register (dedic. RLT for PPG) - for

writing

TMRLR6

TMR6

RLT6 - Reload Register (dedic. RLT for PPG) - for

reading

R

RLT6 - Reload Register (dedic. RLT for PPG) - for

writing

W

RLT6 - Reload Register (dedic. RLT for PPG) - for

reading

R

000074H

000075H

000076H

000077H

000078H

000079H

00007AH

00007BH

00007CH

00007DH

00007EH

00007FH

000080H

000081H

000082H

000083H

000084H

000085H

PPG3-PPG0 - General Control register 1 Low

PPG3-PPG0 - General Control register 1 High

PPG3-PPG0 - General Control register 2 Low

PPG3-PPG0 - General Control register 2 High

PPG0 - Timer register

GCN1L0

GCN1H0

GCN2L0

GCN2H0

GCN10

GCN20

PTMR0

PCSR0

PDUT0

PCN0

RW

R

PPG0 - Timer register

R

PPG0 - Period setting register

PPG0 - Duty cycle register

W

PPG0 - Duty cycle register

W

PPG0 - Control status register Low

PPG0 - Control status register High

PPG1 - Timer register

PCNL0

PCNH0

RW

R

PTMR1

PCSR1

PDUT1

PPG1 - Timer register

R

PPG1 - Period setting register

PPG1 - Duty cycle register

W

PPG1 - Duty cycle register

W

34

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (6 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000086H

000087H

000088H

000089H

00008AH

00008BH

00008CH

00008DH

00008EH

00008FH

000090H

000091H

000092H

000093H

000094H

000095H

000096H

000097H

000098H

000099H

00009AH

00009BH

00009CH

00009DH

00009EH

00009FH

0000A0H

0000A1H

0000A2H

0000A3H

PPG1 - Control status register Low

PPG1 - Control status register High

PPG2 - Timer register

PCNL1

PCNH1

PCN1

PTMR2

PCSR2

PDUT2

PCN2

RW

R

PPG2 - Timer register

R

PPG2 - Period setting register

PPG2 - Duty cycle register

W

PPG2 - Duty cycle register

W

PPG2 - Control status register Low

PPG2 - Control status register High

PPG3 - Timer register

PCNL2

PCNH2

RW

R

PTMR3

PCSR3

PDUT3

PCN3

PPG3 - Timer register

R

PPG3 - Period setting register

PPG3 - Duty cycle register

W

PPG3 - Duty cycle register

W

PPG3 - Control status register Low

PPG3 - Control status register High

PPG7-PPG4 - General Control register 1 Low

PPG7-PPG4 - General Control register 1 High

PPG7-PPG4 - General Control register 2 Low

PPG7-PPG4 - General Control register 2 High

PPG4 - Timer register

PCNL3

PCNH3

RW

R

GCN1L1

GCN1H1

GCN2L1

GCN2H1

GCN11

GCN21

PTMR4

PCSR4

PDUT4

PCN4

PPG4 - Timer register

R

PPG4 - Period setting register

PPG4 - Duty cycle register

W

PPG4 - Duty cycle register

W

PPG4 - Control status register Low

PPG4 - Control status register High

PCNL4

PCNH4

RW

2008-2-7

35

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (7 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0000A4H

0000A5H

0000A6H

0000A7H

0000A8H

0000A9H

0000AAH

0000ABH

0000ACH

0000ADH

0000AEH

0000AFH

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

0000BDH

0000BEH

0000BFH

0000C0H

0000C1H

PPG5 - Timer register

PTMR5

PCSR5

PDUT5

PCN5

R

PPG5 - Timer register

R

PPG5 - Period setting register

W

PPG5 - Period setting register

W

PPG5 - Duty cycle register

W

PPG5 - Duty cycle register

W

PPG5 - Control status register Low

PPG5 - Control status register High

I2C0 - Bus Status Register

PCNL5

PCNH5

IBSR0

IBCR0

ITBAL0

ITBAH0

ITMKL0

ITMKH0

ISBA0

RW

R

I2C0 - Bus Control Register

RW

R

I2C0 - Ten bit Slave address Register Low

I2C0 - Ten bit Slave address Register High

I2C0 - Ten bit Address mask Register Low

I2C0 - Ten bit Address mask Register High

I2C0 - Seven bit Slave address Register

I2C0 - Seven bit Address mask Register

I2C0 - Data Register

ITBA0

ITMK0

ISMK0

IDAR0

ICCR0

IBSR1

IBCR1

ITBAL1

ITBAH1

ITMKL1

ITMKH1

ISBA1

I2C0 - Clock Control Register

I2C1 - Bus Status Register

I2C1 - Bus Control Register

RW

I2C1 - Ten bit Slave address Register Low

I2C1 - Ten bit Slave address Register High

I2C1 - Ten bit Address mask Register Low

I2C1 - Ten bit Address mask Register High

I2C1 - Seven bit Slave address Register

I2C1 - Seven bit Address mask Register

I2C1 - Data Register

ITBA1

ITMK1

ISMK1

IDAR1

ICCR1

SMR0

I2C1 - Clock Control Register

USART0 - Serial Mode Register

USART0 - Serial Control Register

SCR0

36

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (8 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0000C2H

0000C3H

0000C4H

0000C5H

0000C6H

0000C7H

0000C8H

0000C9H

0000CAH

0000CBH

0000CCH

0000CDH

0000CEH

0000CFH

0000D0H

0000D1H

0000D2H

0000D3H

0000D4H

0000D5H

0000D6H

0000D7H

0000D8H

0000D9H

0000DAH

0000DBH

0000DCH

USART0 - TX Register

TDR0

RDR0

W

R

USART0 - RX Register

USART0 - Serial Status

SSR0

RW

USART0 - Control/Com. Register

USART0 - Ext. Status Register

USART0 - Baud Rate Generator Register Low

USART0 - Baud Rate Generator Register High

USART0 - Extended Serial Interrupt Register

Reserved

ECCR0

ESCR0

BGRL0

BGRH0

ESIR0

BGR0

BGR1

BGR2

RW

-

USART1 - Serial Mode Register

USART1 - Serial Control Register

USART1 - TX Register

SMR1

SCR1

RW

W

TDR1

USART1 - RX Register

RDR1

R

USART1 - Serial Status

SSR1

RW

-

USART1 - Control/Com. Register

USART1 - Ext. Status Register

USART1 - Baud Rate Generator Register Low

USART1 - Baud Rate Generator Register High

USART1 - Extended Serial Interrupt Register

Reserved

ECCR1

ESCR1

BGRL1

BGRH1

ESIR1

USART2 - Serial Mode Register

USART2 - Serial Control Register

USART2 - TX Register

SMR2

SCR2

RW

W

TDR2

USART2 - RX Register

RDR2

R

USART2 - Serial Status

SSR2

RW

USART2 - Control/Com. Register

USART2 - Ext. Status Register

USART2 - Baud Rate Generator Register Low

USART2 - Baud Rate Generator Register High

USART2 - Extended Serial Interrupt Register

ECCR2

ESCR2

BGRL2

BGRH2

ESIR2

2008-2-7

37

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (9 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0000DDH

0000DEH

0000DFH

0000E0H

0000E1H

0000E2H

0000E3H

0000E4H

0000E5H

0000E6H

Reserved

-

USART3 - Serial Mode Register

USART3 - Serial Control Register

USART3 - TX Register

SMR3

SCR3

RW

W

TDR3

USART3 - RX Register

RDR3

R

USART3 - Serial Status

SSR3

RW

USART3 - Control/Com. Register

USART3 - Ext. Status Register

USART3 - Baud Rate Generator Register Low

USART3 - Baud Rate Generator Register High

USART3 - Extended Serial Interrupt Register

ECCR3

ESCR3

BGRL3

BGRH3

ESIR3

BGR3

RW

0000E7H-

0000EFH

Reserved

-

0000F0H-

0000FFH

External Bus area

EXTBUS0

RW

000100H

000101H

000102H

000103H

000104H

000105H

000106H

000107H

000108H

000109H

00010AH

00010BH

00010CH

00010DH

00010EH

00010FH

DMA0 - Buffer address pointer low byte

DMA0 - Buffer address pointer middle byte

DMA0 - Buffer address pointer high byte

DMA0 - DMA control register

BAPL0

BAPM0

BAPH0

DMACS0

IOAL0

RW

DMA0 - I/O register address pointer low byte

DMA0 - I/O register address pointer high byte

DMA0 - Data counter low byte

IOA0

RW

IOAH0

RW

DCTL0

DCTH0

BAPL1

BAPM1

BAPH1

DMACS1

IOAL1

DCT0

RW

DMA0 - Data counter high byte

RW

DMA1 - Buffer address pointer low byte

DMA1 - Buffer address pointer middle byte

DMA1 - Buffer address pointer high byte

DMA1 - DMA control register

RW

DMA1 - I/O register address pointer low byte

DMA1 - I/O register address pointer high byte

DMA1 - Data counter low byte

IOA1

RW

IOAH1

RW

DCTL1

DCTH1

DCT1

RW

DMA1 - Data counter high byte

RW

38

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (10 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000110H

000111H

000112H

000113H

000114H

000115H

000116H

000117H

000118H

000119H

00011AH

00011BH

00011CH

00011DH

00011EH

00011FH

000120H

000121H

000122H

000123H

000124H

000125H

000126H

000127H

000128H

000129H

00012AH

00012BH

00012CH

00012DH

DMA2 - Buffer address pointer low byte

DMA2 - Buffer address pointer middle byte

DMA2 - Buffer address pointer high byte

DMA2 - DMA control register

BAPL2

BAPM2

BAPH2

DMACS2

IOAL2

RW

DMA2 - I/O register address pointer low byte

DMA2 - I/O register address pointer high byte

DMA2 - Data counter low byte

IOA2

RW

IOAH2

DCTL2

DCTH2

BAPL3

BAPM3

BAPH3

DMACS3

IOAL3

DCT2

DMA2 - Data counter high byte

DMA3 - Buffer address pointer low byte

DMA3 - Buffer address pointer middle byte

DMA3 - Buffer address pointer high byte

DMA3 - DMA control register

DMA3 - I/O register address pointer low byte

DMA3 - I/O register address pointer high byte

DMA3 - Data counter low byte

IOA3

IOAH3

DCTL3

DCTH3

BAPL4

BAPM4

BAPH4

DMACS4

IOAL4

DCT3

DMA3 - Data counter high byte

DMA4 - Buffer address pointer low byte

DMA4 - Buffer address pointer middle byte

DMA4 - Buffer address pointer high byte

DMA4 - DMA control register

DMA4 - I/O register address pointer low byte

DMA4 - I/O register address pointer high byte

DMA4 - Data counter low byte

IOA4

IOAH4

DCTL4

DCTH4

BAPL5

BAPM5

BAPH5

DMACS5

IOAL5

DCT4

DMA4 - Data counter high byte

DMA5 - Buffer address pointer low byte

DMA5 - Buffer address pointer middle byte

DMA5 - Buffer address pointer high byte

DMA5 - DMA control register

DMA5 - I/O register address pointer low byte

DMA5 - I/O register address pointer high byte

IOA5

IOAH5

2008-2-7

39

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (11 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

00012EH

00012FH

000130H

000131H

000132H

000133H

000134H

000135H

000136H

000137H

000138H

000139H

00013AH

00013BH

00013CH

00013DH

00013EH

00013FH

000140H

000141H

000142H

000143H

000144H

000145H

000146H

000147H

000148H

000149H

00014AH

00014BH

DMA5 - Data counter low byte

DCTL5

DCTH5

BAPL6

BAPM6

BAPH6

DMACS6

IOAL6

DCT5

RW

DMA5 - Data counter high byte

DMA6 - Buffer address pointer low byte

DMA6 - Buffer address pointer middle byte

DMA6 - Buffer address pointer high byte

DMA6 - DMA control register

DMA6 - I/O register address pointer low byte

DMA6 - I/O register address pointer high byte

DMA6 - Data counter low byte

IOA6

IOAH6

DCTL6

DCTH6

BAPL7

BAPM7

BAPH7

DMACS7

IOAL7

DCT6

DMA6 - Data counter high byte

DMA7 - Buffer address pointer low byte

DMA7 - Buffer address pointer middle byte

DMA7 - Buffer address pointer high byte

DMA7 - DMA control register

DMA7 - I/O register address pointer low byte

DMA7 - I/O register address pointer high byte

DMA7 - Data counter low byte

IOA7

IOAH7

DCTL7

DCTH7

BAPL8

BAPM8

BAPH8

DMACS8

IOAL8

DCT7

DMA7 - Data counter high byte

DMA8 - Buffer address pointer low byte

DMA8 - Buffer address pointer middle byte

DMA8 - Buffer address pointer high byte

DMA8 - DMA control register

DMA8 - I/O register address pointer low byte

DMA8 - I/O register address pointer high byte

DMA8 - Data counter low byte

IOA8

IOAH8

DCTL8

DCTH8

BAPL9

BAPM9

BAPH9

DMACS9

DCT8

DMA8 - Data counter high byte

DMA9 - Buffer address pointer low byte

DMA9 - Buffer address pointer middle byte

DMA9 - Buffer address pointer high byte

DMA9 - DMA control register

40

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (12 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

00014CH

00014DH

00014EH

00014FH

DMA9 - I/O register address pointer low byte

DMA9 - I/O register address pointer high byte

DMA9 - Data counter low byte

IOAL9

IOAH9

DCTL9

DCTH9

IOA9

RW

DCT9

DMA9 - Data counter high byte

000150H-

00017FH

Reserved

-

000180H-

00037FH

CPU - General Purpose registers (RAM access)

GPR_RAM

RW

000380H

000381H

000382H

000383H

000384H

000385H

000386H

000387H

000388H

000389H

DMA0 - Interrupt select

DMA1 - Interrupt select

DMA2 - Interrupt select

DMA3 - Interrupt select

DMA4 - Interrupt select

DMA5 - Interrupt select

DMA6 - Interrupt select

DMA7 - Interrupt select

DMA8 - Interrupt select

DMA9 - Interrupt select

DISEL0

DISEL1

DISEL2

DISEL3

DISEL4

DISEL5

DISEL6

DISEL7

DISEL8

DISEL9

RW

00038AH-

00038FH

Reserved

-

000390H

000391H

000392H

000393H

000394H

000395H

DMA - Status register low byte

DMA - Status register high byte

DMA - Stop status register low byte

DMA - Stop status register high byte

DMA - Enable register low byte

DMA - Enable register high byte

DSRL

DSRH

DSSRL

DSSRH

DERL

DSR

DSSR

DER

RW

DERH

000396H-

00039FH

Reserved

-

0003A0H

0003A1H

0003A2H

Interrupt level register

ILR

IDX

ICR

RW

Interrupt index register

Interrupt vector table base register Low

TBRL

TBR

2008-2-7

41

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (13 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0003A3H

0003A4H

0003A5H

Interrupt vector table base register High

Delayed Interrupt register

TBRH

DIRR

NMI

RW

Non Maskable Interrupt register

0003A6H-

0003ABH

Reserved

-

0003ACH

0003ADH

0003AEH

0003AFH

0003B0H

0003B1H

0003B2H

0003B3H

0003B4H

0003B5H

0003B6H

0003B7H

0003B8H

0003B9H

0003BAH

0003BBH

0003BCH

0003BDH

0003BEH

0003BFH

0003C0H

0003C1H

0003C2H

0003C3H

0003C4H

EDSU communication interrupt selection Low

EDSU communication interrupt selection High

ROM mirror control register

EDSU2L

EDSU2H

ROMM

EDSU2

RW

EDSU conﬁguration register

EDSU

Memory patch control/status register ch 0/1

Memory patch control/status register ch 2/3

Memory patch control/status register ch 4/5

Memory patch control/status register ch 6/7

Memory Patch function - Patch address 0 low

Memory Patch function - Patch address 0 middle

Memory Patch function - Patch address 0 high

Memory Patch function - Patch address 1 low

Memory Patch function - Patch address 1 middle

Memory Patch function - Patch address 1 high

Memory Patch function - Patch address 2 low

Memory Patch function - Patch address 2 middle

Memory Patch function - Patch address 2 high

Memory Patch function - Patch address 3 low

Memory Patch function - Patch address 3 middle

Memory Patch function - Patch address 3 high

Memory Patch function - Patch address 4 low

PFCS0

PFCS1

PFCS2

PFCS3

PFAL0

PFAM0

PFAH0

PFAL1

PFAM1

PFAH1

PFAL2

PFAM2

PFAH2

PFAL3

PFAM3

PFAH3

PFAL4

42

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (14 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0003C5H

0003C6H

0003C7H

0003C8H

0003C9H

0003CAH

0003CBH

0003CCH

0003CDH

0003CEH

0003CFH

0003D0H

0003D1H

0003D2H

0003D3H

0003D4H

0003D5H

0003D6H

0003D7H

0003D8H

0003D9H

0003DAH

0003DBH

0003DCH

0003DDH

0003DEH

0003DFH

Memory Patch function - Patch address 4 middle

Memory Patch function - Patch address 4 high

Memory Patch function - Patch address 5 low

Memory Patch function - Patch address 5 middle

Memory Patch function - Patch address 5 high

Memory Patch function - Patch address 6 low

Memory Patch function - Patch address 6 middle

Memory Patch function - Patch address 6 high

Memory Patch function - Patch address 7 low

Memory Patch function - Patch address 7 middle

Memory Patch function - Patch address 7 high

Memory Patch function - Patch data 0 Low

Memory Patch function - Patch data 0 High

Memory Patch function - Patch data 1 Low

Memory Patch function - Patch data 1 High

Memory Patch function - Patch data 2 Low

Memory Patch function - Patch data 2 High

Memory Patch function - Patch data 3 Low

Memory Patch function - Patch data 3 High

Memory Patch function - Patch data 4 Low

Memory Patch function - Patch data 4 High

Memory Patch function - Patch data 5 Low

Memory Patch function - Patch data 5 High

Memory Patch function - Patch data 6 Low

Memory Patch function - Patch data 6 High

Memory Patch function - Patch data 7 Low

Memory Patch function - Patch data 7 High

PFAM4

PFAH4

PFAL5

PFAM5

PFAH5

PFAL6

PFAM6

PFAH6

PFAL7

PFAM7

PFAH7

PFDL0

PFDH0

PFDL1

PFDH1

PFDL2

PFDH2

PFDL3

PFDH3

PFDL4

PFDH4

PFDL5

PFDH5

PFDL6

PFDH6

PFDL7

PFDH7

RW

PFD0

PFD1

PFD2

PFD3

PFD4

PFD5

PFD6

PFD7

RW

0003E0H-

0003F0H

Reserved

-

0003F1H

Memory Control Status Register A

MCSRA

RW

2008-2-7

43

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (15 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0003F2H

0003F3H

Memory Timing Conﬁguration Register A Low

Memory Timing Conﬁguration Register A High

MTCRAL

MTCRAH

MTCRA

RW

0003F4H-

0003F8H

Reserved

-

0003F9H

0003FAH

0003FBH

0003FCH

0003FDH

Flash Memory Write Control register 1

Flash Memory Write Control register 2

Flash Memory Write Control register 3

Flash Memory Write Control register 4

Flash Memory Write Control register 5

FMWC1

FMWC2

FMWC3

FMWC4

FMWC5

RW

0003FEH-

0003FFH

Reserved

-

000400H

000401H

000402H

000403H

000404H

000405H

000406H

000407H

000408H

000409H

00040AH

Standby Mode control register

Clock select register

SMCR

CKSR

RW

R

Clock Stabilisation select register

Clock monitor register

CKSSR

CKMR

Clock Frequency control register Low

Clock Frequency control register High

PLL Control register Low

CKFCRL

CKFCRH

PLLCRL

PLLCRH

RCTCR

MCTCR

SCTCR

CKFCR

PLLCR

RW

PLL Control register High

RC clock timer control register

Main clock timer control register

Sub clock timer control register

Reset cause and clock status register with clear

function

00040BH

RCCSRC

R

00040CH

00040DH

00040EH

00040FH

Reset conﬁguration register

RCR

RW

R

Reset cause and clock status register

Watch dog timer conﬁguration register

Watch dog timer clear pattern register

RCCSR

WDTC

WDTCP

RW

W

000410H-

000414H

Reserved

-

000415H

Clock output activation register

COAR

RW

44

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (16 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000416H

000417H

000418H

000419H

00041AH

00041BH

Clock output conﬁguration register 0

Clock output conﬁguration register 1

Clock Modulator control register

Reserved

COCR0

COCR1

CMCR

RW

-

Clock Modulator Parameter register Low

Clock Modulator Parameter register High

CMPRL

CMPRH

CMPR

RW

00041CH-

00042BH

Reserved

-

00042CH

00042DH

Voltage Regulator Control register

VRCR

CILCR

RW

Clock Input and LVD Control Register

00042EH-

00042FH

Reserved

-

000430H

000431H

000432H

000433H

000434H

000435H

000436H

000437H

000438H

000439H

00043AH

00043BH

00043CH

00043DH

00043EH

00043FH

000440H

000441H

I/O Port P00 - Data Direction Register

I/O Port P01 - Data Direction Register

I/O Port P02 - Data Direction Register

I/O Port P03 - Data Direction Register

I/O Port P04 - Data Direction Register

I/O Port P05 - Data Direction Register

I/O Port P06 - Data Direction Register

I/O Port P07 - Data Direction Register

I/O Port P08 - Data Direction Register

I/O Port P09 - Data Direction Register

I/O Port P10 - Data Direction Register

I/O Port P11 - Data Direction Register

I/O Port P12 - Data Direction Register

I/O Port P13 - Data Direction Register

I/O Port P14 - Data Direction Register

I/O Port P15 - Data Direction Register

Reserved

DDR00

DDR01

DDR02

DDR03

DDR04

DDR05

DDR06

DDR07

DDR08

DDR09

DDR10

DDR11

DDR12

DDR13

DDR14

DDR15

RW

-

I/O Port P17 - Data Direction Register

DDR17

RW

2008-2-7

45

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (17 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000442H-

Reserved

000443H

-

000444H

000445H

000446H

000447H

000448H

000449H

00044AH

00044BH

00044CH

00044DH

00044EH

00044FH

000450H

000451H

000452H

000453H

000454H

000455H

I/O Port P00 - Port Input Enable Register

I/O Port P01 - Port Input Enable Register

I/O Port P02 - Port Input Enable Register

I/O Port P03 - Port Input Enable Register

I/O Port P04 - Port Input Enable Register

I/O Port P05 - Port Input Enable Register

I/O Port P06 - Port Input Enable Register

I/O Port P07 - Port Input Enable Register

I/O Port P08 - Port Input Enable Register

I/O Port P09 - Port Input Enable Register

I/O Port P10 - Port Input Enable Register

I/O Port P11 - Port Input Enable Register

I/O Port P12 - Port Input Enable Register

I/O Port P13 - Port Input Enable Register

I/O Port P14 - Port Input Enable Register

I/O Port P15 - Port Input Enable Register

Reserved

PIER00

PIER01

PIER02

PIER03

PIER04

PIER05

PIER06

PIER07

PIER08

PIER09

PIER10

PIER11

PIER12

PIER13

PIER14

PIER15

RW

-

I/O Port P17 - Port Input Enable Register

PIER17

RW

000456H-

000457H

Reserved

-

000458H

000459H

00045AH

00045BH

00045CH

00045DH

00045EH

00045FH

000460H

I/O Port P00 - Port Input Level Register

I/O Port P01 - Port Input Level Register

I/O Port P02 - Port Input Level Register

I/O Port P03 - Port Input Level Register

I/O Port P04 - Port Input Level Register

I/O Port P05 - Port Input Level Register

I/O Port P06 - Port Input Level Register

I/O Port P07 - Port Input Level Register

I/O Port P08 - Port Input Level Register

PILR00

PILR01

PILR02

PILR03

PILR04

PILR05

PILR06

PILR07

PILR08

RW

46

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (18 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000461H

000462H

000463H

000464H

000465H

000466H

000467H

000468H

000469H

I/O Port P09 - Port Input Level Register

I/O Port P10 - Port Input Level Register

I/O Port P11 - Port Input Level Register

I/O Port P12 - Port Input Level Register

I/O Port P13 - Port Input Level Register

I/O Port P14 - Port Input Level Register

I/O Port P15 - Port Input Level Register

Reserved

PILR09

PILR10

PILR11

PILR12

PILR13

PILR14

PILR15

RW

-

I/O Port P17 - Port Input Level Register

PILR17

RW

00046AH-

00046BH

Reserved

-

00046CH

00046DH

00046EH

00046FH

000470H

000471H

000472H

000473H

000474H

000475H

000476H

000477H

000478H

000479H

00047AH

00047BH

00047CH

00047DH

I/O Port P00 - Extended Port Input Level Register

I/O Port P01 - Extended Port Input Level Register

I/O Port P02 - Extended Port Input Level Register

I/O Port P03 - Extended Port Input Level Register

I/O Port P04 - Extended Port Input Level Register

I/O Port P05 - Extended Port Input Level Register

I/O Port P06 - Extended Port Input Level Register

I/O Port P07 - Extended Port Input Level Register

I/O Port P08 - Extended Port Input Level Register

I/O Port P09 - Extended Port Input Level Register

I/O Port P10 - Extended Port Input Level Register

I/O Port P11 - Extended Port Input Level Register

I/O Port P12 - Extended Port Input Level Register

I/O Port P13 - Extended Port Input Level Register

I/O Port P14 - Extended Port Input Level Register

I/O Port P15 - Extended Port Input Level Register

Reserved

EPILR00

EPILR01

EPILR02

EPILR03

EPILR04

EPILR05

EPILR06

EPILR07

EPILR08

EPILR09

EPILR10

EPILR11

EPILR12

EPILR13

EPILR14

EPILR15

RW

-

I/O Port P17 - Extended Port Input Level Register

EPILR17

RW

00047EH-

00047FH

Reserved

-

2008-2-7

47

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (19 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000480H

000481H

000482H

000483H

000484H

000485H

000486H

000487H

000488H

000489H

00048AH

00048BH

00048CH

00048DH

00048EH

00048FH

000490H

000491H

I/O Port P00 - Port Output Drive Register

I/O Port P01 - Port Output Drive Register

I/O Port P02 - Port Output Drive Register

I/O Port P03 - Port Output Drive Register

I/O Port P04 - Port Output Drive Register

I/O Port P05 - Port Output Drive Register

I/O Port P06 - Port Output Drive Register

I/O Port P07 - Port Output Drive Register

I/O Port P08 - Port Output Drive Register

I/O Port P09 - Port Output Drive Register

I/O Port P10 - Port Output Drive Register

I/O Port P11 - Port Output Drive Register

I/O Port P12 - Port Output Drive Register

I/O Port P13 - Port Output Drive Register

I/O Port P14 - Port Output Drive Register

I/O Port P15 - Port Output Drive Register

Reserved

PODR00

PODR01

PODR02

PODR03

PODR04

PODR05

PODR06

PODR07

PODR08

PODR09

PODR10

PODR11

PODR12

PODR13

PODR14

PODR15

RW

-

I/O Port P17 - Port Output Drive Register

PODR17

RW

000492H-

00049BH

Reserved

-

00049CH

00049DH

00049EH

I/O Port P08 - Port High Drive Register

I/O Port P09 - Port High Drive Register

I/O Port P10 - Port High Drive Register

PHDR08

PHDR09

PHDR10

RW

00049FH-

0004A7H

Reserved

-

0004A8H

0004A9H

0004AAH

0004ABH

0004ACH

0004ADH

I/O Port P00 - Pull-Up resistor Control Register

I/O Port P01 - Pull-Up resistor Control Register

I/O Port P02 - Pull-Up resistor Control Register

I/O Port P03 - Pull-Up resistor Control Register

I/O Port P04 - Pull-Up resistor Control Register

I/O Port P05 - Pull-Up resistor Control Register

PUCR00

PUCR01

PUCR02

PUCR03

PUCR04

PUCR05

RW

48

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (20 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0004AEH

0004AFH

0004B0H

0004B1H

0004B2H

0004B3H

0004B4H

0004B5H

0004B6H

0004B7H

0004B8H

0004B9H

I/O Port P06 - Pull-Up resistor Control Register

I/O Port P07 - Pull-Up resistor Control Register

I/O Port P08 - Pull-Up resistor Control Register

I/O Port P09 - Pull-Up resistor Control Register

I/O Port P10 - Pull-Up resistor Control Register

I/O Port P11 - Pull-Up resistor Control Register

I/O Port P12 - Pull-Up resistor Control Register

I/O Port P13 - Pull-Up resistor Control Register

I/O Port P14 - Pull-Up resistor Control Register

I/O Port P15 - Pull-Up resistor Control Register

Reserved

PUCR06

PUCR07

PUCR08

PUCR09

PUCR10

PUCR11

PUCR12

PUCR13

PUCR14

PUCR15

RW

-

I/O Port P17 - Pull-Up resistor Control Register

PUCR17

RW

0004BAH-

0004BBH

Reserved

-

0004BCH

0004BDH

0004BEH

0004BFH

0004C0H

0004C1H

0004C2H

0004C3H

0004C4H

0004C5H

0004C6H

0004C7H

0004C8H

0004C9H

0004CAH

0004CBH

I/O Port P00 - External Pin State Register

I/O Port P01 - External Pin State Register

I/O Port P02 - External Pin State Register

I/O Port P03 - External Pin State Register

I/O Port P04 - External Pin State Register

I/O Port P05 - External Pin State Register

I/O Port P06 - External Pin State Register

I/O Port P07 - External Pin State Register

I/O Port P08 - External Pin State Register

I/O Port P09 - External Pin State Register

I/O Port P10 - External Pin State Register

I/O Port P11 - External Pin State Register

I/O Port P12 - External Pin State Register

I/O Port P13 - External Pin State Register

I/O Port P14 - External Pin State Register

I/O Port P15 - External Pin State Register

EPSR00

EPSR01

EPSR02

EPSR03

EPSR04

EPSR05

EPSR06

EPSR07

EPSR08

EPSR09

EPSR10

EPSR11

EPSR12

EPSR13

EPSR14

EPSR15

R

2008-2-7

49

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (21 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0004CCH

0004CDH

Reserved

-

I/O Port P17 - External Pin State Register

Reserved

EPSR17

R

0004CEH-

0004CFH

-

0004D0H

0004D1H

0004D2H

0004D3H

0004D4H

0004D5H

0004D6H

0004D7H

0004D8H

0004D9H

0004DAH

0004DBH

0004DCH

0004DDH

0004DEH

0004DFH

0004E0H

0004E1H

0004E2H

0004E3H

0004E4H

0004E5H

0004E6H

0004E7H

0004E8H

0004E9H

ADC analog input enable register 0

ADC analog input enable register 1

ADC analog input enable register 2

ADC analog input enable register 3

ADC analog input enable register 4

Reserved

ADER0

ADER1

ADER2

ADER3

ADER4

RW

-

Peripheral Resource Relocation Register 0

Peripheral Resource Relocation Register 1

Peripheral Resource Relocation Register 2

Peripheral Resource Relocation Register 3

Peripheral Resource Relocation Register 4

Peripheral Resource Relocation Register 5

Peripheral Resource Relocation Register 6

Peripheral Resource Relocation Register 7

Peripheral Resource Relocation Register 8

Peripheral Resource Relocation Register 9

RTC - Sub Second Register L

PRRR0

PRRR1

PRRR2

PRRR3

PRRR4

PRRR5

PRRR6

PRRR7

PRRR8

PRRR9

WTBRL0

WTBRH0

WTBR1

WTSR

RW

WTBR0

RW

RTC - Sub Second Register M

RTC - Sub-Second Register H

RTC - Second Register

RTC - Minutes

WTMR

RTC - Hour

WTHR

RTC - Timer Control Extended Register

RTC - Clock select register

WTCER

WTCKSR

WTCRL

WTCRH

RTC - Timer Control Register Low

RTC - Timer Control Register High

WTCR

50

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (22 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0004EAH

0004EBH

0004ECH

0004EDH

0004EEH

0004EFH

0004F0H

0004F1H

CAL - Calibration unit Control register

Reserved

CUCR

RW

-

CAL - Duration Timer Data Register Low

CAL - Duration Timer Data Register High

CAL - Calibration Timer Register 2 Low

CAL - Calibration Timer Register 2 High

CAL - Calibration Timer Register 1 Low

CAL - Calibration Timer Register 1 High

CUTDL

CUTDH

CUTR2L

CUTR2H

CUTR1L

CUTR1H

CUTD

CUTR2

CUTR1

RW

R

0004F2H-

0004F9H

Reserved

-

RW

-

0004FAH

RLT - Timer input select (for Cascading)

Reserved

TMISR

0004FBH-

0004FFH

000500H

000501H

FRT2 - Data register of free-running timer

TCDT2

TCCS2

RW

FRT2 - Control status register of free-running timer

Low

000502H

000503H

TCCSL2

TCCSH2

RW

FRT2 - Control status register of free-running timer

High

000504H

000505H

FRT3 - Data register of free-running timer

TCDT3

TCCS3

RW

FRT3 - Control status register of free-running timer

Low

000506H

000507H

TCCSL3

TCCSH3

RW

FRT3 - Control status register of free-running timer

High

000508H

000509H

00050AH

00050BH

00050CH

00050DH

00050EH

OCU8 - Output Compare Control Status

OCU9 - Output Compare Control Status

OCU8 - Compare Register

OCS8

OCS9

RW

OCCP8

OCCP9

OCU8 - Compare Register

OCU9 - Compare Register

OCU10 - Output Compare Control Status

OCS10

2008-2-7

51

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (23 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

00050FH

000510H

000511H

000512H

000513H

000514H

000515H

000516H

000517H

000518H

000519H

OCU11 - Output Compare Control Status

OCU10 - Compare Register

OCU11 - Compare Register

ICU8/ICU9 - Control Status Register

ICU8/ICU9 - Edge Register

OCS11

RW

OCCP10

OCCP11

RW

R

ICS89

ICE89

ICU8 - Capture Register Low

ICU8 - Capture Register High

ICU9 - Capture Register Low

ICU9 - Capture Register High

IPCPL8

IPCPH8

IPCPL9

IPCPH9

IPCP8

IPCP9

R

00051AH-

000529H

Reserved

-

00052AH

00052BH

00052CH

00052DH

00052EH

00052FH

000530H

000531H

000532H

USART5 - Serial Mode Register

USART5 - Serial Control Register

USART5 - RX Register

SMR5

SCR5

RW

W

TDR5

USART5 - TX Register

RDR5

R

USART5 - Serial Status

SSR5

RW

USART5 - Control/Com. Register

USART5 - Ext. Status Register

USART5 - Baud Rate Generator Register Low

USART5 - Baud Rate Generator Register High

USART5 - Extended Serial Interrupt Register

ECCR5

ESCR5

BGRL5

BGRH5

ESIR5

BGR5

000533H-

00053DH

Reserved

-

00053EH

00053FH

000540H

000541H

000542H

USART7 - Serial Mode Register

USART7 - Serial Control Register

USART7 - Serial TX Register

SMR7

SCR7

TDR7

RDR7

SSR7

ECCR7

RW

W

USART7 - Serial RX Register

R

USART7 - Serial Status Register

USART7 - Ext. Control/Com. Register

RW

52

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (24 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000543H

000544H

000545H

000546H

000547H

000548H

000549H

00054AH

00054BH

00054CH

00054DH

00054EH

00054FH

000550H

000551H

000552H

000553H

000554H

000555H

000556H

000557H

000558H

000559H

00055AH

USART7 - Ext. Status Com. Register

USART7 - Baud Rate Generator Register Low

USART7 - Baud Rate Generator Register High

USART7 - Extended Serial Interrupt Register

Reserved

ESCR7

BGRL7

BGRH7

ESIR7

RW

BGR7

BGR8

BGR9

RW

-

USART8 - Serial Mode Register

SMR8

SCR8

RW

W

USART8 - Serial Control Register

USART8 - Serial TX Register

TDR8

USART8 - Serial RX Register

RDR8

R

USART8 - Serial Status Register

USART8 - Ext. Control/Com. Register

USART8 - Ext. Status Com. Register

USART8 - Baud Rate Generator Register Low

USART8 - Baud Rate Generator Register High

USART8 - Extended Serial Interrupt Register

Reserved

SSR8

RW

-

ECCR8

ESCR8

BGRL8

BGRH8

ESIR8

USART9 - Serial Mode Register

SMR9

SCR9

RW

W

USART9 - Serial Control Register

USART9 - Serial TX Register

TDR9

USART9 - Serial RX Register

RDR9

R

USART9 - Serial Status Register

USART9 - Ext. Control/Com. Register

USART9 - Ext. Status Com. Register

USART9 - Baud Rate Generator Register Low

USART9 - Baud Rate Generator Register High

USART9 - Extended Serial Interrupt Register

SSR9

RW

ECCR9

ESCR9

BGRL9

BGRH9

ESIR9

00055BH-

00055FH

Reserved

-

000560H

000561H

ALARM0 - Control Status Register

ACSR0

RW

ALARM0 - Extended Control Status Register

AECSR0

2008-2-7

53

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (25 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000562H

000563H

000564H

000565H

000566H

000567H

000568H

000569H

00056AH

00056BH

00056CH

00056DH

00056EH

00056FH

000570H

000571H

000572H

000573H

000574H

000575H

000576H

000577H

000578H

000579H

00057AH

00057BH

00057CH

00057DH

00057EH

00057FH

ALARM1 - Control Status Register

ALARM1 - Extended Control Status Register

PPG6 - Timer register

ACSR1

RW

AECSR1

PTMR6

PCSR6

PDUT6

PCN6

R

PPG6 - Timer register

PPG6 - Period setting register

PPG6 - Duty cycle register

W

PPG6 - Duty cycle register

W

PPG6 - Control status register Low

PPG6 - Control status register High

PPG7 - Timer register

PCNL6

PCNH6

RW

R

PTMR7

PCSR7

PDUT7

PCN7

PPG7 - Timer register

R

PPG7 - Period setting register

PPG7 - Duty cycle register

W

PPG7 - Duty cycle register

W

PPG7 - Control status register Low

PPG7 - Control status register High

PPG11-PPG8 - General Control register 1 Low

PPG11-PPG8 - General Control register 1 High

PPG11-PPG8 - General Control register 2 Low

PPG11-PPG8 - General Control register 2 High

PPG8 - Timer register

PCNL7

PCNH7

RW

R

GCN1L2

GCN1H2

GCN2L2

GCN2H2

GCN12

GCN22

PTMR8

PCSR8

PDUT8

PCN8

PPG8 - Timer register

R

PPG8 - Period setting register

PPG8 - Duty cycle register

W

PPG8 - Duty cycle register

W

PPG8 - Control status register Low

PPG8 - Control status register High

PCNL8

PCNH8

RW

54

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (26 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000580H

000581H

000582H

000583H

000584H

000585H

000586H

000587H

000588H

000589H

00058AH

00058BH

00058CH

00058DH

00058EH

00058FH

000590H

000591H

000592H

000593H

000594H

000595H

000596H

000597H

000598H

000599H

00059AH

00059BH

00059CH

00059DH

PPG9 - Timer register

PTMR9

PCSR9

PDUT9

PCN9

R

PPG9 - Timer register

PPG9 - Period setting register

PPG9 - Duty cycle register

W

PPG9 - Duty cycle register

W

PPG9 - Control status register Low

PPG9 - Control status register High

PPG10 - Timer register

PCNL9

PCNH9

RW

R

PTMR10

PCSR10

PDUT10

PCN10

PPG10 - Timer register

R

PPG10 - Period setting register

PPG10 - Duty cycle register

W

PPG10 - Duty cycle register

W

PPG10 - Control status register Low

PPG10 - Control status register High

PPG11 - Timer register

PCNL10

PCNH10

RW

R

PTMR11

PCSR11

PDUT11

PCN11

PPG11 - Timer register

R

PPG11 - Period setting register

PPG11 - Duty cycle register

W

PPG11 - Duty cycle register

W

PPG11 - Control status register Low

PPG11 - Control status register High

PPG15-PPG12 - General Control register 1 Low

PPG15-PPG12 - General Control register 1 High

PPG15-PPG12 - General Control register 2 Low

PPG15-PPG12 - General Control register 2 High

PPG12 - Timer register

PCNL11

PCNH11

GCN1L3

GCN1H3

GCN2L3

GCN2H3

RW

R

GCN13

GCN23

PTMR12

PPG12 - Timer register

R

2008-2-7

55

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (27 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

00059EH

00059FH

0005A0H

0005A1H

0005A2H

0005A3H

0005A4H

0005A5H

0005A6H

0005A7H

0005A8H

0005A9H

0005AAH

0005ABH

0005ACH

0005ADH

0005AEH

0005AFH

0005B0H

0005B1H

0005B2H

0005B3H

0005B4H

0005B5H

0005B6H

0005B7H

0005B8H

0005B9H

0005BAH

0005BBH

PPG12 - Period setting register

PPG12 - Duty cycle register

PPG12 - Control status register Low

PPG12 - Control status register High

PPG13 - Timer register

PCSR12

PDUT12

PCN12

W

PCNL12

PCNH12

RW

R

PTMR13

PCSR13

PDUT13

PCN13

PPG13 - Timer register

R

PPG13 - Period setting register

PPG13 - Duty cycle register

PPG13 - Control status register Low

PPG13 - Control status register High

PPG14 - Timer register

W

PCNL13

PCNH13

RW

R

PTMR14

PCSR14

PDUT14

PCN14

PPG14 - Timer register

R

PPG14 - Period setting register

PPG14 - Duty cycle register

PPG14 - Control status register Low

PPG14 - Control status register High

PPG15 - Timer register

W

PCNL14

PCNH14

RW

R

PTMR15

PCSR15

PDUT15

PCN15

PPG15 - Timer register

R

PPG15 - Period setting register

PPG15 - Duty cycle register

PPG15 - Control status register Low

PPG15 - Control status register High

W

PCNL15

PCNH15

RW

56

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (28 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0005BCH

0005BDH

0005BEH

0005BFH

0005C0H

0005C1H

0005C2H

0005C3H

0005C4H

0005C5H

0005C6H

0005C7H

0005C8H

0005C9H

0005CAH

0005CBH

0005CCH

0005CDH

0005CEH

0005CFH

0005D0H

0005D1H

0005D2H

0005D3H

0005D4H

0005D5H

0005D6H

0005D7H

0005D8H

0005D9H

PPG19-PPG16 - General Control register 1 Low

PPG19-PPG16 - General Control register 1 High

PPG19-PPG16 - General Control register 2 Low

PPG19-PPG16 - General Control register 2 High

PPG16 - Timer register

GCN1L4

GCN1H4

GCN2L4

GCN2H4

GCN14

RW

R

GCN24

PTMR16

PCSR16

PDUT16

PCN16

PPG16 - Timer register

R

PPG16 - Period setting register

PPG16 - Duty cycle register

W

PPG16 - Duty cycle register

W

PPG16 - Control status register Low

PPG16 - Control status register High

PPG17 - Timer register

PCNL16

PCNH16

RW

R

PTMR17

PCSR17

PDUT17

PCN17

PPG17 - Timer register

R

PPG17 - Period setting register

PPG17 - Duty cycle register

W

PPG17 - Duty cycle register

W

PPG17 - Control status register Low

PPG17 - Control status register High

PPG18 - Timer register

PCNL17

PCNH17

RW

R

PTMR18

PCSR18

PDUT18

PCN18

PPG18 - Timer register

R

PPG18 - Period setting register

PPG18 - Duty cycle register

W

PPG18 - Duty cycle register

W

PPG18 - Control status register Low

PPG18 - Control status register High

PPG19 - Timer register

PCNL18

PCNH18

RW

R

PTMR19

PPG19 - Timer register

R

2008-2-7

57

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (29 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0005DAH

0005DBH

0005DCH

0005DDH

0005DEH

0005DFH

PPG19 - Period setting register

PPG19 - Duty cycle register

PCSR19

PDUT19

PCN19

W

PPG19 - Duty cycle register

W

PPG19 - Control status register Low

PPG19 - Control status register High

PCNL19

PCNH19

RW

0005E0H-

00065FH

Reserved

-

000660H

000661H

000662H

000663H

Peripheral Resource Relocation Register 10

Peripheral Resource Relocation Register 11

Peripheral Resource Relocation Register 12

Peripheral Resource Relocation Register 13

PRRR10

PRRR11

PRRR12

PRRR13

RW

W

000664H-

00069FH

Reserved

-

0006A0H

0006A1H

0006A2H

0006A3H

0006A4H

0006A5H

0006A6H

0006A7H

0006A8H

0006A9H

0006AAH

0006ABH

0006ACH

0006ADH

0006AEH

0006AFH

0006B0H

USB - Host Control register Low

USB - Host Control register High

USB - Host Interrupt Register

HCNTL0

HCNTH0

HCNT0

RW

HIRQ0

RW

USB - Host Error Status Register

USB - Host State Status Register

USB - Host SOF Int. Frame Compare Register

USB - Host Retry Timer Setting Register Low

USB - Host Retry Timer Setting Register Middle

USB - Host Retry Timer Setting Register High

USB - Host Address Register

HERR0

RW

HSTATE0

HFCOMP0

HRTIMERL0

HRTIMERM0

HRTIMERH0

HADR0

RW

USB - Host EOF Setting Register Low

USB - Host EOF Setting Register High

USB - Host Frame Register Low

USB - Host Frame Register High

USB - Host Token End Point Register

Reserved

HEOFL0

HEOF0

RW

HEOFH0

RW

HFRAMEL0

HFRAMEH0

HTOKEN0

HFRAME0

RW

-

USB - UDC Control Register

UDCC0

RW

58

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (30 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0006B1H

0006B2H

0006B3H

0006B4H

0006B5H

0006B6H

0006B7H

0006B8H

0006B9H

0006BAH

0006BBH

0006BCH

0006BDH

0006BEH

0006BFH

0006C0H

0006C1H

0006C2H

0006C3H

0006C4H

0006C5H

0006C6H

0006C7H

0006C8H

0006C9H

0006CAH

0006CBH

0006CCH

0006CDH

0006CEH

Reserved

-

USB - EP0 Control Register Low

USB - EP0 Control Register High

USB - EP1 Control Register Low

USB - EP1 Control Register High - non public

USB - EP2 Control Register Low

USB - EP2 Control Register High

USB - EP3 Control Register Low

USB - EP3 Control Register High

USB - EP4 Control Register Low

USB - EP4 Control Register High

USB - EP5 Control Register Low

USB - EP5 Control Register High

USB - Timer Stamp Register Low

USB - Timer Stamp Register High

USB - UDC Status Register

EP0CL0

EP0CH0

EP1CL0

EP1CH0

EP2CL0

EP2CH0

EP3CL0

EP3CH0

EP4CL0

EP4CH0

EP5CL0

EP5CH0

TMSPL0

TMSPH0

UDCS0

EP0C0

EP1C0

EP2C0

EP3C0

EP4C0

EP5C0

TMSP0

RW

W

USB - UDC Interrupt Enable Register

USB - EP0I Status Register Low

USB - EP0I Status Register High

USB - EP0O Status Register Low

USB - EP0O Status Register High

USB - EP1 Status Register Low

USB - EP1 Status Register High

USB - EP2 Status Register Low

USB - EP2 Status Register High

USB - EP3 Status Register Low

USB - EP3 Status Register High

USB - EP4 Status Register Low

USB - EP4 Status Register High

USB - EP5 Status Register Low

UDCIE0

EP0ISL0

EP0ISH0

EP0OSL0

EP0OSH0

EP1SL0

EP1SH0

EP2SL0

EP2SH0

EP3SL0

EP3SH0

EP4SL0

EP4SH0

EP5SL0

EP0IS0

EP0OS0

EP1S0

EP2S0

EP3S0

EP4S0

EP5S0

RW

2008-2-7

59

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (31 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0006CFH

0006D0H

0006D1H

0006D2H

0006D3H

0006D4H

0006D5H

0006D6H

0006D7H

0006D8H

0006D9H

0006DAH

0006DBH

USB - EP5 Status Register High

USB - EP0 Data register Low

USB - EP0 Data register High

USB - EP1 Data register Low

USB - EP1 Data register High

USB - EP2 Data register Low

USB - EP2 Data register High

USB - EP3 Data register Low

USB - EP3 Data register High

USB - EP4 Data register Low

USB - EP4 Data register High

USB - EP5 Data register Low

USB - EP5 Data register High

EP5SH0

EP0DTL0

EP0DTH0

EP1DTL0

EP1DTH0

EP2DTL0

EP2DTH0

EP3DTL0

EP3DTH0

EP4DTL0

EP4DTH0

EP5DTL0

EP5DTH0

RW

EP0DT0

EP1DT0

EP2DT0

EP3DT0

EP4DT0

EP5DT0

RW

0006DCH-

0006DFH

Reserved

-

0006E0H

0006E1H

0006E2H

0006E3H

0006E4H

0006E5H

0006E6H

0006E7H

0006E8H

0006E9H

0006EAH

0006EBH

0006ECH

0006EDH

0006EEH

External Bus - Area conﬁguration register 0 Low

External Bus - Area conﬁguration register 0 High

External Bus - Area conﬁguration register 1 Low

External Bus - Area conﬁguration register 1 High

External Bus - Area conﬁguration register 2 Low

External Bus - Area conﬁguration register 2 High

External Bus - Area conﬁguration register 3 Low

External Bus - Area conﬁguration register 3 High

External Bus - Area conﬁguration register 4 Low

External Bus - Area conﬁguration register 4 High

External Bus - Area conﬁguration register 5 Low

External Bus - Area conﬁguration register 5 High

External Bus - Area select register 2

EACL0

EACH0

EACL1

EACH1

EACL2

EACH2

EACL3

EACH3

EACL4

EACH4

EACL5

EACH5

EAS2

EAC0

EAC1

EAC2

EAC3

EAC4

EAC5

RW

External Bus - Area select register 3

EAS3

External Bus - Area select register 4

EAS4

60

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (32 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0006EFH

0006F0H

0006F1H

0006F2H

0006F3H

0006F4H

0006F5H

External Bus - Area select register 5

EAS5

EBM

RW

External Bus - Mode register

External Bus - Clock and Function register

External Bus - Address output enable register 0

External Bus - Address output enable register 1

External Bus - Address output enable register 2

External Bus - Control signal register

EBCF

EBAE0

EBAE1

EBAE2

EBCS

0006F6H-

0006FFH

Reserved

-

000700H

000701H

000702H

000703H

000704H

000705H

000706H

000707H

000708H

000709H

00070AH

00070BH

00070CH

00070DH

CAN0 - Control register Low

CTRLRL0

CTRLRH0

STATRL0

STATRH0

ERRCNTL0

ERRCNTH0

BTRL0

CTRLR0

STATR0

ERRCNT0

BTR0

RW

R

CAN0 - Control register High (reserved)

CAN0 - Status register Low

RW

R

CAN0 - Status register High (reserved)

CAN0 - Error Counter Low (Transmit)

CAN0 - Error Counter High (Receive)

CAN0 - Bit Timing Register Low

CAN0 - Bit Timing Register High

CAN0 - Interrupt Register Low

R

RW

R

BTRH0

INTRL0

INTR0

CAN0 - Interrupt Register High

INTRH0

R

CAN0 - Test Register Low

TESTRL0

TESTRH0

BRPERL0

BRPERH0

TESTR0

BRPER0

RW

R

CAN0 - Test Register High (reserved)

CAN0 - BRP Extension register Low

CAN0 - BRP Extension register High (reserved)

RW

R

00070EH-

00070FH

Reserved

-

000710H

000711H

000712H

CAN0 - IF1 Command request register Low

CAN0 - IF1 Command request register High

CAN0 - IF1 Command Mask register Low

IF1CREQL0

IF1CREQH0

IF1CMSKL0

IF1CREQ0

IF1CMSK0

RW

CAN0 - IF1 Command Mask register High (re-

served)

000713H

000714H

IF1CMSKH0

IF1MSK1L0

R

CAN0 - IF1 Mask 1 Register Low

IF1MSK10

RW

2008-2-7

61

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (33 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000715H

000716H

000717H

000718H

000719H

00071AH

00071BH

00071CH

00071DH

00071EH

00071FH

000720H

000721H

000722H

000723H

000724H

000725H

CAN0 - IF1 Mask 1 Register High

CAN0 - IF1 Mask 2 Register Low

CAN0 - IF1 Mask 2 Register High

CAN0 - IF1 Arbitration 1 Register Low

CAN0 - IF1 Arbitration 1 Register High

CAN0 - IF1 Arbitration 2 Register Low

CAN0 - IF1 Arbitration 2 Register High

CAN0 - IF1 Message Control Register Low

CAN0 - IF1 Message Control Register High

CAN0 - IF1 Data A1 Low

IF1MSK1H0

IF1MSK2L0

IF1MSK2H0

IF1ARB1L0

IF1ARB1H0

IF1ARB2L0

IF1ARB2H0

IF1MCTRL0

IF1MCTRH0

IF1DTA1L0

IF1DTA1H0

IF1DTA2L0

IF1DTA2H0

IF1DTB1L0

IF1DTB1H0

IF1DTB2L0

IF1DTB2H0

RW

IF1MSK20

IF1ARB10

IF1ARB20

IF1MCTR0

IF1DTA10

IF1DTA20

IF1DTB10

IF1DTB20

RW

CAN0 - IF1 Data A1 High

CAN0 - IF1 Data A2 Low

CAN0 - IF1 Data A2 High

CAN0 - IF1 Data B1 Low

CAN0 - IF1 Data B1 High

CAN0 - IF1 Data B2 Low

CAN0 - IF1 Data B2 High

000726H-

00073FH

Reserved

-

000740H

000741H

000742H

CAN0 - IF2 Command request register Low

CAN0 - IF2 Command request register High

CAN0 - IF2 Command Mask register Low

IF2CREQL0

IF2CREQH0

IF2CMSKL0

IF2CREQ0

IF2CMSK0

RW

CAN0 - IF2 Command Mask register High (re-

served)

000743H

IF2CMSKH0

R

000744H

000745H

000746H

000747H

000748H

000749H

00074AH

CAN0 - IF2 Mask 1 Register Low

CAN0 - IF2 Mask 1 Register High

CAN0 - IF2 Mask 2 Register Low

CAN0 - IF2 Mask 2 Register High

CAN0 - IF2 Arbitration 1 Register Low

CAN0 - IF2 Arbitration 1 Register High

CAN0 - IF2 Arbitration 2 Register Low

IF2MSK1L0

IF2MSK1H0

IF2MSK2L0

IF2MSK2H0

IF2ARB1L0

IF2ARB1H0

IF2ARB2L0

IF2MSK10

IF2MSK20

IF2ARB10

IF2ARB20

RW

62

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (34 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

00074BH

00074CH

00074DH

00074EH

00074FH

000750H

000751H

000752H

000753H

000754H

000755H

CAN0 - IF2 Arbitration 2 Register High

CAN0 - IF2 Message Control Register Low

CAN0 - IF2 Message Control Register High

CAN0 - IF2 Data A1 Low

IF2ARB2H0

IF2MCTRL0

IF2MCTRH0

IF2DTA1L0

IF2DTA1H0

IF2DTA2L0

IF2DTA2H0

IF2DTB1L0

IF2DTB1H0

IF2DTB2L0

IF2DTB2H0

RW

IF2MCTR0

IF2DTA10

IF2DTA20

IF2DTB10

IF2DTB20

RW

CAN0 - IF2 Data A1 High

CAN0 - IF2 Data A2 Low

CAN0 - IF2 Data A2 High

CAN0 - IF2 Data B1 Low

CAN0 - IF2 Data B1 High

CAN0 - IF2 Data B2 Low

CAN0 - IF2 Data B2 High

000756H-

00077FH

Reserved

-

000780H

000781H

000782H

000783H

CAN0 - Transmission Request 1 Register Low

CAN0 - Transmission Request 1 Register High

CAN0 - Transmission Request 2 Register Low

CAN0 - Transmission Request 2 Register High

TREQR1L0

TREQR1H0

TREQR2L0

TREQR2H0

TREQR10

TREQR20

R

000784H-

00078FH

Reserved

-

000790H

000791H

000792H

000793H

CAN0 - New Data 1 Register Low

CAN0 - New Data 1 Register High

CAN0 - New Data 2 Register Low

CAN0 - New Data 2 Register High

NEWDT1L0

NEWDT1H0

NEWDT2L0

NEWDT2H0

NEWDT10

NEWDT20

R

000794H-

00079FH

Reserved

-

0007A0H

0007A1H

0007A2H

0007A3H

CAN0 - Interrupt Pending 1 Register Low

CAN0 - Interrupt Pending 1 Register High

CAN0 - Interrupt Pending 2 Register Low

CAN0 - Interrupt Pending 2 Register High

INTPND1L0

INTPND1H0

INTPND2L0

INTPND2H0

INTPND10

INTPND20

R

0007A4H-

0007AFH

Reserved

-

2008-2-7

63

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (35 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0007B0H

0007B1H

0007B2H

0007B3H

CAN0 - Message Valid 1 Register Low

CAN0 - Message Valid 1 Register High

CAN0 - Message Valid 2 Register Low

CAN0 - Message Valid 2 Register High

MSGVAL1L0

MSGVAL1H0

MSGVAL2L0

MSGVAL2H0

MSGVAL10

R

MSGVAL20

0007B4H-

0007CDH

Reserved

-

RW

-

0007CEH

CAN0 - Output enable register

Reserved

COER0

0007CFH-

0007FFH

000800H

000801H

000802H

000803H

000804H

000805H

000806H

000807H

000808H

000809H

00080AH

00080BH

00080CH

00080DH

CAN1 - Control register Low

CTRLRL1

CTRLRH1

STATRL1

STATRH1

ERRCNTL1

ERRCNTH1

BTRL1

CTRLR1

STATR1

ERRCNT1

BTR1

RW

R

CAN1 - Control register High (reserved)

CAN1 - Status register Low

RW

R

CAN1 - Status register High (reserved)

CAN1 - Error Counter Low (Transmit)

CAN1 - Error Counter High (Receive)

CAN1 - Bit Timing Register Low

CAN1 - Bit Timing Register High

CAN1 - Interrupt Register Low

R

RW

R

BTRH1

INTRL1

INTR1

CAN1 - Interrupt Register High

INTRH1

R

CAN1 - Test Register Low

TESTRL1

TESTRH1

BRPERL1

BRPERH1

TESTR1

BRPER1

RW

R

CAN1 - Test Register High (reserved)

CAN1 - BRP Extension register Low

CAN1 - BRP Extension register High (reserved)

RW

R

00080EH-

00080FH

Reserved

-

000810H

000811H

000812H

CAN1 - IF1 Command request register Low

CAN1 - IF1 Command request register High

CAN1 - IF1 Command Mask register Low

IF1CREQL1

IF1CREQH1

IF1CMSKL1

IF1CREQ1

IF1CMSK1

RW

CAN1 - IF1 Command Mask register High (re-

served)

000813H

000814H

IF1CMSKH1

IF1MSK1L1

R

CAN1 - IF1 Mask 1 Register Low

IF1MSK11

RW

64

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (36 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000815H

000816H

000817H

000818H

000819H

00081AH

00081BH

00081CH

00081DH

00081EH

00081FH

000820H

000821H

000822H

000823H

000824H

000825H

CAN1 - IF1 Mask 1 Register High

CAN1 - IF1 Mask 2 Register Low

CAN1 - IF1 Mask 2 Register High

CAN1 - IF1 Arbitration 1 Register Low

CAN1 - IF1 Arbitration 1 Register High

CAN1 - IF1 Arbitration 2 Register Low

CAN1 - IF1 Arbitration 2 Register High

CAN1 - IF1 Message Control Register Low

CAN1 - IF1 Message Control Register High

CAN1 - IF1 Data A1 Low

IF1MSK1H1

IF1MSK2L1

IF1MSK2H1

IF1ARB1L1

IF1ARB1H1

IF1ARB2L1

IF1ARB2H1

IF1MCTRL1

IF1MCTRH1

IF1DTA1L1

IF1DTA1H1

IF1DTA2L1

IF1DTA2H1

IF1DTB1L1

IF1DTB1H1

IF1DTB2L1

IF1DTB2H1

RW

IF1MSK21

IF1ARB11

IF1ARB21

IF1MCTR1

IF1DTA11

IF1DTA21

IF1DTB11

IF1DTB21

RW

CAN1 - IF1 Data A1 High

CAN1 - IF1 Data A2 Low

CAN1 - IF1 Data A2 High

CAN1 - IF1 Data B1 Low

CAN1 - IF1 Data B1 High

CAN1 - IF1 Data B2 Low

CAN1 - IF1 Data B2 High

000826H-

00083FH

Reserved

-

000840H

000841H

000842H

CAN1 - IF2 Command request register Low

CAN1 - IF2 Command request register High

CAN1 - IF2 Command Mask register Low

IF2CREQL1

IF2CREQH1

IF2CMSKL1

IF2CREQ1

IF2CMSK1

RW

CAN1 - IF2 Command Mask register High (re-

served)

000843H

IF2CMSKH1

R

000844H

000845H

000846H

000847H

000848H

000849H

00084AH

2008-2-7

CAN1 - IF2 Mask 1 Register Low

CAN1 - IF2 Mask 1 Register High

CAN1 - IF2 Mask 2 Register Low

CAN1 - IF2 Mask 2 Register High

CAN1 - IF2 Arbitration 1 Register Low

CAN1 - IF2 Arbitration 1 Register High

CAN1 - IF2 Arbitration 2 Register Low

IF2MSK1L1

IF2MSK1H1

IF2MSK2L1

IF2MSK2H1

IF2ARB1L1

IF2ARB1H1

IF2ARB2L1

IF2MSK11

IF2MSK21

IF2ARB11

IF2ARB21

RW

65

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (37 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

00084BH

00084CH

00084DH

00084EH

00084FH

000850H

000851H

000852H

000853H

000854H

000855H

CAN1 - IF2 Arbitration 2 Register High

CAN1 - IF2 Message Control Register Low

CAN1 - IF2 Message Control Register High

CAN1 - IF2 Data A1 Low

IF2ARB2H1

IF2MCTRL1

IF2MCTRH1

IF2DTA1L1

IF2DTA1H1

IF2DTA2L1

IF2DTA2H1

IF2DTB1L1

IF2DTB1H1

IF2DTB2L1

IF2DTB2H1

RW

IF2MCTR1

IF2DTA11

IF2DTA21

IF2DTB11

IF2DTB21

RW

CAN1 - IF2 Data A1 High

CAN1 - IF2 Data A2 Low

CAN1 - IF2 Data A2 High

CAN1 - IF2 Data B1 Low

CAN1 - IF2 Data B1 High

CAN1 - IF2 Data B2 Low

CAN1 - IF2 Data B2 High

000856H-

00087FH

Reserved

-

000880H

000881H

000882H

000883H

CAN1 - Transmission Request 1 Register Low

CAN1 - Transmission Request 1 Register High

CAN1 - Transmission Request 2 Register Low

CAN1 - Transmission Request 2 Register High

TREQR1L1

TREQR1H1

TREQR2L1

TREQR2H1

TREQR11

TREQR21

R

000884H-

00088FH

Reserved

-

000890H

000891H

000892H

000893H

CAN1 - New Data 1 Register Low

CAN1 - New Data 1 Register High

CAN1 - New Data 2 Register Low

CAN1 - New Data 2 Register High

NEWDT1L1

NEWDT1H1

NEWDT2L1

NEWDT2H1

NEWDT11

NEWDT21

R

000894H-

00089FH

Reserved

-

0008A0H

0008A1H

0008A2H

0008A3H

CAN1 - Interrupt Pending 1 Register Low

CAN1 - Interrupt Pending 1 Register High

CAN1 - Interrupt Pending 2 Register Low

CAN1 - Interrupt Pending 2 Register High

INTPND1L1

INTPND1H1

INTPND2L1

INTPND2H1

INTPND11

INTPND21

R

0008A4H-

0008AFH

Reserved

-

66

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (38 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0008B0H

0008B1H

0008B2H

0008B3H

CAN1 - Message Valid 1 Register Low

CAN1 - Message Valid 1 Register High

CAN1 - Message Valid 2 Register Low

CAN1 - Message Valid 2 Register High

MSGVAL1L1

MSGVAL1H1

MSGVAL2L1

MSGVAL2H1

MSGVAL11

R

MSGVAL21

0008B4H-

0008CDH

Reserved

-

RW

-

0008CEH

CAN1 - Output enable register

Reserved

COER1

0008CFH-

0008FFH

000900H

000901H

000902H

000903H

000904H

000905H

000906H

000907H

000908H

000909H

00090AH

00090BH

00090CH

00090DH

CAN2 - Control register Low

CTRLRL2

CTRLRH2

STATRL2

STATRH2

ERRCNTL2

ERRCNTH2

BTRL2

CTRLR2

STATR2

ERRCNT2

BTR2

RW

R

CAN2 - Control register High (reserved)

CAN2 - Status register Low

RW

R

CAN2 - Status register High (reserved)

CAN2 - Error Counter Low (Transmit)

CAN2 - Error Counter High (Receive)

CAN2 - Bit Timing Register Low

CAN2 - Bit Timing Register High

CAN2 - Interrupt Register Low

R

RW

R

BTRH2

INTRL2

INTR2

CAN2 - Interrupt Register High

INTRH2

R

CAN2 - Test Register Low

TESTRL2

TESTRH2

BRPERL2

BRPERH2

TESTR2

BRPER2

RW

R

CAN2 - Test Register High (reserved)

CAN2 - BRP Extension register Low

CAN2 - BRP Extension register High (reserved)

RW

R

00090EH-

00090FH

Reserved

-

000910H

000911H

000912H

CAN2 - IF1 Command request register Low

CAN2 - IF1 Command request register High

CAN2 - IF1 Command Mask register Low

IF1CREQL2

IF1CREQH2

IF1CMSKL2

IF1CREQ2

IF1CMSK2

RW

CAN2 - IF1 Command Mask register High (re-

served)

000913H

000914H

IF1CMSKH2

IF1MSK1L2

R

CAN2 - IF1 Mask 1 Register Low

IF1MSK12

RW

2008-2-7

67

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (39 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

000915H

000916H

000917H

000918H

000919H

00091AH

00091BH

00091CH

00091DH

00091EH

00091FH

000920H

000921H

000922H

000923H

000924H

000925H

CAN2 - IF1 Mask 1 Register High

CAN2 - IF1 Mask 2 Register Low

CAN2 - IF1 Mask 2 Register High

CAN2 - IF1 Arbitration 1 Register Low

CAN2 - IF1 Arbitration 1 Register High

CAN2 - IF1 Arbitration 2 Register Low

CAN2 - IF1 Arbitration 2 Register High

CAN2 - IF1 Message Control Register Low

CAN2 - IF1 Message Control Register High

CAN2 - IF1 Data A1 Low

IF1MSK1H2

IF1MSK2L2

IF1MSK2H2

IF1ARB1L2

IF1ARB1H2

IF1ARB2L2

IF1ARB2H2

IF1MCTRL2

IF1MCTRH2

IF1DTA1L2

IF1DTA1H2

IF1DTA2L2

IF1DTA2H2

IF1DTB1L2

IF1DTB1H2

IF1DTB2L2

IF1DTB2H2

RW

IF1MSK22

IF1ARB12

IF1ARB22

IF1MCTR2

IF1DTA12

IF1DTA22

IF1DTB12

IF1DTB22

RW

CAN2 - IF1 Data A1 High

CAN2 - IF1 Data A2 Low

CAN2 - IF1 Data A2 High

CAN2 - IF1 Data B1 Low

CAN2 - IF1 Data B1 High

CAN2 - IF1 Data B2 Low

CAN2 - IF1 Data B2 High

000926H-

00093FH

Reserved

-

000940H

000941H

000942H

CAN2 - IF2 Command request register Low

CAN2 - IF2 Command request register High

CAN2 - IF2 Command Mask register Low

IF2CREQL2

IF2CREQH2

IF2CMSKL2

IF2CREQ2

IF2CMSK2

RW

CAN2 - IF2 Command Mask register High (re-

served)

000943H

IF2CMSKH2

R

000944H

000945H

000946H

000947H

000948H

000949H

00094AH

CAN2 - IF2 Mask 1 Register Low

CAN2 - IF2 Mask 1 Register High

CAN2 - IF2 Mask 2 Register Low

CAN2 - IF2 Mask 2 Register High

CAN2 - IF2 Arbitration 1 Register Low

CAN2 - IF2 Arbitration 1 Register High

CAN2 - IF2 Arbitration 2 Register Low

IF2MSK1L2

IF2MSK1H2

IF2MSK2L2

IF2MSK2H2

IF2ARB1L2

IF2ARB1H2

IF2ARB2L2

IF2MSK12

IF2MSK22

IF2ARB12

IF2ARB22

RW

68

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (40 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

00094BH

00094CH

00094DH

00094EH

00094FH

000950H

000951H

000952H

000953H

000954H

000955H

CAN2 - IF2 Arbitration 2 Register High

CAN2 - IF2 Message Control Register Low

CAN2 - IF2 Message Control Register High

CAN2 - IF2 Data A1 Low

IF2ARB2H2

IF2MCTRL2

IF2MCTRH2

IF2DTA1L2

IF2DTA1H2

IF2DTA2L2

IF2DTA2H2

IF2DTB1L2

IF2DTB1H2

IF2DTB2L2

IF2DTB2H2

RW

IF2MCTR2

IF2DTA12

IF2DTA22

IF2DTB12

IF2DTB22

RW

CAN2 - IF2 Data A1 High

CAN2 - IF2 Data A2 Low

CAN2 - IF2 Data A2 High

CAN2 - IF2 Data B1 Low

CAN2 - IF2 Data B1 High

CAN2 - IF2 Data B2 Low

CAN2 - IF2 Data B2 High

000956H-

00097FH

Reserved

-

000980H

000981H

000982H

000983H

CAN2 - Transmission Request 1 Register Low

CAN2 - Transmission Request 1 Register High

CAN2 - Transmission Request 2 Register Low

CAN2 - Transmission Request 2 Register High

TREQR1L2

TREQR1H2

TREQR2L2

TREQR2H2

TREQR12

TREQR22

R

000984H-

00098FH

Reserved

-

000990H

000991H

000992H

000993H

CAN2 - New Data 1 Register Low

CAN2 - New Data 1 Register High

CAN2 - New Data 2 Register Low

CAN2 - New Data 2 Register High

NEWDT1L2

NEWDT1H2

NEWDT2L2

NEWDT2H2

NEWDT12

NEWDT22

R

000994H-

00099FH

Reserved

-

0009A0H

0009A1H

0009A2H

0009A3H

CAN2 - Interrupt Pending 1 Register Low

CAN2 - Interrupt Pending 1 Register High

CAN2 - Interrupt Pending 2 Register Low

CAN2 - Interrupt Pending 2 Register High

INTPND1L2

INTPND1H2

INTPND2L2

INTPND2H2

INTPND12

INTPND22

R

0009A4H-

0009AFH

Reserved

-

2008-2-7

69

MB96330 Series

FME-MB96330 rev 2

I/O map MB96(F)33x (41 / 41)

Address

Abbreviation

8-bit access

Abbreviation

Access

Register

16-bit access

0009B0H

0009B1H

0009B2H

0009B3H

CAN2 - Message Valid 1 Register Low

CAN2 - Message Valid 1 Register High

CAN2 - Message Valid 2 Register Low

CAN2 - Message Valid 2 Register High

MSGVAL1L2

MSGVAL1H2

MSGVAL2L2

MSGVAL2H2

MSGVAL12

R

MSGVAL22

0009B4H-

0009CDH

Reserved

-

RW

-

0009CEH

CAN2 - Output enable register

Reserved

COER2

0009CFH-

000BFFH

70

2008-2-7

MB96330 Series

FME-MB96330 rev 2

■ INTERRUPT VECTOR TABLE

Interrupt vector table MB96(F)33x (1 / 5)

Offset in

Vector

number

Index in

ICR to

program

Cleared

by DMA

vector ta-

ble

Vector name

Description

0

3FC

3F8

3F4

3F0

3EC

3E8

3E4

3E0

3DC

3D8

3D4

3D0

3CC

3C8

3C4

3C0

3BC

3B8

3B4

3B0

3AC

3A8

3A4

3A0

39C

398

394

390

CALLV0

CALLV1

CALLV2

CALLV3

CALLV4

CALLV5

CALLV6

CALLV7

RESET

No

Yes

-

1

2

-

3

-

4

-

5

-

6

-

7

-

8

-

9

INT9

-

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

EXCEPTION

NMI

-

Non-Maskable Interrupt

DLY

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

Delayed Interrupt

RC Timer

RC_TIMER

MC_TIMER

SC_TIMER

PLL_UNLOCK

EXTINT0

EXTINT1

EXTINT2

EXTINT3

EXTINT4

EXTINT5

EXTINT6

EXTINT7

EXTINT8

EXTINT9

EXTINT10

Main Clock Timer

Sub Clock Timer

Reserved

External Interrupt 0

External Interrupt 1

External Interrupt 2

External Interrupt 3

External Interrupt 4

External Interrupt 5

External Interrupt 6

External Interrupt 7

External Interrupt 8

External Interrupt 9

External Interrupt 10

2008-2-7

71

MB96330 Series

FME-MB96330 rev 2

Interrupt vector table MB96(F)33x (2 / 5)

Offset in

Vector

number

Index in

ICR to

program

Cleared

by DMA

vector ta-

ble

Vector name

Description

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

38C

388

384

380

37C

378

374

370

36C

368

364

360

35C

358

354

350

34C

348

344

340

33C

338

334

330

32C

328

324

320

31C

EXTINT11

EXTINT12

EXTINT13

EXTINT14

EXTINT15

CAN0

Yes

No

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

External Interrupt 11

External Interrupt 12

External Interrupt 13

External Interrupt 14

External Interrupt 15

CAN Controller 0

CAN1

No

CAN Controller 1

CAN2

No

CAN Controller 2

PPG0

Yes

Programmable Pulse Generator 0

Programmable Pulse Generator 1

Programmable Pulse Generator 2

Programmable Pulse Generator 3

Programmable Pulse Generator 4

Programmable Pulse Generator 5

Programmable Pulse Generator 6

Programmable Pulse Generator 7

Programmable Pulse Generator 8

Programmable Pulse Generator 9

Programmable Pulse Generator 10

Programmable Pulse Generator 11

Programmable Pulse Generator 12

Programmable Pulse Generator 13

Programmable Pulse Generator 14

Programmable Pulse Generator 15

Programmable Pulse Generator 16

Programmable Pulse Generator 17

Programmable Pulse Generator 18

Programmable Pulse Generator 19

Reload Timer 0

PPG1

PPG2

PPG3

PPG4

PPG5

PPG6

PPG7

PPG8

PPG9

PPG10

PPG11

PPG12

PPG13

PPG14

PPG15

PPG16

PPG17

PPG18

PPG19

RLT0

72

2008-2-7

MB96330 Series

FME-MB96330 rev 2

Interrupt vector table MB96(F)33x (3 / 5)

Offset in

Vector

number

Index in

ICR to

program

Cleared

by DMA

vector ta-

ble

Vector name

Description

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

318

314

310

30C

308

304

300

2FC

2F8

2F4

2F0

2EC

2E8

2E4

2E0

2DC

2D8

2D4

2D0

2CC

2C8

2C4

2C0

2BC

2B8

2B4

2B0

2AC

2A8

RLT1

RLT2

Yes

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

Reload Timer 1

Reload Timer 2

RLT3

Reload Timer 3

PPGRLT

ICU0

Reload Timer 6 - dedicated for PPG

Input Capture Unit 0

Input Capture Unit 1

Input Capture Unit 2

Input Capture Unit 3

Input Capture Unit 4

Input Capture Unit 5

Input Capture Unit 6

Input Capture Unit 7

Input Capture Unit 8

Input Capture Unit 9

Output Compare Unit 0

Output Compare Unit 1

Output Compare Unit 2

Output Compare Unit 3

Output Compare Unit 4

Output Compare Unit 5

Output Compare Unit 6

Output Compare Unit 7

Output Compare Unit 8

Output Compare Unit 9

Output Compare Unit 10

Output Compare Unit 11

Free Running Timer 0

Free Running Timer 1

Free Running Timer 2

ICU1

ICU2

ICU3

ICU4

ICU5

ICU6

ICU7

ICU8

ICU9

OCU0

OCU1

OCU2

OCU3

OCU4

OCU5

OCU6

OCU7

OCU8

OCU9

OCU10

OCU11

FRT0

FRT1

FRT2

2008-2-7

73

MB96330 Series

FME-MB96330 rev 2

Interrupt vector table MB96(F)33x (4 / 5)

Offset in

Vector

number

Index in

ICR to

program

Cleared

by DMA

vector ta-

ble

Vector name

Description

86

87

2A4

2A0

29C

298

294

290

28C

288

284

280

27C

278

274

270

26C

268

264

260

25C

258

254

250

24C

248

244

FRT3

RTC0

Yes

No

86

87

Free Running Timer 3

Real Timer Clock

Clock Calibration Unit

I2C interface

88

CAL0

No

88

89

IIC0

Yes

No

89

90

IIC1

90

I2C interface

91

ADC0

ALARM0

ALARM1

LINR0

LINT0

LINR1

LINT1

LINR2

LINT2

LINR3

LINT3

LINR5

LINT5

LINR7

LINT7

LINR8

LINT8

LINR9

LINT9

FLASH_A

91

A/D Converter

92

Alarm Comparator 0

Alarm Comparator 1

LIN USART 0 RX

LIN USART 0 TX

LIN USART 1 RX

LIN USART 1 TX

LIN USART 2 RX

LIN USART 2 TX

LIN USART 3 RX

LIN USART 3 TX

LIN USART 5 RX

LIN USART 5 TX

LIN USART 7 RX

LIN USART 7 TX

LIN USART 8 RX

LIN USART 8 TX

LIN USART 9 RX

LIN USART 9 TX

93

No

93

94

Yes

No

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

100

101

102

103

104

105

106

107

108

109

110

Main Flash memory interrupt (only

Flash devices)

111

112

113

114

240

23C

238

234

reserved

USB_EP0IN0

USB_EP0OUT0

USB_EP10

-

reserved

Yes

112

113

114

USB End point 0 IN

USB End point 0 OUT

USB End point 1

2008-2-7

74

MB96330 Series

FME-MB96330 rev 2

Interrupt vector table MB96(F)33x (5 / 5)

Offset in

Vector

number

Index in

ICR to

program

Cleared

by DMA

vector ta-

ble

Vector name

Description

115

116

117

118

119

230

22C

228

224

220

USB_EP20

USB_EP30

USB_EP40

USB_EP50

USB_F10

Yes

No

115

116

117

118

119

USB End point 2

USB End point 3

USB End point 4

USB End point 5

USB function Flags 1 (SUSP SOF

BRST WKUP CONF)

120

121

21C

218

USB_F20

USB_H10

No

120

121

USB function Flags 2 (SPK)

USB MiniHost 1 (DIRQ CNNIRQ URIRQ

RWKIRQ)

122

214

USB_H20

No

122

USB MiniHost 2 (SOFIRQ CMPIRQ)

2008-2-7

75

MB96330 Series

FME-MB96330 rev 2

76

2008-2-7

MB96330 Series

FME-MB96330 rev 2

■ HANDLING DEVICES

Special care is required for the following when handling the device:

• Latch-up prevention

• Unused pins handling

• External clock usage

• Unused sub clock signal

• Notes on PLL clock mode operation

• Power supply pins (VCC/VSS)

• Crystal oscillator circuit

• Turn on sequence of power supply to A/D converter and analog inputs

• Pin handling when not using the A/D converter

• Notes on energization

• Stabilization of power supply voltage

1. Latch-up prevention

• CMOS IC chips may suffer latch-up under the following conditions:

• A voltage higher than VCC or lower than VSS is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between V^CCand VSS.

• The AVCC power supply is applied before the VCC voltage.

• Latch-up may increase the power supply current dramatically, causing thermal damages to the device.

• For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed

the digital power-supply voltage.

2. Unused pins handling

• Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register

PIER = 0).

• Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent

damage of the device. They must therefore be pulled up or pulled down through resistors. To prevent latch-

up, those resistors should be more than 2 kΩ.

• Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with

either input disabled or external pull-up/pull-down resistor as described above.

3. External clock usage

• The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC

Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be

connected as follows:

1. Single phase external clock

• When using a single phase external clock, X0 pin must be driven and X1 pin left open.

X0

X1

2. Opposite phase external clock

2008-2-7

77

MB96330 Series

FME-MB96330 rev 2

• When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the

opposite phase to the X0 (X0A) pins.

X0

X1

4. Unused sub clock signal

• If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the

X0A pin and the X1A pin must be left open.

5. Notes on PLL clock mode operation

• If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the

microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot

be guaranteed.

6. Power supply pins (VCC/VSS

)

• It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is

more than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed

operating range.

• VCC and VSS must be connected to the device from the power supply with lowest possible impedance.

• As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 µF

between VCC and VSS as close as possible to VCC and VSS pins.

7. Crystal oscillator circuit

• Noise at X0 or X1 pins might cause abnormal operation. It is required to provide bypass capacitors with

shortest possible distance to X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and, to

the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits.

• It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground

area for stabilizing the operation.

• It is highly recommended to evaluate the quartz/MCU system at the quartz manufacturer.

8. Turn on sequence of power supply to A/D converter and analog inputs

• It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after

turning the digital power supply (VCC) on.

• It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In

this case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies

simultaneously on or off is acceptable).

9. Pin handling when not using the A/D converter

• It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS.

10. Notes on energization

• To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply

on should be slower than 50µs from 0.2 V to 2.7 V.

78

2008-2-7

MB96330 Series

FME-MB96330 rev 2

11. Stabilization of power supply voltage

• If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply

voltage, a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization

guidelines, the power supply voltage must be stabilized in such a way that Vcc ripple fluctuations (peak to

peak value) in the commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply

voltage and the transient fluctuation rate becomes 0.1V/µs or less in instantaneous fluctuation for power

supply switching.

2008-2-7

79

MB96330 Series

FME-MB96330 rev 2

80

2008-2-7

MB96330 Series

FME-MB96330 rev 2

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

VCC

AVCC

VCC3

VSS - 0.3 VSS + 6.0

VSS - 0.3 VSS + 4.0

V

Power supply voltage

*1

VCC = AVCC

USB power supply voltage

AD Converter voltage references

Input voltage

USB device only

AVRH,

AVRL

AVCC ≥ AVRH, AVCC ≥ AVRL,

AVRH > AVRL, AVRL ≥ AVSS

VSS - 0.3 VSS + 6.0

V

*2

VI

VI ≤ VCC + 0.3V

Vcc3 + 0.5,

USB Input voltage

VIUSB

V^O

VSS - 0.3

4.0

USB pins UDP, UDM

VO ≤ VCC + 0.3V ^*2

Output voltage

VSS - 0.3 VSS + 6.0

Vcc3 + 0.5,

USB output voltage

VOUSB

VSS - 0.3

4.0

USB pins UDP, UDM

Applicable to general purpose I/

O pins ^*3

Maximum Clamp Current

ICLAMP

-4.0

+4.0

mA

Applicable to general purpose I/

O pins ^*3

Total Maximum Clamp Current

“L” level maximum output current

Σ|ICLAMP|

-

40

15

IOL1

mA Normal outputs with driving

strength set to 5mA

IOLUSB

IOLAV1

-

36

5

mA USB pins UDP, UDM

“L” level average output current

mA Normal outputs with driving

strength set to 5mA

IOLAVUSB

ΣIOL1

-

15

100

50

mA USB pins UDP, UDM

mA Normal outputs

“L” level maximum overall output current

“L” level average overall output current

”H” level maximum output current

ΣIOLAV1

IOH1

-15

mA Normal outputs with driving

strength set to 5mA

IOHUSB

IOHAV1

-

-36

-5

mA USB pins UDP, UDM

”H” level average output current

mA Normal outputs with driving

strength set to 5mA

IOHAVUSB

ΣIOH1

-

-15

-100

-50

mA USB pins UDP, UDM

mA Normal outputs

mW

”H” level maximum overall output current

”H” level average overall output current

Permitted Power dissipation ^*4

ΣIOHAV1

PD

TBD^*5

2008-2-7

81

MB96330 Series

FME-MB96330 rev 2

Rating

Max

Parameter

Symbol

Unit

Remarks

Min

0

+70

MB96V300B

^oC

-40

-55

+105

+125

+150

MB96(F)338

Operating ambient temperature

Storage temperature

TA

MB96(F)338Y/R^*6

TSTG

*1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage

at the analog inputs does not exceed AVCC neither when the power is switched on.

*2: VI and VO should not exceed VCC + 0.3 V. VI should also not exceed the speciﬁed ratings. However if the

maximum current to/from a input is limited by some means with external components, the ICLAMP rating super-

sedes the VI rating. Input/output voltages of standard ports depend on VCC.

*3: • Applicable to all general purpose I/O pins (Pnn_m)

• Use within recommended operating conditions.

• Use at DC voltage (current)

• The +B signal should always be applied a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect

other devices.

• Note that if a +B signal is input when the microcontroller power supply is off (not ﬁxed at 0 V), the power

supply is provided from the pins, so that incomplete operation may result.

• Notethatifthe+Binputisappliedduringpower-on, thepowersupplyisprovidedfromthepinsandtheresulting

supply voltage may not be sufﬁcient to operate the Power reset (except devices with persistent low voltage

reset in internal vector mode).

• Sample recommended circuits:

Protective Diode

VCC

Limiting

resistance

P-ch

N-ch

+B input (0V to 16V)

R

*4: The maximum permitted power dissipation depends on the ambient temperature, the air ﬂow velocity and the

thermal conductance of the package on the PCB.

The actual power dissipation depends on the customer application and can be calculated as follows:

P^D= PIO + PINT

PIO = ∑ (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports)

PINT = VCC * (ICC + IA) (internal power dissipation)

82

2008-2-7

MB96330 Series

FME-MB96330 rev 2

ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the

selected operation mode and clock frequency and the usage of functions like Flash programming or the clock

modulator.

IA is the analog current consumption into AVCC.

*5: Worst case value for a package mounted on single layer PCB at speciﬁed TA without air ﬂow.

*6: Please contact Fujitsu for reliability limitations when using under these conditions.

2008-2-7

83

MB96330 Series

FME-MB96330 rev 2

84

2008-2-7

MB96330 Series

FME-MB96330 rev 2

2. Recommended Conditions

Value

Typ

-

Parameter

Symbol

Unit

Remarks

Min

Max

Power supply voltage

VCC

3.0

5.5

V

Use a low inductance capacitor

Smoothing capacitor at C

CS

4.7

-

10

µF (for example X7R ceramic ca-

pacitor)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the devices electrical characteristics are guaranteed when the device is

operated within these ranges.

Semiconductor devices must always be operated within their recommended operating condition ranges. Oper-

ation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data

sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU repre-

sentatives beforehand.

2008-2-7

85

MB96330 Series

FME-MB96330 rev 2

86

2008-2-7

MB96330 Series

FME-MB96330 rev 2

3. DC characteristics

(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Value

Typ

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

Input “H“ voltage

CMOSHysteresis

0.8/0.2 input se-

lected

0.8

VCC

VCC +

0.3

-

V

0.7

VCC +

-

V

VCC ≥ 4.5V

VCC < 4.5V

CMOSHysteresis

0.7/0.3 input se-

lected

VCC

0.3

Port inputs

Pnn_m

0.74

VCC

VCC +

0.3

VIH

AUTOMOTIVE

Hysteresis input

selected

0.8

VCC

VCC +

0.3

-

V

TTL input select-

ed

VCC +

2.0

-

V

0.3

VCC3 +

0.3

V^IHUSB

UDP, UDM

-

USB pins

External clock in

“Fast Clock Input

mode”

0.8

VCC +

-

VIHX0F

X0

V

VCC

0.3

X0,X1,

External clock in

X0A,X1A “oscillation mode”

VCC +

0.3

2.5

VIHX0S

V

CMOS Hysteresis in-

put

0.8

VCC

VCC +

0.3

-

VIHR

VIHM

RSTX

-

VCC -

0.3

VCC +

0.3

MD2-MD0

2008-2-7

87

MB96330 Series

FME-MB96330 rev 2

(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Value

Typ

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

Input “L” voltage

CMOSHysteresis

0.8/0.2 input se-

lected

VSS -

0.2

-

V

0.3

VCC

CMOSHysteresis

0.7/0.3 input se-

lected

VSS -

0.3

VCC

V

Port inputs

Pnn_m

VIL

VSS -

0.3

0.5

VCC

-

VCC ≥ 4.5V

AUTOMOTIVE

Hysteresis input

selected

VSS -

0.3

0.46

VCC

VCC < 4.5V

TTL input select-

ed

VSS -

-

0.8

V

0.3

-0.3

VILUSB

VILX0F

UDP, UDM

X0

-

USB pins

External clock in

“Fast Clock Input

mode”

VSS -

-

0.2 VCC

V

0.3

X0,X1,

External clock in

VSS -

0.3

0.5

VILX0S

V

X0A,X1A “oscillation mode”

CMOS Hysteresis in-

put

VSS -

0.3

-

0.2 VCC

VILR

VILM

RSTX

-

VSS -

0.3

VSS +

0.3

MD2-MD0

4.5V ≤ VCC ≤ 5.5V

I^OH= -2mA

Output“H”voltage

Normal

outputs

Driving strength set

to 2mA

V^CC-

0.5

-

VOH2

VOH5

V

3.0V ≤ VCC < 4.5V

I^OH= -1.6mA

4.5V ≤ VCC ≤ 5.5V

I^OH= -5mA

Normal

outputs

Driving strength set

to 5mA

V^CC-

0.5

3.0V ≤ VCC < 4.5V

I^OH= -3mA

4.5V ≤ VCC ≤ 5.5V

I^OH= -3mA

V^CC-

0.5

I²C outputs

UDP, UDM

-

VOH3

V

3.0V ≤ VCC < 4.5V

I^OH= -2mA

3.0V ≤ VCC3 < 3.6V

I^OH= -100µA

V^CC3-

0.2

VOHUSB

-

USB pins

88

2008-2-7

MB96330 Series

FME-MB96330 rev 2

(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Value

Typ

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

4.5V ≤ VCC ≤ 5.5V

I^OL= +2mA

Output “L” voltage

Normal

outputs

Driving strength set

to 2mA

-

0.4

VOL2

V

3.0V ≤ VCC < 4.5V

I^OL= +1.6mA

4.5V ≤ VCC ≤ 5.5V

I^OL= +5mA

Normal

outputs

Driving strength set

to 5mA

-

0.4

VOL5

VOL3

V

3.0V ≤ VCC < 4.5V

I^OL= +3mA

4.5V ≤ VCC ≤ 5.5V

I^OL= +3mA

I²C outputs

3.0V ≤ VCC < 4.5V

I^OL= +2mA

3.0V ≤ VCC3 < 3.6V

I^OL= 100µA

0.3

+1

VOLUSB

IIL

UDP, UDM

Pnn_m

-

V

USB pins

VCC = 5.5V

Input leak current

Pull-up resistance

-1

µA

V^SS< VI < VCC

VCC3 = 3.6V

-5

-

+5

UDP, UDM

µA USB pins

kΩ

V^SS< VI < VCC3

Pnn_m,

RSTX

-

25

50

100

RUP

2008-2-7

89

MB96330 Series

FME-MB96330 rev 2

(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Value

Parameter

Symbol

Condition

temp

Remarks

Typ

Max Unit

35

44

25˚C

125˚C

25˚C

CLKRC and CLKSC

stopped. Core voltage at

1.9V

PLL Run mode with

CLKS1/2 = 48MHz,

CLKB = CLKP1/2/3 =

24MHz

Power supply cur-

rent in Run

modes*

ICCPLL

mA

47

0 Flash/ROM wait states

36

44

CLKRC and CLKSC

stopped. Core voltage at

1.9V

57

PLL Run mode with

CLKS1/2 = CLKB =

CLKP1/3 = 48MHz,

CLKP2 = 24MHz

mA

60

2 Flash/ROM wait states

45

125˚C

25˚C

CLKRC and CLKSC

stopped. Core voltage at

1.9V

PLL Run mode with

CLKS1/2 = 96MHz,

CLKB = CLKP1/3 =

48MHz, CLKP2 =

24MHz

49

62

mA

65

1 Flash/ROM wait state

50

125˚C

25˚C

4.5

5.1

2.9

3.5

5.5

mA

8.5

CLKPLL, CLKSC and

CLKRC stopped

Main Run mode with

CLKS1/2 = CLKB =

CLKP1/2/3 = 4MHz

I^CCMAIN

1 Flash/ROM wait state

125˚C

25˚C

4

CLKMC, CLKPLL and

CLKSC stopped

RC Run mode with

CLKS1/2 = CLKB =

CLKP1/2/3 = 2MHz

ICCRCH

mA

6.5

1 Flash/ROM wait state

125˚C

90

2008-2-7

MB96330 Series

FME-MB96330 rev 2

(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Value

Parameter

Symbol

Condition

temp

Remarks

Typ

Max Unit

CLKMC, CLKPLL and

CLKSC stopped. Volt-

age regulator in high

power mode

0.4

0.6

mA

3.5

25˚C

RC Run mode with

CLKS1/2 = CLKB =

CLKP1/2/3 = 100kHz,

SMCR:LPMS = 0

Power supply cur-

rent in Run

modes*

0.9

125˚C

1 Flash/ROM wait state

ICCRCL

CLKMC, CLKPLL and

CLKSC stopped. Volt-

age regulator in low pow-

er mode, no Flash pro-

gramming/erasing

allowed.

0.15 0.25

25˚C

RC Run mode with

CLKS1/2 = CLKB =

CLKP1/2/3 = 100kHz,

SMCR:LPMS = 1

mA

0.65

3.2

125˚C

1 Flash/ROM wait state

CLKMC, CLKPLL and

CLKRC stopped, no

Flash programming/

erasing allowed.

0.1

0.6

0.2

3

25˚C

Sub Run mode with

CLKS1/2 = CLKB =

CLKP1/2/3 = 32kHz

I^CCSUB

125˚C

1 Flash/ROM wait state

2008-2-7

91

MB96330 Series

FME-MB96330 rev 2

(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Value

Parameter

Symbol

Condition

temp

Remarks

Typ

Max Unit

9

10.5

mA

13

25˚C

125˚C

25˚C

Power supply cur-

rent in Sleep

modes*

PLL Sleep mode with

CLKS1/2 = 48MHz,

CLKP1/2/3 = 24MHz

CLKRC and CLKSC

stopped. Core voltage at

1.9V

ICCSPLL

9.7

14

15.5

mA

18

CLKRC and CLKSC

stopped. Core voltage at

1.9V

PLL Sleep mode with

CLKS1/2 = CLKP1/3 =

48MHz, CLKP2 =

24MHz

14.8

14

125˚C

25˚C

15.5

mA

18

CLKRC and CLKSC

stopped. Core voltage at

1.9V

PLL Sleep mode with

CLKS1/2 = 96MHz,

CLKP1 = 48MHz,

CLKP2 = 24MHz

14.8

1.5

2

125˚C

25˚C

1.8

mA

4.5

Main Sleep mode with

CLKS1/2 = CLKP1/2/3 =

4MHz

CLKPLL, CLKSC and

CLKRC stopped

I^CCSMAIN

125˚C

25˚C

0.8

1.4

1.3

mA

4

RC Sleep mode with

CLKS1/2 = CLKP1/2/3 =

2MHz

CLKMC, CLKPLL and

CLKSC stopped

ICCSRCH

125˚C

92

2008-2-7

MB96330 Series

FME-MB96330 rev 2

(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Value

Parameter

Symbol

Condition

temp

Remarks

Typ

Max Unit

0.3

0.5

mA

3.4

25˚C

RC Sleep mode with

CLKS1/2 = CLKP1/2/3 =

100kHz,

CLKMC, CLKPLL and

CLKSC stopped. Volt-

age regulator in high

power mode

Power supply cur-

rent in Sleep

modes*

SMCR:LPMSS = 0

0.8

125˚C

ICCSRCL

0.06 0.15

25˚C

RC Sleep mode with

CLKS1/2 = CLKP1/2/3 =

100kHz,

CLKMC, CLKPLL and

CLKSC stopped. Volt-

age regulator in low pow-

er mode

mA

SMCR:LPMSS = 1

0.56

3

125˚C

0.04 0.12

25˚C

Sub Sleep mode with

CLKS1/2 = CLKP1/2/3 =

32kHz

CLKMC, CLKPLL and

CLKRC stopped

I^CCSSUB

0.54

2.9

125˚C

2008-2-7

93

MB96330 Series

FME-MB96330 rev 2

(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Value

Parameter

Symbol

Condition

temp

Remarks

Typ

Max Unit

1.6

2

25˚C

125˚C

25˚C

PLL Timer mode with

CLKMC = 4MHz, CLK-

PLL = MHz

CLKRC and CLKSC

stopped. Core voltage at

1.9V

ICCTPLL

mA

4.8

2.1

0.35

0.85

0.1

0.5

mA

3.3

CLKPLL, CLKRC and

CLKSC stopped. Volt-

age regulator in high

power mode

Main Timer mode with

CLKMC = 4MHz,

SMCR:LPMSS = 0

125˚C

25˚C

ICCTMAIN

ICCTRCH

I^CCTRCL

0.15

mA

2.9

CLKPLL, CLKRC and

CLKSC stopped. Volt-

age regulator in low pow-

er mode

Main Timer mode with

CLKMC = 4MHz,

SMCR:LPMSS = 1

0.6

125˚C

25˚C

0.35

0.85

0.1

0.5

mA

3.3

CLKMC, CLKPLL and

CLKSC stopped. Volt-

age regulator in high

power mode

Power supply cur-

rent in Timer

modes*

RC Timer mode with

CLKRC = 2MHz,

SMCR:LPMSS = 0

125˚C

25˚C

0.15

mA

2.9

CLKMC, CLKPLL and

CLKSC stopped. Volt-

age regulator in low pow-

er mode

RC Timer mode with

CLKRC = 2MHz,

SMCR:LPMSS = 1

0.6

125˚C

25˚C

0.3

0.45

mA

3.2

CLKMC, CLKPLL and

CLKSC stopped. Volt-

age regulator in high

power mode

RC Timer mode with

CLKRC = 100kHz,

SMCR:LPMSS = 0

0.8

125˚C

25˚C

0.05

0.55

0.1

mA

2.8

CLKMC, CLKPLL and

CLKSC stopped. Volt-

age regulator in low pow-

er mode

RC Timer mode with

CLKRC = 100kHz,

SMCR:LPMSS = 1

125˚C

94

2008-2-7

MB96330 Series

FME-MB96330 rev 2

(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Value

Parameter

Symbol

Condition

temp

Remarks

Typ

Max Unit

0.03

0.1

mA

2.8

25˚C

Power supply cur-

rent in Timer

modes*

Sub Timer mode with

CLKSC = 32kHz

CLKMC, CLKPLL and

CLKRC stopped

I^CCTSUB

0.53

125˚C

0.02 0.08

0.52 2.8

0.015 0.06

25˚C

125˚C

25˚C

VRCR:LPMB[2:0] =

“110”

mA

Core voltage at 1.8V

Core voltage at 1.2V

Stop Mode

I^CCH

VRCR:LPMB[2:0] =

“000”

0.4

2.3

125˚C

90

140

25˚C

Power supply cur-

rentforactiveLow

Voltage detector

This current must be

added to all Power sup-

ply currents above

Low voltage detector en-

abled (RCR:LVDE=’1’)

I^CCLVD

µA

100

150

125˚C

Clock modulator

current

Clock modulator en-

abled (CMCR:PDX = ‘1’)

Must be added to all cur-

rent above

I^CCCLOMO

3

4.5

40

mA

-

FlashWrite/Erase

current

Current for one Flash

module

Must be added to all cur-

rent above

ICCFLASH

15

Other than C, AVCC,

AVSS, AVRH, AVRL, VCC,

VSS

Input capacitance

CIN

-

5

15

pF

* The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz

external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of

the Hardware Manual for further details about voltage regulator control.

2008-2-7

95

MB96330 Series

FME-MB96330 rev 2

96

2008-2-7

MB96330 Series

FME-MB96330 rev 2

4. AC Characteristics

Source Clock timing

(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Value

Parameter

Symbol

Unit

Remarks

Min

Typ

Max

3

-

16

MHz Whenusinganoscillationcircuit, PLLoff

When using an opposite phase external

clock, PLL off

0

3.5

0

-

16

48

MHz

Clock frequency

fC

X0, X1

When using an oscillation circuit or op-

MHz

posite phase external clock, PLL on

When using a single phase external

MHz

clockin“FastClockInputmode”, PLLoff

Clock frequency

fFCI

f^CL

f^CR

X0

When using a single phase external

MHz

3.5

32

0

-

clockin“FastClockInputmode”, PLLon

32.768

-

100 kHz When using an oscillation circuit

X0A, X1A

X0A

When using an opposite phase external

100 kHz

clock

When using a single phase external

clock

0

50

1

-

50

kHz

When using slow frequency of RC oscil-

lator

100

200 kHz

Clock frequency

-

When using fast frequency of RC oscil-

lator

2

-

4

MHz

Permitted VCO output frequency of PLL

(CLKVCO)

fCLKVCO

-

50

8

200 MHz

Inputclockpulse

width

PWH, PWL

X0,X1

-

ns Duty ratio is about 30% to 70%

Inputclockpulse

width

PWHL, PWLL X0A,X1A

5

-

µs

2008-2-7

97

MB96330 Series

FME-MB96330 rev 2

tCYL

VIH

VIL

X0

PWH

PWL

tCYLL

VIH

VIL

X0A

PWHL

PWLL

98

2008-2-7

MB96330 Series

FME-MB96330 rev 2

Internal Clock timing

(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Core Voltage Settings

1.8V 1.9V

Parameter

Symbol

Unit

Remarks

Min

0

Max

Min

Max

96

Internal System clock fre-

quency (CLKS1 and

CLKS2)

fCLKS1, fCLKS2

92

0

MHz

Others than below

MB96F338

0

90

0

96

Internal CPU clock fre-

quency (CLKB), internal

peripheralclockfrequency

(CLKP1)

fCLKB, fCLKP1

0

52

0

56

MHz

Others than below

MB96F338

0

43.5

28

0

48

32

MHz

Internal peripheral clock

frequency (CLKP2)

fCLKP2

Internal peripheral clock

frequency (Clock CLKP3)

f^CLKP3

0

43.5

0

48

MHz

MB96F338

WARNING: For USB usage, it is important to change the voltage regulator setting to output 1.9V. Please refer

to the chapter Standby Mode and Voltage Regulator control circuit of the hardware manual to perform

such setting.

2008-2-7

99

MB96330 Series

FME-MB96330 rev 2

100

2008-2-7

MB96330 Series

FME-MB96330 rev 2

External Reset timing

(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Value

Typ

-

Parameter

Reset input time

Symbol

Unit

ns

Remarks

Min

Max

tRSTL

RSTX

500

-

tRSTL

RSTX

0.2 VCC

2008-2-7

101

MB96330 Series

FME-MB96330 rev 2

102

2008-2-7

MB96330 Series

FME-MB96330 rev 2

Power On Reset timing

(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Value

Parameter

Symbol

Unit

Remarks

Min

0.05

1

Typ

Max

30

-

Power on rise time

Power off time

tR

Vcc

-

ms

tOFF

tR

2.7V

VCC

0.2 V

tOFF

If the power supply is changed too rapidly, a power-on reset may occur.

We recommend a smooth startup by restraining voltages when changing the

power supply voltage during operation, as shown in the ﬁgure below.

VCC

3 V

Rising edge of 50 mV/ms

maximum is allowed

2008-2-7

103

MB96330 Series

FME-MB96330 rev 2

104

2008-2-7

MB96330 Series

FME-MB96330 rev 2

External Input timing

(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Value

Min

Used Pin input func-

Parameter Symbol

Condition

Unit

tion

Max

INTn

NMI

External Interrupt

NMI

200

⎯

ns

Pnn_m

TINn

General Purpose IO

Reload Timer

Input pulse

width

tINH

tINL

⎯

TTGn

ADTG

PPG Trigger input

AD Converter Trigger

2*tCLKP1 + 200

(tCLKP1=1/

f^CLKP1)

⎯

ns

Free Running Timer

external clock

FRCKn

INn

Input Capture

Note : Relocated Resource Inputs have same characteristics

VIH

External Pin input

VIL

tINH

tINL

2008-2-7

105

MB96330 Series

FME-MB96330 rev 2

106

2008-2-7

MB96330 Series

FME-MB96330 rev 2

External Bus timing

WARNING: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum

output timing described in the different tables must then be increased by 10ns.

Basic Timing

(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)

Value

Parameter

Symbol

Condition

Unit Remarks

Min

25

Max

⎯

tCYC

tCHCL

ECLK

⎯

tCYC/2-5

-20

tCYC/2+5

20

ns

tCLCH

tCHCBH

tCHCBL

tCLCBH

t^CLCBL

tCHLH

-20

20

ECLK →

UBX/ LBX / CSn time

CSn, UBX,

LBX, ECLK

⎯

ns

-20

20

-20

20

-10

10

tCHLL

-10

10

ECLK → ALE time

ALE, ECLK

tCLLH

-10

10

tCLLL

-10

10

tCHAV

tCLAV

-15

15

ECLK → address valid time

EBM:NMS=1

EBM:NMS=0

A[23:0], ECLK

ns

(non-multiplexed)

-15

15

tCHAV

tCLAV

-15

15

A[23:16],

ECLK

-15

15

ECLK → address valid time

(multiplexed)

tCLADV

tCHADV

tCHRWH

tCHRWL

tCLRWH

tCLRWL

-15

15

AD[15:0],

ECLK

-15

15

-10

10

RDX, WRX,

WRLX,WRHX,

ECLK

-10

10

ECLK → RDX /WRX time

⎯

ns

-10

10

-10

10

(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)

Value

Parameter

Symbol

Condition

Unit Remarks

Min

30

Max

⎯

tCYC

tCHCL

tCLCH

ECLK

⎯

tCYC/2-8

tCYC/2+8

ns

2008-2-7

107

MB96330 Series

FME-MB96330 rev 2

(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)

Value

Parameter

Symbol

Condition

Unit Remarks

Min

-25

-15

-20

-15

Max

25

15

20

15

tCHCBH

tCHCBL

tCLCBH

tCLCBL

tCHLH

ECLK →

CSn, UBX,

LBX, ECLK

⎯

ns

UBX/ LBX / CSn time

tCHLL

ECLK → ALE time

ALE, ECLK

⎯

ns

tCLLH

tCLLL

tCHAV

ECLK → address valid time

(non-multiplexed)

EBM:NMS=1

EBM:NMS=0

A[23:0], ECLK

ns

tCLAV

tCHAV

A[23:16],

ECLK

t^CLAV

ECLK → address valid time

(multiplexed)

tCLADV

tCHADV

tCHRWH

tCHRWL

tCLRWH

tCLRWL

AD[15:0],

ECLK

RDX, WRX,

WRLX, WRHX,

ECLK

ECLK → RDX /WRX time

⎯

ns

108

2008-2-7

MB96330 Series

FME-MB96330 rev 2

tCYC

tCHCL

tCLCH

0.8*Vcc

ECLK

0.2*Vcc

tCLAV

tCHAV

A[23:0]

tCHCBL

tCLCBL

tCHCBH

tCLCBH

CSn

LBX UBX

tCHRWL

tCLRWL

tCHRWH

tCLRWH

RDX

WRX (WRLX, WRHX)

tCHLL

tCLLL

tCLLH

tCHLH

ALE

tCHADV

tCLADV

Address

AD[15:0]

Refer to the Hardware Manual for detailed Timing Charts.

2008-2-7

109

MB96330 Series

FME-MB96330 rev 2

Bus Timing (Read)

(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)

Value

Sym-

bol

Parameter

Conditions

Unit Remarks

Max

Min

EACL:STS=0 and

EACL:ACE=0

tCYC/2 − 5

tCYC − 5

⎯

ALE pulse width

(multiplexed)

EACL:STS=1

tLHLL ALE

⎯

ns

EACL:STS=0 and

EACL:ACE=1

3tCYC/2 − 5

EACL:STS=0 and

EACL:ACE=0

tCYC − 15

3tCYC/2 − 15

2tCYC − 15

5tCYC/2 − 15

tCYC/2 − 15

tCYC − 15

⎯

EACL:STS=1 and

EACL:ACE=0

tAVLL ALE, A[23:16],

ns

EACL:STS=0 and

EACL:ACE=1

EACL:STS=1 and

EACL:ACE=1

EBM:NMS=0

Valid address

⇒ ALE ↓ time

(multiplexed)

EACL:STS=0 and

EACL:ACE=0

EACL:STS=1 and

EACL:ACE=0

t^ADVLLALE,AD[15:0]

ns

EACL:STS=0 and

EACL:ACE=1

3tCYC/2 − 15

EACL:STS=1 and

EACL:ACE=1

2tCYC − 15

tCYC/2 − 15

-15

⎯

EACL:STS=0

EACL:STS=1

ALE ↓

⇒ Address valid time

(multiplexed)

tLLAX ALE, AD[15:0]

tAVRL RDX, A[23:0]

ns

Valid address

⇒ RDX ↓ time

(non-multiplexed)

EBM:NMS= 1

tCYC/2 − 15

⎯

EACL:ACE=0

EBM:NMS=0

3tCYC/2 − 15

5tCYC/2 − 15

tCYC − 15

⎯

tAVRL RDX, A[23:16]

tADVRL RDX, AD[15:0]

ns

EACL:ACE=1

EBM:NMS=0

Valid address

⇒ RDX ↓ time

(multiplexed)

EACL:ACE=0

EBM:NMS=0

ns

EACL:ACE=1

EBM:NMS=0

2tCYC − 15

Valid address

⇒ Valid data input

(non-multiplexed)

A[23:0],

tAVDV

w/o cycle

extension

EBM:NMS= 1

⎯

2tCYC − 55

AD[15:0]

110

2008-2-7

MB96330 Series

FME-MB96330 rev 2

(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)

Value

Sym-

bol

Parameter

Conditions

Unit Remarks

Max

Min

EACL:ACE=0

EBM:NMS=0

⎯

3tCYC − 55

A[23:16],

AD[15:0]

w/o cycle

ns

tAVDV

extension

EACL:ACE=1

EBM:NMS=0

⎯

4tCYC − 55

Valid address

⇒ Valid data input

(multiplexed)

EACL:ACE=0

EBM:NMS=0

5tCYC/2 − 55

w/o cycle

ns

tADVDV AD[15:0]

t^RLRHRDX

extension

EACL:ACE=1

EBM:NMS=0

⎯

7tCYC/2 − 55

w/o cycle

extension

RDX pulse width

⎯

3 tCYC/2 − 5

⎯

ns

w/o cycle

extension

RDX ↓ ⇒ Valid data input tRLDV RDX, AD[15:0]

⎯

3 tCYC/2 − 50 ns

RDX ↑ ⇒ Data hold time

tRHDX RDX, AD[15:0]

0

⎯

ns

Address valid ⇒ Data hold

time

A[23:0],

tAXDX

⎯

0

AD[15:0]

EACL:STS=1 and

EACL:ACE=1

3tCYC/2 − 10

tCYC/2 − 10

⎯

RDX ↑ ⇒ ALE ↑ time

t^RHLHRDX, ALE

ns

other ECL:STS,

EACL:ACE setting

tAVCH A[23:0], ECLK

tADVCH AD[15:0], ECLK

tRLCH RDX, CLK

tCYC − 15

tCYC/2 − 15

tCYC/2 − 10

− 10

⎯

Valid address

⇒ ECLK ↑ time

⎯

ns

RDX ↓ ⇒ ECLK ↑ time

⎯

EACL:STS=0

EACL:STS=1

⎯

ALE ↓ ⇒ RDX ↓ time

tLLRL ALE, RDX

⎯

ECLK↑ ⇒ Valid data input tCHDV AD[15:0], ECLK

⎯

tCYC − 50

2008-2-7

111

MB96330 Series

FME-MB96330 rev 2

(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)

Value

Sym-

bol

Parameter

Conditions

Unit Remarks

Min

Max

⎯

EACL:STS=0 and

EACL:ACE=0

tCYC/2 − 8

tCYC − 8

ALE pulse width

(multiplexed)

EACL:STS=1

tLHLL ALE

⎯

ns

EACL:STS=0 and

EACL:ACE=1

3tCYC/2 − 8

⎯

EACL:STS=0 and

EACL:ACE=0

tCYC − 20

3tCYC/2 − 20

2tCYC − 20

5tCYC/2 − 20

tCYC/2 − 20

tCYC − 20

⎯

EACL:STS=1 and

EACL:ACE=0

tAVLL ALE, A[23:16],

ns

EACL:STS=0 and

EACL:ACE=1

EACL:STS=1 and

EACL:ACE=1

EBM:NMS=0

Valid address

⇒ ALE ↓ time

(multiplexed)

EACL:STS=0 and

EACL:ACE=0

EACL:STS=1 and

EACL:ACE=0

t^ADVLLALE, AD[15:0]

ns

EACL:STS=0 and

EACL:ACE=1

3tCYC/2 − 20

EACL:STS=1 and

EACL:ACE=1

2tCYC − 20

tCYC/2 − 20

-20

⎯

EACL:STS=0

EACL:STS=1

ALE ↓

⇒ Address valid time

(multiplexed)

tLLAX ALE, AD[15:0]

tAVRL RDX, A[23:0]

ns

Valid address

⇒ RDX ↓ time

(non-multiplexed)

EBM:NMS= 1

tCYC/2 − 20

⎯

EACL:ACE=0

EBM:NMS=0

3tCYC/2 − 20

5tCYC/2 − 20

tCYC − 20

⎯

tAVRL RDX, A[23:16]

tADVRL RDX, AD[15:0]

ns

EACL:ACE=1

EBM:NMS=0

Valid address

⇒ RDX ↓ time

(multiplexed)

EACL:ACE=0

EBM:NMS=0

EACL:ACE=1

EBM:NMS=0

2tCYC − 20

Valid address

⇒ Valid data input

(non-multiplexed)

A[23:0],

tAVDV

w/o cycle

ns

EBM:NMS= 1

⎯

2tCYC − 60

extension

AD[15:0]

112

2008-2-7

MB96330 Series

FME-MB96330 rev 2

(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)

Value

Sym-

bol

Parameter

Conditions

Unit Remarks

Min

Max

EACL:ACE=0

EBM:NMS=0

⎯

3tCYC − 60

A[23:16],

AD[15:0]

w/o cycle

ns

tAVDV

extension

EACL:ACE=1

EBM:NMS=0

⎯

4tCYC − 60

Valid address

⇒ Valid data input

(multiplexed)

EACL:ACE=0

EBM:NMS=0

5tCYC/2 − 60

w/o cycle

ns

tADVDV AD[15:0]

t^RLRHRDX

extension

EACL:ACE=1

EBM:NMS=0

⎯

7tCYC/2 − 60

w/o cycle

ns

RDX pulse width

⎯

3tCYC/2 − 8

⎯

extension

w/o cycle

extension

RDX ↓ ⇒ Valid data input tRLDV RDX, AD[15:0]

⎯

3tCYC/2 − 55 ns

RDX ↑ ⇒ Data hold time

tRHDX RDX, AD[15:0]

0

⎯

ns

Address valid ⇒ Data hold

time

tAXDX A[23:0]

⎯

0

EACL:STS=1 and

EACL:ACE=1

3tCYC/2 − 15

tCYC/2 − 15

⎯

RDX ↑ ⇒ ALE ↑ time

t^RHLHRDX, ALE

ns

other ECL:STS,

EACL:ACE setting

tAVCH A[23:0], ECLK

tADVCH AD[15:0], ECLK

tRLCH RDX, CLK

tCYC − 20

tCYC/2 − 20

tCYC/2 − 15

− 15

⎯

Valid address

⇒ ECLK ↑ time

⎯

ns

RDX ↓ ⇒ ECLK ↑ time

⎯

EACL:STS=0

EACL:STS=1

⎯

ALE ↓ ⇒ RDX ↓ time

tLLRL ALE, RDX

⎯

ECLK↑ ⇒ Valid data input tCHDV AD[15:0], ECLK

⎯

tCYC − 55

2008-2-7

113

MB96330 Series

FME-MB96330 rev 2

tAVCH

tCHDV

tRLCH

tADVCH

0.8*Vcc

ECLK

tAVLL

tLLAX

tADVLL

tRHLH

ALE

0.2*VCC

tLHLL

tAVRL

tADVRL

tRLRH

RDX

tLLRL

A[23:0]

tRLDV

tAXDX

tAVDV

tRHDX

tADVDV

VIH

VIL

AD[15:0]

Address

Read data

VIL

Refer to the Hardware Manual for detailed Timing Charts.

Bus Timing (Write)

(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

EACL:STS=0

EBM:NMS=1

tCYC/2 − 15

⎯

Valid address

⇒ WRX ↓ time

(non-multiplexed)

WRX, WRLX,

WRHX,

A[23:0]

tAVWL

ns

EACL:STS=1

EBM:NMS=1

tCYC − 15

⎯

EACL:ACE=0

EBM:NMS=0

3tCYC/2 −

WRX, WRLX,

WRHX,

A[23:16]

15

tAVWL

ns

EACL:ACE=1

EBM:NMS=0

5tCYC/2 −

Valid address

⇒ WRX ↓ time

(multiplexed)

15

EACL:ACE=0

EBM:NMS=0

tCYC − 15

2tCYC − 15

tCYC − 5

WRX, WRLX,

tADVWL WRHX,

ns

EACL:ACE=1

EBM:NMS=0

AD[15:0]

WRX, WRXL,

WRHX

w/o cycle

extension

WRX pulse width

tWLWH

⎯

114

2008-2-7

MB96330 Series

FME-MB96330 rev 2

(T^A= −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

WRX, WRLX,

WRHX,

AD[15:0]

Valid data output

⇒ WRX ↑ time

w/o cycle

extension

tDVWH

⎯

tCYC − 20

⎯

ns

WRX, WRLX,

WRHX,

AD[15:0]

WRX ↑

tWHDX

tWHAX

⎯

tCYC/2 − 15

⎯

ns

⇒ Data hold time

EACL:STS=1

EBM:NMS=1

EACL:STS=0

EBM:NMS=1

WRX ↑

⇒ Address valid time

(non-multiplexed)

− 15

⎯

ns

WRX, WRLX,

WRHX, A[23:0]

tCYC/2 − 15

WRX ↑

⇒ Address valid time

(multiplexed)

WRX, WRLX,

WRHX,

A[23:16]

EBM:NMS=0

tCYC/2 − 15

⎯

ns

EBM:ACE=1 and

EACL:STS=1

other EBM:ACE

and

2tCYC − 10

tCYC − 10

⎯

WRX ↑ ⇒ ALE ↑ time

WRX, WRLX,

WRHX, ALE

EBM:NMS=0

t^WHLH

ns

(multiplexed)

EACL:STS setting

WRX ↓ ⇒ ECLK ↑

time

WRX, WRLX,

WRHX, ECLK

⎯

tWLCH

tCYC/2 − 10

⎯

EACL:STS=0

EBM:NMS=1

⎯

tCYC/2 − 15

tCYC − 15

CSn ⇒ WRX time

(non-multiplexed)

WRX, WRLX,

WRHX, CSn

tCSLWL

EACL:STS=1

EBM:NMS=1

3tCYC/2 −

EACL:ACE=0

EBM:NMS=0

15

CSn ⇒ WRX time

(multiplexed)

WRX, WRLX,

WRHX, CSn

tCSLWL

ns

5tCYC/2 −

EACL:ACE=1

EBM:NMS=0

⎯

15

EACL:STS=1

EBM:NMS=1

EACL:STS=0

EBM:NMS=1

− 15

⎯

ns

WRX ⇒ CSn time

WRX, WRLX,

WRHX, CSn

tWHCSH

(non-multiplexed)

tCYC/2 − 15

WRX ⇒ CSn time

(multiplexed)

WRX, WRLX,

WRHX, CSn

EBM:NMS=0

tCYC/2 − 15

⎯

ns

(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

EACL:STS=0

EBM:NMS=1

tCYC/2 − 20

⎯

Valid address

⇒ WRX ↓ time

(non-multiplexed)

WRX, WRLX,

WRHX,

A[23:0]

tAVWL

ns

EACL:STS=1

EBM:NMS=1

tCYC − 20

⎯

2008-2-7

115

MB96330 Series

FME-MB96330 rev 2

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

EACL:ACE=0

EBM:NMS=0

3tCYC/2 −

⎯

WRX, WRLX,

WRHX,

A[23:16]

20

t^AVWL

ns

EACL:ACE=1

EBM:NMS=0

5tCYC/2 −

⎯

Valid address

20

⇒ WRX ↓ time

(multiplexed)

EACL:ACE=0

EBM:NMS=0

tCYC − 20

2tCYC − 20

tCYC − 8

WRX, WRLX,

tADVWL WRHX,

ns

EACL:ACE=1

EBM:NMS=0

AD[15:0]

WRX, WRXL,

WRHX

w/o cycle

extension

WRX pulse width

t^WLWH

⎯

ns

WRX, WRLX,

WRHX,

AD[15:0]

Valid data output

⇒ WRX ↑ time

w/o cycle

extension

tDVWH

tCYC − 25

WRX, WRLX,

WRHX,

AD[15:0]

WRX ↑

tWHDX

tWHAX

⎯

t^CYC/2 − 20

⎯

ns

⇒ Data hold time

EACL:STS=1

EBM:NMS=1

EACL:STS=0

EBM:NMS=1

WRX ↑

⇒ Address valid time

(non-multiplexed)

− 20

⎯

ns

WRX, WRLX,

WRHX, A[23:0]

tCYC/2 − 20

WRX ↑

⇒ Address valid time

(multiplexed)

WRX, WRLX,

WRHX,

A[23:16]

EBM:NMS=0

tCYC/2 − 20

⎯

ns

EBM:ACE=1 and

EACL:STS=1

other EBM:ACE

and

2tCYC − 15

tCYC − 15

⎯

WRX ↑ ⇒ ALE ↑ time

WRX, WRLX,

WRHX, ALE

EBM:NMS=0

tWHLH

ns

(multiplexed)

EACL:STS setting

WRX ↓ ⇒ ECLK ↑

time

WRX, WRLX,

WRHX, ECLK

⎯

tWLCH

tCYC/2 − 15

⎯

EACL:STS=0

EBM:NMS=1

⎯

tCYC/2 − 20

tCYC − 20

CSn ⇒ WRX time

(non-multiplexed)

WRX, WRLX,

WRHX, CSn

tCSLWL

EACL:STS=1

EBM:NMS=1

3tCYC/2 −

EACL:ACE=0

EBM:NMS=0

20

CSn ⇒ WRX time

(multiplexed)

WRX, WRLX,

WRHX, CSn

tCSLWL

ns

5tCYC/2 −

EACL:ACE=1

EBM:NMS=0

⎯

20

EACL:STS=1

EBM:NMS=1

EACL:STS=0

EBM:NMS=1

− 20

⎯

ns

WRX ⇒ CSn time

WRX, WRLX,

WRHX, CSn

tWHCSH

(non-multiplexed)

tCYC/2 − 20

WRX ⇒ CSn time

(multiplexed)

WRX, WRLX,

WRHX, CSn

EBM:NMS=0

tCYC/2 − 20

⎯

ns

116

2008-2-7

MB96330 Series

FME-MB96330 rev 2

tWLCH

0.8*VCC

ECLK

ALE

tWHLH

tAVWL

tWLWH

tADVWL

WRX (WRLX, WRHX)

0.2*VCC

tCSLWL

tWHCSH

CSn

tWHAX

A[23:0]

tDVWH

tWHDX

AD[15:0]

Address

Write data

Refer to the Hardware Manual for detailed Timing Charts.

Ready Input Timing

(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)

Rated Value

Test

Parameter

Symbol

Units

Remarks

Condition

Min

35

0

Max

RDY setup time

RDY hold time

tRYHS

tRYHH

RDY

⎯

ns

⎯

(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)

Rated Value

Test

Parameter

Symbol

Units

Condition

Min

45

0

Max

RDY setup time

RDY hold time

tRYHS

tRYHH

RDY

⎯

ns

⎯

Note : If the RDY setup time is insufﬁcient, use the auto-ready function.

2008-2-7

117

MB96330 Series

FME-MB96330 rev 2

0.8*VCC

ECLK

tRYHS

VIH

tRYHH

VIH

RDY

When WAIT is not used.

RDY

VIL

When WAIT is used.

Refer to the Hardware Manual for detailed Timing Charts.

Hold Timing

(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, Cl = 50pF)

Value

Parameter

Symbol

Condition

Units Remarks

Min

Max

Pin floating ⇒ HAKX ↓ time

HAKX ↑ time ⇒ Pin valid time

tXHAL

tHAHV

HAKX

tCYC − 20 tCYC + 20

ns

⎯

(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, Cl = 50pF)

Value

Parameter

Symbol

Condition

Units Remarks

Min

Max

Pin floating ⇒ HAKX ↓ time

HAKX ↑ time ⇒ Pin valid time

tXHAL

tHAHV

HAKX

tCYC − 25 tCYC + 25

ns

⎯

0.8*VCC

HAKX

0.2*VCC

tHAHV

tXHAL

High-Z

0.8*VCC

0.2*VCC

Each pin

Refer to the Hardware Manual for detailed Timing Charts.

118

2008-2-7

MB96330 Series

FME-MB96330 rev 2

USART timing

WARNING: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum

output timing described in the different tables must then be increased by 10ns.

(TA = -40˚C to 125˚C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF)

VCC = AVCC= 4.5V VCC = AVCC= 3.0V

to 5.5V

to 4.5V

Parameter

Symbol

Condition

Unit

Min

Max

Min

Max

Serial clock cycle time

tSCYCI

tSLOVI

SCKn

4 tCLKP1

⎯

4 tCLKP1

⎯

ns

SCK ↓ → SOT delay

time

SCKn,

SOTn

-20

+20

⎯

-30

+30

⎯

SOT → SCK ↑ delay

time

SCKn,

SOTn

N*tCLKP1

- 20 ^*1

N*tCLKP1 -

30 ^*1

tOVSHI

tIVSHI

Internal Shift

Clock Mode

SCKn,

SINn

tCLKP1 +

45

tCLKP1 +

55

Valid SIN → SCK ↑

⎯

ns

SCK ↑ → Valid SIN

hold time

SCKn,

SINn

t^SHIXI

0

⎯

0

⎯

Serial clock “L” pulse

width

tCLKP1 +

10

tCLKP1 +

10

tSLSHE

tSHSLE

tSLOVE

tIVSHE

tSHIXE

SCKn

⎯

Serial clock “H” pulse

width

tCLKP1 +

10

tCLKP1 +

10

⎯

SCK ↓ → SOT delay

time

SCKn,

SOTn

2 tCLKP1

+ 45

2 tCLKP1

+ 55

⎯

External Shift

Clock Mode

SCKn,

SINn

tCLKP1/2

+ 10

tCLKP1/2+

Valid SIN → SCK ↑

⎯

10

SCK ↑ → Valid SIN

hold time

SCKn,

SINn

tCLKP1 +

10

tCLKP1 +

10

SCK fall time

SCK rise time

tFE

tRE

SCKn

⎯

20

⎯

20

ns

Notes: • AC characteristic in CLK synchronized mode.

• CL is the load capacity value of pins when testing.

• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some

parameters. These parameters are shown in “MB96300 Super series HARDWARE MANUAL”

• tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns

*1: Parameter N depends on tSCYCI and can be calculated as follows:

• if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2

• if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1

Examples:

tSCYCI

4*t^CLKP1

N

2

5*tCLKP1, 6*tCLKP1

7*tCLKP1, 8*tCLKP1

...

3

4

...

2008-2-7

119

MB96330 Series

FME-MB96330 rev 2

tSCYCI

SCK for

0.8*VCC

ESCR:SCES = 0

0.2*VCC

0.8*VCC

SCK for

0.8*V^CC

ESCR:SCES = 1

0.2*VCC

tSLOVI

tOVSHI

0.8*VCC

0.2*VCC

SOT

SIN

tSHIXI

tIVSHI

VIH

VIL

VIH

VIL

Internal Shift Clock Mode

tSLSHE

tSHSLE

SCK for

VIH

VIL

VIH

VIL

ESCR:SCES = 0

VIL

SCK for

VIH

VIL

tSLOVE

VIH

ESCR:SCES = 1

VIL

tFE

tRE

0.8*V^CC

0.2*VCC

SOT

SIN

tIVSHE

tSHIXE

VIH

VIL

VIH

VIL

External Shift Clock Mode

120

2008-2-7

MB96330 Series

FME-MB96330 rev 2

I²C Timing

(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V,VSS = AVSS =0V)

Fast-mode*⁴

Standard-mode

Parameter

Symbol

Condition

Unit

Min

Max

Min

Max

SCL clock frequency

f^SCL

0

100

0

400

kHz

Hold time (repeated) START condition

SDA↓→SCL↓

tHDSTA

4.0

⎯

0.6

⎯

µs

“L” width of the SCL clock

“H” width of the SCL clock

tLOW

tHIGH

4.7

4.0

⎯

1.3

0.6

⎯

µs

Set-up time for a repeated START condition

SCL↑→SDA↓

tSUSTA

tHDDAT

tSUDAT

tSUSTO

tBUS

4.7

0

⎯

3.45*²

⎯

0.6

0

⎯

0.9*³

⎯

µs

ns

µs

R = 1.7 kΩ,

C = 50 pF*¹

Data hold time

SCL↓→SDA↓↑

Data set-up time

SDA↓↑→SCL↑

250

4.0

4.7

100

0.6

1.3

Set-up time for STOP condition

SCL↑→SDA↑

⎯

Bus free time between a STOP and START

condition

⎯

*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.

*3 : A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement

tSUDAT ≥ 250 ns must then be met.

*4 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz.

SDA

t

BUS

tSUDAT

t

HDSTA

t

LOW

SCL

tHIGH

t

HDSTA

t

HDDAT

t

SUSTA

tSUSTO

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121

MB96330 Series

FME-MB96330 rev 2

122

2008-2-7

MB96330 Series

FME-MB96330 rev 2

5. USB Characteristics

(TA = -40˚C to 105˚C, VCC = AVCC= 3.0V to 5.5V,VSS = AVSS = 0V, VCC3 = 3.0V to 3.6V)

Parameter

Input High level voltage

Input Low level voltage

Differential Input Sensitivity

Differential Common Mode Range

Output High level voltage

Output Low level voltage

Cross over voltage

Symbol Min

Max Unit

Note

VIH

VIL

2.0

-

0.8

-

V

Input characteristics

VDI

0.2

0.8

2.8

0.0

1.3

4

V

VCM

VOH

VOL

VCRS

tFR

2.5

3.6

0.3

2.0

20

V

IOH = -100µA

IOL = 100µA

V

Output characteris-

tics

Rise time

ns

%

Ω

Fall time

tFF

4

20

Rising/Falling time matching

Output resistance

tRFM

ZDRV

90

28

111.11

44

TFR/TFF

includes RS = 27Ω

Data Signal Timing

UDP

UDM

90%

VCRS

10%

tFR

tFF

Load Condition:

Testing Point

CL=50pF

Testing Point

CL=50pF

RS=27Ω

UDP

RS=27Ω

UDM

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123

MB96330 Series

FME-MB96330 rev 2

124

2008-2-7

MB96330 Series

FME-MB96330 rev 2

6. Analog Digital Converter

(TA = -40 ˚C to +125 ˚C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)

Value

Parameter

Symbol

Unit

Remarks

Min

-

Typ

Max

10

Resolution

-

bit

Total error

-3

+3

LSB

Nonlinearity error

-2.5

+2.5

Differentialnonlinearity

error

-

-1.9

-

+1.9

LSB

AVRL - AVRL+ AVRL +

1.5 0.5 2.5

Zero reading voltage

VOT

ANn

Full scale reading

voltage

AVRH - AVRH - AVRH+

VFST

ANn

LSB

3.5

1.5

0.5

1.0

2.0

0.5

1.2

-1

-

16,500 µs 4.5V ≤ ΑVCC ≤ 5.5V

Compare time

Sampling time

-

µs 3.0V ≤ ΑV^CC< 4.5V

µs 4.5V ≤ ΑVCC ≤ 5.5V

µs 3.0V ≤ ΑVCC < 4.5V

µA TA = 25 ˚C

-

+1

+3

Analog port input cur-

rent

IAIN

ANn

-3

µA TA = 125 ˚C

Analog input voltage

range

VAIN

AVRH

AVRL

IA

AVRL

-

AVRH

AVcc

V

AVRH/

AVRH2

0.75

AVcc

-

Reference voltage

range

0.25

AVCC

AVRL

AVcc

AVSS

-

2.5

-

AD Converter ac-

-

5

mA

tive

Power supply current

AD Converter not

operated

IAH

µA

AVRH/

AVRL

AD Converter ac-

IR

0.7

-

1

mA

tive

Reference voltage cur-

rent

AVRH/

AVRL

AD Converter not

operated

IRH

5

µA

Offset between input

channels

-

ANn

-

TBD

LSB

Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller.

Deﬁnition of A/D Converter Terms

Resolution: Analog variation that is recognized by an A/D converter.

Total error: Difference between the actual value and the ideal value. The total error includes zero transition error,

full-scale transition error and linear error.

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125

MB96330 Series

FME-MB96330 rev 2

Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” <--> “00 0000 0001”)

and full-scale transition line (“11 1111 1110” <--> “11 1111 1111”) and actual conversion characteristics.

Differential linearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from

an ideal value.

Zero reading voltage: Input voltage which results in the minimum conversion value.

Full scale reading voltage: Input voltage which results in the maximum conversion value.

Total error

3FF

1.5 LSB

3FE

3FD

Actual conversion

characteristics

{1 LSB × (N − 1) + 0.5 LSB}

004

003

002

001

VNT

(Actually-measured value)

Actual conversion

characteristics

Ideal characteristics

0.5 LSB

AVRL

AVRH

Analog input

VNT − {1 LSB × (N − 1) + 0.5 LSB}

[LSB]

Total error of digital output “N” =

1 LSB

AVRH − AVRL

1 LSB = (Ideal value)

[V]

1024

N: A/D converter digital output value

VOT (Ideal value) = AVRL + 0.5 LSB [V]

VFST (Ideal value) = AVRH − 1.5 LSB [V]

VNT : A voltage at which digital output transitions from (N − 1) to N.

126

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MB96330 Series

FME-MB96330 rev 2

Non linearity error

Differential linearity error

Ideal

characteristics

3FF

Actual conversion

characteristics

3FE

N + 1

Actual conversion

characteristics

{1 LSB × (N − 1)

+ VOT }

3FD

VFST (actual

measurement

value)

N

VNT (actual

measurement value)

004

003

002

001

V (N + 1) T

(actual measurement

value)

Actual conversion

characteristics

N − 1

N − 2

VNT

(actual measurement value)

Ideal characteristics

Actual conversion

characteristics

VOT (actual measurement value)

Analog input

AVRL

AVRH

AVRL

AVRH

Analog input

V^NT− {1 LSB × (N − 1) + VOT}

[LSB]

Non linearity error of digital output N =

1 LSB

V (N+1) T − VNT

−1 LSB [LSB]

1 LSB

Differential linearity error of digital output N =

1 LSB =

VFST − VOT

[V]

1022

N

: A/D converter digital output value

VOT : Voltage at which digital output transits from “000H” to “001H.”

VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”

Notes on A/D Converter Section

• About the external impedance of the analog input and the sampling time of the A/D converter (with sample

and hold circuit):

If the external impedance is too high to keep sufﬁcient sampling time, the analog voltage charged to the

internal sample and hold capacitor is insufﬁcient, adversely affecting A/D conversion precision.

• analog input circuit model:

R

Comparator

Analog input

C

Sampling switch

Reference value:

• C = 8.5 pF (Max)

2008-2-7

127

MB96330 Series

FME-MB96330 rev 2

To satisfy the A/D conversion precision standard, the relationship between the external impedance and minimum

sampling time must be considered and then either the resistor value and operating frequency must be adjusted

or the external impedance must be decreased so that the sampling time (Tsamp) is longer than the minimum

value. Usually, this value is set to 7τ, where τ = RC. If the external input resistance (Rext) connected to the analog

input is included, the sampling time is expressed as follows:

Tsamp [min] = 7 × (Rext + 2.6kΩ) × C for 4.5 ≤ AVcc ≤ 5.5

Tsamp [min] = 7 × (Rext + 12.1kΩ) × C for 3.0 ≤ AVcc ≤ 4.5

If the sampling time cannot be sufﬁcient, connect a capacitor of about 0.1 µF to the analog input pin.

•

About the error

The accuracy gets worse as |AVRH - AVRL| becomes smaller.

128

2008-2-7

MB96330 Series

FME-MB96330 rev 2

7. Alarm Comparator

(TA = -40 ˚C to +125 ˚C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V)

Value

Typ

Parameter

Symbol

Unit

Remarks

Min

Max

Alarm comparator

enabled in fast

mode (one channel)

IA5ALMF

-

25

40

µA

Alarm comparator

enabled in slow

mode (one channel)

Power supply current

AVCC

IA5ALMS

-

7

-

10

5

µA

Alarm comparator

disabled

IA5ALMH

IALIN

-1

-3

-

+1

+3

µA TA = 25 ˚C

µA TA = 125 ˚C

ALARM pin input cur-

rent

ALARM pin input volt-

age range

VALIN

0

-

AVCC

V

External low threshold

high->low transition

0.36 * AVCC 0.36*AVCC

-0.25 -0.1

V^EVTL(H->L)

VEVTL(L->H)

VEVTH(H->L)

VEVTH(L->H)

VIVTL(H->L)

VIVTL(L->H)

VIVTH(H->L)

VIVTH(L->H)

External low threshold

low->high transition

0.36*AVCC 0.36 * AVCC

+0.1 +0.25

INTREF = 0

Externalhighthreshold

high->low transition

0.78 * AVCC 0.78*AVCC

V

-0.25

-0.1

Externalhighthreshold

low->high transition

0.78*AVCC 0.78 * AVCC

ALARM0,

ALARM1

+0.1

1.1

+0.25

-

Internal low threshold

high->low transition

0.9

-

Internal low threshold

low->high transition

1.3

2.4

2.6

1.55

-

INTREF = 1

Internal high threshold

high->low transition

2.2

-

Internal high threshold

low->high transition

2.85

Switching hysteresis

VHYS

tCOMPF

tCOMPS

50

-

0.3

2

300

2

mV

µs

CMD = 1 (fast)

CMD = 0 (slow)

Comparison time

-

100

µs

2008-2-7

129

MB96330 Series

FME-MB96330 rev 2

Comparator

Output

H

L

VALIN

VxVTx(H->L)

VHYS

VxVTx(L->H)

130

2008-2-7

MB96330 Series

FME-MB96330 rev 2

8. Low Voltage Detector characteristics

(T = -40 ˚C to +125 ˚C, V = AV = 3.0V - 5.5V, V = AV = 0V)

A

cc

ss

Value

Parameter

Symbol

Unit

Remarks

Min

60

Max

75

T

Stabilization time

Level 0

µs

V

LVDSTAB

V

CILCR:LVL[3:0]=”0000”

CILCR:LVL[3:0]=”0001”

CILCR:LVL[3:0]=”0010”

CILCR:LVL[3:0]=”0011”

CILCR:LVL[3:0]=”0100”

CILCR:LVL[3:0]=”0101”

CILCR:LVL[3:0]=”0110”

CILCR:LVL[3:0]=”0111”

CILCR:LVL[3:0]=”1000”

CILCR:LVL[3:0]=”1001”

2.7

2.9

3.1

3.5

3.6

3.7

3.8

3.9

4.0

4.1

2.9

DL0

V

Level 1

3.1

DL1

V

Level 2

3.3

DL2

V

Level 3

3.75

3.85

3.95

4.05

4.15

4.25

4.35

DL3

V

Level 4

DL4

V

Level 5

DL5

V

Level 6

DL6

V

Level 7

DL7

V

Level 8

DL8

V

Level 9

DL9

V

Level 10

Level 11

Level 12

Level 13

Level 14

Level 15

not used

DL10

V

not used

DL11

V

DL12

V

DL13

V

DL14

V

DL15

Levels 10 to 15 are not used in this device.

For correct detection, the slope of the voltage level must satisfy

V

dV

dt

-----

µs

≤ 0.004

.

Faster variations are regarded as noise and may not be detected.

The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of

Vcc = 2.7V. The electrical characteristics however are only valid in the speciﬁed range (usually down to 3.0V).

2008-2-7

131

MB96330 Series

FME-MB96330 rev 2

Low Voltage Detector Operation

In the following ﬁgure, the occurrence of a low voltage condition is illustrated. For a detailed description of the

reset and startup behavior, please refer to the corresponding hardware manual chapter.

Voltage [V]

V_CC

V_{DLx, Max}

V_{DLx, Min}

dV

dt

Time [s]

Power Reset Extension Time

Low Voltage Reset Assertion

Normal Operation

2008-2-7

132

MB96330 Series

FME-MB96330 rev 2

9. FLASH memory program/erase characteristics

(TA = 25^oC, Vcc = 5.0V)

Value

Parameter

Unit

Remarks

Min

Typ

Max

Erasure programming time not

included

Sector erase time

Chip erase time

-

0.9

3.6

s

n is the number of Flash sector

of the device

-

n*0.9

23

n*3.6

370

Word (16-bit width) pro-

gramming time

System overhead time not in-

cluded

us

Programme/Erase cycle 10 000

Flash data retention time 20

cycle

year

*1

*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius

equation to convert high temperature measurements into normalized value at 85^oC)

2008-2-7

133

MB96330 Series

FME-MB96330 rev 2

134

2008-2-7

MB96330 Series

FME-MB96330 rev 2

■ EXAMPLE CHARACTERISTICS

To be prepared

2008-2-7

135

MB96330 Series

FME-MB96330 rev 2

2008-2-7

136

MB96330 Series

FME-MB96330 rev 2

■ PACKAGE DIMENSION MB96(F)33x LQFP 144P

144-pin plastic LQFP

Lead pitch

0.50 mm

20.0 × 20.0 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Weight

Plastic mold

1.70 mm MAX

1.20g

Code

(Reference)

(FPT-144P-M08)

P-LFQFP144-20×20-0.50

144-pin plastic LQFP

(FPT-144P-M08)

22.00±0.20(.866±.008)SQ

* 20.00±0.10(.787±.004)SQ

0.145±0.055

(.006±.002)

108

73

109

72

0.08(.003)

Details of "A" part

1.50 –⁺0⁰.^.1²0⁰

(Mounting height)

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

0.10±0.10

(.004±.004)

(Stand off)

0˚~8˚

INDEX

144

37

0.25(.010)

0.50±0.20

(.020±.008)

"A"

0.60±0.15

(.024±.006)

1

36

LEAD No.

0.50(.020)

0.22±0.05

(.009±.002)

M

0.08(.003)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2003 FUJITSU LIMITED F144019S-c-4-6

2008-2-7

137

MB96330 Series

FME-MB96330 rev 2

138

2008-2-7

MB96330 Series

FME-MB96330 rev 2

■ ORDERING INFORMATION

Persistent

Subclock Low Volt-

age Reset

Part number

Package

Remarks

MB96336YSA PMC-GSE2 ^*1

MB96336RSA PMC-GSE2 ^*1

MB96336YWA PMC-GSE2 ^*1

MB96336RWA PMC-GSE2 ^*1

MB96338YSA PMC-GSE2 ^*1

MB96338RSA PMC-GSE2 ^*1

MB96338YWA PMC-GSE2 ^*1

MB96338RWA PMC-GSE2 ^*1

MB96F338YSA PMC-GSE2 ^*1

MB96F338RSA PMC-GSE2 ^*1

MB96F338YWA PMC-GSE2 ^*1

MB96F338RWA PMC-GSE2 ^*1

MB96F338USA PMC-GSE2 ^*1

MB96F338UWA PMC-GSE2 ^*1

Yes

No

144 pin Plastic LQFP

(FPT-144P-M08)

Yes

No

Yes

No

144 pin Plastic LQFP

(FPT-144P-M08)

Yes

No

Yes

No

144 pin Plastic LQFP

(FPT-144P-M08)

Yes

No

144 pin Plastic LQFP

(FPT-144P-M08)

with USB

Yes

416 pin Plastic BGA For evalua-

(BGA416-M02) tion

MB96V300BRB-ES

Yes

No

*1: These devices are under development. All information in this datasheet is preliminary for the devices under

development.

2008-2-7

139

MB96330 Series

FME-MB96330 rev 2

140

2008-2-7

MB96330 Series

FME-MB96330 rev 2

■ REVISION HISTORY

Revision

Date

Modiﬁcation

Prelim 0.1

Prelim 0.2

2007-05-23 Creation

2007-08-14 - information about MB96F338U (with USB function) is added

- DMA 8ch --> 16ch

- ADC reference switch is removed

Prelim 0.3

2007-09-11 - Circuit Type of Device with “U“ sufﬁx is added

- Circuit Type diagram: TTL input cell type was changed from NOR to NAND

- IO Map, IRQ table are updated

- Parallel Programing Flash Memory Control Signals is updated

- DC/AC spec of USB I/O is added

Prelim 0.4

Prelim 0.5

Prelim 1

2007-09-24 - Block diagram for MB96F338U was corrected: USB PB1 -> PB3

- IRQ table was modiﬁed: Vector number 111 was inserted (reserved)

- Pin assignment was corrected: not used resource name was removed

2007-11-02 - Internal Max Freq 56MHz --> 48MHz

- DMA 12ch --> 10ch

- FPT-144P-M12 package was removed

2007-12-20 Update of the block diagram to include USB block.

Update DC characteristics to include all USB pins characteristics.

IOMAP regenerated.

Memory maps and Flash conﬁguration reworked.

Typos corrected accross the document.

Renaming of the Flash banks.

2008-2-7

141

MB96330 Series

FME-MB96330 rev 2

Revision

Prelim 2

Date

Modiﬁcation

2008-02-07 • Features:

- Removed ADC reference switch

- changed USB description

• Lineup:

- option description added

- Part number names corrected

- Flash B removed

- RLT6 added

• Block diagrams:

- Flash B removed

- OUT5_R -> OUT6_R

- TX2_R, RX2_R added

- SIN2_R, SOT2_R, SCK2_R and SOT9 added

- not existing TTGx, TTGx_R and PPGx_R pins deleted

- RLT6 added

• Pin function description: relocated clock output and CAN pins added

• I/O ciruit types updated

• Memory maps replaced by new standard maps

• Parallel Flash programming pinning removed

• IOMAP regenerated (naming style changed, all reserved registers added)

• DC current limits updated with new setting and corrected frequencies

• External bus timings: missing conditions added and readability improved

• Alarm comparator spec updated (transition voltages deﬁned)

• Ordering information updated

• Typos and formatting corrected

142

2008-2-7

MB96330 Series

FME-MB96330 rev 2

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before

ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

Exportation/release of any products described in this document

may require necessary procedures in accordance with the

regulations of the Foreign Exchange and Foreign Trade Control

Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or

registered trademarks of their respective owners.

Edited

Strategic Business Development Dept.

MB96330 Series

FME-MB96330 rev 2

144

2008-2-7


型号：	MB96338RSAPMC-GSE2
厂家：	FUJITSU
描述：	Microcontroller, 16-Bit, MROM, 48MHz, CMOS, PQFP144, 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LFQFP-144 时钟微控制器外围集成电路
文件：	总144页 (文件大小：1502K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB96338RSAPMC-GSE2 [FUJITSU]

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