MB96F326YWAPMC-GE2 [FUJITSU]
16-bit Proprietary Microcontroller; 16位微控制器专有
| 型号： | MB96F326YWAPMC-GE2 |
| 厂家： | 
FUJITSU |
| 描述： | 16-bit Proprietary Microcontroller |
| 文件： | 总159页 (文件大小：2466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MB96300
PRELIMININARY SPECIFICATION
FME-MB96300 rev 19
16-bit Proprietary Microcontroller
CMOS
F2MC-16FX MB96300 Series
■ DESCRIPTION
MB96300 series is based on Fujitsu’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like
performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy
migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation
include significantly improved performance - even at the same operation frequency, reduced power consumption
and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction
cycle time of 17.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly
reduces emission peaks in the frequency spectrum. The emitted power is minimised by the on-chip voltage
regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies
for peripheral resources independent of the CPU speed.
■ PACKAGES
• 48-pin
48-pin Plastic LQFP
(FPT-48P-M26)
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
MB96300 Series
Preliminary Specification
• 64-pin
64-pin Plastic LQFP
64-pin Plastic LQFP
(FPT-64P-M23)
(FPT-64P-M24)
• 80-pin
80-pin Plastic LQFP
(FPT-80P-M21)
• 100-pin
100-pin Plastic QFP
100-pin Plastic LQFP
(FPT-100P-M22)
(FPT-100P-M20)
2
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
• 120-pin
120-pin Plastic LQFP
(FPT-120P-M21)
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
3
MB96300 Series
Preliminary Specification
■ FEATURES
• 16-bit core CPU, up to 56 MHz internal, 17.8 ns instruction cycle time
• 0.18µm CMOS Process Technology
• Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different
addressing modes; barrel shift; variety of pointers)
• 8-byte instruction execution queue
• Signed multiply (16 bit × 16 bit) and divide (32 bit/16 bit) instructions available
• Internal voltage regulator supports reduced internal MCU voltage, offering low EMI and low power
consumption figures
• Code Security Feature
• Up to 5 FULL-CAN interfaces; conforming to Version 2.0 Part A and Part B, ISO16845 certified
• Powerful interrupt functions (8 progr. priority levels; up to 16 external interrupts)
• Fast Interrupt processing
• Up to 16 channels DMA - Automatic transfer function independent of CPU, can be assigned freely to
resources
• Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer)
• Watchdog Timer
• Up to 10 channels full duplex USARTs (SCI/LIN)
• Up to 2 channels I2C with 400 kbit/s
• Up to 40 channels analog inputs for A/D Converter (Resolution 10 bits or 8 bits)
• Up to 6 channels16-bit reload timer
• Up to 12 channels ICU (Input capture unit) 16 bit
• Up to 12 channels OCU (Output compare unit) 16 bit
• Up to 4 channels 16-bit free running timer
• Up to 20 channels × 16-bit Programmable Pulse Generator
• Up to 6 channels Stepper Motor Controller with integrated high current output drivers
• LCD controller with up to 4 COM × 72 SEG, internal or external voltage generation
• Memory Patch Function, can also be used to implement embedded debug support
• Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes, Stop mode)
• 3-32 MHz external clock, on-chip PLL with programmable multiplication factor 1 ... 16
• 32 kHz Subsystem Clock
• 100kHz/2MHz internal RC clock
• External bus interface with up to 6 Chip select signals, 8bit or 16bit data, 24bit address, multiplexed or non-
multiplexed, programmable timing
• Up to 2 channels Alarm comparators
• Programmable input levels (Automotive / CMOS-Schmitt trigger / TTL) for all ports
• Programmable Pull-up resistors for all ports
• Programmable output driving strength for EMI optimization
• Package : 48-pin / 64-pin / 80-pin /100-pin / 120-pin plastic QFP and LQFP
4
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
• Controller Area Network (CAN) - License of Robert Bosch GmbH
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
5
MB96300 Series
Preliminary Specification
■ PRODUCT LINEUP
Features
MB96V300
MB9632x
MB9634x
MB9635x
MB9636x
MB9638x
Evaluation
sample
Flash product: MB96F3xx
Mask ROM product: MB963xx
Product type
CPU
F2MC-16FX CPU
On-chip PLL clock multiplier (x1..16, 1/2 when PLL stop)
Minimum instruction execution time: 17.8 ns (56MHz)
Clock source selectable from main- and subclock oscillator (partnumber suffix “W”), on-chip RC
oscillator, independently for CPU and 2 clock domains of peripherals
System clock
Flash/
ROM
RAM
6kB
MB96344R,
MB96344Y
MB96384R,
MB96384Y
128kB
MB96F365R,
MB96F365Y
MB96385R,
MB96385Y
160kB
288kB
6kB
MB96F326R,
MB96F326Y
MB96F356R,
MB96F356Y
12kB
MB96F346R,
MB96346R,
MB96F346Y,
MB96346Y
MB96F386R,
MB96386R,
MB96F386Y,
MB96386Y
ROM/Flash
memory
emulation by
external RAM,
288kB
16kB
MB96F347R,
MB96347R,
MB96F347Y,
MB96347Y
MB96F387R,
MB96387R,
MB96F387Y,
MB96387Y
92kB internal
RAM
416kB
544kB
16kB
24kB
24kB
MB96F348R,
MB96F348Y
Main:
544kB,
Sat.:
MB96F348C,
MB96F348H,
MB96F348T
32kB
Technology
0.18mm CMOS with on-chip voltage regulator for internal power supply
FPT-100P-
M20
FPT-100P-
M22
FPT-64P-M23
FPT-64P-M24
FPT-120P-
M21
Package
DMA
BGA416
FPT-80P-M21
FPT-48P-M26
16 channels
4 channels
6 channels
4 channels
3 channels
7 channels
6
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Features
MB96V300
10 channels
MB9632x
MB9634x
MB9635x
MB9636x
MB9638x
MB96F348H/
T:
4 channels
others:
4 channels
4 channels
2 channels
5 channels
USART
7 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
2 channels
1 channel
Master and Slave functionality, 8-bit and 10-bit addressing
18 channels 24 channels 15 channels
2 channel
1 channel
1 channel
I2C
40 channels
16 channels
A/D Converter
SAR-type, 10bit resolution, signals interrupt on conversion end, single conversion mode, continuous
conversion mode, stop conversion mode, activation by software, external trigger or reload timer
MB96384R/Y,
MB96385R/Y:
A/D Converter
Reference
Voltage switch
yes
no
no
others:
yes
yes
no
no
6 channels
4 channels
4 channels
4 channels
3 channels
4 channels
16-bit Reload
Timer
Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency, event count function
4 channels 4 channels 2 channels 2 channels 1 channel 2 channels
Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4), Prescaler
with 1/22, 1/24, 1/26, 1/28 of peripheral clockfrequency
16-bit Free-
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7
I/O Timer 2 (clock input FRCK2) corresponds to ICU 8/9
Running Timer
I/O Timer 3 (clock input FRCK3) corresponds to ICU 10/11
12 channels
6 channels
8 channels
4 channels
4 channels
8 channels
16-bit Output
Compare
Signals an interrupt when a match with 16-bit I/O Timer
A pair of compare registers can be used to generate an output signal.
12 channels 12 channels 8 channels 6 channels
Signals an interrupt upon external event
4 channels
16-bit Input
Capture
Rising edge, falling edge or rising & falling edge sensitive
20 channels 20 channels 16 channels 20 channels
8 channels
16 bit down counter, cycle and duty setting registers
Interrupt at triggering, cycle or duty match
PWM operation and one-shot operation
Internal prescaler allows 1/2, 1/4, 1/8, 1/16 of peripheral clock as counter clock and Reload timer
overflow as clock input
16-bit
Programmable
Pulse Generator
Can be triggered by software or reload timer
Synchronous trigger of up to 4 PPG channels
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
7
MB96300 Series
Preliminary Specification
Features
MB96V300
5 channels
MB9632x
MB9634x
MB9635x
MB9636x
1 channel
MB9638x
MB96384R/Y,
MB96385R/Y:
1 channel
2 channels
2 channels
2 channels
others:
2 channels
CAN Interface
(not available on
MB963xxA,
Supports CAN protocol version 2.0 part A and B
ISO16845 certified
Bit rates up to 1 Mbit/s
MB963xxC)
32 message objects
ach message object has its own identifier mask
E
Programmable FIFO mode (concatenation of message objects)
Maskable interrupt
Disabled Automatic Retransmission mode for Time Triggered CAN applications
Programmable loop-back mode for self-test operation
6 channels
5 channels
Stepping Motor
Controller
Four high current outputs for each channel
Two synchronized 8/10-bit PWMs per channel
Internal prescaling for PMW clock: 1, 1/2, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/16 of peripheral clock
16 channels 15 channels 16 channels 13 channels 10 channels 8 channels
Edge sensitive or level sensitive
External
Interrupts
Interrupt mask and pending bit per channel
Each available CAN channel RX has an external interrupt for wake-up
Selected USART channels SIN have an external interrupt for wake-up
1 channel
Disabled after reset
Once enabled, can not be disabled other than by reset.
Level high or level low sensitive
Non-Maskable
Interrupt
Pin shared with external interrupt 0.
1channel
2 channels
8-bit PWM signal is mixed with tone frequency from 16-bit reload counter
PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8, 1/16 of peripheral clock
Tone frequency: PWM frequency / 2 / (reload value + 1)
Sound Generator
4 COM x 72
SEG
4 COM x 65
SEG
Display up to 288 segments
Duty cycle: Selectable from options: 1/2, 1/3 and 1/4
Bias: Fixed at 1/3
Frame period: Selectable from three options. (for clock, peripheral clock, subclock or RC oscillator clock
is selectable)
LCD Controller
Driver: Built-in (for internal divider resistors), or external divider resistors
Data memory: Built-in 16-byte data memory for display
Stop mode: Enable LCD display in the sub-stop mode
Blank display: Selectable
Pin: All SEG and COM pins can be switched between general and specialized purposes
Others: External divided resistors can be also used to shut off the current when LCD is deactivated
8
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Features
MB96V300
MB9632x
MB9634x
MB9635x
MB9636x
MB9638x
1
MB96F348H/T: no
others: 1
Can be clocked either from sub oscillator (devices with partnumber suffix “W”), main oscillator or from
the RC oscillator
Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration)
Read/write accessible second/minute/ hour registers
Real Time Clock
Can signal interrupts every halfsecond/second/ minute/hour/day
Internal clock divider and prescaler provide exact 1s clock based on a 4 MHz or a 32 kHz clock input
(devices with partnumber suffix “W”)
64 for part
number with
suffix "W", 66
for part
80 for part
number with
suffix "W", 82
for part
49 for part
number with
suffix "W", 51
for part
34 for part
number with
suffix "W", 36
for part
94 for part
number with
suffix "W", 96
for part
136
number with
suffix "S"
number with
suffix "S"
number with
suffix "S"
number with
suffix "S"
number with
suffix "S
I/O Ports
Virtually all external pins can be used as general purpose I/O
All push-pull outputs (except when used as I2C SDA/SCL line)
Bit-wise programmable input enable
Bit-wise programmable Pull-up resistor
Bit-wise programmable as input/output or peripheral signal
Bit-wise programmable as CMOS schmitt trigger/ automotive / TTL input
Bit-wise programmable output driving strength
2 channels
2 channels
MB96384R/Y,
MB96385R/Y:
1 channel
others:
2 channels
Alarm comparator
Monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the
defined thresholds
Threshold voltages defined externally or generated internally
Status is readable, interrupts can be masked separately
Yes
Yes
Multiplexed address/data lines
Non-multiplexed address/data lines (MB96V300 and MB9638x only)
16-bit bidirectional data bus
24-bit address lines (MB9635x: 22-bit address lines)
Wait state request
External bus
interface
External bus master possible
Timing programmable
Chip select
6 signals
6 signals
6 signals
6 signals
6 signals
2 channels
2 channels
2 channels
2 channels
2 channels
2 channels
Output any on-chip clock
Clock output
function
Inverted and non-inverted clock (MB9636x,MB9635x has only non-inverted clock output)
Prescaler: 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128 of selected clock
Synchronous or asynchronous start/stop
Low voltage reset
Reset is generated when supply voltage is below minimum.
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
9
MB96300 Series
Preliminary Specification
Features
MB96V300
MB9632x
MB9634x
MB9635x
MB9636x
MB9638x
On-chip RC-
oscillator
For quick and save startup, oscillator stop detection, watchdog operation, normal clock source
2 frequencies selectable (100kHz, 2MHz)
Supports automatic programming, Embedded AlgorithmTM*1
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Flash Memory
Data retention time : 20 years
Erase can be performed on each sector individually
Sector protection
Flash Security feature to protect the content of the Flash
Low voltage detection during Flash erase
*1 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
10
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
■ PIN ASSIGNMENTS
MB96300
Pin assignment of MB96(F)32x
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
Vcc
C
61
62
63
64
40
39
P01_0/AD08/TIN1/CKOT1/TTG16_R
P09_1 /PPG9/LBX
P09_0 /PPG8/UBX
P17_2 /FRCK3/TTG17
P13_5 /PPG17
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P00_7 /AD07/INT15/PPG11_R
P00_6 /AD06/INT14/PPG10_R
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P02_5 /A21/IN1/TTG1/TTG9/ADTG_R
P04_4 /SDA0/FRCK0/TIN0_R
P04_5 /SCL0/FRCK1/TIN2_R
P03_0 /ALE/IN4/TTG4/TTG12/TOT0_R
P03_1 /RDX/IN5/TTG5 /TTG13/TOT2_R
P03_2 /WRLX/INT10_R /RX2
P03_3 /WRHX /TX2
P00_5/AD05/NT13/SIN8_R/PPG9_R
P00_4/AD04/INT12/SOT8_R/PPG8_R
P00_3/AD03/INT11/SCK8_R/TTG11_R
P00_2/AD02/INT10/SIN7_R/TTG10_R
P00_1 /AD01/INT9/SOT7_R/TTG9_R
LQFP-80
P00_0/AD00/INT8/SCK7_R/TTG8_R
Package code(mold)
FPT-80P-M21
P03_4 /HRQ/OUT4
P17_7/TX3/IN11/TTG19
P03_5 /HAKX/OUT5
P03_6 /RDY/OUT6
P03_7/CLK /OUT7
MD_0
MD_1
MD_2
P13_6 /PPG18/IN8
P13_7 /PPG19/IN9
X1A*/P04_1*
X0A*/P04_0*
Vss
P06_0 /AN0/PPG0/CS0_R
P06_1/AN /PPG1/CS1_R
AVcc
Vcc
P04_3/IN7/TX1/TTG7/TTG15
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
1)Devices with suffix W: X0A/X1A
Devices with suffix S: P04_0, P04_1
(FPT-80P-M21)
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
11
MB96300 Series
Preliminary Specification
Pin assignment of MB96(F)34x (QFP package)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P00_4/AD04/INT12/SOT8_R2)
P00_5/AD05/INT13/SIN8_R2)
P00_6/AD06/INT14
P00_7/AD07/INT15
P01_0/AD08/CKOT1/TIN1
P01_1/AD09/CKOTX1/TOT1
P01_2/AD10/INT11_R/SIN3
P01_3/AD11/SOT3
P01_4/AD12/SCK3
Vcc
P07_5/AN21/INT5/SCK9_R2)
P07_4/AN20/INT4
P07_3/AN19/INT3
P07_2/AN18/INT2
P07_1/AN17/INT1
P07_0/AN16/INT0/NMI
Vss
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P06_7/AN7/PPG7
P06_6/AN6/PPG6
P06_5/AN5/PPG5
P06_4/AN4/PPG4
P06_3/AN3/PPG3
P06_2/AN2/PPG2
P06_1/AN1/PPG1
P06_0/AN0/PPG0
AVss
QFP - 100
Vss
Package code (mold)
FPT-100P-M22
X1
X0
P01_5/AD13/INT7_R/SIN2_R
P01_6/AD14/SOT2_R
P01_7/AD15/SCK2_R
P02_0/A16/PPG12
P02_1/A17/PPG13
P02_2/A18/PPG14
P02_3/A19/PPG15
AVRL
AVRH
AVcc
P05_7/AN15/INT5_R
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1)
Devices with suffix W: X0A/X1A
Devices with suffix S: P04_0, P04_1
2) SIN7_R, SOT7_R, SCK7_R, SIN8_R, SOT8_R, SCK8_R, SIN9_R, SOT9_R, SCK9_R only available on MB96F348R/Y
(FPT-100P-M22)
Remark:
MB96(F)34x products are pin-compatible to F2MC-16LX family MB90340 series.
12
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Pin assignment of MB96(F)34x (LQFP package)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P00_1AD01/INT9/SOT7_R2)
P00_2/AD02/INT10/SIN7_R2)
P00_3/AD03/INT11/SCK8_R2)
P00_4/AD04/INT12/SOT8_R2)
P00_5/AD05/INT13/SIN8_R2)
P00_6/AD06/INT14
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
MD1
MD2
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P07_5/AN21/INT5/SCK9_R2)
P07_4/AN20/INT4
P07_3/AN19/INT3
P07_2/AN18/INT2
P07_1/AN17/INT1
P07_0/AN16/INT0/NMI
Vss
P00_7/AD07/INT15
P01_0/AD08/CKOT1/TIN1
P01_1/AD09/CKOTX1/TOT1
P01_2/AD10/INT11_R/SIN3
P01_3/AD11/SOT3
P06_7/AN7/PPG7
P06_6/AN6/PPG6
P06_5/AN5/PPG5
P06_4/AN4/PPG4
P06_3/AN3/PPG3
P06_2/AN2/PPG2
P06_1/AN1/PPG1
P06_0/AN0/PPG0
AVss
LQFP - 100
P01_4/AD12/SCK3
Vcc
Vss
Package code (mold)
FPT-100P-M20
X1
X0
P01_5/AD13/INT7_R/SIN2_R
P01_6/AD14/SOT2_R
P01_7/AD15/SCK2_R
P02_0/A16/PPG12
AVRL
AVRH
P02_1/A17/PPG13
AVcc
P02_2/A18/PPG14
P05_7/AN15/INT5_R
P05_6/AN14/INT4_R
P05_5/AN13/INT0_R/NMI_R
P05_4/AN12/TOT3/INT2_R
P02_3/A19/PPG15
P02_4/A20/TTG8/TTG0/IN0
P02_5/A21/TTG9/TTG1/IN1/ADTG_R
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
1) Devices with suffix W: X0A/X1A
Devices with suffix S: P04_0, P04_1
2) SIN7_R, SOT7_R, SCK7_R, SIN8_R, SOT8_R, SCK8_R, SIN9_R, SOT9_R, SCK9_R only available on MB96F348R/Y
(FPT-100P-M20)
Remark:
MB96(F)34x products are pin-compatible to F2MC-16LX family MB90340 series.
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
13
MB96300 Series
Preliminary Specification
Pin assignment of MB96(F)35x
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P01_0/AD08/CKOT1/TIN1/TTG16_R
P00_7/AD07/INT15/PPG11_R
P00_6/AD06/INT14/PPG10_R
P00_5/AD05/INT13/SIN8_R/PPG9_R
P00_4/AD04/INT12/SOT8_R/PPG8_R
P00_3/AD03/INT11/SCK8_R/TTG11_R
P00_2/AD02/INT10/SIN7_R/TTG10_R
P00_1/AD01/INT9/SOT7_R/TTG9_R
P00_0/AD00/INT8/SCK7_R/TTG8_R
MD0
Vcc
C
P02_5/A21/TTG9/TTG1/IN1/ADTG_R
P04_4/SDA0/FRCK0/TIN0_R
P04_5/SCL0/FRCK1/TIN2_R
P03_0/ALE/IN4/TTG4/TTG12/TOT0_R
P03_1/RDX/IN5/TTG5/TTG13/TOT2_R
P03_2/WRLX/WRX/RX2/INT10_R
P03_3/TX2/WRHX
LQFP - 64
Package code (mold)
FPT-64P-M23/M24
P03_4/HRQ/OUT4
MD1
P03_5/HAKX/OUT5
MD2
P03_6/RDY/OUT6
X1A*/P04_1*
P03_7/CLK/OUT7
X0A*/P04_0*
P06_0/AN0/PPG0/CS0_R
P06_1/AN1/PPG1/CS1_R
AVcc
Vss
P04_3/IN7/TX1/TTG7/TTG15
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
1)Devices with suffix W: X0A/X1A
Devices with suffix S: P04_0, P04_1
(FPT-64P-M23/M24)
Remark:
MB96(F)35x products are pin-compatible to F2MC-16LX family MB90350 series.
14
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Pin assignment of MB96(F)36x
36 35 34 33 32 31 30 29 28 27 26 25
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
P08_5/SIN1/INT1_R
P08_7/SCK1
RSTX
MD0
P08_6/SOT1
P04_3/TX1/TTG7/TTG15
P04_2/RX1/INT9_R/TTG6/TTG14
P08_3/SOT0/TOT2
P08_4/SCK0/INT15_R
P08_2/SIN0/TIN2/INT14_R
P04_4/FRCK0
MD1
LQFP-48
MD2
P05_7/AN15/INT5_R
P05_6/AN14/INT4_R
P05_5/AN13/INT0_R/NMI_R
P05_4/AN12/TOT3/INT2_R
P05_3/AN11/TIN3
P05_2/AN10
P05_1/AN9
Package code (mold)
FPT-48P-M26
X0A*/P04_0*
X1A*/P04_1*
AVss
1
2
3
4
5
6
7
8
9 10 11 12
* Devices with suffix W: X0A/X1A
Devices with suffix S: P04_0, P04_1
(FPT-48P-M26)
Remark:
MB96(F)36x products are pin-compatible to F2MC-16LX family MB90360 series
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
15
MB96300 Series
Preliminary Specification
Pin assignment of MB96(F)38x
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
91
92
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
Vcc
Vss
P00_3/INT6_R/A00/CS3_R/SEG15
P00_4/INT7_R/ALE/SEG16
P00_5/TTG2/IN6/RDX/SEG17
P00_6/TTG3/IN7/WRLX/WRX/SEG18
P00_7/SGO0/CLK/SEG19
P01_0/SGA0/AD00/SEG20
P01_1/OUT0/CKOT1/AD01/SEG21
P01_2/OUT1/CKOTX1/AD02/SEG22
P01_3/PPG5/AD03/SEG23
P01_4/AD04/SIN4/SEG24
P01_5/AD05/SOT4/SEG25
P01_6/AD06/SCK4/SEG26
P01_7/CKOTX1_R/AD07/SEG27
P02_0/CKOT1_R/AD08/SEG28
P02_1/IN6_R/AD09/SEG29
P02_2/IN7_R/AD10/SEG30
P02_3/SGO0_R/AD11/SEG31
P02_4/SGA0_R/AD12/SEG32
P02_5/OUT0_R/AD13/SEG33
P02_6/OUT1_R/AD14/SEG34
P02_7/PPG5_R/AD15/SEG35
P03_0/V0/A16/SEG36
P10_3/PWM2M4/PPG7
P10_2/PWM2P4/SCK2/PPG6
P10_1/PWM1M4/SOT2/TOT3
P10_0/PWM1P4/SIN2/TIN3
P09_7/PWM2M3
DVss
93
94
95
96
97
98
DVcc
99
P09_6/PWM2P3
P09_5/PWM1M3
P09_4/PWM1P3
P09_3/PWM2M2
P09_2/PWM2P2
P09_1/PWM1M2
P09_0/PWM1P2
P08_7/PWM2M1
P08_6/PWM2P1
P08_5/PWM1M1
DVss
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
LQFP - 120
Package code (mold)
FPT-120P-M21
DVcc
P08_4/PWM1P1
P08_3/PWM2M0
P08_2/PWM2P0
P08_1/PWM1M0
P08_0/PWM1P0
P05_7/AN15/TOT2/SGA1_R/SEG64
P05_6/AN14/TIN2/SGO1_R/SEG63
P05_5/AN13/TX1/SEG62 3)
P05_4/AN12/RX1/INT2_R/SEG61 3)
Vss
P03_1/V1/A17/SEG37
P03_2/V2/A18/SEG38
P03_3/V3/A19/SEG39
P03_4/INT4/RX0
P03_5/TX0
P03_6/NMI/INT0
Vcc
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1)
Devices with suffix W: X0A/X1A
Devices with suffix S: P04_0, P04_1
2) MB96384/5: Alarm1 not available
3) MB96384/5: TX1 resp. RX1 not available
(FPT-120P-M21)
16
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
■ PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
58
59
55
90
91
52
92
93
54
46
47
45
28
27
23
X1
X0
Oscillation output
Oscillation input
Reset input
A
E
RSTX
P00_0
General purpose I/O
External bus interface (non-
multiplexed mode) data line
External bus interface
(multiplexed mode) address/
data line
AD00
75
77
30
24
H
External interrupt request
input pin for INT8
INT8
Relocated USART7 serial
clock I/O (not available on
MB96F348H/T)
SCK7_R
TTG8_R
P00_1
Relocated PPG8 trigger
General purpose I/O
External bus interface (non-
multiplexed mode) data line
External bus interface
(multiplexed mode) address/
data line
AD01
INT9
76
78
31
25
H
External interrupt request
input pin for INT9
Relocated USART 7 serial
data output (not available on
MB96F348H/T)
SOT7_R
TTG9_R
Relocated PPG9 trigger
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
17
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P00_2
AD02
General purpose I/O
External bus interface (non-
multiplexed mode) data line
External bus interface
(multiplexed mode) address/
data line
77
79
32
26
H
External interrupt request
input pin for INT10
INT10
Relocated USART 7 serial
data input (not available on
MB96F348H/T)
SIN7_R
TTG10_R
P00_3
Relocated PPG10 trigger
General purpose I/O
External bus interface (non-
multiplexed mode) data line
External bus interface
(multiplexed mode) address/
data line
AD03
INT11
78
80
33
27
H
External interrupt request
input pin for INT11
Relocated USART8 serial
clock I/O (not available on
MB96F348H/T)
SCK8_R
TTG11_R
Relocated PPG11 trigger
18
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P00_4
AD04
General purpose I/O
External bus interface (non-
multiplexed mode) data line
External bus interface
(multiplexed mode) address/
data line
79
81
External interrupt request
input pin for INT12
34
28
INT12
H
Relocated USART 8 serial
data output (not available on
MB96F348H/T)
SOT8_R
PPG8_R
Relocated
Programmable Pulse
Generator outputs
P00_5
AD05
General purpose I/O
External bus interface (non-
multiplexed mode) data line
External bus interface
(multiplexed mode) address/
data line
80
82
External interrupt request
input pin for INT13
35
29
INT13
H
Relocated USART8 serial
clock I/O (not available on
MB96F348H/T)
SCK8_R
PPG9_R
Relocated
Programmable Pulse
Generator outputs
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
19
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P00_6 to
P00_7
General purpose I/O
External bus interface (non-
multiplexed mode) data lines
External bus interface
(multiplexed mode) address/
data lines
AD06 to
AD07
81 to 82
83 to 84
36 to 37
30 to 31
H
INT14 to
INT15
External interrupt request
input pins for INT14 to INT15
PPG10_R
to
PPG11_R
Relocated
Programmable Pulse
Generator outputs
P01_0
General purpose I/O
External bus interface (non-
multiplexed mode) data line
External bus interface
(multiplexed mode) address/
data line
AD08
83
85
H
40
32
Reload Timer 1 event input
pin
TIN1
Clock Output Function 1
clock output
CKOT1
Relocated PPG16 trigger
input
TTG16_R
P01_1
General purpose I/O
External bus interface (non-
multiplexed mode) data line
External bus interface
(multiplexed mode) address/
data line
AD09
84
86
41
33
H
TOT1
Reload Timer 1 output
Clock Output Function 1
inverted Clock Output
CKOTX1
TTG17_R
Relocated PPG17 trigger
20
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P01_2
AD10
General purpose I/O
External bus interface (non-
multiplexed mode) data line
External bus interface
(multiplexed mode) address/
data line
85
87
42
34
H
SIN3
USART 3 serial data input
Relocated external interrupt
request input for INT11
INT11_R
TTG18_R
P01_3
Relocated PPG18 trigger
General purpose I/O
External bus interface (non-
multiplexed mode) data line
External bus interface
(multiplexed mode) address/
data line
86
88
AD11
43
35
H
SOT3
TTG19_R
P01_4
USART 3 serial data output
Relocated PPG19 trigger
General purpose IO
External bus interface (non-
multiplexed mode) data line
External bus interface
(multiplexed mode) address/
data line
87
89
AD12
36
H
44
SCK3
USART 3 clock I/O
PPG16_R
Relocated Pulse
Programable output
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
21
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P01_5
AD13
General purpose IO
External bus interface (non-
multiplexed mode) data line
External bus interface
(multiplexed mode) address/
data line
92
94
45
37
H
Relocated external interrupt
request pin for INT7
INT7_R
Relocated USART 2 serial
data input
SIN2_R
PPG17_R
Relocated Pulse
Programable output
P01_6
AD14
General purpose IO
External bus interface (non-
multiplexed mode) data line
External bus interface
(multiplexed mode) address/
data line
93
95
46
38
H
Relocated USART2 serial
data output
SOT2_R
PPG18_R
Relocated Pulse
Programable output
P01_7
AD15
General purpose IO
External bus interface (non-
multiplexed mode) data line
External bus interface
(multiplexed mode) address/
data line
94
96
47
39
H
SCK2_R
Relocated USART2 clock I/O
PPG19_R
Relocated Pulse
Programable output
22
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P02_0
General purpose IO
36
Programmable Pulse
Generator outputs
PPG12
95
97
50
40
H
H
External bus interface
address output
A16
Relocated Clock Output
Function 1 clock output
36
35
CKOT1_R
P02_1
General purpose IO
Programmable Pulse
Generator output
PPG13
51
52
96
97
98
99
41
42
External bus interface
address output
A17
P02_2
PPG14
General purpose IO
34
Programmable Pulse
Generator output
H
H
H
External bus interface
address output
A18
CKOT0_R
Relocated Clock Output
Function 0 clock output
34
33
P02_3
General purpose IO
Programmable Pulse
Generator output
PPG15
53
98
100
43
External bus interface
address output
A19
P02_4
IN0
General purpose IO
32
Input Capture Unit 0 data
sample input
Programmable Pulse
Generator PPG0 and PPG8
trigger input
54
99
1
44
TTG0/
TTG8
External bus interface
address output
A20
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
23
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P02_5
General purpose IO
Relocated A/D converter
trigger input
ADTG_R
31
Input Capture Unit ICU 1 data
sample input
IN1
65
100
1
51
H
H
H
Programmable Pulse
Generator PPG1 and PPG9
trigger
TTG1/
TTG9
External bus interface
address output
A21
P02_6,
P02_7
General purpose IO
30, 29
Input Capture Unit ICU2 to
ICU3 data sample input
IN2, IN3
Programmable Pulse
Generator PPG2 and PPG10
trigger,
Programmable Pulse
Generator PPG3 and PPG11
trigger
TTG2/
TTG10,
TTG3/
TTG11
56, 57
1, 2
3, 4
External bus interface
address outputs
A22, A23
P03_0
IN4
General purpose IO
Input Capture Unit 4 data
sample input
External bus interface
address latch enable output
pin
3
5
ALE
68
54
Programmable Pulse
Generator PPG4 and PPG12
trigger
TTG4/
TTG12
Reload Timer 0 relocated
output
TOT0_R
24
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P03_1
RDX
General purpose IO
External bus interface read
strobe output
Input Capture Unit ICU 5 data
sample input
4
6
IN5
69
55
H
Programmable Pulse
Generator PPG5 and PPG13
trigger
TTG5/
TTG13
TOT2_R
P03_2
Reload Timer 2 relocated
output
General purpose IO
External bus (16-bit data
mode) interface low byte write
strobe output pin
External bus (8-bit data
mode) interface write strobe
output pin
WRLX /
WRX
5
7
70
56
H
Relocated external interrupt
request input for INT10
INT10_R
CAN2 interface RX input
(not available on
RX2
MB96F3xxA, MB96F3xxC)
P03_3
WRHX
General purpose IO
External bus interface write
strobe output pin for the 8
higher bits of the data bus
6
8
71
72
57
58
H
H
CAN2 interface TX output pin
(not available on
MB96F3xxA, MB96F3xxC)
TX2
P03_4
HRQ
General purpose IO
External bus interface hold
request input
7
9
Output Compare Unit OCU4
waveform output
OUT4
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
25
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P03_5
HAKX
General purpose IO
External bus interface hold
acknowledge output
73
8
10
11
59
H
H
H
Output Compare Unit OCU5
waveform output
OUT5
P03_6
RDY
General purpose IO
External bus interface
external wait state request
74
9
60
Output Compare Unit OCU6
waveform output
OUT6
P03_7
CLK
General purpose IO
External bus interface clock
output pin
75
10
12
61
Output Compare Unit OCU7
waveform output pin
OUT7
P04_0,
P04_1
General purpose IO (only for
devices with S-suffix)
H
B
24,25
11, 12
13, 14
19, 20
46, 47
Oscillator input pins for sub-
clock (only for devices without
S-suffix)
X0A, X1A
P04_2
IN6
General purpose IO
Input Capture Unit ICU6 data
sample input
CAN1 Interface RX input
(not available on
RX1
19
16
18
16
41
H
MB96F3xxA, MB96F3xxC)
Relocated external interrupt
request input pin for INT9
INT9_R
Programmable Pulse
Generators PPG6 and
PPG14 trigger
TTG6/
TTG14
26
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P04_3
IN7
General purpose IO
Input Capture Unit ICU7 data
sample input
Programmable Pulse
Generators PPG7 and
PPG15 trigger
TTG7/
TTG15
21
17
19
17
40
H
CAN1 Interface TX Output
pin
(not available on
TX1
MB96F3xxA, MB96F3xxC)
P04_4
FRCK0
SDA0
General purpose IO
45
35
18
19
20
21
Free Running Timer 0 input
I2C 0 interface serial data I/O
66
67
52
53
N
N
Reload Timer 0 event
relocated input pin
TIN0_R
P04_5
SCL0
General purpose IO
I2C 0 interface serial clock I/
O
FRCK1
TIN2_R
Free Running Timer 1 input
Reload Timer 2 event
relocated input pin
P04_6
SDA1
P04_7
General purpose IO
20
21
22
23
N
N
I2C 1 interface serial data I/O
General purpose IO
I2C 1 interface serial clock I/
O
SCL1
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
27
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P05_0
AN8
General purpose IO
A/D converter analog input
pin
10
9
12
22
24
SIN2
I
I
USART2 serial data input
Relocated input of external
interrupt INT3
INT3_R1
ALARM0
P05_1
AN9
Alarm Comparator 0 input
General purpose IO
13
11
10
A/D converter analog input
USART 2 serial data output
Alarm Comparator 1 input
General purpose IO
23
24
25
25
26
27
SOT2
ALARM1
P05_2
AN10
14
15
12
13
11
12
I
I
A/D converter analog input
USART 2 clock I/O
SCK2
P05_3
AN11
General purpose IO
A/D converter analog input
Reload Timer 3 event input
Real Timer clock output
General purpose IO
TIN3
WOT
P05_4
AN12
A/D converter analog input
Output pin for the reload timer
3
14
15
26
27
28
29
13
14
16
17
I
I
TOT3
Relocated input of external
interrupt INT2
INT2_R
P05_5
AN13
General purpose IO
A/D converter analog input
Relocated External interrupt
INT0 input
INT0_R
NMI_R
Relocated Non-Maskable
Interrupt NMI
28
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P05_6
AN14
General purpose IO
A/D converter analog input
16
28
30
31
15
18
I
I
Relocated External Interrupt
INT4 input
INT4_R
P05_7
AN15
General purpose IO
A/D converter analog input
29
19
Relocated External Interrupt
INT5 input
17
INT5_R
Output Compare Unit OCU10
waveform reloacted output
pin
OUT10_R
P06_0 to
P06_4
General purpose IO
62, 63, 3
to 5
AN0 to
AN4
34 to 38
36 to 40
A/D converter analog input
78,79, 3
to 5
62, 63, 3
to 5
I
PPG0 to
PPG4
Programmable Pulse
Generator outputs
CS0_R to
CS4_R
External Chip selects
relocated output
P06_5
AN5
General purpose IO
A/D converter analog input
39
40
41
42
6
7
I
I
Programmable Pulse
Generator outputs
6
7
6
7
PPG5
External Chip select
relocated output
CS5_R
P06_6
AN6
General purpose IO
A/D converter analog input
Programmable Pulse
Generator outputs
PPG6
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
29
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P06_7
AN7
General purpose IO
10
A/D converter analog input
8
41
43
45
8
I
I
Programmable Pulse
Generator output
PPG7
P07_0
AN16
General purpose IO
A/D converter analog input
External interrupt INT0
request input
18
43
INT0
Non-Maskable Interrupt NMI
input
NMI
P07_1
General purpose IO
AN17 to
AN20
A/D converter analog input
9
44
46
I
I
INT1 to
INT4
External interrupt INT1 to
INT4 request input
P07_2 to
P07_4
General purpose IO
AN18to
AN20
45 to 47
47 to 49
A/D converter analog input
INT2 to
INT4
External interrupt INT2 to
INT4 request input
P07_5
AN21
General purpose IO
A/D converter analog input
External interrupt INT5
request input
I
INT5
48
50
Relocated USART9 serial
clock I/O (not available on
MB96F348H/T)
SCK9_R
30
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P07_6
AN22
General purpose IO
A/D converter analog input
External interrupt INT6
request input
I
INT6
53
55
Relocated USART 9 serial
data output (not available on
MB96F348H/T)
SOT9_R
P07_7
AN23
General purpose IO
A/D converter analog input
External interrupt INT7
request input
I
INT7
54
56
Relocated USART 9 serial
data input (not available on
MB96F348H/T)
SIN9_R
P08_0
CKOTX0
ADTG
General purpose IO
Clock Output Function 0
inverted output
11
55
57
H
A/D converter trigger input
Relocated external interrupt
INT12 request input
INT12_R
TIN0
P08_1
TOT0
Reload Timer 0 event input
General purpose IO
Reload Timer 0 output
56
57
58
59
H
H
CKOT0
Clock output function 0 output
Relocated external interrupt
INT13 request input
INT13_R
P08_2
SIN0
TIN2
General purpose IO
USART 0 serial data input
Reload Timer 2 event input
44
Relocated external interrupt
INT14 request input
INT14_R
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
31
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P08_3
SOT0
TOT2
P08_4
SCK0
General purpose IO
USART0 serial data output
Reload timer 2 output
General purpose IO
USART0 clock I/O
58
60
61
62
42
H
H
H
59
60
43
37
Relocated external interrupt
INT15 request input
INT15_R
P08_5
SIN1
General purpose IO
USART1 serial data input
Relocated external interrupt
INT1 request input
INT1_R
P08_6
SOT1
P08_7
SCK1
P09_0
General purpose IO
USART1 serial data output
General purpose IO
USART1 clock I/O
61
62
63
64
39
38
H
H
General purpose IO
Programmable Pulse
Generator 8 output
PPG8
UBX
38
39
48
65
66
67
67
68
69
H
H
H
External Bus Interface Upper
Byte select strobe
P09_1
PPG9
General purpose IO
Output pin for PPG 9
External Bus Interface Lower
Byte select strobe
LBX
P09_2
PPG10
General purpose IO
Programmable Pulse
Generator 10 output
External Bus Interface Chip
Select 5
CS5
32
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P09_3
General purpose IO
Programmable Pulse
Generator 11 output
PPG11
H
H
H
49
68
70
External Bus Interface Chip
Select 4
CS4
P09_4 to
P09_7
General purpose IO
69 to 72
71 to 74
OUT0 to
OUT3
Output Compare Unit OCU0
to OCU3 waveform output
CS3 to
CS0
External Bus Interface Chip
Select 3 to 0
P10_0
General purpose IO
CAN0 interface RX input
(not available on
MB96F3xxA, MB96F3xxC)
RX0
73
74
75
76
Relocated external interrupt
INT8 request input
INT8_R
P10_1
General purpose IO
CAN0 interface TX output
(not available on
MB96F3xxA, MB96F3xxC)
H
I
TX0
P13_5
General purpose IO
64
Programmable Pulse
Generator17 output
PPG17
P13_6 ,
P13_7
General purpose IO
Programmable Pulse
Generator output
76,77
PPG18,P
PG19
I
Input Capture Unit ICU8,
ICU9 data sample input
IN8,IN9
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
33
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
P17_2
General purpose IO
FRCK3
Free Running Timer3 input
63
I
Programmable Pulse
Generators PPG17 trigger
TTG17
P17_6
OCU11
General purpose IO
Output Compare Unit OCU11
waveform output pin
Input Capture Unit ICU10
data sample input
IN10
20
I
Programmable Pulse
Generators PPG18 trigger
TTG18
Relocated input of external
interrupt INT3
INT3_R
P17_7
IN11
General purpose IO
Input Capture Unit ICU11
data sample input
29
80
I
Programmable Pulse
Generators PPG19 trigger
TTG19
AVCC
Analog circuits VCC power
supply
30
31
32
33
64
2
1
2
F
A/D converter upper
reference voltage
Supply voltage to AVCC pin
must be kept higher than or
equal to AVRH pin voltage
specially when the supply
voltage to AVRH is turned on
or off
2
1
AVRH
G
A/D converter lower
reference voltage
32
33
34
35
AVRL
AVSS
F
F
Analog circuits VSS power
supply
1
48
34
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
PIN DESCRIPTION FOR MB96(F)32x, MB96(F)34x, MB96(F)35x, MB96(F)36x
Pin no.
Circuit
type
MB9632
x
MB9635
x
MB9636
x
Pin name
Function
MB9634x
QFP100*1
LQFP64*3
LQFP48*4
LQFP80*5
LQFP100*2
Input pins for specifying the
operating mode
The pins must be directly
connected to VCC or VSS
26, 27,
28
49, 50,
51
51, 52,
53
21, 22,
23
20, 21,
22
MD2,
MD1, MD0
C
13, 63,
88
15, 65,
90
22,61
23,60
49
24
25
VCC
VSS
Power supply
Power supply
13, 42,
64, 89
16, 44,
66, 91
18, 48
Internally regulated power
supply stabilization capacitor
pin. Please refer to the
datasheet for recommended
capacitor values.
62
15
17
50
26
C
F
*1: FPT-100P-M22
*2: FPT-100P-M20
*3: FPT-64P-M23/M24
*4: FPT-48P-M26
*5: FPT-80P-M21
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
35
MB96300 Series
Preliminary Specification
■ PIN DESCRIPTION FOR MB96(F)38X
PIN DESCRIPTION FOR MB96(F)38X
Pin no.
Pin name
Circuit
type
Function
MB96(F)38x
LQFP120*1
65
66
68
X0
A
Oscillation input
X1
A
B
H
B
H
E
J
Oscillation output
X0A
Oscillation input (only for devices without S-suffix)
General purpose I/O (only for devices with S-suffix)
Oscillation output (only for devices without S-suffix)
General purpose I/O (only for devices with S-suffix)
Reset input
P04_0
X1A
69
P04_1
RSTX
P11_0
A01
70
71
General purpose I/O
External bus (non-multiplexed mode) address line
LCD controller/driver common output pin
External bus chip select 5
COM0
CS5
72 to 74
P11_1 to
P11_3
J
General purpose I/O
A02 to A04
External bus (non-multiplexed mode) address lines
LCD controller/driver common output pins
COM1 to
COM3
PPG0_R to
PPG2_R
Relocated Programmable Pulse Generator 0 to 2 outputs
General purpose I/O
75, 76
P11_4,
P11_5
J
A05, A06
External bus (non-multiplexed mode) address lines
LCD controller / driver segment outputs
SEG0, SEG1
PPG3_R,
PPG4_R
Relocated Programmable Pulse Generator 3 and 4 outputs
77
P11_6
FRCK0_R
A07
J
General purpose I/O
Relocated Free-Running Timer 0 clock input
External bus (non-multiplexed mode) address line
LCD controller / driver segment output
MB96300_shortspec.fm
SEG2
36
FME/EMDC- 2007-02-12
Preliminary Specification
MB96300
PIN DESCRIPTION FOR MB96(F)38X
Pin no.
Pin name
Circuit
type
Function
MB96(F)38x
LQFP120*1
78, 79
P11_7,
J
General purpose I/O
P12_0
IN0_R,IN1_R
A08, A09
SEG3, SEG4
P12_1
Input Capture Unit relocated input pin
External bus (non-multiplexed mode) address lines
LCD controller / driver segment output
General purpose I/O
80
J
J
J
TIN1_R
A10
Relocated event input pin for Reload Timer 1
External bus (non-multiplexed mode) address line
LCD controller / driver segment output
General purpose I/O
SEG5
81
P12_2
TOT1_R
A11
Relocated output pin for Reload Timer 1
External bus (non-multiplexed mode) address line
LCD controller / driver segment output
General purpose I/O
SEG6
82, 83
P12_3,
P12_4
OUT2_R,
TOT2_R
Relocated waveform output pins of Output Compare Units
A12, A13
SEG7, SEG8
P12_5
External bus (non-multiplexed mode) address lines
LCD controller / driver segment outputs
General purpose I/O
84
85
J
J
TIN2_R
A14
Relocated event input pin for Reload Timer 2
External bus (non-multiplexed mode) address line
LCD controller / driver segment output
General purpose I/O
SEG9
P12_6
TOT2_R
A15
Relocated output pin for Reload Timer 2
External bus (non-multiplexed mode) address line
LCD controller / driver segment output
SEG10
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
37
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)38X
Pin no.
Pin name
Circuit
type
Function
MB96(F)38x
LQFP120*1
86
P12_7
J
J
J
J
J
General purpose I/O
INT1_R
HRQ
Relocated external interrupt 1
External bus Hold Request
SEG11
P00_0
INT3_R
HAKX
SEG12
P00_1
INT4_R
WRHX
SEG13
P00_2
INT5_R
RDY
LCD controller / driver segment output
General purpose I/O
87
88
89
92
Relocated external interrupt 3
External bus Hold Acknowlegde
LCD controller / driver segment output
General purpose I/O
Relocated external interrupt 4
External bus High byte Write strobe
LCD controller / driver segment output
General purpose I/O
Relocated external interrupt 5
External bus external wait state request
LCD controller / driver segment output
General purpose I/O
SEG14
P00_3
INT6_R
A00
Relocated external interrupt 6
External bus (non-multiplexed mode) address line
External bus relocated Chip Select 3
LCD controller / driver segment output
General purpose I/O
CS3_R
SEG15
P00_4
INT7_R
ALE
93
J
Relocated external interrupt 7
External bus Address Latch Enable signal
LCD controller / driver segment output
SEG16
38
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
PIN DESCRIPTION FOR MB96(F)38X
Pin no.
Pin name
Circuit
type
Function
MB96(F)38x
LQFP120*1
94
P00_5
J
J
General purpose I/O
TTG2
IN6
Programmable Pulse Generator 2 trigger
Input Capture Unit ICU 6 data sample input
External bus Read Strobe
RDX
SEG17
P00_6
TTG3
IN7
LCD controller / driver segment output
General purpose I/O
95
Trigger for Programmable Pulse Generator 3
Input Capture Unit ICU7 data sample input
WRLX
WRX
External bus (16-bit data mode) low byte write strobe
External bus (8-bit data mode) write strobe
LCD controller / driver segment output
General purpose I/O
SEG18
P00_7
SGO0
CLK
96
97
J
J
SGO output of Sound Generator 0
External bus clock
SEG19
P01_0
SGA0
AD00
LCD controller / driver segment output
General purpose I/O
SGA output of Sound Generator 0
External bus (non-multiplexed mode) data line and External bus
(multiplexed mode) address/data line
SEG20
P01_1
OUT0
CKOT1
AD01
LCD controller / driver segment output
General purpose I/O
98
J
Output Compare Unit OCU0 waveform output
Output of Clock Output function 1
External bus (non-multiplexed mode) data line and External bus
(multiplexed mode) address/data line
SEG21
LCD controller / driver segment output
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
39
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)38X
Pin no.
Pin name
Circuit
type
Function
MB96(F)38x
LQFP120*1
99
P01_2
J
General purpose I/O
OUT1
Waveform output pin for Output Compare Unit 1
Clock Output function 1 inverted output
CKOTX1
AD02
External bus (non-multiplexed mode) data line and External bus
(multiplexed mode) address/data line
SEG22
P01_3
PPG5
AD03
LCD controller / driver segment output
General purpose I/O
100
101
102
103
J
J
J
J
Programmable Pulse Generator 5 output
External bus (non-multiplexed mode) data line and External bus
(multiplexed mode) address/data line
SEG23
P01_4
AD04
LCD controller / driver segment output
General purpose I/O
External bus (non-multiplexed mode) data lines and External bus
(multiplexed mode) address/data lines
SIN4
USART 4 serial data input
LCD controller / driver segment outputs
General purpose I/O
SEG24
P01_5
AD05
External bus (non-multiplexed mode) data lines and External bus
(multiplexed mode) address/data lines
SOT4
SEG25
P01_6
AD06
USART 4 serial data output
LCD controller / driver segment outputs
General purpose I/O
External bus (non-multiplexed mode) data lines and External bus
(multiplexed mode) address/data lines
SCK4
USART 1 serial clock
SEG26
LCD controller / driver segment outputs
40
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
PIN DESCRIPTION FOR MB96(F)38X
Pin no.
Pin name
Circuit
type
Function
MB96(F)38x
LQFP120*1
104
P01_7
J
J
J
General purpose I/O
CKOTX1_R
AD07
Relocated Clock Output function 1 inverted output
External bus (non-multiplexed mode) data line and External bus
(multiplexed mode) address/data line
SEG27
P02_0
LCD controller / driver segment output
General purpose I/O
105
CKOT1_R
AD08
Relocated clock output function 1 output
External bus (non-multiplexed mode) data line and External bus
(multiplexed mode) address/data line
SEG28
LCD controller / driver segment output
General purpose I/O
106, 107
P02_1,
P02_2
IN6_R,
IN7_R
Relocated Input Capture Units 6 and 7 data sample input pins
AD09, AD10
External bus (non-multiplexed mode) data line and External bus
(multiplexed mode) address/data line
SEG29,
SEG30
LCD controller / driver segment output
108
109
P02_3
SGO0_R
AD11
J
J
General purpose I/O
Relocated Sound Generator 0 SGO output
External bus (non-multiplexed mode) data line and External bus
(multiplexed mode) address/data line
SEG31
P02_4
SGA0_R
AD12
LCD controller / driver segment output
General purpose I/O
Relocated Sound generator 0 SGA output
External bus (non-multiplexed mode) data line and External bus
(multiplexed mode) address/data line
SEG32
LCD controller / driver segment output
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
41
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)38X
Pin no.
Pin name
Circuit
type
Function
MB96(F)38x
LQFP120*1
110,111
P02_5,
J
General purpose I/O
P02_6
OUT0_R,
OUT1_R
Relocated Output Compare Units OCU 0 and OCU 1 waveform
outputs
AD13, AD14
External bus (non-multiplexed mode) data line and External bus
(multiplexed mode) address/data lines
SEG33,
SEG34
LCD controller / driver segment outputs
112
P02_7
PPG5_R
AD15
J
J
General purpose I/O
Relocated Programmable Pulse Generator 5 output
External bus (non-multiplexed mode) data line and External bus
(multiplexed mode) address/data line
SEG35
LCD controller / driver segment output
General purpose I/O
113 to 116
P03_0 to
P03_3
V0 to V3
LCD controller / driver reference voltage pins (when reference
voltage is externally supplied)
A16 to A19
External bus (non-multiplexed mode) data line and External bus
(multiplexed mode) address/data lines
SEG36 to
SEG39
LCD controller / driver segment outputs (when reference voltage is
internally supplied)
117
P03_4
INT4
RX0
J
General purpose I/O
External Interrupt 4
CAN0 interface RX input
General purpose I/O
118
119
P03_5
TX0
J
J
CAN0 Interface TX output
General purpose I/O
P03_6
NMI
Non-Maskable Interrupt input
External interrupt 0 input
INT0
42
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
PIN DESCRIPTION FOR MB96(F)38X
Pin no.
Pin name
Circuit
type
Function
MB96(F)38x
LQFP120*1
3
P03_7
J
J
J
J
General purpose I/O
INT1
External Interrupt 1 input
USART 1 serial data input
External bus Chip Select 0
External bus address line
SIN1
CS0
A20
SEG40
P13_0
INT2
LCD controller / driver segment output
General purpose I/O
4
5
6
External Interrupt 2 input
SOT1
CS1
USART 1 serial data output
External bus Chip Select 1
External bus address line
A21
SEG41
P13_1
INT3
LCD controller / driver segment output
General purpose I/O
External Interrupt 3 input
SCK1
CS2
USART 1 serial clock
External bus Chip Select 1
External bus address line
A22
SEG42
P13_2
PPG0
TIN0
LCD controller / driver segment output
General purpose I/O
Output pin for Programmable Pulse Generator 0
Reload Timer 0 input pin
FRCK1
CS3
Free Running Timer 1 input pin
External bus Chip Select 3
External bus address line
A23
SEG43
LCD controller / driver segment output
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
43
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)38X
Pin no.
Pin name
Circuit
type
Function
MB96(F)38x
LQFP120*1
7
P13_3
J
General purpose I/O
PPG1
TOT0
WOT
Output pin for Programmable Pulse Generator 1
Reload Timer 0 output
Real Time Clock output
UBX
External bus Upper Byte Strobe
LCD controller / driver segment output
General purpose I/O
SEG44
P13_4
SIN0
8
9
J
J
USART 0 data input
INT6
External interrupt 1 input
SEG45
P13_5
SOT0
ATDG
INT7
LCD controller / driver segment output
General purpose I/O
USART 0 data input
A/D converter trigger input
External interrupt 7 input
SEG46
P13_6
SCK0
CKOTX0
LBX
LCD controller / driver segment output
General purpose I/O
10
11
12
J
J
J
USART 0 clock
Clock Output function 0 inverted output
External bus interface low byte strobe
LCD controller / driver segment output
General purpose I/O
SEG47
P13_7
PPG2
CKOT0
CS4
Programmable Pulse Generator 2 output
Clock Output function 0 output
External bus interface Chip Select 4
LCD controller / driver segment output
General purpose I/O
SEG48
P04_4
PPG3
SDA0
Programmable Pulse Generator 3 output
I2C interface 0 data I/O
44
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
PIN DESCRIPTION FOR MB96(F)38X
Pin no.
Pin name
Circuit
type
Function
MB96(F)38x
LQFP120*1
13
P04_5
J
General purpose I/O
PPG4
SCL0
P06_0
AN0
Programmable Pulse Generator 4 output
I2C interface 0 clock I/O
14
15
16
17
K
K
K
K
General purpose I/O
A/D converter inputs
SCK5
IN2_R
SEG49
P06_1
AN1
USART 5 Serial clock
Input Capture Unit relocated input pin
LCD controller / driver segment outputs
General purpose I/O
A/D converter inputs
SOT5
IN3_R
SEG50
P06_2
AN2
USART 5 Serial data output
Input Capture Unit relocated input pin
LCD controller / driver segment outputs
General purpose I/O
A/D converter input
INT5
External interrupt input
SIN5
USART 5 Serial input data
LCD controller / driver segment output
General purpose I/O
SEG51
P06_3
AN3
A/D converter input
FRCK0
SEG52
Free Running Timer 0 clock input
LCD controller / driver segment output
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MB96300_shortspec.fm
45
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)38X
Pin no.
Pin name
Circuit
type
Function
MB96(F)38x
LQFP120*1
18, 19
P06_4,
K
General purpose I/O
P06_5
AN4, AN5
IN0, IN1
A/D converter inputs
Input Capture Unit input pin
TTG0/TTG4,
TTG1/TTG5
Programmable Pulse Generator 0 and 4 external trigger,
Programmable Pulse Generator 1 and 5 external trigger
SEG53,
SEG54
LCD controller / driver segment outputs
20
21
P06_6
AN6
K
K
General purpose I/O
A/D converter input
TIN1
Reload Timer 1 input
IN4_R
SEG55
P06_7
AN7
Input Capture Unit relocated input pin
LCD controller / driver segment output
General purpose I/O
A/D converter input
TOT1
IN5_R
SEG56
AVCC
AVRH
Reload Timer 1 output
Input Capture Unit relocated input pin
LCD controller / driver segment output
Analogue circuits power supply
22
23
F
G
A/D converter high reference voltage
Supply voltage to AVCC pin must be kept higher than or equal to
AVRH pin voltage especially when the supply voltage to AVRH is
turned on or off
24
25
AVRL
AVSS
F
F
A/D converter low reference voltage
Analogue circuits power supply
46
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
PIN DESCRIPTION FOR MB96(F)38X
Pin no.
Pin name
Circuit
type
Function
MB96(F)38x
LQFP120*1
26, 27
P05_0,
K
General purpose I/O
P05_1
AN8, AN9
A/D converter inputs
ALARM0,
ALARM1
Alarm comparator 0, 1 inputs
SEG57,
SEG58
LCD controller / driver segment outputs
28
29
32
33
P05_2
AN10
K
K
K
K
General purpose I/O
A/D converter inputs
OUT2
SGO1
SEG59
P05_3
AN11
Output Compare Unit 2 and 3 waveform output pins
SGO output of Sound Generator 1
LCD controller / driver segment outputs
General purpose I/O
A/D converter inputs
OUT3
SGA1
SEG60
P05_4
AN12
Output Compare Unit 2 and 3 waveform output pins
SGA output of Sound Generator 1
LCD controller / driver segment outputs
General purpose I/O
A/D converter input
RX1
CAN controller 1 data receive
Relocated External Interrupt 2 input
LCD controller / driver segment output
General purpose I/O
INT2_R
SEG61
P05_5
AN13
A/D converter input
TX1
CAN controller 1 data transmit
LCD controller / driver segment output
SEG62
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
47
MB96300 Series
Preliminary Specification
PIN DESCRIPTION FOR MB96(F)38X
Pin no.
Pin name
Circuit
type
Function
MB96(F)38x
LQFP120*1
34
P05_6
K
General purpose I/O
AN14
A/D converter input
TIN2
Reload Timer 2 event input
Relocated SGO output of Sound Generator 1
LCD controller / driver segment output
General purpose I/O
SGO1_R
SEG63
P05_7
AN15
35
K
A/D converter input
TOT2
Reload Timer 2 output
SGA1_R
SEG64
Relocated SGA output of Sound Generator 1
LCD controller / driver segment output
General purpose I/O
36 to 39
GP08_0 to
GP08_3
M
M
M
M
PWM1P0
PWM1M0
PWM2P0
PWM2M0
Stepper Motor Controller 0 outputs
40, 43 to 45
GP08_4 to
GP08_7
General purpose I/O
PWM1P1
PWM1M1
PWM2P1
PWM2M1
Stepper Motor Controller 1 outputs
46 to 49
GP09_0 to
GP09_3
General purpose I/O
PWM1P2
PWM1M2
PWM2P2
PWM2M2
Stepper Motor Controller 2 outputs
50 to 52, 55 GP09_4 to
GP09_7
General purpose I/O
PWM1P3
PWM1M3
PWM2P3
PWM2M3
Stepper Motor Controller 3 outputs
48
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
PIN DESCRIPTION FOR MB96(F)38X
Pin no.
Pin name
Circuit
type
Function
MB96(F)38x
LQFP120*1
56
GP10_0
PWM1P4
SIN2
M
General purpose I/O
Stepper Motor Controller 4 output
USART 2 Serial data input
TIN3
Reload Timer 3 event input
General purpose I/O
57
58
GP10_1
PWM1M4
SOT2
M
M
Stepper Motor Controller 4 output
USART 2 Serial data output
Reload Timer 3 output
TOT3
GP10_2
PWM2P4
SCK2
General purpose I/O
Stepper Motor Controller 4 output
USART 2 clock
PPG6
Programmable Pulse Generator 6 output
General purpose I/O
59
GP10_3
PWM2M4
PPG7
M
C
Stepper Motor Controller 4 output
Programmable Pulse Generator 7 output
Input pins for specifying the operating mode
62, 63, 64
MD0, MD1,
MD2
The pins must be directly connected to VCC or VSS
30, 60, 90,
120
VCC
Power supply
1, 31, 61, 91 VSS
Power supply
41, 53,
42, 54
2
DVCC
High current I/O power supply
High current I/O power supply
DVSS
C
F
Internally regulated power supply stabilization capacitor pin. Please
refer to the datasheet for recommended capacitor values.
*1: FPT-120P-M21
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
49
MB96300 Series
Preliminary Specification
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
Oscillation circuit
High-speed oscillation feedback resistor =
approx. 1 MΩ
X1
X0
Xout
Standby control signal
B
Oscillation circuit
Low-speed oscillation feedback resistor =
approx. 10 MΩ
X1A
X0A
Xout
Standby control signal
C
E
Mask ROM and EVA device:
CMOS Hysteresis input pin
Flash device:
R
Hysteresis
inputs
CMOS input pin
CMOS Hysteresis input pin
Pull-up resistor value: approx. 50 kΩ
Pull-up
Resistor
R
Hysteresis
inputs
F
Power supply input protection circuit
50
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Type
Circuit
Remarks
G
A/D converter ref+ (AVRH) power supply input
pin, With the protection circuit
ANE
AVR
Flash devices do not have a protection circuit
against VCC for pin AVRH
ANE
H
CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up registor:50kΩ approx.
pull-up control
Pout
Nout
R
Hysteresis input
Hysteresis input
Automotive inputs
TTL input
Standby control for
input shutdown
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
51
MB96300 Series
Preliminary Specification
Type
Circuit
Remarks
I
CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function)
TTL input with input shutdown function
Programmable pull-up registor: 50kΩ approx.
Analogue input
pull-up control
Pout
Nout
R
Hysteresis input
Hysteresis input
Automotive inputs
TTL input
Standby control for
input shutdown
Analog input
J
CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function)
TTL input with input shutdown function
Programmable pull-up registor: 50kΩ approx.
SEG or COM output
pull-up control
Pout
Nout
R
Hysteresis input
Hysteresis input
Automotive inputs
TTL input
Standby control for
input shutdown
SEG, COM output
52
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Type
Circuit
Remarks
K
CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function)
TTL input with input shutdown function
Programmable pull-up registor: 50kΩ approx.
Analogue input
pull-up control
Pout
Nout
SEG output
R
Hysteresis input
Hysteresis input
Automotive inputs
TTL input
Standby control for
input shutdown
Analog input
SEG output
L
CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function)
TTL input with input shutdown function
Programmable pull-up registor:50kΩ approx.
Analogue input
pull-up control
Pout
Nout
R
Hysteresis input
Hysteresis input
Automotive inputs
TTL input
Standby control for
input shutdown
Analog input
SEG output
V input
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
53
MB96300 Series
Preliminary Specification
Type
Circuit
Remarks
M
CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA, IOL =
30mA, IOH = -30mA)
2 different CMOS hysteresis inputs with input
shutdown function
pull-up control
Pout
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up registor:50kΩ approx.
Nout
R
Hysteresis input
Hysteresis input
Automotive inputs
TTL input
Standby control for
input shutdown
N
CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up registor:50kΩ approx.
pull-up control
Pout
Nout
R
Hysteresis input
Hysteresis input
Automotive inputs
TTL input
Standby control for
input shutdown
54
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
■ HANDLING DEVICES
Special care is required for the following when handling the device:
• Preventing latch-up
• Treatment of unused pins
• Using external clock
• Precautions for when not using a sub clock signal
• Notes on during operation of PLL clock mode
• Power supply pins (VCC/VSS)
• Crystal Oscillator Circuit
• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
• Connection of Unused Pins of A/D Converter
• Notes on Energization
• Stabilization of power supply voltage
1. Preventing latch-up
• CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS.
• The AVCC power supply is applied before the VCC voltage.
• Latch-up may increase the power supply current drastically, causing thermal damage to the device.
• For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the
digital power-supply voltage.
2. Treatment of unused pins
• Unused input pins may be left open when the input is disabled (corresponding bit of Port Input Enable register
PIER = 0).
• Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent
damage of the device. Therefore they must be pulled up or pulled down through resistors. To prevent latchup,
those resistors should be more than 2 kOhm.
• Unused bidirectional pins should be set to the output state and can be left open, or the input state with either
input disabled or external pull-up/pull-down resistor as described above.
3. Using external clock
• To use external clock, drive the X0 pin and leave X1 pin open.
4. Precautions for when not using a sub clock signal
• If you do not connect pins X0A and X1A to an oscillator, use a pull-down resistor on the X0A pin, and
• leave the X1A pin open.
5. Notes on during operation of PLL clock mode
• If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the
microcontroller attempts to be working with the freely oscillating PLL. Performance of this operation, however,
cannot be guaranteed.
6. Power supply pins (VCC/VSS)
• Ensure that all VCC-level power supply pins are at the same potential. In addition, ensure the same for all
VSS-level power supply pins. If there are more than one VCC or VSS system, the device may operate
incorrectly even within the guaranteed operating range.
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
55
MB96300 Series
Preliminary Specification
• Connect VCC and VSS to the device from the power supply with lowest possible impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor
between VCC and VSS as close as possible to VCC and VSS pins.
7. Crystal Oscillator Circuit
• Noise at X0 or X1 pins may possibly cause abnormal operation. Make sure to provide bypass capacitors with
shortest distance to X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to
the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
• It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
8. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
• Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) after
turning-on the digital power supply (VCC).
• Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies
simultaneously is acceptable).
9. Connection of Unused Pins of A/D Converter
• Connect unused pins of A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS.
10. Notes on Energization
• To prevent malfunction of the internal voltage regulator, supply voltage profile while turning on the power
supply should be slower than 50us from 0.2 V to 2.7 V.
11. Stabilization of power supply voltage
• If the power supply voltage varies acutely even within the operation assurance range of the Vcc power supply
voltage, a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization
guidelines, stabilize the power supply voltage so that Vcc ripple fluctuations (peak to peak value) in the
commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the
transient fluctuation rate becomes 0.1V/µs or less in instantaneous fluctuation for power supply switching.
56
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
■ BLOCK DIAGRAMS
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
57
MB96300 Series
Preliminary Specification
Block Diagram of MB96V300
AD00 ... AD15
A00 ... A23
ALE
RDX
X0, X1
X0A, X1A
RSTX
WRLX, WRHX
HRQ
HAKX
MD0...MD2
NMI
RDY
CLK
LBX, UBX
CS0 ... CS5
Emulation
Memory
Interface
Memory Patch
Unit
Clock &
Mode Controller
Interrupt
Controller
External Bus
Interface
Debug Support
Unit Interface
16FX
CPU
16FX Core Bus (CLKB)
Voltage
Regulator
DMA
Controller
Peripheral
Bus Bridge
Peripheral
Bus Bridge
Watchdog
88kB RAM
Boot ROM
VCC
VSS
C
SDA0 ... SDA1
SCL0 ... SCL1
I2C
2 ch.
CAN
Interface
5 ch.
TX0 ... TX4
RX0 ... RX4
AVCC
AVSS
10-bit ADC
40 ch.
AVRH
AVRL
AN0 ... AN39
Sound
Generator
SGO0
SGA0
ADTG
16-bit Reload
Timer
TIN0 ... TIN5
SIN0 ... SIN9
SOT0 ... SOT9
SCK0 ... SCK9
TOT0 ... TOT5
USART
10 ch.
6 ch.
FRCK0
IN0 ... IN3
OUT0 ... OUT3
I/O Timer 0
ICU 0/1/2/3
OCU 0/1/2/3
ALARM0
ALARM1
Alarm
Comparator
2 ch.
FRCK1
IN4 ... IN7
OUT4 ... OUT7
I/O Timer 1
ICU 4/5/6/7
OCU 4/5/6/7
TTG0 ... TTG19
PPG0 ... PPG19
16-bit PPG
20 ch.
I/O Timer 2
ICU 8/9
FRCK2
IN8, IN9
PWM1M0 ... PWM1M5
PWM1P0 ... PWM1P5
PWM2M0 ... PWM2M5
PWM2P0 ... PWM2P5
OCU 8/9
OUT8 ... OUT9
Stepper
Motor
Controller
FRCK3
IN10,IN11
OUT10 ... OUT11
I/O Timer 3
ICU 10/11
OCU 10/11
DVDD
DVSS
6 ch.
External
Interrupt
Real Time
Clock
WOT
INT0 ... INT15
LCD
controller/
driver
V0 ... V3
COM0 ... COM3
SEG0 ... SEG71
Clock Output
Function
2 ch.
CKOT0, CKOT1
CKOTX0, CKOTX1
58
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Block Diagram of MB96F3xx
AD00 ... AD15
A00 ... A23
ALE
RDX
X0, X1
WRLX, WRHX
HRQ
X0A, X1A
RSTX
MD0...MD2
HAKX
NMI
RDY
CLK
LBX, UBX
CS0 ... CS5
Memory Patch
Clock &
Mode Controller
Interrupt
Controller
External Bus
Interface
Main Flash
Memory
Satellite Flash
Memory
16FX
CPU
Unit
16FX Core Bus (CLKB)
Voltage
Regulator
DMA
Controller
Peripheral
Bus Bridge
Peripheral
Bus Bridge
Watchdog
RAM
Boot ROM
VCC
VSS
C
SDA0 ... SDAn
SCL0 ... SCLn
I2C
n ch.
CAN
Interface
n ch.
TX0 ... TXn
RX0 ... RXn
AVCC
AVSS
10-bit ADC
n ch.
AVRH
AVRL
AN0 ... ANn
Sound
Generator
n ch.
SGOn
SGAn
ADTG
16-bit Reload
Timer
TIN0 ... TINn
SIN0 ... SINn
SOT0 ... SOTn
SCK0 ... SCKn
TOT0 ... TOTn
USART
n ch.
n ch.
FRCK0
IN0 ... INn
OUT0 ... OUTn
I/O Timer 0
ICU 0/1/2/3
OCU 0/1/2/3
ALARM0
ALARM1
Alarm
Comparator
n ch.
FRCK1
INm ... INn
OUTm ... OUTn
I/O Timer 1
ICU 4/5/6/7
OCU 4/5/6/7
TTG0 ... TTG19
PPG0 ... PPG19
16-bit PPG
n ch.
FRCK2
IN8, IN9
OUT8, OUT9
I/O Timer 2
ICU 8/9
PWM1M0 ... PWM1Mn
PWM1P0 ... PWM1Pn
PWM2M0 ... PWM2Mn
PWM2P0 ... PWM2Pn
OCU 8/9
Stepper
Motor
Controller
FRCK3
IN10,IN11
OUT10, OUT11
I/O Timer 3
ICU 10/11
OCU 10/11
n ch.
DVDD
DVSS
External
Interrupt
Real Time
Clock
WOT
INT0 ... INTn
not available
on all products
Suffix "n" denotes variable
number of instances in
different products. Please
refer to product lineup.
LCD
controller/
driver
V0 ... V3
COM0 ... COM3
SEG0 ... SEG71
Clock Output
Function
n ch.
CKOT0, CKOT1
CKOTX0, CKOTX1
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
59
MB96300 Series
Preliminary Specification
Block Diagram of MB963xx
AD00 ... AD15
A00 ... A23
ALE
RDX
X0, X1
X0A, X1A
RSTX
WRLX, WRHX
HRQ
HAKX
MD0...MD2
NMI
RDY
CLK
LBX, UBX
CS0 ... CS5
Memory Patch
Unit
Clock &
Mode Controller
Interrupt
Controller
External Bus
Interface
16FX
CPU
ROM
16FX Core Bus (CLKB)
Voltage
Regulator
DMA
Controller
Peripheral
Bus Bridge
Peripheral
Bus Bridge
Watchdog
RAM
Boot ROM
VCC
VSS
C
SDA0 ... SDAn
SCL0 ... SCLn
I2C
n ch.
CAN
TX0 ... TXn
RX0 ... RXn
AVCC
AVSS
Interface
n ch.
10-bit ADC
AVRH
n ch.
AVRL
AN0 ... ANn
Sound
Generator
n ch.
SGOn
SGAn
ADTG
16-bit Reload
Timer
TIN0 ... TINn
SIN0 ... SINn
SOT0 ... SOTn
SCK0 ... SCKn
TOT0 ... TOTn
USART
n ch.
n ch.
FRCK0
IN0 ... INn
OUT0 ... OUTn
I/O Timer 0
ICU 0/1/2/3
OCU 0/1/2/3
ALARM0
ALARM1
Alarm
Comparator
n ch.
FRCK1
INm ... INn
OUTm ... OUTn
I/O Timer 1
ICU 4/5/6/7
OCU 4/5/6/7
TTG0 ... TTG19
16-bit PPG
n ch.
PPG0 ... PPG19
FRCK2
IN8, IN9
OUT8/OUT9
I/O Timer 2
ICU 8/9
PWM1M0 ... PWM1Mn
PWM1P0 ... PWM1Pn
PWM2M0 ... PWM2Mn
PWM2P0 ... PWM2Pn
Stepper
Motor
OCU 8/9
Controller
FRCK3
IN10,IN11
OUT10/OUT11
I/O Timer 3
ICU 10/11
OCU 10/11
DVDD
DVSS
n ch.
External
Interrupt
Real Time
Clock
WOT
INT0 ... INTn
not available
on all products
Suffix "n" denotes variable
number of instances in
different products. Please
refer to product lineup.
LCD
controller/
driver
V0 ... V3
COM0 ... COM3
SEG0 ... SEG71
Clock Output
Function
n ch.
CKOT0, CKOT1
CKOTX0, CKOTX1
60
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
■ MEMORY MAP
MB96V300
MB96(F)3xx
ff.ffff
User
ROM
Start address of
User ROM area and
number of small sector
depends on the device
Main Flash
Emulation
ROM
Small Sectors
Main RCB ***
df.007f
df.0000
Satellite Flash
Satellite Flash is not available on all devices
de.002f
de.0000
10.0000
Sat RCB ***
de.0000
external
Bus
external
Bus
Boot-ROM
0f.e000
DSU
area
0f.0000
0e.0000
external
RAM
02.0000
internal
RAM
internal
RAM
01.0000
00.8000
ROM/RAM
-Mirror
ROM/RAM
-Mirror
internal
RAM
internal
RAM
RAMSTART**
00.1200
00.0c00
ext. bus
ext. bus
Peripheral
Peripheral
00.0380
00.0180
00.0100
00.00f0
GPR*
DMA
GPR*
DMA
ext. bus
ext. bus
Peripheral
00.0000 Peripheral
* Unused GPR banks can be used as RAM area.
** Please refer to the table “RAMSTART for different RAM sizes” on the next page
*** ROM Configuration Block (RCB) must not be used for other purposes than described in the manual
The external Bus area DMA area are only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device configuration.
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
61
MB96300 Series
Preliminary Specification
■ RAMSTART for different RAM sizes
Devices
RAM size
1 kB
RAMSTART
7E40
7A40
7640
2 kB
3 kB
4 kB
7240
5 kB
6E40
6A40
6640
MB96344, MB96F365, MB96384, MB96385
6 kB
7 kB
8 kB
6240
9 kB
5E40
5A40
5640
10 kB
11 kB
12 kB
13 kB
14 kB
15 kB
MB96F326, MB96F356
5240
4E40
4A40
4640
MB96(F)346, MB96(F)347, MB96(F)386,
MB96(F)387
16 kB
4240
17 kB
18 kB
19 kB
20 kB
21 kB
22 kB
23 kB
24 kB
25 kB
26 kB
27 kB
28 kB
3E40
3A40
3640
3240
2E40
2A40
2640
2240
1E40
1A40
1640
1240
MB96F348
62
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
■ I/O MAP
Table 0-1 I/O map (1 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000000H
I/O Port - Port Data Register Port 00
I/O Port - Port Data Register Port 01
I/O Port - Port Data Register Port 02
I/O Port - Port Data Register Port 03
I/O Port - Port Data Register Port 04
I/O Port - Port Data Register Port 05
I/O Port - Port Data Register Port 06
I/O Port - Port Data Register Port 07
I/O Port - Port Data Register Port 08
I/O Port - Port Data Register Port 09
I/O Port - Port Data Register Port 10
I/O Port - Port Data Register Port 11
I/O Port - Port Data Register Port 12
I/O Port - Port Data Register Port 13
I/O Port - Port Data Register Port 14
I/O Port - Port Data Register Port 15
I/O Port - Port Data Register Port 16
I/O Port - Port Data Register Port 17
ADC - Control Status Register 0 Low
ADC - Control Status Register 0 High
ADC - Data register 0 Low
PDR00
PDR01
PDR02
PDR03
PDR04
PDR05
PDR06
PDR07
PDR08
PDR09
PDR10
PDR11
PDR12
PDR13
PDR14
PDR15
PDR16
PDR17
ADCSL
ADCSH
ADCRL
ADCRH
ADSRL
ADSRH
ADECR
RW
000001H
000002H
000003H
000004H
000005H
000006H
000007H
000008H
000009H
00000AH
00000BH
00000CH
00000DH
00000EH
00000FH
000010H
000011H
000018H
000019H
00001AH
00001BH
00001CH
00001DH
00001EH
000020H
000021H
000022H
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
ADCS
ADCR
ADSR
ADC - Data register 0 High
RW
RW
RW
RW
RW
RW
RW
ADC - Setting Register 0 Low
ADC - Setting Register 0 High
ADC - Extended configuration register
FRT - Data register of free-running timer 0
FRT - Data register of free-running timer 0
TCDT0
TCCS0
FRT - Control status register of free-
running timer 0
TCCSL0
FME/EMDC- 2007-02-12
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63
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (2 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000023H
FRT - Control status register of free-
running timer 0
TCCSH0
RW
000024H
000025H
000026H
FRT - Data register of free-running timer 1
FRT - Data register of free-running timer 1
TCDT1
TCCS1
RW
RW
RW
FRT - Control status register of free-
running timer 1
TCCSL1
TCCSH1
000027H
FRT - Control status register of free-
running timer 1
RW
000028H
000029H
00002AH
00002BH
00002CH
00002DH
00002EH
00002FH
000030H
000031H
000032H
000033H
000034H
000035H
000036H
000037H
000038H
000039H
00003AH
00003BH
00003CH
00003DH
00003EH
OCU - Output Compare Control Status 0
OCU - Output Compare Control Status 1
OCU - Compare Register 0
OCS0
OCS1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
OCCP0
OCCP1
OCU - Compare Register 0
OCU - Compare Register 1
OCU - Compare Register 1
OCU - Output Compare Control Status 2
OCU - Output Compare Control Status 3
OCU - Compare Register 2
OCS2
OCS3
OCCP2
OCCP3
OCU - Compare Register 2
OCU - Compare Register 3
OCU - Compare Register 3
OCU - Output Compare Control Status 4
OCU - Output Compare Control Status 5
OCU - Compare Register 4
OCS4
OCS5
OCCP4
OCCP5
OCU - Compare Register 4
OCU - Compare Register 5
OCU - Compare Register 5
OCU - Output Compare Control Status 6
OCU - Output Compare Control Status 7
OCU - Compare Register 6
OCS6
OCS7
OCCP6
OCCP7
OCU - Compare Register 6
OCU - Compare Register 7
64
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (3 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
00003FH
OCU - Compare Register 7
ICU - Control Status Register 0/1
ICU - Edge register 0/1
RW
000040H
000041H
000042H
000043H
000044H
000045H
000046H
000047H
000048H
000049H
00004AH
00004BH
00004CH
00004DH
00004EH
00004FH
000050H
000051H
000052H
000053H
000054H
000055H
000056H
000057H
000058H
000059H
ICS01
RW
RW
R
ICE01
ICU - Capture Register 0
ICU - Capture Register 0
ICU - Capture Register 1
ICU - Capture Register 1
ICU - Control Status Register 2/3
ICU - Edge register 2/3
IPCPL0
IPCPH0
IPCPL1
IPCPH1
ICS23
IPCP0
IPCP1
R
R
R
RW
RW
R
ICE23
ICU - Capture Register 2
ICU - Capture Register 2
ICU - Capture Register 3
ICU - Capture Register 3
ICU - Control Status Register 4/5
ICU - Edge register 4/5
IPCPL2
IPCPH2
IPCPL3
IPCPH3
ICS45
IPCP2
IPCP3
R
R
R
RW
RW
R
ICE45
ICU - Capture Register 4
ICU - Capture Register 4
ICU - Capture Register 5
ICU - Capture Register 5
ICU - Control Status Register 6/7
ICU - Edge register 6/7
IPCPL4
IPCPH4
IPCPL5
IPCPH5
ICS67
IPCP4
IPCP5
R
R
R
RW
RW
R
ICE67
ICU - Capture Register 6
ICU - Capture Register 6
ICU - Capture Register 7
ICU - Capture Register 7
External Interrupt - Enable Register 0
IPCPL6
IPCPH6
IPCPL7
IPCPH7
ENIR0
IPCP6
IPCP7
R
R
R
RW
RW
External Interrupt - Interrupt request
Register 0
EIRR0
00005AH
00005BH
External Interrupt - Level Select 0
External Interrupt - Level Select 0
ELVRL0
ELVRH0
ELVR0
RW
RW
FME/EMDC- 2007-02-12
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65
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (4 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
00005CH
External Interrupt - Enable Register 1
ENIR1
EIRR1
RW
00005DH
External Interrupt - Interrupt request
Register 1
RW
00005EH
00005FH
000060H
000061H
External Interrupt - Level Select 1
External Interrupt - Level Select 1
ELVRL1
ELVRH1
ELVR1
RW
RW
RW
RW
RLT - Timer Control Status Register 0 Low TMCSRL0
TMCSR0
RLT - Timer Control Status Register 0
High
TMCSRH0
000062H
000062H
000063H
000063H
000064H
000065H
RLT - Reload Register 0 Low - for writing
RLT - Reload Register 0 Low - for reading
RLT - Reload Register 0 High - for writing
RLT - Reload Register 0 High - for reading
TMRLR0
TMR0
W
R
W
R
RLT - Timer Control Status Register 1 Low TMCSRL1
TMCSR1
RW
RW
RLT - Timer Control Status Register 1
High
TMCSRH1
000066H
000066H
000067H
000067H
000068H
000069H
RLT - Reload Register 1 Low - for writing
RLT - Reload Register 1 Low - for reading
RLT - Reload Register 1 High - for writing
RLT - Reload Register 1 High - for reading
TMRLR1
TMR1
W
R
W
R
RLT - Timer Control Status Register 2 Low TMCSRL2
TMCSR2
RW
RW
RLT - Timer Control Status Register 2
High
TMCSRH2
00006AH
00006AH
00006BH
00006BH
00006CH
00006DH
RLT - Reload Register 2 - for writing
RLT - Reload Register 2 - for reading
RLT - Reload Register 2 - for writing
RLT - Reload Register 2 - for reading
TMRLR2
TMR2
W
R
W
R
RLT - Timer Control Status Register 3 Low TMCSRL3
TMCSR3
RW
RW
RLT - Timer Control Status Register 3
High
TMCSRH3
00006EH
00006EH
00006FH
RLT - Reload Register 3 - for writing
RLT - Reload Register 3 - for reading
RLT - Reload Register 3 - for writing
TMRLR3
TMR3
W
R
W
66
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (5 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
00006FH
RLT - Reload Register 3 - for reading
R
000070H
000071H
000072H
000072H
000073H
000073H
000074H
000075H
000076H
000077H
RLT - Timer Control Status Register 6 Low TMCSRL6
(dedic. RLT for PPG) - for writing
TMCSR6
RW
RW
W
RLT - Timer Control Status Register 6
High (dedic. RLT for PPG)
TMCSRH6
RLT - Reload Register 6 Low (dedic. RLT
for PPG) - for writing
TMRLR6
TMR6
RLT - Reload Register 6 Low (dedic. RLT
for PPG) - for reading
R
RLT - Reload Register 6 High (dedic. RLT
for PPG) - for writing
W
RLT - Reload Register 6 High (dedic. RLT
for PPG) - for reading
R
PPG - General Control rgister 1 PPG 3-0
Low
GCN1L0
GCN1H0
GCN2L0
GCN2H0
GCN10
GCN20
RW
RW
RW
RW
PPG - General Control rgister 1 PPG 3-0
High
PPG - General Control rgister 2 PPG 3-0
Low
PPG - General Control rgister 2 PPG 3-0
High
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
00007FH
000080H
000081H
000082H
000083H
000084H
PPG - Timer register 0
PTMR0
PCSR0
PDUT0
PCN0
R
PPG - Timer register 0
R
PPG - Period setting register 0
PPG - Period setting register 0
PPG - Duty cycle register 0
PPG - Duty cycle register 0
PPG - Control status register 0
PPG - Control status register 0
PPG - Timer register 1
W
W
W
W
RW
RW
R
PCNL0
PCNH0
PTMR1
PCSR1
PDUT1
PPG - Timer register 1
R
PPG - Period setting register 1
PPG - Period setting register 1
PPG - Duty cycle register 1
W
W
W
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
67
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (6 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000085H
PPG - Duty cycle register 1
PPG - Control status register 1
PPG - Control status register 1
PPG - Timer register 2
PDUTH1
PCNL1
PCNH1
W
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
000090H
000091H
000092H
000093H
000094H
000095H
000096H
000097H
000098H
PCN1
RW
RW
R
PTMR2
PCSR2
PDUT2
PCN2
PPG - Timer register 2
R
PPG - Period setting register 2
PPG - Period setting register 2
PPG - Duty cycle register 2
PPG - Duty cycle register 2
PPG - Control status register 2
PPG - Control status register 2
PPG - Timer register 3
W
W
W
W
PCNL2
PCNH2
RW
RW
R
PTMR3
PCSR3
PDUT3
PCN3
PPG - Timer register 3
R
PPG - Period setting register 3
PPG - Period setting register 3
PPG - Duty cycle register 3
PPG - Duty cycle register 3
PPG - Control status register 3
PPG - Control status register 3
W
W
W
W
PCNL3
PCNH3
GCN1L1
RW
RW
RW
PPG - General Control rgister 1 PPG 7-4
Low
GCN11
000099H
00009AH
00009BH
PPG - General Control rgister 1 PPG 7-4
High
GCN1H1
GCN2L1
GCN2H1
RW
RW
RW
PPG - General Control rgister 2 PPG 7-4
Low
GCN21
PPG - General Control rgister 2 PPG 7-4
High
00009CH
00009DH
00009EH
00009FH
PPG - Timer register 4
PTMR4
PCSR4
R
PPG - Timer register 4
R
PPG - Period setting register 4
PPG - Period setting register 4
W
W
68
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (7 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0000A0H
PPG - Duty cycle register 4
PPG - Duty cycle register 4
PPG - Control status register 4
PPG - Control status register 4
PPG - Timer register 5
PDUT4
W
W
0000A1H
0000A2H
0000A3H
0000A4H
0000A5H
0000A6H
0000A7H
0000A8H
0000A9H
0000AAH
0000ABH
0000ACH
0000ADH
0000AEH
PCNL4
PCNH4
PCN4
RW
RW
R
PTMR5
PCSR5
PDUT5
PCN5
PPG - Timer register 5
R
PPG - Period setting register 5
PPG - Period setting register 5
PPG - Duty cycle register 5
PPG - Duty cycle register 5
PPG - Control status register 5
PPG - Control status register 5
I2C - Bus Status Register 0
I2C - Bus Control Register 0
W
W
W
W
PCNL5
PCNH5
IBSR0
IBCR0
ITBAL0
RW
RW
R
RW
RW
I2C - Ten bit Slave address Register 0
Low
ITBA0
ITMK0
0000AFH
0000B0H
0000B1H
I2C - Ten bit Slave address Register 0
High
ITBAH0
ITMKL0
ITMKH0
RW
RW
RW
I2C - Ten bit Address mask Register 0
Low
I2C - Ten bit Address mask Register 0
High
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
I2C - Seven bit Slave address Register 0
I2C - Seven bit Address mask Register 0
I2C - Data Register 0
ISBA0
ISMK0
IDAR0
ICCR0
IBSR1
IBCR1
ITBAL1
RW
RW
RW
RW
R
I2C - Clock Control Register 0
I2C - Bus Status Register 1
I2C - Bus Control Register 1
RW
RW
I2C - Ten bit Slave address Register 1
Low
ITBA1
0000B9H
I2C - Ten bit Slave address Register 1
High
ITBAH1
RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
69
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (8 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0000BAH
0000BBH
I2C - Ten bit Address mask Register 1
Low
ITMKL1
ITMKH1
ITMK1
RW
I2C - Ten bit Address mask Register 1
High
RW
0000BCH
0000BDH
0000BEH
0000BFH
0000C0H
I2C - Seven bit Slave address Register 1
I2C - Seven bit Address mask Register 1
I2C - Data Register 1
ISBA1
ISMK1
IDAR1
ICCR1
SMR0
RW
RW
RW
RW
RW
I2C - Clock Control Register 1
LIN USART USART - Serial Mode
Register 0
0000C1H
0000C2H
0000C2H
0000C3H
0000C4H
0000C5H
0000C6H
LIN USART - Serial Control Register 0
LIN USART - TX Register 0
SCR0
RW
W
TDR0
LIN USART - RX Register 0
RDR0
SSR0
R
LIN USART - Serial Status 0
RW
RW
RW
RW
LIN USART - Control/Com. Register 0
LIN USART - Ext. Status Register 0
ECCR0
ESCR0
BGRL0
LIN USART - Baud Rate Generator
Register 0 Low
BGR0
0000C7H
LIN USART - Baud Rate Generator
Register 0 High
BGRH0
RW
0000CAH
0000CBH
0000CCH
0000CCH
0000CDH
0000CEH
0000CFH
0000D0H
LIN USART - Serial Mode Register 1
LIN USART - Serial Control Register 1
LIN USART - TX Register 1
SMR1
SCR1
TDR1
RW
RW
W
LIN USART - RX Register 1
RDR1
SSR1
R
LIN USART - Serial Status 1
RW
RW
RW
RW
LIN USART - Control/Com. Register 1
LIN USART - Ext. Status Register 1
ECCR1
ESCR1
BGRL1
LIN USART - Baud Rate Generator
Register 1 Low
BGR1
0000D1H
0000D4H
LIN USART - Baud Rate Generator
Register 1 High
BGRH1
SMR2
RW
RW
LIN USART - Serial Mode Register 2
70
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (9 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0000D5H
LIN USART - Serial Control Register 2
LIN USART - TX Register 2
SCR2
RW
0000D6H
0000D6H
0000D7H
0000D8H
0000D9H
0000DAH
TDR2
W
LIN USART - RX Register 2
RDR2
SSR2
R
LIN USART - Serial Status 2
RW
RW
RW
RW
LIN USART - Control/Com. Register 2
LIN USART - Ext. Status Register 2
ECCR2
ESCR2
BGRL2
LIN USART - Baud Rate Generator
Register 2 Low
BGR2
0000DBH
LIN USART - Baud Rate Generator
Register 2 High
BGRH2
RW
0000DEH
0000DFH
0000E0H
0000E0H
0000E1H
0000E2H
0000E3H
0000E4H
LIN USART - Serial Mode Register 3
LIN USART - Serial Control Register 3
LIN USART - TX Register 3
SMR3
SCR3
TDR3
RW
RW
W
LIN USART - RX Register 3
RDR3
SSR3
R
LIN USART - Serial Status 3
RW
RW
RW
RW
LIN USART - Control/Com. Register 3
LIN USART - Ext. Status Register 3
ECCR3
ESCR3
BGRL3
LIN USART - Baud Rate Generator
Register 3 Low
BGR3
0000E5H
LIN USART - Baud Rate Generator
Register 3 High
BGRH3
RW
0000F0H
000100H
000101H
000102H
000103H
000104H
external bus
EXTBUS0
BAPL0
RW
RW
RW
RW
RW
RW
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte
DMA - Buffer address pointer high byte
DMA - DMA control register
BAPM0
BAPH0
DMACS0
IOAL0
DMA - I/O register address pointer low
byte
IOA0
000105H
DMA - I/O register address pointer high
byte
IOAH0
RW
000106H
000107H
DMA - Data counter low byte
DMA - Data counter high byte
DCTL0
DCTH0
DCT0
RW
RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
71
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (10 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000108H
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte
DMA - Buffer address pointer high byte
DMA - DMA control register
BAPL1
BAPM1
BAPH1
DMACS1
IOAL1
RW
000109H
00010AH
00010BH
00010CH
RW
RW
RW
RW
DMA - I/O register address pointer low
byte
IOA1
00010DH
DMA - I/O register address pointer high
byte
IOAH1
RW
00010EH
00010FH
000110H
000111H
000112H
000113H
000114H
DMA - Data counter low byte
DCTL1
DCTH1
BAPL2
BAPM2
BAPH2
DMACS2
IOAL2
DCT1
RW
RW
RW
RW
RW
RW
RW
DMA - Data counter high byte
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte
DMA - Buffer address pointer high byte
DMA - DMA control register
DMA - I/O register address pointer low
byte
IOA2
000115H
DMA - I/O register address pointer high
byte
IOAH2
RW
000116H
000117H
000118H
000119H
00011AH
00011BH
00011CH
DMA - Data counter low byte
DCTL2
DCTH2
BAPL3
BAPM3
BAPH3
DMACS3
IOAL3
DCT2
RW
RW
RW
RW
RW
RW
RW
DMA - Data counter high byte
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte
DMA - Buffer address pointer high byte
DMA - DMA control register
DMA - I/O register address pointer low
byte
IOA3
00011DH
DMA - I/O register address pointer high
byte
IOAH3
RW
00011EH
00011FH
000120H
000121H
DMA - Data counter low byte
DCTL3
DCTH3
BAPL4
BAPM4
DCT3
RW
RW
RW
RW
DMA - Data counter high byte
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte
72
FME/EMDC- 2007-02-12
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Preliminary Specification
MB96300
Table 0-1 I/O map (11 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000122H
DMA - Buffer address pointer high byte
DMA - DMA control register
BAPH4
DMACS4
IOAL4
RW
000123H
000124H
RW
RW
DMA - I/O register address pointer low
byte
IOA4
000125H
DMA - I/O register address pointer high
byte
IOAH4
RW
000126H
000127H
000128H
000129H
00012AH
00012BH
00012CH
DMA - Data counter low byte
DCTL4
DCTH4
BAPL5
BAPM5
BAPH5
DMACS5
IOAL5
DCT4
RW
RW
RW
RW
RW
RW
RW
DMA - Data counter high byte
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte
DMA - Buffer address pointer high byte
DMA - DMA control register
DMA - I/O register address pointer low
byte
IOA5
00012DH
DMA - I/O register address pointer high
byte
IOAH5
RW
00012EH
00012FH
000130H
000131H
000132H
000133H
000134H
DMA - Data counter low byte
DCTL5
DCTH5
BAPL6
BAPM6
BAPH6
DMACS6
IOAL6
DCT5
RW
RW
RW
RW
RW
RW
RW
DMA - Data counter high byte
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte
DMA - Buffer address pointer high byte
DMA - DMA control register
DMA - I/O register address pointer low
byte
IOA6
000135H
DMA - I/O register address pointer high
byte
IOAH6
RW
000136H
000137H
000138H
000139H
00013AH
00013BH
DMA - Data counter low byte
DMA - Data counter high byte
Buffer address pointer low byte
Buffer address pointer middle byte
Buffer address pointer high byte
DMA control register
DCTL6
DCTH6
BAPL7
BAPM7
BAPH7
DMACS7
DCT6
RW
RW
RW
RW
RW
RW
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MB96300 Series
Preliminary Specification
Table 0-1 I/O map (12 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
00013CH
I/O register address pointer low byte
I/O register address pointer high byte
Data counter low byte
IOAL7
IOA7
RW
00013DH
00013EH
00013FH
000140H
000141H
000142H
000143H
000144H
IOAH7
DCTL7
DCTH7
BAPL8
BAPM8
BAPH8
DMACS8
IOAL8
RW
RW
RW
RW
RW
RW
RW
RW
DCT7
Data counter high byte
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte
DMA - Buffer address pointer high byte
DMA - DMA control register
DMA - I/O register address pointer low
byte
IOA8
000145H
DMA - I/O register address pointer high
byte
IOAH8
RW
000146H
000147H
000148H
000149H
00014AH
00014BH
00014CH
DMA - Data counter low byte
DCTL8
DCTH8
BAPL9
BAPM9
BAPH9
DMACS9
IOAL9
DCT8
RW
RW
RW
RW
RW
RW
RW
DMA - Data counter high byte
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte
DMA - Buffer address pointer high byte
DMA - DMA control register
DMA - I/O register address pointer low
byte
IOA9
00014DH
DMA - I/O register address pointer high
byte
IOAH9
RW
00014EH
00014FH
000150H
000151H
000152H
000153H
000154H
DMA - Data counter low byte
DCTL9
DCT9
RW
RW
RW
RW
RW
RW
RW
DMA - Data counter high byte
DCTH9
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte
DMA - Buffer address pointer high byte
DMA - DMA control register
BAPL10
BAPM10
BAPH10
DMACS10
IOAL10
DMA - I/O register address pointer low
byte
IOA10
000155H
DMA - I/O register address pointer high
byte
IOAH10
RW
74
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Preliminary Specification
MB96300
Table 0-1 I/O map (13 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000156H
DMA - Data counter low byte
DCTL10
DCTH10
BAPL11
BAPM11
BAPH11
DMACS11
IOAL11
DCT10
RW
000157H
000158H
000159H
00015AH
00015BH
00015CH
DMA - Data counter high byte
RW
RW
RW
RW
RW
RW
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte
DMA - Buffer address pointer high byte
DMA - DMA control register
DMA - I/O register address pointer low
byte
IOA11
00015DH
DMA - I/O register address pointer high
byte
IOAH11
RW
00015EH
00015FH
000160H
000161H
000162H
000163H
000164H
DMA - Data counter low byte
DCTL11
DCTH11
BAPL12
BAPM12
BAPH12
DMACS12
IOAL12
DCT11
RW
RW
RW
RW
RW
RW
RW
DMA - Data counter high byte
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte
DMA - Buffer address pointer high byte
DMA - DMA control register
DMA - I/O register address pointer low
byte
IOA12
000165H
DMA - I/O register address pointer high
byte
IOAH12
RW
000166H
000167H
000168H
000169H
00016AH
00016BH
00016CH
DMA - Data counter low byte
DCTL12
DCTH12
BAPL13
BAPM13
BAPH13
DMACS13
IOAL13
DCT12
RW
RW
RW
RW
RW
RW
RW
DMA - Data counter high byte
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte
DMA - Buffer address pointer high byte
DMA - DMA control register
DMA - I/O register address pointer low
byte
IOA13
00016DH
DMA - I/O register address pointer high
byte
IOAH13
RW
00016EH
00016FH
DMA - Data counter low byte
DMA - Data counter high byte
DCTL13
DCTH13
DCT13
RW
RW
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MB96300 Series
Preliminary Specification
Table 0-1 I/O map (14 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000170H
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte
DMA - Buffer address pointer high byte
DMA - DMA control register
BAPL14
BAPM14
BAPH14
DMACS14
IOAL14
RW
000171H
000172H
000173H
000174H
RW
RW
RW
RW
DMA - I/O register address pointer low
byte
IOA14
000175H
DMA - I/O register address pointer high
byte
IOAH14
RW
000176H
000177H
000178H
000179H
00017AH
00017BH
00017CH
DMA - Data counter low byte
DCTL14
DCTH14
BAPL15
BAPM15
BAPH15
DMACS15
IOAL15
DCT14
RW
RW
RW
RW
RW
RW
RW
DMA - Data counter high byte
DMA - Buffer address pointer low byte
DMA - Buffer address pointer middle byte
DMA - Buffer address pointer high byte
DMA - DMA control register
DMA - I/O register address pointer low
byte
IOA15
00017DH
DMA - I/O register address pointer high
byte
IOAH15
RW
00017EH
00017FH
000180H
DMA - Data counter low byte
DMA - Data counter high byte
DCTL15
DCT15
RW
RW
RW
DCTH15
GPR_RAM
CPU - General Purpose registers (RAM
access)
000380H
000381H
000382H
000383H
000384H
000385H
000386H
000387H
000388H
000389H
DMA - Interrupt select for DMA channel 0
DMA - Interrupt select for DMA channel 1
DMA - Interrupt select for DMA channel 2
DMA - Interrupt select for DMA channel 3
DMA - Interrupt select for DMA channel 4
DMA - Interrupt select for DMA channel 5
DMA - Interrupt select for DMA channel 6
DMA - Interrupt select for DMA channel 7
DMA - Interrupt select for DMA channel 8
DMA - Interrupt select for DMA channel 9
DISEL0
DISEL1
DISEL2
DISEL3
DISEL4
DISEL5
DISEL6
DISEL7
DISEL8
DISEL9
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
76
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Preliminary Specification
MB96300
Table 0-1 I/O map (15 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
00038AH
DMA - Interrupt select for DMA channel 10 DISEL10
DMA - Interrupt select for DMA channel 11 DISEL11
DMA - Interrupt select for DMA channel 12 DISEL12
DMA - Interrupt select for DMA channel 13 DISEL13
DMA - Interrupt select for DMA channel 14 DISEL14
DMA - Interrupt select for DMA channel 15 DISEL15
RW
00038BH
00038CH
00038DH
00038EH
00038FH
000390H
RW
RW
RW
RW
RW
RW
DMA status register for DMA channels 7 - DSRL
0
DSR
000391H
000392H
000393H
000394H
000395H
DMA status register for DMA channels 15 DSRH
- 8
RW
RW
RW
RW
RW
DMA stop status register for DMA
channels 7 - 0
DSSRL
DSSR
DER
DMA stop status register for DMA
channels 15 - 8
DSSRH
DMA enable register for DMA channels 7 - DERL
0
DMA enable register for DMA channels 15 DERH
- 8
0003A0H
0003A1H
0003A2H
0003A3H
0003A4H
0003A5H
0003AEH
0003AFH
0003B0H
Interrupt level register
ILR
ICR
RW
RW
RW
RW
RW
RW
RW
RW
RW
Interrupt Index register
IDX
Interrupt vector Table base register
Interrupt vector Table base register
Delayed Interrupt register
TBRL
TBRH
DIRR
NMI
TBR
Non maskable Interrupt register
ROM mirror control register
EDSU configuration register
ROMM
EDSU
Memory patch control/status register ch 0/
1
PFCS0
PFCS1
0003B1H
0003B2H
0003B3H
Memory patch control/status register ch 0/
1
RW
RW
RW
Memory patch control/status register ch 2/
3
Memory patch control/status register ch 2/
3
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MB96300 Series
Preliminary Specification
Table 0-1 I/O map (16 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0003B4H
Memory patch control/status register ch 4/
5
PFCS2
RW
0003B5H
0003B6H
0003B7H
0003B8H
0003B9H
0003BAH
0003BBH
0003BCH
0003BDH
0003BEH
0003BFH
0003C0H
0003C1H
0003C2H
0003C3H
0003C4H
0003C5H
Memory patch control/status register ch 4/
5
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Memory patch control/status register ch 6/
7
PFCS3
Memory patch control/status register ch 6/
7
Memory Patch function - Patch address 0
low
PFAL0
PFAM0
PFAH0
PFAL1
PFAM1
PFAH1
PFAL2
PFAM2
PFAH2
PFAL3
PFAM3
PFAH3
PFAL4
PFAM4
Memory Patch function - Patch address 0
middle
Memory Patch function - Patch address 0
high
Memory Patch function - Patch address 1
low
Memory Patch function - Patch address 1
middle
Memory Patch function - Patch address 1
high
Memory Patch function - Patch address 2
low
Memory Patch function - Patch address 2
middle
Memory Patch function - Patch address 2
high
Memory Patch function - Patch address 3
low
Memory Patch function - Patch address 3
middle
Memory Patch function - Patch address 3
high
Memory Patch function - Patch address 4
low
Memory Patch function - Patch address 4
middle
78
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Preliminary Specification
MB96300
Table 0-1 I/O map (17 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0003C6H
Memory Patch function - Patch address 4
high
PFAH4
PFAL5
PFAM5
PFAH5
PFAL6
PFAM6
PFAH6
PFAL7
PFAM7
PFAH7
RW
0003C7H
0003C8H
0003C9H
0003CAH
0003CBH
0003CCH
0003CDH
0003CEH
0003CFH
Memory Patch function - Patch address 5
low
RW
RW
RW
RW
RW
RW
RW
RW
RW
Memory Patch function - Patch address 5
middle
Memory Patch function - Patch address 5
high
Memory Patch function - Patch address 6
low
Memory Patch function - Patch address 6
middle
Memory Patch function - Patch address 6
high
Memory Patch function - Patch address 7
low
Memory Patch function - Patch address 7
middle
Memory Patch function - Patch address 7
high
0003D0H
0003D1H
0003D2H
0003D3H
0003D4H
0003D5H
0003D6H
0003D7H
0003D8H
0003D9H
0003DAH
0003DBH
0003DCH
0003DDH
Memory Patch function - Patch data 0
Memory Patch function - Patch data 0
Memory Patch function - Patch data 1
Memory Patch function - Patch data 1
Memory Patch function - Patch data 2
Memory Patch function - Patch data 2
Memory Patch function - Patch data 3
Memory Patch function - Patch data 3
Memory Patch function - Patch data 4
Memory Patch function - Patch data 4
Memory Patch function - Patch data 5
Memory Patch function - Patch data 5
Memory Patch function - Patch data 6
Memory Patch function - Patch data 6
PFDL0
PFDH0
PFDL1
PFDH1
PFDL2
PFDH2
PFDL3
PFDH3
PFDL4
PFDH4
PFDL5
PFDH5
PFDL6
PFDH6
PFD0
PFD1
PFD2
PFD3
PFD4
PFD5
PFD6
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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MB96300 Series
Preliminary Specification
Table 0-1 I/O map (18 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0003DEH
0003DFH
0003F1H
Memory Patch function - Patch data 7
Memory Patch function - Patch data 7
PFDL7
PFDH7
MFMCS
PFD7
RW
RW
RW
Flash Memory Configuration register
(Main Flash) + EVA
0003F2H
0003F6H
Flash Memory Timing Configuration
register 0 (Main Flash) + EVA
MFMTCL
SFMTCL
MFMTC
SFMTC
RW
RW
Flash Memory Timing Configuration
register 0 (Sat Flash) + EVA
000400H
000401H
000402H
000403H
000404H
000405H
000406H
000407H
000408H
000409H
00040AH
00040BH
Standby Mode control register
Clock select register
SMCR
RW
RW
RW
R
CKSR
Clock Stabilisation select register
Clock monitor register
CKSSR
CKMR
Clock Frequncy control register Low
Clock Frequncy control register High
PLL Control register Low
CKFCRL
CKFCRH
PLLCRL
PLLCRH
RCTCR
MCTCR
SCTCR
CKFCR
PLLCR
RW
RW
RW
RW
RW
RW
RW
R
PLL Control register High
RC clock timer control register
Main clock timer control register
Sub clock timer control register
Reset cause and clock status register with RCCSRC
clear function
00040CH
00040DH
00040EH
00040FH
000415H
000416H
000417H
000418H
00041AH
00041BH
Reset configuration register
RCR
RW
R
Reset cause and clock status register
Watch dog timer configuration register
Watch dog timer clear pattern register
Clock output activation register
RCCSR
WDTC
WDTCP
COAR
RW
W
RW
RW
RW
RW
RW
RW
Clock output configuration register 0
Clock output configuration register 1
Clock Modulator control register
COCR0
COCR1
CMCR
CMPRL
CMPRH
Clock Modulator Parameter register Low
Clock Modulator Parameter register High
CMPR
80
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Preliminary Specification
MB96300
Table 0-1 I/O map (19 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000430H
I/O Port - Data Direction Register Port 00
I/O Port - Data Direction Register Port 01
I/O Port - Data Direction Register Port 02
I/O Port - Data Direction Register Port 03
I/O Port - Data Direction Register Port 04
I/O Port - Data Direction Register Port 05
I/O Port - Data Direction Register Port 06
I/O Port - Data Direction Register Port 07
I/O Port - Data Direction Register Port 08
I/O Port - Data Direction Register Port 09
I/O Port - Data Direction Register Port 10
I/O Port - Data Direction Register Port 11
I/O Port - Data Direction Register Port 12
I/O Port - Data Direction Register Port 13
I/O Port - Data Direction Register Port 14
I/O Port - Data Direction Register Port 15
I/O Port - Data Direction Register Port 16
I/O Port - Data Direction Register Port 17
DDR00
DDR01
DDR02
DDR03
DDR04
DDR05
DDR06
DDR07
DDR08
DDR09
DDR10
DDR11
DDR12
DDR13
DDR14
DDR15
DDR16
DDR17
PIER00
RW
000431H
000432H
000433H
000434H
000435H
000436H
000437H
000438H
000439H
00043AH
00043BH
00043CH
00043DH
00043EH
00043FH
000440H
000441H
000444H
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
I/O Port - Port Input Enable Register I/O
Port - Port 00
000445H
000446H
000447H
000448H
000449H
00044AH
I/O Port - Port Input Enable Register I/O
Port - Port 01
PIER01
PIER02
PIER03
PIER04
PIER05
PIER06
RW
RW
RW
RW
RW
RW
I/O Port - Port Input Enable Register I/O
Port - Port 02
I/O Port - Port Input Enable Register I/O
Port - Port 03
I/O Port - Port Input Enable Register I/O
Port - Port 04
I/O Port - Port Input Enable Register I/O
Port - Port 05
I/O Port - Port Input Enable Register I/O
Port - Port 06
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MB96300 Series
Preliminary Specification
Table 0-1 I/O map (20 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
00044BH
I/O Port - Port Input Enable Register I/O
Port - Port 07
PIER07
PIER08
PIER09
PIER10
PIER11
PIER12
PIER13
PIER14
PIER15
PIER16
PIER17
PILR00
PILR01
PILR02
PILR03
PILR04
PILR05
PILR06
RW
00044CH
00044DH
00044EH
00044FH
000450H
000451H
000452H
000453H
000454H
000455H
000458H
000459H
00045AH
00045BH
00045CH
00045DH
00045EH
I/O Port - Port Input Enable Register I/O
Port - Port 08
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
I/O Port - Port Input Enable Register I/O
Port - Port 09
I/O Port - Port Input Enable Register I/O
Port - Port 10
I/O Port - Port Input Enable Register I/O
Port - Port 11
I/O Port - Port Input Enable Register I/O
Port - Port 12
I/O Port - Port Input Enable Register I/O
Port - Port 13
I/O Port - Port Input Enable Register I/O
Port - Port 14
I/O Port - Port Input Enable Register I/O
Port - Port 15
I/O Port - Port Input Enable Register I/O
Port - Port 16
I/O Port - Port Input Enable Register I/O
Port - Port 17
I/O Port - Port Input Level Register I/O
Port - Port 00
I/O Port - Port Input Level Register I/O
Port - Port 01
I/O Port - Port Input Level Register I/O
Port - Port 02
I/O Port - Port Input Level Register I/O
Port - Port 03
I/O Port - Port Input Level Register I/O
Port - Port 04
I/O Port - Port Input Level Register I/O
Port - Port 05
I/O Port - Port Input Level Register I/O
Port - Port 06
82
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Preliminary Specification
MB96300
Table 0-1 I/O map (21 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
00045FH
I/O Port - Port Input Level Register I/O
Port - Port 07
PILR07
PILR08
PILR09
PILR10
PILR11
PILR12
PILR13
PILR14
PILR15
PILR16
PILR17
EPILR00
EPILR01
EPILR02
EPILR03
EPILR04
EPILR05
EPILR06
RW
000460H
000461H
000462H
000463H
000464H
000465H
000466H
000467H
000468H
000469H
00046CH
00046DH
00046EH
00046FH
000470H
000471H
000472H
I/O Port - Port Input Level Register I/O
Port - Port 08
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
I/O Port - Port Input Level Register I/O
Port - Port 09
I/O Port - Port Input Level Register I/O
Port - Port 10
I/O Port - Port Input Level Register I/O
Port - Port 11
I/O Port - Port Input Level Register I/O
Port - Port 12
I/O Port - Port Input Level Register I/O
Port - Port 13
I/O Port - Port Input Level Register I/O
Port - Port 14
I/O Port - Port Input Level Register I/O
Port - Port 15
I/O Port - Port Input Level Register I/O
Port - Port 16
I/O Port - Port Input Level Register I/O
Port - Port 17
I/O Port - Extended Port Input Level
Register Port 00
I/O Port - Extended Port Input Level
Register Port 01
I/O Port - Extended Port Input Level
Register Port 02
I/O Port - Extended Port Input Level
Register Port 03
I/O Port - Extended Port Input Level
Register Port 04
I/O Port - Extended Port Input Level
Register Port 05
I/O Port - Extended Port Input Level
Register Port 06
FME/EMDC- 2007-02-12
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MB96300 Series
Preliminary Specification
Table 0-1 I/O map (22 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000473H
I/O Port - Extended Port Input Level
Register Port 07
EPILR07
EPILR08
EPILR09
EPILR10
EPILR11
EPILR12
EPILR13
EPILR14
EPILR15
EPILR16
EPILR17
PODR00
PODR01
PODR02
PODR03
PODR04
PODR05
PODR06
RW
000474H
000475H
000476H
000477H
000478H
000479H
00047AH
00047BH
00047CH
00047DH
000480H
000481H
000482H
000483H
000484H
000485H
000486H
I/O Port - Extended Port Input Level
Register Port 08
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
I/O Port - Extended Port Input Level
Register Port 09
I/O Port - Extended Port Input Level
Register Port 10
I/O Port - Extended Port Input Level
Register Port 11
I/O Port - Extended Port Input Level
Register Port 12
I/O Port - Extended Port Input Level
Register Port 13
I/O Port - Extended Port Input Level
Register Port 14
I/O Port - Extended Port Input Level
Register Port 15
I/O Port - Extended Port Input Level
Register Port 16
I/O Port - Extended Port Input Level
Register Port 17
I/O Port - Port Output Drive Register Port
00
I/O Port - Port Output Drive Register Port
01
I/O Port - Port Output Drive Register Port
02
I/O Port - Port Output Drive Register Port
03
I/O Port - Port Output Drive Register Port
04
I/O Port - Port Output Drive Register Port
05
I/O Port - Port Output Drive Register Port
06
84
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Preliminary Specification
MB96300
Table 0-1 I/O map (23 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000487H
I/O Port - Port Output Drive Register Port
07
PODR07
PODR08
PODR09
PODR10
PODR11
PODR12
PODR13
PODR14
PODR15
PODR16
PODR17
RW
000488H
000489H
00048AH
00048BH
00048CH
00048DH
00048EH
00048FH
000490H
000491H
I/O Port - Port Output Drive Register Port
08
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
I/O Port - Port Output Drive Register Port
09
I/O Port - Port Output Drive Register Port
10
I/O Port - Port Output Drive Register Port
11
I/O Port - Port Output Drive Register Port
12
I/O Port - Port Output Drive Register Port
13
I/O Port - Port Output Drive Register Port
14
I/O Port - Port Output Drive Register Port
15
I/O Port - Port Output Drive Register Port
16
I/O Port - Port Output Drive Register Port
17
00049CH
00049DH
00049EH
0004A8H
I/O Port - Port High Drive Register Port 08 PHDR08
I/O Port - Port High Drive Register Port 09 PHDR09
I/O Port - Port High Drive Register Port 10 PHDR10
RW
RW
RW
RW
I/O Port - Pull-Up resistor Control Register PUCR00
Port 00
0004A9H
0004AAH
0004ABH
0004ACH
I/O Port - Pull-Up resistor Control Register PUCR01
Port 01
RW
RW
RW
RW
I/O Port - Pull-Up resistor Control Register PUCR02
Port 02
I/O Port - Pull-Up resistor Control Register PUCR03
Port 03
I/O Port - Pull-Up resistor Control Register PUCR04
Port 04
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
85
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (24 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0004ADH
0004AEH
0004AFH
0004B0H
0004B1H
0004B2H
0004B3H
0004B4H
0004B5H
0004B6H
0004B7H
0004B8H
0004B9H
0004BCH
0004BDH
0004BEH
0004BFH
0004C0H
I/O Port - Pull-Up resistor Control Register PUCR05
Port 05
RW
I/O Port - Pull-Up resistor Control Register PUCR06
Port 06
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
I/O Port - Pull-Up resistor Control Register PUCR07
Port 07
I/O Port - Pull-Up resistor Control Register PUCR08
Port 08
I/O Port - Pull-Up resistor Control Register PUCR09
Port 09
I/O Port - Pull-Up resistor Control Register PUCR10
Port 10
I/O Port - Pull-Up resistor Control Register PUCR11
Port 11
I/O Port - Pull-Up resistor Control Register PUCR12
Port 12
I/O Port - Pull-Up resistor Control Register PUCR13
Port 13
I/O Port - Pull-Up resistor Control Register PUCR14
Port 14
I/O Port - Pull-Up resistor Control Register PUCR15
Port 15
I/O Port - Pull-Up resistor Control Register PUCR16
Port 16
I/O Port - Pull-Up resistor Control Register PUCR17
Port 17
I/O Port - External Pin State Register Port EPSR00
00
I/O Port - External Pin State Register Port EPSR01
01
R
I/O Port - External Pin State Register Port EPSR02
02
R
I/O Port - External Pin State Register Port EPSR03
03
R
I/O Port - External Pin State Register Port EPSR04
04
R
86
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (25 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0004C1H
I/O Port - External Pin State Register Port EPSR05
05
R
R
R
R
R
R
R
R
R
R
R
R
R
0004C2H
0004C3H
0004C4H
0004C5H
0004C6H
0004C7H
0004C8H
0004C9H
0004CAH
0004CBH
0004CCH
0004CDH
I/O Port - External Pin State Register Port EPSR06
06
I/O Port - External Pin State Register Port EPSR07
07
I/O Port - External Pin State Register Port EPSR08
08
I/O Port - External Pin State Register Port EPSR09
09
I/O Port - External Pin State Register Port EPSR10
10
I/O Port - External Pin State Register Port EPSR11
11
I/O Port - External Pin State Register Port EPSR12
12
I/O Port - External Pin State Register Port EPSR13
13
I/O Port - External Pin State Register Port EPSR14
14
I/O Port - External Pin State Register Port EPSR15
15
I/O Port - External Pin State Register Port EPSR16
16
I/O Port - External Pin State Register Port EPSR17
17
0004D0H
0004D1H
0004D2H
0004D3H
0004D4H
0004D6H
ADC analog input enable register 0
ADC analog input enable register 1
ADC analog input enable register 2
ADC analog input enable register 3
ADC analog input enable register 4
ADER0
ADER1
ADER2
ADER3
ADER4
PRRR0
RW
RW
RW
RW
RW
RW
Peripheral Resource Relocation Register
0
0004D7H
Peripheral Resource Relocation Register
1
PRRR1
RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
87
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (26 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0004D8H
Peripheral Resource Relocation Register
2
PRRR2
PRRR3
PRRR4
PRRR5
PRRR6
PRRR7
PRRR8
PRRR9
RW
0004D9H
0004DAH
0004DBH
0004DCH
0004DDH
0004DEH
0004DFH
Peripheral Resource Relocation Register
3
RW
RW
RW
RW
RW
RW
RW
Peripheral Resource Relocation Register
4
Peripheral Resource Relocation Register
5
Peripheral Resource Relocation Register
6
Peripheral Resource Relocation Register
7
Peripheral Resource Relocation Register
8
Peripheral Resource Relocation Register
9
0004E0H
0004E1H
0004E2H
0004E3H
0004E4H
0004E5H
0004E6H
0004E7H
0004E8H
0004E9H
0004EAH
0004ECH
0004EDH
0004EEH
0004EFH
0004F0H
0004F1H
RTC - Sub Second Register L
RTC - Sub Second Register M
RTC - Sub-Second Register H
RTC - Second Register
WTBRL0
WTBRH0
WTBR1
WTSR
WTBR0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
RTC - Minutes
WTMR
RTC - Hour
WTHR
RTC - Timer Control Extended Register
RTC - Clock select register
WTCER
WTCKSR
WTCRL
WTCRH
CUCR
RTC - Timer Control Register L
RTC - Timer Control Register H
CAL - Calibration unit Control register
CAL - Sub/RC-clock timer data register L
CAL - Sub/RC-clock timer data register H
CAL - Main clock timer data register 2 L
CAL - Main clock timer data register 2 H
CAL - Main clock timer data register 1 L
CAL - Main clock timer data register 1 H
CUTDL
CUTDH
CUTR2L
CUTR2H
CUTR1L
CUTR1H
CUTD
CUTR2
CUTR1
R
R
R
88
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (27 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0004F2H
RLT - Timer Control Status Register 4 Low TMCSRL4
TMCSR4
RW
0004F3H
RLT - Timer Control Status Register 4
High
TMCSRH4
RW
0004F4H
0004F4H
0004F5H
0004F5H
0004F6H
0004F7H
RLT - Reload Register 4 - for writing
RLT - Reload Register 4 - for reading
RLT - Reload Register 4 - for writing
RLT - Reload Register 4 - for reading
TMRLR4
TMR4
W
R
W
R
RLT - Timer Control Status Register 5 Low TMCSRL5
TMCSR5
RW
RW
RLT - Timer Control Status Register 5
High
TMCSRH5
0004F8H
0004F8H
0004F9H
0004F9H
0004FAH
000500H
000501H
000502H
RLT - Reload Register 5 - for writing
RLT - Reload Register 5 - for reading
RLT - Reload Register 5 - for writing
RLT - Reload Register 5 - for reading
RLT - Timer input select (for Cascading)
FRT - Data register of free-running timer 2
FRT - Data register of free-running timer 2
TMRLR5
TMR5
W
R
W
R
TMISR
RW
RW
RW
RW
TCDT2
TCCS2
FRT - Control status register of free-
running timer 2
TCCSL2
TCCSH2
000503H
FRT - Control status register of free-
running timer 2
RW
000504H
000505H
000506H
FRT - Data register of free-running timer 3
FRT - Data register of free-running timer 3
TCDT3
TCCS3
RW
RW
RW
FRT - Control status register of free-
running timer 3
TCCSL3
TCCSH3
000507H
FRT - Control status register of free-
running timer 3
RW
000508H
000509H
00050AH
00050BH
00050CH
OCU - Output Compare Control Status 8
OCU - Output Compare Control Status 9
OCU - Compare Register 8
OCS8
OCS9
RW
RW
RW
RW
RW
OCCP8
OCCP9
OCU - Compare Register 8
OCU - Compare Register 9
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
89
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (28 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
00050DH
OCU - Compare Register 9
RW
00050EH
00050FH
000510H
000511H
000512H
000513H
000514H
000515H
000516H
000517H
000518H
000519H
00051AH
00051BH
00051CH
00051DH
00051EH
00051FH
000520H
000521H
000522H
000522H
000523H
000524H
000525H
000526H
OCU - Output Compare Control Status 10 OCS10
OCU - Output Compare Control Status 11 OCS11
OCU - Compare Register 10
RW
RW
RW
RW
RW
RW
RW
RW
R
OCCP10
OCCP11
OCU - Compare Register 10
OCU - Compare Register 11
OCU - Compare Register 11
ICU - Control Status Register 8/9
ICU - Edge register 8/9
ICS89
ICE89
ICU - Capture Register 8
IPCPL8
IPCPH8
IPCPL9
IPCPH9
ICS1011
ICE1011
IPCPL10
IPCPH10
IPCPL11
IPCPH11
SMR4
IPCP8
IPCP9
ICU - Capture Register 8
R
ICU - Capture Register 9
R
ICU - Capture Register 9
R
ICU - Control Status Register 10/11
ICU - Edge register 10/11
RW
RW
R
ICU - Capture Register 10
IPCP10
IPCP11
ICU - Capture Register 10
R
ICU - Capture Register 11
R
ICU - Capture Register 11
R
LIN USART - Serial Mode Register 4
LIN USART - Serial Control Register 4
LIN USART - TX Register 4
LIN USART - RX Register 4
LIN USART - Serial Status 4
LIN USART - Control/Com. Register 4
LIN USART - Ext. Status Register 4
RW
RW
W
SCR4
TDR4
RDR4
R
SSR4
RW
RW
RW
RW
ECCR4
ESCR4
BGRL4
LIN USART - Baud Rate Generator
Register 4 Low
BGR4
000527H
LIN USART - Baud Rate Generator
Register 4 High
BGRH4
RW
90
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (29 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
00052AH
LIN USART - Serial Mode Register 5
LIN USART - Serial Control Register 5
LIN USART - RX Register 5
SMR5
SCR5
TDR5
RW
00052BH
00052CH
00052CH
00052DH
00052EH
00052FH
000530H
RW
W
LIN USART - TX Register 5
RDR5
SSR5
R
LIN USART - Serial Status 5
RW
RW
RW
RW
LIN USART - Control/Com. Register 5
LIN USART - Ext. Status Register 5
ECCR5
ESCR5
BGRL5
LIN USART - Baud Rate Generator
Register 5 Low
BGR5
000531H
LIN USART - Baud Rate Generator
Register 5 High
BGRH5
RW
000534H
000535H
000536H
000536H
000537H
000538H
000539H
00053AH
LIN USART - Serial Mode Register 6
LIN USART - Serial Control Register 6
LIN USART - Serial TX Register 6
LIN USART - Serial RX Register 6
LIN USART - Serial Status Register 6
SMR6
SCR6
TDR6
RDR6
SSR6
RW
RW
W
R
RW
RW
RW
RW
LIN USART - Ext. Control/Com. Register 6 ECCR6
LIN USART - Ext. Status Com. Register 6 ESCR6
LIN USART - Baud Rate Generator
Register 6
BGRL6
BGR6
00053BH
LIN USART - Baud Rate Generator
Register 6
BGRH6
RW
00053EH
00053FH
000540H
000540H
000541H
000542H
000543H
000544H
LIN USART - Serial Mode Register 7
LIN USART - Serial Control Register 7
LIN USART - Serial TX Register 7
LIN USART - Serial RX Register 7
LIN USART - Serial Status Register 7
SMR7
SCR7
TDR7
RDR7
SSR7
RW
RW
W
R
RW
RW
RW
RW
LIN USART - Ext. Control/Com. Register 7 ECCR7
LIN USART - Ext. Status Com. Register 7 ESCR7
LIN USART - Baud Rate Generator
Register 7
BGRL7
BGR7
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
91
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (30 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000545H
LIN USART - Baud Rate Generator
Register 7
BGRH7
RW
000548H
000549H
00054AH
00054AH
00054BH
00054CH
00054DH
00054EH
LIN USART - Serial Mode Register 8
LIN USART - Serial Control Register 8
LIN USART - Serial TX Register 8
LIN USART - Serial RX Register 8
LIN USART - Serial Status Register 8
SMR8
SCR8
TDR8
RDR8
SSR8
RW
RW
W
R
RW
RW
RW
RW
LIN USART - Ext. Control/Com. Register 8 ECCR8
LIN USART - Ext. Status Com. Register 8 ESCR8
LIN USART - Baud Rate Generator
Register 8
BGRL8
BGR8
00054FH
LIN USART - Baud Rate Generator
Register 8
BGRH8
RW
000552H
000553H
000554H
000554H
000555H
000556H
000557H
000558H
LIN USART - Serial Mode Register 9
LIN USART - Serial Control Register 9
LIN USART - Serial TX Register 9
LIN USART - Serial RX Register 9
LIN USART - Serial Status Register 9
SMR9
SCR9
TDR9
RDR9
SSR9
RW
RW
W
R
RW
RW
RW
RW
LIN USART - Ext. Control/Com. Register 9 ECCR9
LIN USART - Ext. Status Com. Register 9 ESCR9
LIN USART - Baud Rate Generator
Register 9
BGRL9
BGR9
000559H
LIN USART - Baud Rate Generator
Register 9
BGRH9
RW
000560H
000561H
000562H
000563H
000564H
000565H
000566H
000567H
Alarm Comparator 0
ACSR0
RW
RW
RW
RW
R
Alarm Comparator 0
AECSR0
ACSR1
Alarm Comparator 1
Alarm Comparator 1
AECSR1
PPG - Timer register 6
PPG - Timer register 6
PPG - Period setting register 6
PPG - Period setting register 6
PTMR6
PCSR6
R
W
W
92
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (31 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000568H
PPG - Duty cycle register 6
PPG - Duty cycle register 6
PPG - Control status register 6
PPG - Control status register 6
PPG - Timer register 7
PDUT6
W
W
000569H
00056AH
00056BH
00056CH
00056DH
00056EH
00056FH
000570H
000571H
000572H
000573H
000574H
PCNL6
PCNH6
PCN6
RW
RW
R
PTMR7
PCSR7
PDUT7
PCN7
PPG - Timer register 7
R
PPG - Period setting register 7
PPG - Period setting register 7
PPG - Duty cycle register 7
PPG - Duty cycle register 7
PPG - Control status register 7
PPG - Control status register 7
W
W
W
W
PCNL7
PCNH7
RW
RW
RW
PPG - General Control register 1 PPG 11- GCN1L2
8 Low
GCN12
000575H
000576H
000577H
PPG - General Control register 1 PPG 11- GCN1H2
8 High
RW
RW
RW
PPG - General Control register 2 PPG 11- GCN2L2
8 Low
GCN22
PPG - General Control register 2 PPG 11- GCN2H2
8 High
000578H
000579H
00057AH
00057BH
00057CH
00057DH
00057EH
00057FH
000580H
000581H
000582H
PPG - Timer register 8
PTMR8
PCSR8
PDUT8
PCN8
R
PPG - Timer register 8
R
PPG - Period setting register 8
PPG - Period setting register 8
PPG - Duty cycle register 8
PPG - Duty cycle register 8
W
W
W
W
RW
RW
R
PPG - Control status register 8
PPG - Control status register 8
PPG - Timer register 9
PCNL8
PCNH8
PTMR9
PCSR9
PPG - Timer register 9
R
PPG - Period setting register 9
W
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
93
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (32 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000583H
PPG - Period setting register 9
PPG - Duty cycle register 9
PPG - Duty cycle register 9
PPG - Control status register 9
PPG - Control status register 9
PPG - Timer register 10
W
W
W
000584H
000585H
000586H
000587H
000588H
000589H
00058AH
00058BH
00058CH
00058DH
00058EH
00058FH
000590H
000591H
000592H
000593H
000594H
000595H
000596H
000597H
000598H
PDUT9
PCN9
PCNL9
PCNH9
RW
RW
R
PTMR10
PCSR10
PDUT10
PCN10
PPG - Timer register 10
R
PPG - Period setting register 10
PPG - Period setting register 10
PPG - Duty cycle register 10
PPG - Duty cycle register 10
PPG - Control status register 10
PPG - Control status register 10
PPG - Timer register 11
W
W
W
W
PCNL10
PCNH10
RW
RW
R
PTMR11
PCSR11
PDUT11
PCN11
PPG - Timer register 11
R
PPG - Period setting register 11
PPG - Period setting register 11
PPG - Duty cycle register 11
PPG - Duty cycle register 11
PPG - Control status register 11
PPG - Control status register 11
W
W
W
W
PCNL11
PCNH11
GCN1L3
RW
RW
RW
PPG - General Control rgister 1 PPG 15-
12 Low
GCN13
000599H
00059AH
00059BH
PPG - General Control rgister 1 PPG 15-
12 High
GCN1H3
GCN2L3
GCN2H3
RW
RW
RW
PPG - General Control rgister 2 PPG 15-
12 Low
GCN23
PPG - General Control rgister 2 PPG 15-
12 High
00059CH
00059DH
PPG - Timer register 12
PPG - Timer register 12
PTMR12
R
R
94
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (33 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
00059EH
PPG - Period setting register 12
PPG - Period setting register 12
PPG - Duty cycle register 12
PPG - Duty cycle register 12
PPG - Control status register 12
PPG - Control status register 12
PPG - Timer register 13
PCSR12
W
W
W
W
00059FH
0005A0H
0005A1H
0005A2H
0005A3H
0005A4H
0005A5H
0005A6H
0005A7H
0005A8H
0005A9H
0005AAH
0005ABH
0005ACH
0005ADH
0005AEH
0005AFH
0005B0H
0005B1H
0005B2H
0005B3H
0005B4H
0005B5H
0005B6H
0005B7H
0005B8H
0005B9H
0005BAH
0005BBH
PDUT12
PCN12
PCNL12
PCNH12
RW
RW
R
PTMR13
PCSR13
PDUT13
PCN13
PPG - Timer register 13
R
PPG - Period setting register 13
PPG - Period setting register 13
PPG - Duty cycle register 13
PPG - Duty cycle register 13
PPG - Control status register 13
PPG - Control status register 13
PPG - Timer register 14
W
W
W
W
PCNL13
PCNH13
RW
RW
R
PTMR14
PCSR14
PDUT14
PCN14
PPG - Timer register 14
R
PPG - Period setting register 14
PPG - Period setting register 14
PPG - Duty cycle register 14
PPG - Duty cycle register 14
PPG - Control status register 14
PPG - Control status register 14
PPG - Timer register 15
W
W
W
W
PCNL14
PCNH14
RW
RW
R
PTMR15
PCSR15
PDUT15
PCN15
PPG - Timer register 15
R
PPG - Period setting register 15
PPG - Period setting register 15
PPG - Duty cycle register 15
PPG - Duty cycle register 15
PPG - Control status register 15
PPG - Control status register 15
W
W
W
W
PCNL15
PCNH15
RW
RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
95
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (34 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0005BCH
0005BDH
0005BEH
0005BFH
PPG - General Control rgister 1 PPG 19-
16 Low
GCN1L4
GCN1H4
GCN2L4
GCN2H4
GCN14
RW
PPG - General Control rgister 1 PPG 19-
16 High
RW
RW
RW
PPG - General Control rgister 2 PPG 19-
16 Low
GCN24
PPG - General Control rgister 2 PPG 19-
16 High
0005C0H
0005C1H
0005C2H
0005C3H
0005C4H
0005C5H
0005C6H
0005C7H
0005C8H
0005C9H
0005CAH
0005CBH
0005CCH
0005CDH
0005CEH
0005CFH
0005D0H
0005D1H
0005D2H
0005D3H
0005D4H
0005D5H
0005D6H
PPG - Timer register 16
PTMR16
PCSR16
PDUT16
PCN16
R
PPG - Timer register 16
R
PPG - Period setting register 16
PPG - Period setting register 16
PPG - Duty cycle register 16
PPG - Duty cycle register 16
PPG - Control status register 16
PPG - Control status register 16
PPG - Timer register 17
W
W
W
W
RW
RW
R
PCNL16
PCNH16
PTMR17
PCSR17
PDUT17
PCN17
PPG - Timer register 17
R
PPG - Period setting register 17
PPG - Period setting register 17
PPG - Duty cycle register 17
PPG - Duty cycle register 17
PPG - Control status register 17
PPG - Control status register 17
PPG - Timer register 18
W
W
W
W
RW
RW
R
PCNL17
PCNH17
PTMR18
PCSR18
PDUT18
PCN18
PPG - Timer register 18
R
PPG - Period setting register 18
PPG - Period setting register 18
PPG - Duty cycle register 18
PPG - Duty cycle register 18
PPG - Control status register 18
W
W
W
W
RW
PCNL18
96
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (35 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0005D7H
PPG - Control status register 18
PPG - Timer register 19
PCNH18
RW
0005D8H
0005D9H
0005DAH
0005DBH
0005DCH
0005DDH
0005DEH
0005DFH
0005E0H
0005E1H
PTMR19
PCSR19
PDUT19
PCN19
R
PPG - Timer register 19
R
PPG - Period setting register 19
PPG - Period setting register 19
PPG - Duty cycle register 19
PPG - Duty cycle register 19
PPG - Control status register 19
PPG - Control status register 19
SMC 0 - PWM control register
W
W
W
W
PCNL19
PCNH19
PWC0
RW
RW
RW
RW
SMC 0 - extended control register (Output PWEC0
enable)
0005E2H
0005E3H
0005E4H
0005E5H
0005E6H
0005E7H
0005EAH
0005EBH
SMC 0 - PWM control register PWM 1
SMC 0 - PWM control register PWM 1
SMC 0 - PWM control register PWM 2
SMC 0 - PWM control register PWM 2
PWC10
PWC20
RW
RW
RW
RW
RW
RW
RW
RW
SMC 0 - PWM Select register
SMC 0 - PWM Select register
SMC 1 - PWM control register
PWS10
PWS20
PWC1
SMC 1 - extended control register (Output PWEC1
enable)
0005ECH
0005EDH
0005EEH
0005EFH
0005F0H
0005F1H
0005F4H
0005F5H
SMC 1 - PWM control register PWM 1
SMC 1 - PWM control register PWM 1
SMC 1 - PWM control register PWM 2
SMC 1 - PWM control register PWM 2
PWC11
PWC21
RW
RW
RW
RW
RW
RW
RW
RW
SMC 1 - PWM Select register
SMC 1 - PWM Select register
SMC 2 - PWM control register
PWS11
PWS21
PWC2
SMC 2 - extended control register (Output PWEC2
enable)
0005F6H
SMC 2 - PWM control register PWM 1
PWC12
RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
97
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (36 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0005F7H
SMC 2 - PWM control register PWM 1
SMC 2 - PWM control register PWM 2
SMC 2 - PWM control register PWM 2
SMC 2 - PWM Select register
RW
0005F8H
0005F9H
0005FAH
0005FBH
0005FEH
0005FFH
PWC22
RW
RW
RW
RW
RW
RW
PWS12
PWS22
PWC3
SMC 2 - PWM Select register
SMC 3 - PWM control register
SMC 3 - extended control register (Output PWEC3
enable)
000600H
000601H
000602H
000603H
000604H
000605H
000608H
000609H
SMC 3 - PWM control register PWM 1
SMC 3 - PWM control register PWM 1
SMC 3 - PWM control register PWM 2
SMC 3 - PWM control register PWM 2
PWC13
PWC23
RW
RW
RW
RW
RW
RW
RW
RW
SMC 3 - PWM Select register
SMC 3 - PWM Select register
SMC 4 - PWM control register
PWS13
PWS23
PWC4
SMC 4 - extended control register (Output PWEC4
enable)
00060AH
00060BH
00060CH
00060DH
00060EH
00060FH
000612H
000613H
SMC 4 - PWM control register PWM 1
SMC 4 - PWM control register PWM 1
SMC 4 - PWM control register PWM 2
SMC 4 - PWM control register PWM 2
PWC14
PWC24
RW
RW
RW
RW
RW
RW
RW
RW
SMC 4 - PWM Select register
SMC 4 - PWM Select register
SMC 5 - PWM control register
PWS14
PWS24
PWC5
SMC 5 - extended control register (Output PWEC5
enable)
000614H
000615H
000616H
000617H
000618H
SMC 5 - PWM control register PWM 1
SMC 5 - PWM control register PWM 1
SMC 5 - PWM control register PWM 2
SMC 5 - PWM control register PWM 2
PWC15
PWC25
RW
RW
RW
RW
RW
SMC 5 - PWM Select register
PWS15
98
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (37 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000619H
SMC 5 - PWM Select register
PWS25
RW
00061CH
00061DH
LCD - Output Enable Register 0 (Seg 7-0) LCDER0
RW
RW
LCD - Output Enable Register 1 (Seq 15-
8)
LCDER1
LCDER2
LCDER3
LCDER4
LCDER5
LCDER6
LCDER7
LCDER8
00061EH
00061FH
000620H
000621H
000622H
000623H
000624H
LCD - Output Enable Register 2 (Seq 23-
16)
RW
RW
RW
RW
RW
RW
RW
LCD - Output Enable Register 3 (Seq 31-
24)
LCD - Output Enable Register 4 (Seq 39-
32)
LCD - Output Enable Register 5 (Seq 47-
40)
LCD - Output Enable Register 6 (Seq 55-
48)
LCD - Output Enable Register 7 (Seq 63-
56)
LCD - Output Enable Register 8 (Seq 71-
64)
000626H
000627H
000628H
000629H
00062AH
00062BH
00062CH
00062DH
00062EH
00062FH
000630H
000631H
000632H
000633H
000634H
LCD - Output Enable Register 10 (Vx)
LCD - Extended Control Register
LCD - Common pin switching register
LCD - Control Register
LCDVER
LECR
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
LCDCMR
LCR
LCD - Data register for Segment 0-1
LCD - Data register for Segment 3-2
LCD - Data register for Segment 5-4
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment 11-10
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment 21-20
VRAM0
VRAM1
VRAM2
VRAM3
VRAM4
VRAM5
VRAM6
VRAM7
VRAM8
VRAM9
VRAM10
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
99
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (38 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000635H
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment 31-30
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment 41-40
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment 51-50
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment 61-60
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment
LCD - Data register for Segment 71-70
VRAM11
VRAM12
VRAM13
VRAM14
VRAM15
VRAM16
VRAM17
VRAM18
VRAM19
VRAM20
VRAM21
VRAM22
VRAM23
VRAM24
VRAM25
VRAM26
VRAM27
VRAM28
VRAM29
VRAM30
VRAM31
VRAM32
VRAM33
VRAM34
VRAM35
RW
000636H
000637H
000638H
000639H
00063AH
00063BH
00063CH
00063DH
00063EH
00063FH
000640H
000641H
000642H
000643H
000644H
000645H
000646H
000647H
000648H
000649H
00064AH
00064BH
00064CH
00064DH
0006E0H
0006E1H
0006E2H
0006E3H
0006E4H
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
External bus Area configuration register 0 EACL0
External bus Area configuration register 0 EACH0
External bus Area configuration register 1 EACL1
External bus Area configuration register 1 EACH1
External bus Area configuration register 2 EACL2
EAC0
EAC1
EAC2
100
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (39 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0006E5H
External bus Area configuration register 2 EACH2
External bus Area configuration register 3 EACL3
External bus Area configuration register 3 EACH3
External bus Area configuration register 4 EACL4
External bus Area configuration register 4 EACH4
External bus Area configuration register 5 EACL5
External bus Area configuration register 5 EACH5
RW
0006E6H
0006E7H
0006E8H
0006E9H
0006EAH
0006EBH
0006ECH
0006EDH
0006EEH
0006EFH
0006F0H
0006F1H
0006F2H
EAC3
EAC4
EAC5
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
External bus Area select register 2
External bus Area select register 3
External bus Area select register 4
External bus Area select register 5
External bus Mode register
EAS2
EAS3
EAS4
EAS5
EBM
External bus Clock and Function register
EBCF
EBAE0
External bus Address output enable
register 0
0006F3H
0006F4H
External bus Address output enable
register 1
EBAE1
EBAE2
RW
RW
External bus Address output enable
register 2
0006F5H
000700H
000701H
000702H
000703H
000704H
000705H
000706H
000707H
000708H
000709H
00070AH
External bus Control signal register
CAN 0 - Control register
EBCS
RW
RW
R
CTRLRL0
CTRLRH0
STATRL0
STATRH0
ERRCNTL0
ERRCNTH0
BTRL0
CTRLR0
STATR0
ERRCNT0
BTR0
CAN 0 - Control register (reserved)
CAN 0 - Status register
RW
R
CAN 0 - Status register (reserved)
CAN 0 - Error Counter (Transmit)
CAN 0 - Error Counter (Receive)
CAN 0 - Bit Timing Register
CAN 0 - Bit Timing Register
CAN 0 - Interrupt Register
R
R
RW
RW
R
BTRH0
INTRL0
INTR0
CAN 0 - Interrupt Register
INTRH0
R
CAN 0 - Test Register
TESTRL0
TESTR0
RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 101
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (40 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
00070BH
CAN 0 - Test Register (reserved)
CAN 0 - BRP Extension register
TESTRH0
BRPERL0
BRPERH0
R
00070CH
00070DH
BRPER0
RW
R
CAN 0 - BRP Extension register
(reserved)
000710H
000711H
000712H
000713H
CAN 0 - IF1 Command request register
CAN 0 - IF1 Command request register
CAN 0 - IF1 Command Mask register
IF1CREQL0
IF1CREQH0
IF1CMSKL0
IF1CMSKH0
IF1CREQ0
IF1CMSK0
RW
RW
RW
R
CAN 0 - IF1 Command Mask register
(reserved)
000714H
000715H
000716H
000717H
000718H
000719H
00071AH
00071BH
00071CH
00071DH
00071EH
00071FH
000720H
000721H
000722H
000723H
000724H
000725H
000740H
000741H
000742H
CAN 0 - IF1 Mask Register
CAN 0 - IF1 Mask Register
CAN 0 - IF1 Mask Register
CAN 0 - IF1 Mask Register
CAN 0 - IF1 Arbitration register
CAN 0 - IF1 Arbitration register
CAN 0 - IF1 Arbitration register
CAN 0 - IF1 Arbitration register
CAN 0 - IF1 Message Control Register
CAN 0 - IF1 Message Control Register
CAN 0 - IF1 Data A1
IF1MSK1L0
IF1MSK1H0
IF1MSK2L0
IF1MSK2H0
IF1ARB1L0
IF1ARB1H0
IF1ARB2L0
IF1ARB2H0
IF1MCTRL0
IF1MCTRH0
IF1DTA1L0
IF1DTA1H0
IF1DTA2L0
IF1DTA2H0
IF1DTB1L0
IF1DTB1H0
IF1DTB2L0
IF1DTB2H0
IF2CREQL0
IF2CREQH0
IF2CMSKL0
IF1MSK10
IF1MSK20
IF1ARB10
IF1ARB20
IF1MCTR0
IF1DTA10
IF1DTA20
IF1DTB10
IF1DTB20
IF2CREQ0
IF2CMSK0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
CAN 0 - IF1 Data A1
CAN 0 - IF1 Data A2
CAN 0 - IF1 Data A2
CAN 0 - IF1 Data B1
CAN 0 - IF1 Data B1
CAN 0 - IF1 Data B2
CAN 0 - IF1 Data B2
CAN 0 - IF2 Command request register
CAN 0 - IF2 Command request register
CAN 0 - IF2 Command Mask register
102
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (41 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000743H
CAN 0 - IF2 Command Mask register
(reserved
IF2CMSKH0
R
000744H
000745H
000746H
000747H
000748H
000749H
00074AH
00074BH
00074CH
00074DH
00074EH
00074FH
000750H
000751H
000752H
000753H
000754H
000755H
000780H
000781H
000782H
000783H
000790H
000791H
000792H
000793H
0007A0H
0007A1H
CAN 0 - IF2 Mask Register
CAN 0 - IF2 Mask Register
CAN 0 - IF2 Mask Register
CAN 0 - IF2 Mask Register
CAN 0 - IF2 Arbitration register
CAN 0 - IF2 Arbitration register
CAN 0 - IF2 Arbitration register
CAN 0 - IF2 Arbitration register
CAN 0 - IF2 Message Control Register
CAN 0 - IF2 Message Control Register
CAN 0 - IF2 Data A1
IF2MSK1L0
IF2MSK1H0
IF2MSK2L0
IF2MSK2H0
IF2ARB1L0
IF2ARB1H0
IF2ARB2L0
IF2ARB2H0
IF2MCTRL0
IF2MCTRH0
IF2DTA1L0
IF2DTA1H0
IF2DTA2L0
IF2DTA2H0
IF2DTB1L0
IF2DTB1H0
IF2DTB2L0
IF2DTB2H0
TREQR1L0
TREQR1H0
TREQR2L0
TREQR2H0
NEWDT1L0
NEWDT1H0
NEWDT2L0
NEWDT2H0
INTPND1L0
INTPND1H0
IF2MSK10
IF2MSK20
IF2ARB10
IF2ARB20
IF2MCTR0
IF2DTA10
IF2DTA20
IF2DTB10
IF2DTB20
TREQR10
TREQR20
NEWDT10
NEWDT20
INTPND10
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
CAN 0 - IF2 Data A1
CAN 0 - IF2 Data A2
CAN 0 - IF2 Data A2
CAN 0 - IF2 Data B1
CAN 0 - IF2 Data B1
CAN 0 - IF2 Data B2
CAN 0 - IF2 Data B2
CAN 0 - Transmission Request Register
CAN 0 - Transmission Request Register
CAN 0 - Transmission Request Register
CAN 0 - Transmission Request Register
CAN 0 - New Data Register
CAN 0 - New Data Register
CAN 0 - New Data Register
CAN 0 - New Data Register
CAN 0 - Interrupt Pending Register
CAN 0 - Interrupt Pending Register
R
R
R
R
R
R
R
R
R
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 103
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (42 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0007A2H
CAN 0 - Interrupt Pending Register
CAN 0 - Interrupt Pending Register
CAN 0 - Message Valid Register
CAN 0 - Message Valid Register
CAN 0 - Message Valid Register
CAN 0 - Message Valid Register
CAN 0 - Output enable register
INTPND2L0
INTPND2H0
MSGVAL1L0
MSGVAL1H0
MSGVAL2L0
MSGVAL2H0
COER0
INTPND20
MSGVAL10
MSGVAL20
R
R
R
R
R
R
0007A3H
0007B0H
0007B1H
0007B2H
0007B3H
0007CEH
0007D0H
0007D1H
RW
RW
RW
Sound Generator 0 - Control Register Low SGCRL0
SGCR0
Sound Generator 0 - Control Register
High
SGCRH0
0007D2H
0007D3H
0007D4H
0007D5H
0007D6H
0007D7H
Sound Generator 0 - Frequency Register
Sound Generator 0 - Amplitude Register
Sound Generator 0 - Decrement Register
Sound Generator 0 - Tone Register
SGFR0
SGAR0
SGDR0
SGTR0
RW
RW
RW
RW
RW
RW
Sound Generator 1 - Control Register Low SGCRL1
SGCR1
Sound Generator 1 - Control Register
High
SGCRH1
0007D8H
0007D9H
0007DAH
0007DBH
000800H
000801H
000802H
000803H
000804H
000805H
000806H
000807H
000808H
Sound Generator 1 - Frequency Register
Sound Generator 1 - Amplitude Register
Sound Generator 1 - Decrement Register
Sound Generator 1 - Tone Register
CAN 1 - Control register
SGFR1
RW
RW
RW
RW
RW
R
SGAR1
SGDR1
SGTR1
CTRLRL1
CTRLRH1
STATRL1
STATRH1
ERRCNTL1
ERRCNTH1
BTRL1
CTRLR1
STATR1
ERRCNT1
BTR1
CAN 1 - Control register (reserved)
CAN 1 - Status register
RW
R
CAN 1 - Status register (reserved)
CAN 1 - Error Counter (Transmit)
CAN 1 - Error Counter (Receive)
CAN 1 - Bit Timing Register
R
R
RW
RW
R
CAN 1 - Bit Timing Register
BTRH1
CAN 1 - Interrupt Register
INTRL1
INTR1
104
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (43 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000809H
CAN 1 - Interrupt Register
CAN 1 - Test Register
INTRH1
R
00080AH
00080BH
00080CH
00080DH
TESTRL1
TESTRH1
BRPERL1
BRPERH1
TESTR1
BRPER1
RW
R
CAN 1 - Test Register (reserved)
CAN 1 - BRP Extension register
RW
R
CAN 1 - BRP Extension register
(reserved)
000810H
000811H
000812H
000813H
CAN 1 - IF1 Command request register
CAN 1 - IF1 Command request register
CAN 1 - IF1 Command Mask register
IF1CREQL1
IF1CREQH1
IF1CMSKL1
IF1CMSKH1
IF1CREQ1
IF1CMSK1
RW
RW
RW
R
CAN 1 - IF1 Command Mask register
(reserved)
000814H
000815H
000816H
000817H
000818H
000819H
00081AH
00081BH
00081CH
00081DH
00081EH
00081FH
000820H
000821H
000822H
000823H
000824H
000825H
000840H
CAN 1 - IF1 Mask Register
CAN 1 - IF1 Mask Register
CAN 1 - IF1 Mask Register
CAN 1 - IF1 Mask Register
CAN 1 - IF1 Arbitration register
CAN 1 - IF1 Arbitration register
CAN 1 - IF1 Arbitration register
CAN 1 - IF1 Arbitration register
CAN 1 - IF1 Message Control Register
CAN 1 - IF1 Message Control Register
CAN 1 - IF1 Data A1
IF1MSK1L1
IF1MSK1H1
IF1MSK2L1
IF1MSK2H1
IF1ARB1L1
IF1ARB1H1
IF1ARB2L1
IF1ARB2H1
IF1MCTRL1
IF1MCTRH1
IF1DTA1L1
IF1DTA1H1
IF1DTA2L1
IF1DTA2H1
IF1DTB1L1
IF1DTB1H1
IF1DTB2L1
IF1DTB2H1
IF2CREQL1
IF1MSK11
IF1MSK21
IF1ARB11
IF1ARB21
IF1MCTR1
IF1DTA11
IF1DTA21
IF1DTB11
IF1DTB21
IF2CREQ1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
CAN 1 - IF1 Data A1
CAN 1 - IF1 Data A2
CAN 1 - IF1 Data A2
CAN 1 - IF1 Data B1
CAN 1 - IF1 Data B1
CAN 1 - IF1 Data B2
CAN 1 - IF1 Data B2
CAN 1 - IF2 Command request register
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 105
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (44 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000841H
CAN 1 - IF2 Command request register
CAN 1 - IF2 Command Mask register
IF2CREQH1
IF2CMSKL1
IF2CMSKH1
RW
000842H
000843H
IF2CMSK1
RW
R
CAN 1 - IF2 Command Mask register
(reserved
000844H
000845H
000846H
000847H
000848H
000849H
00084AH
00084BH
00084CH
00084DH
00084EH
00084FH
000850H
000851H
000852H
000853H
000854H
000855H
000880H
000881H
000882H
000883H
000890H
000891H
000892H
000893H
CAN 1 - IF2 Mask Register
CAN 1 - IF2 Mask Register
CAN 1 - IF2 Mask Register
CAN 1 - IF2 Mask Register
CAN 1 - IF2 Arbitration register
CAN 1 - IF2 Arbitration register
CAN 1 - IF2 Arbitration register
CAN 1 - IF2 Arbitration register
CAN 1 - IF2 Message Control Register
CAN 1 - IF2 Message Control Register
CAN 1 - IF2 Data A1
IF2MSK1L1
IF2MSK1H1
IF2MSK2L1
IF2MSK2H1
IF2ARB1L1
IF2ARB1H1
IF2ARB2L1
IF2ARB2H1
IF2MCTRL1
IF2MCTRH1
IF2DTA1L1
IF2DTA1H1
IF2DTA2L1
IF2DTA2H1
IF2DTB1L1
IF2DTB1H1
IF2DTB2L1
IF2DTB2H1
TREQR1L1
TREQR1H1
TREQR2L1
TREQR2H1
NEWDT1L1
NEWDT1H1
NEWDT2L1
NEWDT2H1
IF2MSK11
IF2MSK21
IF2ARB11
IF2ARB21
IF2MCTR1
IF2DTA11
IF2DTA21
IF2DTB11
IF2DTB21
TREQR11
TREQR21
NEWDT11
NEWDT21
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
CAN 1 - IF2 Data A1
CAN 1 - IF2 Data A2
CAN 1 - IF2 Data A2
CAN 1 - IF2 Data B1
CAN 1 - IF2 Data B1
CAN 1 - IF2 Data B2
CAN 1 - IF2 Data B2
CAN 1 - Transmission Request Register
CAN 1 - Transmission Request Register
CAN 1 - Transmission Request Register
CAN 1 - Transmission Request Register
CAN 1 - New Data Register
CAN 1 - New Data Register
CAN 1 - New Data Register
CAN 1 - New Data Register
R
R
R
R
R
R
R
106
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (45 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0008A0H
CAN 1 - Interrupt Pending Register
CAN 1 - Interrupt Pending Register
CAN 1 - Interrupt Pending Register
CAN 1 - Interrupt Pending Register
CAN 1 - Message Valid Register
CAN 1 - Message Valid Register
CAN 1 - Message Valid Register
CAN 1 - Message Valid Register
CAN 1 - Output enable register
CAN 2 - Control register
INTPND1L1
INTPND1H1
INTPND2L1
INTPND2H1
MSGVAL1L1
MSGVAL1H1
MSGVAL2L1
MSGVAL2H1
COER1
INTPND11
R
R
R
R
R
R
R
R
0008A1H
0008A2H
0008A3H
0008B0H
0008B1H
0008B2H
0008B3H
0008CEH
000900H
000901H
000902H
000903H
000904H
000905H
000906H
000907H
000908H
000909H
00090AH
00090BH
00090CH
00090DH
INTPND21
MSGVAL11
MSGVAL21
RW
RW
R
CTRLRL2
CTRLRH2
STATRL2
CTRLR2
STATR2
ERRCNT2
BTR2
CAN 2 - Control register (reserved)
CAN 2 - Status register
RW
R
CAN 2 - Status register (reserved)
CAN 2 - Error Counter (Transmit)
CAN 2 - Error Counter (Receive)
CAN 2 - Bit Timing Register
STATRH2
ERRCNTL2
ERRCNTH2
BTRL2
R
R
RW
RW
R
CAN 2 - Bit Timing Register
BTRH2
CAN 2 - Interrupt Register
INTRL2
INTR2
CAN 2 - Interrupt Register
INTRH2
R
CAN 2 - Test Register
TESTRL2
TESTRH2
BRPERL2
BRPERH2
TESTR2
BRPER2
RW
R
CAN 2 - Test Register (reserved)
CAN 2 - BRP Extension register
RW
R
CAN 2 - BRP Extension register
(reserved)
000910H
000911H
000912H
000913H
CAN 2 - IF1 Command request register
CAN 2 - IF1 Command request register
CAN 2 - IF1 Command Mask register
IF1CREQL2
IF1CREQH2
IF1CMSKL2
IF1CMSKH2
IF1CREQ2
IF1CMSK2
RW
RW
RW
R
CAN 2 - IF1 Command Mask register
(reserved)
000914H
CAN 2 - IF1 Mask Register
IF1MSK1L2
IF1MSK12
RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 107
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (46 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000915H
CAN 2 - IF1 Mask Register
CAN 2 - IF1 Mask Register
CAN 2 - IF1 Mask Register
CAN 2 - IF1 Arbitration register
CAN 2 - IF1 Arbitration register
CAN 2 - IF1 Arbitration register
CAN 2 - IF1 Arbitration register
CAN 2 - IF1 Message Control Register
CAN 2 - IF1 Message Control Register
CAN 2 - IF1 Data A1
IF1MSK1H2
IF1MSK2L2
IF1MSK2H2
IF1ARB1L2
IF1ARB1H2
IF1ARB2L2
IF1ARB2H2
IF1MCTRL2
IF1MCTRH2
IF1DTA1L2
IF1DTA1H2
IF1DTA2L2
IF1DTA2H2
IF1DTB1L2
IF1DTB1H2
IF1DTB2L2
IF1DTB2H2
IF2CREQL2
IF2CREQH2
IF2CMSKL2
IF2CMSKH2
RW
000916H
000917H
000918H
000919H
00091AH
00091BH
00091CH
00091DH
00091EH
00091FH
000920H
000921H
000922H
000923H
000924H
000925H
000940H
000941H
000942H
000943H
IF1MSK22
IF1ARB12
IF1ARB22
IF1MCTR2
IF1DTA12
IF1DTA22
IF1DTB12
IF1DTB22
IF2CREQ2
IF2CMSK2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
CAN 2 - IF1 Data A1
CAN 2 - IF1 Data A2
CAN 2 - IF1 Data A2
CAN 2 - IF1 Data B1
CAN 2 - IF1 Data B1
CAN 2 - IF1 Data B2
CAN 2 - IF1 Data B2
CAN 2 - IF2 Command request register
CAN 2 - IF2 Command request register
CAN 2 - IF2 Command Mask register
CAN 2 - IF2 Command Mask register
(reserved
000944H
000945H
000946H
000947H
000948H
000949H
00094AH
00094BH
CAN 2 - IF2 Mask Register
CAN 2 - IF2 Mask Register
CAN 2 - IF2 Mask Register
CAN 2 - IF2 Mask Register
CAN 2 - IF2 Arbitration register
CAN 2 - IF2 Arbitration register
CAN 2 - IF2 Arbitration register
CAN 2 - IF2 Arbitration register
IF2MSK1L2
IF2MSK1H2
IF2MSK2L2
IF2MSK2H2
IF2ARB1L2
IF2ARB1H2
IF2ARB2L2
IF2ARB2H2
IF2MSK12
IF2MSK22
IF2ARB12
IF2ARB22
RW
RW
RW
RW
RW
RW
RW
RW
108
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (47 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
00094CH
CAN 2 - IF2 Message Control Register
CAN 2 - IF2 Message Control Register
CAN 2 - IF2 Data A1
IF2MCTRL2
IF2MCTRH2
IF2DTA1L2
IF2DTA1H2
IF2DTA2L2
IF2DTA2H2
IF2DTB1L2
IF2DTB1H2
IF2DTB2L2
IF2DTB2H2
TREQR1L2
TREQR1H2
TREQR2L2
TREQR2H2
NEWDT1L2
NEWDT1H2
NEWDT2L2
NEWDT2H2
INTPND1L2
INTPND1H2
INTPND2L2
INTPND2H2
MSGVAL1L2
MSGVAL1H2
MSGVAL2L2
MSGVAL2H2
COER2
IF2MCTR2
RW
00094DH
00094EH
00094FH
000950H
000951H
000952H
000953H
000954H
000955H
000980H
000981H
000982H
000983H
000990H
000991H
000992H
000993H
0009A0H
0009A1H
0009A2H
0009A3H
0009B0H
0009B1H
0009B2H
0009B3H
0009CEH
000A00H
000A01H
000A02H
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
IF2DTA12
IF2DTA22
IF2DTB12
IF2DTB22
TREQR12
TREQR22
NEWDT12
NEWDT22
INTPND12
INTPND22
MSGVAL12
MSGVAL22
CAN 2 - IF2 Data A1
CAN 2 - IF2 Data A2
CAN 2 - IF2 Data A2
CAN 2 - IF2 Data B1
CAN 2 - IF2 Data B1
CAN 2 - IF2 Data B2
CAN 2 - IF2 Data B2
CAN 2 - Transmission Request Register
CAN 2 - Transmission Request Register
CAN 2 - Transmission Request Register
CAN 2 - Transmission Request Register
CAN 2 - New Data Register
CAN 2 - New Data Register
CAN 2 - New Data Register
CAN 2 - New Data Register
CAN 2 - Interrupt Pending Register
CAN 2 - Interrupt Pending Register
CAN 2 - Interrupt Pending Register
CAN 2 - Interrupt Pending Register
CAN 2 - Message Valid Register
CAN 2 - Message Valid Register
CAN 2 - Message Valid Register
CAN 2 - Message Valid Register
CAN 2 - Output enable register
CAN 3 - Control register
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
RW
RW
R
CTRLRL3
CTRLR3
STATR3
CAN 3 - Control register (reserved)
CAN 3 - Status register
CTRLRH3
STATRL3
RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 109
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (48 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000A03H
CAN 3 - Status register (reserved)
CAN 3 - Error Counter (Transmit)
CAN 3 - Error Counter (Receive)
CAN 3 - Bit Timing Register
CAN 3 - Bit Timing Register
CAN 3 - Interrupt Register
STATRH3
ERRCNTL3
ERRCNTH3
BTRL3
R
R
R
000A04H
000A05H
000A06H
000A07H
000A08H
000A09H
000A0AH
000A0BH
000A0CH
000A0DH
ERRCNT3
BTR3
RW
RW
R
BTRH3
INTRL3
INTR3
CAN 3 - Interrupt Register
INTRH3
R
CAN 3 - Test Register
TESTRL3
TESTRH3
BRPERL3
BRPERH3
TESTR3
BRPER3
RW
R
CAN 3 - Test Register (reserved)
CAN 3 - BRP Extension register
RW
R
CAN 3 - BRP Extension register
(reserved)
000A10H
000A11H
000A12H
000A13H
CAN 3 - IF1 Command request register
CAN 3 - IF1 Command request register
CAN 3 - IF1 Command Mask register
IF1CREQL3
IF1CREQH3
IF1CMSKL3
IF1CMSKH3
IF1CREQ3
IF1CMSK3
RW
RW
RW
R
CAN 3 - IF1 Command Mask register
(reserved)
000A14H
000A15H
000A16H
000A17H
000A18H
000A19H
000A1AH
000A1BH
000A1CH
000A1DH
000A1EH
000A1FH
000A20H
CAN 3 - IF1 Mask Register
CAN 3 - IF1 Mask Register
CAN 3 - IF1 Mask Register
CAN 3 - IF1 Mask Register
CAN 3 - IF1 Arbitration register
CAN 3 - IF1 Arbitration register
CAN 3 - IF1 Arbitration register
CAN 3 - IF1 Arbitration register
CAN 3 - IF1 Message Control Register
CAN 3 - IF1 Message Control Register
CAN 3 - IF1 Data A1
IF1MSK1L3
IF1MSK1H3
IF1MSK2L3
IF1MSK2H3
IF1ARB1L3
IF1ARB1H3
IF1ARB2L3
IF1ARB2H3
IF1MCTRL3
IF1MCTRH3
IF1DTA1L3
IF1DTA1H3
IF1DTA2L3
IF1MSK13
IF1MSK23
IF1ARB13
IF1ARB23
IF1MCTR3
IF1DTA13
IF1DTA23
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
CAN 3 - IF1 Data A1
CAN 3 - IF1 Data A2
110
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (49 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000A21H
CAN 3 - IF1 Data A2
IF1DTA2H3
IF1DTB1L3
IF1DTB1H3
IF1DTB2L3
IF1DTB2H3
IF2CREQL3
IF2CREQH3
IF2CMSKL3
IF2CMSKH3
RW
000A22H
000A23H
000A24H
000A25H
000A40H
000A41H
000A42H
000A43H
CAN 3 - IF1 Data B1
IF1DTB13
IF1DTB23
IF2CREQ3
IF2CMSK3
RW
RW
RW
RW
RW
RW
RW
R
CAN 3 - IF1 Data B1
CAN 3 - IF1 Data B2
CAN 3 - IF1 Data B2
CAN 3 - IF2 Command request register
CAN 3 - IF2 Command request register
CAN 3 - IF2 Command Mask register
CAN 3 - IF2 Command Mask register
(reserved
000A44H
000A45H
000A46H
000A47H
000A48H
000A49H
000A4AH
000A4BH
000A4CH
000A4DH
000A4EH
000A4FH
000A50H
000A51H
000A52H
000A53H
000A54H
000A55H
000A80H
000A81H
CAN 3 - IF2 Mask Register
CAN 3 - IF2 Mask Register
CAN 3 - IF2 Mask Register
CAN 3 - IF2 Mask Register
CAN 3 - IF2 Arbitration register
CAN 3 - IF2 Arbitration register
CAN 3 - IF2 Arbitration register
CAN 3 - IF2 Arbitration register
CAN 3 - IF2 Message Control Register
CAN 3 - IF2 Message Control Register
CAN 3 - IF2 Data A1
IF2MSK1L3
IF2MSK1H3
IF2MSK2L3
IF2MSK2H3
IF2ARB1L3
IF2ARB1H3
IF2ARB2L3
IF2ARB2H3
IF2MCTRL3
IF2MCTRH3
IF2DTA1L3
IF2DTA1H3
IF2DTA2L3
IF2DTA2H3
IF2DTB1L3
IF2DTB1H3
IF2DTB2L3
IF2DTB2H3
TREQR1L3
TREQR1H3
IF2MSK13
IF2MSK23
IF2ARB13
IF2ARB23
IF2MCTR3
IF2DTA13
IF2DTA23
IF2DTB13
IF2DTB23
TREQR13
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
CAN 3 - IF2 Data A1
CAN 3 - IF2 Data A2
CAN 3 - IF2 Data A2
CAN 3 - IF2 Data B1
CAN 3 - IF2 Data B1
CAN 3 - IF2 Data B2
CAN 3 - IF2 Data B2
CAN 3 - Transmission Request Register
CAN 3 - Transmission Request Register
R
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 111
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (50 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000A82H
CAN 3 - Transmission Request Register
CAN 3 - Transmission Request Register
CAN 3 - New Data Register
TREQR2L3
TREQR2H3
NEWDT1L3
NEWDT1H3
NEWDT2L3
NEWDT2H3
INTPND1L3
INTPND1H3
INTPND2L3
INTPND2H3
MSGVAL1L3
MSGVAL1H3
MSGVAL2L3
MSGVAL2H3
COER3
TREQR23
NEWDT13
NEWDT23
INTPND13
INTPND23
MSGVAL13
MSGVAL23
R
R
R
R
R
R
R
R
R
R
R
R
R
R
000A83H
000A90H
000A91H
000A92H
000A93H
000AA0H
000AA1H
000AA2H
000AA3H
000AB0H
000AB1H
000AB2H
000AB3H
000ABEH
000B00H
000B01H
000B02H
000B03H
000B04H
000B05H
000B06H
000B07H
000B08H
000B09H
000B0AH
000B0BH
000B0CH
000B0DH
CAN 3 - New Data Register
CAN 3 - New Data Register
CAN 3 - New Data Register
CAN 3 - Interrupt Pending Register
CAN 3 - Interrupt Pending Register
CAN 3 - Interrupt Pending Register
CAN 3 - Interrupt Pending Register
CAN 3 - Message Valid Register
CAN 3 - Message Valid Register
CAN 3 - Message Valid Register
CAN 3 - Message Valid Register
CAN 3 - Output enable register
CAN 4 - Control register
RW
RW
R
CTRLRL4
CTRLRH4
STATRL4
CTRLR4
STATR4
ERRCNT4
BTR4
CAN 4 - Control register (reserved)
CAN 4 - Status register
RW
R
CAN 4 - Status register (reserved)
CAN 4 - Error Counter (Transmit)
CAN 4 - Error Counter (Receive)
CAN 4 - Bit Timing Register
STATRH4
ERRCNTL4
ERRCNTH4
BTRL4
R
R
RW
RW
R
CAN 4 - Bit Timing Register
BTRH4
CAN 4 - Interrupt Register
INTRL4
INTR4
CAN 4 - Interrupt Register
INTRH4
R
CAN 4 - Test Register
TESTRL4
TESTR4
BRPER4
RW
R
CAN 4 - Test Register (reserved)
CAN 4 - BRP Extension register
TESTRH4
BRPERL4
BRPERH4
RW
R
CAN 4 - BRP Extension register
(reserved)
112
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (51 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000B10H
CAN 4 - IF1 Command request register
CAN 4 - IF1 Command request register
CAN 4 - IF1 Command Mask register
IF1CREQL4
IF1CREQH4
IF1CMSKL4
IF1CMSKH4
IF1CREQ4
RW
000B11H
000B12H
000B13H
RW
RW
R
IF1CMSK4
CAN 4 - IF1 Command Mask register
(reserved)
000B14H
000B15H
000B16H
000B17H
000B18H
000B19H
000B1AH
000B1BH
000B1CH
000B1DH
000B1EH
000B1FH
000B20H
000B21H
000B22H
000B23H
000B24H
000B25H
000B40H
000B41H
000B42H
000B43H
CAN 4 - IF1 Mask Register
CAN 4 - IF1 Mask Register
CAN 4 - IF1 Mask Register
CAN 4 - IF1 Mask Register
CAN 4 - IF1 Arbitration register
CAN 4 - IF1 Arbitration register
CAN 4 - IF1 Arbitration register
CAN 4 - IF1 Arbitration register
CAN 4 - IF1 Message Control Register
CAN 4 - IF1 Message Control Register
CAN 4 - IF1 Data A1
IF1MSK1L4
IF1MSK1H4
IF1MSK2L4
IF1MSK2H4
IF1ARB1L4
IF1ARB1H4
IF1ARB2L4
IF1ARB2H4
IF1MCTRL4
IF1MCTRH4
IF1DTA1L4
IF1DTA1H4
IF1DTA2L4
IF1DTA2H4
IF1DTB1L4
IF1DTB1H4
IF1DTB2L4
IF1DTB2H4
IF2CREQL4
IF2CREQH4
IF2CMSKL4
IF2CMSKH4
IF1MSK14
IF1MSK24
IF1ARB14
IF1ARB24
IF1MCTR4
IF1DTA14
IF1DTA24
IF1DTB14
IF1DTB24
IF2CREQ4
IF2CMSK4
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
CAN 4 - IF1 Data A1
CAN 4 - IF1 Data A2
CAN 4 - IF1 Data A2
CAN 4 - IF1 Data B1
CAN 4 - IF1 Data B1
CAN 4 - IF1 Data B2
CAN 4 - IF1 Data B2
CAN 4 - IF2 Command request register
CAN 4 - IF2 Command request register
CAN 4 - IF2 Command Mask register
CAN 4 - IF2 Command Mask register
(reserved
000B44H
000B45H
CAN 4 - IF2 Mask Register
CAN 4 - IF2 Mask Register
IF2MSK1L4
IF2MSK1H4
IF2MSK14
RW
RW
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 113
MB96300 Series
Preliminary Specification
Table 0-1 I/O map (52 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000B46H
CAN 4 - IF2 Mask Register
IF2MSK2L4
IF2MSK2H4
IF2ARB1L4
IF2ARB1H4
IF2ARB2L4
IF2ARB2H4
IF2MCTRL4
IF2MCTRH4
IF2DTA1L4
IF2DTA1H4
IF2DTA2L4
IF2DTA2H4
IF2DTB1L4
IF2DTB1H4
IF2DTB2L4
IF2DTB2H4
TREQR1L4
TREQR1H4
TREQR2L4
TREQR2H4
NEWDT1L4
NEWDT1H4
NEWDT2L4
NEWDT2H4
INTPND1L4
INTPND1H4
INTPND2L4
INTPND2H4
MSGVAL1L4
MSGVAL1H4
IF2MSK24
IF2ARB14
IF2ARB24
IF2MCTR4
IF2DTA14
IF2DTA24
IF2DTB14
IF2DTB24
TREQR14
TREQR24
NEWDT14
NEWDT24
INTPND14
INTPND24
MSGVAL14
RW
000B47H
000B48H
000B49H
000B4AH
000B4BH
000B4CH
000B4DH
000B4EH
000B4FH
000B50H
000B51H
000B52H
000B53H
000B54H
000B55H
000B80H
000B81H
000B82H
000B83H
000B90H
000B91H
000B92H
000B93H
000BA0H
000BA1H
000BA2H
000BA3H
000BB0H
000BB1H
CAN 4 - IF2 Mask Register
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
CAN 4 - IF2 Arbitration register
CAN 4 - IF2 Arbitration register
CAN 4 - IF2 Arbitration register
CAN 4 - IF2 Arbitration register
CAN 4 - IF2 Message Control Register
CAN 4 - IF2 Message Control Register
CAN 4 - IF2 Data A1
CAN 4 - IF2 Data A1
CAN 4 - IF2 Data A2
CAN 4 - IF2 Data A2
CAN 4 - IF2 Data B1
CAN 4 - IF2 Data B1
CAN 4 - IF2 Data B2
CAN 4 - IF2 Data B2
CAN 4 - Transmission Request Register
CAN 4 - Transmission Request Register
CAN 4 - Transmission Request Register
CAN 4 - Transmission Request Register
CAN 4 - New Data Register
CAN 4 - New Data Register
CAN 4 - New Data Register
CAN 4 - New Data Register
CAN 4 - Interrupt Pending Register
CAN 4 - Interrupt Pending Register
CAN 4 - Interrupt Pending Register
CAN 4 - Interrupt Pending Register
CAN 4 - Message Valid Register
CAN 4 - Message Valid Register
R
R
R
R
R
R
R
R
R
R
R
R
R
114
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Table 0-1 I/O map (53 / 53)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000BB2H
000BB3H
000BCEH
000C00H
CAN 4 - Message Valid Register
CAN 4 - Message Valid Register
CAN 4 - Output enable register
MSGVAL2L4
MSGVAL2H4
COER4
MSGVAL24
R
R
RW
RW
External bus area (16-bit address up to
000FFFH)
EXTBUS1
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 115
MB96300 Series
Preliminary Specification
■ INTERRUPT VECTOR TABLE MB96V300
Index in
ICR to
program
Offset
in vector
table
Vector
number
DMA can
clear
Vector name
Description
IL
-
0
3FC
3F8
3F4
3F0
3EC
3E8
3E4
3E0
3DC
3D8
3D4
3D0
3CC
3C8
3C4
3C0
3BC
3B8
3B4
3B0
3AC
3A8
3A4
3A0
39C
398
394
390
38C
388
384
380
37C
CALLV0
CALLV1
No
No
1
-
2
CALLV2
No
-
3
CALLV3
No
-
4
CALLV4
No
-
5
CALLV5
No
-
6
CALLV6
No
-
7
CALLV7
No
-
8
RESET
No
-
9
INT9
No
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
EXCEPTION
NMI
No
-
No
-
Non-Maskable Interrupt
Delayed Interrupt
RC Timer
DLY
No
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RC_TIMER
MC_TIMER
SC_TIMER
RESERVED
EXTINT0
EXTINT1
EXTINT2
EXTINT3
EXTINT4
EXTINT5
EXTINT6
EXTINT7
EXTINT8
EXTINT9
EXTINT10
EXTINT11
EXTINT12
EXTINT13
EXTINT14
EXTINT15
No
No
Main Clock Timer
Sub Clock Timer
No
No
Reserved
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
External Interrupt 8
External Interrupt 9
External Interrupt 10
External Interrupt 11
External Interrupt 12
External Interrupt 13
External Interrupt 14
External Interrupt 15
116
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Index in
ICR to
program
IL
Offset
in vector
table
Vector
number
DMA can
clear
Vector name
Description
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
378
374
370
36C
368
364
360
35C
358
354
350
34C
348
344
340
33C
338
334
330
32C
328
324
320
31C
318
314
310
30C
308
304
300
2FC
2F8
2F4
2F0
CAN0
CAN1
CAN2
CAN3
CAN4
PPG0
PPG1
PPG2
PPG3
PPG4
PPG5
PPG6
PPG7
PPG8
PPG9
PPG10
PPG11
PPG12
PPG13
PPG14
PPG15
PPG16
PPG17
PPG18
PPG19
RLT0
No
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
CAN Controller 0
No
CAN Controller 1
CAN Controller 2
CAN Controller 3
CAN Controller 4
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Programmable Pulse Generator 0
Programmable Pulse Generator 1
Programmable Pulse Generator 2
Programmable Pulse Generator 3
Programmable Pulse Generator 4
Programmable Pulse Generator 5
Programmable Pulse Generator 6
Programmable Pulse Generator 7
Programmable Pulse Generator 8
Programmable Pulse Generator 9
Programmable Pulse Generator 10
Programmable Pulse Generator 11
Programmable Pulse Generator 12
Programmable Pulse Generator 13
Programmable Pulse Generator 14
Programmable Pulse Generator 15
Programmable Pulse Generator 16
Programmable Pulse Generator 17
Programmable Pulse Generator 18
Programmable Pulse Generator 19
Reload Timer 0
RLT1
Reload Timer 1
RLT2
Reload Timer 2
RLT3
Reload Timer 3
RLT4
Reload Timer 4
RLT5
Reload Timer 5
PPGRLT
ICU0
Reload Timer 6 - dedicated for PPG
Input Capture Unit 0
ICU1
Input Capture Unit 1
ICU2
Input Capture Unit 2
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 117
MB96300 Series
Preliminary Specification
Index in
ICR to
program
Offset
Vector
number
DMA can
clear
in vector
table
Vector name
Description
IL
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
2EC
2E8
2E4
2E0
2DC
2D8
2D4
2D0
2CC
2C8
2C4
2C0
2BC
2B8
2B4
2B0
2AC
2A8
2A4
2A0
29C
298
294
290
28C
288
284
280
27C
278
274
270
26C
268
264
ICU3
ICU4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
Input Capture Unit 3
Input Capture Unit 4
Input Capture Unit 5
Input Capture Unit 6
Input Capture Unit 7
Input Capture Unit 8
Input Capture Unit 9
Input Capture Unit 10
Input Capture Unit 11
Output Compare Unit 0
Output Compare Unit 1
Output Compare Unit 2
Output Compare Unit 3
Output Compare Unit 4
Output Compare Unit 5
Output Compare Unit 6
Output Compare Unit 7
Output Compare Unit 8
Output Compare Unit 9
Output Compare Unit 10
Output Compare Unit 11
Free Running Timer 0
Free Running Timer 1
Free Running Timer 2
Free Running Timer 3
Real Timer Clock
ICU5
ICU6
ICU7
ICU8
ICU9
ICU10
ICU11
OCU0
OCU1
OCU2
OCU3
OCU4
OCU5
OCU6
OCU7
OCU8
OCU9
OCU10
OCU11
FRT0
FRT1
FRT2
FRT3
RTC0
CAL0
SG0
No
Clock Calibration Unit
Sound Generator
No
IIC0
Yes
Yes
Yes
No
I2C interface
IIC1
I2C interface
ADC0
ALARM0
ALARM1
LINR0
LINT0
A/D Converter
Alarm Comparator 0
Alarm Comparator 1
LIN USART 0 RX
No
Yes
Yes
LIN USART 0 TX
118
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Index in
ICR to
program
IL
Offset
in vector
table
Vector
number
DMA can
clear
Vector name
Description
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
260
25C
258
254
250
24C
248
244
240
23C
238
234
230
22C
228
224
220
21C
LINR1
LINT1
LINR2
LINT2
LINR3
LINT3
LINR4
LINT4
LINR5
LINT5
LINR6
LINT6
LINR7
LINT7
LINR8
LINT8
LINR9
LINT9
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
LIN USART 1 RX
LIN USART 1 TX
LIN USART 2 RX
LIN USART 2 TX
LIN USART 3 RX
LIN USART 3 TX
LIN USART 4 RX
LIN USART 4 TX
LIN USART 5 RX
LIN USART 5 TX
LIN USART 6 RX
LIN USART 6 TX
LIN USART 7 RX
LIN USART 7 TX
LIN USART 8 RX
LIN USART 8 TX
LIN USART 9 RX
LIN USART 9 TX
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 119
MB96300 Series
Preliminary Specification
■ INTERRUPT VECTOR TABLE MB96(F)32x
Offset in
vector ta-
ble
Index in
ICR to pro-
gram
Vector
number
Clearedby
DMA
Vector name
Description
0
3FC
3F8
3F4
3F0
3EC
3E8
3E4
3E0
3DC
3D8
3D4
3D0
3CC
3C8
3C4
3C0
3BC
3B8
3B4
3B0
3AC
3A8
3A4
3A0
39C
398
394
390
38C
388
384
380
37C
378
CALLV0
CALLV1
CALLV2
CALLV3
CALLV4
CALLV5
CALLV6
CALLV7
RESET
No
No
-
1
-
2
No
-
3
No
-
4
No
-
5
No
-
6
No
-
7
No
-
8
No
-
9
INT9
No
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
EXCEPTION
NMI
No
-
No
-
Non-Maskable Interrupt
Delayed Interrupt
RC Timer
DLY
No
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
RC_TIMER
MC_TIMER
SC_TIMER
PLL_UNLOCK
EXTINT0
EXINT1
No
No
Main Clock Timer
Sub Clock Timer
No
No
Reserved
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 7
External Interrupt 8
External Interrupt 9
External Interrupt 10
External Interrupt 11
External Interrupt 12
External Interrupt 13
External Interrupt 14
External Interrupt 15
CAN Controller 1
CAN Controller 2
EXTINT2
EXTINT3
EXTINT4
EXTINT5
EXTINT7
EXTINT8
EXTINT9
EXTINT10
EXTINT11
EXTINT12
EXTINT13
EXTINT14
EXTINT15
CAN1
CAN2
No
120
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Offset in
vector ta-
ble
Index in
ICR to pro-
gram
Vector
number
Clearedby
DMA
Vector name
Description
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
374
370
36C
368
364
360
35C
358
354
350
34C
348
344
340
33C
338
334
330
32C
328
324
320
31C
318
314
310
30C
308
304
300
2FC
2F8
2F4
2F0
2EC
2E8
PPG0
PPG1
PPG2
PPG3
PPG4
PPG5
PPG6
PPG7
PPG8
PPG9
PPG10
PPG11
PPG12
PPG13
PPG14
PPG15
PPG16
PPG17
PPG18
PPG19
RLT0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
Programmable Pulse Generator 0
Programmable Pulse Generator 1
Programmable Pulse Generator 2
Programmable Pulse Generator 3
Programmable Pulse Generator 4
Programmable Pulse Generator 5
Programmable Pulse Generator 6
Programmable Pulse Generator 7
Programmable Pulse Generator 8
Programmable Pulse Generator 9
Programmable Pulse Generator 10
Programmable Pulse Generator 11
Programmable Pulse Generator 12
Programmable Pulse Generator 13
Programmable Pulse Generator 14
Programmable Pulse Generator 15
Programmable Pulse Generator 16
Programmable Pulse Generator 17
Programmable Pulse Generator 18
Programmable Pulse Generator 19
Reload Timer 0
RLT1
Reload Timer 1
RLT2
Reload Timer 2
RLT3
Reload Timer 3
PPGRLT
ICU0
Reload Timer 6 - dedicated for PPG
Input Capture Unit 0
ICU1
Input Capture Unit 1
ICU2
Input Capture Unit 2
ICU3
Input Capture Unit 3
ICU4
Input Capture Unit 4
ICU5
Input Capture Unit 5
ICU6
Input Capture Unit 6
ICU7
Input Capture Unit 7
ICU8
Input Capture Unit 8
ICU9
Input Capture Unit 9
ICU10
Input Capture Unit 10
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 121
MB96300 Series
Preliminary Specification
Offset in
Vector
number
Index in
ICR to pro-
gram
Clearedby
DMA
vector ta-
ble
Vector name
Description
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
2E4
2E0
2DC
2D8
2D4
2D0
2CC
2C8
2C4
2C0
2BC
2B8
2B4
2B0
2AC
2A8
2A4
2A0
29C
298
294
290
28C
288
ICU11
OCU4
OCU5
OCU6
OCU7
OCU10
OCU11
FRT0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
Input Capture Unit 11
Output Compare Unit 4
Output Compare Unit 5
Output Compare Unit 6
Output Compare Unit 7
Output Compare Unit 10
Output Compare Unit 11
Free Running Timer 0
Free Running Timer 1
Free Running Timer 2
Free Running Timer 3
Real Timer Clock
FRT1
FRT2
FRT3
RTC0
CAL0
No
Clock Calibration Unit
I2C interface
IIC0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
ADC0
A/D Converter
LINR2
LINT2
LINR3
LINT3
LINR7
LINT7
LINR8
LINT8
MAIN_FLASH
LIN USART 2 RX
LIN USART 2 TX
LIN USART 3 RX
LIN USART 3 TX
LIN USART 7 RX
LIN USART 7 TX
LIN USART 8 RX
LIN USART 8 TX
Main Flash memory interrupt
122
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
■ INTERRUPT VECTOR TABLE MB96(F)34x
Offset in
vector ta-
ble
Index in
ICR to pro-
gram
Vector
number
Cleared
by DMA
Vector name
Description
0
3FC
3F8
3F4
3F0
3EC
3E8
3E4
3E0
3DC
3D8
3D4
3D0
3CC
3C8
3C4
3C0
3BC
3B8
3B4
3B0
3AC
3A8
3A4
3A0
39C
398
394
390
38C
388
384
380
37C
CALLV0
CALLV1
No
No
-
1
-
2
CALLV2
No
-
3
CALLV3
No
-
4
CALLV4
No
-
5
CALLV5
No
-
6
CALLV6
No
-
7
CALLV7
No
-
8
RESET
No
-
9
INT9
No
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
EXCEPTION
NMI
No
-
No
-
Non-Maskable Interrupt
DLY
No
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Delayed Interrupt
RC Timer
RC_TIMER
MC_TIMER
SC_TIMER
RESERVED
EXTINT0
EXTINT1
EXTINT2
EXTINT3
EXTINT4
EXTINT5
EXTINT6
EXTINT7
EXTINT8
EXTINT9
EXTINT10
EXTINT11
EXTINT12
EXTINT13
EXTINT14
EXTINT15
No
No
Main Clock Timer
Sub Clock Timer
No
No
Reserved
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
External Interrupt 8
External Interrupt 9
External Interrupt 10
External Interrupt 11
External Interrupt 12
External Interrupt 13
External Interrupt 14
External Interrupt 15
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 123
MB96300 Series
Preliminary Specification
Offset in
Vector
number
Index in
ICR to pro-
gram
Cleared
by DMA
vector ta-
ble
Vector name
Description
CAN Controller 0
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
378
374
370
36C
368
364
360
35C
358
354
350
34C
348
344
340
33C
338
334
330
32C
328
324
320
31C
318
314
310
30C
308
304
300
2FC
2F8
2F4
2F0
2EC
CAN0
CAN1
PPG0
PPG1
PPG2
PPG3
PPG4
PPG5
PPG6
PPG7
PPG8
PPG9
PPG10
PPG11
PPG12
PPG13
PPG14
PPG15
RLT0
No
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
No
CAN Controller 1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Programmable Pulse Generator 0
Programmable Pulse Generator 1
Programmable Pulse Generator 2
Programmable Pulse Generator 3
Programmable Pulse Generator 4
Programmable Pulse Generator 5
Programmable Pulse Generator 6
Programmable Pulse Generator 7
Programmable Pulse Generator 8
Programmable Pulse Generator 9
Programmable Pulse Generator 10
Programmable Pulse Generator 11
Programmable Pulse Generator 12
Programmable Pulse Generator 13
Programmable Pulse Generator 14
Programmable Pulse Generator 15
Reload Timer 0
RLT1
Reload Timer 1
RLT2
Reload Timer 2
RLT3
Reload Timer 3
PPGRLT
ICU0
Reload Timer 6 - dedicated for PPG
Input Capture Unit 0
ICU1
Input Capture Unit 1
ICU2
Input Capture Unit 2
ICU3
Input Capture Unit 3
ICU4
Input Capture Unit 4
ICU5
Input Capture Unit 5
ICU6
Input Capture Unit 6
ICU7
Input Capture Unit 7
OCU0
OCU1
OCU2
OCU3
OCU4
Output Compare Unit 0
Output Compare Unit 1
Output Compare Unit 2
Output Compare Unit 3
Output Compare Unit 4
124
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Offset in
vector ta-
ble
Index in
ICR to pro-
gram
Vector
number
Cleared
by DMA
Vector name
Description
Output Compare Unit 5
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
2E8
2E4
2E0
2DC
2D8
2D4
2D0
2CC
2C8
2C4
2C0
2BC
2B8
2B4
2B0
2AC
2A8
2A4
2A0
OCU5
OCU6
OCU7
FRT0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
Output Compare Unit 6
Output Compare Unit 7
Free Running Timer 0
Free Running Timer 1
I2C interface
FRT1
IIC0
IIC1
I2C interface
ADC0
A/D Converter
ALARM0
ALARM1
LINR0
LINT0
Alarm Comparator 0
Alarm Comparator 1
LIN USART 0 RX
LIN USART 0 TX
LIN USART 1 RX
LIN USART 1 TX
LIN USART 2 RX
LIN USART 2 TX
LIN USART 3 RX
LIN USART 3 TX
Main Flash memory
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
LINR1
LINT1
LINR2
LINT2
LINR3
LINT3
MAIN_FLASH
Satellite Flash memory
(only MB96F348H/T)
88
89
90
91
92
93
94
95
96
29C
298
294
290
28C
288
284
280
27C
SAT_FLASH
LINR7
LINT7
No
Yes
Yes
Yes
Yes
Yes
Yes
No
88
89
90
91
92
93
94
95
96
LIN USART 7 RX
(only MB96F34(6/7/8)R/Y)
LIN USART 7 TX
(only MB96F34(6/7/8)R/Y)
LIN USART 8 RX
(only MB96F34(6/7/8)R/Y)
LINR8
LINT8
LIN USART 8 TX
(only MB96F34(6/7/8)R/Y)
LIN USART 9 RX
(only MB96F34(6/7/8)R/Y)
LINR9
LINT9
LIN USART 9 TX
(only MB96F34(6/7/8)R/Y)
Real Timer Clock
(only MB96F34(6/7/8)R/Y)
RTC0
Clock Calibration Unit
(only MB96F34(6/7/8)R/Y)
CAL0
No
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 125
MB96300 Series
Preliminary Specification
126
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
■ INTERRUPT VECTOR TABLE MB96(F)35x
Offset in
vector ta-
ble
Index in
ICR to pro-
gram
Vector
number
Clearedby
DMA
Vector name
Description
0
1
3FC
3F8
3F4
3F0
3EC
3E8
3E4
3E0
3DC
3D8
3D4
3D0
3CC
3C8
3C4
3C0
3BC
3B8
CALLV0
CALLV1
CALLV2
CALLV3
CALLV4
CALLV5
CALLV6
CALLV7
RESET
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
-
-
2
-
3
-
4
-
5
-
6
-
7
-
8
-
9
INT9
-
10
11
12
13
14
15
16
17
EXCEPTION
NMI
-
-
Non-Maskable Interrupt
Delayed Interrupt
RC Timer
DLY
12
13
14
15
16
17
RC_TIMER
MC_TIMER
SC_TIMER
PLL_UNLOCK
EXTINT0
Main Clock Timer
Sub Clock Timer
Reserved
External Interrupt 0
19
21
3B0
3A8
EXTINT2
EXTINT4
Yes
Yes
19
21
External Interrupt 2
External Interrupt 4
23
24
25
26
27
28
29
30
31
32
3A0
39C
398
394
390
38C
388
384
380
37C
EXTINT7
EXTINT8
EXTINT9
EXTINT10
EXTINT11
EXTINT12
EXTINT13
EXTINT14
EXTINT15
CAN1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
23
24
25
26
27
28
29
30
31
32
External Interrupt 7
External Interrupt 8
External Interrupt 9
External Interrupt 10
External Interrupt 11
External Interrupt 12
External Interrupt 13
External Interrupt 14
External Interrupt 15
CAN Controller 1
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 127
MB96300 Series
Preliminary Specification
Offset in
Vector
number
Index in
ICR to pro-
gram
Clearedby
DMA
vector ta-
ble
Vector name
Description
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
378
374
370
36C
368
364
360
35C
358
354
350
34C
348
344
340
33C
338
334
330
32C
328
324
320
31C
318
314
310
30C
CAN2
PPG0
PPG1
PPG2
PPG3
PPG4
PPG5
PPG6
PPG7
PPG8
PPG9
PPG10
PPG11
PPG12
PPG13
PPG14
PPG15
PPG16
PPG17
PPG18
PPG19
RLT0
No
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
CAN Controller 2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Programmable Pulse Generator 0
Programmable Pulse Generator 1
Programmable Pulse Generator 2
Programmable Pulse Generator 3
Programmable Pulse Generator 4
Programmable Pulse Generator 5
Programmable Pulse Generator 6
Programmable Pulse Generator 7
Programmable Pulse Generator 8
Programmable Pulse Generator 9
Programmable Pulse Generator 10
Programmable Pulse Generator 11
Programmable Pulse Generator 12
Programmable Pulse Generator 13
Programmable Pulse Generator 14
Programmable Pulse Generator 15
Programmable Pulse Generator 16
Programmable Pulse Generator 17
Programmable Pulse Generator 18
Programmable Pulse Generator 19
Reload Timer 0
RLT1
Reload Timer 1
RLT2
Reload Timer 2
RLT3
Reload Timer 3
PPGRLT
ICU0
Reload Timer 6 - dedicated for PPG
Input Capture Unit 0
ICU1
Input Capture Unit 1
63
64
65
66
300
2FC
2F8
2F4
ICU4
ICU5
ICU6
ICU7
Yes
Yes
Yes
Yes
63
64
65
66
Input Capture Unit 4
Input Capture Unit 5
Input Capture Unit 6
Input Capture Unit 7
128
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Offset in
vector ta-
ble
Index in
ICR to pro-
gram
Vector
number
Clearedby
DMA
Vector name
Description
71
72
73
74
2E0
2DC
2D8
2D4
OCU4
OCU5
OCU6
OCU7
Yes
Yes
Yes
Yes
71
72
73
74
Output Compare Unit 4
Output Compare Unit 5
Output Compare Unit 6
Output Compare Unit 7
77
78
2C8
2C4
FRT0
FRT1
Yes
Yes
77
78
Free Running Timer 0
Free Running Timer 1
81
82
83
84
85
86
87
88
89
90
91
92
93
2B8
2B4
2B0
2AC
2A8
2A4
2A0
29C
298
294
290
28C
288
RTC0
CAL0
No
No
81
82
83
84
85
86
87
88
89
90
91
92
93
Real Timer Clock
Clock Calibration Unit
I2C interface
IIC0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
ADC0
A/D Converter
LINR2
LINT2
LIN USART 2 RX
LIN USART 2 TX
LIN USART 3 RX
LIN USART 3 TX
LIN USART 7 RX
LIN USART 7 TX
LIN USART 8 RX
LIN USART 8 TX
Main Flash memory interrupt
LINR3
LINT3
LINR7
LINT7
LINR8
LINT8
MAIN_FLASH
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 129
MB96300 Series
Preliminary Specification
■ INTERRUPT VECTOR TABLE MB96(F)36x
Index in
ICR to
program
Offset
in vector
table
Vector
number
Clearedby
DMA
Vector name
Description
IL
-
0
3FC
3F8
3F4
3F0
3EC
3E8
3E4
3E0
3DC
3D8
3D4
3D0
3CC
3C8
3C4
3C0
3BC
3B8
3B4
3B0
3AC
3A8
3A4
3A0
39C
398
394
390
38C
388
384
380
37C
CALLV0
CALLV1
CALLV2
CALLV3
CALLV4
CALLV5
CALLV6
CALLV7
RESET
No
No
1
-
2
No
-
3
No
-
4
No
-
5
No
-
6
No
-
7
No
-
8
No
-
9
INT9
No
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
EXCEPTION
NMI
No
-
No
-
Non-Maskable Interrupt
Delayed Interrupt
DLY
No
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RC_TIMER
MC_TIMER
SC_TIMER
RESERVED
EXTINT0
EXTINT1
EXTINT2
EXTINT3
EXTINT4
EXTINT5
EXTINT9
EXTINT12
EXTINT14
CAN1
No
RC Timer
No
Main Clock Timer
No
Sub Clock Timer
No
Reserved
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 9
External Interrupt 12
External Interrupt 14
CAN Controller 1
PPG4
Yes
Yes
Yes
Yes
Yes
Yes
Programmable Pulse Generator 4
Programmable Pulse Generator 5
Programmable Pulse Generator 6
Programmable Pulse Generator 7
Programmable Pulse Generator 12
Programmable Pulse Generator 13
MB96300_shortspec.fm
PPG5
PPG6
PPG7
PPG12
PPG13
130
FME/EMDC- 2007-02-12
Preliminary Specification
MB96300
Index in
ICR to
program
IL
Offset
in vector
table
Vector
number
Clearedby
DMA
Vector name
Description
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
378
374
370
36C
368
364
360
35C
358
354
350
34C
348
344
340
33C
PPG14
PPG15
RLT2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Programmable Pulse Generator 14
Programmable Pulse Generator 15
Reload Timer 2
RLT3
Reload Timer 3
PPGRLT
ICU0
Reload Timer 6 - dedicated for PPG
Input Capture Unit 0
Input Capture Unit 1
Input Capture Unit 2
Input Capture Unit 3
Free Running Timer 0
A/D Converter
ICU1
ICU2
ICU3
FRT0
ADC0
LINR0
LINT0
LIN USART 0 RX
No
LIN USART 0 TX
LINR1
LINT1
No
LIN USART 1 RX
No
LIN USART 1 TX
MAIN_FLASH
No
Main Flash memory
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 131
MB96300 Series
Preliminary Specification
■ INTERRUPT VECTOR TABLE MB96(F)38x
Offset in
vector ta-
ble
Index in
ICR to pro-
gram
Vector
number
Clearedby
DMA
Vector name
Description
0
3FC
3F8
3F4
3F0
3EC
3E8
3E4
3E0
3DC
3D8
3D4
3D0
3CC
3C8
3C4
3C0
3BC
3B8
3B4
3B0
3AC
3A8
3A4
3A0
39C
398
394
390
38C
388
384
380
37C
CALLV0
CALLV1
CALLV2
CALLV3
CALLV4
CALLV5
CALLV6
CALLV7
RESET
INT9
No
No
-
1
-
2
No
-
3
No
-
4
No
-
5
No
-
6
No
-
7
No
-
8
No
-
9
No
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
EXCEPTION
NMI
No
-
No
-
Non-Maskable Interrupt
DLY
No
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Delayed Interrupt
RC_TIMER
MC_TIMER
SC_TIMER
RESERVED
EXTINT0
EXTINT1
EXTINT2
EXTINT3
EXTINT4
EXTINT5
EXTINT6
EXTINT7
CAN0
No
RC Timer
No
Main Clock Timer
No
Sub Clock Timer
No
Reserved
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
CAN Controller 0
CAN1
No
CAN Controller 1
PPG0
Yes
Yes
Yes
Yes
Yes
Yes
Programmable Pulse Generator 0
Programmable Pulse Generator 1
Programmable Pulse Generator 2
Programmable Pulse Generator 3
Programmable Pulse Generator 4
Programmable Pulse Generator 5
PPG1
PPG2
PPG3
PPG4
PPG5
132
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Offset in
vector ta-
ble
Index in
ICR to pro-
gram
Vector
number
Clearedby
DMA
Vector name
Description
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
378
374
370
36C
368
364
360
35C
358
354
350
34C
348
344
340
33C
338
334
330
32C
328
324
320
31C
318
314
310
30C
308
304
300
2FC
2F8
2F4
2F0
2EC
PPG6
PPG7
RLT0
RLT1
RLT2
RLT3
PPGRLT
ICU0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Programmable Pulse Generator 6
Programmable Pulse Generator 7
Reload Timer 0
Reload Timer 1
Reload Timer 2
Reload Timer 3
Reload Timer 6 - dedicated for PPG
Input Capture Unit 0
Input Capture Unit 1
Input Capture Unit 2
Input Capture Unit 3
Input Capture Unit 4
Input Capture Unit 5
Input Capture Unit 6
Input Capture Unit 7
Output Compare Unit 0
Output Compare Unit 1
Output Compare Unit 2
Output Compare Unit 3
Free Running Timer 0
Free Running Timer 1
Real Timer Clock
ICU1
ICU2
ICU3
ICU4
ICU5
ICU6
ICU7
OCU0
OCU1
OCU2
OCU3
FRT0
FRT1
RTC0
CAL0
SG0
No
Clock Calibration Unit
Sound Generator 0
Sound Generator 1
I2C interface
No
SG1
No
IIC0
Yes
Yes
No
ADC0
ALARM0
ALARM1
LINR0
LINT0
LINR1
LINT1
LINR2
LINT2
LINR4
A/D Converter
Alarm Comparator 0
Alarm Comparator 1
LIN USART 0 RX
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LIN USART 0 TX
LIN USART 1 RX
LIN USART 1 TX
LIN USART 2 RX
LIN USART 2 TX
LIN USART 4 RX
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 133
MB96300 Series
Preliminary Specification
Offset in
Vector
number
Index in
ICR to pro-
gram
Clearedby
DMA
vector ta-
ble
Vector name
Description
LIN USART 4 TX
69
70
71
72
2E8
2E4
2E0
2DC
LINT4
LINR5
Yes
Yes
Yes
No
69
70
71
72
LIN USART 5 RX
LINT5
LIN USART 5 TX
MAIN_FLASH
Main Flash memory interrupt
134
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Max
Parameter
Symbol
Unit
Remarks
Min
VCC
VSS - 0.3 VSS + 6.0
VSS - 0.3 VSS + 6.0
V
V
AVCC
VCC = AVCC *1
Power supply voltage
AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH > ΑVRL, AVRL ≥ ΑVSS
AVRH, AVRL VSS - 0.3 VSS + 6.0
V
DVCC
VI
VSS - 0.3 VSS + 6.0
VSS - 0.3 VSS + 6.0
VSS - 0.3 VSS + 6.0
V
V
V
*2
Input voltage
≤ (D)VCC + 0.3V *3
≤ (D)VCC + 0.3V *3
Output voltage
VO
Applicable to general purpose
I/O pins *4
Maximum Clamp Current
ICLAMP
-4.0
-
+4.0
40
mA
mA
Applicable to general purpose
I/O pins *4
Total Maximum Clamp Current
Σ|ICLAMP|
“L” level maximum output current
“L” level average output current
IOL1
IOLAV1
IOL2
-
15
5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
C
Normal outputs
Normal outputs
-
“L” level maximum output current
“L” level average output current
-
40
High current outputs
High current outputs
Normal outputs
IOLAV2
ΣIOL1
ΣIOL2
ΣIOLAV1
ΣIOLAV2
IOH1
-
30
“L” level maximum overall output current
“L” level maximum overall output current
“L” level average overall output current
“L” level average overall output current
“H” level maximum output current
“H” level average output current
“H” level maximum output current
“H” level average output current
“H” level maximum overall output current
“H” level maximum overall output current
“H” level average overall output current
“H” level average overall output current
Power consumption
-
100
330
50
-
High current outputs
Normal outputs
-
-
250
-15
-5
High current outputs
Normal outputs
-
IOHAV1
IOH2
-
Normal outputs
-
-40
-30
-100
-330
-50
-250
600
+70
+105
+125
High current outputs
High current outputs
Normal outputs
IOHAV2
ΣIOH1
ΣIOH2
ΣIOHAV1
ΣIOHAV2
PD
-
-
-
-
High current outputs
Normal outputs
-
High current outputs
MB96F348H/T
-
0
MB96V300
Operating temperature
TA
-40
-40
C
MB96F348H/T
C
other devices
Operating temperature at Flash erase/
write
TAF
-40
-55
+105
+150
C
C
Storage temperature
TSTG
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 135
MB96300 Series
Preliminary Specification
*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*2: If DVCC is powered before VCC, then SMC I/O pin state is undefined. To avoid this, we recommend to always
power VCC before DVCC. It is not necessary to set VCC and DVCC to the same value.
*3: VI and VO should not exceed (D)VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun
current to/from a input is limited by some means with external components, the ICLAMP rating supercedes the VI
rating. Input/output voltages of high current ports depend on DVCC, of other ports on VCC.
*4: • Applicable to all general purpose I/O pins (GP00_0 to GP17_7)
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Notethatifthe+Binputisappliedduringpower-on, thepowersupplyisprovidedfromthepinsandtheresulting
supply voltage may not be sufficient to operate the Power reset (except devices with persitant low voltage
reset in internal vector mode).
• When using the LCD controller, No +B signal must be applied to any LCD I/O pin (including unused
SEG/COM pins).
• Sample recommended circuits:
Protective Diode
VCC
Limiting
resistance
P-ch
N-ch
+B input (0V to 16V)
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
136
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
2. Recommended Conditions
Value
Typ
-
Parameter
Symbol
Unit
Remarks
Min
Max
Power supply voltage
VCC
CS
3.0
5.5
V
Smoothingcapacitorat
C pin
4.7
-
10
µF Use a X7R Ceramic Capacitor
0
-
-
-
+70
+105
+125
C
C
C
MB96V300
MB96F348H/T
Operating temperature
TA
-40
-40
MB96F3xx, MB963xx
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the devices electrical characteristics are warranted when the device is operated
within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU repre-
sentatives beforehand.
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 137
MB96300 Series
Preliminary Specification
3. DC characteristics
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
Port inputs if CMOS
Hysteresis0.8/0.2 in-
put is selected
0.8
VCC
(D)VCC
+ 0.3
VIHS08
-
-
-
V
Port inputs if CMOS
Hysteresis0.7/0.3 in-
put is selected
0.7
VCC
(D)VCC
+ 0.3
VIHS07
VIHSA
-
-
V
V
Port inputs if AUTO-
MOTIVE Hysteresis
input is selected
0.8
VCC
(D)VCC
+ 0.3
-
-
Input “H” voltage
Port inputs if TTL in-
put is selected
(D)VCC
+ 0.3
VIHTTL
VIHR
-
-
-
-
-
-
2.0
-
-
-
V
V
V
0.8
VCC
RSTX input pin
(CMOS Hysteresis)
VCC +
0.3
VCC -
0.3
VCC +
0.3
VIHM
MD input pin
Port inputs if CMOS
Hysteresis0.8/0.2 in-
put is selected
VSS -
0.3
0.2
VILS08
VILS07
VILSA
-
-
-
-
-
V
V
V
(D)VCC
Port inputs if CMOS
Hysteresis0.7/0.3 in-
put is selected
VSS -
0.3
0.3
(D)VCC
Port inputs if AUTO-
MOTIVE Hysteresis
input is selected
VSS -
0.3
0.5
(D)VCC
-
-
Input “L” voltage
VSS -
0.3
Port inputs if TTL in-
put is selected
VILTTL
VILR
-
-
-
-
-
-
-
-
-
0.8
V
V
V
VSS -
0.3
RSTX input pin
(CMOS Hysteresis)
0.2 VCC
VSS -
0.3
VSS +
0.3
VILM
MD input pin
138
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
4.5V≤ (D)VCC ≤ 5.5V
IOH = -2mA
Normal
and High
Current
outputs
Driving strength set
to 2mA
(D)VCC
- 0.5
VOH2
-
-
V
3.0V≤ (D)VCC < 4.5V
IOH = -1.6mA
4.5V≤ (D)VCC ≤ 5.5V
IOH = -5mA
Normal
and High
Current
outputs
Driving strength set
to 5mA
(D)VCC
- 0.5
VOH5
VOH30
VOH3
VOL2
VOL5
VOL30
VOL3
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
3.0V≤ (D)VCC < 4.5V
IOH = -3mA
Output“H”voltage
4.5V ≤ DVCC ≤ 5.5V
IOH = -30mA
High cur-
rent out-
puts
Driving strength set
to 30mA
DVCC -
0.5
-
3.0V ≤ DVCC < 4.5V
IOH = -20mA
4.5V ≤ VCC ≤ 5.5V
IOH = -3mA
VCC -
0.5
I2C outputs
-
3.0V ≤ VCC < 4.5V
IOH = -2mA
4.5V≤ (D)VCC ≤ 5.5V
IOL = +2mA
Normal
and High
Current
outputs
Driving strength set
to 2mA
-
-
-
-
0.4
0.4
0.4
0.4
3.0V≤ (D)VCC < 4.5V
IOL = +1.6mA
4.5V≤ (D)VCC ≤ 5.5V
IOL = +5mA
Normal
and High
Current
outputs
Driving strength set
to 5mA
3.0V≤ (D)VCC < 4.5V
IOL = +3mA
Output “L” voltage
4.5V ≤ DVCC ≤ 5.5V
IOL = +30mA
High cur-
rent out-
puts
Driving strength set
to 30mA
3.0V ≤ DVCC < 4.5V
IOL = +20mA
4.5V ≤ VCC ≤ 5.5V
IOL = +3mA
I2C outputs
3.0V ≤ VCC < 4.5V
IOL = +2mA
DVCC = VCC = 5.5V
VSS < VI < VCC
Input leak current
Pull-up resistance
IIL
GPnn_m
-1
-
+1
µA
kΩ
GPnn_m,
RSTX
RUP
-
25
50
100
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 139
MB96300 Series
Preliminary Specification
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
PLL Run mode
with CLKB =
CLKP1 = 56MHz,
CLKP2 = 28MHz
CLKMC, CLKRC and
CLKSC active
-
45
60
mA
PLL Run mode
with CLKB =
CLKP1 = CLKP2
= 24MHz
CLKMC, CLKRC and
CLKSC active
-
-
-
-
-
-
-
-
20
60
5
26
100
8
mA
ICCPLL
Writing/erasing
FLASH memory
in PLL Run mode
with CLKB =
CLKP1 = 56MHz,
CLKP2 = 28MHz
CLKMC, CLKRC and
CLKSC active, pro-
mA gramming of one
Flashmacroatatime
only
Main Run mode
with CLKB =
CLKP1 = CLKP2
= 4MHz
CLKPLL and CLKRC
stopped
mA
Writing/erasing
FLASH memory
inMainRunmode
with CLKB =
CLKP1 = CLKP2
= 4MHz
ICCMAIN
CLKPLL and CLKRC
stopped, program-
ming of one Flash
macro at a time only
20
3
48
6
mA
Power supply cur-
rent in Run
modes*
VCC
RC Run mode
with CLKB =
CLKP1 = CLKP2
= 2MHz
CLKMC, CLKPLL
mA
and CLKSC stopped
Writing/erasing
FLASH memory
in RC Run mode
with CLKB =
CLKP1 = CLKP2
= 2MHz
ICCRCH
CLKMC, CLKPLL
andCLKSCstopped,
mA programming of one
Flashmacroatatime
only
18
0.5
15.5
46
3.5
RC Run mode
with CLKB =
CLKP1 = CLKP2
= 100kHz
CLKMC, CLKPLL
mA
and CLKSC stopped
Writing/erasing
FLASH memory
in RC Run mode
with CLKB =
CLKP1 = CLKP2
= 100kHz
ICCRCL
CLKMC, CLKPLL
andCLKSCstopped,
43.5 mA programming of one
Flashmacroatatime
only
CLKMC, CLKPLL
andCLKRCstopped,
mA no Flash program-
ming/erasing al-
lowed.
Sub Run mode
with CLKB =
CLKP1 = CLKP2
= 32kHz
ICCSUB
-
0.15
2.5
140
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
PLL Sleep mode
with CLKP1 =
56MHz, CLKP2 =
28MHz, TA=+25˚C
CLKRC and CLKSC
stopped
ICCSPLL
-
10
15
mA
Main Sleep mode
with CLKP1 =
CLKP2 = 4MHz,
TA=+25˚C
CLKPLL CLKRC and
CLKSC stopped
ICCSMAIN
ICCSRCH
ICCSRCL
ICCSSUB
ICCTPLL
-
-
-
-
-
1.1
0.8
2
mA
mA
mA
mA
mA
RC Sleep mode
with CLKP1 =
CLKP2 = 2MHz,
TA=+25˚C
Power supply cur-
rent in Sleep
modes*
CLKMC, CLKPLL
and CLKSC stopped
VCC
1.5
0.7
0.2
2.5
RC Sleep mode
with CLKP1 =
CLKP2=100kHz,
TA=+25˚C
CLKMC, CLKPLL
and CLKSC stopped
0.35
0.08
1.5
Sub Sleep mode
with CLKP1 =
CLKP2 = 32kHz,
TA=+25˚C
CLKMC, CLKPLL
and CLKRC stopped
PLL Timer mode
with CLKMC =
4MHz, CLKPLL =
56MHz, TA=+25˚C
CLKRC and CLKSC
stopped
Main Timer mode
with CLKMC =
4MHz, TA=+25˚C
CLKPLL CLKRC and
CLKSC stopped
ICCTMAIN
ICCTRCH
-
-
0.35
0.35
0.6
0.6
mA
mA
Power supply cur-
rent in Timer
modes*
RC Timer mode
with CLKRC =
2MHz, TA=+25˚C
CLKMC, CLKPLL
and CLKSC stopped
VCC
RC Timer mode
with CLKRC =
100kHz,
CLKMC, CLKPLL
and CLKSC stopped
ICCTRCL
-
0.3
0.55 mA
0.15 mA
TA=+25˚C
Sub Timer mode
with CLKSC =
32kHz, TA=+25˚C
CLKMC, CLKPLL
and CLKRC stopped
ICCTSUB
ICCH
-
-
0.05
0.04
Power supply cur-
rent in Stop
mode*
At Stop Mode,
VCC
0.1
15
mA
pF
TA=+25˚C
Other than
C, AVCC,
AVSS,
Input capacitance
CIN
AVRH,
-
-
5
AVRL, VCC,
VSS, DVCC,
DVSS
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 141
MB96300 Series
Preliminary Specification
* The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a
32kHz external clock connected to the Sub oscillator, low voltage detector disabled.
Input/output voltages of high current ports depend on DVCC, of other ports on VCC.
Note: Certain devices of MB96F348 have a higher current consumption than stated in the table above:
• MB96F348HSA and MB96F348TWA: additional ~140 µA in all operation modes
• MB96F348HWA: additional ~280 µA in all operation modes
4. AC Characteristics
(1) Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
When using an oscilla-
tion circuit, PLL off
3
-
16
MHz
MHz
MHz
X0, X1
When using an oscilla-
tion circuit, PLL on
3.5
3
-
-
16
32
fC
When using an external
clock, PLL off
X0, X1
X0A, X1A
-
Clock frequency
When using an external
clock, PLL on
3.5
-
-
32
MHz
kHz
kHz
fCL
32.768
100
100
200
When using slow fre-
quency of RC oscillator
50
fCR
When using fast fre-
quency of RC oscillator
1
2
4
MHz
Duty ratio is about 30%
to 70%
PWH, PWL
PWHL, PWLL
tCR, tCF
X0
X0A
X0
10
5
-
-
-
-
-
ns
µs
ns
Input clock pulse width
When using external
clock
Input clock rise and falltime
-
5
Internal CPU clock frequen-
cy (Clock CLKB), internal
peripheral clock frequency
(Clock CLKP1)
fCLKB, fCLKP1
-
-
-
56
MHz
Internal peripheral clock fre-
quency (Clock CLKP2)
fCLKP2
tCP
-
-
-
-
-
32
-
MHz
ns
Internal operating clock cy-
cle time
16.125
(2) External Reset timing
TBD
142
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
(3) Power On Reset timing
TBD
(4) Clock Output timing
TBD
(5) External Bus timing
TBD
(6) USART timing
TBD
(7) External Interrupt timing
TBD
(8) Timer related resource input timing
TBD
(9) Timer related resource output timing
TBD
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 143
MB96300 Series
Preliminary Specification
(10) I2C Timing
TBD
144
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
5. A/D Converter
(TA = -40 ˚C to +125 ˚C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
-
Typ
Max
10
Resolution
-
-
-
-
-
-
-
-
-
bit
Total error
-3
+3
LSB
LSB
Nonlinearity error
-2.5
+2.5
Differential nonlineari-
ty error
-
-
-1.9
-
+1.9
LSB
LSB
AVRL - AVRL+ AVRL +
1.5 0.5 2.5
Zero reading voltage
VOT
ANn
Full scale reading
voltage
AVRH - AVRH - AVRH+
VFST
ANn
LSB
3.5
1.5
0.5
4.5V ≤ ΑVCC ≤ 5.5V
3.0V ≤ ΑVCC < 4.5V
4.5V ≤ ΑVCC ≤ 5.5V
3.0V ≤ ΑVCC < 4.5V
1.0
2.0
0.5
1.2
-1
-
-
-
-
-
-
16,500 µs
Compare time
Sampling time
-
-
-
-
-
-
µs
µs
µs
-
+1
+3
µA TA = 25 ˚C
µA TA = 125 ˚C
Analog port input cur-
rent
IAIN
ANn
ANn
-3
Analog input voltage
range
VAIN
AVRL
-
-
AVRH
AVcc
V
V
AVRH/
AVRH2
0.75
AVcc
AVRH
Reference voltage
range
0.25
AVCC
AVRL
IA
AVRL
AVcc
AVSS
-
2.5
-
V
-
-
-
-
5
5
1
5
mA AC Converter active
Power supply current
AD Converter not
operated
IAH
AVcc
µA
IR
AVRH
AVRH
0.7
-
mA AC Converter active
Reference voltage cur-
rent
AD Converter not
operated
IRH
µA
Offset between input
channels
-
ANn
-
-
TBD
LSB
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 145
MB96300 Series
Preliminary Specification
6. Low Voltage Detector
(TA = -40 ˚C to +125 ˚C, VCC = 3.0V - 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
Low voltage detec-
tor enabled
Power supply current
ICCLVD
VCC
-
70
100
µA
(RCR:LVDE=’1’)
7. Alarm Comparator
(TA = -40 ˚C to +125 ˚C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
Alarm comparator
enabled in fast
IA5ALMF
-
20
70
µA
mode (onechannel)
Alarm comparator
enabled in slow
mode (onechannel)
Power supply current
AVCC
IA5ALMS
-
-
3
-
10
5
µA
µA
Alarm comparator
disabled
IA5ALMH
8. LCD
TBD
146
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
■ EXAMPLE CHARACTERISTICS
TBD
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 147
MB96300 Series
Preliminary Specification
■ ORDERING INFORMATION
MCU with CAN controller
Satellite
flash
memory
Persistant
Subclock Low Volt-
age Reset
Part number
Package
Remarks
MB96F326YSA PMC-G(S)E2
MB96F326RSA PMC-G(S)E2
MB96F326YWA PMC-G(S)E2
MB96F326RWA PMC-G(S)E2
MB96F346YSA PQC-G(S)E2
MB96F346RSA PQC-G(S)E2
MB96F346YWA PQC-G(S)E2
MB96F346RWA PQC-G(S)E2
MB96F346YSA PMC-G(S)E2
MB96F346RSA PMC-G(S)E2
MB96F346YWA PMC-G(S)E2
MB96F346RWA PMC-G(S)E2
MB96F347YSA PQC-G(S)E2
MB96F347RSA PQC-G(S)E2
MB96F347YWA PQC-G(S)E2
MB96F347RWA PQC-G(S)E2
MB96F347YSA PMC-G(S)E2
MB96F347RSA PMC-G(S)E2
MB96F347YWA PMC-G(S)E2
MB96F347RWA PMC-G(S)E2
MB96F348YSA PQC-G(S)E2
MB96F348RSA PQC-G(S)E2
MB96F348YWA PQC-G(S)E2
MB96F348RWA PQC-G(S)E2
MB96F348YSA PMC-G(S)E2
MB96F348RSA PMC-G(S)E2
MB96F348YWA PMC-G(S)E2
MB96F348RWA PMC-G(S)E2
Yes
No
No
80 pin Plastic LQFP
(FPT-80P-M21)
No
Yes
Yes
No
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
No
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
No
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
No
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
148
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Satellite
flash
memory
Persistant
Subclock Low Volt-
age Reset
Part number
Package
Remarks
MB96F348TSA PQC-G(S)E2
MB96F348HSA PQC-G(S)E2
MB96F348TWA PQC-G(S)E2
MB96F348HWA PQC-G(S)E2
MB96F348TSA PMC-G(S)E2
MB96F348HSA PMC-G(S)E2
MB96F348TWA PMC-G(S)E2
MB96F348HWA PMC-G(S)E2
MB96F356YSA PMC-G(S)E2
MB96F356RSA PMC-G(S)E2
MB96F356YWA PMC-G(S)E2
MB96F356RWA PMC-G(S)E2
MB96F356YSA PMC1-G(S)E2
MB96F356RSA PMC1-G(S)E2
MB96F356YWA PMC1-G(S)E2
MB96F356RWA PMC1-G(S)E2
MB96F386YSA PMC-G(S)E2
MB96F386RSA PMC-G(S)E2
MB96F386YWA PMC-G(S)E2
MB96F386RWA PMC-G(S)E2
MB96F387YSA PMC-G(S)E2
MB96F387RSA PMC-G(S)E2
MB96F387YWA PMC-G(S)E2
MB96F387RWA PMC-G(S)E2
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
Yes
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
Yes
No
No
64 pin Plastic LQFP
(FPT-64P-M23)
Yes
Yes
No
No
Yes
No
No
64 pin Plastic LQFP
(FPT-64P-M24)
Yes
Yes
No
Yes
No
No
Yes
Yes
No
120 pin Plastic LQFP
(FPT-120P-M21)
No
Yes
No
No
Yes
Yes
No
Emulated
by ext.
RAM
416 pin Plastic BGA For evalua-
MB96V300RB-ES
Yes
No
(BGA416-M02)
tion
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 149
MB96300 Series
Preliminary Specification
MCU without CAN controller
Satellite
flash
Part number
Subclock
Package
Remarks
memory
MB96F326ASA PMC-G(S)E2
MB96F326AWA PMC-G(S)E2
MB96F346ASA PQC-G(S)E2
MB96F346AWA PQC-G(S)E2
MB96F346ASA PMC-G(S)E2
MB96F346AWA PMC-G(S)E2
MB96F347ASA PQC-G(S)E2
MB96F347AWA PQC-G(S)E2
MB96F347ASA PMC-G(S)E2
MB96F347AWA PMC-G(S)E2
MB96F348ASA PQC-G(S)E2
MB96F348AWA PQC-G(S)E2
MB96F348ASA PMC-G(S)E2
MB96F348AWA PMC-G(S)E2
MB96F348CSA PQC-G(S)E2
MB96F348CWA PQC-G(S)E2
MB96F348CSA PMC-G(S)E2
MB96F348CWA PMC-G(S)E2
MB96F356ASA PMC-G(S)E2
MB96F356AWA PMC-G(S)E2
MB96F356ASA PMC1-G(S)E2
MB96F356AWA PMC1-G(S)E2
No
Yes
No
80 pin Plastic LQFP
(FPT-80P-M21)
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
No
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
No
Yes
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
No
64 pin Plastic QFP
(FPT-64P-M23)
Yes
No
64 pin Plastic LQFP
(FPT-64P-M24)
Yes
150
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
■ Package dimensions of MB96(F)32x LQFP 80P
80-pin plastic LQFP
Lead pitch
0.50 mm
12 mm × 12 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.47 g
Code
(Reference)
P-LFQFP80-12×12-0.50
(FPT-80P-M21)
80-pin plastic LQFP
(FPT-80P-M21)
14.00±0.20(.551±.008)SQ
*
12.00±0.10(.472±.004)SQ
0.145±0.055
(.006±.002)
60
41
61
40
0.08(.003)
Details of "A" part
1.50 –+00..1200
(Mounting height)
.059 –+..000048
0.10±0.05
(.004±.002)
(Stand off)
INDEX
0˚~8˚
80
21
"A"
0.25(.010)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
1
20
LEAD No.
0.50(.020)
0.20±0.05
(.008±.002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 151
MB96300 Series
Preliminary Specification
■ PACKAGE DIMENSION MB96(F)34x LQFP 100P
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 mm × 14.0 mm
Gullwing
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
16.00±0.20(.630±.008)SQ
*
14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +–00..1200 .059 –+..000048
(Mounting height)
INDEX
0.10±0.10
(.004±.004)
(Stand off)
100
26
0˚~8˚
"A"
(0.50(.020))
0.25(.010)
0.60±0.15
(.024±.006)
1
25
0.50(.020)
0.20±0.05
(.008±.002)
0.145±0.055
(.0057±.0022)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2005 FUJITSU LIMITED F100031S-c-2-1
•
•
152
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
■ PACKAGE DIMENSION MB96(F)34x QFP 100P
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Gullwing
Lead shape
Sealing method
Mounting height
Plastic mold
3.35 mm MAX
P-QFP100-14×20-0.65
Code
(Reference)
(FPT-100P-M22)
100-pin plastic QFP
(FPT-100P-M22)
23.90±0.40(.941±.016)
*
20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
31
0.25(.010)
3.00 +–00..2305
.118 +–..000184
(Mounting height)
0~8˚
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.17±0.06
(.007±.002)
M
0.13(.005)
0.25±0.20
(.010±.008)
(Stand off)
0.80±0.20
(.031±.008)
"A"
0.88±0.15
(.035±.006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002 FUJITSU LIMITED F100008S-c-5-5
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 153
MB96300 Series
Preliminary Specification
■ PACKAGE DIMENSION MB96(F)35x LQFP 64P - M23
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
12 × 12 mm
package length
Lead shape
Gullwing
Sealing method
Mounting height
Plastic mold
1.70 mm MAX
P-LQFP64-12×12-0.65
Code
(Reference)
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M23)
14.00±0.20(.551±.008)SQ
*12.00±0.10(.472±.004)SQ
0.145±0.055
(.0057±.0022)
48
33
49
32
0.10(.004)
Details of "A" part
1.50 –+00..1200
(Mounting height)
.059 +–..000048
0.25(.010)
INDEX
0~8˚
64
17
0.50±0.20
(.020±.008)
0.10±0.10
(.004±.004)
(Stand off)
"A"
1
16
0.60±0.15
(.024±.006)
0.65(.026)
0.32±0.05
(.013±.002)
M
0.13(.005)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2003 FUJITSU LIMITED F64018S-c-3-5
154
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
■ PACKAGE DIMENSION MB96(F)35x LQFP 64P- M24
64-pin plastic LQFP
Lead pitch
0.50 mm
10.0 × 10.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.32 g
Code
(Reference)
(FPT-64P-M24)
P-LFQFP64-10×10-0.50
64-pin plastic LQFP
(FPT-64P-M24)
12.00±0.20(.472±.008)SQ
*
10.00±0.10(.394±.004)SQ
0.145±0.055
(.006±.002)
48
33
49
32
Details of "A" part
0.08(.003)
1.50 –+00..1200
(Mounting height)
.059 +–..000048
INDEX
0.10±0.10
(.004±.004)
(Stand off)
0˚~8˚
64
17
"A"
0.25(.010)
0.50±0.20
(.020±.008)
1
16
LEAD No.
0.60±0.15
(.024±.006)
0.50(.020)
0.20±0.05
(.008±.002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2005 FUJITSU LIMITED F64036S-c-1-1
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 155
MB96300 Series
Preliminary Specification
■ PACKAGE DIMENSION MB96(F)36x LQFP 48P
48-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
7 × 7 mm
package length
Lead shape
Sealing method
Mounting height
Weight
Gullwing
Plastic mold
1.70 mm MAX
0.17 g
Code
(Reference)
P-LFQFP48-7×7-0.50
(FPT-48P-M26)
48-pin plastic LQFP
(FPT-48P-M26)
9.00±0.20(.354±.008)SQ
+0.40
7.00 –0.10 .276 –+..000146 SQ
0.145±0.055
(.006±.002)
*
36
25
37
24
Details of "A" part
0.08(.003)
1.50 –+00..1200
.059 –+..000048
(Mounting height)
INDEX
48
13
0.10±0.10
(.004±.004)
(Stand off)
"A"
0˚~8˚
1
12
LEAD No.
0.50(.020)
0.25(.010)
0.20±0.05
M
0.08(.003)
(.008±.002)
0.60±0.15
(.024±.006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2003 FUJITSU LIMITED F48040S-c-2-2
156
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
■ PACKAGE DIMENSION MB96(F)38x LQFP 120P
120-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
16.0 × 16.0 mm
Gullwing
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.88 g
Code
(Reference)
P-LFQFP120-16×16-0.50
(FPT-120P-M21)
120-pin plastic LQFP
(FPT-120P-M21)
18.00±0.20(.709±.008)SQ
+0.40
16.00 –0.10
.630 +–..000146 SQ
*
90
61
91
60
0.08(.003)
Details of "A" part
1.50 –+00..1200
.059 –+..000048
(Mounting height)
INDEX
0~8˚
"A"
120
31
0.10±0.05
(.004±.002)
(Stand off)
1
30
LEAD No.
0.145 +–00..0035
0.60±0.15
(.024±.006)
0.22±0.05
(.009±.002)
M
0.50(.020)
0.08(.003)
.006 +–..000012
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002 FUJITSU LIMITED F120033S-c-4-4
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 157
MB96300 Series
Preliminary Specification
■ Revision History
Revision
11
Date
Modification
2006-09-27
2006-09-27
“Description” and “Features”: “64MHz” replaced by “up to 64MHz”
11
“Pin Description”: New circuit type “N” for I2C pins added. Cicruit types I, J, K
and L: driving strength corrected from 4mA to 5/2mA
11
11
11
11
12
12
2006-09-27
2006-09-29
2006-10-01
2006-10-04
2006-11-01
2006-11-01
“AD Converter”: Conversion and Sampling time definitions added
Electrical characteristics updated
In Memory map: bank configuration record are added
MB96(F)38X pin description: Pin 93 and pin 103 corrected
INT3_R1 function added, INTxR function renamed to INTx_R
Electrical characteristics for RC clock modes updated (reduced values). Note for
additional current of certain MB96F348 devices added
12
2006-11-15
changed max. frequence on cover page and feature list from 64MHz/15.6ns to
56MHz / 17.8ns to avoid confusion
13
13
2006-11-29
2006-12-07
Made PLL unlock interrupt RESERVED.
C-Pin Capacitor spec added (4.7-10uF X7R cap); Bank0/1 Flash -> Main/Sat
Flash, ICC values slightly modified after corner sample review.
13
13
13
13
13
14
15
15
2006-12-11
2006-12-11
2006-12-11
2006-12-11
2006-12-11
2006-12-12
2006-12-13
2006-12-13
F35X: 2 -> 4 UARTS, 0 -> 1 Real time clock
IAIN=3uA max at high temp
Max operating temperature for Flash erase/write 105 deg, 10.000 cycles
64 pin package is “FPT-64P-M09” (wrong package was stated in lineup)
All reloacated pin functions renamed from xxxR to xxx_R
Removed small RAM size devices from RAMSTART table.
Ordering information: All part numbers changed from “-HE2” to “E2”
Block diagrams corrected: External bus pin names corrected, mode pins added,
clock output pin names corrected. External bus address name changed: A0-A23 ->
A00 - A23, AD0 - AD7 -> AD00 - AD07.
16
2007-01-22
Added MB96320. Modified pin-out and interrupt vector table of MB9635x.
Modified pin out of MB9636x.
17
17
2007-01-23
2007-01-26
Added package dimension MB96(F)356 LQFP 64P - M24
Updated product line-up.
Added MB96F326 and MB96F356 ordering information
18
2007-01-29
Corrected ordering information: MB96F326 PQC -> MB96F326 PMC
158
FME/EMDC- 2007-02-12
MB96300_shortspec.fm
Preliminary Specification
MB96300
Revision
19
Date
Modification
2007-02-07
added MB96384, MB96385 to product lineup
added line for ADC-Reference switch to product line up
Pinout MB96(F)38x: added exception for MB96384/5
20
2007-02-12
Features: added 80-pin
Product line up: removed MB96xxxA
fixed formating for RTC
Pin description MB96(F)326...: TTG10_R -> TTG11_R
IO-Map: removed DMA-Turbo Register
FME/EMDC- 2007-02-12
MB96300_shortspec.fm 159
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