MBM29DL400BC-55PBT [FUJITSU]
Flash, 256KX16, 55ns, PBGA48, PLASTIC, FBGA-48;型号: | MBM29DL400BC-55PBT |
厂家: | FUJITSU |
描述: | Flash, 256KX16, 55ns, PBGA48, PLASTIC, FBGA-48 |
文件: | 总56页 (文件大小:525K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20866-2E
FLASH MEMORY
CMOS
4M (512K × 8/256K × 16) BIT
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
■ FEATURES
• Single 3.0 V read, program, and erase
Minimizes system level power requirements
• Simultaneous operations
Read-while-Erase or Read-while-Program
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts (Pin compatible with MBM29LV400TC/BC)
48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
• Minimum 100,000 program/erase cycles
• High performance
55 ns maximum access time
• Sector erase architecture
Two 16K byte, four 8K bytes, two 32K byte, and six 64K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
(Continued)
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
(Continued)
• Sector protection
Hardware method disables any combination of sectors from program or erase operations
• Sector Protection Set function by Extended sector protection command
• Fast Programming Function by Extended Command
• Temporary sector unprotection
Temporary sector unprotection via the RESET pin.
■ PACKAGE
48-pin plastic TSOP (I)
48-pin plastic TSOP (I)
Marking Side
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
2
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
■ GENERAL DESCRIPTION
The MBM29DL400TC/BC are a 4M-bit, 3.0 V-only Flash memory organized as 512K bytes of 8 bits each or
256K words of 16 bits each. The MBM29DL400TC/BC are offered in a 48-pin TSOP(I) package. These devices
are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC
are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM
programmers.
MBM29DL400TC/BC provides simultaneous operation which can read a data while program/erase. The
simultaneous operation architecture provides simultaneous operation by dividing the memory space into two
banks. The device can allow a host system to program or erase in one bank, then immediately and simultaneously
read from the other bank.
The standard MBM29DL400TC/BC offer access times 55 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The MBM29DL400TC/BC are pin and command set compatible with JEDEC standard E2PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29DL400TC/BC are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29DL400TC/BC are erased when shipped from the
factory.
The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the devices internally reset to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29DL400TC/BC memories electrically erase the entire chip
or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one
byte/word at a time using the EPROM programming mechanism of hot electron injection.
3
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
• Two 16K bytes, four 8K bytes, two 32K bytes, and six 64K bytes
• Individual-sector, multiple-sector, or bulk-erase capability
• Individual or multiple-sector protection is user definable.
(X8)
(X16)
(X8)
(X16)
7FFFFH 3FFFFH
7C000H 3E000H
74000H 3A000H
72000H 39000H
70000H 38000H
6E000H 37000H
6C000H 36000H
64000H 32000H
60000H 30000H
50000H 28000H
40000H 20000H
30000H 18000H
20000H 10000H
10000H 08000H
00000H 00000H
7FFFFH 3FFFFH
70000H 38000H
60000H 30000H
50000H 28000H
40000H 20000H
30000H 18000H
20000H 10000H
1C000H 0C000H
14000H 0A000H
12000H 09000H
10000H 08000H
0E000H 07000H
0C000H 06000H
04000H 02000H
00000H 00000H
16K byte/8K word
32K byte/16K word
8K byte/4K word
8K byte/4K word
8K byte/4K word
8K byte/4K word
32K byte/16K word
16K byte/8K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
16K byte/8K word
32K byte/16K word
8K byte/4K word
8K byte/4K word
8K byte/4K word
8K byte/4K word
32K byte/16K word
16K byte/8K word
bank 2
bank 1
bank 1
bank 2
MBM29DL400TC Sector Architecture
MBM29DL400BC Sector Architecture
4
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
■ PRODUCT LINE UP
Part No.
VCC = 3.3 V
MBM29DL400TC/MBM29DL400BC
+0.3 V
–0.3 V
-55
-70
—
—
Ordering Part No.
+0.6 V
–0.3 V
VCC = 3.0 V
—
55
55
30
—
70
70
30
-90
90
90
35
-12
120
120
50
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
■ BLOCK DIAGRAM
V CC
V SS
Bank 2 Address
Cell Matrix
(Bank 2)
A0 to A17
(A-1)
X-Decoder
RY/BY
RESET
WE
State
Control
Status
.
DQ 0 to DQ 15
CE
Command
Register
OE
BYTE
DQ 0 to DQ 15
X-Decoder
Bank 1 Address
Cell Matrix
(Bank 1)
5
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
■ CONNECTION DIAGRAMS
TSOP(I)
A15
A14
A13
A12
A11
A10
A9
A8
1
2
3
4
5
6
7
8
A16
BYTE
VSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
(Marking Side)
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
N.C.
N.C.
WE
RESET
N.C.
N.C.
RY/BY
N.C.
A17
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MBM29DL400TC/MBM29DL400BC
Standard Pinout
A7
A6
A5
A4
A3
A2
A1
VSS
CE
A0
FPT-48P-M19
A1
A2
A3
A4
A5
A6
A7
A17
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A0
CE
VSS
OE
(Marking Side)
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
N.C.
RY/BY
N.C.
N.C.
RESET
WE
N.C.
N.C.
A8
MBM29DL400TC/MBM29DL400BC
Reverse Pinout
A9
A10
A11
A12
A13
A14
A15
BYTE
A16
FPT-48P-M20
6
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
■ LOGIC SYMBOL
Table 1 MBM29DL400TC/BC Pin Configuration
Pin
A-1, A0 to A17
DQ0 to DQ15
CE
Function
Address Inputs
A-1
Data Inputs/Outputs
Chip Enable
18
A0 to A17
16 or 8
DQ0 to DQ15
OE
Output Enable
WE
Write Enable
CE
OE
WE
RY/BY
Ready/Busy Output
Hardware Reset Pin/Temporary Sector
Unprotection
RY/BY
RESET
BYTE
RESET
BYTE
N.C.
VSS
Selects 8-bit or 16-bit mode
No Internal Connection
Device Ground
VCC
Device Power Supply
7
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Table 2 MBM29DL400TC/BC User Bus Operations (BYTE = VIH)
Operation
Auto-Select Manufacturer Code (1)
Auto-Select Device Code (1)
Read (3)
CE OE WE
A0
L
A1
L
A6
L
A9
VID
VID
A9
X
DQ0 to DQ15 RESET
L
L
L
H
L
L
L
L
X
X
L
L
H
H
H
X
H
L
Code
Code
DOUT
H
H
H
H
H
H
H
H
VID
L
H
A0
X
L
L
L
A1
X
A6
X
X
A6
L
Standby
X
H
H
VID
L
HIGH-Z
HIGH-Z
DIN
Output Disable
X
X
X
Write (Program/Erase)
Enable Sector Protection (2), (4)
Verify Sector Protection (2), (4)
Temporary Sector Unprotection (5)
Reset (Hardware)/Standby
A0
L
A1
H
H
X
A9
VID
VID
X
X
H
X
X
L
L
Code
X
X
X
X
X
X
X
X
X
HIGH-Z
Table 3 MBM29DL400TC/BC User Bus Operations (BYTE = VIL)
DQ15/
Operation
CE
OE WE
A0
A1
A6
A9 DQ0 to DQ7 RESET
A-1
Auto-Select Manufacturer Code (1)
Auto-Select Device Code (1)
Read (3)
L
L
L
H
L
L
L
L
X
X
L
L
H
H
H
X
H
L
L
L
H
A0
X
X
A0
L
L
L
L
L
VID
VID
A9
X
Code
Code
DOUT
H
H
H
H
H
H
H
H
VID
L
L
L
A-1
X
A1
X
A6
X
X
A6
L
Standby
X
H
H
VID
L
HIGH-Z
HIGH-Z
DIN
Output Disable
X
X
X
Write (Program/Erase)
Enable Sector Protection (2), (4)
Verify Sector Protection (2), (4)
Temporary Sector Unprotection (5)
Reset (Hardware)/Standby
A-1
L
A1
H
H
X
A9
VID
VID
X
X
H
X
X
L
L
L
Code
X
X
X
X
X
X
X
X
X
X
X
HIGH-Z
Legend: L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See DC Characteristics for voltage levels.
Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See
Table 8.
2. Refer to the section on Sector Protection.
3. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
4. VCC = 3.3 V ± 10%
5. It is also used for the extended sector protection.
8
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
■ ORDERING INFORMATION
Standard Products
Fujitsu standard products are available in several packages. The order number is formed by a combination of:
MBM29DL400
T
C
-55
PFTN
PACKAGE TYPE
PFTN = 48-Pin Thin Small Outline Package
(TSOP) Standard Pinout
PFTR = 48-Pin Thin Small Outline Package
(TSOP) Reverse Pinout
SPEED OPTION
See Product Selector Guide
Device Revision
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
MBM29DL400
4Mega-bit (512K × 8-Bit or 256K × 16-Bit) CMOS Flash Memory
3.0 V-only Read, Program, and Erase
9
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
■ FUNCTIONAL DESCRIPTION
Simultaneous Operation
MBM29DL400TC/BC have feature, which is capability of reading data from one bank of memory while a program
or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the
conventional features (read, program, erase, erase-suspend read, and erase-suspend program). The bank
selection can be selected by bank address (A16, A17) with zero latency.
The MBM29DL400TC/BC have two banks which contain Bank 1 (16KB, 32KB, 8KB, 8KB, 8KB, 8KB, 32KB, and
16KB) and Bank 2 (64KB × six sectors).
The simultaneous operation can not execute multi-function mode in the same bank. Table 4 shows combination
to be possible for simultaneous operation.
Table 4 Simultaneous Operation
Case
Bank 1 Status
Read mode
Bank 2 Status
Read mode
1
2
3
4
5
6
7
Read mode
Autoselect mode
Program mode
Erase mode *
Read mode
Read mode
Read mode
Autoselect mode
Program mode
Erase mode *
Read mode
Read mode
*: An erase operation may also be supended to read from or program to a sector not being erased.
Read Mode
TheMBM29DL400TC/BChavetwocontrolfunctionswhichmustbesatisfiedinordertoobtaindataattheoutputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”
Standby Mode
There are two ways to implement the standby mode on the MBM29DL400TC/BC devices, one using both the
CE and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.
Under this condition the current consumed is less than 5 µA max. During Embedded Algorithm operation, VCC
active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either
of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE
= “H” or “L”). Under this condition the current is consumed is less than 5 µA max. Once the RESET pin is taken
high, the device requires tRH of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
10
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29DL400TC/BC data. This mode can be used effectively with an application requested low power
consumption such as handy terminals.
To activate this mode, MBM29DL400TC/BC automatically switch themselves to low power mode when
MBM29DL400TC/BC addresses remain stably during access fine of 150 ns. It is not necessary to control CE,
WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level).
During simultaneous operation, VCC active current (ICC2) is required.
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29DL400TC/BC read-out the data for changed addresses.
Output Disable
With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the devices.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All
addresses are DON’T CARES except A0, A1, and A6 (A-1). (See Tables 2 and 3.)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29DL400TC/BC are erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in Table 8. (Refer to Autoselect Command section.)
Word 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04H) and word 1 (A0 = VIH) represents the device
identifier code (MBM29DL400TC = 0CH and MBM29DL400BC = 0FH for ×8 mode; MBM29DL400TC = 220CH
and MBM29DL400BC = 220FH for ×16 mode). These two bytes/words are given in the tables 5.1 and 5.2. All
identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read
the proper device codes when executing the autoselect, A1 must be VIL. (See Tables 5.1 and 5.2.)
In case of applying VID on A9, since both Bank 1 and Bank 2 enters Autoselect mode, the simultenous operation
can not be executed.
11
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Table 5 .1 MBM29DL400TC/BC Sector Protection Verify Autoselect Codes
*1
Type
Manufacture’s Code
A12 to A17
A6
A1
A0
Code (HEX)
04H
A-1
VIL
VIL
X
X
VIL
VIL
VIL
Byte
Word
Byte
0CH
MBM29DL400TC
MBM29DL400BC
X
X
VIL
VIL
VIH
220CH
0FH
Device Code
VIL
X
VIL
VIL
VIL
VIH
VIH
VIL
Word
220FH
Sector
Addresses
01H*2
Sector Protection
VIL
*1: A-1 is for Byte mode.
*2: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.
Table 5 .2 Expanded Autoselect Code Table
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Type
Code
A-1/0
Manufacturer’s Code
04H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
(B) 0CH A-1
MBM29DL400TC
(W) 220CH
0
0
1
0
0
0
1
0
Device
Code
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
(B) 0FH A-1
MBM29DL400BC
(W) 220FH
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
A-1/0
Sector Protection
01H
(B): Byte mode
(W): Word mode
12
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Protection
The MBM29DL400TC/BC feature hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 13). The sector protection feature is enabled using programming
equipment at the user’s site. The devices are shipped with all sectors unprotected. Alternatively, Fujitsu may
program and protect sectors in the factory prior to shiping the device.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID = 11.5 V), CE = VIL, and A0 = A6 = VIL, A1 = VIH. The sector addresses (A17, A16, A15, A14, A13, and A12) should
be set to the sector to be protected. Tables 6 and 7 define the sector address for each of the forteen (14)
individual sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is
terminated with the rising edge of the same. Sector addresses must be held constant during the WE pulse. See
Figures 16 and 25 for sector protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A17, A16, A15, A14, A13, and A12) while (A6,
A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the
devices will read 00H for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6
are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes.
A-1 requires to apply to VIL on byte mode.
It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing
a read operation at the address location XX02H, where the higher order addresses (A17, A16, A15, A14, A13, and
A12) are the desired sector address will produce a logical “1” at DQ0 for a protected sector. See Tables 5.1 and
5.2 for Autoselect codes.
Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29DL400TC/BC devices
in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage
(12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector
addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected
again. See Figures 17 and 26.
13
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
RESET
Hardware Reset
The MBM29DL400TC/BC devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20 µs after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional tRH before it will allow read access. When the RESET pin is low, the devices will
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 12 for the timing
diagram. Refer to Temporary Sector Unprotection for additional functionality.
14
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Table 6 Sector Address Tables (MBM29DL400TC)
Sector Address
Sector Size
(X 8)
Address Range
(X 16)
Address Range
Bank
Bank Sector
(K bytes/
K words)
Address
A17 A16 A15 A14 A13 A12
SA0
SA1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
0
0
1
1
1
0
0
0
1
1
X
X
X
X
X
X
0
1
0
1
1
0
0
1
0
1
X
X
X
X
X
X
X
64/32
64/32
64/32
64/32
64/32
64/32
16/8
00000H to 0FFFFH
10000H to 1FFFFH
20000H to 2FFFFH
30000H to 3FFFFH
40000H to 4FFFFH
50000H to 5FFFFH
60000H to 63FFFH
00000H to 07FFFH
08000H to 0FFFFH
10000H to 17FFFH
18000H to 1FFFFH
20000H to 27FFFH
28000H to 2FFFFH
30000H to 31FFFH
SA2
Bank 2
SA3
SA4
SA5
SA6
64000H to 67FFFH
68000H to 6BFFFH
32000H to 33FFFH
34000H to 35FFFH
SA7
1
1
0
X
32/16
SA8
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
8/4
8/4
8/4
8/4
6C000H to 6DFFFH
6E000H to 6FFFFH
70000H to 71FFFH
72000H to 73FFFH
36000H to 36FFFH
37000H to 37FFFH
38000H to 38FFFH
39000H to 39FFFH
SA9
Bank 1
SA10
SA11
SA12
SA13
74000H to 77FFFH
78000H to 7BFFFH
3A000H to 3BFFFH
3C000H to 3DFFFH
1
1
1
1
1
1
X
X
32/16
16/8
7C000H to 7FFFFH
3E000H to 3FFFFH
Note: The address range is A17: A-1 if in byte mode (BYTE = VIL). The address range is A17: A0 if in word mode
(BYTE = VIH).
15
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Table 7 Sector Address Tables (MBM29DL400BC)
Sector Address
Sector Size
(×8)
(×16)
Address Range
Bank
Bank Sector
(Kbytes/
Kwords)
Address
Address Range
A17 A16 A15 A14 A13 A12
SA13
SA12
1
1
1
1
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
1
1
0
0
0
1
1
1
0
0
X
X
X
X
X
X
1
0
1
0
0
1
1
0
1
0
X
X
X
X
X
X
X
X
X
1
64/32
64/32
64/32
64/32
64/32
64/32
16/8
70000H to 7FFFFH 38000H to 3FFFFH
60000H to 6FFFFH 30000H to 37FFFH
50000H to 5FFFFH 28000H to 2FFFFH
40000H to 4FFFFH 20000H to 27FFFH
30000H to 3FFFFH 18000H to 1FFFFH
20000H to 2FFFFH 10000H to 17FFFH
1C000H to 1FFFFH 0E000H to 0FFFFH
SA11
Bank 2
SA10
SA9
SA8
SA7
14000H to 17FFFH, 0A000H to 0BFFFH,
18000H to 1BFFFH 0C000H to 0DFFFH
SA6
SA5
0
0
1
32/16
0
0
0
0
0
0
0
0
1
1
0
0
8/4
8/4
8/4
8/4
12000H to 13FFFH
10000H to 11FFFH
09000H to 09FFFH
08000H to 08FFFH
SA4
Bank 1
0
SA3
1
0E000H to 0FFFFH 07000H to 07FFFH
0C000H to 0DFFFH 06000H to 06FFFH
SA2
SA1
SA0
0
X
X
X
08000H to 0BFFFH, 04000H to 05FFFH,
0
0
0
0
0
0
32/16
16/8
04000H to 07FFFH
02000H to 03FFFH
00000H to 03FFFH
00000H to 01FFFH
Note: The address range is A17: A-1 if in byte mode (BYTE = VIL). The address range is A17: A0 if in word mode
(BYTE = VIH).
16
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Table 8 MBM29DL400TC/BC Command Definitions
Fourth Bus
First Bus Second Bus Third Bus
Write Cycle Write Cycle Write Cycle
Fifth Bus
Sixth Bus
Bus
Write
Cycles
Req’d
Read/Write
Cycle
Command
Sequence
Write Cycle Write Cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Word
Read/Reset
Read/Reset
1
3
XXXH F0H
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Byte
Word
Byte
555H
AAH
2AAH
555H
555H
55H
F0H
RA
RD
AAAH
AAAH
(BA)
555H
Word
Byte
555H
AAH
AAAH
2AAH
555H
Autoselect
3
55H
90H
—
—
—
—
—
—
—
—
(BA)
AAAH
Word
Byte
Word
Byte
Word
Byte
555H
AAH
2AAH
555H
2AAH
555H
2AAH
555H
—
555H
AAAH
555H
AAAH
555H
AAAH
—
Program
4
6
6
55H
55H
55H
A0H
80H
80H
PA
PD
—
—
AAAH
555H
AAH
555H
AAAH
555H
AAAH
—
2AAH
555H
2AAH
555H
—
555H
Chip Erase
Sector Erase
AAH
AAH
55H
55H
10H
30H
AAAH
AAAH
555H
AAH
SA
AAAH
Erase Suspend
Erase Resume
1
1
BA
BA
B0H
30H
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Word
555H
AAAH
XXXH
XXXH
BA
2AAH
555H
555H
AAAH
Set to
3
2
2
4
AAH
A0H
90H
55H
PD
20H
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Fast Mode
Byte
Word
Byte
Word
Byte
Word
Byte
Fast
Program *
PA
—
—
XXXH
XXXH
Reset from
Fast Mode *
F0H
—
BA
Extended
Sector
Protect
XXXH 60H SPA 60H SPA 40H SPA SD
Notes: 1. Address bits A11 to A17 = X = “H” or “L” for all address commands except or Program Address (PA), Sector
Address (SA), and Bank Address (BA).
2. Bus operations are defined in Tables 2 and 3.
3. RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
BA = Bank Address (A16 to A17)
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.
5. SPA =Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0).
SD = Sector protection verify data. Output 01H at protected sector addresses and output 00H at
unprotected sector addresses.
* : This command is valid while Fast Mode.
6. The system should generate the following address patterns:
Word Mode: 555H or 2AAH to addresses A0 to A10
Byte Mode: AAAH or 555H to addresses A–1 and A0 to A10
7. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
17
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the
read mode. Some commands are required Bank Address (BA) input. When command sequences are inputed
to bank being read, the commands have priority than reading. Table 8 defines the valid register command
sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally equivalent,
resetting the device to the read mode. Please note that commands are always written at DQ0 to DQ7 and DQ8
to DQ15 bits are ignored.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/
Reset operation is initiated by writing the Read/Reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the
command register contents are altered.
The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures
that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
The Autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write
cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device
codes can be read from the bank, and an actual data of memory cell can be read from the another bank.
Following the command write, a read cycle from address (BA)00H retrieves the manufacture code of 04H. A
read cycle from address (BA)01H for ×16((BA)02H for ×8) returns the device code (MBM29DL400TC = 0CH
and MBM29DL400BC = 0FH for ×8 mode; MBM29DL400TC = 220CH and MBM29DL400BC = 220FH for ×16
mode). (See Tables 5.1 and 5.2.)
All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Sector state (protection
or unprotection) will be informed by address (BA)02H for ×16 ((BA)04H for ×8). Scanning the sector addresses
(A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a
protected sector. The programming verification should be performed by verify sector protection on the protected
sector. (See Tables 2 and 3.)
The manufacture and device codes can be allowed reading from selected bank. To read the manufacture and
device codes and sector protection status from non-selected bank, it is necessary to write Read/Reset command
sequence into the register and then Autoselect command should be written into the bank to be read.
If the software (program code) for Autoselect command is stored into the Frash memory, the device and
manufacture codes should be read from the other bank where is not contain the software.
18
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.
Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,
the system is not required to provide further controls or timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.
The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit),
or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bitatwhichtimethedevicesreturntothereadmodeandaddressesarenolongerlatched. (SeeTable9, Hardware
Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by the system
at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 21 illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or
RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command
sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the
device returns to read the mode.
Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
Figure 22 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
19
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever
happens later, while the command (Data=30H) is latched on the rising edge of CE or WE which happens first.
Aftertime-outof50µsfromtherisingedgeofthelastsectorerasecommand, thesectoreraseoperationwillbegin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 8. This sequence
is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than 50 µs otherwise that command will not be accepted and
erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs
from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase
command(s). If another falling edge of CE or WE, whichever happens first occurs within the 50 µs time-out
window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section
DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period
will reset the devices to the read mode, ignoring the previous command string. Resetting the devices once
execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow
them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the
sector erase buffer may be done in any sequence and with any number of sectors (0 to 13).
Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or
RY/BY.
The sector erase begins after the 50 µs time out from the rising edge of CE or WE whichever happens first for
the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status
section.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at
an address within any of the sectors being erased.
Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] × Number of Sector
Erase
In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not performe.
Figure 22 illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
(B0H) during the Sector Erase time-out results in immediate termination of the time-out period and suspension
of the erase operation.
Writing the Erase Resume command (30H) resumes the erase operation. The bank addresses of sector being
erasing or suspending should be set when writting the Erase Suspend or Erase Resume command.
20
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/
BY output pin will be at Hi-Z and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use
the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been
suspended. Further writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-
suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I
(DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address
while DQ6 can be read from any address within bank being erase-suspended.
To resume the operation of Sector Erase, the Resume command (30H) should be written to the bank being erase
suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend
command can be written after the chip has resumed erasing.
Extended Command
(1) Fast Mode
MBM29DL400TC/BC has Fast Mode function. This mode dispenses with the initial two unclock cycles
required in the standard program command sequence by writing Fast Mode command into the command
register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in
standardprogramcommand. (Donotwriteerasecommandinthismode.)Thereadoperationisalsoexecuted
after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command
register. The first cycle must contain the bank address. (Refer to the Figure 28 Extended algorithm.) The
VCC active current is required even CE = VIH during Fast Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to
the Figure 28 Extended algorithm.)
(3) Extended Sector Protection
In addition to normal sector protection, the MBM29DL400TC/BC has Extended Sector Protection as
extended function. This function enable to protect sector by forcing VID on RESET pin and write a commnad
sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins.
The only RESET pin requires VID for sector protection in this mode. The extended sector protect requires
VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60H) into
the command register. Then, the sector addresses pins (A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0,
1, 0) should be set to the sector to be protected (recommend to set VIL for the other addresses pins), and
write extended sector protect command (60H). A sector is typically protected in 150 µs. To verify programming
of the protection circuitry, the sector addresses pins (A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1,
0) should be set and write a command (40H). Following the command write, a logical “1” at device output
DQ0 will produce for protected sector in the read operation. If the output data is logical “0”, please repeat to
write extended sector protect command (60H) again. To terminate the operation, it is necessary to set RESET
pin to VIH.
21
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Write Operation Status
Detailed in Table 9 are all the status flags that can determine the status of the bank for the current mode operation.
The read operation from the bank where is not operate Embedded Algorithm returns a data of memory cell.
These bits offer a method for determining whether a Embedded Algorithm is completed properly. The information
on DQ2 is address sensitive. This means that if an address from an erasing sector is consectively read, then the
DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consectively read.
This allows the user to determine which sectors are erasing and which are not.
The status flag is not output from bank (non-busy bank) not executing Embedded Algorithm. For example, there
is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1] <busy bank>,
[2] <non-busy bank>, [3] <busy bank>, the DQ6 is toggling in the case of [1] and [3]. In case of [2], the data of
memory cell is outputted. In the erase-suspend read mode with the same read sequence, DQ6 will not be toggled
in the [1] and [3].
In the erase suspend read mode, DQ2 is toggled in the [1] and [3]. In case of [2], the data of memory cell is
outputted.
Table 9 Hardware Sequence Flags
Status
DQ7
DQ6
DQ5 DQ3
DQ2
Embedded Program Algorithm
DQ7 Toggle
0
0
0
1
1
Toggle
(Note 1)
Embedded Erase Algorithm
0
1
Toggle
1
Erase Suspend Read
(Erase Suspended Sector)
0
0
Toggle
In Progress
Erase
Erase Suspend Read
Suspended
Data Data Data Data Data
1
(Non-Erase Suspended Sector)
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ7 Toggle
DQ7 Toggle
0
0
(Note 1)
Embedded Program Algorithm
Embedded Erase Algorithm
1
1
0
1
1
0
Toggle
N/A
Exceeded
Time Limits
Erase
Erase Suspend Program
Suspended
DQ7 Toggle
1
0
N/A
(Non-Erase Suspended Sector)
Mode
Notes: 1. Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from
non-erase suspend sector address will indicate logic “1” at the DQ2 bit.
2. DQ0 and DQ1 are reserve pins for future use.
3. DQ4 is Fujitsu internal use only.
22
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
DQ7
Data Polling
The MBM29DL400TC/BC devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in Figure 23.
For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse
sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid.
If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ7 is active for approximately 100 µs, then the bank returns to read mode.
Once the Embedded Algorithm operation is close to being completed, the MBM29DL400TC/BC data pins (DQ7)
may change asynchronously while the output enable (OE) is asserted low. This means that the devices are
driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time.
Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device
has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6
may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts.
TheDataPollingfeatureisonlyactiveduringtheEmbeddedProgrammingAlgorithm, EmbeddedEraseAlgorithm
or sector erase time-out. (See Table 9.)
See Figure 9 for the Data Polling timing specifications and diagrams.
DQ6
Toggle Bit I
The MBM29DL400TC/BC also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ6 to toggle.
23
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
The system can use DQ6 to determine whether a sector is actively erasing or is erase-suspended. When a bank
is actively erasing (that is, the Embedded Erase Algorithm is in progress), DQ6 toggles. When a bank enters the
Erase Suspend mode, DQ6 stops toggling. Successive read cycles during the erase-suspend-program cause
DQ6 to toggle.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
See Figure 10 for the Toggle Bit I timing specifications and diagrams.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the devices under this
condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).
The OE and WE pins will control the output disable functions as described in Tables 2 and 3.
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the
DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly
used. If this occurs, reset the device with command sequence.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on
the second status check, the command may not have been accepted.
See Table 9: Hardware Sequence Flags.
DQ2
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows:
24
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also Table 9 and Figure 19.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from an erasing sector.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
Mode
DQ7
DQ7
0
DQ6
DQ2
1
Program
Erase
Toggle
Toggle
Toggle (Note)
Erase-Suspend Read
(Erase-Suspended Sector)
(Note 1)
1
1
Toggle
Erase-Suspend Program
DQ7
Toggle
1 (Note)
Note: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-
erase suspend sector address will indicate logic “1” at the DQ2 bit.
RY/BY
Ready/Busy
The MBM29DL400TC/BC provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29DL400TC/BC are placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to Figure 11 and 12 for a detailed timing diagram. The RY/BY
pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL400TC/BC devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0
to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin
becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer
to Figures 13, 14 and 15 for the timing diagram.
Data Protection
The MBM29DL400TC/BC are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
25
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than 2.3 V (typically 2.4 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when VCC is above 2.3 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
26
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
■ ABSOLUTE MAXIMUM RATINGS
Storage Temperature ..................................................................................................–55°C to +125°C
Ambient Temperature with Power Applied ..................................................................–40°C to +85°C
Voltage with respect to Ground All pins except A9, OE, RESET (Note 1)...................–0.5 V to VCC+0.5 V
VCC (Note 1) ................................................................................................................–0.5 V to +5.5 V
A9, OE, and RESET (Note 2) ......................................................................................–0.5 V to +13.0 V
Notes: 1. Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negative
overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCC
+0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns.
2. Minimum DC input voltage on A9, OE and RESET pins are –0.5 V. During voltage transitions, A9, OE
and RESET pins may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input
voltage on A9, OE and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of
up to 20 ns. when VCC is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING RANGES
Ambient Temperature (TA)
MBM29DL400TC/BC-55 ..........................................................................................–20°C to +70°C
MBM29DL400TC/BC-70/-90/-12..............................................................................–40°C to +85°C
VCC Supply Voltages
MBM29DL400TC/BC-55/-70....................................................................................+3.0 V to +3.6 V
MBM29DL400TC/BC-90/-12....................................................................................+2.7 V to +3.6 V
Operating ranges define those limits between which the functionality of the devices are guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the dwvice is
perated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
27
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
■ MAXIMUM OVERSHOOT
20 ns
20 ns
+0.6 V
–0.5 V
–2.0 V
20 ns
Figure 1 Maximum Negative Overshoot Waveform
20 ns
V CC +2.0 V
V CC +0.5 V
+2.0 V
20 ns
20 ns
Figure 2 Maximum Positive Overshoot Waveform 1
20 ns
+14.0 V
+13.0 V
V CC +0.5 V
20 ns
20 ns
*: This waveform is applied for A9, OE, and RESET.
Figure 3 Maximum Positive Overshoot Waveform 2
28
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
■ DC CHARACTERISTICS
Parameter
Symbol
Parameter Description
Test Conditions
Min.
Max.
Unit
ILI
Input Leakage Current
Output Leakage Current
VIN = VSS to VCC, VCC = VCC Max.
VOUT = VSS to VCC, VCC = VCC Max.
–1.0
–1.0
+1.0
+1.0
µA
µA
ILO
A9, OE, RESET Inputs Leakage VCC = VCC Max.
ILIT
—
—
35
µA
Current
A9, OE, RESET = 12.5 V
Byte
Word
Byte
18
20
8
CE = VIL, OE = VIH,
f=10 MHz
mA
ICC1
VCC Active Current (Note 1)
CE = VIL, OE = VIH,
f=5 MHz
—
mA
Word
10
35
ICC2
ICC3
ICC4
VCC Active Current (Note 2)
VCC Current (Standby)
CE = VIL, OE = VIH
—
—
mA
VCC = VCC Max., CE = VCC ± 0.3 V,
RESET = VCC ± 0.3 V
5
5
µA
VCC = VCC Max.,
RESET = VSS ± 0.3 V
VCC Current (Standby, Reset)
—
—
µA
VCC = VCC Max., CE = VSS ± 0.3 V,
RESET = VCC ± 0.3 V
VIN = VCC ± 0.3 V or VSS ± 0.3 V
VCC Current
(Automatic Sleep Mode) (Note 3)
ICC5
5
µA
Byte
CE = VIL, OE = VIH
Word
—
—
—
—
45
45
45
45
VCC Active Current (Note 5)
(Read-While-Program)
ICC6
mA
Byte
CE = VIL, OE = VIH
Word
VCC Active Current (Note 5)
(Read-While-Erase)
ICC7
mA
mA
VCC Active Current
(Erase-Suspend-Program)
ICC8
CE = VIL, OE = VIH
—
35
VIL
VIH
Input Low Level
Input High Level
—
—
–0.5
2.0
0.6
V
V
VCC+0.3
Voltage for Autoselect and Sector
Protection (A9, OE, RESET)
(Note 4)
VID
—
11.5
12.5
V
VOL
Output Low Voltage Level
Output High Voltage Level
Low VCC Lock-Out Voltage
IOL = 4.0 mA, VCC = VCC Min.
IOH = –2.0 mA, VCC = VCC Min.
IOH = –100 µA
—
2.4
0.45
—
V
V
V
V
VOH1
VOH2
VLKO
VCC–0.4
2.3
—
—
2.5
Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
4. Applicable for only VCC applying.
5. Embedded Algorithm (program or erase) is in progress. (@5 MHz)
29
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Parameter
Symbols
-55
-70
-90
-12
Description
Test Setup
Unit
(Note) (Note) (Note) (Note)
JEDEC Standard
tAVAV
tAVQV
tRC
Read Cycle Time
—
Min.
55
55
70
70
90
90
120
120
ns
ns
CE = VIL
OE = VIL
tACC
Address to Output Delay
Max.
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
OE = VIL Max.
55
30
25
25
70
30
25
25
90
35
30
30
120
50
ns
ns
ns
ns
—
—
—
Max.
Max.
Max.
30
30
Output Hold Time From Addresses,
CE or OE, Whichever Occurs First
tAXQX
—
tOH
—
—
—
Min.
Max.
Max.
0
20
5
0
20
5
0
20
5
0
20
5
ns
µs
ns
tREADY
RESET Pin Low to Read Mode
tELFL
tELFH
—
CE or BYTE Switching Low or High
Note: Test Conditions:
Output Load: 1 TTL gate and 30 pF (MBM29DL400TC/BC-55/-70)
1 TTL gate and 100 pF (MBM29DL400TC/BC-90/-12)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output:1.5 V
3.3 V
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diodes = IN3064
or Equivalent
Note: CL = 30 pF including jig capacitance (MBM29DL400TC/BC-55/-70)
CL = 100 pF including jig capacitance (MBM29DL400TC/BC-90/-12)
Figure 4 Test Conditions
30
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
• Write/Erase/Program Operations
Parameter Symbols
JEDEC Standard
MBM29DL400TC/BC
Description
Unit
-55
55
0
-70
70
0
-90
90
0
-12
120
0
tAVAV
tWC
tAS
Write Cycle Time
Min.
Min.
ns
ns
tAVWL
Address Setup Time
Address Setup Time to OE Low During Toggle
Bit Polling
—
tWLAX
—
tASO
tAH
Min.
Min.
Min.
15
45
0
15
45
0
15
45
0
15
50
0
ns
ns
ns
Address Hold Time
Address Hold Time from CE or OE High During
Toggle Bit Polling
tAHT
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Data Hold Time
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Min.
Typ.
Typ.
Min.
30
0
35
0
45
0
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
µs
ns
µs
µs
µs
Read
0
0
0
0
Output Enable
Hold Time
—
tOEH
Toggle and Data Polling
10
20
20
0
10
20
20
0
10
20
20
0
10
25
25
0
—
—
tCEPH
tOEPH
tGHWL
tGHEL
tCS
CE High During Toggle Bit Polling
OE High During Toggle Bit Polling
Read Recover Time Before Write
Read Recover Time Before Write
CE Setup Time
tGHWL
tGHEL
tELWL
tWLEL
tWHEH
tEHWH
tWLWH
tELEH
tWHWL
tEHEL
tWHWH1
tWHWH2
—
0
0
0
0
0
0
0
0
tWS
WE Setup Time
0
0
0
0
tCH
CE Hold Time
0
0
0
0
tWH
WE Hold Time
0
0
0
0
tWP
Write Pulse Width
30
30
25
25
8
35
35
25
25
8
45
45
25
25
8
50
50
30
30
8
tCP
CE Pulse Width
tWPH
tCPH
Write Pulse Width High
CE Pulse Width High
tWHWH1
tWHWH2
tVCS
Byte Programming Operation
Sector Erase Operation (Note 1)
VCC Setup Time
1
1
1
1
50
50
50
50
—
tVIDR
tVLHT
tWPP
tOESP
Rise Time to VID (Note 2)
Voltage Transition Time (Note 2)
Write Pulse Width (Note 2)
OE Setup Time to WE Active (Note 2)
Min. 500 500 500 500
Min.
Min. 100 100 100 100
Min.
—
4
4
4
4
—
—
4
4
4
4
(Continued)
31
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
(Continued)
Parameter Symbols
JEDEC Standard
MBM29DL400TC/BC
Description
Unit
-55
4
-70
4
-90
4
-12
4
—
—
—
—
—
—
—
—
tCSP
tRB
CE Setup Time to WE Active (Note 2)
Recover Time From RY/BY
Min.
Min.
µs
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
tRP
RESET Pulse Width
Min. 500
Min. 200
500
200
30
30
90
30
500
200
35
35
90
35
500
200
50
50
90
50
tRH
RESET Hold Time Before Read
BYTE Switching Low to Output High-Z
BYTE Switching High to Output Active
Program/Erase Valid to RY/BY Delay
Delay Time from Embedded Output Enable
tFLQZ
tFHQV
tBUSY
tEOE
Max.
Min.
30
30
90
30
Max.
Max.
Notes: 1. This does not include the preprogramming time.
2. This timing is for Sector Protection operation.
32
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
■ SWITCHING WAVEFORMS
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
“H” or “L”
Any Change
Permitted
Changing
State
Unknown
Does Not
Apply
Center Line is
High-
Impedance
“Off” State
t RC
Addresses
Addresses Stable
t ACC
CE
OE
t OE
t DF
t OEH
WE
t CE
High-Z
High-Z
Outputs
Output Valid
Figure 5.1 AC Waveforms for Read Operations
33
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
t RC
Addresses
Addresses Stable
t ACC
CE
t RH
t RP
t RH
t CE
RESET
Outputs
t OH
High-Z
Output Valid
Figure 5.2 AC Waveforms for Hardware Reset/Read Operations
34
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Data Polling
3rd Bus Cycle
Addresses
555H
PA
PA
t WC
t RC
t AS
t AH
CE
t CH
t CS
t CE
OE
t WP
t WPH
t OE
t GHWL
t WHWH1
WE
t OH
t DS
t DH
A0H
PD
DQ 7
D OUT
D OUT
Data
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 6 Alternate WE Controlled Program Operations
35
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
3rd Bus Cycle
Data Polling
Addresses
PA
PA
555H
t WC
t AS
t AH
WE
t WS
t WH
OE
CE
t GHEL
t CP
t CPH
t WHWH1
t DS
t DH
A0H
PD
DQ 7
D OUT
Data
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 7 Alternate CE Controlled Program Operations
36
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
2AAH
555H
555H
Addresses
555H
2AAH
SA
t WC
t AS
t AH
CE
t CS
t CH
OE
t WP
t WPH
t GHWL
WE
t DS
t DH
10H/
30H
AAH
55H
80H
AAH
55H
Data
t VCS
V CC
Notes: 1. SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAH (Byte)
for Chip Erase.
2. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
Figure 8 AC Waveforms Chip/Sector Erase Operations
37
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
CE
t CH
t OE
t DF
OE
t OEH
WE
t CE
*
High-Z
High-Z
DQ7 =
Data
Data
DQ7
DQ7
Valid Data
t WHWH1 or 2
DQ0 to DQ6
Valid Data
DQ0 to DQ6
RY/BY
DQ0 to DQ6 = Output Flag
t BUSY
t EOE
* : DQ7 = Valid Data (The device has completed the Embedded operation).
Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations
38
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Address
tAHT tASO
tAHT tAS
CE
tCEPH
WE
tOEPH
tOEH
tOEH
OE
tOE
tCE
tDH
*
Stop
Output
Valid
Toggle
Data
Toggle
Data
Toggle
Data
DQ 6/DQ2
Data
Toggling
tBUSY
RY/BY
* : DQ6 stops toggling (The device has completed the Embedded operation).
Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
39
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
CE
The rising edge of the last write pulse
WE
Entire programming
or erase operations
RY/BY
t BUSY
Figure 11 RY/BY Timing Diagram during Program/Erase Operations
WE
RESET
tRP
t RB
RY/BY
tREADY
Figure 12 RESET/RY/BY Timing Diagram
40
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
CE
BYTE
Data Output
(DQ0 to DQ7)
Data Output
(DQ0 to DQ14)
DQ0 to DQ14
tELFH
tFHQV
DQ15
DQ15/A-1
A-1
Figure 13 Timing Diagram for Word Mode Configuration
CE
BYTE
tELFL
DQ0 to DQ14
Data Output
(DQ0 to DQ14)
Data Output
(DQ0 to DQ7)
DQ15/A-1
DQ15
A-1
tFLQZ
Figure 14 Timing Diagram for Byte Mode Configuration
The falling edge of the last write signal
CE or WE
Input
Valid
BYTE
tSET
(tAS)
tHOLD (tAH)
Figure 15 BYTE Timing Diagram for Write Operations
41
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
A17, A16
A15, A14
A13, A12
SAX
SAY
A0
A1
A6
12 V
3 V
A9
t VLHT
12 V
3 V
OE
WE
CE
t VLHT
t VLHT
t VLHT
t WPP
t OESP
t CSP
Data
VCC
01H
t VCS
t OE
SAX : Sector Address for initial sector
SAY : Sector Address for next sector
Note: A-1 is VIL on byte mode.
Figure 16 AC Waveforms for Sector Protection
42
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
VCC
tVIDR
tVCS
tVLHT
VID
3 V
3 V
RESET
CE
WE
tVLHT
tVLHT
Program or Erase Command Sequence
Unprotection period
RY/BY
Figure 17 Temporary Sector Unprotection Timing Diagram
Read
Command
Read
Command
Read
Read
tRC
tWC
tRC
tWC
tRC
tRC
BA2
BA2
(PA)
BA2
(PA)
Address
CE
BA1
BA1
BA1
(555H)
tACC
tCE
tAS
tAS
tAH
tAHT
tOE
tCEPH
OE
WE
DQ
tDF
tGHWL
tOEH
tWP
tDS
tDH
tDF
Valid
Output Intput Output Intput
Valid
Valid
Valid
Valid
Status
Output
(A0H) (PD)
Note: This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1: Address of Bank 1.
BA2: Address of Bank 2.
Figure 18 Back-to-back Read/Write Timing Diagram
43
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
WE
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Toggle
DQ2 and DQ6
with OE or CE
Note: DQ2 is read from the erase-suspended sector.
Figure 19 DQ2 vs. DQ6
44
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
VCC
tVCS
RESET
Add
tVLHT
tWC
tWC
tVIDR
SPAX
SPAX
SPAY
A0
A1
A6
CE
OE
tWP
TIME-OUT
WE
Data
60H
60H
40H
01H
60H
tOE
SPAX : Sector Address to be protected
SPAY : Next Sector Address to be protected
TIME-OUT : Time-Out window = 150 µs (min)
Figure 20 Extended Sector Protection Timing Diagram
45
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
EMBEDDED ALGORITHMS
Start
Write Program Command
Sequence
(See below)
Data Polling Device
No
Last Address
?
Increment Address
Yes
Programming Completed
Program Command Sequence* (Address/Command):
555H/AAH
2AAH/55H
555H/A0H
Program Address/Program Data
* : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
Figure 21 Embedded ProgramTM Algorithm
46
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
EMBEDDED ALGORITHMS
Start
Write Erase Command
Sequence
(See below)
Data Polling or Toggle Bit
Successfully Completed
Erasure Completed
Individual Sector/Multiple Sector*
Chip Erase Command Sequence*
(Address/Command):
Erase Command Sequence
(Address/Command):
555H/AAH
2AAH/55H
555H/80H
555H/AAH
2AAH/55H
555H/10H
555H/AAH
2AAH/55H
555H/80H
555H/AAH
2AAH/55H
Sector Address/30H
Sector Address/30H
Additional sector
erase commands
are optional.
Sector Address/30H
* : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
Figure 22 Embedded EraseTM Algorithm
47
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Start
Read
(DQ 0 to DQ 7)
Addr. = VA
VA = Byte address for programming
= Any of the sector addresses within
the sector being erased during
sector erase or multiple sector
erases operation
Yes
DQ 7 = Data?
No
= Any of the sector addresses within
the sector not being protected
during chip erase
No
DQ 5 = 1?
Yes
Read
(DQ 0 to DQ 7)
Addr. = VA
Yes
DQ 7 = Data?
No
Fail
Pass
Note: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Figure 23 Data Polling Algorithm
48
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Start
Read
(DQ 0 to DQ 7)
Addr. = VA
VA = Bank address being executed
Embedded Algorithm.
No
DQ 6 = Toggle
?
Yes
No
DQ 5 = 1?
Yes
Read
(DQ 0 to DQ 7)
Addr. = VA
No
DQ 6 = Toggle
?
Yes
Fail
Pass
Note: DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as
DQ5 changing to “1” .
Figure 24 Toggle Bit Algorithm
49
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Start
Setup Sector Addr.
(A17, A16, A15, A14, A13, A12)
PLSCNT = 1
OE = V ID, A 9 =V ID,
A 6 = CE = V IL, RESET = V IH
A 0 = V IL, A 1 = V IH
Activate WE Pulse
Time out 100 µs
Increment PLSCNT
WE = V IH, CE = OE = V IL
(A 9 should remain V ID
)
Read from Sector
(Addr. = SA, A 0 = V IL,
A 1 = V IH, A = V IL)*
6
No
No
PLSCNT = 25?
Yes
Data = 01H?
Yes
Yes
Remove V ID from A 9
Write Reset Command
Protect Another Sector?
No
Device Failed
Remove V ID from A 9
Write Reset Command
Sector Protection
Completed
* : A-1 is VIL on byte mode.
Figure 25 Sector Protection Algorithm
50
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Start
RESET = VID
(Note 1)
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotection Completed
(Note 2)
Notes: 1. All protected sectors are unprotected.
2. All previously protected sectors are protected once again.
Figure 26 Temporary Sector Unprotection Algorithm
51
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
FAST MODE ALGORITHM
Start
RESET = VID
Wait to 4 µs
Device is Operating in
Temporary Sector
Unprotection Mode
No
Extended Sector
Protection Entry?
Yes
To Setup Sector Protection
Write XXXH/60H
PLSCNT = 1
To Sector Protection
Write SPA/60H
(A0 = VIL, A1 = VIH, A6 = VIL)
Time Out 150 µs
Increment PLSCNT
To Verify Sector Protection
Write SPA/40H
Setup Next Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
Read from Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
No
No
Data = 01H?
Yes
PLSCNT = 25?
Yes
Yes
Remove VID from RESET
Write Reset Command
Protection Other Sector
?
No
Remove VID from RESET
Write Reset Command
Device Failed
Sector Protection
Completed
Figure 27 Extended Sector Protection Algorithm
52
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
FAST MODE ALGORITHM
Start
555H/AAH
Set Fast Mode
2AAH/55H
555H/20H
XXXH/A0H
Program Address/Program Data
Data Polling Device
No
In Fast Program
Verify Byte?
Yes
No
Last Address
?
Increment Address
Yes
Programming Completed
(BA)XXXH/90H
XXXH/F0H
Reset Fast Mode
* : The sequence is applied for × 16 mode.
The addresses differ from × 8 mode.
Figure 28 Embedded ProgramTM Algorithm for Fast Mode
53
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
■ ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Unit
Comments
Min.
Typ.
Max.
Excludes programming time
prior to erasure
Sector Erase Time
—
1
10
sec
Word Programming Time
Byte Programming Time
—
—
16
8
360
300
µs
µs
Excludes system-level
overhead
Excludes system-level
overhead
Chip Programming Time
Program/Erase Cycle
—
4.2
—
12.5
—
sec
100,000
cycles
—
■ TSOP(I) PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0
VOUT = 0
VIN = 0
6
8.5
8
7.5
12
10
pF
pF
pF
COUT
Output Capacitance
Control Pin Capacitance
CIN2
Note: Test conditions TA = 25°C, f = 1.0 MHz
54
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
■ PACKAGE DIMENSIONS
* : Resin protrusion. (Each Side: 0.15 (.006)max)
48-pin plastic TSOP(I)
(FPT-48P-M19)
LEAD No.
1
48
Details of "A" part
INDEX
0.15(.006)
MAX
0.35(.014)
MAX
"A"
0.15(.006)
0.25(.010)
24
25
20.00±0.20
(.787±.008)
* 12.00±0.20
(.472±.008)
*
18.40±0.20
(.724±.008)
11.50REF
(.460)
1.10 –+00..0150
.043 –+..000024
(Mounting height)
0.50(.0197)
TYP
0.05(0.02)MIN
(STAND OFF)
0.10(.004)
0.15±0.05
(.006±.002)
0.20±0.10
(.008±.004)
M
0.10(.004)
19.00±0.20
(.748±.008)
0.50±0.10
(.020±.004)
C
Dimensions in mm (inches).
1996 FUJITSU LIMITED F48029S-2C-2
* : Resin protrusion. (Each Side: 0.15 (.006)max)
48-pin plastic TSOP(I)
(FPT-48P-M20)
LEAD No.
1
48
Details of "A" part
INDEX
0.15(.006)
MAX
0.35(.014)
MAX
"A"
0.15(.006)
0.25(.010)
24
25
19.00±0.20
(.748±.008)
0.50±0.10
(.020±.004)
0.15±0.10
(.006±.002)
0.20±0.10
(.008±.004)
M
0.10(.004)
0.50(.0197)
TYP
0.05(0.02)MIN
(STAND OFF)
0.10(.004)
1.10 –+00..0150
* 18.40±0.20
11.50(.460)REF
* 12.00±0.20(.472±.008)
.043 –+..000024
(Mounting height)
(.724±.008)
20.00±0.20
(.787±.008)
C
Dimensions in mm (inches).
1996 FUJITSU LIMITED F48030S-2C-2
55
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
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The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
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or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
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approval.
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Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
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FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Any semiconductor devices have an inhereut chance of
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prevention of over-current levels and other abnormal operating
conditions.
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Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9811
FUJITSU LIMITED Printed in Japan
相关型号:
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