MBM29PL160TD_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20872-1E

PAGE MODE FLASH MEMORY

CMOS

16M (2M × 8/1M × 16) BIT

-75/-90

MBM29PL160TD

/MBM29PL160BD

■ FEATURES

• Single 3.0 V read, program and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Uses same software commands as E²PROMs

• Compatible with MASK ROM pinouts

48-pin TSOP (I) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type)

44-pin SOP (Package suffix: PF)

• Minimum 100,000 program/erase cycles

• High performance

25 ns maximum page access time (75ns maximum random access time)

• An 8 words page read mode function

• Sector erase architecture

One 8K word, two 4K words, one 112K word, and seven 128K words sectors in word mode

One 16K byte, two 8K bytes, one 224K byte, and seven 256K bytes sectors in byte mode

Any combination of sectors can be concurrently erased. Also supports full chip erase

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

• Embedded Erase^TMAlgorithms

Automatically pre-programs and erases the chip or any sector

• Embedded program^TMAlgorithms

Automatically programs and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switches themselves to low power mode

• Low V^CCwrite inhibit ≤ 2.5 V

(Continued)

Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

(Continued)

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Sector protection

Hardware method disables any combination of sectors from program or erase operations

• Temporary sector unprotection

Temporary sector unprotection with the software command

• 5V tolerant (Data, Address, and Control Signals)

• In accordance with CFI (Common Flash Memory Interface)

■ PACKAGE

48-pin plastic TSOP (I)

Marking Side

(FPT-48P-M19)

(FPT-48P-M20)

44-pin plastic SOP

(FPT-44P-M16)

2

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

■ GENERAL DESCRIPTION

The MBM29PL160TD/BD is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M

words of 16 bits each. The MBM29PL160TD/BD is offered in a 48-pin TSOP (I), and 44-pin SOP packages. The

device is designed to be programmed in-system with the standard system 3.0 V V^CCsupply. 12.0 V V^PPand 5.0

V V^CCare not required for write or erase operations. The device can also be reprogrammed in standard EPROM

programmers.

The standard MBM29PL160TD/BD offers access times of 75 ns and 90 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write

enable (WE), and output enable (OE) controls.

The MBM29PL160TD/BD is pin and command set compatible with JEDEC standard E²PROMs. Commands are

written to the command register using standard microprocessor write timings. Register contents serve as input

to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and erase operations. Reading data out of the device is

similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29PL160TD/BD is programmed by executing the program command sequence. This will invoke the

Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths

and verifies proper cell margins. Typically, each sector can be programmed and verified in about 2.0 seconds.

Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase

Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed

before executing the erase operation. During erase, the device automatically times the erase pulse widths and

verifies proper cell margins.

Any individual sector is typically erased and verified in 4.8 second. (If already preprogrammed.)

The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29PL160TD/BD is erased when shipped from the

factory.

The device features single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V^CCdetector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ⁷

or by the Toggle Bit feature on DQ⁶output pin. Once the end of a program or erase cycle has been comleted,

the device internally resets to the read mode.

Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The MBM29PL160TD/BD memory electrically erases all bits

within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word

at a time using the EPROM programming mechanism of hot electron injection.

3

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE

• One 8K word, two 4K words, one 112K word, and seven 128K words sectors in word mode.

• One 16K byte, two 8K bytes, one 224K byte, and seven 256K bytes sectors in byte mode.

• Individual-sector, multiple-sector, or bulk-erase capability.

• Individual or multiple-sector protection is user definable.

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

Sector Size

(× 8) Address Range

000000H to 03FFFFH

040000H to 07FFFFH

080000H to 0BFFFFH

0C0000H to 0FFFFFH

100000H to 13FFFFH

140000H to 16FFFFH

180000H to 1BFFFFH

1C0000H to 1F7FFFH

1F8000H to 1F9FFFH

1FA000H to 1FBFFFH

1FC000H to 1FFFFFH

(× 16) Address Range

00000H to 1FFFFH

20000H to 3FFFFH

40000H to 5FFFFH

60000H to 7FFFFH

80000H to 9FFFFH

A0000H to BFFFFH

C0000H to DFFFFH

E0000H to FBFFFH

FC000H to FCFFFH

FD000H to FDFFFH

FE000H to FFFFFH

256 Kbytes or 128 Kwords

224 Kbytes or 112 Kwords

8 Kbytes or 4 Kwords

16 Kbytes or 8 Kwords

MBM29PL160TD Top Boot Sector Architecture

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

Sector Size

(× 8) Address Range

000000H to 003FFFH

004000H to 005FFFH

006000H to 007FFFH

008000H to 03FFFFH

040000H to 07FFFFH

080000H to 0BFFFFH

0C0000H to 0FFFFFH

100000H to 13FFFFH

140000H to 17FFFFH

180000H to 1BFFFFH

1C0000H to 1FFFFFH

(× 16) Address Range

00000H to 01FFFH

02000H to 02FFFH

03000H to 03FFFH

04000H to 1FFFFH

20000H to 3FFFFH

40000H to 5FFFFH

60000H to 7FFFFH

80000H to 9FFFFH

A0000H to BFFFFH

C0000H to DFFFFH

E0000H to FFFFFH

16 Kbytes or 8 Kwords

8 Kbytes or 4 Kwords

224 Kbytes or 112 Kwords

256 Kbytes or 128 Kwords

MBM29PL160BD Bottom Boot Sector Architecture

4

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

■ PRODUCT LINE UP

Part No.

V^CC= 3.0 V

MBM29PL160TD/160BD

+0.6 V

–0.3 V

Ordering Part No.

-75

-90

Max. Address Access Time (ns)

Max. Page Address Access Time (ns)

Max. CE Access Time (ns)

75

25

75

25

90

35

90

35

Max. OE Access Time (ns)

■ BLOCK DIAGRAM

DQ⁰to DQ¹⁵

V^CC

V^SS

Input/Output

Buffers

Erase Voltage

Generator

State

Control

WE

BYTE

Command

Register

Program Voltage

Generator

Chip Enable

Output Enable

STB

Data Latch

Logic

CE

OE

Y-Gating

Y-Decoder

X-Decoder

STB

Timer for

Program/Erase

Address

Latch

Low V^CCDetector

Cell Matrix

A⁰to A¹⁹

A^-1

5

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

■ CONNECTION DIAGRAMS

SOP

TSOP(I)

(Marking Side)

BYTE

A¹⁶

A¹⁵

A¹⁴

A¹³

A¹²

A¹¹

A¹⁰

A⁹

N.C.

V^SS

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

(Marking Side)

1

2

44

43

2

WE

A¹⁸

N.C.

A¹⁹

DQ¹⁵/A^-1

DQ⁷

DQ¹⁴

DQ⁶

DQ¹³

DQ⁵

DQ¹²

DQ⁴

V^CC

3

4

5

6

A¹⁷

A⁷

A⁶

A⁵

A⁸

3

4

5

6

7

8

42

41

40

39

38

37

7

8

A⁹

9

A⁸

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

A¹⁰

A¹¹

A¹⁹

WE

N.C.

A¹⁸

A¹⁷

A⁷

V^CC

V^SS

Standard Pinout

DQ¹¹

DQ³

DQ¹⁰

DQ²

DQ⁹

DQ¹

DQ⁸

DQ⁰

OE

A⁴

A³

A¹²

A¹³

A⁶

A⁵

A⁴

A²

A¹

9

36

35

34

33

A¹⁴

A¹⁵

A³

A²

10

11

12

A¹

A⁰

V^SS

N.C.

CE

A⁰

A¹⁶

FPT-48P-M19

(Marking Side)

CE

BYTE

V^SS

OE

13

14

32

31

V^SS

DQ¹⁵/A^-1

DQ⁰

DQ⁷

15

16

30

29

CE

A⁰

N.C.

V^SS

OE

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

DQ⁸

DQ¹

DQ⁹

DQ²

DQ¹⁰

DQ¹⁴

DQ⁶

A¹

A²

DQ⁰

DQ⁸

DQ¹

DQ⁹

DQ²

DQ¹⁰

DQ³

DQ¹¹

V^SS

17

28

A³

A⁴

DQ¹³

DQ⁵

18

19

27

26

A⁵

A⁶

A⁷

A¹⁷

A¹⁸

N.C.

WE

A¹⁹

A⁸

DQ¹²

20

21

22

25

24

23

Reverse Pinout

V^CC

DQ³

DQ⁴

V^CC

DQ⁴

DQ¹²

DQ⁵

DQ¹³

DQ⁶

DQ¹⁴

DQ⁷

DQ¹⁵/A^-1

V^SS

DQ¹¹

A⁹

A¹⁰

A¹¹

A¹²

A¹³

A¹⁴

A¹⁵

A¹⁶

BYTE

8

7

6

FPT-44P-M16

5

4

3

2

N.C.

1

FPT-48P-M20

6

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

■ LOGIC SYMBOL

Table 1 MBM29PL160TD/BD Pin Configuration

Function

Address Inputs

A^-1, A⁰to A¹⁹

DQ⁰to DQ¹⁵

A^-1

20

Data Inputs/Outputs

A⁰to A¹⁹

16 or 8

CE

OE

Chip Enable

DQ⁰to DQ¹⁵

Output Enable

CE

OE

Write Enable

WE

BYTE

Selects 8-bit or 16-bit mode

Pin Not Connected Internally

Device Ground

BYTE

N.C.

V^SS

V^CC

Device Power Supply

7

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

■ DEVICE BUS OPERATIONS

Table 2 MBM29PL160TD/BD User Bus Operation (BYTE = V^IH)

DQ⁰to DQ¹⁵

Code

D^OUT

Operation

Auto-Select Manufacture Code (1)

Auto-Select Device Code (1)

Read (3)

CE

L

OE

L

WE

H

A⁰

L

A¹

L

A⁶

L

A⁹

V^ID

A⁹

X

L

H

A⁰

X

L

H

A¹

X

A⁶

X

Standby

H

L

X

HIGH-Z

D^IN

Output Disable

H

V^ID

L

H

X

Write (Program/Erase)

Enable Sector Protection (2), (4)

Verify Sector Protection (2), (4)

L

A⁰

L

A¹

H

A⁶

L

A⁹

V^ID

L

X

L

H

L

Code

Table 3 MBM29PL160TD/BD User Bus Operation (BYTE = V^IL)

DQ¹⁵/

Operation

CE OE WE

A⁰

A¹

A⁶

A⁹

DQ⁰to DQ⁷

A^-1

Auto-Select Manufacture Code (1)

Auto-Select Device Code (1)

Read (3)

L

H

L

H

X

H

L

H

A⁰

X

L

V^ID

A⁹

X

Code

D^OUT

L

A^-1

X

A¹

X

A⁶

X

A⁶

L

Standby

X

HIGH-Z

D^IN

Output Disable

H

V^ID

L

X

Write (Program/Erase)

Enable Sector Protection (2), (4)

Verify Sector Protection (2), (4)

A^-1

L

A⁰

L

A¹

H

A⁹

V^ID

X

H

L

Code

Legend: L = V^IL, H = V^IH, X = V^ILor V^IH.

= pulse input. See DC Characteristics for voltage levels.

Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See

Table 7.

2. Refer to the section on Sector Protection.

3. WE can be V^ILif OE is V^IL, OE at V^IHinitiates the write operations.

4. V^CC= 3.3 V ±10%

8

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

■ FUNCTIONAL DESCRIPTION

Random Read Mode

The MBM29PL160TD/BD has two control functions which must be satisfied in order to obtain data at the outputs.

CE is the power control and should be used for a device selection. OE is the output control and should be used

to gate data to the output pins if a device is selected.

Address access time (t^ACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (t^CE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the

addresses have been stable for at least t^ACC- t^OEtime.) See Figure 5.1 for timing specifications. When reading

out a data without changing addresses after powe-up, it is necessary to input hardware reset or to change CE

pin from "H" to "L".

Page Read Mode

The MBM29PL160TD/BD is capable of fast Page read mode and is compatible with the Page mode MASK ROM

read operation. This mode provides faster read access speed for random locations within a page. The Page size

of the MBM29PL160TD/BD device is 8 words, or 16 bytes, within the appropriate Page being selected by the

higheraddress bits A⁰to A²(in the word mode) and A^-1to A²(in the byte mode) determining the specific word/

bytewithin that page. This is an asynchronous operation with the microprocessor supplying the specific word or

byte location.

The rondom or initial page access is equal to t^ACCand subsequent Page read access (as long as the locations

specified by the microprocessor fall within that Page) is equivalent to t^PACC. Here again, CE selects the device

and OE is the output control and should be used to gate data to the output pins if the device is selected. Fast

Page mode accesses are obtained by keeping A³to A¹⁹constant and changing A⁰to A²to select the specific

word, or changing A^-1to A²to select the specific byte, within that page. See Figure 5.2 for timing specifications.

Standby Mode

The MBM29PL160TD/BD has a standby mode, a CMOS standby mode (CE input hel at V^CC±0.3 V.), when the

current consumed is less than 50 µA. During Embedded Algorithm operation, V^CCActive current (I^CC2) is required

even CE = “H”. The device can be read with standard access time (t^CE) from standby modes.

In the standby mode, the outputs are in the high-impedance state, independent of the OE input. If the device

is deselected during erasure or programming, the device will draw active current until the operation is completed.

Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of

MBM29PL160TD/BD data. This mode can be used effectively with an application requesting low power

consumption such as handy terminals.

To activate this mode, MBM29PL160TD/BD automatically switches itself to low power mode when addresses

remain stable for 150 ns. It is not necessary to control CE, WE, and OE in this mode. During such mode, the

current consumed is typically 50 µA (CMOS Level).

Standard address access timings provide new data when addresses are changed. While in sleep mode, output

data is latched and always available to the system.

Output Disable

If the OE input is at a logic high level (V^IH), output from the device is disabled. This will cause the output pins to

be in a high-impedance state.

9

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

Autoselect

The Autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer

and type. The intent is to allow programming equipment to automatically match the device to be programmed

with its corresponding programming algorithm. The Autoselect command may also be used to check the status

of write-protected sectors. (See Tables 4.1 and 4.2.) This mode is functional over the entire temperature range

of the device.

To activate this mode, the programming equipment must force V^ID(11.5 V to 12.5 V) on address pin A⁹. Two

identifier bytes may then be sequenced from the devices outputs by toggling address A⁰from V^ILto V^IH. All

addresses are DON’T CARES except A⁰, A¹, and A⁶(A^-1). (See Table 2 or Table 3.) (Recomend to set VIL for

the other addresses pins.)

The manufacturer and device codes may also be read via the command register, for instances when the

MBM29PL160TD/BD is erased or programmed in a system without access to high voltage on the A⁹pin. The

command sequence is illustrated in Table 7, Command Definitions.

Word 0 (A⁰= V^IL) represents the manufacture’s code and word 1 (A⁰= V^IH) represents the device identifier code.

For the MBM29PL160TD/BD these two bytes are given in the Table 4.2. All identifiers for manufactures and

device will exhibit odd parity with DQ⁷defined as the parity bit. In order to read the proper device codes when

executing the Autoselect, A¹must be V^IL. (See Tables 2 or 3.)

If BYTE = V^IL(for byte mode), the device code is 27H (for top boot block) or 45H (for bottom boot block). If BYTE

= V^IH(for word mode), the device code is 2227H (for top boot block) or 2245H (for bottom boot block).

In order to determine which sectors are write protected, A¹must be at V^IHwhile running through the sector

addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ⁰(DQ⁰=1).

10

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

Table 4.1 MBM29PL160TD/BD Sector Protection Verify Autoselect Code

Code

A^-1*¹

Type

Manufacture’s Code

A¹²to A¹⁹

A⁶

A¹

A⁰

(HEX)

X

V^IL

X

04H

Byte

Word

Byte

27H

MBM29PL160TD

MBM29PL160BD

X

V^IL

V^IH

2227H

45H

Device Code

V^IL

X

Word

2245H

Sector

Addresses

01H*²

01H*³

Sector Protection

V^IL

V^IH

V^IL

V^IH

V^IL

Temporary Sector Unprotection

*1: A^-1is for Byte mode.

X

*2: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.

*3: Outputs 01H at Temporary Sector Unprotect and outputs 00H at Non Temporary Sector Unprotect.

Table 4.2 Expanded Autoselect Code Table

Code DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

Manufacture’s Code

04H A^-1/0

0

1

0

1

0

1

0

1

0

1

0

1

(B)

(W) 2227H

27H A^-1HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

MBM29PL160TD

0

1

0

1

0

Device

Code

(B)

45H A^-1HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

MBM29PL160BD

(W)

2245H

0

1

0

1

0

Sector Protection

01H A^-1/0

Temporary Sector

Unprotection

0

1

(B): Byte mode

(W): Word mode

11

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

Table 5 Sector Address Tables (MBM29PL160TD)

Sector

A¹⁹

A¹⁸

A¹⁷

A¹⁶

A¹⁵

A¹⁴

A¹³

A¹²

(× 8) Address Range (× 16) Address Range

Address

SA0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

000000H to 03FFFFH

040000H to 07FFFFH

080000H to 0BFFFFH

0C0000H to 0FFFFFH

100000H to 13FFFFH

140000H to 17FFFFH

180000H to 1BFFFFH

1C0000H to 1F7FFFH

1F8000H to 1F9FFFH

1FA000H to 1FBFFFH

1FC000H to 1FFFFFH

00000H to 1FFFFH

20000H to 3FFFFH

40000H to 5FFFFH

60000H to 7FFFFH

80000H to 9FFFFH

A0000H to BFFFFH

C0000H to DFFFFH

E0000H to FBFFFH

FC000H to FCFFFH

FD000H to FDFFFH

FE000H to FFFFFH

SA1

SA2

SA3

SA4

SA5

SA6

SA7

00000 - 11011

SA8

1

0

1

0

1

SA9

SA10

X

Table 6 Sector Address Tables (MBM29PL160BD)

Sector

Address

A¹⁹

A¹⁸

A¹⁷

A¹⁶

A¹⁵

A¹⁴

A¹³

A¹²

(× 8) Address Range (× 16) Address Range

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

000000H to 003FFFH

004000H to 005FFFH

006000H to 007FFFH

008000H to 03FFFFH

040000H to 07FFFFH

080000H to 0BFFFFH

0C0000H to 0FFFFFH

100000H to 13FFFFH

140000H to 17FFFFH

180000H to 1BFFFFH

1C0000H to 1FFFFFH

00000H to 01FFFH

02000H to 02FFFH

03000H to 03FFFH

04000H to 1FFFFH

20000H to 3FFFFH

40000H to 5FFFFH

60000H to 7FFFFH

80000H to 9FFFFH

A0000H to BFFFFH

C0000H to DFFFFH

E0000H to FFFFFH

00100 - 11111

X

12

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

Write

Device erasure and programming are accomplished via the command register. The command register is written

by bringing WE to V^IL, while CE is at V^ILand OE is at V^IH. Addresses are latched on the falling edge of CE or

WE, whichever occurs later, while data is latched on the rising edge of CE or WE pulse, whichever occurs first.

Standard microprocessor write timings are used. See Figures 6 to 8.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

Sector Protection

The MBM29PL160TD/BD features hardware sector protection. This feature will disable both program and erase

operations in any number of sectors (0 through 10). The sector protection feature is enabled using programming

equipment at the user’s site. The device is shipped with all sectors unprotected.

To activate this mode, the programming equipment must force V^IDon address pin A⁹and control pin OE, CE =

V^IL, A⁰= A⁶= V^IL, A¹= V^IH. The sector addresses pins (A¹⁹, A¹⁸, A¹⁷, A¹⁶, A¹⁵, A¹⁴, A¹³, and A¹²) should be set to

the sector to be protected. Tables 5 and 6 define the sector address for each of the eleven (11) individual sectors.

Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the

rising edge of the same. Sector addresses must be held constant during the WE pulse. See figures 14 and 20

for sector protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must force V^IDon address pin A⁹

with CE and OE at V^ILand WE at V^IH. Scanning the sector addresses (A¹⁹, A¹⁸, A¹⁷, A¹⁶, A¹⁵, A¹⁴, A¹³, and A¹²)

while (A⁶, A¹, A⁰) = (0, 1, 0) will produce a logical “1” at device output DQ⁰for a protected sector. Otherwise the

device will read 00H for an unprotected sector. In this mode, the lower order addresses, except for A⁰, A¹, and

A⁶are DON’T CARES. Address locations with A¹= V^ILare reserved for Autoselect manufacturer and device

codes. A^-1requires to V^ILin byte mode.

ItisalsopossibletodetermineifasectorisprotectedinthesystembywritinganAutoselectcommand. Performing

a read operation at the address location XX02H, where the higher order addresses pins (A¹⁹, A¹⁸, A¹⁷, A¹⁶, A¹⁵,

A¹⁴, A¹³, and A¹²) represents the sector address will produce a logical “1” at DQ⁰for a protected sector. See

Tables 4.1 and 4.2 for Autoselect codes.

Temporary Sector Unprotection

This feature allows temporary unprotection of previously protected sectors of the MBM29PL160TD/BD devices

in order to change data. The Temporary Sector Unprotection mode is activated by command register. During

this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once

the mode is taken away using command register, all the previously protected sectors will be protected again.

(See Figures 20.)

13

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

Table 7 MBM29PL160TD/BD Standard Command Definitions

Second

Bus

Fourth Bus

Read/Write

Cycle

Command

Sequence

First Bus

Third Bus

Fifth Bus

Sixth Bus

Bus

Write Write Cycle

Write Cycle

Write Cycle Write Cycle

Write Cycle

Cycles

Req'd

(Notes 1, 2, 3, 5)

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Word

/Byte

Read/Reset

(Note 6)

1

3

XXXH F0H

—

Word

Byte

555H

AAH

2AAH

555H

2AAH

555H

2AAH

555H

AAAH

555H

AAAH

555H

Read/Reset

(Note 6)

55H

F0H RA

RD

AAAH

Word

Byte

555H

AAH

Autoselect

3

4

6

55H

90H

—

AAAH

Byte/Word

Program

Word

555H

AAH

A0H PA

PD

Byte

AAAH

555H

AAAH

(Notes 3, 4)

Word

Byte

Word

Byte

555H

AAH

2AAH

555H

2AAH

555H

AAAH

555H

AAAH

555H

80H

2AAH

555H

2AAH

555H

Chip Erase

AAH

55H

10H

30H

AAAH

555H

AAH

555H

80H

Sector Erase

(Note 3)

SA

AAAH

Sector Erase

Suspend

Word

/Byte

1

XXXH B0H

—

Word

/Byte

Sector Erase

Resume

XXXH 30H

555H

Temporary

Unprotect

Enable

Word

Byte

Word

Byte

2AAH

555H

2AAH

555H

AAAH

555H

AAAH

4

AAH

55H

E0H XXXH 01H

E0H XXXH 00H

—

AAAH

Temporary

Unprotect

Disable

555H

AAH

AAAH

Notes: 1. Address bits A¹¹to A¹⁹= X = “H” or “L” for all address commands except or Program Address (PA) and

Sector Address (SA).

2. Bus operations are defined in Tables 2 and 3.

3. RA =Address of the memory location to be read.

PA =Address of the memory location to be programmed. Addresses are latched on the falling edge of

the WE pulse.

SA =Address of the sector to be erased. The combination of A¹⁹, A¹⁸, A¹⁷, A¹⁶, A¹⁵, A¹⁴, A¹³, and A¹²will

uniquely select any sector.

4. RD =Data read from location RA during read operation.

PD =Data to be programmed at location PA. Data is latched on the rising edge of WE.

5. The system should generate the following address patterns:

Word Mode: 555H or 2AAH to addresses A⁰to A¹⁰

Byte Mode: AAAH or 555H to addresses A^-1to A¹⁰

6. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

14

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

Table 8 MBM29PL160TD/BD Extended Command Definitions

Bus

Write

First Bus

Second Bus

Write Cycle

Third Bus

Fourth Bus

Read Cycle

Command

Sequence

Write Cycle

Cycles

Req'd

Addr

Data

Addr

2AAH

555H

Data

Addr

Data

Addr

Data

Word

Byte

Word

Byte

Word

Byte

Word

Byte

555H

AAAH

XXXH

55H

555H

Set to Fast

3

2

AAH

55H

20H

—

Mode

AAAH

Fast Program *1

A0H

90H

98H

PA

PD

F0H *3

—

XXXH

Reset from Fast

Mode *1

Query

—

Command *2

AAH

SPA : Sector Address to be protected. Set sector address (SA) and (A⁶, A¹, A⁰) = (0, 1, 0).

SD : Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected sector

addresses.

*1. This command is valid while fast mode.

*2. Addresses from system set to A⁰to A⁶. The other addresses are “Don’t care”.

*3. The data" 00H" is also acceptable.

Command Definitions

Device operations are selected by writing specific address and data sequences into the command register.

Writing incorrect address and data values or writing them in an improper sequence will reset the device to the

read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and

Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both

Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that

commands are always written at DQ⁰to DQ⁷and DQ⁸to DQ¹⁵bits are ignored.

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ⁵= 1) to read mode, the read/reset

operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor

read cycles retrieve array data from the memory. The device remains enabled for reads until the command

register contents are altered.

Thedevicewillautomaticallypower-upintheRead/Resetstate. Inthiscase, acommandsequenceisnotrequired

to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no

spurious alteration of the memory contents occurs during the power transition. Refer to the AC Read

Characteristics and Waveforms for specific timing parameters. (See Figure 5.1 and 5.2.)

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,

manufactures and device codes must be accessible while the device resides in the target system. PROM

programmers typically access the signature codes by raising A⁹to a high voltage. However, multiplexing high

voltage onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming

methodology. The operation is initiated by writing the Autoselect command sequence into the command register.

Following the last command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A

read cycle from address XX01H for ×16 (XX02H for ×8) retrieves the device code (MBM29PL160TD = 27H and

15

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

MBM29PL160BD = 45H for ×8 mode; MBM29PL160TD = 2227H and MBM29PL160BD = 2245H for ×16 mode).

(See Tables 4.1 and 4.2.)

All manufactures and device codes will exhibit odd parity with DQ⁷defined as the parity bit.

The sector state (protection or unprotection) will be indicated by address XX02H for ×16 (XX04H for ×8).

Scanning the sector addresses (A¹⁹, A¹⁸, A¹⁷, A¹⁶, A¹⁵, A¹⁴, A¹³, and A¹²) while (A⁶, A¹, A⁰) = (0, 1, 0) will produce

a logical “1” at device output DQ⁰for a protected sector. The programming verification should be perform margin

mode verification on the protected sector. (See Tables 2 and 3.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and,

also to write the Autoselect command during the operation, by executing it after writing the Read/Reset command

sequence.

Word/Byte Programming

The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.

There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.

Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the

rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens

first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system

is not required to provide further controls or timings. The device will automatically provide adequate internally

generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.)

The automatic programming operation is completed when the data on DQ⁷is equivalent to data written to this

bit at which time the device return to the read mode and addresses are no longer latched. (See Table 9, Hardware

Sequence Flags.) Therefore, the device requires that a valid address be supplied by the system at this time.

Hence, Data Polling must be performed at the memory location which is being programmed.

Any commands written to the chip during this period will be ignored. If hardware reset occures during the

programming operation, it is impossible to guarantee whether the data being written is correct or not.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success

according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only

erase operations can convert “0”s to “1”s.

Figure 16 illustrates the Embedded Program^TMAlgorithm using typical command strings and bus operations.

Chip Erase

Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm command sequence the device will automatically program and verify the entire memory for an all zero

data pattern prior to electrical erase. (Preprogram Function.) The system is not required to provide any controls

or timings during these operations.

The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates

when the data on DQ⁷is “1” (See Write Operation Status section.) at which time the device returns to read mode.

(See Figure 8.)

Figure 17 illustrates the Embedded Erase^TMAlgorithm using typical command strings and bus operations.

Sector Erase

Sector erase is a six-bus cycle operation. There are two “unlock” write cycles, followed by writing the “set-up”

command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address

(any address location within the desired sector) is latched on the falling edge of WE, while the command (Data

= 30H) is latched on the rising edge of WE. After a time-out of 50 µs from the rising edge of the last sector erase

command, the sector erase operation will begin.

16

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

Multiple sectors may be erased concurrently by writing six-bus cycle operations on Table 7. This sequence is

followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently

erased. The time between writes must be less than 50 µs otherwise that command will not be accepted and

erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this

condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs

from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling

edge of the WE occurs within the 50 µs time-out window the timer is reset. Monitor DQ³to determine if the sector

erase timer window is still open. (See section DQ³, Sector Erase Timer.) Any command other than Sector Erase

or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous

command string. Resetting the device once excution has begun will corrupt the data in the sector. In that case,

restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for

Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any

number of sectors (0 to 10).

Sector erase does not require the user to program the device prior to erase. The device automatically programs

all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram Function). When erasing

a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any

controls or timings during these operations. (See Figure 8.)

The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last

sector erase command pulse and terminates when the data on DQ⁷is “1” (See Write Operation Status section)

at which time the device returns to the read mode. Data polling must be performed at an address within any of

the sectors being erased. Multiple Sector Erase Time; [Sector Program Time (Preprogramming) + Sector Erase

Time] × Number of Sector Erase.

Figure 17 illustrates the Embedded Erase^TMAlgorithm using typical command strings and bus operations.

Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads

from or program to a sector not being erased. This command is applicable ONLY during the Sector Erase

operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if

written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command

during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the

erase operation.

Writing the Erase Resume command resumes the erase operation. The addresses are “DON’T CARES” when

writing the Erase Suspend or Erase Resume commands.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum

of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/

BY output pin and the DQ⁷bit will be at logic “1”, and DQ⁶will stop toggling. The user must use the address of

the erasing sector for reading DQ⁶and DQ⁷to determine if the erase operation has been suspended. Further

writes of the Erase Suspend command are ignored.

When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading

data in this mode is the same as reading from the standard read mode except that the data must be read from

sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the

device is in the erase-suspend-read mode will cause DQ²to toggle. (See the section on DQ².)

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate

command sequence for Program. This Program mode is known as the erase-suspend-program mode. Again,

programming in this mode is the same as programming in the regular Program mode except that the data must

beprogrammedtosectorsthatarenoterase-suspended. Successivelyreadingfromtheerase-suspendedsector

while the devices are in the erase-suspend-program mode will cause DQ²to toggle. The end of the erase-

suspended Program operation is detected by Data polling of DQ⁷and the Toggle Bit (DQ⁶) which is the same

as the regular Program operation. Note that DQ⁷must be read from the Program address while DQ⁶can be read

from any address.

17

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of

the Resume command at this point will be ignored. Another Erase Suspend command can be written after the

chip has resumed erasing.

Extended Command

(1) Fast Mode

MBM29PL160TD/BDhasFastModefunction. Thismodedispenseswiththeinitialtwounlockcyclesrequired

in the standard program command sequence writing Fast Mode command into the command register. In this

mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program

command. (Do not write erase command in this mode.) The read operation is also executed after exiting this

mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register.

(Refer to the Figure 22 Extended algorithm.) The V^CCactive current is required even CE = V^IHduring Fast

Mode.

(2) Fast Programming

During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program

Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to

the Figure 22 Extended algorithm.)

(3) CFI (Common Flash Memory Interface)

The CFI (Common Flash Memory Interface) specification outlines device and host system software

interrogation handshake which allows specific vendor-specified software algorithms to be used for entire

families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backward-

compatible software support for the specified flash device families. Refer to CFI specification in detail.

The operation is initiated by writing the query command (98H) into the command register. Following the

command write, a read cycle from specific address retrives device information. Please note that output data

of upper byte (DQ⁸to DQ¹⁵) is “0” in word mode (16 bit) read. Refer to the CFI code table. To terminate

operation, it is necessary to write the read/reset command sequence into the register.

18

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

Write Operation Status

Table 9 Hardware Sequence Flags

Status

DQ⁷

0

DQ⁶

DQ⁵

0

DQ³

0

DQ²

1

Embedded Program Algorithm

Embedded/Erase Algorithm

Toggle

0

1

Toggle

Erase Suspend Read

(Erase Suspended Sector)

1

0

Data

0

Data

0

Toggle

Data

In

Erase

Progress

Erase Suspend Read

Suspend

Data

DQ⁷

Data

(Non-Erase Suspended Sector)

Mode

Erase Suspend Program

(Non-Erase Suspended Sector)

Toggle

(Note 1)

1

(Note 2)

Embedded Program Algorithm

Embedded/Erase Algorithm

DQ⁷

0

Toggle

1

0

1

Exceeded

Time

N/A

Limits

Erase Suspend Program

(Non-Erase Suspended Sector)

DQ⁷

Toggle

1

0

N/A

Notes: 1. Performing successive read operations from any address will cause DQ⁶to toggle.

2. Reading the byte address being programmed while in the erase-suspend program mode will indicate

logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ²to

toggle.

3. DQ⁰and DQ¹are reserve pins for future use.

4. DQ⁴is Fujitsu internal use only.

DQ⁷

Data Polling

The MBM29PL160TD/BD device features Data Polling as a method to indicate to the host that the Embedded

Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the

devices will produce the complement of the data last written to DQ⁷. Upon completion of the Embedded Program

Algorithm, an attempt to read the device will produce the true data last written to DQ⁷. During the Embedded

Erase Algorithm, an attempt to read the device will produce a “0” at the DQ⁷output. Upon completion of the

Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ⁷output. The flowchart

for Data Polling (DQ⁷) is shown in Figure 18.

For chip erase and sector erase, Data Polling is valid after the rising edge of the sixth WE pulse in the six-write

pulse sequence. Data Polling must be performed at a sector address within any of the sectors being erased and

not at a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is

closetobeingcompleted, theMBM29PL160TD/BDdatapins(DQ⁷)maychangeasynchronouslywhiletheoutput

enable (OE) is asserted low. This means that the device is driving status information on DQ⁷at one instant of

time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ⁷

output, it may read the status or valid data. Even if the device has completed the Embedded Program Algorithm

operation and DQ⁷has a valid data, the data outputs on DQ⁰to DQ⁶may be still invalid. The valid data on DQ⁰

to DQ⁷will be read on successive read attempts.

TheDataPollingfeatureisonlyactiveduringtheEmbeddedProgrammingAlgorithm,EmbeddedEraseAlgorithm

or sector erase time-out.

See Figure 9 for the Data Polling timing specifications and diagrams.

19

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

DQ⁶

Toggle Bit I

The MBM29PL160TD/BD also feature the “Toggle Bit I” as a method to indicate to the host system that the

Embedded Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from

the device will result in DQ⁶toggling between one and zero. Once the Embedded Program or Erase Algorithm

cycle is completed, DQ⁶will stop toggling and valid data can be read on the next successive attempts. During

programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence.

For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six-

write pulse sequence. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 µs and then stop

toggling without the data having changed. In erase, the device will erase all the selected sectors except for the

ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about

100 µs and then drop back into read mode, having changed none of the data.

Either CE or OE toggling will cause the DQ⁶to toggle. In addition, an Erase Suspend/Resume command will

cause the DQ⁶to toggle.

See Figure 10 and Figure 19 for the Toggle Bit I timing specifications and diagrams.

DQ⁵

Exceeded Timing Limits

DQ⁵will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ⁵will produce a “1”. This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling is the only operating function of the device under this

condition. The CE circuit will partially power down the device under these conditions. The OE and WE pins will

control the output disable functions as described in Tables 2 and 3.

The DQ⁵failure condition may also appear if a user tries to program a non blank location without erasing. In this

case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never

reads a valid data on DQ⁷and DQ⁶never stops toggling. Once the device has exceeded timing limits, the DQ⁵

bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used.

If this occurs, reset the device with command sequence.

DQ³

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ³will

remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase

command sequence.

If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ³may

be used to determine if the sector erase timer window is still open. If DQ³is high (“1”) the internally controlled

erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase

operation is completed as indicated by Data Polling or Toggle Bit I. If DQ³is low (“0”), the device will accept

additional sector erase commands. To insure the command has been accepted, the system software should

check the status of DQ³prior to and following each subsequent sector erase command. If DQ³is high on the

second status check, the command may not have been accepted.

See Table 9: Hardware Sequence Flags.

20

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

DQ²

Toggle Bit II

This Toggle Bit II, along with DQ⁶, can be used to determine whether the device is in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ²to toggle during the Embedded Erase Algorithm. If the

device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ²

to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address

of the non-erase suspended sector will indicate a logic “1” at DQ².

DQ⁶is different from DQ²in that DQ⁶toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress.

For example, DQ²and DQ⁶can be used together to determine if the erase-suspend-read mode is in progress.

(DQ²toggles while DQ⁶does not.) See also Table 10 and Figure 15.

Furthermore, DQ²can also be used to determine which sector is being erased. When the device is in the erase

mode, DQ²toggles if this bit is read from an erasing sector.

Table 10 Toggle Bit Status

Mode

DQ⁷

0

DQ⁶

DQ²

1

Program

Erase

Toggle

Erase Suspend Read

(Erase Suspended Sector)

(Note 1)

1

Toggle

Erase-Suspend Program

DQ⁷

Toggle (Note 1)

1 (Note 2)

Notes: 1. Performing successive read operations from any address will cause DQ⁶to toggle.

2. Reading the byte address being programmed while in the erase-suspend program mode will indicate

logic “1” at the DQ²bit. However, successive reads from the erase-suspended sector will cause DQ²to

toggle.

Word/Byte Configuration

The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29PL160TD/BD device. When

this pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ⁰

to DQ¹⁵. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ¹⁵/A^-1pin

becomes the lowest address bit and DQ⁸to DQ¹⁴bits are tri-stated. However, the command bus cycle is always

an 8-bit operation and hence commands are written at DQ⁰to DQ⁷and DQ⁸to DQ¹⁵bits are ignored. Refer to

Figures 11 to 13 for the timing diagrams.

Data Protection

The MBM29PL160TD/BD is designed to offer protection against accidental erasure or programming caused by

spurious system level signals that may exist during power transitions. During power up the device automatically

resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the

memory contents only occurs after successful completion of specific multi-bus cycle command sequence.

The device also incorporates several features to prevent inadvertent write cycles resulting form V^CCpower-up

and power-down transitions or system noise.

21

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

Low V^CCWrite Inhibit

To avoid initiation of a write cycle during V^CCpower-up and power-down, a write cycle is locked out for V^CCless

than 2.3 V (typically 2.4 V). If V^CC< V^LKO, the command register is disabled and all internal program/erase circuits

are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until

the V^CClevel is greater than V^LKO. It is the users responsibility to ensure that the control pins are logically correct

to prevent unintentional writes when V^CCis above 2.3 V.

If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be

erased again prior to programming.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not change the command registers.

Logical Inhibit

Writing is inhibited by holding any one of OE = V^IL, CE = V^IH, or WE = V^IH. To initiate a write, CE and WE must

be a logical zero while OE is a logical one.

Power-up Write Inhibit

Power-up of the devices with WE = CE = V^ILand OE = V^IHwill not accept commands on the rising edge of WE.

The internal state machine is automatically reset to read mode on power-up.

22

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

Table 11 Common Flash Memory Interface Code

DQ⁰to DQ¹⁵

Description

A⁰to A⁶

Description

A⁰to A⁶

Query-unique ASCII string

“QRY”

10h

11h

12h

0051h

0052h

0059h

Erase Block Region 2

Information

31h

32h

33h

34h

0001h

0000h

0020h

0000h

Primary OEM Command Set

2h: AMD/FJ standard type

13h

14h

0002h

0000h

Erase Block Region 3

Information

35h

36h

37h

38h

0000h

0080h

0003h

Address for Primary

Extended Table

15h

16h

0040h

0000h

Alternate OEM Command

Set (00h = not applicable)

17h

18h

0000h

Erase Block Region 4

Information

39h

3Ah

3Bh

3Ch

0006h

0000h

0004h

Address for Alternate OEM

Extended Table

19h

1Ah

0000h

V^CCMin. (write/erase)

D7-4: volt, D3-0: 100 mvolt

1Bh

0027h

Query-unique ASCII string

“PRI”

40h

41h

42h

0050h

0052h

0049h

V^CCMax. (write/erase)

D7-4: volt, D3-0: 100 mvolt

1Ch

0036h

Major version number, ASCII

Minor version number, ASCII

43h

44h

45h

0031h

0030h

0000h

V^PPMin. voltage

V^PPMax. voltage

1Dh

1Eh

1Fh

0000h

0004h

Address Sensitive Unlock

0 = Required

1 = Not Required

Typical timeout per single

byte/word write 2^Nµs

Typical timeout for Min. size

20h

21h

22h

23h

24h

25h

26h

27h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

0015h

Erase Suspend

46h

47h

48h

0002h

0001h

buffer write 2^Nµs

0 = Not Supported

1 = To Read Only

2 = To Read & Write

Typical timeout per individual

block erase 2^Nms

Sector Protect

Typical timeout for full chip

0 = Not Supported

X = Number of sectors in per

group

erase 2^Nms

Max. timeout for byte/word

write 2^Ntimes typical

Sector Temporary Unprotect

00 = Not Supported

01 = Supported

Max. timeout for buffer write

2^Ntimes typical

Max. timeout per individual

block erase 2^Ntimes typical

Sector Protection Algorithm

Number of Sector for Bank2

49h

4Ah

4Bh

0004h

00h

Max. timeout for full chip

erase 2^Ntimes typical

Device Size = 2^Nbyte

Burst Mode Type

00 = Not supported

00h

Page Mode Type

00 = Not supported

01 = 4 word Page

02 = 8 word Page

4Ch

02h

Flash Device Interface

description

28h

29h

0002h

0000h

Max. number of byte in

multi-byte write = 2^N

2Ah

2Bh

0000h

Number of Erase Block

Regions within device

2Ch

0004h

Erase Block Region 1

Information

2Dh

2Eh

2Fh

30h

0000h

0040h

0000h

23

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

■ ABSOLUTE MAXIMUM RATINGS

Storage Temperature ..................................................................................................–55°C to +125°C

Ambient Temperature with Power Applied ..................................................................–40°C to +85°C

Voltage with respect to Ground All pins except A⁹, OE, and RESET (Note 1)............–0.5 V to +5.5 V

V^CC(Note 1) ................................................................................................................–0.5 V to +4.0 V

A⁹, OE, and RESET (Note 2) ......................................................................................–0.5 V to +13.0 V

Notes: 1. Minimum DC voltage on input or l/O pins are –0.5 V. During voltage transitions, inputs may negative

overshoot V^SSto –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and l/O pins are 6.0V.

During voltage transitions,outputs may positive overshoot to V^CC+2.0 V for periods of up to 20 ns.

2. Minimum DC input voltage on A⁹, OE, and RESET pins are –0.5 V. During voltage transitions, A⁹, OE,

and RESET pins may negative overshoot V^SSto –2.0 V for periods of up to 20 ns. Maximum DC input

voltage on A⁹, OE, and RESET pins are +13.0 V which may positive overshoot to 13.5 V for periods of

up to 20 ns. Voltage difference between input voltage and supply voltage (V^IN– V^CC) do not exceed 9 V.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING RANGES

Ambient Temperature (T^A)

MBM29PL160TD/BD-75 ...........................................................................–20°C to +70°C

MBM29PL160TD/BD-90 ...........................................................................–40°C to +85°C

V^CCSupply Voltages

MBM29PL160TD/BD-75/90 ......................................................................+2.7 V to +3.6 V

Operating ranges define those limits between which the functionality of the device is quaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

24

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

■ MAXIMUM OVERSHOOT

20 ns

+0.6 V

–0.5 V

–2.0 V

20 ns

Figure 1 Maximum Negative Overshoot Waveform

20 ns

6.0 V

V^CC+0.5 V

+2.0 V

20 ns

Figure 2 Maximum Positive Overshoot Waveform 1

20 ns

+13.5 V

+13.0 V

V^CC+0.5 V

20 ns

Note : This waveform is applied for A⁹, OE, and RESET.

Figure 3 Maximum Positive Overshoot Waveform 2

25

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

■ DC CHARACTERISTICS

Parameter

Symbol

Parameter Description

Test Conditions

Min.

Max.

Unit

I^LI

Input Leakage Current

Output Leakage Current

V^IN= V^SSto V^CC, V^CC= V^CCMax.

V^OUT= V^SSto V^CC, V^CC= V^CCMax.

–1.0

+1.0

µA

I^LO

A⁹, OE, RESET Inputs Leakage V^CC= V^CCMax.,

I^LIT

—

35

70

40

µA

mA

Current

A⁹, OE = 12.5 V

CE = V^IL, OE = V^IH

f = 10 MHz

I^CC1

V^CCActive Current (Note 1)

CE = V^IL, OE = V^IH

f = 5 MHz

I^CC2

I^CC3

V^CCActive Current (Note 2)

V^CCCurrent (Standby)

V^CCCurrent

CE = V^IL, OE = V^IH

—

35

5

mA

µA

V^CC= V^CCMax., CE = V^CC±0.3 V,

V^CC= V^CCMax., CE = V^SS±0.3 V,

I^CC4

—

5

µA

(Automatic Sleep Mode) (Note 3) V^IN= V^CC±0.3 V or V^SS±0.3 V

30MHz

40MHz

—

12

15

mA

V

V^CCActive Current

(Page Read Mode)

I^CC5

CE = V^IL, OE = V^IH

V^IL

V^IH

Input Low Level

—

–0.5

2.0

0.8

5.5

Input High Level (Note 5)

V

Voltage for Autoselect,Sector

Protection (A⁹, OE) (Note 4, 5)

V^ID

—

11.5

12.5

V

V^OL

V^OH1

V^OH2

V^LKO

Output Low Voltage Level

Output High Voltage Level

Low V^CCLock-Out Voltage

I^OL= 4.0 mA, V^CC= V^CCMin.

I^OH= –2.0 mA, V^CC= V^CCMin.

I^OH= –100 µA

—

2.4

0.45

—

V

V^CC– 0.4

2.3

—

2.5

Notes: 1. The l^CCcurrent listed includes both the DC operating current and the frequency dependent component.

2. l^CCactive while Embedded Erase or Embedded Program is in progress.

3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

4. Applicable for only sector protection.

5. The input voltage must be input after Vcc is valid.

26

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

■ AC CHARACTERISTICS

• Read Only Operations Characteristics

Parameter

Symbols

-75

(Note)

-90

(Note)

Description

Test Setup

Unit

JEDEC

Standard

t^AVAV

t^RC

Read Cycle Time

—

Min.

75

25

90

35

ns

CE = V^IL

OE = V^IL

t^AVQV

—

t^ACC

t^PRC

Address to Output Delay

Page Read Cycle Time

Max.

Min.

Max.

—

CE = V^IL

OE = V^IL

—

t^PACC

Page Address to Output Delay

t^ELQV

t^GLQV

t^EHQZ

t^GHQZ

t^CE

t^OE

t^DF

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output HIGH-Z

Output Enable to Output HIGH-Z

OE = V^IL

Max.

75

25

20

90

35

30

ns

—

Output Hold Time From Address, CE

or OE, Whichever Occurs First

t^AXQX

—

t^OH

—

Min.

4

5

ns

t^ELFL

t^ELFH

CE or BYTE Switching Low or High

Max.

Note: Test Conditions: Output Load: 1 TTL gate and 30 pF (MBM29PL160TD/BD-75)

1 TTL gate and 100 pF (MBM29PL160TD/BD-90)

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 1.5 V

Output: 1.5 V

3.3 V

IN3064

or Equivalent

2.7 k

Ω

Device

Under

Test

6.2 k

Ω

CL

Diodes = IN3064

or Equivalent

Notes: C

L

= 30 pF including jig capacitance (MBM29PL160TD/BD-75)

CL

= 100 pF including jig capacitance (MBM29PL160TD/BD-90)

Figure 4 Test Conditions

27

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

• Write (Erase/Program) Operations

MBM29PL160TD/BD

Parameter Symbols

Description

Unit

JEDEC

t^AVAV

t^AVWL

t^WLAX

t^DVWH

t^WHDX

—

Standard

-75

75

0

-90

90

0

t^WC

t^AS

Write Cycle Time

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min.

ns

t^AH

45

35

0

45

0

t^DS

t^DH

t^OES

Output Enable Setup Time

0

Read

0

Output Enable

—

t^OEH

Hold Time

Toggle and Data Polling

10

0

10

0

t^GHWL

t^GHEL

t^GHWL

t^GHEL

Read Recover Time Before Write

(OE High to CE Low)

Min.

0

ns

t^ELWL

t^WLEL

t^WHEH

t^EHWH

t^WLWH

t^ELEH

t^WHWL

t^EHEL

t^CS

t^WS

t^CH

CE Setup Time

Min.

0

ns

WE Setup Time

CE Hold Time

0

t^WH

t^WP

t^CP

WE Hold Time

0

Write Pulse Width

CE Pulse Width

Write Pulse Width High

CE Pulse Width High

35

20

8.6

12.6

4.8

75

50

4

35

30

8.6

12.6

4.8

90

50

4

t^WPH

t^CPH

Byte

t^WHWH1

Programming Operation

Typ.

µs

Word

t^WHWH2

—

t^WHWH2

t^EOE

Sector Erase Operation (Note 1)

Delay Time from Embedded Output Enable

V^CCSetup Time

Typ.

Max.

Min.

Max.

Min.

sec

ns

µs

ns

—

t^VCS

—

t^VLHT

t^WPP

t^OESP

t^CSP

Voltage Transition Time (Note 2)

Write Pulse Width (Note 2)

—

100

4

100

4

—

OE Setup Time to WE Active (Note 2)

CE Setup Time to WE Active (Note 2)

Recover Time From RY/BY

—

4

—

t^RB

0

—

t^FLQZ

t^FHQV

BYTE Switching Low to Output HIGH-Z

BYTE Switching High to Output Active

30

40

30

—

Notes: 1. This does not include the preprogramming time.

2. This timing is for Sector Protection operation.

28

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

■ SWITCHING WAVEFORMS

• Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Must Be

Steady

Will Be

Steady

May

Change

from H to L

Will Be

Change

from H to L

May

Change

from L to H

Will Be

Change

from L to H

“H” or “L”:

Any Change

Permitted

Changing,

State

Unknown

Does Not

Apply

Center Line is

High-

Impedance

“Off” State

t^RC

Addresses

Addresses Stable

t^ACC

CE

OE

t^OE

t^DF

t^OEH

WE

t^CE

t^OH

HIGH-Z

Outputs

Output Valid

Figure 5.1 AC Waveforms for Read Operations

29

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

A¹³to A¹⁹

Addresses Valid

A⁰to A²

(A^-1)

Aa

t^RC

Ab

Ac

t^PRC

t^ACC

t^CE

CE

OE

WE

t^OE

t^OEH

t^PACC

t^OH

t^PACC

t^OH

t^DF

t^OH

HIGH-Z

Outputs

Da

Db

Dc

Figure 5.2 AC Waveforms for Page Read Mode Operations

30

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

3rd Bus Cycle

Data Polling

555H

t^WC

PA

Addresses

t^RC

t^AS

t^AH

CE

t^CH

t^CS

t^CE

OE

t^OE

t^WP

t^WPH

t^GHWL

t^WHWH1

WE

t^OH

t^DS

t^DH

PD

D^OUT

A0H

DQ⁷

Data

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at word address.

3. DQ⁷is the output of the complement of the data written to the device.

4. D^OUTis the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 6 AC Waveforms for Alternate WE Controlled Program Operations

31

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

3rd Bus Cycle

555H

Data Polling

PA

Addresses

t^WC

t^AH

t^AS

WE

t^WS

t^WH

OE

CE

t^CP

t^CPH

t^WHWH1

t^GHEL

t^DS

t^DH

PD

D^OUT

DQ⁷

A0H

Data

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at word address.

3. DQ⁷is the output of the complement of the data written to the device.

4. D^OUTis the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 7 AC Waveforms for Alternate CE Controlled Program Operations

32

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

2AAH

555H

SA*

2AAH

Addresses

555H

t^WC

t^AS

t^AH

CE

t^CS

t^CH

OE

t^WP

t^WPH

t^GHWL

WE

t^DS

t^DH

30H for Sector Erase

10H

AAH

55H

80H

55H

Data

V^CC

t^VCS

* : 1. SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAAH (Byte) for Chip

Erase.

2. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 8 AC Waveforms for Chip/Sector Erase Operations

33

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

CE

t^CH

t^DF

t^OE

OE

t^OEH

WE

t^CE

*

High-Z

DQ⁷=

Valid Data

Data

DQ⁷

t^{WHWH1 or 2}

DQ0 to DQ6

Valid Data

DQ⁰to DQ⁶= Output Flag

DQ⁰to DQ⁶

(t^EOE)

* : DQ⁷= Valid Data (The device has completed the Embedded operation.)

Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations

CE

t^OEH

WE

t^OEH

t^OES

OE

*

t^DH

DQ⁶=

Stop Toggling

DQ⁰to DQ⁷

Data Valid

DQ⁶= Toggle

Data

DQ⁶

t^OE

* : DQ⁶= Stops toggling. (The device has completed the Embedded operation.)

Figure 10 AC Waveforms for Taggle Bit I during Embedded Algorithm Operations

34

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

CE

BYTE

DQ⁰to DQ¹⁴

DQ⁰to DQ⁷

t^FHQV

DQ⁰to DQ¹⁴

t^ELFH

DQ¹⁵

DQ¹⁵/A^-1

A^-1

Figure 11 Timing Diagram for Word Mode Configuration

CE

BYTE

t^ELFL

DQ⁰to DQ¹⁴

DQ⁰to DQ⁷

DQ¹⁵/^A-1

DQ¹⁵

A^-1

t^FLQZ

Figure 12 Timing Diagram for Byte Mode Configuration

35

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

CE

The falling edge of the last WE signal

WE

Input

Valid

BYTE

t^SET

(t^AS)

t^HOLD

(t^AH)

Figure 13 BYTE Timing Diagram for Write Operations

36

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

A¹⁹, A¹⁸, A¹⁷

A¹⁶, A¹⁵, A¹⁴

A¹³, A¹²

SAX

SAY

A⁰

A¹

A⁶

V^ID

3 V

A⁹

t^VLHT

V^ID

3 V

OE

t^VLHT

t^WPP

WE

CE

t^VLHT

t^OESP

t^CSP

01H

Data

V^CC

t^VCS

t^OE

SAX = Sector Address for initial sector

SAY = Sector Address for next sector

Note: A^-1is V^ILon byte mode.

Figure 14

AC Waveforms for Sector Protection Timing Diagram

37

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

WE

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase Suspend

Read

Erase

Complete

DQ⁶

DQ²

Toggle

DQ²and DQ⁶

with OE

Note: DQ²is read from the erase-suspended sector.

Figure 15 DQ²vs. DQ⁶

38

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

■ FLOW CHART

Start

Write Program Command

Sequence

(See Below)

Data Polling Device

No

Verify Byte

?

Yes

No

Increment Address

Last Address

?

Yes

Programming Completed

Program Command Sequence* (Address/Command):

555H/AAH

2AAH/55H

555H/A0H

Program Address/Program Data

* : The sequence is applied for ×16 mode.

The addresses differ from ×8 mode.

Figure 16 Embedded Program^TMAlgorithm

39

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

Start

Write Erase Command

Sequece

(See Below)

Data Polling or Toggle Bit

from Device

No

Data = FFH

?

Yes

Erasure Completed

Individual Sector/Multiple Sector*

Chip Erase Command Sequence*

Erase Command Sequence

(Address/Command):

555H/AAH

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

555H/10H

555H/AAH

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

Sector Address/30H

Additional sector

erase commands

are optional.

* : The sequence is applied for ×16 mode.

The addresses differ from ×8 mode.

Figure 17 Embedded Erase^TMAlgorithm

40

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

VA =Address for programming

=Any of the sector addresses

Start

within the sector being erased

during sector erase or multiple

erases operation.

Read Byte

=Any of the sector addresses

within the sector not being

protected during sector erase or

multiple sector erases

operation.

(DQ⁰to DQ⁷)

Addr. = VA

Yes

DQ⁷= Data?

No

DQ⁵= 1?

Yes

Read Byte

(DQ⁰to DQ⁷)

Addr. = VA

Yes

DQ⁷= Data?

*

No

Fail

Pass

* : DQ⁷is rechecked even if DQ⁵= “1” because DQ⁷may change simultaneously with DQ⁵.

Figure 18 Data Polling Algorithm

41

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

Start

Read

(DQ⁰to DQ⁷)

Addr. = “H” or “L”

No

DQ⁶= Toggle

?

Yes

No

DQ⁵= 1?

Yes

Read Byte

(DQ⁰to DQ⁷)

Addr. = “H” or “L”

No

DQ⁶= Toggle

? *

Yes

Fail

Pass

* : DQ⁶is rechecked even if DQ⁵= “1” because DQ⁶may stop toggling at the same time as

DQ⁵changing to “1”.

Figure 19 Toggle Bit Algorithm

42

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

Start

Setup Sector Addr.

(A^19,A¹⁸, A¹⁷, A^16,

A¹⁵, A¹⁴, A¹³, A¹²)

PLSCNT = 1

OE = V^ID, A⁹= V^ID

A⁶= CE = V^IL

A⁰= V^IL, A¹= V^IH

Activate WE Pulse

Increment PLSCNT

Time out 100 µs

WE = V^IH, CE = OE = V^IL

(A⁹should remain V^ID)

Read from Sector

( A¹= V^IH, A⁰= V^IL,

Addr. = SA, A⁶= V^IL)*

No

PLSCNT = 25?

Yes

Data = 01H?

Yes

Remove V^IDfrom A⁹

Write Reset Command

Protect Another Sector?

No

Remove V^IDfrom A⁹

Device Failed

Write Reset Command

Sector Protection

Completed

* : A^-1is V^ILon byte mode.

Figure 20 Sector Protection Algorithm

43

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

Start

Temporary Unprotect Enable

Command Write (Note 1)

Perform Erase or

Program Operations

Temporary Unprotect Disable

Command Write

Temporary Sector

Unprotection Completed

(Note 2)

Notes: 1. All protected sectors are unprotected.

2. All previously protected sectors are protected once again.

Figure 21 Temporary Sector Unprotection Algorithm

44

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

Start

555H/AAH

Set Fast Mode

2AAH/55H

555H/20H

XXXXH/A0H

In Fast Program

Program Address/Program Data

Data Polling Device

No

Verify Byte?

Yes

No

Last Address

?

Increment Address

Yes

Programming Completed

XXXH/90H

XXXH/F0H

Reset Fast Mode

* : The sequence is applied for ×16 mode.

* : The addresses differ from ×8 mode.

Figure 22 Embedded Programming Algorithm for Fast Mode

45

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

■ ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Unit

sec

µs

Comments

Min.

Typ.

Max.

Excludes programming time

prior to erasure

Sector Erase Time

—

4.8

60

Byte Programming Time

Word Programming Time

—

8.6

300

360

Excludes system-level

overhead

12.6

Excludes system-level

overhead

Chip Programming Time

Erase/Program Cycle

—

18

—

140

—

sec

100,000

cycles

—

■ PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Test Setup

Typ.

Max.

Unit

C^IN

Input Capacitance

V^IN= 0

V^OUT= 0

V^IN= 0

6.0

8.5

8.0

7.5

pF

C^OUT

Output Capacitance

Control Pin Capacitance

12.0

11.5

C^IN2

Note: Test conditions T^A= 25°C, f = 1.0 MHz

46

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

■ ORDERING INFORMATION

Standard Products

Fujitsu standard products are available in several packages. The order number is formed by a combination of:

MBM29PL160

T

D

-80 PFTN

PACKAGE TYPE

PFTN = 48-Pin Thin Small Outline Package

(TSOP) Standard Pinout

PFTR = 48-Pin Thin Small Outline Package

(TSOP) Reverse Pinout

PF

=44-Pin Small Outline Package (SOP)

SPEED OPTION

See Product Selector Guide

DEVICE REVISION

BOOT CODE SECTOR ARCHITECTURE

T = Top sector

B = Bottom sector

DEVICE NUMBER/DESCRIPTION

MBM29PL160

16 Mega-bit (2M × 8-Bit or 1M × 16-Bit) CMOS Page Mode Flash Memory

3.0 V-only Read, Write, and Erase

47

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

■ PACKAGE DIMENSIONS

48-pin plastic TSOP (I)

*: Resin protruction. (Each side: 0.15(.006) Max)

(FPT-48P-M19)

LEAD No.

1

48

Details of "A" part

INDEX

0.15(.006)

MAX

0.35(.014)

MAX

"A"

0.15(.006)

0.25(.010)

24

25

20.00±0.20

(.787±.008)

* 12.00±0.20

(.472±.008)

* 18.40±0.20

(.724±.008)

11.50REF

(.460)

1.10 –⁺0⁰.^.0¹5⁰

.043 –⁺.^.0⁰0⁰2⁴

(Mounting height)

0.50(.0197)

TYP

0.05(0.02)MIN

(STAND OFF)

0.10(.004)

0.15±0.05

(.006±.002)

0.20±0.10

(.008±.004)

M

0.10(.004)

19.00±0.20

(.748±.008)

0.50±0.10

(.020±.004)

Dimensions in mm (inches)

C

1996 FUJITSU LIMITED F48029S-2C-2

(Continued)

48

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

48-pin plastic TSOP (I)

*: Resin protrusion. (Each side: 0.15(.006) Max)

(FPT-48P-M20)

LEAD No.

1

48

Details of "A" part

INDEX

0.15(.006)

MAX

0.35(.014)

MAX

"A"

0.15(.006)

0.25(.010)

24

25

19.00±0.20

(.748±.008)

0.50±0.10

(.020±.004)

0.15±0.10

(.006±.002)

0.20±0.10

(.008±.004)

M

0.10(.004)

0.50(.0197)

TYP

0.05(0.02)MIN

(STAND OFF)

0.10(.004)

1.10 –⁺0⁰.^.0¹5⁰

* 18.40±0.20

11.50(.460)REF

* 12.00±0.20(.472±.008)

.043 –⁺.^.0⁰0⁰2⁴

(Mounting height)

(.724±.008)

20.00±0.20

(.787±.008)

Dimensions in mm (inches)

(Continued)

C

1996 FUJITSU LIMITED F48030S-2C-2

49

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

44-pin plastic SOP

(FPT-44P-M16)

28.45 ⁺^–0⁰^.^.²²⁰⁵1.120 ^–⁺^.^.⁰⁰⁰¹⁸⁰

2.35±0.15(.093±.006)

(Mounting height)

0.80±0.20

(.031±.008)

44

23

13.00±0.10 16.00±0.20

(.512±.004) (.630±.008)

14.40±0.20

(.567±.008)

INDEX

1

22

LEAD No.

0.15±0.05

(.006±.002)

1.27(.050)TYP

0.10(.004)

0.40 ⁺^–0⁰^.^.⁰¹⁵⁰

.016 ⁺^–.^.⁰⁰⁰⁰²⁴

0.20 ⁺–0⁰.^.1¹5⁰.008 –⁺.^.0⁰0⁰6⁴

M

Ø0.13(.005)

(Stand off)

26.67(1.050)REF

Dimensions in mm (inches)

C

1998 FUJITSU LIMITED F44023S-4C-4

50

MBM29PL160TD-75/-90/MBM29PL160BD-75/-90

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: 81(44) 754-3763

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

Fax: 81(44) 754-3329

http://www.fujitsu.co.jp/

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications,

and are not intended to be incorporated in devices for actual use.

Also, FUJITSU is unable to assume responsibility for

infringement of any patent rights or other rights of third parties

arising from the use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

Fax: (408) 922-9179

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and measurement

equipment, personal or household devices, etc.).

CAUTION:

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded (such

as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608

Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Any semiconductor devices have an inhereut chance inherently

a certain rate of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for

export of those products from Japan.

Fax: (65) 281-0220

http://www.fmap.com.sg/

F9907

FUJITSU LIMITED Printed in Japan

51


型号：	MBM29PL160TD
厂家：	FUJITSU
描述：	16M (2M x 8/1M x 16) BIT 16M （ 2M ×8 / 1M ×16 ）位
文件：	总51页 (文件大小：566K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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