SOB8UV6484AL-125T-S [FUJITSU]
DRAM;
| 型号： | SOB8UV6484AL-125T-S |
| 厂家： | 
FUJITSU |
| 描述： | DRAM 动态存储器 |
| 文件： | 总9页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 1997
Revision 1.0
data sheet
SOB8UV6484-(67/84/100/125)T-S
64MByte (8M x 64) CMOS
Synchronous DRAM Module
General Description
The SOB8UV6484-(67/84/100/125)T-S is a high performance, 64-megabtye synchronous, dynamic RAM module organized as
8M words by 64 bits, in a 144-pin, small outline dual-in-line memory module (SODIMM) package.
The module utilizes eight Fujitsu MB81164842A-(67/84/100/125) PFTN CMOS 8Mx8 synchronous dynamic RAMs in surface
mount package (TSOP) on an epoxy laminated substrate. Each device is accompanied by a decoupling capacitor for improved
noise immunity.
A 256 Byte Serial EEPROM contains the module configuration information.
Features
• High Density 64MByte
• Cycle Time:
• Low Power:
8ns (125 MHz), 10ns (100 MHz), 12ns (84 MHz), 15ns (67 MHz)
Active 5.6W (125 MHz), 4.9W (100 MHz), 4.5W (84 MHz), 4.0W (67 MHz)
• LVTTL-compatible inputs and outputs
• Separate power and ground planes to improve noise immunity
• Single power supply of 3.3V±0.3V
• Height: 1.060 inch
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Ratings
-0.5 to +4.6
10.4
Unit
V
Voltage on any pin relative to V
V
SS
T
T
P
Power Dissipation
W
T
Operating Temperature
Storage Temperate
0 to +70
-55 to +125
±50
°C
°C
mA
opr
T
stg
OS
I
Short Circuit Output Current
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0 to +70 °C)
Symbol
Parameter
Supply Voltage
Min
Typ
Max
3.6
0
Unit
V
V
V
V
3.0
0
3.3
V
V
V
V
CC
SS
IH
Ground
0
-
V
+0.5
Input High voltage
Input Low voltage
2.0
-0.5
CC
-
0.8
IL
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
1
December 1997
Revision 1.0
SOB8UV6484-(67/84/100/125)T-S
Functional Diagram
DQMB7
DQMB6
DQMB5
DQMB4
DQMB3
DQMB2
DQMB1
CLK1
DQMB0
WE
RAS*
CAS*
CLK0
CS0*
CKE0
BA0
8M x 16
BLOCK
8M x 16
BLOCK
8M x 16
BLOCK
8M x 16
BLOCK
BA1
DQ0~DQ15
SCL
DQ16~DQ31
DQ32~DQ47
DQ48~DQ63
DQ0~DQ63
0.01mF
SCL
SDA
EEPROM
SDA
V
V
SS
CC
Decoupling capacitors
to all devices
(All specifications of the device are subject to change without notice.)
Notes:
1. A~A11 to all the devices.
2. CLKs are terminated using 10 ohm series resistors.
3. A0~A2 of serial PD EEPROM are grounded.
4. Each 8mx16 Block comprises two 8Mx8 SDRAMs.
5. DQMs vs Data I/Os
DQMB0 controls DQ0 ~ DQ7
DQMB1 controls DQ8 ~ DQ15
DQMB2 controls DQ16 ~ DQ23
DQMB3 controls DQ24 ~ DQ31
DQMB4 controls DQ32 ~ DQ39
DQMB5 controls DQ40 ~ DQ47
DQMB6 controls DQ48 ~ DQ55
DQMB7 controls DQ56 ~ DQ63
6. Clock Wiring
CLK0,CLK1
10W
10W
SDRAM1
SDRAM2
SDRAM3
SDRAM4
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
2
December 1997
Revision 1.0
SOB8UV6484-(67/84/100/125)T-S
Pin Name
A0~A11
A0~A8
BA0, BA1
DQ0~DQ63
CLK0, CLK1
RAS*
Row Addresses
DQMB0-DQMB7
DQ Mask Enables
Chip Select
Write Enable
Column Addresses
Bank Select Address
Data Inputs/Outputs
Clock Inputs
Row Address Strobes
Column Address Strobes
Clock Enables
CS0*
WE*
SCL
SDA
VCC
VSS
Serial Clock
Serial Data Input/Output
Power Supply
Ground
CAS*
CKE0
NC
No Connection
Pin No.
Pin Designation
Pin No.
2
Pin Designation
Pin No.
73
Pin Designation
Pin No.
74
Pin Designation
CLK1
1
3
VSS
VSS
NC
4
75
76
DQ0
DQ1
DQ2
DQ3
VCC
DQ32
DQ33
DQ34
DQ35
VCC
VSS
VSS
5
6
77
NC
78
NC
7
8
79
NC
80
NC
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
81
VCC
82
VCC
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
83
DQ16
DQ17
DQ18
DQ19
VSS
84
DQ48
DQ49
DQ50
DQ51
VSS
DQ4
DQ5
DQ6
DQ7
VSS
DQ36
DQ37
DQ38
DQ39
VSS
85
86
87
88
89
90
91
92
93
DQ20
DQ21
DQ22
DQ23
VCC
94
DQ52
DQ53
DQ54
DQ55
VCC
DQMB0
DQMB1
VCC
DQMB4
DQMB5
VCC
95
96
97
98
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
A0
A3
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
A1
A4
A6
A7
A2
A5
A8
BA0 (Note)
VSS
VSS
VSS
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ40
DQ41
DQ42
DQ43
VCC
A9
BA1 (Note)
A11
A10/AP (Note)
VCC
VCC
DQMB2
DQMB3
VSS
DQMB6
DQMB7
VSS
DQ12
DQ13
DQ14
DQ15
VSS
DQ44
DQ45
DQ46
DQ47
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ56
DQ57
DQ58
DQ59
VCC
NC
NC
NC
NC
DQ28
DQ29
DQ30
DQ31
VSS
DQ60
DQ61
DQ62
DQ63
VSS
CLK0
VCC
CKE0
VCC
RAS*
WE*
CS0*
NC
CAS*
NC
NC
SDA
SCL
NC
VCC
VCC
Notes: 1. Address A10 : Initiates Auto-Precharge
2. Address BA0,BA1 : Bank select within the SDRAM devices.
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
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December 1997
Revision 1.0
SOB8UV6484-(67/84/100/125)T-S
SERIAL PD INFORMATION
Byte#
Function Described
Function Supported
128 bytes
Hex Value
80h
0
1
2
3
4
5
6
7
8
9
# Bytes Written into serial memory at module mfr
Total # bytes of SPD memory device
Fundamental memory type
256 bytes
08h
04h
0Ch
09h
01h
40h
00h
01h
80h
A0h
C0h
F0h
75h
85h
85h
90h
00h
80h
08h
00h
01h
8Fh
04h
06h
01h
01h
00h
0Eh
C0h
F0h
20h
90h
90h
A0h
A0h
00h
00h
1Dh
1Eh
23h
28h
10h
14h
14h
14h
18h
1Eh
1Eh
1Eh
30h
3Ch
41h
46h
10h
00h
01h
SDRAM
# Row Address on this assembly
12
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly
9
1
64 bits
Data Width of this assembly (continued)
Voltage interface standard of this assembly
SDRAM cycle time at CL=3 (tCLK)
LVTTL
8ns
10ns
12ns
15ns
10
SDRAM Access from Clock at CL=3 (tAC)
7.5ns
8.5ns
8.5ns
9.0ns
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Non-Parity
Refresh Rate/Type
S/R, Normal 15.6 ms
SDRAM Width Primary DRAM
ECC SDRAM Data Width
Min. clock delay, Back to Back Random Column Addresses (ICCD)
Burst Length Supported
x8
N/A
1CLK
1, 2, 4, 8 & Full
# Banks on each SDRAM device
CAS# Latency
4
2, 3
CS# Latency
0
Write Latency
0
SDRAM Module Attribute
SDRAM Device Attribute
Min Clock cycle Time at CL=2 (tCLK)
Non-Buffered/Registered
Vcc, B/R, S/W, P/A, A/P
12ns
15ns
17ns
24
Max. Data Access Time from clock at CL=2 (tAC)
9.0ns
9.0ns
10ns
10ns
25
26
27
Min Clock cycle Time at CL=1 (tCLK)
Max. Data Access Time from clock at CL=1 (tAC)
Min. Row Precharge Time (tRP)
N/A
N/A
29ns
30ns
35ns
40ns
28
29
30
Min. Row Active Delay (tRRD)
Min. RAS to CAS Delay (tRCD)
Min. RAS Pulse Width (tRAS)
16ns
20ns
20ns
20ns
24ns
30ns
30ns
30ns
48ns
60ns
65ns
70ns
31
32-61
62
Module Bank Density
Superset Information
SPD Revision
64MB
Rev. 1
63
Checksum for bytes 0-62
Manufacturer’s Information
Unused Storage Locations
64-127
128+
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
4
December 1997
Revision 1.0
SOB8UV6484-(67/84/100/125)T-S
DC CHARACTERISTICS
(VCC = 3.3V±0.3V, VSS = 0V, TA = 0 to +70 °)
125
Max.
100
Max.
84
67
Parameter
Symbol
Test Condition
No Burst, t = min.
Unit
Note
Min.
Min.
Min.
Max.
Min.
Max.
CK
-
720
-
640
-
600
-
560
mA
1, 2
t
= min.
RC
I
Operating Current
CC1
No Burst, t = min.,
CK
t
= min.
-
1280
-
1120
-
1040
-
960
mA
1, 2
RC
All Banks Active
CKE -V , t = min.
IL CK
-
-
-
16
160
40
-
-
-
16
160
40
-
-
-
16
160
40
-
-
-
16
160
40
mA
mA
mA
1, 2
1.2
All Banks Idle
Precharge Standby
Current
I
I
CC2
CKE = V , t = min.
IH CK
All Banks Idle
CKE = V , t = min.
IL CK
1, 2
Any Bank Active
Active Standby
Current
CC3
CKE = V , t = min.
IH CK
-
-
200
-
-
200
960
-
-
200
920
-
-
200
680
mA
mA
1, 2
1, 2
Any Bank Active
I
I
I
t
= min.
Burst Mode Current
Refresh Current
1100
CC4
CC5
CC6
CK
t
t
= min., t = min.,
CK
RC
= min.
-
1560
-
1360
-
1240
-
1120
mA
1, 2
1, 2
RRD
Auto Refresh
CKE - V
Self Refresh Current
Input Leakage
-
16
-
16
-
16
-
16
mA
IL
I
0V £ Vin £ V
-180
180
-180
180
-180
180
-180
180
mA
LI
CC
0V £ Vout £ V
Output Leakage
Current
CC
I
-10
10
-10
10
-10
10
-10
10
mA
LO
D
= Disable
out
V
High I = -2mA
Output High Voltage
Output Low Voltage
2.4
-
-
2.4
-
-
2.4
-
-
2.4
-
-
V
V
OH
out
V
Low I = 2 mA
0.4
0.4
0.4
0.4
OL
out
†CL = CAS* Latency
Notes:
1.
I
depends on output load condition when the device is selected I (max.) is specified at the output open condition.
CC CC
2. An initial pulse of 200ms is required after power-up followed by a minimum of eight Auto-Refresh-Cycles.
CAPACITANCE
(TA =+25°C, VCC = 3.3V±0.3V)
Parameter
Input Capacitance (Address, WE*, RAS*, CAS*)
Input Capacitance (DQMBs)
Symbol
Max.
45
Unit
pF
Note
C
1
1
I1
C
10
pF
I2
C
Input Capacitance (CS0*, CKE0)
Input Capacitance (CLK0,CLK1)
45
pF
1
I3
C
25
pF
1
I4
C
Input/Output Capacitance (DQ0~DQ63)
12
pF
1, 2
I/O
Notes:
1. Capacitance is measured with Boonton Meter or effective capacitance method.
2. CAS* - V to disable D
.
out
IH
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
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December 1997
Revision 1.0
SOB8UV6484-(67/84/100/125)T-S
AC CHARACTERISTICS
(TA = 0 to +70°C, VCC = 3.3V±0.3V, VSS = 0V)
Parameter
Symbol Unit
125
100
84
67
Notes
CL=3
CL=2
8
-
-
10
15
-
-
12
17
-
-
15
20
-
-
tCK
Clock Period
ns
1, 2, 3, 6
12
0.5
tT
Transition Time
Clock High Time
Clock Low Time
Input Setup Time
Input Hold Time
ns
ns
ns
ns
ns
2
0.5
2
0.5
2
0.5
2
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
tCH
tCL
tSI
tHI
3.5
3.5
2.5
-
-
-
3.5
3.5
3.0
-
-
-
4
4
-
-
-
4
4
-
-
-
3.0
3.0
1.0
-
7.5
9
1.0
-
8.5
9
1.0
-
8.5
10
-
1.0
-
9.0
10
-
CL=3
CL=2
-
-
-
-
-
-
-
-
tAC
Output Valid from Clock
ns
1, 2, 3
tLZ
Output In Low-Z
ns
ns
2
-
3
-
3
3
1, 2, 3
tHZ
-
-
-
-
-
-
-
Output in High-Z
2
2
3
3
3
3
3
3
1, 2, 3, 4
1, 2, 3
tOH
Output Hold Time
ns
-
tREF
tRC
Time between Refresh
RAS Cycle Time
ms
ns
-
65.6
-
-
65.6
-
-
65.6
-
65.6
-
1, 2, 3
77
-
90
-
100
-
-
110
-
1, 2, 3, 5
1, 2, 3
tRAC
tCAC
tRP
RAS Access Time
ns
45
21
-
54
24
-
56
60
30
-
CAS Access Time
ns
-
-
-
26
-
1, 2, 3
RAS Precharge Time
RAS Active Time
ns
29
48
24
8
30
60
30
10
20
3
35
65
30
12
20
4
-
40
70
30
15
20
5
1, 2, 3
tRAS
tRCD
tWR
ns
100000
100000
100000
100000 1, 2, 3
RAS to CAS Delay Time
Write Recovery Time
RAS to RAS Delay Time
Power-down Exit Time
CKE to Clock Disable
DQM to Output in High-Z
DQM to Input Data Delay
Last Output to Write Command Delay
Write Command to Input Data Delay
ns
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
ns
tRRD
tPDE
ICKE
IDQZ
IDQD
IOWD
IDWD
ns
16
3
ns
cycle
cycle
cycle
cycle
cycle
1
2
0
2
1
2
0
2
1
2
0
2
1
2
0
2
0
3
2
3
2
2
0
3
2
3
2
2
0
3
2
3
2
2
0
3
2
3
2
2
CL=3
CL=2
CL=3
CL=2
Precharge to Output in
High-Z Delay
IROH
cycle
cycle
Burst Stop Command to Output in
High-Z Delay
IBSH
IMRD
ICCD
ICBD
Mode Register Access to Bank Active (min.)
CAS to CAS Delay
cycle
cycle
cycle
1
1
1
1
CAS Bank Delay
1
1
1
1
1
1
1
1
1
1
1
1
CL=3
Write to Precharge Read Delay
CL=2
IRWL
cycle
Notes:
1. An initial pulse of at least 200ms is required after power-up followed by a minimum of eight auto refresh cycles.
2. AC characteristics assume t = 1ns and 50pF capacitive load. If t is longer than 1ms, reference level for measuring time of input
T
T
signal is V (min.) and V (max.).
IH
IL
3. 1.4V is the reference level for measuring timing of input signals.
4. and t defines the time at which the outputs achieve ±200mV.
t
HZ
OH
5. Actual clock output of t will be sum clock of t
and t .
RP
RC
RAS
6. 20ns is not supported in SPD.
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
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December 1997
Revision 1.0
SOB8UV6484-(67/84/100/125)T-S
Physical Dimensions
144-pin (72x2) DIMM
Front View
T.B.D.
2.661
2.503
0.158x2
T. B. D
Æ070x2
“A”
1
143
0.913
1.291
0.181
0.098
0.130
0.145
0.040
±±0.004
0.031
0.083
2
144
0.157
0.157
0.031
0.100
0.024
T. B. D
0.010
0.098
0.059
Back View
Detail “A”
( All dimensions are in inches with 0.005" tolerance unless otherwise specified)
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
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December 1997
Revision 1.0
SOB8UV6484-(67/84/100/125)T-S
Ordering Information
S O B 8 U V 64 8 4
- 100 T - S
(1) (2) (3) (4) (5) (6)
(7) (8) (8a) (9) (10) (11)
(12) (13)
(14) (15)
(1) Memory Type
S : SDRAM
(9)
Interface Level
Blank : LVTTL
G : SGRAM
S
:
SSTL
(2) Module Shape
S : SIMM
(10) Module Revision / Applied “Standard” *1
Blank : Rev. 0
D : DIMM
A
B
:
:
Rev. 1
Rev. 2 (etc.)
O : Small Outline DIMM
(3) Module Pin Count
A : 72-pin
*1 When DRAM device or PCB is
revised, the revision is changed
B : 144-pin
C : 168-pin
D : 200-pin
(11) Power consumption
Blank : Standard
L
:
Low Power
(4) Word Depth
1
2
4
8
: 1M
: 2M
: 4M
: 8M
(12) Clock Frequency
67
:
:
:
:
67Mhz
84Mhz
100Mhz
125Mhz
84
100
125
256 : 256K
512 : 512K
.
(13) Package of Component
(5) Buffer Type
B : Buffered
J
T
:
:
SOJ
TSOP
U : Unbuffered
(14) Private Brand Name *2
(6) Operating Voltage
Blank : Common Products
V : 3,3V
G
:
FMG Brand
(7) Data Width
*2 This column is applicable to
custom modules, NOT applicable
to JEDEC standard commodity
products
(ex. 64=x64, 72=x72 etc.)
(8) Device Configuration
4 : x4
8 : x8
(15) Assembly & Test Site
1 : x16
S
:
Smart Modular Technologies
3 : x32
(8a) Refresh
2 : 2krf
4 : 4krf
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
8
December 1997
Revision 1.0
SOB8UV6484-(67/84/100/125)T-S
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Memory Marketing Dept.
4-1-1, Kamikodanaka Nakahara-ku,
Kawasaki 211-88, Japan
Tel: (044)754-3767
FAX: (044)754-3343
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street
San Jose, CA 95134-1804, USA.
Tel: 408-922-9000
FAX: 408-432-9044, 9045
Europe
All Rights Reserved.
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich–Buchschlag
Germany
Circuit diagrams utilizing Fujitsu products are included
as a means of illustrating typical semiconductor appli-
cations. Complete information sufficient for construction
purposes is not necessarily given.
Tel: (06103) 690-0
FAX: (06103) 690-122
The information given in this document have been care-
fully checked and is believed to be reliable. However,
Fujitsu assumes no responsibility for inaccuracies.
The information contained in this document does not
convey any licence under the copyrights, patent rights
or trademarks claimed and owned by Fujitsu.
Asia
FUJITSU MICROELECTRONICS ASIA PTE LIMITED
#05-08, 151 Lorong Chuan
NewTechPark
Fujitsu reserves the right to change products or specifi-
cations without notice.
Singapore 556741
No part of this publication may be copied or reproduced
in any form or by any means, or transferred to any third
party without prior written consent of Fujitsu.
Tel: (65) 281 0770
FAX: (65) 281 0220
The information contained in this document are not
intended for use with equipments which require
extremely high reliability such as aerospace equip-
ments, undersea repeaters, nuclear control systems or
medical equipments for life support.
ã FUJITSU LIMITED 1997
PrintedinGermany
Fujitsu Microelectronics, Inc./Fujitsu Mikroelektronik GmbH
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