MB91302APFF-G-020-BNDE1

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-16502-3E

32-Bit Proprietary Microcontroller

CMOS

FR60 MB91301 Series

MB91302A/V301A

■ DESCRIPTION

The MB91301 series are a line of microcontrollers based on a 32-bit RISC CPU core (FR family) , incorporating

a variety of I/O resources and a bus control mechanism for embedded control that requires the processing of a

high-performance, fast CPU as well as an SDRAM interface that can connect SDRAM directly to the chip.

The large address space supported by the 32-bit CPU addressing means that operation is primarily based on

external bus access although instruction cache memory of 4 Kbytes and RAM of 4 Kbytes( for data) are included

for high-speed execution of CPU instructions.

The MB91302A and MB91V301A are FR60 products based on the FR30/40 CPU with enhanced bus access for

higher speed operation. The device specifications include a D/A converter to facilitate motor control and are ideal

for use in DVD players that support fly-by transfer.

■ FEATURES

The MB91301 series is a line of ICs with various programs embedded in internal ROM.

ROM variation

Built-in the real

time OS version (Internal Program Loader) version

Built-in IPL

User ROM

version

Without ROM

version

Product name

MB91302A

(Continued)

■ PACKAGES

144-pin, Plastic LQFP

179-pin, Ceramic PGA

(FPT-144P-M12)

(PGA-179C-A03)

MB91301 Series

1. FR CPU

• 32-bit RISC, load/store architecture, 5-stage pipeline

• 68 MHz internal operating frequency (Max) [external (Max) 68 MHz] (when using PLL with base frequency

(Max) = 17 MHz)

• General purpose registers : 32 bits×16

• 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle

• Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift

etc.

• Instructions adapted for high-level languages : Function entry/exit instructions, multiple-register load/store

instructions

• Easier assembler coding : Register interlock function

• Branch instructions with delay slots : Reduced overhead time in branch executions

• Built-in multiplier with instruction-level support

Signed 32-bit multiplication : 5 cycles

Signed 16-bit multiplication : 3 cycles

• Interrupt (PC, PS save) : 6 cycles, 16 priority levels

2. Bus interface

• Operating frequency : Max 68 MHz (when using SDRAM)

• Full 24-bit address output (16 Mbytes memory space)

• 8-bit, 16-bit or 32-bit data input/output

• Built-in pre-fetch buffer

• Unused data and address pins can be used as general-purpose input/output ports.

• Eight fully independent chip select outputs, can be set in minimum 64 Kbytes units.

• Supports the following memory interfaces

Asynchronous SRAM, asynchronous ROM/Flash

Page mode ROM/Flash ROM (selectable page size = 1, 2, 4, or 8)

Burst mode ROM/Flash ROM (MBM29BL160D/161D/162D)

• SDRAM (FCRAM Type, CAS Latency 1 to 8, 2/4 bank products.)

• Address/Data multiplex bus (only 8/16-bit width)

• Basic bus cycle : 2 cycles

• Automatic wait cycle generation function can insert wait cycles, independently programmable for each memory

area.

• RDY input for external wait cycles

• Endian setting of byte ordering (Big/Little)

CS0 area only for big endian

• Prohibition setting of write (only for Read)

• Permission/prohibition setting of fetch into built-in cache

• Permission/prohibition setting of prefetch function

• DMA supports fly-by transfer with independent I/O wait control

• External bus arbitration can be used using BRQ and BGRNT.

3. Built-in memory

• 4 Kbytes DATA RAM

• 4 Kbytes RAM (MB91302A)

(Continued)

2

MB91301 Series

4. Instruction cache

• Size : 4 Kbytes

• 2-way set associative

• 128 blocks/way, 4 entries/block

• Lock function enables program code to be made cache-resident

• Areas not used for instruction cache can be used as instruction RAM

5. DMAC (DMA Controller)

• 5-channel (2-channel external-to-external)

• 3 transfer triggers : External pin, internal peripheral, software

• Capable of selecting an internal peripheral as a transfer source freely for each channel

• Addressing using 32-bit full addressing mode (increment, decrement, fixed)

• Transfer modes : Demand transfer, burst transfer, step transfer, or block transfer

• Supports fly-by transfer (between external I/O and memory)

• Selectable transfer data size : 8, 16, or 32-bit

6. Bit search module

• Searches words from MSB for position of first 1/0 bit value change

7. Reload Timers

• 16-bit timer : 3 channels

• Internal clock : 2 clock cycle resolution, divide by 2/8/32 selective

8. UART

• Full duplex, double buffer UART

• Independent 3 channels

• Data length : 7 bits to 9 bits (without parity) , 6 bits to 8 bits (with parity)

• Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable

Multi-processor mode

• Built-in 16-bit timer (U-TIMER) as a baud rate generator to generate arbitrary baud rates

• External clock can be used as transfer clock

• Variety of error detection functions (parity, frame, overrun)

9. Interrupt controller

• External interrupt input : 1 non-maskable interrupt pin and 8 normal interrupt pins (INT0 to INT7)

• Internal internal resources : UART, DMAC, A/D, U-TIMER, Delay interrupt, I²C, Free-run timer, Input capture

• Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt

10. A/D converter

• 10-bit resolution, 4 channels

• Successive approximation type, conversion time : 4.1 µs at 34 MHz

• Built-in sample and hold circuit

• Conversion modes : Single conversion mode, scan conversion mode and repeat conversion mode selectable

• Conversion triggers : Software, external trigger and built-in timer selectable

11. I²C* interface

• Internal 2-channels master/slave transmit/receive

• Internal arbitration function, clock synch function

12. Free-run timer

• 16 bit : 1channel

(Continued)

3

MB91301 Series

(Continued)

13. Input capture

• 4 channels

14. Other interval timers

• 16-bit timer : 3 channels (U-TIMER)

• PPG timer : 4 channels

• Watchdog timer : 1 channel

15. Other features

• Reset resources : watchdog timer/software reset/external reset (INIT pin)

• Power-saving modes : Stop mode, sleep mode

• Clock control

Gear function : Allows arbitrary different operating clock frequencies to be set for the CPU and peripherals.

You can select one of the 16 gear clock factors of 1/1 to 1/16. PLL multiplication can also be selected. Note,

however, that peripherals operate at a maximum of 34 MHz.

• CMOS technology : 0.25 µm

• Power supply (analog power supply): 3.3 V 0.3 V (internal regulator used)

* : Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use, these

components in an I²C system provided that the system conforms to the I²C Standard Specification as defined

by Philips.

■ PRODUCT LINEUP

MB91302A

MB91V301A

Evaluation version

(For evaluation and develop-

ment)

Mask ROM product

(for volume production)

Type

RAM

4 Kbytes

(only for data)

16 Kbytes

(data 8 KB+8 KB)

4 Kbytes

ROM has non-ROM model, the optimal real time

OS internal model*¹, and the IPL (Internal Program

Loader) internal model*²by adding the user ROM

model.

ROM

8 Kbytes (RAM)

DSU

⎯

DSU4

LQFP-144

(0.4 mm pitch)

Package

PGA-179

*1 : The Fujitsu product of real time OS REALOS/FR by conforming to the µITRON 3.0 is stored and optimized

with the MB91302A.

*2 : The ROM stores the IPL (Internal Program Loader) . Loading various programs can be executed from the

external system by the internal UART/SIO. Using this function, for example, writing on board to the Flash

memory connected to the external can be executed.

4

MB91301 Series

■ PIN ASSIGNMENTS

• MB91302A

(TOP VIEW)

1

108

P13/D11

P14/D12

P15/D13

P16/D14

P17/D15

DEOP1/PPG1/PB5

2

107

DACK1/TRG1/PB4

3

106

DREQ1/PB3

4

105

DEOP0/PB2

5

104

DACK0/PB1

6

103

V

SS

DREQ0/PB0

7

102

C

V

CC

8

101

P20/D16

P21/D17

P22/D18

P23/D19

P24/D20

P25/D21

P26/D22

P27/D23

V

SS

9

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

TIN2/TRG3/PH2

TIN1/PPG3/PH1

TIN0/PH0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

TRG0/PJ7

PPG0/PJ6

SCK1/PJ5

SOT1/PJ4

SIN1/PJ3

V

SS

CC

V

SCK0/PJ2

SOT0/PJ1

SIN0/PJ0

D24

D25

D26

D27

D28

D29

D30

D31

V

CC

INT7/SCK2/PG7

INT6/SOT2/PG6

INT5/SIN2/PG5

INT4/ATG/PG4/FRCK

INT3/PG3/ICU3

INT2/PG2/ICU2

INT1/PG1/ICU1

INT0/PG0/ICU0

AV^SS/AVRL

AN0

V

SS

CC

V

P80/RDY

P81/BGRNT

P82/BRQ

RD

AN1

DQMUU/WR0(UUB)

P85/DQMUL/WR1(ULB)

P86/DQMLU/WR2(LUB)

P87/DQMLL/WR3(LLB)

P90/SYSCLK

AN2

AN3

AVR

AVRH

AVCC

(FPT-144P-M12)

5

MB91301 Series

• MB91V301A

(TOP VIEW)

INDEX

5

178 174 172 168 165 161 160 156 155 151 150 145 142 140

179 177 173 169 166 162 157 154 149 148 144 139 134 133

1

2

7

10

15

16

20

21

25

26

30

33

37

39

43

50

4

2

176 171 167 163 159 153 147 143 138 137 132 129

180 175 170 164 158 152 146 141 135 131 128 127

3

9

3

4

130 126 124 123

125 122 121 120

119 118 117 116

113 114 112 115

107 108 109 111

101 102 104 110

5

13

14

19

22

27

31

34

38

42

44

52

8

6

1

136

12

18

24

28

32

36

41

47

49

55

11

17

23

29

35

40

45

48

54

60

6

7

8

9

10

11

12

13

14

15

91

85

81

79

78

96

90

86

83

82

98

93

92

87

84

103 106

99 105

94 100

46

51

53

58

61

56

57

59

65

62

63

64

66

68

69

67

70

74

73

72

71

80

77

76

75

89

88

97

95

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

(PGA-179C-A03)

6

MB91301 Series

• MB91V301A Pin No. Table

No.

E5

C3

C4

B3

A1

D5

A2

Pin Name

No.

31

32

33

34

35

36

37

B10

C10

A11

B11

D10

C11

A12

Pin Name

V^SS

No.

61

62

63

64

65

66

E15

G12

G13

G14

F15

G15

H14

Pin Name

A07

1

N.C.

2

P13/D11

V^SS

V^CC

V^SS

3

P80/RDY

P81/BGRNT

P82/BRQ

RD

V^CC

4

V^CC

A08

5

P14/D12

P15/D13

P16/D14

A09

6

A10

7

DQMUU/WR0 (UUB) 67

A11

P85/DQMUL/WR1

8

9

C5

B4

A3

P17/D15

V^SS

38

39

40

B12

A13

D11

68

H12

H13

H15

A12

A13

A14

(ULB)

P86/DQMLU/WR2

69

(LUB)

P87/DQMLL/WR3

10

V^CC

70

(LLB)

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

D6

C6

B5

B6

A4

A5

D7

C7

B7

A6

A7

B8

D8

C8

A8

A9

B9

C9

D9

A10

P20/D16

P21/D17

P22/D18

P23/D19

P24/D20

P25/D21

P26/D22

P27/D23

V^SS

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

C12

B13

A14

B14

D12

E11

C13

D13

C14

A15

E12

B15

E13

D14

C15

F12

F13

E14

F14

D15

V^SS

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

J15

J14

J13

J12

K15

K14

K13

L15

L14

K12

L13

M15

M14

N15

L12

M13

N14

P15

P14

M12

A15

V^SS

V^CC

P90/SYSCLK

V^CC

P91/MCLKE

P60/A16

P61/A17

P62/A18

P63/A19

SDA0/P64/A20

SCL0/P65/A21

SDA1/P66/A22

SCL1/P67/A23

V^CC

P92/MCLK

P93

V^SS

V^CC

P94/SRAS/LBA/AS

V^CC

P95/SCAS/BAA

D24

P96/SWE/WR

V^SS

D25

D26

V^CC

D27

A00

EWR3

V^SS

A01

EWR2

V^CC

A02

EWR1

D28

A03

EWR0

D29

A04

ECS

D30

A05

EMRAM

D31

A06

ICD3

(Continued)

7

MB91301 Series

(Continued)

No.

91

L11

N13

N12

P13

R15

M11

R14

N11

P12

R13

M10

N10

P11

P10

R12

R11

M9

Pin Name

ICD2

No.

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

P6

N6

R5

P5

M6

N5

R4

P4

R3

M5

N4

P3

R2

P2

M4

L5

Pin Name

SOT0/PJ1

SCK0/PJ2

SIN1/PJ3

SOT1/PJ4

SCK1/PJ5

PPG0/PJ6

TRG0/PJ7

TIN0/PH0

No.

151

152

153

154

155

156

157

158

L1

Pin Name

V^CC

92

ICD1

J4

INIT

93

ICD0

J3

NMI

94

V^SS

J2

V^SS

95

V^CC

K1

J1

V^CC

96

BREAK

ICLK

CS0/PA0

CS1/PA1

CS2/PA2

CS3/PA3

CS4/TRG2/PA4

CS5/PPG2/PA5

CS6/PA6

CS7/PA7

V^SS

97

H2

H4

H3

H1

G1

G2

G3

G4

F1

F2

F3

E1

E2

F4

E3

D1

D2

C1

E4

D3

C2

B1

B2

D4

98

ICS2

99

ICS1

TIN1/PPG3/PH1 159

TIN2/TRG3/PH2 160

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

ICS0

TRST

V^SS

161

162

163

164

165

166

C

AV^CC

DREQ0/PB0

DACK0/PB1

DEOP0/PB2

DREQ1/PB3

AVRH

AVR

V^CC

AN3

D00/P00

D01/P01

D02/P02

D03/P03

V^SS

AN2

N3

M3

N2

R1

L4

DACK1/TRG1/PB4 167

DEOP1/PPG1/PB5 168

N9

AN1

P9

AN0

IOWR/PB6

IORD/PB7

V^CC

169

170

171

172

173

174

175

176

177

178

179

180

R10

R9

AV^SS/AVRL

INT0/PG0/ICU0

INT1/PG1/ICU1

INT2/PG2/ICU2

INT3/PG3/ICU3

V^CC

P8

P1

L3

V^SS

D04/P04

D05/P05

D06/P06

D07/P07

V^SS

M8

X0

N8

M2

N1

K4

K3

L2

X1

R8

INT4/ATG/PG4/FRCK 145

V^SS

R7

INT5/SIN2/PG5

INT6/SOT2/PG6

INT7/SCK2/PG7

V^CC

146

147

148

149

150

V^CC

P7

MD0

MD1

MD2

V^CC

N7

D08/P10

D09/P11

D10/P12

M7

K2

M1

R6

SIN0/PJ0

8

MB91301 Series

■ PIN DESCRIPTIONS

• Except for Power supply, GND, and Tool pins

Pin no.

Pin name

I/O circuit

type

Function

MB91302A MB91V301A

External data bus bits 0 to 7. It is available in the

external bus mode.

D00 to D07

166 to 169,

132 to 139

J

172 to 175

Can be used as ports in 8-bit or 16-bit external bus

mode.

P00 to P07

External data bus bits 8 to 15.

It is available in the external bus mode.

D08 to D15

142 to 144, 178 to 180, 2,

1 to 5

5 to 8

Can be used as ports in 8-bit or 16-bit external bus

mode.

P10 to P17

External data bus bits 16 to 23.

It is available in the external bus mode.

D16 to D23

P20 to P27

D24 to D31

8 to 15

11 to 18

J

Can be used as ports in 8-bit external bus mode.

21 to 24,

27 to 30

External data bus bits 24 to 31.

It is available in the external bus mode.

18 to 25

C

External ready input. The pin has this function when

external ready input is enabled.

RDY

P80

28

29

33

J

General purpose input/output port. The pin has this

function when external ready input is disabled.

Acknowledge output for external bus release.

Outputs "L" when the external bus is released. The

pin has this function when output is enabled.

BGRNT

P81

34

General purpose input/output port. The pin has this

function when output is disabled for external bus

release acknowledge.

External bus release request input. Input "1" to

request release of the external bus. The pin has this

function when input is enabled.

BRQ

30

35

J

General purpose input/output port. The pin has this

function when the external bus release request

input is disabled.

P82

RD

31

32

36

37

C

External bus read strobe output.

External bus write strobe output. When WR is used

as the write strobe, this becomes the byte-enable

pin (UUB).

Select signal (DQMUU) of D31 to D24 at using of

SDRAM.

WR0/ (UUB) /

DQMUU

(Continued)

9

MB91301 Series

Pin no.

I/O circuit

type

Pin name

Function

MB91302A MB91V301A

External bus write strobe output. The pin has this

function when WR1 output is enabled. When WR is

used as the write strobe, this becomes the byte-

enable pin (ULB). Select signal (DQMUL) of D23 to

D16 at using of SDRAM.

WR1/ (ULB) /

DQMUL

33

34

35

38

39

40

J

General purpose input/output port. The pin has this

function when the external bus write-enable output

is disabled.

P85

External bus write strobe output. The pin has this

function when WR2 output is enabled. When WR is

used as the write strobe, this becomes the byte-

enable pin (LUB). Select signal (DQMLU) of D08 to

D05 at using of SDRAM.

WR2/ (LUB) /

DQMLU

General purpose input/output port. The pin has this

function when the external bus write-enable output

is disabled.

P86

External bus write strobe output. The pin has this

function when WR3 output is enabled. When WR is

used as the write strobe, this becomes the byte-

enable pin (LLB). Select signal (DQMLL) of D07 to

D00 at using of SDRAM.

WR3/ (LLB) /

DQMLL

General purpose input/output port. The pin has this

functions when the external bus write-enable output

is disabled.

P87

System clock output. The pin has this function when

system clock output is enabled. This outputs the

same clock as the external bus operating frequency.

(Output halts in stop mode.)

SYSCLK

36

37

43

40

C

J

General purpose input/output port. The pin has this

function when system clock output is disabled.

P90

MCLKE

P91

Clock enable signal for memory.

General purpose input/output port. The pin has this

function when clock enable output is disabled.

Memory clock output. The pin has this function

when memory clock output is enabled. This outputs

the same clock as the external bus operating

frequency. (Output halts in sleep mode.)

MCLK

38

39

45

46

C

General purpose input/output port. The pin has this

function when memory clock output is disabled.

P92

P93

General purpose input/output port.

(Continued)

10

MB91301 Series

Pin no.

I/O circuit

type

Pin name

Function

MB91302A MB91V301A

Address strobe output. The pin has this function

when ASE bit of port function register 9 is enabled

“1”.

AS

Address strobe output for burst flash ROM. The pin

has this function when ASE bit of port function

register 9 is enabled “1”.

LBA

SRAS

P94

40

49

J

RAS single for SDRAM. This pin has this function

when ASE bit of port function register 9 is enabled

“1”.

General purpose input/output port. The pin has this

function when ASE bit of port function register 9 is

"0" general purpose port.

Address advance output for burst Flash ROM. The

pin has this function when BAAE bit of port function

register (PFR9) is enabled.

BAA

CAS signal for SDRAM. This pin has this function

when BAAE bit of port function register (PFR9) is

enabled.

41

50

SCAS

P95

J

General purpose input/output port. The pin has this

function when BAAE bit of port function register is

general purpose port.

Memory write strobe output. This pin has this

function when WRXE bit of port function register is

enabled.

WR

SWE

P96

Write output for SDRAM. This pin has this function

when WRXE bit of port function register is enabled.

42

51

J

General purpose input/output port. This pin has this

function when WRXE bit of port function register is

general purpose port.

45 to 52

55 to 62

54 to 61

64 to 71

A00 to A07

A08 to A15

C

External address bits 0 to 7.

External address bits 8 to 15.

External address bits 16 to 19. It is available in

external bus mode.

A16 to A19

P60 to P63

64 to 67

74 to 77

J

Can be used as ports when external address bus is

not used.

(Continued)

11

MB91301 Series

Pin no.

I/O circuit

type

Pin name

Function

MB91302A MB91V301A

Data input pin for I²C bus function. This function is

enable when typical operation of I²C is enable. The

port output must remains off unless intentionally

turned on. (Open drain output) (This function is only

for MB91302A, MB91V301A.)

SDA0

68

69

70

78

79

80

T

External address bus bit 20.

A20

P64

This function is enable during prohibited I²C

operation and using external bus.

General-purpose I/O port.

This function is enable during prohibited I²C and

nonused external address bus.

CLK input pin for I²C bus function. This function is

enable when typical operation of I²C is enable. The

port output must remains off unless intentionally

turned on. (open drain output) (This function is only

for MB91302A, MB91V301A.)

SCL0

External address bus bit 21.

This function is enable during prohibited I²C

operation and using external bus.

A21

P65

General-purpose I/O port.

This function is enable during prohibited I²C and

nonused external address bus.

DATA input pin for I²C bus function. This function is

enable when typical operation of I²C is enable. The

output must remains off unless intentionally turned

on. (open drain output) (This function is only for

MB91302A, MB91V301A.)

SDA1

External address bus bit 20.

This function is enable during prohibited I²C

operation and using external bus.

A22

P66

General-purpose I/O port.

This function is enable during prohibited I²C and

nonused external address bus.

(Continued)

12

MB91301 Series

Pin no.

I/O circuit

type

Pin name

Function

MB91302A MB91V301A

CLK input pin for I²C bus function. This function is

enable when typical operation of I²C is enable. The

port output must remains off unless intentionally

turned on. (open drain output) (This function is only

for MB91302A, MB91V301A.)

SCL1

71

81

T

External address bus bit 21.

This function is enable during prohibited I²C

operation and using external bus.

A23

General-purpose I/O port.

P67

This function is enable during prohibited I²C

operation and nonused external address bus.

76 to 79

81 to 84

106 to 109

111 to 114

AN3 to AN0

D

V

Analog input pin.

External interrupt inputs. These inputs are used con-

tinuously when the corresponding external

interrupt is enabled. In this case, do not output to

these ports unless doing so intentionally.

INT0 to INT3

PG0 to PG3

ICU0 to ICU3

General purpose input/output ports.

Input capture input pins. These inputs are used con-

tinuously when selected as input capture inputs. In

this case, do not output to these ports unless

doing so intentionally.

External interrupt input. These inputs are used

continuously when the corresponding external

interrupt is enabled. In this case, do not output to

these ports unless doing so intentionally.

INT4

External trigger input for A/D converter. This input is

used continuously when selected as the A/D

converter start trigger. In this case, do not output to

this port unless doing so intentionally.

ATG

PG4

85

115

V

General purpose input/output ports.

External clock input pin for free-run timer. This input

is used continuously when selected as the external

clock input pin for the free-run timer. In this case, do

not output to this port unless doing so intentionally.

FRCK

External interrupt input. These inputs are used

continuously when the corresponding external

interrupt is enabled. In this case, do not output to

these ports unless doing so intentionally.

INT5

86

116

V

UART2 data input pin. This input is used continuous-

ly when UART2 is performing input. In this case, do

not output to this port unless doing so intentionally.

SIN2

PG5

General purpose input/output port.

(Continued)

13

MB91301 Series

Pin no.

I/O circuit

type

Pin name

Function

MB91302A MB91V301A

External interrupt input. This input is used

continuously when the corresponding external

interrupt is enabled. In this case, do not output to

these ports unless doing so intentionally.

INT6

87

117

V

UART2 data output pin. The pin has this function

when UART2 data output is enabled.

SOT2

PG6

General purpose input/output port.

External interrupt input. This input is used

continuously when the corresponding external

interrupt is enabled. In this case, do not output to

these ports unless doing so intentionally.

INT7

88

90

118

120

V

U

UART2 clock input/output pin. The pin has this

function when UART2 clock output is enabled.

SCK2

PG7

General purpose input/output port.

UART0 data input pin. This input is used continuously

when UART0 is performing input. In this case, do not

output to this port unless doing so intentionally.

SIN0

PJ0

SOT0

PJ1

General purpose input/output port.

UART0 data output pin. The pin has this function

when UART0 data output is enabled.

91

92

121

122

U

General purpose input/output port.

UART0 clock input/output pin. The pin has this

function when UART0 clock output is enabled.

SCK0

PJ2

General purpose input/output port.

UART1 data input pin. This input is used continuously

when UART1 is performing input. In this case, do not

output to this port unless doing so intentionally.

SIN1

93

123

U

PJ3

SOT1

PJ4

General purpose input/output port.

UART1 data output pin. The pin has this function

when UART1 data output is enabled.

94

95

96

124

125

126

U

General purpose input/output port.

UART1 clock input/output pin. The pin has this

function when UART1 clock output is enabled.

SCK1

PJ5

General purpose input/output port.

PPG timer output. This pin has this function when

PPG0 output is enabled.

PPG0

PJ6

General purpose input/output port.

(Continued)

14

MB91301 Series

Pin no.

I/O circuit

type

Pin name

Function

MB91302A MB91V301A

External trigger input for PPG timer.

This input is used continuously when the

corresponding timer input is enabled. In this case, do

not output to this port unless doing so intentionally.

TRG0

PJ7

97

98

127

128

U

J

General purpose input/output port.

Reload timer input. This input is used continuously

when the corresponding timer input is enabled. In

this case, do not output to this port unless doing so

intentionally.

TIN0

PH0

TIN1

General purpose input/output port.

Reload timer input. This input is used continuously

when the corresponding timer input is enabled. In

this case, do not output to this port unless doing so

intentionally.

99

129

J

PPG timer output. The pin has this function when

PPG3 output is enabled.

PPG3

PH1

General purpose input/output port.

Reload timer input. This input is used continuously

when the corresponding timer input is enabled. In

this case, do not output to this port unless doing so

intentionally.

TIN2

100

103

130

133

J

External trigger input for PPG timer. This input is

used continuously when the corresponding timer

input is enabled. In this case, do not output to this

port unless doing so intentionally.

TRG3

PH2

General purpose input/output port.

External input for DMA transfer requests. This input

is used continuously when selected as a DMA

activation trigger. In this case, do not output to this

port unless doing so intentionally.

DREQ0

PB0

DACK0

PB1

General purpose input/output port.

External acknowledge output for DMA transfer

requests. The pin has this function when outputting

DMA transfer request acknowledgement is enabled.

104

105

134

135

J

General purpose input/output port.

Completion output for DMA external transfer. The

pin has this function when outputting DMA transfer

completion is enabled.

DEOP0

PB2

General purpose input/output port.

(Continued)

15

MB91301 Series

Pin no.

I/O circuit

type

Pin name

Function

MB91302A MB91V301A

DMA External input for DMA transfer requests. This

input is used continuously when selected as a DMA

activation trigger. In this case, do not output to this

port unless doing so intentionally.

DREQ1

106

136

J

General purpose input/output port. The pin has this

function when completion output and stop input are

disabled for DMA transfer.

PB3

External acknowledge output for DMA transfer

requests. The pin has this function when outputting

DMA transfer request acknowledgement is enabled.

DACK1

External trigger input for PPG timer. This input is

used continuously when the corresponding timer

input is enabled. In this case, do not output to this

port unless doing so intentionally.

107

108

137

138

J

TRG1

PB4

General purpose input/output port.

Completion output for DMA external transfer. The

pin has this function when outputting DMA transfer

completion is enabled.

DEOP1

PPG timer output. The pin has this function when

PPG1 bit is enabled.

PPG1

PB5

General purpose input/output port.

Write strobe output for DMA fly-by transfer. The pin

has this function when outputting a write strobe for

DMA fly-by transfer is enabled.

IOWR

PB6

109

110

139

140

J

General purpose input/output port. The pin has this

function when outputting a write strobe for DMA

fly-by transfer is disabled.

Read strobe output for DMA fly-by transfer. The pin

has this function when outputting a read strobe for

DMA fly-by transfer is disabled.

IORD

PB7

General purpose input/output port. The pin has this

function when outputting a write strobe for DMA

fly-by transfer is disabled.

112

113

143

144

X0

X1

A

Clock (oscillation) input.

Clock (oscillation) output.

Mode pins 0 to 2. The levels applied to these pins

set the basic operating mode. Connect V^CCor V^SS.

116 to 118

147 to 149

MD0 to MD2

G

External reset input (Reset to initialize settings)

(“L” active)

119

120

152

053

INIT

NMI

B

M

NMI (Non Maskable Interrupt) input (“L” active)

(Continued)

16

MB91301 Series

(Continued)

Pin no.

MB91302A MB91V301A

I/O circuit

type

Pin name

Function

Chip select 0 output. The pin has this function when

chip select 0 output is enabled.

CS0

PA0

CS1

PA1

CS2

PA2

CS3

PA3

CS4

122

123

124

125

156

157

158

159

J

General purpose input/output port. The pin has this

function when chip select 0 output is disabled.

Chip select 1 output. The pin has this function when

chip select 1 output is enabled.

General purpose input/output port. The pin has this

function when chip select 1 output is disabled.

Chip select 2 output. The pin has this function when

chip select 2 output are enabled.

General purpose input/output port. The pin has this

function when chip select 2 output is disabled.

Chip select 3 output. The pin has this function when

chip select 3 output are enabled.

General purpose input/output port. The pin has this

function when chip select 3 output is disabled.

Chip select 4 output. The pin has this function when

chip select 4 output is enabled.

External trigger input for PPG timer. This input is

used continuously when the corresponding timer

input is enabled. In this case, do not output to this

port unless doing so intentionally.

126

160

TRG2

J

General purpose input/output port. The pin has this

function when chip select 4 output is disabled.

PA4

CS5

Chip select 5 output. The pin has this function when

chip select 5 output are enabled.

PPG timer output. The pin has this function when

PPG2 bit is enabled.

PPG2

127

161

J

General purpose input/output port. The pin has this

function when chip select 5 output and PPG timer

output are disabled.

PA5

Chip select 6 output. The pin has this function when

chip select 6 output is enabled.

CS6

PA6

CS7

PA7

128

129

162

163

J

General purpose input/output port. The pin has this

function when chip select 6 output are disabled.

Chip select 7 output. The pin has this function when

chip select 7 output are enabled.

General purpose input/output port. The pin has this

function when chip select 7 output is disabled.

17

MB91301 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

•Oscillation feedback resistance

approx. 1 MΩ

X1

Clock input

A

X0

Standby control

•CMOS hysteresis input with pull-up

resistor

P-ch

N-ch

P-ch

B

Digital input

•CMOS level I/O with standby control

•I^OL= 4 mA

P-ch

Digital output

N-ch

C

Digital input

Standby control

•Analog input

With switch

P-ch

N-ch

D

Analog input

Control

(Continued)

18

MB91301 Series

Type

Circuit

Remarks

•CMOS level output

No standby control

P-ch

N-ch

G

Digital input

•With Pull-up control

•CMOS level I/O

with standby control

•With Pull-up control

•I^OL= 4 mA

Pull-up control

Digital output

P-ch

N-ch

Digital output

Digital input

J

Standby control

•With Pull-up control

•CMOS level output

CMOS level hysteresis input

with standby control

•I^OL= 4 mA

Pull-up control

Digital output

P-ch

N-ch

Digital output

Digital input

K

Standby control

•With Pull-up control

•CMOS level output

CMOS level hysteresis input

no standby control

•I^OL= 4 mA

Pull-up control

Digital output

P-ch

N-ch

P-ch

L

Digital output

Digital input

•CMOS level hysteresis input

no standby control

P-ch

N-ch

M

Digital input

(Continued)

19

MB91301 Series

Type

Circuit

Remarks

•Output buffer

•CMOS level output

•I^OL= 4 mA

P-ch

N-ch

Digital output

N

•Input buffer

•CMOS level input

O

Digital input

•Input buffer with pull-down

•Pull-down resistor value = 25 kΩ

approx. (Typ)

P

N-ch

•Input buffer with Pull-up

P-ch

Q

Digital input

•I/O buffer with pull-down

•CMOS level output

•I^OL= 4 mA

P-ch

Digital output

N-ch

R

N-ch

Digital input

•I/O buffer

•CMOS level output

•I^OL= 4 mA

P-ch

Digital output

N-ch

S

Digital output

Digital input

(Continued)

20

MB91301 Series

(Continued)

Type

Circuit

Remarks

•N-ch open-drain output

•CMOS level I/O with standby control

•Without pull-up control

•I^OL= 4 mA

Pull-up control

P-ch

N-ch

Digital output with

open-drain control

Digital output

T

Digital input

•CMOS level output

•CMOS level hysteresis input

with standby control

•5 V tolerant

P-ch

N-ch

Digital output

•I^OL= 4 mA

U

Digital input

•CMOS level output

•CMOS level hysteresis input

with standby control

•5 V tolerant

P-ch

N-ch

Digital output

•I^OL= 4 mA

V

Digital input

21

MB91301 Series

■ HANDLING DEVICES

■MB91301 series

• Operation at start-up

Always apply a settings initialization (INIT) to the INIT pin immediately after turning on the power.

Also, in order to provide a delay while the oscillator circuits stabilize immediately after start-up, maintain the “L”

level input to the INIT pin for the required stabilization delay time. (The initialization processing (INIT) triggered

by the INIT pin initializes the oscillation stabilization delay time to the minimum setting.)

• External clock input at start-up

At power-on start-up, always input a clock signal until the oscillation stabilization delay time is ended.

• Output indeterminate at power-on time

When the power is turned on, the output pin may remain indeterminate until the internal power supply becomes

stable.

• Built-in DC/DC regulator

This device has a built-in regulator, requiring 3.3 V input to the Vcc pin and a bypass capacitor of approximately

4.7 µF connected to the C pin for the regulator.

3.3 V

VCC

C

AVCC

4.7 µF

AVRH

AVR

V^SS

0.05 µF

AV^SS/AVRL

MB91301 series

VSS

GND

Note of built-in DC/DC regulator

• Note on use of the A/D converter

As the MB91301 series contains an A/D converter, be sure to supply power to AVcc at 3.3 V and insert a capacitor

of at least 0.05 µF between the AVR pin and the AVss/AVRL pin.

3.3 V

AVCC

AVRH

AVR

0.05 µF

AV^SS/AVRL MB91301 series

Note on Use of A/D Converter

22

MB91301 Series

• Preventing Latchup

When CMOS integrated circuit devices are subjected to applied voltages higher than V^CCat input and output

pins, or to voltages lower than V^SS, as well as when voltages in excess of rated levels are applied between V^CC

and V^SS, a phenomenon known as latchup can occur. When a latchup condition occurs, the supply current can

increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take

sufficient care to avoid exceeding maximum ratings.

• Power supply pins

Devices with multiple V^CCand V^SSsupply pins are designed to prevent problems such as latchup occurring by

providing internal connections between pins at the same potential. However, in order to reduce unwanted

radiation, prevent abnormal operation of strobe signals due to a rise in ground level, and to maintain the total

output current ratings, all such pins should always be connected externally to power supply or ground. Also,

ensure that the impedance of the V^CCand V^SSconnections to the power supply are as low as possible.

In addition, it is recommended that a bypass capacitor of approximately 0.1µF be connected between V^CCand

V^SS. Connect the capacitor close to the V^CCand V^SSpins.

• Crystal oscillators

Noise in proximity to the X0 and X1 pins can cause abnormal operation in this device. Printed circuit boards

should be designed so that the X0 and X1 pins, crystal (or ceramic) oscillator, and bypass capacitor connected

to ground are placed as close together as possible.

Also, to ensure stable operation, it is strongly recommended that the printed circuit board art work be designed

such that the X0 and X1 pins are surrounded by ground.

Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.

• Treatment of NC and OPEN pins

Pins marked as "NC" or "OPEN" must be left open-circuit.

• Treatment of unused input pins

If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected

to pull-up or pull-down resistors.

• Mode pins (MD0 to MD2)

These pins should be connected directly to V^CCor V^SS. To prevent the device erroneously switching to test mode

due to noise, design the printed circuit board such that the distance between the mode pins and V^CCor V^SSis

as short as possible and the connection impedance is low.

• Remarks for External Clock Operation

When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to

X0 must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin stops at

“H” output in stop mode) .

When operating at 12.5 MHz or less, the microcontroller can be used with the clock signal supplied only to pin X0.

“Using an external clock (normal) and (12.5 MHz) ” shows examples of how the MB91301 uses the external clock.

23

MB91301 Series

X0

X1

MB91301 series

Note: Stop mode (oscillation stop mode) can not be used.

Using an external clock (normal)

X0

X1

OPEN

MB91301 series

Using an external clock (12.5 MHz Max)

• Notes on during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even

when there is no external oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed.

• Clock control block

For L-level input to the INIT pin, allow for the regulator settling time or oscillation settling time.

• Bit search module

The 0-detection, 1-detection, and transition-detection data registers (BSD0, BSD1, and BSDC) are only word-

accessible.

• I/O port access

Byte access only for access to port

• Shared port function switching

To switch a pin that also serves as a port, use the port function register (PFR). Note, however, that bus pins are

switched depending on external bus settings.

• D-bus memory

Do not set a code area in D-bus memory.

No instruction fetch is performed to the D-bus.

Instruction fetches to the D-bus area result in incorrect data interpreted as code, which can cause the micro-

controller to lose control.

Do not set a data area in I-bus memory.

24

MB91301 Series

• I-bus memory

Do not set a stack area or vector table in I-bus memory.

It may cause a hang during EIT processing (including RETI).

Recovery from the hang requires a reset.

Do not perform DMA transfer to I-bus memory.

• Low-power consumption modes

• To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the

TBCR, or time-base counter control register) and be sure to use the following sequence:

(LDI

STB

#value_of_standby, R0)

#_STCR, R12)

R0, @R12

; Write to standby control register (STCR)

; Read STCR for synchronous standby

; Read STCR again for dummy read

; NOP x 5 for timing adjustment

LDUB @R12, R0

NOP

• If you use the monitor debugger, follow the precautions below:

Do not set a breakpoint within the above array of instructions.

Do not single-step the above array of instructions.

• Prefetch

When accessing a prefetch-enabled little endian area, use word access only (access in 32 bits).

Byte or halfword access results in wrong data read.

• MCLK and SYSCLK

MCLK causes a stop in SLEEP/STOP mode while SYSCLK causes a stop only in STOP mode. Use either

depending on each application.

• Pull-up control

When function pins listed in the AC specifications (such as external bus control pins) have pull-up control,

enabling the pull-up resistor for a pin causes the actual pin load conditions to change. As all AC specifications

for this device were measured under the condition of pull-up resistors disabled, the values are not guaranteed

of AC specifications when pull-up resistors are enabled.

Even if the pull-up resistor is set to enabled for a pin, if the HIZ bit in the standby control register (STCR) specifies

setting output pins to high impedance during stop mode (HIZ = 1) , changing to stop mode (STOP = 1) causes

the pull-up resistor to be disabled.

25

MB91301 Series

• R15 (General purpose register)

When any of the following instructions is executed, the SSP* or USP* value is not used as R15, resulting in an

incorrect value written to memory.

AND

OR

EOR

R15, @Ri

ANDH

ORH

EORH

R15, @Ri

ANDB R15, @Ri

ORB R15, @Ri

EORB R15, @Ri

XCHB @Rj, R15

* : R15 is a virtual register. When a program attempts to access R15, the SSP or USP is accessed depending

on the status of the “S” flag as an SP flag. When coding the above ten instructions using an assembler,

specify a general-purpose register other than R15.

• RETI instruction

Please do not neither control register of the instruction cache nor the data access to RAM of the instruction

cache immediately before the instruction of RETI.

• Notes on the PS register

Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt

handler to break or the PS flag to update its display setting when the debugger is being used. As the microcon-

troller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs oper-

ations before and after the EIT as specified in either case.

• The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS

instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data

event or emulator menu:

(1) D0 and D1 flags are updated earlier.

(2) The EIT handler (user interrupt/NMI or emulator) is executed.

(3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are

updated to the same values as those in (1) above.

• The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed

to enable interruptions when a user interrupt or NMI trigger event has occurred.

(1) The PS register is updated earlier.

(2) The EIT handler (user interrupt/NMI or emulator) is executed.

(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the

same value as that in (1) above.

• A/D converter

When the device is turned on or returns from a reset or stop, it takes time for the external capacitor to be charged,

requiring the A/D converter to wait for at least 10 ms.

• Watchdog timer

The watchdog timer function of this model monitors that a program delays a reset within a certain period of time

and resets the CPU if the program fails to delay it, for example, because the program runs out of control. Once

the watchdog timer function is enabled, therefore, the watchdog timer continues to operate until a reset takes

place.

An exception, for example during stop, sleep and DMA transfer modes, is the automatic delaying of a reset under

a condition in which the CPU stops program execution.

Note, however, that a watchdog reset may not occur in the above state caused when the system runs out of

control. If this is the case, use the external INIT pin to cause a reset (INIT) .

26

MB91301 Series

■Unique to the evaluation chip MB91V301A

• Tool reset

On an evaluation board, use the chip with INIT and TRST connected together.

• Simultaneous occurrences of a software break and a user interrupt/NMI

When a software break and a user interrupt /NMI take place at the same time, the emulator debugger can cause

the following phenomena:

• The debugger stops pointing to a location other than the programmed breakpoints.

• The halted program is not re-executed correctly.

If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has

been used, avoid setting any break at the relevant location.

• Single-stepping the RETI instruction

If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly

after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being

executed. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant

interrupt routine becomes unnecessary, perform debugging with that interrupt disabled.

• Operand break

A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data

event break to access to the area containing the address of a system stack pointer.

• ICE startup sequence

When using the ICE, when you start debugging, ensure that the bus configuration is set correctly for the area

being used before downloading. After turning on the power to the target, the states of the RD and WR0 to WR3

pins are undefined until you perform the above setting. Accordingly, include enabling pull-up as part of the startup

sequence. If using these pins as general-purpose ports, set as output ports to prevent conflict with the output

signals during the time the pin states are undefined.

External bus width

32 bit

16 bit

8 bit

Pin name

RD

Pull-up

WR0

Pull-up

WR1 (P85)

WR2 (P86)

WR3 (P87)

* : Use as output ports.

Pull-up

*

27

MB91301 Series

• Configuration batch file

The example batch file below sets the mode vector and sets up the CS0 configuration register for the download

area. Use values appropriate to the hardware in the wait, timing, and other settings.

#---------------------------------------------------------

# Set MODR (0x7fd) =Enable In memory+16 bit External Bus

set mem/byte 0x7fd=0x5

#---------------------------------------------------------

# Set ASR0 (0x640); 0x0010_0000 - 0x002f_ffff

set mem/halfword 0x640=0x0010

#---------------------------------------------------------

# Set ACR0 (0x642)

#

; ASZ [3:0]=0101:2 Mbytes

#

; DBW [1:0]=01:16 bit width, automatically set from

MODR

#

; BST [1:0]=00:1 burst (16 bit x 2)

; SREN=0:Disable BRQ

; PFEN=1:Enable Pre fetch buffer

; WREN=1:Enable Write operation

; LEND=0: Big endian

; TYPE [3:0]=0010:WEX: Disable RDY

set mem/harfword 0x642=0x5462

#---------------------------------------------------------

# Set AWR0 (0x660)

#

; W15-12=0010:auto wait=2

; WR07, 06=01:RD, WR delay=1cycle

; W05, 04=01:WR->WR delay=1cycle (for WEX)

; W03 =1:MCLK->RD/WR delay=0.5cycle

;

:for async Memory

; W02 =0:ADR->CS delay=0

; W01 =0:ADR->RD/WR setup 0cycle

; W00 =RD/WR->ADR hold 0cycle

set mem/halfword 0x660=0x2058

#---------------------------------------------------------

• Emulation memory

If SRAM as the emulation memory is built on target board, SRAM for be accessed by RD, WR signal, and +BYTE

control signal can not be used. (The external bus is initialized to the bus mode for accessing RD, WRn after reset.)

28

MB91301 Series

■ BLOCK DIAGRAM

• MB91302A, MB91V301A

FR CPU

Core

Instruction Cache

4 KB

DREQ0, DREQ1

DACK0, DACK1

32

DMAC

5 channels

DEOP0, DEOP1

IOWR

Bit search module

IORD

MB91302A : RAM 4 KB

MB91V301A : RAM 8 KB (stack)

A23 to A00

D31 to D16

D15 to D00

RD, WR

WR0 to WR3

CS0 to CS7

RDY

Bus

Converter

MB91302A : ROM 4 KB*

MB91V301A : RAM 8 KB

32

External memory

I/F

16

Adapter

32

BRQ

X0, X1

BGRNT

SYSCLK

MCLK

MD0 to MD2

INIT

Clock

control

AS

16

MCLKE

Interrupt

controller

SRAS

SCAS

SWE

SDRAM I/F

8 channels

External interrupts

INT0 to INT7

NMI

DQMUU, L

DQMLU,L

LBA

SIN0 to SIN2

SOT0 to SOT2

SCK0 to SCK2

BAA

3 channels

UART

4 channels

PPG timer

PPG0 to PPG3

TRG0 to TRG3

3 channels

U-TIMER

PORT

PORT I/F

AN0 to AN3

ATG

AVRH, AVCC

AVSS/AVRL

4 channels

A/D converter

2 channels

I²C I/F

SDA0, SDA1

SCL0, SCL1

3 channels

TIN0 to TIN2

Reload timer

FRCK

Free Run Timer

4 channels

Input Capture

ICU0 to ICU3

* : ROM has non-ROM model, the optimal real time OS internal model, and the IPL (Internal Program

Loader) internal model by adding the user ROM model.

29

MB91301 Series

■ CPU

1. Memory Space

The FR family has 4 Gbytes (2³²addresses) of logical address space with linear access from the CPU.

• Direct Addressing Areas

The following areas of address space are used for I/O operations.

These areas are called direct addressing areas, in which the address of an operand can be specified directly

during an instruction.

The direct areas differ according to the size of the data accessed, as follows.

→ byte data access

→ half word data access : 000^Hto 1FF^H

→ word data access : 000^Hto 3FF^H

: 000^Hto 0FF^H

30

MB91301 Series

• Memory map

(MB91302A)

(Single chip

mode)

(MB91302A)

Internal ROM

External bus

mode

(MB91302A)

External ROM

External bus

mode

(MB91V301A)

External ROM

External bus

mode

Internal ROM

External bus mode

(MODR register at

ROAM = 1)

0000 0000

H

Direct

addre

ssing

area

Direct

addre

ssing

area

addre

ssing

area

addre

ssing

area

addre

ssing

area

I/O

0000 0400

H

see

“■I/O

MAP”

I/O

see

“■I/O

MAP”

I/O

see

“■I/O

MAP”

I/O

see

“■I/O

MAP”

I/O

see

“■I/O

MAP”

I/O

0001 0000

H

1

∗

I-RAM

0002 0000

Access

prohibited

Access

prohibited

Access

prohib-

ited

Access

prohib-

ited

Access

prohib-

ited

0003 E000

H

Internal

RAM

8 Kbytes

Internal

RAM

8 Kbytes

0003 F000

H

Internal

RAM

Internal

RAM

Internal

RAM

4 Kbytes

0004 0000

H

Internal

RAM

8 Kbytes

0004 2000

H

External

area

Access

prohibit-

ed

Access

prohib-

ited

0006 0000

H

000E 0000

H

External

area

External

area

External

area

Access

prohib-

ited

000F E000

H

Internal

RAM

8 Kbytes

emula-

tion

000F F000

H

Internal

ROM

4Kbytes*²

Internal

ROM

4Kbytes*²

0010 0000

H

Access

prohib-

ited

External

area

External

area

External

area

External

area

FFFF FFFF

H

MB91302A has non-ROM model, the optimal real time OS internal model, and the IPL (Internal program Loader)

internal model by adding the user ROM model.

*1 : On specific area between 10000^Hand 2000^H, 4 Kbytes RAM can be used.

Refer to “■INSTRUCTION CACHE”.

*2 : The real time OS internal model stores the real time OS kernel. The program loader internal model stores

the program loader.

Note : Internal ROM emulation : only MB91V301A

Note : Each mode is set depending on the mode vector fetch after INIT is negated. (For mode setting, see “■MODE

SETTINGS”.)

31

MB91301 Series

2. Registers

The FR series has two types of registers: application-specific registers in the CPU and general purpose registers

in memory.

• Dedicated registers

Program counter (PC)

: 32-bit register. Stores the current instruction address.

Program status (PS)

: 32-bit register. Contains the register pointer and condition code.

Table base register (TBR)

: Stores the top address of the vector table used by the EIT (exception/interrupt/

trap) function.

Return pointer (RP)

: Stores the subroutine return address.

System stack pointer (SSP) : Points to the system stack area.

User stack pointer (USP)

: Points to the user stack area.

Multiplication and division

result register (MDH/MDL)

: 32-bit registers used for multiplication and division.

Initial value

32 bit

PC

XXXX XXXXH

Program counter

Program status

PS

TBR

RP

000F FC00H

XXXX XXXXH

0000 0000H

XXXX XXXXH

Table base register

Return pointer

SSP

USP

System stack pointer

User stack pointer

MDH

MDL

XXXX XXXXH

Multiplication and division

result register

• PC (Program Counter)

The PC is the program counter and stores the address of the currently executing instruction.

31

0

PC

• Table base register (TBR)

The TBR is the table base register and stores the top address of the vector table used by the EIT function.

31

0

TBR

32

MB91301 Series

• Return pointer (RP)

The RP is the return pointer and stores the subroutine return address.

31

0

RP

• System stack pointer (SSP)

The SSP is the system stack pointer and functions as R15 when the S flag is “0”.

31

0

SSP

• User stack pointer (USP)

The USP is the user stack pointer and functions as R15 when the S flag is “1”.

31

0

USP

• Multiplication and division result register (MDH/MDL)

MDH/MDL : 32-bit registers used for multiplication and division.

MDH

MDL

: Remainder

: Quotient

31

0

MDH

MDL

Multiplication and division result register

33

MB91301 Series

• Program status (PS)

This register holds the program status and is divided into the ILM, SCR, and CCR.

31

20

16

10

0

Bit position→

8 7

⎯

ILM

SCR

CCR

PS

• Condition code register (CCR)

S flag

: Specifies which stack pointer to use as R15.

I flag

: Enables or disables user interrupt requests.

N flag

Z flag

V flag

: Indicates the sign when an operation result is represented as a “2” complement integer.

: Indicates whether an operation result is “0”.

: Indicates whether an overflow occurred for an operation result when the operation operand is

represented as a “2” complement integer.

C flag

: Indicates whether an operation resulted in a borrow or a carry from the most significant bit.

7

6

5

4

I

3

2

Z

1

0

Initial Value

- - 00XXXX^B

⎯

S

N

V

C

CCR

• System condition code register (SCR)

D1, D0 flags : Stores intermediate data for stepwise multiplication operations.

T flags

: A flag specifying whether the step trace trap function is enabled or not.

10

9

8

T

Initial Value

XX0^B

D1 D0

SCR

• Interrupt level mask register(ILM)

ILM4 to ILM0 : This register stores the interrupt level mask value. The value in the ILM register is used as

the level mask. Only interrupt requests to the CPU that have an interrupt level that is higher

than the level specified in ILM are accepted.

20

ILM4

0

19

ILM3

0

18

ILM2

0

17

ILM1

0

16

Initial Value

01111^B

ILM0 Interrupt Level

0

1

0

High

• • •

0

• • •

15

↑

(Medium)

↓

0

1

0

• • •

1

• • •

31

1

Low

ILM

34

MB91301 Series

■ GENERAL PURPOSE REGISTERS

General purpose registers R0 to R15 are used by the CPU. The registers are used as the accumulator and

memory access pointers for CPU operations.

32-bit

Initial Value

XXXX XXXXH

R0

R1

R12

R13

R14

R15

AC (Accumulator)

FP (Frame Pointer)

SP (Stack Pointer)

XXXX XXXXH

0000 0000H

The following three registers are treated as having special meanings to enhance the operation of some instruc-

tions.

R13 : Virtual accumulator (AC)

R14 : Frame pointer (FP)

R15 : Stack pointer (SP)

The values of R0 to R14 after a reset are undefined. R15 is initialized to 0000 0000^H(SSP value) .

35

MB91301 Series

■ MODE SETTINGS

In the FR series, the mode is set by the mode pins (MD2, MD1, and MD0) and mode register (MODR).

1. Mode Pins

The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed.

Mode Pins

Reset vector access

Mode name

Remarks

area

MD2 MD1 MD0

0

Internal ROM vector mode

External ROM vector mode

Internal

Single-chip mode*

The bus width is specified by the

mode register.

0

1

External

Values other than those listed in the table are prohibited.

* : Single chip mode is able to set only MB91302A.

2. Mode Register (MODR)

• Details of mode register (MODR)

The data written to the mode register by the mode vector fetch operation (see “3.11.3 reset sequences”) is

called the mode data.

After the data is set to the mode register (MODR), the device operates with the operating mode specified by

this data. The mode register is set by all types of reset. The register cannot be written to by user programs.

Operation mode setting bits

Initial Value

23

22

21

20

19

18

17

16

bit

Address

⎯

ROMA WTH1 WTH0

XXXXXXXX^B

W

Operation mode setting bits

Initial Value

31

30

29

28

27

26

25

24

bit

Address

⎯

ROMA WTH1 WTH0

XXXXXXXX^B

W

Bit31 to bit24 are all reserved bits.

Be sure to set this bit to “00000.”

Operation is not guaranteed when any value other than “00000.” is set.

36

MB91301 Series

• Operating mode

Bus mode

Single chip

Access mode

Internal ROM external bus

32-bit bus width

16-bit bus width

8-bit bus width

External ROM external bus

• Bus mode

The bus mode controls the operations of internal ROM and the external access function. It is specified with

the mode setting pins (MD2, MD1, and MD0) and the ROMA bit in mode data.

• Access mode

The access mode controls the external data bus width. It is specified with the WTH1 and WTH0 bits in the

mode register and the DBW1 and DBW0 bits in area configuration registers 0 to 7 (ACR0 to ACR7).

• Bus Modes

The FR family has three bus modes: bus mode 0 (single-chip mode), bus mode 1 (internal-ROM, external-bus

mode), and bus mode 2 (external-ROM, external-bus mode).

The MB91V301A supports only bus mode 2 (external-ROM, external-bus mode).

See “1. Memory Space” in ■CPU for details.

• Bus mode0 (single chip mode) (only MB91302A)

The internal I/O, 4 Kbytes D-bus RAM, 32 Kbytes F-bus RAM (FRAM) and 96 Kbytes F-bus ROM are valid,

while access to any other areas is invalid under this mode. The function of external pin is peripheral or general-

purpose port. The pin can not be used as the bus pin.

• Bus mode 1 (internal ROM external bus mode)

The internal I/O, D-bus RAM, F-bus RAM (FRAM) and F-bus ROM are valid, and access to areas where

external access is enabled will access external space under this mode. A part of an external terminal functions

as a bus terminal.

• Bus mode 2 (External-ROM, external-bus mode)

This mode enables internal I/O and D-bus RAM, in which any access is access to external space. Some

external pins serve as bus pins.

37

MB91301 Series

■ I/O MAP

This shows the location of the various peripheral resource registers in the memory space.

[How to read the table]

Register

Address

Block

+0

PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

+1

+2

+3

T-unit

Port Data Register

000000^H

Read/write attribute, Access type

(B : Byte, H : Half-word, W : Word)

Initial value after a reset

Register name (Address of column 1 register is 4n, address of column

2 register is 4n+2, etc.)

Location of left-most register (When using word access,

the register in column 1 is in the MSB side of the data.)

Note : Initial values of register bits are represented as follows :

“1” : Initial value“1”

“0” : Initial value“0”

“X” : Initial value“X”

“-” : No physical register at this location

38

MB91301 Series

Register

Address

Block

+0

+1

+2

+3

PDR0 [R/W] B

XXXXXXXX

PDR1 [R/W] B

XXXXXXXX

PDR2 [R/W] B

XXXXXXXX

000000^H

000004^H

⎯

PDR6 [R/W] B

XXXXXXXX

T-unit

Port Data

⎯

Register

PDR8 [R/W] B

XXXXXXXX

PDR9 [R/W] B

- XXXXXXX

PDRA [R/W] B

XXXXXXXX

PDRB [R/W] B

XXXXXXXX

000008^H

00000C^H

⎯

R-bus

Port Data

Register

PDRG [R/W] B

XXXXXXXX

PDRH [R/W] B

-- -- -XXX

PDRJ [R/W] B

XXXXXXXX

000010^H

⎯

000014^H

to

00003C^H

Reserved

EIRR [R/W] B, H, W ENIR [R/W] B, H, W

00000000 00000000

ELVR [R/W] B, H, W

000040^H

000044^H

000048^H

00004C^H

000050^H

000054^H

000058^H

00005C^H

Ext int

00000000

DICR [R/W] B, H, W HRCL [R/W] B, H, W

-- -- -- -0 0 - -11111

⎯

DLYI/I-unit

TMRLR0 [W] H, W

XXXXXXXX XXXXXXXX

TMR0 [R] H, W

XXXXXXXX XXXXXXXX

Reload

Timer 0

TMCSR0 [R/W] B, H, W

-- XX0000 00000000

⎯

TMRLR1 [W] H, W

XXXXXXXX XXXXXXXX

TMR1 [R] H, W

XXXXXXXX XXXXXXXX

Reload

Timer 1

TMCSR1 [R/W] B, H, W

-- XX0000 00000000

⎯

TMRLR2 [W] H, W

XXXXXXXX XXXXXXXX

TMR2 [R] H, W

XXXXXXXX XXXXXXXX

Reload

Timer 2

TMCSR2 [R/W] B, H, W

-- XX0000 00000000

⎯

SIDR0 [R]

SODR0 [W] B, H, W

XXXXXXXX

SSR0 [R/W] B, H, W

00001000

SCR0 [R/W] B, H, W SMR0 [R/W] B, H, W

000060^H

000064^H

000068^H

00006C^H

UART0

U-TIMER 0

UART1

00000100

00 -- 0- 0 -

UTIM0 [R] H, W (UTIMR0 [W] H, W)

00000000 00000000

DRCL0 [W] B

-- -- -- --

UTIMC0 [R/W] B

0- -00001

SIDR1 [R]

SSR1 [R/W] B, H, W

SODR1 [W] B, H, W

00001000

SCR1 [R/W] B, H, W SMR1 [R/W] B, H, W

00000100

00 -- 0- 0 -

XXXXXXXX

UTIM1 [R] H, W (UTIMR1 [W] H, W )

00000000 00000000

DRCL1 [W] B

-- -- -- --

UTIMC1 [R/W] B

0- -00001

U-TIMER 1

(Continued)

39

MB91301 Series

Register

Address

Block

+0

+1

+2

+3

SIDR2 [R]

SODR2 [W] B, H, W

XXXXXXXX

SSR2 [R/W] B, H, W

000070^H

SCR2 [R/W] B, H, W SMR2 [R/W] B, H, W

UART2

00001000

00000100

00 -- 0- 0 -

UTIM2 [R] H, W (UTIMR2 [W] H, W )

00000000 00000000

DRCL2 [W] B

-- -- - -- -

UTIMC2 [R/W] B

0- -00001

000074^H

000078^H

00007C^H

U-TIMER 2

ADCR [R] B, H, W

000000XX XXXXXXXX

ADCS [R/W] B, H, W

00000000 00000000

A/D

Converter

Sequential

Comparator

ADCR0 [R] B, H, W ADCR1 [R] B, H, W ADCR2 [R] B, H, W ADCR3 [R] B, H, W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000080^H

to

000090^H

⎯

Reserved

IBCR0 [R/W] B, H, W IBSR0 [R] B, H, W

ITBA0 [R, R/W] B, H, W

00000000 00000000

000094^H

00000000

ISBA0 [R, R/W]

ITMK0 [R, R/W] B, H, W

00111111 11111111

ISMK0 [R/W] B, H, W

000098^H

B, H, W

00000000

I²C

interface0

01111111

ICCR0 [R, W, R/W]

B, H, W

IDBL0 [R, R/W]

B, H, W

IDAR0 [R/W] B, H, W

00009C^H

⎯

00000000

00011111

00000000

0000A0^H

0000A4^H

⎯

Reserved

0000A8^H

to

0000B0^H

⎯

IBCR1 [R/W] B, H, W IBSR1 [R] B, H, W

ITBA1 [R, R/W] B, H, W

00000000 00000000

0000B4^H

00000000

ISBA1 [R, R/W]

ITMK1 [R, R/W] B, H, W

00111111 11111111

ISMK1 [R/W] B, H, W

0000B8^H

B, H, W

00000000

I²C

interface1

01111111

ICCR1 [R, W, R/W]

B, H, W

IDBL1 [R, R/W]

B, H, W

IDAR1 [R/W] B, H, W

0000BC^H

⎯

00000000

00011111

00000000

0000C0^H

0000C4^H

⎯

Reserved

0000C8^H

to

0000D0^H

⎯

TCDT [R/W] H, W

00000000 00000000

TCCS [R/W] B, H, W 16 bit Free

0000D4^H

0000D8^H

⎯

00000000

IPCP0 [R/W] H, W

XXXXXXXX_XXXXXXXX

Run Timer

IPCP1 [R/W] H, W

XXXXXXXX_XXXXXXXX

16 bit Input

Capture

(Continued)

40

MB91301 Series

Register

Address

Block

+0

+1

+2

+3

IPCP3 [R/W] H, W

XXXXXXXX_XXXXXXXX

IPCP2 [R/W] H, W

XXXXXXXX_XXXXXXXX

0000DC^H

0000E0^H

16 bit

Input

ICS23 [R/W] B, H, W

00000000

ICS01 [R/W] B, H, W

capture

⎯

00000000

0000E4^H

to

000114^H

⎯

Reserved

GCN10 [R/W] H

00110010 00010000

GCN20 [R/W] B

00000000

000118^H

000011C^H

000120^H

⎯

PPG timer

Reserved

⎯

PTMR0 [R] H

11111111 11111111

PCSR0 [W] H, W

XXXXXXXX XXXXXXXX

PPG0

PPG1

PPG2

PDUT0 [W] H, W

XXXXXXXX XXXXXXXX

PCNH0 [R/W] B

00000000

PCNL0 [R/W] B

000000X0

000124^H

000128^H

00012C^H

000130^H

000134^H

000138^H

00013C^H

PTMR1[R] H

11111111 11111111

PCSR1 [W] H, W

XXXXXXXX XXXXXXXX

PDUT1 [W] H, W

XXXXXXXX XXXXXXXX

PCNH1 [R/W] B

00000000

PCNL1 [R/W] B

000000X0

PTMR2 [R] H

11111111 11111111

PCSR2 [W] H, W

XXXXXXXX XXXXXXXX

PDUT2 [W] H, W

XXXXXXXX XXXXXXXX

PCNH2 [R/W] B

00000000

PCNL2 [R/W] B

000000X0

PTMR3[R] H

11111111 11111111

PCSR3 [W] H, W

XXXXXXXX XXXXXXXX

PPG3

PDUT3 [W] H, W

XXXXXXXX XXXXXXXX

PCNH3 [R/W] B

00000000

PCNL3 [R/W] B

000000X0

000140^H

to

0001FC^H

⎯

Reserved

DMACA0 [R/W] B, H, W*¹

00000000 0000XXXX XXXXXXXX XXXXXXXX

000200^H

000204^H

000208^H

00020C^H

000210^H

DMACB0 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

DMACA1 [R/W] B, H, W*¹

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMAC

DMACB1 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

DMACA2 [R/W] B, H, W*¹

00000000 0000XXXX XXXXXXXX XXXXXXXX

(Continued)

41

MB91301 Series

Register

Address

Block

+0

+1

+2

+3

DMACB2 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

000214^H

DMACA3 [R/W] B, H, W*¹

00000000 0000XXXX XXXXXXXX XXXXXXXX

000218^H

00021C^H

000220^H

000224^H

DMACB3 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

DMAC

DMACA4 [R/W] B, H, W*¹

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB4 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

000228^H

to

00023C^H

⎯

Reserved

DMAC

DMACR [R/W] B

0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX

000240^H

000244^H

to

000300^H

⎯

Reserved

I-Cache

ISIZE [R/W] B, H, W

-- - -- -10

000304^H

⎯

000308^H

to

0003E0^H

⎯

Reserved

I-Cache

ICHCR [R/W] B, H, W

0 - 000000

0003E4^H

0003E8^H

to

0003EF^H

⎯

Reserved

BSD0 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003F0^H

0003F4^H

0003F8^H

0003FC^H

BSD1 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

Bit Search

Module

BSDC [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSRR [R] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

R-bus Data

Direction

Register

DDRG [R/W] B

00000000

DDRH [R/W] B

⎯

DDRJ [R/W] B

00000000

000400^H

-- -- -000

(Continued)

42

MB91301 Series

Register

Address

Block

+0

+1

+2

+3

000404^H

to

00040C^H

⎯

Reserved

R-bus Port

PFRJ [R/W] B

Function

PFRG [R/W] B

00 - -- -- -

PFRH [R/W] B

- -- -- -0 -

000410^H

⎯

- 000 - 00 -

Register

000414^H

to

00041C^H

⎯

Reserved

R-bus

Pull-up

Resistance

Control

PCRH [R/W] B

- -- -- 000

000420^H

⎯

Register

000424^H

to

00043C^H

⎯

Reserved

ICR00 [R/W] B, H, W ICR01 [R/W] B, H, W ICR02 [R/W] B, H, W ICR03 [R/W] B, H, W

000440^H

000444^H

000448^H

00044C^H

000450^H

000454^H

000458^H

00045C^H

000460^H

000464^H

000468^H

-- -11111

ICR04 [R/W] B, H, W ICR05 [R/W] B, H, W ICR06 [R/W] B, H, W ICR07 [R/W] B, H, W

-- -11111 -- -11111 -- -11111 - -- 11111

ICR08 [R/W] B, H, W ICR09 [R/W] B, H, W ICR10 [R/W] B, H, W ICR11 [R/W] B, H, W

-- -11111 -- -11111 -- -11111 - -- 11111

ICR12 [R/W] B, H, W ICR13 [R/W] B, H, W ICR14 [R/W] B, H, W ICR15 [R/W] B, H, W

-- -11111 -- -11111 -- -11111 - -- 11111

ICR16 [R/W] B, H, W ICR17 [R/W] B, H, W ICR18 [R/W] B, H, W ICR19 [R/W] B, H, W

-- -11111 -- -11111 -- -11111 - -- 11111

ICR20 [R/W] B, H, W ICR21 [R/W] B, H, W ICR22 [R/W] B, H, W ICR23 [R/W] B, H, W Interrupt

-- -11111

- -- 11111

-- -11111

ICR24 [R/W] B, H, W ICR25 [R/W] B, H, W ICR26 [R/W] B, H, W ICR27 [R/W] B, H, W

-- -11111 -- -11111 -- -11111 - -- 11111

ICR28 [R/W] B, H, W ICR29 [R/W] B, H, W ICR30 [R/W] B, H, W ICR31 [R/W] B, H, W

-- -11111 -- -11111 -- -11111 - -- 11111

ICR32 [R/W] B, H, W ICR33 [R/W] B, H, W ICR34 [R/W] B, H, W ICR35 [R/W] B, H, W

-- -11111 -- -11111 -- -11111 - -- 11111

ICR36 [R/W] B, H, W ICR37 [R/W] B, H, W ICR38 [R/W] B, H, W ICR39 [R/W] B, H, W

-- -11111 -- -11111 -- -11111 - -- 11111

ICR40 [R/W] B, H, W ICR41 [R/W] B, H, W ICR42 [R/W] B, H, W ICR43 [R/W] B, H, W

-- -11111 -- -11111 -- -11111 - -- 11111

-- -11111

- -- 11111

Controller

(Continued)

43

MB91301 Series

Register

Address

Block

+0

+1

+2

+3

ICR44 [R/W] B, H, W ICR45 [R/W] B, H, W ICR46 [R/W] B, H, W ICR47 [R/W] B, H, W

00046C^H

- -- 11111

-- - 11111

- -- 11111

Interrupt

Controller

000470^H

to

00047C^H

⎯

RSRR [R, R/W]

B, H, W

10000000 (INIT)

-0 - XX -00 (INIT)

XXX - -X00 (RST)

STCR [R/W] B, H, W

001100 -1 (INIT)

0011XX -1 (INIT)

00X1XX - X (RST)

TBCR [R/W] B, H, W CTBR [W] B, H, W

000480^H

00XXX -00 (INIT)

00XXX- XX (RST)

XXXXXXXX (INIT)

XXXXXXXX (RST)

Clock

Control

unit

CLKR [R/W] B, H, W WPR [W] B, H, W DIVR0 [R/W] B, H, W DIVR1 [R/W] B, H, W

000484^H

- 000 -000 (INIT)

-XXX- XXX (RST)

XXXXXXXX (INIT)

XXXXXXXX (RST)

00000011 (INIT)

XXXXXXXX (RST)

0000- - - - (INIT)

XXXX - - - - (RST)

000488^H

to

0005FC^H

⎯

Reserved

DDR0 [R/W] B

00000000

DDR1 [R/W] B

00000000

DDR2 [R/W] B

00000000

000600^H

000604^H

000608^H

⎯

T-unit

Data

Direction

Register

DDR6 [R/W] B

00000000

⎯

DDR8 [R/W] B

00000000

DDR9 [R/W] B

- 0000000

DDRA [R/W] B

00000000

DDRB [R/W] B

00000000

00060C^H

000610^H

⎯

PFR6 [R/W] B

11111111

PFR61 [R/W] B

- -- -0000

000614^H

000618^H

00061C^H

000620^H

000624^H

⎯

T-unit

Port

Function

Register

PFR8 [R/W] B

111 - -0 - -

PFR9 [R/W] B

- 0000111

PFRA1 [R/W] B

11111111

PFRB1 [R/W] B

00000000

PFRB2 [R/W] B

000 -- -00

PFRA2 [R/W] B

- -0 - -- --

⎯

PCR0 [R/W] B

00000000

PCR1 [R/W] B

00000000

PCR2 [R/W] B

00000000

T-unit

Pull-up

Resis-

tance

Control

Register

PCR6 [R/W] B

00000000

⎯

PCR8 [R/W] B

00000000

PCR9 [R/W] B

-000- -0 -

PCRA [R/W] B

00000000

PCRB [R/W] B

00000000

000628^H

00062C^H

⎯

(Continued)

44

MB91301 Series

Register

Address

Block

+0

+1

+2

+3

000630^H

to

00063C^H

⎯

Reserved

ASR0 [R/W] H, W

00000000 00000000

ACR0 [R/W] H, W

1111XX00 00000000

000640^H

000644^H

000648^H

00064C^H

000650^H

000654^H

000658^H

00065C^H

000660^H

000664^H

000668^H

00066C^H

ASR1 [R/W] H, W

XXXXXXXX XXXXXXXX

ACR1 [R/W] B, H, W

XXXXXXXX XXXXXXXX

ASR2 [R/W] H, W

XXXXXXXX XXXXXXXX

ACR2 [R/W] B, H, W

XXXXXXXX XXXXXXXX

ASR3 [R/W] H, W

XXXXXXXX XXXXXXXX

ACR3 [R/W] B, H, W

XXXXXXXX XXXXXXXX

ASR4 [R/W] H, W

XXXXXXXX XXXXXXXX

ACR4 [R/W] B, H, W

XXXXXXXX XXXXXXXX

ASR5 [R/W] H, W

XXXXXXXX XXXXXXXX

ACR5 [R/W] B, H, W

XXXXXXXX XXXXXXXX

ASR6 [R/W] H, W

XXXXXXXX XXXXXXXX

ACR6 [R/W] B, H, W

XXXXXXXX XXXXXXXX

ASR7 [R/W] H, W

XXXXXXXX XXXXXXXX

ACR7 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR0 [R/W] B, H, W

01111111 11111011

AWR1 [R/W] B, H, W

XXXXXXXX XXXXXXXX

T-unit

AWR2 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR3 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR4 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR5 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR6 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR7 [R/W] B, H, W

XXXXXXXX XXXXXXXX

MCRA [R/W] B, H, W MCRB [R/W] B, H, W

000670^H

000674^H

000678^H

00067C^H

⎯

XXXXXXXX

⎯

IOWR0 [R/W] B, H, W IOWR1 [R/W] B, H, W IOWR2 [R/W] B, H, W

⎯

XXXXXXXX

⎯

TCR [R/W] B, H, W

00000000 (INIT)

0000XXXX (RST)

CSER [R/W] B, H, W CHER [R/W] B, H, W

000680^H

000684^H

⎯

00000001

11111111

RCR [R/W] B, H, W

00XXXXXX XXXX0XXX

⎯

(Continued)

45

MB91301 Series

Register

Address

Block

+0

+1

+2

+3

00068C^H

to

0007F8^H

⎯

Reserved

T-unit

MODR [W] *²

XXXXXXXX

0007FC^H

⎯

000800^H

to

000AFC^H

⎯

Reserved

ESTS0 [R/W] B

X0000000

ESTS1 [R/W] B

XXXXXXXX

ESTS2 [R] B

1XXXXXXX

000B00^H

000B04^H

000B08^H

000B0C^H

000B10^H

⎯

ECTL0 [R/W] B

0X000000

ECTL1 [R/W] B

00000000

ECTL2 [W] B

000X0000

ECTL3 [R/W] B

00X00X11

ECNT0 [W] B

XXXXXXXX

ECNT1 [W] B

XXXXXXXX

EUSA [W] B

XXX00000

EDTC [W] B

0000XXXX

EWPT [R] H

00000000 00000000

ECTL4 [R] ([R/W]) B ECTL5 [R] ([R/W]) B

-0X00000 -- -- 000X

EDTR0 [W] H

XXXXXXXX XXXXXXXX

EDTR1 [W] H

XXXXXXXX XXXXXXXX

000B14^H

to

000B1C^H

⎯

EIA0 [W] W

000B20^H

000B24^H

000B28^H

000B2C^H

000B30^H

000B34^H

000B38^H

000B3C^H

000B40^H

000B44^H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA1 [W] W

DSU

(Evaluation

chip only)

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA2 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA3 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA4 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA5 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA6 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA7 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EDTA [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EDTM [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

(Continued)

46

MB91301 Series

Register

Address

Block

+0

+1

+2

+3

EOA0 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B48^H

000B4C^H

000B50^H

000B54^H

000B58^H

000B5C^H

000B60^H

000B64^H

000B68^H

000B6C^H

EOA1 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EPCR [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EPSR [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIAM0 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DSU

(Evaluation

chip only)

EIAM1 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOAM0/EODM0 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOAM1/EODM1 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOD0 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOD1 [W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B70^H

to

000FFC^H

⎯

Reserved

DMASA0 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001000^H

001004^H

001008^H

00100C^H

001010^H

001014^H

001018^H

00101C^H

001020^H

DMADA0 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMASA1 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMADA1 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMASA2 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMAC

DMADA2 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMASA3 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMADA3 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMASA4 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

(Continued)

47

MB91301 Series

(Continued)

Register

Address

Block

+0

+1

+2

+3

DMADA4 [R/W] W

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DMAC

001024^H

001028^H

to

001FFC^H

⎯

Reserved

*1 : Byte access is not permitted for the lower 16 bits of DMAC0 to DMAC4 (DTC15 to DTC0) .

*2 : This register is accessed through mode vector fetch; it cannot be accessed in normal mode.

48

MB91301 Series

■ INTERRUPT VECTORS

Interrupt No.

Interrupt

level*¹

TBR default

Interrupt

Offset

RN

address*²

10

0

16

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

Reset

⎯

3FC^H

3F8^H

3F4^H

3F0^H

3EC^H

3E8^H

3E4^H

3E0^H

3DC^H

3D8^H

3D4^H

3D0^H

3CC^H

3C8^H

3C4^H

000FFFFC^H

000FFFF8^H

000FFFF4^H

000FFFF0^H

000FFFEC^H

000FFFE8^H

000FFFE4^H

000FFFE0^H

000FFFDC^H

000FFFD8^H

000FFFD4^H

000FFFD0^H

000FFFCC^H

000FFFC8^H

000FFFC4^H

⎯

Mode vector

1

System reserved

Coprocessor absent trap

Coprocessor error trap

INTE instruction

2

3

4

5

6

7

8

9

Instruction break exception

Operand break trap

Step trace trap

10

11

12

13

14

NMI request (tool)

Undefined instruction exception

15 (F^H)

fixed

NMI request

15

0F

3C0^H

000FFFC0^H

⎯

External interrupt 0

External interrupt 1

External interrupt 2

External interrupt 3

External interrupt 4

External interrupt 5

External interrupt 6

External interrupt 7

Reload timer 0

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

ICR16

3BC^H

3B8^H

3B4^H

3B0^H

3AC^H

3A8^H

3A4^H

3A0^H

39C^H

398^H

394^H

390^H

38C^H

388^H

384^H

380^H

37C^H

000FFFBC^H

000FFFB8^H

000FFFB4^H

000FFFB0^H

000FFFAC^H

000FFFA8^H

000FFFA4^H

000FFFA0^H

000FFF9C^H

000FFF98^H

000FFF94^H

000FFF90^H

000FFF8C^H

000FFF88^H

000FFF84^H

000FFF80^H

000FFF7C^H

6

7

11

12

⎯

8

Reload timer 1

9

Reload timer 2

10

0

UART0 (RX completed)

UART1 (RX completed)

UART2 (RX completed)

UART0 (TX completed)

UART1 (TX completed)

UART2 (TX completed)

1

2

3

4

5

(Continued)

49

MB91301 Series

Interrupt No.

Interrupt

level*¹

TBR default

address*²

Interrupt

Offset

RN

10

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

16

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

DMAC0 (end, error)

DMAC1 (end, error)

DMAC2 (end, error)

DMAC3 (end, error)

DMAC4 (end, error)

A/D

ICR17

ICR18

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

ICR32

ICR33

ICR34

ICR35

ICR36

ICR37

ICR38

ICR39

ICR40

ICR41

ICR42

ICR43

ICR44

ICR45

ICR46

ICR47

⎯

378^H

374^H

370^H

36C^H

368^H

364^H

360^H

35C^H

358^H

354^H

350^H

34C^H

348^H

344^H

340^H

33C^H

338^H

334^H

330^H

32C^H

328^H

324^H

320^H

31C^H

318^H

314^H

310^H

30C^H

308^H

304^H

300^H

2FC^H

2F8^H

2F4^H

000FFF78^H

000FFF74^H

000FFF70^H

000FFF6C^H

000FFF68^H

000FFF64^H

000FFF60^H

000FFF5C^H

000FFF58^H

000FFF54^H

000FFF50^H

000FFF4C^H

000FFF48^H

000FFF44^H

000FFF40^H

000FFF3F^H

000FFF38^H

000FFF34^H

000FFF30^H

000FFF2C^H

000FFF28^H

000FFF24^H

000FFF20^H

000FFF1C^H

000FFF18^H

000FFF14^H

000FFF10^H

000FFF0C^H

000FFF08^H

000FFF04^H

000FFF00^H

000FFEFC^H

000FFEF8^H

000FFEF4^H

⎯

15

13

14

⎯

PPG0

PPG1

PPG2

PPG3

System reserved

U-TIMER0

U-TIMER1

U-TIMER2

Time base timer overflow

I²C I/F0

I²C I/F1

System reserved

16 bit Free Run Timer

ICU0 (load)

ICU1 (load)

ICU2 (load)

ICU3 (load)

System reserved

Delay interrupt bit

System reserved (Used by REALOS)

System reserved

⎯

(Continued)

50

MB91301 Series

(Continued)

Interrupt No.

Interrupt

level*¹

TBR default

Interrupt

Offset

RN

address*²

10

67

68

69

70

71

72

73

74

75

76

77

78

79

16

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

System reserved

⎯

2F0^H

2EC^H

2E8^H

2E4^H

2E0^H

2DC^H

2D8^H

2D4^H

2D0^H

2CC^H

2C8^H

2C4^H

2C0^H

000FFEF0^H

000FFEEC^H

000FFEE8^H

000FFEE4^H

000FFEE0^H

000FFEDC^H

000FFED8^H

000FFED4^H

000FFED0^H

000FFECC^H

000FFEC8^H

000FFEC4^H

000FFEC0^H

⎯

80

to

255

50

to

FF

2BC^H

to

000^H

000FFEBC^H

to

000FFC00^H

Used by INT instruction

⎯

*1 : ICRs are registers built in the interrupt controller to set interrupt levels for individual interrupt requests.

The ICRs are provided for the different interrupt levels.

*2 : The TBR is the register holding the start address of the EIT vector table.

The TBR value and the offset value preset for each EIT source are added together to be the vector address.

Note: The 1 Kbyte area from the TBR address is the EIT vector area.

The vector size is 4 bytes and the relationship between vector number and vector address is expressed as

follows:

Vctadr = TBR + vctofs

= TBR + (3FC^H− 4 × vct)

vctadr : vector address

vctofs : vector offset

vct

: vector number

51

MB91301 Series

■ INSTRUCTION CACHE

The instruction cache is a fast local memory for temporary storage. Once an instruction code is accessed from

external slower memory, the instruction cache holds the instruction code inside to increase the speed of access-

ing the same code from then on.

By setting the RAM mode, the instruction cache data RAM is made directly read/write-accessible by software.

• Configuration

• FR family’s basic instruction length : Two bytes

• Block layout : Two-way set associative

• Blocks : 128 blocks per way

16 bytes per block ( = 4 sub-blocks)

4 bytes per sub-block ( = 1 bus access unit)

• Instruction Cache Configuration

4 bytes

I3

4 bytes

I2

4 bytes

I1

4 bytes

I0

Way 1

Sub

block 3

Sub

block 2

Sub

block 1

Sub

block 0

Cash tag

block 0

128 block

Sub

block 0

Sub

block 1

Sub

block 2

Sub

block 3

block 127

block 0

Cash tag

Way 2

Sub

block 2

Sub

block 3

Sub

block 1

Sub

block 0

128 block

Sub

block 2

Sub

block 3

Sub

block 1

Sub

block 0

Cash tag

block 127

52

MB91301 Series

• Instruction Cache Tags

Way 1

31

09

08

Vacancy

Address tag

07

06

SBV2

05

04

03

02

01

00

Vacancy

SBV3

SBV1

SBV0

TAGV

LRU

ETLK

Way 2

31

09

08

Vacancy

Address tag

07

06

SBV2

05

04

03

02

01

00

Vacancy

SBV3

SBV1

SBV0

TAGV

ETLK

[bit 31 to bit 9] Address tag

The address tag stores the upper 23 bits of the memory address of the instruction cached in the corresponding

block.

For example, memory address IA of the instruction data stored in sub-block k in block i is obtained from the

following equation:

IA = address tag × 2⁹+ i × 2⁴+ k × 2²

The address tag is used to check for a match with the instruction address requested for access by the CPU.

The CPU and cache behave as follows depending on the result of the tag check:

• When the requested instruction data exists in the cache (hit), the cache transfers the data to the CPU within

the cycle.

• When the requested instruction data does not exist in the cache (miss), the CPU and cache obtain the data

loaded by external access at the same time.

[bit 7 to bit4] SBV3 to SBV0 : Sub-block validation

When SBVⁿcontains "1", the corresponding sub-block holds the current instruction data at the address located

by the tag. Each sub-block usually holds two instructions (excluding immediate-value transfer instructions).

[bit 3] TAGV : Tag validation bit

This bit indicates whether the address tag value is valid. When the bit contains "0", the corresponding block is

invalid regardless of the settings of the sub-block validation bits. (The bit is set to "0" when the cache is flushed.)

[bit 1] LRU (only in way 1)

This bit exists only in the instruction cache tag in way 1. The bit indicates way 1 or 2 as the way containing the

last entry accessed in the selected set. When set to "1", the LRU bit indicates that the entry of the set in way 1

is the last entry accessed. When set to "0", it indicates that the one in way 2 is the last entry accessed.

[bit 0] ETLK : Entry lock

This bit is used to lock all the entries in the block corresponding to the tag in the cache. When the ETLK bit is

set to "1", the entries are locked and are not updated when a cache miss occurs. Note, however, that invalid

sub-blocks are updated. If a cache miss occurs with both of ways 1 and 2 in the entry lock states, access to

external memory takes place after losing one cycle used for evaluating the cache miss.

53

MB91301 Series

Control Registers

• Cache Size Register (ISIZE)

bit

Initial value

- - - - - - 10^B

7

6

5

4

3

2

1

0

Address: 00000307^H

⎯

SIZE1

R/W

SIZE0

R/W

⎯

• Instruction Cache Control Register (ICHCR)

The instruction cache (I-cache) control register (ICHCR) controls the operations of the instruction cache.

Writing a value to the ICHCR has no effect on the caching of any instruction fetched within three cycles that follow.

bit

Initial value

0 - 000000^B

7

6

5

4

3

2

1

0

Address: 000003E7^H

RAM

R/W

⎯

GBLK

R/W

ALFL

R/W

EOLK

R/W

ELKR

R/W

FLSH

R/W

ENAB

R/W

Cache off

RAM off

Cache off Cache 4 K Cache 4 K Cache 2 K Cache 2 K Cache 1 K

Cache

RAM on

Address

RAM on

RAM off

RAM on

RAM off

RAM on

RAM off

00010000H

00010200H

00010400H

00010600H

00010800H

00010FFFH

00014000H

00014200H

00014400H

00014600H

00014800H

00014FFFH

00018000H

00018200H

00018400H

00018600H

00018800H

00018FFFH

0001C000H

0001C200H

0001C400H

0001C600H

0001C800H

0001CFFFH

TAG1

<TAG1>

TAG2

<TAG1>

TAG2

<TAG2>

IRAM1

<TAG2>

$RAM1

IRAM1

$RAM1

IRAM1

<IRAM1>

IRAM2

<IRAM1>

IRAM2

<$RAM1> <IRAM1>

$RAM2

<$RAM1>

<IRAM1>

<$RAM1>

$RAM2

IRAM2

<IRAM2>

<$RAM2> <IRAM2>

<$RAM2>

<IRAM2>

<$RAM2>

TAG1 ⋅⋅⋅TAG RAM (way1)

TAG2 ⋅⋅⋅TAG RAM (way2)

<> ⋅⋅⋅Mirror area

$RAM1 ⋅⋅⋅Cache RAM (way1) IRAM1 ⋅⋅⋅I-bus RAM (way1)

$RAM2 ⋅⋅⋅Cache RAM (way2) IRAM1 ⋅⋅⋅I-bus RAM (way2)

RAM on/off⋅⋅⋅RAM bit = I/O

TAG RAM

Cache RAM

Instruction at address 000 (SBV0)

←Entry at address 00x

00010000H

00010004H

00010008H

0001000CH

00010010H

00010014H

00018000^H

00018004H

00018008H

0001800CH

00018010H

00018014H

Instruction at address 004 (SBV1)

Instruction at address 008 (SBV2)

Instruction at address 00C (SBV3)

Instruction at address 010 (SBV0)

Instruction at address 014 (SBV1)

⋅⋅⋅

←Mirror of 00x

←Entry at address 00x

←Mirror of 00x

54

MB91301 Series

Address

000^H

Cache 4 K

$RAM1

Cache 2 K

$RAM1

Cache 1 K

$RAM1

Cache off

IRAM1

200H

400H

IRAM1

$RAM2

600H

000H

200H

400H

600H

$RAM2

IRAM2

$RAM2

IRAM2

ROMA = 1

(ROM present)

ROMA = 0

(ROM absent)

Address

00000000H

Direct area

IRAM

Direct area

IRAM

00010000H

00020000H

00030000H

00040000H

(Even the D-bus RAM area is cashed, when it is

transferred to the IA-Bus.)

Internal ROM/RAM area should be cached.

Internal

memory

Cache area

00100000H

FFFFFFFFH

Each chip-select area can be set as a non-cache

area.

Cache area

55

MB91301 Series

■ PERIPHERAL RESOURCES

1. External Bus Interface Controller

• External Bus Interface Controller Features

• Maximum output address width = 32-bit (4 Gbytes memory space)

• Various different types of external memory (8-bit, 16-bit, or 32-bit devices) can be directly connected and the

controller can support multiple devices with different access timings.

Asynchronous SRAM, asynchronous ROM/FLASH memory (supports multiple write strobe access or byte-

enable access)

Page mode ROM/FLASH memory (2, 4, or 8 page size)

Burst mode ROM/FLASH memory

Address/data multiplexed bus (8-bit or 16-bit width only)

Synchronous memory (built-in ASIC memory, etc.)

Note: Synchronous SRAM cannot be directly connected.

• Memory can be divided into eight independent banks (chip select areas) with a separate chip select output

for each bank.

The size of each area can be set in 64 Kbytes increments (the size of each chip select area can range from

64 Kbytes to 2 Gbytes)

Each area can be located anywhere in the physical address space (subject to boundary limitations based on

the area size)

• The following functions can be set independently for each chip select area :

Chip select area enable/disable (Access is not performed to disabled areas)

Setting of an access timing type to support each type of memory (For SDRAM, only the CS6 and CS7 areas

can be connected.)

Detailed access timing settings (wait cycles and similar settings for each access type)

Data bus width (8-bit, 16-bit, 32-bit)

Byte-ordering setting (big or little endian)

Note: The CS0 area must be big endian.

Write-prohibit setting (read-only areas)

Enable or disable loading into built-in cache

Enable or disable prefetch function

Maximum burst length setting (1, 2, 4, 8)

• Different detailed timing settings can be set for each timing type

Even for the same type, different settings can be used for each chip select area.

Up to 15 auto-wait cycles can be specified. (For asynchronous SRAM, ROM, Flash, and I/O areas)

The bus cycle can be extended by the external RDY input. (For asynchronous SRAM, ROM, Flash, and I/O

areas)

Fast access wait and page wait settings are supported (For burst/page mode ROM and Flash areas)

Idle cycles, recovery cycles, setup delays, and similar can be inserted.

Capable of setting timing values such as the CAS latency and RAS-CAS delay (SDRAM area)

Capable of controlling the distributed/centralized auto-refresh, self-refresh, and other refresh timings (SDRAM

area)

• DMA supports fly-by transfer

Transfer between memory and I/O can be performed by a single access.

Memory wait cycles can be synchronized with the I/O wait period during fly-by transfer.

Hold times can be maintained by extending access to the data source only.

Separate idle and recovery cycle settings can be specified for use in fly-by transfer.

• Supports external bus arbitration using BRQ and BGRNT.

• Pins not used by the external interface can be set as general purpose I/O ports.

56

MB91301 Series

• Block Diagram

Internal

address bus data bus

32

External data bus

switch

write buffer

read buffer

MUX

DATA BLOCK

ADDRESS BLOCK

+1 or +2

External address

bus

address buffer

ASR

ASZ

CS0 to CS7

comparator

SRAS, SCAS,

SDRAM control

SWE, MCLKE,

DQMUU, DQMUL,

DQMLU, DQMLL

RCR

under flow

refresh counter

RD

External pin controller

WR0, WR1,

WR2, WR3,

AS, BAA

All block control

registers

BRQ

BGRNT

RDY

&

control

57

MB91301 Series

• I/O pin

External interface pin (Some pins are general purpose pins.)

The following shows I/O pins of each interface.

• Normal bus interface

A23 to A00, D31 to D00 (AD15 to AD00)

CS0, CS1, CS2, CS3, CS4, CS5, CS6, CS7

AS, SYSCLK, MCLK,

RD

WR, WR0 (UUB) , WR1 (ULB) , WR2 (ULB) , WR3 (LLB) ,

RDY, BRQ, BGRNT

• Memory interface

MCLK, MCLKE

MCLKI (for SDRAM)

LBA ( = AS) , BAA (for burst ROM/FLASH)

SRAS, SCAS, SWE ( = WR) (for SDRAM)

DQMUU, DQMUL, DQMLU, DQMLL (for SDRAM ( = WR0, WR1, WR2, WR3) )

• DMA interface

IOWR, IORD

DACK0, DACK1

DREQ0, DREQ1

DEOP0, DEOP1

58

MB91301 Series

• Register List

31

24 23

16 15

08 07

ACR0

ACR1

ACR2

ACR3

ACR4

ACR5

ACR6

ACR7

AWR1

AWR3

AWR5

AWR7

00

ASR0

ASR1

ASR2

ASR3

ASR4

ASR5

ASR6

ASR7

AWR0

AWR2

AWR4

AWR6

Area select registers 0 to 7 (ASR0 to ASR7)

Area configuration registers 0 to 7 (ACR0 to ACR7)

Area weight register (AWR0 to AWR7)

Memory setting register

(For SDRAM/FCRAM auto-precharge OFF mode) (MCRA)

Memory setting register

Reserved

MCRA

Reserved

IOWR0

MCRB

Reserved

IOWR1

Reserved

TCR

(For FCRAM auto-precharge ON mode) (MCRB)

Reserved

CHER

Reserved

CSER

DMAC I/O wait registers (IOWR0 and IOWR1)

Chip-select area enable register (CSER)

Cache fetch enable register (CHER)

Reserved

RCR

Reserved

Terminal and timing control register (TCR)

Refresh control register (RCR)

Reserved

(MODR)

Reserved

Notes : • Reserved indicates a reserved register. When writing, always set to “0”.

• The MODR register cannot be accessed by the user program.

59

MB91301 Series

2. I/O Ports

MB91301 series pins can be used as I/O ports when not set for use by the external bus interface or the various

peripheral I/O functions.

• I/O port (with pull-up resistor) block diagram

PDR read

Port Bus

Peripheral input

0

1

Pull-up resistor

(approx. 25 kΩ)

Peripheral output

1

0

PDR

PFR

DDR

PCR

PCR = 0 : No pull-up resistor

PCR = 1 : Use pull-up resistor

PDR : Port Data Register

DDR : Data Direction Register

PFR : Port Function Register

PCR : Pull-up Control Register

Note : For port output, the pull-up resistor is disabled irrespective of the setting.

I/O ports with pull-up resistors have the following registers :

• PDR (Port Data Register)

• DDR (Data Direction Register)

• PFR (Port Function Register)

• PCR (Pull-up Control Register)

I/O ports have three following modes

• When port is in input mode (PFR = “0” & DDR = “0”)

PDR read : Reads the level of the corresponding external pin.

PDR write : Writes the value to the PDR.

• When port is in output mode (PFR = “0” & DDR = “1”)

PDR read : Reads the PDR value.

PDR write : Outputs the PDR value to the corresponding external pin.

• When port is in peripheral output mode (PFR = “1” & DDR = “X”)

PDR

: Reads the value of the corresponding peripheral output.

PDR write : Writes the value to the PDR.

60

MB91301 Series

Notes : • Use byte access to access ports.

• The external bus function has priority for port 0 to port A when these are used as external bus pins.

Accordingly, writing to the DDR has no effect on the pin input/output setting while the pins are operating

as external bus pins. The value set in the DDR becomes meaningful when the PFR register is modified

to set the pins as general purpose ports.

• In stop mode (HIZ = 0), the pull-up resistor control register setting is used.

• In stop mode (HIZ = 1), the pull-up resistor control register (PCR) setting is ignored during hardware

standby.

• Using pull-up resistors is prohibited when these pins are used as external bus pins. In this case, do not

write “1” to the corresponding bit in the pull-up resistor control register (PCR).

61

MB91301 Series

• Port Data Register (PDR)

PDR0

Initial value

7

6

5

4

3

2

1

0

P07

P06

R/W

P05

R/W

P04

R/W

P03

R/W

P02

R/W

P01

R/W

P00

R/W

Address : 00000000^H

XXXXXXXX^B

R/W

PDR1

Initial value

7

6

5

4

3

2

1

0

P17

P16

R/W

P15

R/W

P14

R/W

P13

R/W

P12

R/W

P11

R/W

P10

R/W

Address : 00000001^H

XXXXXXXX^B

R/W

PDR2

Initial value

7

6

5

4

3

2

1

0

P27

P26

R/W

P25

R/W

P24

R/W

P23

R/W

P22

R/W

P21

R/W

P20

R/W

Address : 00000002^H

XXXXXXXX^B

R/W

PDR6

Initial value

7

6

5

4

3

2

1

0

P67

P66

R/W

P65

R/W

P64

R/W

P63

R/W

P62

R/W

P61

R/W

P60

R/W

Address : 00000006^H

XXXXXXXX^B

R/W

PDR8

Initial value

7

6

5

4

3

2

1

0

P87

P86

R/W

P85

R/W

P84

R/W

P83

R/W

P82

R/W

P81

R/W

P80

R/W

Address : 00000008^H

XXXXXXXX^B

R/W

PDR9

Initial value

7

6

5

4

3

2

1

0

⎯

P96

R/W

P95

R/W

P94

R/W

P93

R/W

P92

R/W

P91

R/W

P90

R/W

Address : 00000009^H

- XXXXXXX^B

R/W

PDRA

Initial value

7

6

5

4

3

2

1

0

PA7

PA6

R/W

PA5

R/W

PA4

R/W

PA3

R/W

PA2

R/W

PA1

R/W

PA0

R/W

Address : 0000000A^H

XXXXXXXX^B

R/W

PDRB

Initial value

7

6

5

4

3

2

1

0

PB7

PB6

R/W

PB5

R/W

PB4

R/W

PB3

R/W

PB2

R/W

PB1

R/W

PB0

R/W

Address : 0000000B^H

XXXXXXXX^B

R/W

PDRG

Initial value

7

6

5

4

3

2

1

0

PG7

PG6

R/W

PG5

R/W

PG4

R/W

PG3

R/W

PG2

R/W

PG1

R/W

PG0

R/W

Address : 00000010^H

XXXXXXXX^B

R/W

PDRH

Initial value

- - - - - XXX^B

7

6

5

4

3

2

1

0

⎯

PH2

R/W

PH1

R/W

PH0

R/W

Address : 00000011^H

R/W

PDRJ

Initial value

7

6

5

4

3

2

1

0

PJ7

PJ6

R/W

PJ5

R/W

PJ4

R/W

PJ3

R/W

PJ2

R/W

PJ1

R/W

PJ0

R/W

Address : 00000013^H

XXXXXXXX^B

R/W

• PDR0 to PDR2, PDR6, PDR8 to PDRB, PDRG, PDRH and PDRJ are the I/O data registers for the I/O pots.

• The corresponding PDR0 to DDRJ and PFR6 to PFRJ registers control input/output.

• P00 to P07, P10 to P17 and P20 to P27 do not have a PFR (port function register).

62

MB91301 Series

• Data Direction Register (DDR)

DDR0

Initial value

7

6

5

4

3

2

1

0

P07

P06

R/W

P05

R/W

P04

R/W

P03

R/W

P02

R/W

P01

R/W

P00

R/W

Address : 00000600^H

00000000^B

R/W

DDR1

Initial value

00000000^B

7

6

5

4

3

2

1

0

P17

P16

R/W

P15

R/W

P14

R/W

P13

R/W

P12

R/W

P11

R/W

P10

R/W

Address : 00000601^H

R/W

DDR2

Initial value

00000000^B

7

6

5

4

3

2

1

0

P27

R/W

P26

R/W

P25

R/W

P24

R/W

P23

R/W

P22

R/W

P21

R/W

P20

R/W

Address : 00000602^H

DDR6

Initial value

00000000^B

7

6

5

4

3

2

1

0

P67

R/W

P66

R/W

P65

R/W

P64

R/W

P63

R/W

P62

R/W

P61

R/W

P60

R/W

Address : 00000606^H

DDR8

Initial value

00000000^B

7

6

5

4

3

2

1

0

P87

R/W

P86

R/W

P85

R/W

P84

R/W

P83

R/W

P82

R/W

P81

R/W

P80

R/W

Address : 00000608^H

DDR9

Initial value

- 0000000^B

7

6

5

4

3

2

1

0

⎯

P96

R/W

P95

R/W

P94

R/W

P93

R/W

P92

R/W

P91

R/W

P90

R/W

Address : 00000609^H

R/W

DDRA

Initial value

00000000^B

7

6

5

4

3

2

1

0

PA7

R/W

PA6

R/W

PA5

R/W

PA4

R/W

PA3

R/W

PA2

R/W

PA1

R/W

PA0

R/W

Address : 0000060A^H

DDRB

Initial value

00000000^B

7

6

5

4

3

2

1

0

PB7

R/W

PB6

R/W

PB5

R/W

PB4

R/W

PB3

R/W

PB2

R/W

PB1

R/W

PB0

R/W

Address : 0000060B^H

DDRG

Initial value

00000000^B

7

6

5

4

3

2

1

0

PG7

R/W

PG6

R/W

PG5

R/W

PG4

R/W

PG3

R/W

PG2

R/W

PG1

R/W

PG0

R/W

Address : 00000400^H

DDRH

Initial value

- - - - - 000^B

7

6

5

4

3

2

1

0

⎯

PH2

R/W

PH1

R/W

PH0

R/W

Address : 00000401^H

R/W

DDRJ

Initial value

00000000^B

7

6

5

4

3

2

1

0

PJ7

R/W

PJ6

R/W

PJ5

R/W

PJ4

R/W

PJ3

R/W

PJ2

R/W

PJ1

R/W

PJ0

R/W

Address : 00000403H

DDR0 to DDR2, DDR6, DDR8 to DDRB, DDRG, DDRH and DDRJ control the direction (input or output) of each

bit in the corresponding port.

When PFR = 0 DDR = 0 : Port input

DDR = 1 : Port output

When PFR = 1 DDR = 0 : Peripheral input

DDR = 1 : Peripheral output

63

MB91301 Series

• Pull-up Resistor Control Register (PCR)

PCR0

bit

Initial value

00000000^B

7

6

5

4

3

2

1

0

Address : 00000620^H

P07

R/W

P06

R/W

P05

R/W

P04

R/W

P03

R/W

P02

R/W

P01

R/W

P00

R/W

PCR1

Initial value

00000000^B

7

6

5

4

3

2

1

0

Address : 00000621^H

P17

R/W

P16

R/W

P15

R/W

P14

R/W

P13

R/W

P12

R/W

P11

R/W

P10

R/W

PCR2

Initial value

00000000^B

7

6

5

4

3

2

1

0

Address : 00000622^H

P27

R/W

P26

R/W

P25

R/W

P24

R/W

P23

R/W

P22

R/W

P21

R/W

P20

R/W

PCR6

Initial value

00000000^B

7

6

5

4

3

2

1

0

Address : 00000626^H

P67

R/W

P66

R/W

P65

R/W

P64

R/W

P63

R/W

P62

R/W

P61

R/W

P60

R/W

PCR8

Initial value

00000000^B

7

6

5

4

3

2

1

0

Address : 00000628^H

P87

R/W

P86

R/W

P85

R/W

P84

R/W

P83

R/W

P82

R/W

P81

R/W

P80

R/W

PCR9

Initial value

- 000 - - 0 -^B

7

6

5

4

3

2

1

0

Address : 00000629^H

⎯

P96

R/W

P95

R/W

P94

R/W

⎯

P91

R/W

⎯

R/W

PCRA

Initial value

00000000^B

7

6

5

4

3

2

1

0

Address : 0000062A^H

PA7

R/W

PA6

R/W

PA5

R/W

PA4

R/W

PA3

R/W

PA2

R/W

PA1

R/W

PA0

R/W

PCRB

Initial value

00000000^B

7

6

5

4

3

2

1

0

Address : 0000062B^H

PB7

R/W

PB6

R/W

PB5

R/W

PB4

R/W

PB3

R/W

PB2

R/W

PB1

R/W

PB0

R/W

PCRH

Initial value

- - - - - 000^B

7

6

5

4

3

2

1

0

Address : 00000421^H

⎯

PH2

R/W

PH1

R/W

PH0

R/W

PCR0 to PCR2, PCR6, PCR8 to PCRB, PCRG, PCRH and PCRJ control the pull-up resistors for the corre-

sponding port.

PCR = 0 : No pull-up resistor

PCR = 1 : Use pull-up resistor

64

MB91301 Series

• Port Function Register (PFR)

PFR6

bit

Initial value

7

6

5

4

3

2

1

0

Address : 00000616^H

11111111^B

A23E

R/W

A22E

R/W

A21E

R/W

A20E

R/W

A19E

R/W

A18E

R/W

A17E

R/W

A16E

R/W

PFR8

Initial value

111 - - 0 - -^B

7

6

5

4

3

2

1

0

Address : 00000618^H

WR3XE WR2XE WR1XE

⎯

BRQE

R/W

⎯

R/W

6

R/W

5

R/W

PFR9

Initial value

- 0000111^B

7

4

3

2

1

0

Address : 00000619^H

⎯

WRXE BAAE

ASXE

R/W

⎯

MCKE MCKEE SYSE

R/W

6

R/W

5

R/W

2

R/W

1

R/W

0

PFRA1

Initial value

11111111^B

7

4

3

Address : 0000061A^H

CS7XE CS6XE CS5XE CS4XE CS3XE CS2XE CS1XE CS0XE

R/W

PFRB1

Initial value

00000000^B

7

6

5

4

3

2

1

0

Address : 0000061B^H

DES1

R/W

AK12

R/W

AK11

R/W

AK10

R/W

DES0

R/W

AK02

R/W

AK01

R/W

AK00

R/W

PFRB2

Initial value

000 - - - 00^B

7

6

5

4

3

2

1

0

Address : 0000061C^H

DRDE DWRE PPE1

⎯

AKH1

R/W

AKH0

R/W

PFRA2

Initial value

- - 0 - - - - -^B

7

6

5

4

3

2

1

0

Address : 0000061E^H

⎯

PPE2

R/W

⎯

R/W

PFRG

Initial value

00 - - - - - -^B

7

6

5

4

3

2

1

0

Address : 00000410^H

SCE2

R/W

SOE2

R/W

⎯

R/W

PFRH

Initial value

- - - - - - 0 -^B

7

6

5

4

3

2

1

0

Address : 00000411^H

⎯

PPE3

R/W

⎯

R/W

PFRJ

Initial value

- 000 - 00 -^B

7

6

5

4

3

2

1

0

Address : 00000413^H

⎯

PPE0

R/W

SCE1

R/W

SOE1

R/W

⎯

SCE0

R/W

SOE0

R/W

⎯

R/W

PFR61

Initial value

- - - - 0000 ^B

7

6

5

4

⎯

3

2

1

0

Address : 00000617^H

⎯

TEST1 TEST0 I2CE1 I2CE0

R/W R/W R/W R/W

R/W

PFR6, PFR8 to PFRB, PFRA2, PFRG, PFRH and PFRJ control the output for the corresponding external bus

interface or peripheral output bit.

Always write "0" to unused bits in the PFR.

65

MB91301 Series

3. Interrupt Controller

The interrupt controller receives and processes interrupts.

• Hardware Configuration

The interrupt controller consists of the following :

• ICR register

• Interrupt priority determination circuit

• Interrupt level and interrupt number (vector) generator

• Hold request removal request generator

• Principal Functions

The main functions of the interrupt controller are as follows :

• Detect NMI and interrupt requests

• Prioritize interrupts (according to level and number)

• Notify interrupt level of selected interrupt request (to CPU)

• Notify interrupt number of selected interrupt request (to CPU)

If an NMI or interrupt request with an interrupt level other than "11111^B" occurs, notify recovery from stop mode

(to CPU)

• Generate hold request removal requests to the bus master

• Block Diagram

^{(“1” when LEVEL}≠ ¹¹¹¹¹^B)

UNMI

WAKEUP

D termine order of priority

Determine order of priority

5

LEVEL4 to LEVEL40

MHALTI

NMI

processing

HLDREQ

removal

request

LEVEL

d termination

determination

LEVEL,

VECTOR

genera-

tion

ICR00

RI00

VECTOR

VCT5 to VCT50

6

d termination

determination

ICR47

RI47

(DLYIRQ)

R-bus

66

MB91301 Series

• Register List

bit

7

6

5

4

3

2

1

0

⎯

ICR4

ICR3

ICR2

ICR1

ICR0

00000440H

00000441H

00000442H

00000443H

00000444H

00000445H

00000446H

00000447H

00000448H

00000449H

0000044AH

0000044BH

0000044CH

0000044DH

0000044EH

0000044FH

00000450H

00000451H

00000452H

00000453H

00000454H

00000455H

00000456H

00000457H

00000458H

00000459H

0000045AH

0000045BH

0000045CH

0000045DH

0000045EH

0000045FH

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

ICR16

ICR17

ICR18

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

Address:

⎯

ICR4

ICR3

ICR2

ICR1

ICR0

(Continued)

67

MB91301 Series

(Continued)

bit

7

6

5

4

3

2

1

0

⎯

ICR4

ICR3

ICR2

ICR1

ICR0

00000460

00000461

00000462

00000463

00000464

00000465

00000466

00000467

00000468

00000469

0000046A

0000046B

0000046C

0000046D

0000046E

0000046F

H

ICR32

ICR33

ICR34

ICR35

ICR36

ICR37

ICR38

ICR39

ICR40

ICR41

ICR42

ICR43

ICR44

ICR45

ICR46

ICR47

Address:

⎯

ICR4

ICR3

ICR2

ICR1

ICR0

MHALTI

⎯

LVL4

LVL3

LVL2

LVL1

LVL0

Address:

0000045

H

HRCL

68

MB91301 Series

4. External Interrupt/NMI Control Block

The external interrupt control block controls external interrupt requests input to the NMI and INT0 to INT7 pins.

The interrupt trigger level can be selected from "H", "L", "rising edge", or "falling edge" (except for NMI).

• Block Diagram

R-bus

8

Interrupt enable register

9

8

9

INT0 to INT7

NMI

Edge detection circuit

Interrupt

request

Gate

Request F/F

Interrupt request register

Interrupt level setting register

• Register List

External interrupt enable register (ENIR)

bit

7

6

5

4

3

2

1

0

EN7

EN6

EN5

EN4

EN3

EN2

EN1

EN0

External interrupt request register (EIRR)

bit

15

14

13

12

11

10

9

8

ER7

ER6

ER5

ER4

ER3

ER2

ER1

ER0

Request level setting register (ELVR)

bit

15

14

13

12

11

10

9

8

LB7

LA7

LB6

LA6

LB5

LA5

LB4

LA4

bit

7

6

5

4

3

2

1

0

LB3

LA3

LB2

LA2

LB1

LA1

LB0

LA0

69

MB91301 Series

5. Delay Interrupt Module

The delay interrupt module is used to generate interrupts for task switching.

This module can be used to generate and cancel interrupts to the CPU via software.

• Block Diagram

R-bus

DLYI

Interrupt request

• Register List

Delay interrupt control register (DICR)

bit

7

6

5

4

3

2

1

0

⎯

DLYI

70

MB91301 Series

6. PPG Timer

The PPG timer can output highly precise PWM waveforms efficiently.

The MB91301 series contains four channels of PPG timer.

• Features of the PPG Timer

• Each channel consists of a 16-bit down counter, a 16-bit data register with cycle setting buffer, a 16-bit compare

register with duty setting buffer, and pin control section.

• The count clocks for the 16-bit down counter can be selected from the following four types :

Internal clock φ, φ/4, φ/16, φ/64

• The counter is initialized to “FFFF^H” at a reset or counter borrow.

• Each channel has a PPG output.

• Register outline

Cycle setting register: Reload data register with buffer

Duty setting register: Compare register with buffer

Transfer from the buffer takes place upon a counter borrow.

• Pin control overview

A duty match sets the pin control section to 1. (Preferential)

A counter borrow resets it to 0.

The output value fix mode is available, which can each output all "L" (or "H").

A polarity can also be specified.

• An interrupt request can be generated at a combination of the following events :

Activation of the PPG timer

Counter borrow (cycle match)

Duty match

Counter borrow (cycle match) or duty match

DMA transfer can be initiated by the above interrupt request.

• It is possible to set the simultaneous activation of two or more channels by means of software or another

interval timer.

Restarting during operation can also be set.

• The request level to be detected can be selected from among "rising edge", "falling edge", and "both edges".

71

MB91301 Series

• Block diagram

16-bit reload timer

ch0

TRG input

PPG timer ch0

PPG0

PPG1

PPG2

PPG3

16-bit reload timer

ch1

TRG input

PPG timer ch1

General

control

register 1

4

General control

(resource select)

TRG input

PPG timer ch2

register 2

4

TRG input

PPG timer ch3

External TRG0 to TRG3

• Block diagram for 1 channel

PCSR

PDUT

Prescaler

1 / 1

cmp

1 / 4

Load

CK

1 / 16

1 / 64

16-bit down counter

Start Borrow

PPG mask

PPG output

S

Q

Peripheral clock

R

Conversion

bit

Enable

IRQ

Edge

detection

TRG input

Soft trigger

72

MB91301 Series

• Register List

bit 15

7

0

General control register 10

GCN10

General control register 20

ch0 timer register

GCN20

PCNL0

PCNL1

PCNL2

PCNL3

PTMR0

PCSR0

PDUT0

ch0 cycle setting register

ch0 duty setting register

ch0 control status register

PCNH0

PCNH1

PCNH2

PCNH3

ch1 timer register

PTMR1

PCSR1

PDUT1

ch1 cycle setting register

ch1 duty setting register

ch1 control status register

ch2 timer register

PTMR2

PCSR2

PDUT2

ch2 cycle setting register

ch2 duty setting register

ch2 control status register

ch3 timer register

PTMR3

PCSR3

PDUT3

ch3 cycle setting register

ch3 duty setting register

ch3 control status register

73

MB91301 Series

7. 16-Bit Reload Timer

The 16-bit timer consists of a 16-bit down-counter, 16-bit reload register, prescaler for generating the internal

count clock, and a control register.

The clock source can be selected from three internal clock signals (machine clock divided by 2, 8, or 32) or the

external event.

The interrupt can be used to initiate DMA transfer.

The MB91301 series has three 16-bit reload timer channels.

• Block Diagram

16

16-bit reload register (TMRLR)

7

Reload

16

16-bit down counter (TMR) UF

Count enable

RELD

OUT

CTL.

INTE

UF

IRQ

Re-trigger

CNTE

TRG

Clock selector

CSL1

CSL0

EXCK

3

IN CTL.

φ

Prescaler

clear

3

External

trigger

selection

MOD0

2¹2³2⁵

External trigger input (TI)

MOD1

MOD2

CLKP input

3

74

MB91301 Series

• Register List

Control status register (TMCSR)

bit

15

14

13

12

11

10

9

8

⎯

CSL1

CSL0

MOD2 MOD1

bit

7

6

5

4

3

2

1

0

MOD0

⎯

OUTL

RELD

INTE

UF

CNTE

TRG

16-bit timer register (TMR)

bit

15

0

16-bit reload register (TMRLR)

bit

15

75

MB91301 Series

8. U-TIMER (16 bit timer for UART baud rate generation)

The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Any desired baud rate can be set

using the combination of the chip operating frequency and U-TIMER reload value.

The U-TIMER can also be used as an interval timer by generating an interrupt from a count underflow event.

The MB91301 series has three U-TIMER channels. When used as an interval timer, two U-TIMER channels can

be connected in cascade for a maximum count interval of up to 2³²× φ.

Cascade connection is only available for ch0 and ch1 or ch0 and ch2.

• Block Diagram

15

0

UTIMR (reload register)

load

UTIM (timer)

clock

underflow

f.f.

control

φ (CLKP)

(Peripheralclock)

MUX

ch0 only

to UART

under flow U-TIMER 1

76

MB91301 Series

• Register List

15

8

7

0

UTIM

UTIMR

UTIMC

• U-TIMER (UTIM)

Address bit

Initial value

15

b15

R

14

b14

R

2

b2

R

1

0

000064^H(ch 0)

00006C^H(ch 1)

000074^H(ch 2)

b1

R

b0

R

00000000 00000000^B

UTIM contains the timer value. Use a 16-bit transfer instruction to access the register.

Reload register (UTIMR)

Address

bit

Initial value

15

b15

W

14

b14

W

2

1

0

000064^H(ch 0)

00006C^H(ch 1)

000074^H(ch 2)

b2

W

b1

W

b0

W

00000000 00000000^B

UTIMR is the register that contains the value to be reloaded to UTIM when UTIM causes an underflow.

Use a 16-bit transfer instruction to access the register.

77

MB91301 Series

9. UART

The UART is a serial I/O port for asynchronous (start-stop synchronized) or CLK synchronized transmission.

The MB91301 series has three UART channels.

• UART Features

• Full duplex double buffer

• Asynchronous (start-stop synchronized) or CLK synchronized transmission

• Supports multi-processor mode

• Fully programmable baud rate

The internal timer can be set to any desired baud rate (see “8. U-TIMER” description)

• Variable baud rate can be input from an external clock.

• Error detection functions (parity, framing, overrun)

• Transmission signal format is NRZ

• The interrupt can be used to initiate DMA transfer.

• The DMAC interrupt can be cleared by writing to the DRCL register.

78

MB91301 Series

• Block Diagram

Control signal

RX interrupt

(to CPU)

SCK (clock)

TX interrupt

(to CPU)

TX clock

From U-TIMER

Clock

selection

circuit

RX clock

External clock

SCK

RX control circuit

TX control circuit

SI (Receive data)

Start bit detect

circuit

TX start

circuit

Receive bit

counter

Send bit

counter

Receive parity

counter

Send parity

counter

SO (Send data)

Receive status

decision circuit

RX shifter

RX

TX shifter

TX start

complete

SIDR

SODR

Receive error

signal for DMA

(to DMAC)

R - bus

MD1

MD0

PEN

P

PE

ORE

SBL

CL

FRE

RDRF

TDRE

BDS

RIE

SMR

register

SCR

register

SSR

register

CS0

A/D

REC

RXE

TXE

SCKE

TIE

Control

signal

79

MB91301 Series

• Register List

15

8

7

0

SCR

SMR

(R/W)

SSR

SIDR (R)/SODR (W)

DRCL

8 bit

(W)

8 bit

Serial input data register

Serial output data register (SIDR/SODR)

7

6

5

4

3

2

1

0

bit

D7

D6

D5

D4

D3

D2

D1

D0

Serial status register (SSR)

7

6

5

4

3

2

1

0

bit

PE

ORE

FRE

RDRF TDRE

BDS

RIE

TIE

Serial mode register (SMR)

7

6

5

4

3

2

1

0

bit

MD1

MD0

⎯

CS0

⎯

SCKE

⎯

Serial control register (SCR)

7

6

5

4

3

2

1

0

bit

PEN

P

SBL

CL

A/D

REC

RXE

TXE

DRCL register (DRCL)

7

6

5

4

3

2

1

0

bit

⎯

80

MB91301 Series

10. A/D Converter (Successive Approximation Type)

The A/D converter converts analog input voltages to digital values.

• A/D Converter Features

• Peripheral clock (CLKP) 140 clock cycle

• Minimum conversion time 4.1 µs/ch (for machine clock 34 MHz = CLKP)

• Built-in sample & hold circuit

• Resolution = 10-bit

• 4 channel program-selectable analog inputs

Single conversion mode : Convert 1 specified channel

Scan conversion mode : Continuous conversion of multiple channels. Conversion can be specified for up

to 4 channels.

• Single, continuous, and stop conversion operation is supported.

Single conversion mode

: Convert specified channel then stop.

Continuous conversion mode : Perform continuous conversion for the selected channel.

Stop conversion mode

: Perform conversion for one channel, then wait for the next activation trigger

(synchronizes the conversion start timing)

• DMA transfer can be initiated by an interrupt.

• Selectable conversion activation trigger: Software, external trigger (falling edge), or reload timer (rising edge)

81

MB91301 Series

• Block Diagram

AVCC AVRH AV^SSAVR

Internal voltage

generator

Sample & hold circuit

AN0

AN1

AN2

AN3

Successive

approximation register

Data register

(ADCR : 10 bit)

Upper 8 bit COPY

Data register

(ADCR0 to ADCR7 : 8bit)

Channel decoder

A/D control register

(ADCS)

Timing generation circuit

Machine clock

φ (CLKP)

Prescaler

ATG (Externalpintrigger)

Reload timer ch2

(internal connection)

• Register List

Control status register (ADCS)

15

14

13

12

11

10

9

8

bit

BUSY

INT

INTE

CRF

STS1

STS0

STRT

⎯

7

6

5

4

3

2

1

0

bit

MD1

MD0

ANS2

ANS1

ANS0

ANE2

ANE1

ANE0

Data register (ADCR)

15

14

13

12

11

10

9

8

bit

⎯

7

6

5

4

3

2

1

0

bit

7

Conversion result register (ADCR0 to ADCR3)

7

6

5

4

3

2

1

0

bit

7

6

5

82

MB91301 Series

11. DMAC (DMA Controller)

The DMA controller is used to perform DMA (direct memory access) transfer on the FR family device.

Using DMA transfer under the control of the DMA controller improves system performance by enabling data to

be transferred at high speed independently of the CPU.

• Hardware Configuration

• Independent DMA channels × 5 channels

• 5-channel independent access control circuits

• 32-bit address register (Supports reloading : 2 per channel)

• 16-bit transfer count register (Supports reloading : 1 per channel)

• 4-bit block count register (1 per channel)

• External transfer request input pins : DREQ0, DREQ1 (ch0, ch1 only)

• External transfer request acknowledge output pins : DACK0, DACK1 (ch0, ch1 only)

• DMA completion output pins : DEOP0, DEOP1 (ch0, ch1 only)

• fly-by transfer (memory to I/O , I/O to memory) (ch0, ch1 only)

• Two-cycle transfer

• Main Functions of the DMA Controller

• Supports independent data transfer for multiple channels (5 channels)

(1) Priority order (ch 0 > ch 1 > ch 2 > ch 3 > ch 4)

(2) Order can be reversed for ch 0 and ch 1

(3) DMAC activation triggers

• Input from dedicated external pin (edge detection/level detection, ch 0, ch 1 only)

• Request from built-in peripheral (shared interrupt request, including external interrupts)

• Software request (register write)

(4) Transfer modes

• Demand transfer, burst transfer, step transfer, or block transfer

Addressing mode: Full 32-bit address (increment/decrement/fixed)

(address increment can be in the range−255 to +255)

• Data type : byte/half-word/word

• Single-shot or reload operation selectable

83

MB91301 Series

• Block Diagram

Counter

Buffer

DMA

start trigger

selection

circuit & request

acknowledge

control

DMA transfer

request to bus

controller

Peripheral start request/

Stop input

Selector

External pin start

request/Stop input

DTC two-stage register

DTCR

Counter

Buffer

DSS [3:0]

Priority

circuit

IRQ

[4:0]

To interrupt controller

Read

Write

Read/write

control

Selector

ERIR, EDIR

MCLREQ

BLK register

Clear peripheral interrupt

Status

transition

circuit

TYPE, MOD, WS

DDNO register

DDNO

DMA control

DSAD two-stage register

SDAM, SASZ [7:0] SADR

Access

Write back

ad-

dress

DADM, DASZ [7:0] DADR

DDAD two-stage register

Write back

5-channel DMAC block diagram

84

MB91301 Series

• Register List

bit 31

24 23

16 15

08 07

00

ch 0 control status

ch 1 control status

ch 2 control status

ch 3 control status

ch 4 control status

register A DMACA0 0000200H

register B DMACB0 0000204H

register A DMACA1 0000208H

DMACB1 000020CH

DMACA2 0000210H

DMACB2 0000214H

DMACA3 0000218H

DMACB3 000021CH

DMACA4 0000220H

DMACB4 0000224H

register B

register A

register B

register A

register B

register A

register B

bit 31

24 23

16 15

08 07

00

DMACR 0000240H

Overall control register

DMASA0 0001000H

DMADA0 0001004H

DMASA1 0001008H

DMADA1 000100CH

DMASA2 0001010H

DMADA2 0001014H

DMASA3 0001018H

DMADA3 000101CH

DMASA4 0001020H

DMADA4 0001024H

ch 0 transfer source address register

ch 0 transfer destination address register

ch 1 transfer source address register

ch 1 transfer destination address register

ch 2 transfer source address register

ch 2 transfer destination address register

ch 3 transfer source address register

ch 3 transfer destination address register

ch 4 transfer source address register

ch 4 transfer destination address register

85

MB91301 Series

12. I²C Interface

I²C interface is the serial I/O port that support INTER IC BUS and functions as the master/slave device on the

I²C bus. It has the features below.

• Master/slave transmission and reception

• Arbitration function

• Clock synchronization

• Slave address/general call address detection function

• Forwarding direction detection function

• The function of generating/detecting repeat “START” conditions.

• Bus error detection function

• 10-bit/7-bit slave address

• Control slave address receiving at the master mode

• For support multiple slave address

• Can be interrupt at transmitting or bus mirror

• For normal mode (Max 100 Kbps) /fast mode (Max 400 Kbps)

86

MB91301 Series

• Block Diagram (1 ch)

ICCR

EN

I²C operating enable

IDBL

DBL

Clock enable

CLKP

ICCR

CS4

CS3

CS2

CS1

CS0

Clock dividing 2

2 3 4 5

32

Shift clock

generation

Sync

Clock select 2 (1/12)

Shift clock edge

change timing

IBSR

BB

Bus busy

Repeat start

Last Bit

RSC

LRB

TRX

ADT

AL

Start/stop condition

detection

Transmission/

reception

Error

First Byte

Arbitration lost

detection

IBCR

BER

SCL0/1

SDA0/1

BEIE

INTE

INT

Interrupt request

IRQ

IBCR

SCC

End

Start

Master

MSS

ACK

Start/stop condition

generation

ACK enable

GC-ACK enable

GCAA

IDAR

IBSR

AAS

GCA

Slave

Slave address

comparison

Global call

ISMK

FNSB

ITMK

ENTB

RAL

ITBA

ITMK

ISBA

ISMK

87

MB91301 Series

• Register List

• Bus control register (IBCR0/1)

15

14

13

12

11

10

9

8

Address :

000094^H/0000B4^H

BER

BEIE

SCC

MSS

ACK

GCAA

INTE

INT

R/W

0

R/W

0

W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Initial value = >

• Bus status register (IBSR0/1)

7

6

5

4

3

2

1

0

Address :

000095^H/0000B5^H

BB

RSC

AL

LRB

TRX

AAS

GCA

ADT

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Initial value = >

• 10-bit slave address register (ITBA0/1)

15

14

13

12

11

10

9

8

Address :

000096^H/0000B6^H

⎯

TA9

TA8

R

0

R

0

R

0

R

0

R

0

R/W

0

R/W

0

R

0

Initial value = >

Address :

7

6

5

4

3

2

1

0

000097^H/0000B7^H

TA7

TA6

TA5

TA4

TA3

TA2

TA1

TA0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Initial value = >

(Continued)

88

MB91301 Series

(Continued)

• 10-bit slave address mask register (ITMK0/1)

15

14

13

12

11

10

9

8

Address :

000098^H/0000B8^H

ENTB

RAL

⎯

TM9

TM8

R/W

0

R

0

R

1

R

1

R

1

R

1

R/W

1

R/W

1

Initial value = >

7

6

5

4

3

2

1

0

Address :

000099^H/0000B9^H

TM7

TM6

TM5

TM4

TM3

TM2

TM1

TM0

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Initial value = >

• 7-bit slave address register (ISBA0/1)

7

6

5

4

3

2

1

0

Address :

00009B^H/0000BB^H

⎯

SA6

SA5

SA4

SA3

SA2

SA1

SA0

R

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Initial value = >

• 7-bit slave address mask register (ISMK0/1)

15

14

13

12

11

10

9

8

Address :

00009A^H/0000BA^H

ENSB

SM6

SM5

SM4

SM3

SM2

SM1

SM0

R/W

0

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Initial value = >

•Data register (IDAR0/1)

Address :

7

6

5

4

3

2

1

0

00009D^H/0000BD^H

D7

D6

D5

D4

D3

D2

D1

D0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Initial value = >

•Clock control register (ICCR0/1)

15

14

13

12

11

10

9

8

Address :

00009E^H/0000BE^H

TEST

⎯

EN

CS4

CS3

CS2

CS1

CS0

W

0

R

0

R/W

0

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Initial value = >

•Clock disable register (IDBL0/1)

7

6

5

4

3

2

1

0

Address :

00009F^H/0000BF^H

⎯

DBL

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R/W

0

Initial value = >

89

MB91301 Series

13. 16 bit Free Run Timer

16-bit free-run timer consists of a 16-bit up counter and a control status register.

The timer count value is used as the base timer of output compare and input capture.

• The count clock can be selected from four different clocks.

• Can be generated the interrupt by the counter over-flow.

• Setting the mode enables initialization of counter through compare-match operation with the value of the

compare clear register0 in the output compare.

90

MB91301 Series

•Block Diagram

Interrupt

ECLK

IVF

IVFE

STOP

MODE

CLR

CLK1

CLK0

φ

Prescaler

FRCK

Clock selector

16-bit Free run Timer

(TCDT)

Clock

To internal circuit (T15 to T00)

Comparator0

•Register List

Timer data register (upper)

(TCDT)

15

14

13

12

11

10

9

8

T15

T14

T13

T12

T11

T10

T9

T8

Timer data register (lower)

(TCDT)

7

6

5

4

3

2

1

0

T07

T06

T05

T04

T03

T02

T01

T00

Timer control status register

7

6

5

4

3

2

1

0

(lower)

(TCCS)

ECLK

IVF

IVFE

STOP MODE

CLR

CLK1

CLK0

91

MB91301 Series

14. Input Capture

This module has a function that detects a rising edge, falling edge or both edges and holds a value of the

16-bit free-run timer in a register at the time of detection. It can also generate an interrupt when detecting an edge.

The input capture consist of input capture and control registers.

Each input capture have the corresponded external input pins.

• The valid edge of the external input can be selected from three types :

Rising edge

Falling edge

Both edges

• It can generate an interrupt when it detects the valid edge of the external input.

92

MB91301 Series

•Block Diagram

16-bit timer count value (T15 to T00)

ICU0, ICU2

input pin

Capture data register

ch (0, 2)

Edge detection

EG01

EG21

EG00

EG20

EG11

EG31

EG10

EG30

16-bit timer count value (T15 to T00)

ICU1, ICU3

input pin

Capture data register

ch (1, 3)

Edge detection

ICP1

ICP3

ICP0

ICE1

ICE3

ICE0

ICP2

ICE2

Interrupt

93

MB91301 Series

•Register List

Input capture data register (upper)

(IPCP)

15

14

13

12

11

10

9

8

CP15

CP14

CP13

CP12

CP11

CP10

CP09

CP08

Input capture data register (lower)

(IPCP)

7

6

5

4

3

2

1

0

CP07

CP06

CP05

CP04

CP03

CP02

CP01

CP00

Capture control register

(ICS23)

7

6

5

4

3

2

1

0

ICP3

ICP2

ICE3

ICE2

EG31

EG30

EG21

EG20

Capture control register

(ICS01)

7

6

5

4

3

2

1

0

ICP1

ICP0

ICE1

ICE0

EG11

EG10

EG01

EG00

94

MB91301 Series

15. Clock Generation Control

The internal operating clock is generated as follows in MB91301 series.

• Source clock selection : Selects the clock source.

• Base clock generation : The base clock is generated by dividing the source clock by 2 or using a PLL.

• Generation in each internal block : The base clock is divided to generate the operating clock for each block.

95

MB91301 Series

• Block Diagram

[Clock generator]

DIVR0, 1 register

CPU clock division

CPU clock

(CLKB)

Peripheral clock

division

Peripheral clock

(CLKP)

External bus clock

division

External bus

clock (CLKT)

CLKRregister

Oscilla-

tion

circuit

X0

X1

PLL

1/2

[Stop/sleep

controller]

Internal interrupt

Internal reset

Stop state

State

transi-

tion

control

circuit

STCR register

SLEEP state

Reset F/F

Internalreset(RST)

Internalreset(INIT)

[Reset circuit]

INIT pin

RSRR register

[Watchdog controller]

WPR register

Watchdog F/F

Timebase counter

Count clock

CTBR register

Selector

Overflow detection F/F

TBCR register

Timebase timer

interrupt request

Interrupt enable

96

MB91301 Series

• Register List

• RSRR : Reset initiation register/Watchdog timer control register

bit

Address : 00000480^H

15

INIT

R

14

⎯

R

0

13

12

⎯

R

0

11

10

⎯

R

0

9

WT1

R/W

0

8

WT0

R/W

0

WDOG

SRST

R

0

R

0

Initial value (INIT pin)

Initial value (INIT)

Initial value (RST)

1

−

0

−

X

−

0

X

−

X

0

• STCR : Standby control register

bit

7

6

5

HIZ

R/W

1

4

SRST

R/W

1

3

OS1

R/W

0

2

OS0

R/W

0

1

⎯

−

0

Address : 00000481^HSTOP SLEEP

OSCD1

R/W

1

Initial value (INIT pin)

Initial value (INIT)

Initial value (RST)

0

1

X

−

1

X

1

X

−

X

• TBCR : Timebase counter control register

bit

Address : 00000482^H

15

TBIF

R/W

0

14

TBIE

R/W

0

13

TBC2

R/W

X

12

TBC1

R/W

X

11

TBC0

R/W

X

10

⎯

−

9

8

SYNCR SYNCS

R/W

0

R/W

0

Initial value (INIT)

Initial value (RST)

0

X

−

X

• CTBR : Timebase counter clear register

bit

Address : 00000483^H

7

D7

W

X

6

D6

W

X

5

D5

W

X

4

D4

W

X

3

D3

W

X

2

D2

W

X

1

D1

W

X

0

D0

W

X

Initial value (INIT)

Initial value (RST)

X

• CLKR : Clock source control register

bit

Address : 00000484^H

15

⎯

−

14

13

12

11

⎯

−

10

9

8

PLL1S2 PLL1S1 PLL1S0

PLL1EN CLKS1 CLKS0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Initial value (INIT)

Initial value (RST)

−

X

−

X

(Continued)

97

MB91301 Series

(Continued)

• WPR : Watchdog reset generation delay register

bit

Address : 00000485^H

7

D7

W

X

6

D6

W

X

5

D5

W

X

4

D4

W

X

3

D3

W

X

2

D2

W

X

1

D1

W

X

0

D0

W

X

Initial value (INIT)

Initial value (RST)

X

• DIVR0 : Base clock division setting register 0

bit

Address : 00000486^H

15

B3

R/W

0

14

B2

R/W

0

13

B1

R/W

0

12

B0

R/W

0

11

P3

R/W

0

10

P2

R/W

0

9

P1

R/W

1

8

P0

R/W

1

Initial value (INIT)

Initial value (RST)

X

• DIVR1 : Base clock division setting register 1

bit

Address : 00000487^H

7

T3

R/W

0

6

T2

R/W

0

5

T1

R/W

0

4

T0

R/W

0

3

⎯

−

2

⎯

−

1

⎯

−

0

⎯

−

Initial value (INIT)

Initial value (RST)

X

−

− : Changes depending on what triggered the reset.

× : Not initialized

98

MB91301 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(V^SS= AV^SS= 0 V)

Rating

Parameter

Supply voltage

Symbol

Unit

Remarks

Min

Max

V^CC

V^SS− 0.5

V^SS+ 4.0

V

*1

*2

Analog supply voltage

AV^CC

AVRH,

AVRL

Analog reference voltage

V^SS− 0.5

AV^CC

V

*2

Input voltage

V^I

V^SS− 0.3

V^CC+ 0.3

V

Analog pin input voltage

Output voltage

V^IA

V^OH

AV^CC+ 0.3

V^CC+ 0.3

“L” level maximum output

current

I^OL

⎯

10

8

mA

*3

*4

“L” level average output current

I^OLAV

ΣI^OL

“L” level total maximum output

current

100

“L” level total average output

current

ΣI^OLAV

⎯

50

mA

*5

“H” level maximum output

current

I^OH

⎯

−10

−4

mA

*3

*4

“H” level average output current

I^OHAV

ΣI^OH

“H” level total maximum output

current

−50

“H” level total average output

current

ΣI^OHAV

⎯

−20

mA

*5

Power consumption

Operating temperature

Storage temperature

P^D

Ta

⎯

0

1000

+70

mW

°C

T^STG

−50

+150

°C

*1 : V^CCmust not be lower than V^SS− 0.3 V.

*2 : AV^CC, AVRH and AVRL should not exceed V^CC+0.3 V, including at power-on. AVRH and AVRL should not exceed

AV^CC. Also AVRL should not exceed AVRH.

*3 : The maximum output current is the peak value for a single pin.

*4 : The average output current is the average current for a single pin over a period of 100ms.

*5 : The total average output current is the average current for all pins over a period of 100ms.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

99

MB91301 Series

2. Recommended Operating Conditions

(V^SS= AV^SS= 0 V)

Remarks

Value

Parameter

Supply voltage

Symbol

Unit

Min

3.0

Max

3.6

V^CC

AV^CC

AVRH

AVRL

Ta

V

Normal operation

Analog supply voltage

Analog reference voltage

Operating temperature

V^SS+ 3

AV^SS

0

3.6

AV^CC

AVRH

+70

V

°C

The maximum power rising slope (∆V/∆t) must be 0.05 V/µs when the 3 V power supply is turned on.

It takes about 100 µs until the 2.5 V power supply becomes stable after the 3 V power supply becomes stable.

Keep INIT input during that interval.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

100

MB91301 Series

3. DC Characteristics

(V^CC= 3.0 V to 3.6 V , V^SS= AV^SS= 0 V, Ta = 0 °C to +70 °C)

Value

Sym-

Parameter

bol

Pin name

Condition

Unit

Remarks

Min

Typ

Max

Non-hystere-

sis input pin

V^IH

V^IHS

V^IL

⎯

2.0

⎯

V^CC+ 0.3

V

“H” level input

voltage

Hysteresis

input pin

0.8 × V^CC

V^SS

⎯

V^CC+ 0.3

0.8

Hysteresis input

Non-hystere-

sis input pin

“L” level input

voltage

Hysteresis

input pin

V^ILS

V^SS

0.2 × V^CC

V^CC

“H” level output

voltage

V^CC= 3.0 V

I^OH= −4.0 mA

V^CC= 3.0 V

I^OL= 4.0 mA

V^OHAll output pins

V^OLAll output pins

V^CC− 0.4

V^SS

“L” level output

voltage

0.4

Input leak

current

(Hi-Z output

leak current)

V^CC= 3.6 V

I^LI

All input pins* 0.45 V < V^I<

−5

⎯

+5

µA

kΩ

V^CC

Pull-up

resistance

With pins Pull- V^CC= 3.6 V

up settings V^I= 0.45 V

R^UP

10

25

120

When operating at :

CLKB : 68 MHz

mA CLKT : 68 MHz

CLKP : 34 MHz

(×4 multiplier)

f^C= 17 MHz

V^CC= 3.6 V

I^CC

⎯

120

150

Power supply

current

V^CC

When sleeping at :

mA CLKP : 34 MHz

in sleep mode

f^C= 17 MHz

V^CC= 3.6 V

I^CCS

⎯

50

90

Ta = +25 °C

V^CC= 3.6 V

I^CCH

200

700

µA In stop mode

Except for

V^CC

V^SS

AV^CC

AV^SS

Input

capacitance

⎯

C^IN

⎯

5

15

pF

AVRH

AVR

* : Excludes X0, X1, pins with internal pull-up resistor (INIT, TRST), and pins with a pull-up resistor set by PCR.

101

MB91301 Series

4. AC Characteristics

(1) Clock Timing Ratings

(V^CC= 3.0 V to 3.6 V , V^SS= AV^SS= 0 V, Ta = 0 °C to +70 °C)

Value

Sym- Pin

bol name

Condi-

tion

Parameter

Unit

Remarks

Min

Max

X0,

X1

Using PLL

Clock frequency (1)

f^C

12.5

17

MHz

(When operating at max in-

ternal frequency (68 MHz) =

17 MHz self-oscillation with

×4 PLL)

Self-oscillation (1/2 division

input)

⎯

X0,

X1

Clock cycle time

t^C

⎯

58.8

34

ns

X0,

X1

Clock frequency (2)

f^C

⎯

10

MHz

f^CP

0.78*

14.7

68

34

MHz CPU

Internal operation clock

frequency

f^CPP

f^CPT

t^CP

⎯

MHz Peripherals

MHz External bus

ns CPU

68

1280*

Internal operation clock

cycle time

t^CPP

t^CPT

⎯

29.4

ns Peripherals

ns External bus

14.7

* : Values are for minimum clock frequency (12.5 MHz) input to X0, oscillation circuit uses PLL, and gear ratio = 1/16.

• Conditions for measuring the clock timing ratings

tC

0.8 VCC

Output pin

C = 50 pF

• Warranted operation range

V^CC(V)

Warranted operation range (Ta = 0 °C to +70 °C)

f^CPPis represented by the shaded area.

3.6

3.0

fCP / fCPP

(MHz)

0

0.78

34

68

Internal operation clock

102

MB91301 Series

• External/internal clock setting range

fcp, fCPT MHz

70

68

4 multiplier (CPU)

5 multiplier (CPU)

60

50

40

30

20

10

0

3 multiplier (CPU)

48

f

CPP

34

4 multiplier, 2 divide

(CPU, peripheral)

5 multiplier, 2 divide

(CPU, peripheral)

3 multiplier, 2 divide

(CPU, peripheral)

24

22.7

4 multiplier, 3 divide

(CPU, peripheral)

5 multiplier, 3 divide

(CPU, peripheral)

17

4 multiplier, 4 divide

(CPU, peripheral)

1/2 divide

5

fc

0

10

PLL

20

30

MHz

12.5

17

34

Notes : • If using the PLL, input an external clock in the range 12.5 MHz to 17 MHz.

• Allow a PLL oscillation stabilization time > 300 µs.

• Set the gear ratio for the internal clock to be within the values shown in the “(1) Clock Timing Ratings”

table.

103

MB91301 Series

(2) Clock Output Timing

(V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, Ta = 0 °C to +70 °C)

Value

Sym-

Parameter

bol

Pin name Condition

Unit Remarks

Min

Max

SYSCLK,

MCLK

Cycle time

t^CYC

t^CHCL

t^CLCH

t^CPT

⎯

ns

*1

*2

*3

SYSCLK,

MCLK

1

2

1

2

SYSCLK↑→SYSCLK↓

SYSCLK↓→SYSCLK↑

⎯

t^CYC−2.35

t^CYC+2.65

SYSCLK,

MCLK

1

2

1

2

t

CYC

t

CHCL

t

CLCH

V

OH

V

OH

SYSCLK

MCLK

V

OL

*1 : t^CYCis the frequency of one clock cycle after gearing.

*2 : The following ratings are for the gear ratio set to × 1.

For the ratings when the gear ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the

following equation.

Min : (1 / 2 × 1 / n) × t^CYC− 2.35

Max : (1 / 2 × 1 / n) × t^CYC+ 2.65

*3 : The following rating are for the gear ratio set to × 1.

Min : (1 / 2 × 1 / n) × t^CYC− 2.35

Max : (1 / 2 × 1 / n) × t^CYC+ 2.65

(3) Reset and Tool Reset Input Ratings

(V^CC= 3.0 V to 3.6 V , V^SS= AV^SS= 0 V, Ta = 0 °C to +70 °C)

Value

Sym-

bol

Parameter

Pin name Condition

Unit

Remarks

Min

Max

INIT input time (at power-on)

20 + α

⎯

µs

INIT input time

( other than at power-on)

INIT,

⎯

t^CP× 5

20 + α

⎯

ns

t^INTL

TRST

INIT input time

(recovery from stop)

µs

tINTL

INIT

TRST

0.2 VCC

104

MB91301 Series

(4) Normal Bus Access Read/Write Operation

Sym-

(V^CC= 3.0 V to 3.6 V , V^SS= AV^SS= 0 V, Ta = 0 °C to +70 °C)

Value

Parameter

Pin name

Condition

Unit Remarks

bol

Min

3

Max

⎯

CS0 to CS7 setup

t^CSLCH

t^CHCSH

ns

SYSCLK,

CS0 to CS7

CS0 to CS7 hold

Address setup

3

t^CYC/ 2 + 4

SYSCLK,

A23 to A00

t^ASCH

t^ASWL

3

⎯

ns

WR0 to WR3,

A23 to A00

4

5

3

⎯

ns

t^ASRLRD, A23 to A00

SYSCLK,

t^CHAX

t^CYC/ 2 + 4

A23 to A00

Address hold

WR0 to WR3,

t^WHAX

t^CYC/ 2 − 5

t^CYC/ 2 − 7

⎯

ns

A23 to A00

t^RHAXRD, A23 to A00

Valid address→

Valid data input time

A23 to A00,

t^AVDV

3 / 2×t^CYC−

ns

*

D31 to D00

11

WR0 to WR3 delay time

t^CHWL

t^CHWH

⎯

6

ns

SYSCLK, WR,

WR0 to WR3

WR0 to WR3 minimum pulse

width

WR,

WR0 to WR3

t^WLWH

t^DSWH

t^WHDX

t^CYC− 5

t^CYC

⎯

ns

⎯

Data setup

→WRx↑

WR,

WR0 to WR3,

D31 to D00

WRx↑→

Data hold time

5

RD delay time

t^CHRL

t^CHRH

⎯

6

ns

SYSCLK,

RD

10

RD↓→

t^RLDV

t^DSRH

t^RHDX

⎯

10

0

t^CYC− 10

ns

*

Valid data input time

Data setup

→RD↑ time

RD,

D31 to D00

⎯

RD↑→

Data hold time

RD minimum pulse width

AS setup

t^RLRH

t^ASLCH

t^CHASH

t^BLCH

RD

t^CYC− 5

⎯

ns

t^CYC/ 2 − 6

SYSCLK,

AS

AS hold

3

t^CYC/ 2 − 6

3

UUB/ULB/LUB/LLB set up

UUB/ULB/LUB/LLB hold

SYSCLK, UUB/

ULB/LUB/LLB

t^CHBH

* : When the bus is delayed by automatic wait insertion or RDY input, add (t^CYC× number of wait cycles) to the rated

values.

105

MB91301 Series

t

CYC

BA1

VOH

MCLK

SYSCLK

tASLCH

tCHASH

VOH

AS

(LBA)

VOL

tCSLCH

tCHCSH

VOH

CS0 to CS7

VOL

tASCH

tCHAX

VOH

VOL

VOH

VOL

A23 to A00

tCHRH

tCHRL

tRLRH

RD

VOH

VOL

tASRL

tRHAX

tRHDX

tRLDV

tDSRH

tAVDV

D31 to D00

VOH

VOL

VOH

VOL

tCHWL

tCHWH

tWLWH

VOH

WR0 to WR3

WR

VOL

tASWL

tWHAX

tWHDX

(at WR-control)

tDSWH

VOH

VOL

VOH

VOL

D31 to D00

Write

tBLCH

tCHBH

WR0 to WR3

(UUB, ULB,

LUB, LLB)

(at WR-control)

106

MB91301 Series

(5) BAA Timing

(V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, Ta = 0 °C to +70 °C)

Value

Sym-

bol

Parameter

Pin name

Condition

Unit Remarks

Min

t^CYC/ 2 − 6

3

Max

⎯

BAA setup

BAA hold

t^CHBAH

t^CHBAL

ns

SYSCLK,

BAA

⎯

t

CYC

V

OH

V

OH

MCLK

SYSCLK

t

CHBAH

t

CHBAL

BAA

107

MB91301 Series

(6) Ready Input Timings

(V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, Ta = 0 °C to +70 °C)

Value

Sym-

bol

Parameter

RDY setup time

Pin name Condition

Unit

Remarks

Min

Max

SYSCLK

⎯

t^RDYS

10

⎯

ns

→SYSCLK↓

RDY

SYSCLK↓→

RDY hold time

SYSCLK

⎯

t^RDYH

0

⎯

RDY

t

CYC

SYSCLK

MCLK

V

OH

VOH

V

OL

VOL

t

RDYS

tRDYH

t

RDYS

t

RDYH

RDY

V

OH

VOH

(Wait specified

by RDY)

V

OL

VOL

RDY

V

OH

VOH

(Nowaitspecified

by RDY)

V

OL

VOL

108

MB91301 Series

(7) Hold Timing

(V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, Ta = 0 °C to +70 °C)

Value

Sym-

bol

Parameter

Pin name Condition

Unit

Remarks

Min

⎯

Max

6

BGRNT delay time

t^CHBGL

t^CHBGH

ns

SYSCLK,

BGRNT

⎯

6

⎯

BGRNT,

each pins

Pin floating

→BGRNT ↓time

t^XHAL

t^HAHV

t^CYC− 10

t^CYC+ 10

ns

BGRNT ↑→pin valid time

Note : The time from receiving BRQ to BGRNT changing is one cycle or more.

tCYC

SYSCLK

MCLK

VOH

BRQ

tCHBGL

tCHBGH

VOH

BGRNT

VOL

tXHAL

tHAHV

Other pins

High-Z

109

MB91301 Series

(8) SDRAM Timing

(V^CC= 3.0 V to 3.6 V , V^SS= AV^SS= 0 V, Ta = 0 °C to +70 °C)

Value

Condi-

tion

Parameter

Symbol Pin name

Unit

Remarks

Min

⎯

5

Max

68

Output clock cycle time

“H” level clock pulse width

“L” level clock pulse width

t^CYCSD

t^CHSD

t^CLSD

MHz

ns

MCLK

⎯

5

⎯

ns

MCLKO↑→ output delay

t^ODSDCKE

t^OHSDCKE

t^ODSDRAS

t^OHSDRAS

t^ODSDCAS

t^OHSDCAS

t^ODSDWE

t^OHSDWE

t^ODSDCS

t^OHSDCS

t^ODSDA

⎯

2

11

⎯

11

⎯

11

⎯

11

⎯

11

⎯

11

⎯

11

ns

time

MCLKE

SRAS

Output hold time

MCLKO↑→ output delay

time

⎯

2

Output hold time

MCLKO↑→ output delay

time

⎯

2

SCAS

Output hold time

MCLKO↑→ output delay

time

⎯

2

SWE

Output hold time

⎯

MCLKO↑→ output delay

time

⎯

2

CS6, CS7

A00 to A15

Output hold time

MCLKO↑→ output delay

time

⎯

2

Output hold time

t^OHSDA

MCLKO↑→ output delay

time

DQMUU,

DQMUL,

DQMLU,

DQMLL

t^ODSDDQM

⎯

Output hold time

t^OHSDDQM

t^ODSDD

2

⎯

ns

MCLKO↑→ output delay

time

⎯

11

D00 to D31

Output hold time

t^OHSDD

t^ISSDD

t^IHSDD

2

4

2

⎯

ns

Data input setup time

Data input hold time

⎯

110

MB91301 Series

tCYCSD

MCLKO

tCHSD

tCLSD

tODSDCKE

tODSDRAS

tODSDCAS

tODSDWE

tODSDCS

tODSDA

MCLKE

SRAS

SCAS

SWE

CS6

tODSDDQM

CS7

A00 to A15

DQMUU

DQMUL

DQMLU

DQMLL

tOHSDCKE

tOHSDRAS

tOHSDCAS

tOHSDWE

tOHSDCS

tOHSDA

tOHSDDQM

tODSDD

D00 to D31

output

tOHSDD

D00 to D31

input

tISSDD

tIHSDD

111

MB91301 Series

(9) UART Timing

(V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, Ta = 0 °C to +70 °C)

Value

Sym-

Parameter

bol

Pin name

Condition

Unit Remarks

Min

Max

Serial clock cycle time

t^SCYC

t^SLOV

SCK0 to SCK2

8 t^CYCP

⎯

ns

SCK0 to SCK2,

SOT0 to SOT2

SCK↓ →SO delay time

−80

100

60

+80

⎯

Internal

shift clock

mode

SCK0 to SCK2,

SIN0 to SIN2

Valid SI →SCK↑

t^IVSH

ns

SCK0 to SCK2,

SIN0 to SIN2

SCK↑ → valid SIN hold time t^SHIX

⎯

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

t^SLSH

SCK0 to SCK2

4 t^CYCP

⎯

ns

SCK0 to SCK2,

SOT0 to SOT2

SCK↓ →SOT delay time

Valid SIN→SCK↑

t^SLOV

t^IVSH

t^SHIX

External

shift clock

mode

⎯

60

150

⎯

ns

SCK0 to SCK2,

SIN0 to SIN2

SCK0 to SCK2,

SIN0 to SIN2

SCK↑→ valid SIN hold time

⎯

Notes : • These are the AC ratings for CLK synchronous mode.

• t^CYCPis the peripheral clock cycle time.

112

MB91301 Series

• Internal shift clock mode

tSCYC

VOH

SCK0 to SCK2

VOL

tSLOV

VOL

VOH

VOL

SOT0 to SOT2

SIN0 to SIN2

tIVSH

tSHIX

VOH

VOL

VOH

VOL

• External shift clock mode

tSLSH

tSHSL

VOH

SCK0 to SCK2

VOL

tSLOV

VOH

VOL

SOT0 to SOT2

SIN0 to SIN2

tIVSH

tSHIX

VOH

VOL

VOH

VOL

113

MB91301 Series

(10) Reload Timer Clock and PPG Timer Input Timings

(V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, Ta = 0 °C to +70 °C)

Value

Sym-

bol

Parameter

Pin name

Condition

Unit Remarks

Min

Max

TIN0 to TIN2,

PPG0 to PPG3,

TRG0 to TRG3

t^TIWH

t^TIWL

Input pulse width

⎯

2 t^CYCP*

⎯

ns

* : t^CYCPis the peripheral clock cycle time.

TIN0 to TIN2

V

IH

VIH

PPG0 to PPG3

TRG0 to TRG3

V

IL

VIL

t

TIWL

t

TIWH

(11) Trigger Input Timing

(V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, Ta = 0 °C to +70 °C)

Value

Sym-

bol

Parameter

Pin name Condition

Unit

Remarks

Min

Max

A/D activation trigger input time t^ATGL

* : t^CYCPis the peripheral clock cycle time.

ATG

⎯

5 t^CYCP*

⎯

ns

tATGL

ATG

VIL

114

MB91301 Series

(12) DMA Controller Timing

(V^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, Ta = 0 °C to +70 °C)

[ For edge detection ] (Block/step transfer mode, burst transfer mode)

Value

Sym-

bol

Parameter

Pin name

Condition

Unit

Remarks

Min

Max

DREQ input pulse width t^DRWL

DREQ 0, DREQ1

⎯

2 t^CYC

⎯

ns

Note : When f^CPT> f^CP, t^CYCbecomes same as t^CP.

[ For level detection ] (Demand transfer mode)

Value

Sym-

bol

Parameter

Pin name

Condition

Unit

Remarks

Min

Max

SYSCLK,

DREQ 0, DREQ1

DSTP setup time

DSTP hold time

t^DREQS

10

⎯

ns

⎯

SYSCLK,

DREQ 0, DREQ1

t^DREQH

0.0

⎯

[ For all operation modes ]

Value

Sym-

Parameter

bol

Pin name

Condition

Unit

Remarks

Min

Max

10

t^CLDL

DACK delay time

t^CLDH

⎯

SYSCLK, DACK 0,

DACK1

ns

t^CLEL

DEOP delay time

t^CLEH

SYSCLK, DEOP 0,

DEOP1

⎯

t^CLIRL

IORD delay time

t^CLIRH

SYSCLK,

IORD

t^CLIWL

IOWR delay time

t^CLIWH

SYSCLK,

IOWR

115

MB91301 Series

tCYC

VOH

SYSCLK

MCLK

VOL

tCLDL

tCLEL

tCLDH

tCLEH

VOH

VOL

DACK0, DACK1

DEOP0, DEOP1

IORD

VOL

tCLIRL

tCLIWL

tCLIRH

tCLIWH

VOH

VOL

IOWR

tDRWL

tDREQS

tDREQH

VOH

DREQ0, DREQ1

VOL

VOH

VOL

116

MB91301 Series

(13) I²C Timing

• At master mode operation

(A^VCC= V^CC= 3.3 0.3 V, A^VSS= V^SS= 0.0 V, Ta = 0 °C to +70 °C)

Fast mode*³

Typical mode

Sym-

Parameter

bol

Conditions

Unit

Remarks

Min

0

Max

100

⎯

Min

0

Max

SCL clock frequency

f^SCLSCL0, SCL1

400 kHz

“L” period of SCL clock t^LOWSCL0, SCL1

“H” period of SCL clock t^HIGHSCL0, SCL1

BUS free time between

4.7

4.0

1.3

0.6

⎯

µs

⎯

“STOP condition” and

“START condition”

t^BUSSDA0, SDA1

4.7

⎯

5 × M*¹

⎯

1.3

⎯

µs

SCL↓→SDA output

delay time

SCL0, SCL1,

t^HDDAT

5 × M*¹ns

SDA0, SDA1

Setup time of “repeat

START condition”

SCL↑→SDA↓

SCL0, SCL1,

t^SUSTA

4.7

0.6

⎯

µs

R = 1 kΩ,

SDA0, SDA1

C = 50 pF*⁴

Hold time of “repeat

START condition”

SDA↓→SCL↓

After that, the

SCL0, SCL1,

t^HDSTA

4.0

⎯

0.6

µs first clock pulse

SDA0, SDA1

is generated.

Setup time of “STOP

condition”

SCL↑→SDA↑

SCL0, SCL1,

t^SUSTO

µs

SDA0, SDA1

SDA data input hold

time (vs. SCL↓)

t^HDDATSDA0, SDA1

t^SUDATSDA0, SDA1

2 × M*¹

⎯

2 × M*¹

⎯

µs

SDA data input setup

time (vs. SCL↑)

250

100*²

ns

*1 : M = resource clock cycle (ns)

*2 : A high-speed mode I²C bus device can be used for a standard mode I²C bus system as long as the device

satisfies a requirement of “t^SUDAT≥ 250 ns”.

When a certain device does not extend the “L” period of the SCL signal, the next data must be output to the

SDA line within 1250 ns (maximum SDA/SCL rise time + t^SUDATA) in which the SCL line is released.

*3 : For use at over 100 kHz, set the resource clock frequency to at least 6 MHz.

*4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines.

117

MB91301 Series

• At slave mode operation

(A^VCC= V^CC= 3.3 0.3 V, A^VSS= V^SS= 0.0 V, Ta = 0 °C to +70 °C)

Typical mode Fast mode*³

Sym-

Parameter

bol

Conditions

Unit

Remarks

Min

0

Max

100

⎯

Min

0

Max

SCL clock frequency

f^SCLSCL0, SCL1

400 kHz

“L” period of SCL clock t^LOWSCL0, SCL1

“H” period of SCL clock t^HIGHSCL0, SCL1

BUS free time between

4.7

4.0

1.3

0.6

⎯

µs

⎯

“STOP condition” and

“START condition”

t^BUSSDA0, SDA1

4.7

⎯

5 × M*¹

⎯

1.3

⎯

µs

SCL↓→SDA output

delay time

SCL0, SCL1,

t^HDDAT

5 × M*¹ns

SDA0, SDA1

Setup time of “repeat

START condition”

SCL↑→SDA↓

SCL0, SCL1,

t^SUSTA

4.7

0.6

⎯

µs

R = 1 kΩ,

SDA0, SDA1

C = 50 pF*⁴

Hold time of “repeat

START condition”

SDA↓→SCL↓

After that, the

SCL0, SCL1,

t^HDSTA

4.0

⎯

0.6

µs first clock pulse

SDA0, SDA1

is generated.

Setup time of “STOP

condition”

SCL↑→SDA↑

SCL0, SCL1,

t^SUSTO

µs

SDA0, SDA1

SDA data input hold

time (vs. SCL↓)

2 ×

t^HDDATSDA0, SDA1

t^HDSTASDA0, SDA1

⎯

µs

M*¹

SDA data input setup

time (vs. SCL↑)

250

100*²

ns

*1 : M = resource clock cycle (ns)

*2 : A high-speed mode I²C bus device can be used for a standard mode I²C bus system as long as the device

satisfies a requirement of “t^SUDAT≥ 250 ns”.

When a certain device does not extend the “L” period of the SCL signal, the next data must be output to the

SDA line within 1250 ns (maximum SDA/SCL rise time + t^SUDATA) in which the SCL line is released.

*3 : For use at over 100 kHz, set the resource clock frequency to at least 6 MHz.

*4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines.

V

OH

OL

SDA

SCL

t

BUS

t

LOW

t

HDSTA

V

OH

V

OL

t

HDSTA

tSUDAT

t

SUSTA

t

SUSTO

t

HIGH

t

HDDAT

f

SCL

118

MB91301 Series

5. Electrical Characteristics for the A/D Converter

(V^CC= AV^CC= 3.0 V to 3.6 V, V^SS= AV^SS= 0 V, AVRH = 3.0 V to 3.6 V , Ta = 0 °C to +70 °C)

Value

Parameter

Symbol Pin name

Unit

Min

⎯

Typ

⎯

Max

10

Resolution

Total error

⎯

BIT

LSB

⎯

−8.5

−3.0

−2.5

−8.0

⎯

+8.5

+3.0

+2.5

+8.0

Linearity error

⎯

Differential linearity error

Zero transition error

Full-scale transition error

⎯

V^OT

V^FST

AN0 to AN3

+0.5

AN0 to AN3 AVRH − 8.0 AVRH − 1.5 AVRH + 8.0

4.1 µs

machine

Conversion time*¹

⎯

clock(CLKP)

34 MHz at

operating

⎯

µs

Analog port input current

Analog input voltage

Reference voltage

I^AIN

V^AIN

⎯

AN0 to AN3

AVRH

⎯

AVss

⎯

0.1

⎯

10

AVRH

AV^CC

2

µA

V

⎯

V

I^A

0.6

⎯

mA

µA

mA

µA

LSB

Power supply current

AV^CC

I^AH*²

⎯

10

I^R

⎯

0.6

⎯

2

Reference voltage supply current

Variation between channels

AVRH

I^RH*²

⎯

10

AN0 to AN3

⎯

5

*1 : For V^CC= AV^CC= 3.0 V to 3.6 V , machine clock = 34 MHz

*2 : Current when A/D converter not operating and CPU in stop mode (V^CC= AV^CC= AVRH = 3.6 V)

Notes : • The relative error increases as AVRH becomes smaller.

• Ensure that the output impedance of the external circuit connected to the analog input meets the following

condition :

^{Output impedance of external circuit}< ^{7 k}Ω

If the output impedance of the external circuit is too high, the analog voltage sampling time may be too

short.

119

MB91301 Series

• About the external impedance of the analog input and its sampling time

• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting

A/D conversion precision.

• Analog input equivalent circuit

R

Comparator

Analog input

C

During sampling : ON

R

C

MB91302A

8.1 kΩ (Max) 10.0 pF (Max)

Note : The values are reference.

• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance

and minimum sampling time and either adjust the resistor value and operating frequency or decrease the

external impedance so that the sampling time is longer than the minimum value.

• The relationship between the external impedance and minimum sampling time

(External impedance = 0 kΩ to 100 kΩ)

(External impedance = 0 kΩ to 20 kΩ)

MB91302A

100

90

80

70

60

50

40

30

20

10

0

20

18

16

14

12

10

8

6

4

2

0

5

10

15

20

25

30

35

0

1

2

3

4

5

6

7

8

Minimum sampling time (µs)

• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

• About errors

As |AVRH − AV^SS| becomes smaller, values of relative errors grow larger.

120

MB91301 Series

6. Power-on ratings

Parameter

Value

Symbol

Unit

Remarks

Min

⎯

Max

38

Power rise time

tr

ms

V

Tilt = 0.05 V / ms

Power start time

Voff

Von

toff

⎯

0.1

⎯

Power end voltage

Power shutdown time

2.0

1

V

⎯

ms

tr

toff

Von

VCC

Voff

121

MB91301 Series

■ PIN STATUS IN EACH CPU STATE

• Terms used in the pin status list

• Input ready

Indicates that the input function can be used.

• Input 0 fixed

Indicates that the input level has been internally fixed to be 0 to prevent leakage when the input is released.

• Output Hi-Z

Indicates to put the pin in a high impedance state with the pin driving transistor disabled for driving.

• Output held

Indicates the output in the output state existing immediately before this mode is established.

If the device enters this mode with an internal output peripheral operating or while serving as an output port,

the output is performed by the internal peripheral or the port output is maintained, respectively.

• Previous state held

When the device serves for output or input immediately before entering this mode, the device maintains the

output or is ready for the input, respectively.

122

MB91301 Series

• Pin Status List (External bus : 32 bit bus width)

At initialization (INIT)

Stop mode

Function

name

Bus released

(BGRNT)

Specified

function

name

Function

name

Port

Sleep

mode

Pin no.

Initial

value

name

HIZ = 0

HIZ = 1

Bus width

32 bit

Bus width

8 bit

CS not

shared

CS shared

1 to 5

P13 to P17

P20 to P27

D11 to D15

D16 to D23

D11 to D15

D16 to D23

P13 to P17

P20 to P27

P : Previous P : Previous

Output

Hi-Z/

input 0

fixed

state held

F : Output

state held

F : Output

Output Hi-Z

Input ready

8 to 15

Output Hi-Z

held or

Hi-Z

held or

Hi-Z

18 to 25 P30 to P37

D24 to D31

RDY

D24 to D31

P80

D24 to D31

P80

P : Previous

state held

F : RDY input

P : Previous P : Previous

state held state held

F : RDY input F : RDY input

28

29

P80

P81

P : Previous

state held Previous

F : H output state held

BGRNT

P81

Output Hi-Z

Input ready

L output

P : Previous

state held

F:BRQinput

invalid

Output

Hi-Z/

input 0

fixed

30

P82

BRQ

RD

P82

RD

P82

RD

BRQ input

31

32

33

34

35

P83

P84

P85

P86

P87

H output

DQMUU/WR0 DQMUU/WR0 DQMUU/WR0

P : Previous

state held

DQMUL/WR1 DQMUL/WR1

DQMLU/WR2 DQMLU/WR2

DQMLL/WR3 DQMLL/WR3

P85

P86

P87

state held

F : H output

Output Hi-Z

F : H output

Asserted

: L output

Negated

P : Previous P : Previous Output

state held state held Hi-Z/

F : SYSCLK F : H or L out- input 0

F : CLK

output

F : CLK

output

36

37

38

P90

P91

P92

SYSCLK

MCLKE

MCLK

⎯

SYSCLK

MCLKE

MCLK

SYSCLK

MCLKE

MCLK

: CLK output

output

put

fixed

F:Output

Hi-Z

H output

F : L output

Output Hi-Z

H output

Asserted

: L output

Negated

P : Previous P : Previous

state held state held

F : H output F : H output

F:Output

Hi-Z

F : CLK

output

: CLK output

Output Hi-Z Previous

Input ready

Output

Hi-Z

Port

Function

Port

Function

39

40

P93

P94

P93

P94

P93

P94

state held

P : Previous

state held H output

F : H output

SRAS/LBA/

AS

Output Hi-Z

Input ready

Output

Hi-Z

Output Hi-Z

F : H output

H output

P : Previous

state held H output

F : H output

Output Hi-Z

Input ready

Output

Hi-Z

41

42

P95

P96

SCAS/BAA

SWE/WR

P95

P96

P95

P96

P : Previous

Output

Hi-Z/

Output Hi-Z

Input ready

state held Previous

Output Hi-Z

F : SWE

output

state held

input 0

fixed

45 to 52 P40 to P47

55 to 62 P50 to P57

64 to 67 P60 to P63

A00 to A07

A08 to A15

A16 to A19

A20/SDA0

A21/SCL0

A22/SDA1

A23/SCL1

A00 to A07

A08 to A15

A16 to A19

A20

A00 to A07

A08 to A15

A16 to A19

A20

P : Previous

state held The same as Hi-Z/

F : Address

Output

68

69

70

71

P64

P65

P66

P67

FF output

Output Hi-Z

stated left

input 0

fixed

output

A21

A22

A23

input

invalid

76 to 79

⎯

AN3 to AN0

AN3 to AN0 input invalid

PG0

input invalid

81

82

83

84

PG0

PG1

PG2

PG3

INT0/ICU0

INT1/ICU1

INT2/ICU2

INT3/ICU3

PG0

PG1

PG2

PG3

P : Previous P : Previous P:Output

PG1

Output Hi-Z

state held

F : Normal

operation

state held

F : Input

ready

Hi-Z

F : Input

ready

Normal

operation

Normal

operation

Input ready

PG2

PG3

(Continued)

123

MB91301 Series

(Continued)

At initialization (INIT)

Function

Stop mode

Function

Bus released

(BGRNT)

Specified

function

name

Port

name

Sleep

mode

Pin no.

name

Initial

HIZ = 0

HIZ = 1

value

Bus width

32 bit

Bus width

CS

CS not

shared

8 bit

shared

INT4/ATG/

FRCK

85

PG4

P : Previous P : Previous P : Output

Output Hi-Z

Input ready

state held

F : Normal

state held

F : Input

ready

Hi-Z

F : Input

ready

Normal

operation

Normal

operation

86

87

PG5

PG6

PG7

PJ0

PJ1

PJ2

PJ3

PJ4

PJ5

PJ6

PJ7

PH0

PH1

PH2

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

INT5/SIN2

INT6/SOT2

INT7/SCK2

SIN0

PG5

PG6

PG7

PJ0

PG5

PG6

PG7

PJ0

operation

88

90

91

SOT0

PJ1

92

SCK0

PJ2

P : Previous

state held Previous

F : Normal state held

Output Hi-

Z/input 0

fixed

93

SIN1

PJ3

Output Hi-Z

Input ready

Normal

operation

Normal

operation

94

SOT1

PJ4

operation

95

SCK1

PJ5

96

PPG0

PJ6

97

TRG0

PJ7

98

TIN0

PH0

PH1

PH2

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

CS0

CS1

CS2

CS3

CS4

CS5

CS6

CS7

D00 to D07

PH0

PH1

PH2

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

CS0

CS1

CS2

CS3

CS4

CS5

CS6

CS7

P00 to P07

P : Previous

state held Previous

F : Normal state held

Output Hi-

Z/input 0

fixed

Output Hi-Z

Input ready

Normal

operation

Normal

operation

99

TIN1/PPG3

TIN2/TRG3

DREQ0

DACK0

DEOP0

DREQ1

DACK1/TRG1

DEOP1/PPG1

IOWR

operation

100

103

104

105

106

107

108

109

110

122

123

124

125

126

127

128

129

P : Previous

Output Hi-

Z/input 0

fixed

Output Hi-Z

Input ready

state held Previous

F : Normal state held

operation

Normal

operation

Normal

operation

IORD

CS0

CS1

CS2

F : SREN = F : SREN =

0 : H

CS3

Output

Hi-Z

output,

SREN=

1 : Out-

put Hi-Z

output,

SREN =

1 : Out-

put Hi-Z

H output

CS4/TRG2

CS5/PPG2

CS6

CS7

132 to 139 P00 to P07

D00 to D07

P : Previous P : Previous

state held state held Output Hi-

F : Output

Output Hi-Z

Input ready

F : Output

held or

Hi-Z

Z/input 0

fixed

Output Hi-Z Output Hi-Z

142 to 144 P10 to P12

D08 to D10

P10 to P12

held or

Hi-Z

P : General-purpose port selected, F : Specified function selected

Notes : • The bus width is determined after a mode vector fetch.

• The bus width at initialization time is 8 bits.

124

MB91301 Series

• Pin Status List (External bus : 16 bit bus width)

At initialization (INIT)

Stop mode

Function

name

Bus released

(BGRNT)

Specified

function

name

Function

name

Port

Sleep

mode

Pin no.

Initial

value

name

HIZ = 0

HIZ = 1

Bus width

16 bit

Bus width

8 bit

CS

shared

CS not

shared

1 to 5

P13 to P17

P20 to P27

D11 to D15

D16 to D23

P13 to P17

D16 to D23

P13 to P17

P20 to P27

P : Previous

state

P : Previous

state held Output Hi-

F : Output

held or

Hi-Z

8 to 15

Output Hi-Z

Input ready

held

Z/input 0

fixed

Output Hi-Z Output Hi-Z

F : Output

held or

Hi-Z

18 to 25 P30 to P37

D24 to D31

P : Previ-

ous

state

held

F : RDY

input

P : Previ-

ous

state

held

F : RDY

input

P : Previous

state held

F : RDY input

28

P80

RDY

P80

Output Hi-Z P : Previous Previous

29

30

P81

P82

BGRNT

P81

Input ready

state held state held

F : H output

L output

Output Hi-

Z/input 0

fixed

P : Previous

state held

F : BRQ

input in-

valid

BRQ

RD

P82

RD

P82

RD

BRQ input BRQ input

Output Hi-Z Output Hi-Z

31

32

33

34

35

P83

P84

P85

P86

P87

H output

DQMUU/WR0 DQMUU/WR0 DQMUU/WR0

P : Previous

state held

F : H output

DQMUL/WR1 DQMUL/WR1

P85

P86

P87

DQMLU/WR2

DQMLL/WR3

P86

P87

F : H output

Asserted

: L output

Negated

P : Previous P : Previous

state held state held

F : SYSCLK F : H or L

Output Hi-

Z/input 0

fixed

F : CLK

output

F : CLK

output

36

37

38

P90

P91

P92

SYSCLK

MCLKE

MCLK

⎯

SYSCLK

MCLKE

MCLK

SYSCLK

MCLKE

MCLK

: CLK output

output

F : Output

Hi-Z

H output

F : L output

Output Hi-Z H output

Asserted

: L output

Negated

P : Previous P : Previous

state held state held

F : H output F : H output

F : Output

Hi-Z

F : CLK

Output Hi-Z

output

: CLK output

Output Hi-Z Previous

Input ready

39

40

P93

P94

P93

P94

P93

P94

Output Hi-Z Output Hi-Z

state held

P : Previous

state held H output

F : H output

SRAS/LBA/

AS

Output Hi-Z

Input ready

Output Hi-Z Output Hi-Z F : H output

Output Hi-Z Output Hi-Z H output

P : Previous

state held H output

F : H output

Output Hi-Z

Input ready

41

42

P95

P96

SCAS/BAA

SWE/WR

P95

P96

P95

P96

P : Previous

state held Previous

F : SWE out- state held

put

Output Hi-

Input ready

Z/input 0

fixed

Output Hi-Z

state held

45 to 52 P40 to P47

55 to 62 P50 to P57

64 to 67 P60 to P63

A00 to A07

A08 to A15

A16 to A19

A20/SDA0

A21/SCL0

A22/SDA1

A23/SCL1

A00 to A07

A08 to A15

A16 to A19

A20

A00 to A07

A08 to A15

A16 to A19

A20

P : Previous

state

Output Hi-

Z/input 0

fixed

The same as

held

68

69

70

71

P64

P65

P66

P67

FF output

Output Hi-Z Output Hi-Z

stated left

F : Address

A21

output

A22

A23

76 to 79

⎯

AN3 to AN0

AN3 to AN0 input invalid

input invalid input invalid

(Continued)

125

MB91301 Series

(Continued)

At initialization (INIT)

Function

Stop mode

Function

Bus released

(BGRNT)

Specified

function

name

Port

name

Sleep

mode

Pin no.

name

Initial

HIZ = 0

HIZ = 1

value

Bus width

16 bit

Bus width

CS

CS not

shared

8 bit

shared

P : Previous P : Previous P : Output

Output Hi-Z

PG0

state held

F : Normal

operation

state held

F : Input

ready

Hi-Z

F : Input

ready

Normal

operation

Normal

operation

81

PG0

INT0/ICU0

PG0

Input ready

82

83

84

PG1

PG2

PG3

INT1/ICU1

INT2/ICU2

INT3/ICU3

PG1

PG2

PG3

PG1

PG2

PG3

P : Previous P : Previous P : Output

INT4/ATG/

FRCK

Output Hi-Z

PG4

state held

F : Normal

operation

state held

F : Input

ready

Hi-Z

F : Input

ready

Normal

operation

Normal

operation

85

PG4

Input ready

86

87

PG5

PG6

PG7

PJ0

PJ1

PJ2

PJ3

PJ4

PJ5

PJ6

PJ7

PH0

PH1

PH2

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

INT5/SIN2

INT6/SOT2

INT7/SCK2

SIN0

PG5

PG6

PG7

PJ0

PG5

PG6

PG7

PJ0

PJ1

PJ2

88

90

91

SOT0

PJ1

92

SCK0

PJ2

P : Previous

state held Previous

F : Normal state held

Output

Hi-Z/input0

fixed

93

SIN1

PJ3

Output Hi-Z

Normal

operation

Normal

operation

Input ready

94

SOT1

PJ4

operation

95

SCK1

PJ5

PJ6

PJ7

PH0

96

PPG0

PJ6

97

TRG0

PJ7

98

TIN0

PH0

PH1

PH2

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

CS0

CS1

CS2

CS3

CS4

CS5

CS6

CS7

P00 to P07

P : Previous

state held Previous

F : Normal state held

Output

Hi-Z/input0

fixed

Output Hi-Z

Input ready

Normal

operation

Normal

operation

99

TIN1/PPG3

TIN2/TRG3

DREQ0

DACK0

DEOP0

DREQ1

DACK1/TRG1

DEOP1/PPG1

IOWR

PH1

operation

100

103

104

105

106

107

108

109

110

122

123

124

125

126

127

128

129

PH2

PB0

PB1

PB2

P : Previous

Output

Hi-Z/input0

fixed

PB3

Output Hi-Z

state held Previous

F : Normal state held

operation

Normal

operation

Normal

operation

Input ready

PB4

PB5

PB6

PB7

CS0

CS1

CS2

IORD

CS0

CS1

F : SREN = F : SREN =

CS2

0 : H

CS3

output,

SREN=

1 : Out-

put Hi-Z

output,

SREN =

1 : Out-

put Hi-Z

H output

CS4

H output

Output Hi-Z

CS4/TRG2

CS5/PPG2

CS6

CS5

CS6

CS7

132 to 139 P00 to P07

D00 to D07

P00 to P07

Output Hi-Z

P : Previous P : Previous

state held state held Output

F : Output

held or

Hi-Z

Hi-Z/input0 Output Hi-Z Output Hi-Z

fixed

Input ready

142 to 144 P10 to P12

D08 to D10

P10 to P12

held or

Hi-Z

P : General-purpose port selected, F : Specified function selected

Notes : • The bus width is determined after a mode vector fetch.

• The bus width at initialization time is 8 bits.

126

MB91301 Series

• Pin Status List (External bus : 8 bit bus width)

At initialization (INIT)

Stop mode

Function

name

Bus released

(BGRNT)

Specified

function

name

Function

name

Port

Pin no.

Sleep mode

Initial

value

name

HIZ = 0

HIZ = 1

Bus width

8 bit

Bus width

8 bit

CS

shared

CS not

shared

1 to 5

P13 to P17 D11 to D15

P20 to P27 D16 to D23

P13 to P17

P20 to P27

P13 to P17

P20 to P27

P : Previous

state held

F : Output held

or Hi-Z

state held Output

Output Hi-Z

Input ready

8 to 15

F : Output

held or

Hi-Z

Hi-Z/input Output Hi-Z Output Hi-Z

0 fixed

18 to 25 P30 to P37 D24 to D31

D24 to D31

P : Previous P : Previous

P : Previous

state held

F : RDY input

state

held

F : RDY

input

state

held

F : RDY

input

28

29

30

P80

P81

P82

RDY

P80

P : Previous

state held

F : H output

Output Hi-Z

Input ready

BGRNT

P81

L output

P : Previous

state held

F : BRQ

input in-

valid

Output

Hi-Z/input

0 fixed

BRQ

RD

P82

RD

P82

RD

BRQ input BRQ input

Output Hi-Z Output Hi-Z

31

32

33

34

35

P83

P84

P85

P86

P87

H output

DQMUU/WR0 DQMUU/WR0 DQMUU/WR0

P : Previous

state held

F : H output

DQMUL/WR1

DQMLU/WR2

DQMLL/WR3

P85

P86

P87

P85

P86

P87

F : H output

Asserted

: L output

Negated

P : Previous

state held

F : SYSCLK

output

P : Previous

state held

F : H or L

output

Output

Hi-Z/input

0 fixed

F : CLK

output

F : CLK

output

36

37

38

P90

P91

P92

SYSCLK

MCLKE

MCLK

SYSCLK

MCLKE

MCLK

SYSCLK

MCLKE

MCLK

: CLK output

F : Output

Hi-Z

H output

F : L output

Output Hi-Z H output

Asserted

: L output

Negated

P : Previous

state held

F : H output

P : Previous

state held

F : H output

F : Output

Hi-Z

F : CLK

Output Hi-Z

output

: CLK output

Output Hi-Z

Input ready

Previous state Previous

39

40

P93

P94

⎯

P93

P94

P93

P94

Output Hi-Z Output Hi-Z

Output Hi-Z F : H output

held

state held

P : Previous

state held H output

F : H output

Output Hi-Z

Input ready

Output

Hi-Z

SRAS/LBA/AS

P : Previous

state held H output

F : H output

Output Hi-Z

Input ready

Output

Hi-Z

41

42

P95

P96

SCAS/BAA

SWE/WR

P95

P96

P95

P96

Output Hi-Z H output

state held

F : SWE output

Output

Hi-Z/input Output Hi-Z

0 fixed

Output Hi-Z

Input ready

state held

45 to 52 P40 to P47

55 to 62 P50 to P57

64 to 67 P60 to P63

A00 to A07

A08 to A15

A16 to A19

A20/SDA0

A21/SCL0

A22/SDA1

A23/SCL1

A00 to A07

A08 to A15

A16 to A19

A20

A00 to A07

A08 to A15

A16 to A19

A20

P : Previous

state held The same as

F : Address

Output

68

69

70

71

P64

P65

P66

P67

FF output

Hi-Z/input Output Hi-Z Output Hi-Z

0 fixed

stated left

output

A21

A22

A23

Previous state

held

input

invalid

76 to 79

⎯

AN3 to AN0

AN3 to AN0 input invalid

input invalid

P : Previous

state held

F : Normal op- F : Input

eration ready

P : Previous P : Output

Output Hi-Z

PG0

state held

Hi-Z

F : Input

ready

Normal

operation

Normal

operation

81

PG0

INT0/ICU0

PG0

Input ready

(Continued)

127

MB91301 Series

(Continued)

At initialization (INIT)

Function

Stop mode

Function

Bus released

(BGRNT)

Specified

function

name

Port

Sleep

mode

Pin no.

name

Initial

name

HIZ = 0

HIZ = 1

value

Bus width

8 bit

Bus width

CS

CS not

shared

8 bit

PG1

PG2

PG3

shared

82

83

84

PG1

PG2

PG3

INT1/ICU1

INT2/ICU2

INT3/ICU3

PG1

PG2

PG3

P : Previous P : Previous P : Output

INT4/ATG/

FRCK

Output Hi-Z

PG4

state held

F : Normal

state held

F : Input

ready

Hi-Z

F : Input

ready

Normal

operation

Normal

operation

85

PG4

Input ready

operation

86

87

PG5

PG6

PG7

PJ0

PJ1

PJ2

PJ3

PJ4

PJ5

PJ6

PJ7

PH0

PH1

PH2

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

INT5/SIN2

INT6/SOT2

INT7/SCK2

SIN0

PG5

PG6

PG7

PJ0

PG5

PG6

PG7

PJ0

PJ1

PJ2

88

90

91

SOT0

PJ1

92

SCK0

PJ2

P : Previous

state held Previous

F : Normal state held

Output

Hi-Z/input 0

fixed

93

SIN1

PJ3

Output Hi-Z

Normal

operation

Normal

operation

Input ready

94

SOT1

PJ4

operation

95

SCK1

PJ5

PJ6

PJ7

PH0

96

PPG0

PJ6

97

TRG0

PJ7

98

TIN0

PH0

PH1

PH2

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

CS0

CS1

CS2

CS3

CS4

CS5

CS6

CS7

P00 to P07

P : Previous

state held Previous

F : Normal state held

Output

Hi-Z/input 0

fixed

Output Hi-Z

Input ready

Normal

operation

Normal

operation

99

TIN1/PPG3

TIN2/TRG3

DREQ0

DACK0

DEOP0

DREQ1

DACK1/TRG1

DEOP1/PPG1

IOWR

PH1

operation

100

103

104

105

106

107

108

109

110

122

123

124

125

126

127

128

129

PH2

PB0

PB1

PB2

P : Previous

Output

Hi-Z/input 0

fixed

PB3

Output Hi-Z

state held Previous

F : Normal state held

operation

Normal

operation

Normal

operation

Input ready

PB4

PB5

PB6

PB7

CS0

CS1

CS2

IORD

CS0

CS1

CS2

F : SREN = F : SREN =

0 : H

CS3

output,

SREN =

1 : Out-

put Hi-Z

output,

SREN =

1 : Out-

put Hi-Z

H output

CS4

H output

Output Hi-Z

CS4/TRG2

CS5/PPG2

CS6

CS5

CS6

CS7

132 to 139 P00 to P07 D00 to D07

P00 to P07

Output Hi-Z

P : Previous P : Previous

state held state held Output

F : Output

held or

Hi-Z

Hi-Z/input 0 Output Hi-Z Output Hi-Z

fixed

Input ready

142 to 144 P10 to P12 D08 to D10

P10 to P12

held or

Hi-Z

P : General-purpose port selected, F : Specified function selected

Notes : • The bus width is determined after a mode vector fetch.

• The bus width at initialization time is 8 bits.

128

MB91301 Series

• Pin Status List (Single chip mode)

At initialization (INIT)

Stop mode

Function name

Initial value

Specified func-

tion name

Pin no.

Port name

Sleep mode

Internal ROM

mode vector

(MD2-0 = 000)

HIZ = 1

^HIZ= ⁰

Bus width

8 bit

1 to 5

8 to 15

18 to 25

28

P13 to P17

P20 to P27

P30 to P37

P80

⎯

P13 to P17

P20 to P27

P30 to P37

P80

Previous state

held

Previous state

held

⎯

Output Hi-Z

29

P81

⎯

P81

30

P82

⎯

P82

31

P83

⎯

P83

32

P84

⎯

P84

33

P85

⎯

P85

34

P86

⎯

P86

Previous state

held

Previous state

held

35

P87

⎯

P87

36

P90

⎯

P90

Output Hi-Z/

Input ready

Output Hi-Z/

input 0 fixed

37

P91

⎯

P91

38

P92

⎯

P92

39

P93

⎯

P93

40

P94

SRAS

SCAS/BAA

SWE/WR

⎯

P94

41

P95

42

P96

45 to 52

55 to 62

64 to 67

68

P40 to P47

P50 to P57

P60 to P63

P64

P40 to P47

P50 to P57

P60 to P63

P64

Output Hi-Z

⎯

SDA0

SCL0

SDA1

SCL1

AN0 to AN3

INT0/ICU0

INT1/ICU1

INT2/ICU2

INT3/ICU3

INT4/ATG/FRCK

INT5/SIN2

INT6/SOT2

INT7/SCK2

SIN0

Previous state

held

69

P65

70

P66

71

P67

76 to 79

81

⎯

AN0 to AN3

PG0

Input invalid

input invalid

PG0

82

PG1

83

PG2

84

PG3

Previous state

held

P : Output Hi-Z

F : Input ready

85

PG4

86

PG5

P: Previous state

held

F : Input ready

PG6

Output Hi-Z/

Input ready

88

PG7

state held

90

PJ0

91

PJ1

SOT0

SCK0

SIN1

PJ1

92

PJ2

Output Hi-Z/

input 0 fixed

93

PJ3

94

PJ4

SOT1

SCK1

PJ4

95

PJ5

(Continued)

129

MB91301 Series

(Continued)

At initialization (INIT)

Stop mode

Function name

Initial value

Specified func-

tion name

Pin no.

Port name

Sleep mode

Internal ROM

mode vector

(MD2-0 = 000)

HIZ = 1

^HIZ= ⁰

Bus width

8 bit

96

97

PJ6

PJ7

PPG0

PJ6

PJ7

TRG0

98

PH0

TIN0

PH0

99

PH1

TIN1/PPG3

PH1

100

PH2

TIN2/TRG3

PH2

103

PB0

⎯

PB0

104

PB1

105

PB2

⎯

PB2

106

PB3

⎯

PB3

107

PB4

TRG1

PPG1

⎯

PB4

108

PB5

Output Hi-Z/

Input ready

Previous state

held

Previous state

held

Output Hi-Z/

input 0 fixed

109

PB6

110

PB7

⎯

PB7

122

PA0

⎯

PA0

123

PA1

⎯

PA1

124

PA2

⎯

PA2

125

PA3

⎯

PA3

126

PA4

TRG2

PPG2

⎯

PA4

127

PA5

128

PA6

129

PA7

⎯

PA7

132 to 139

142 to 144

P00 to P07

P10 to P12

⎯

P00 to P07

P10 to P12

⎯

P : General-purpose port selected, F : Specified function selected

Notes : • The bus width is determined after a mode vector fetch.

• The bus width at initialization time is 8 bits.

130

MB91301 Series

■ EXAMPLE CHARACTERISTICS

I^CC− Internal frequency (PLL On)

External V^CC= 3.6 V, Ta = + 25 °C

I^CC− External V^CC(PLL On)

Internal frequency = 68 MHz, Ta = + 25 °C

140

120

100

80

120

100

80

60

40

20

0

I^CC

ICCS

I^CC

ICCS

60

40

20

0

2.7

3

3.3

3.6

3.9

0

10 20 30 40 50 60 70 80

Internal frequency [MHz]

External V^CC[V]

V^OL− External V^CC

Internal frequency = 68 MHz, Ta = + 25 °C

V^OH− External V^CC

Internal frequency = 68 MHz, Ta = + 25 °C

0.8

4

3

2

1

0

0.6

0.4

0.2

0

2.7

3

3.3

3.6

3.9

2.7

3

3.3

3.6

3.9

External V^CC[V]

I^IL− External V^CC

Internal frequency = 68 MHz, Ta = + 25 °C

0

100

200

300

400

2.7

3

3.3

3.6

3.9

External V^CC[V]

131

MB91301 Series

■ ORDERING IMFORMATION

Part No.

Package

Remarks

MB91302APFF-G-001-BNDE1

MB91302APFF-G-010-BNDE1

Without ROM

Optional real time OS internal model

144-pin Plastic LQFP

(FPT-144P-M12)

Built-in IPL (Internal Program Loader)

version

MB91302APFF-G-020-BNDE1

MB91302APFF-G-XXX-BNDE1

User ROM version

Development pack for MB91302A real

time OS internal model (MB91V301A

and CD-ROM for development)

179-pin Ceramic PGA

(PGA-179C-A03)

MB91V301A-RDK01*

MB91V301A

179-pin Ceramic PGA

(PGA-179C-A03)

Evaluation chip

* : In case of buying this product, it is necessary to make a contract with “MB91V301A-RDK01 Fujitsu software

product use contract”.

132

MB91301 Series

■ PACKAGE DIMENSIONS

Note 1) * : These dimensions include resin protrusion.

144-pin Plastic LQFP

(FPT-144P-M12)

Resin protrusion is +0.25 (.010) Max (each side) .

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

18.00±0.20(.709±.008)SQ

+0.40

16.00^–^0.10.630 ⁺–^.^.⁰⁰⁰¹⁴⁶SQ

*

73

108

72

109

0.08(.003)

Details of "A" part

1.50 –⁺0⁰.^.210⁰

.059 –⁺.^.0⁰⁰04⁸

(Mounting height)

INDEX

0~8˚

37

144

"A"

0.10±0.05

(.004±.002)

0.60±0.15

1

LEAD No.

36

(Stand off)

(.024±.006)

0.25(.010)

0.145 ⁺–0⁰.^.0⁰3⁵

.006 –⁺.^.0⁰0⁰1²

0.40(.016)

0.18±0.035

.007±.001

M

0.07(.003)

C

2003 FUJITSU LIMITED F144024S-c-3-3

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

(Continued)

133

MB91301 Series

(Continued)

179-pin Ceramic PGA

(PGA-179C-A03)

2.54±0.25

1.27(.050)TYP DIA

(.100±.010)

35.56(1.400)

REF

INDEX

INDEX AREA

0.46 ⁺–0⁰.^.0¹5⁸DIA

.018 ⁺^–.^.⁰⁰⁰⁰²⁷

38.10±0.51 SQ

(1.500±.020)

1.27±0.25

(.050±.010)

6.10(.240)

MAX

3.40 –⁺0⁰.^.3⁴6¹

.134 ⁺^–.^.⁰⁰¹¹⁴⁶

C

1994 FUJITSU LIMITED R179004SC-3-2

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

134

MB91301 Series

The information for microcontroller supports is shown in the following homepage.

http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0512


型号：	MB91302APFF-G-020-BNDE1
厂家：	FUJI ELECTRIC
描述：	32-Bit Proprietary Microcontroller 32位微控制器专用微控制器外围集成电路 ISM频段时钟
文件：	总135页 (文件大小：1391K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB91302APFF-G-020-BNDE1 [FUJI]

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