GPC12A-NnnV-C [GENERALPLUS]
12KB Sound Controller (OTP);
| 型号： | GPC12A-NnnV-C |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 12KB Sound Controller (OTP) |
| 文件： | 总16页 (文件大小：355K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPC12A
12KB Sound Controller (OTP)
MAR. 23, 2006
Version 1.0
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPC12A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3
2. BLOCK DIAGRAM ...................................................................................................................................................................................... 3
3. FEATURES.................................................................................................................................................................................................. 3
4. APPLICATION FIELD.................................................................................................................................................................................. 3
5. SIGNAL DESCRIPTIONS* .......................................................................................................................................................................... 4
5.1. PIN MAP ............................................................................................................................................................................................... 5
6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 6
6.1. CPU ..................................................................................................................................................................................................... 6
6.2. OTP EPROM AREA .............................................................................................................................................................................. 6
6.3. RAM AREA............................................................................................................................................................................................ 6
6.4. MAP OF MEMORY AND I/OS .................................................................................................................................................................... 6
6.5. I/O PORT CONFIGURATION*.................................................................................................................................................................... 6
6.6. POWER SAVING MODE ........................................................................................................................................................................... 6
6.7. LOW VOLTAGE RESET ............................................................................................................................................................................ 7
6.8. TIMER/COUNTER ................................................................................................................................................................................... 7
6.9. SPEECH AND MELODY............................................................................................................................................................................ 8
6.10.SERIAL INTERFACE TIMING...................................................................................................................................................................... 8
6.11.WATCHDOG ENABLE/DISABLE ................................................................................................................................................................. 8
6.12.IDENTIFY CODE AND SECURITY OPTION ................................................................................................................................................... 8
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................... 9
7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................... 9
7.2. AC CHARACTERISTICS (TA = 25℃)......................................................................................................................................................... 9
7.3. DC CHARACTERISTICS (VDD = 3.0V, TA = 25°C).................................................................................................................................... 9
7.4. DC CHARACTERISTICS (VDD = 5.0V, TA = 25°C).................................................................................................................................... 9
7.5. THE RELATIONSHIP BETWEEN ROSC AND FCPU .........................................................................................................................................11
7.5.1. VDD = 3.0V..............................................................................................................................................................................11
7.5.2. VDD = 5.0V..............................................................................................................................................................................11
7.6. THE RELATIONSHIP BETWEEN IOP AND FCPU ............................................................................................................................................11
7.7. THE RELATIONSHIP BETWEEN FCPU AND VDD.........................................................................................................................................11
8. APPLICATION CIRCUIT ........................................................................................................................................................................... 12
9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 13
9.1. PAD ASSIGNMENT ............................................................................................................................................................................... 13
9.2. ORDERING INFORMATION ..................................................................................................................................................................... 13
9.3. PACKAGE INFORMATION ....................................................................................................................................................................... 14
10.DISCLAIMER............................................................................................................................................................................................. 15
11. REVISION HISTORY ................................................................................................................................................................................. 16
© Generalplus Technology Inc.
Proprietary & Confidential
2
MAR. 23, 2006
Version: 1.0
GPC12A
12KB SOUND CONTROLLER (OTP)
1. GENERAL DESCRIPTION
3. FEATURES
The GPC12A, a two-channel speech/melody synthesizer, equips
an 8-bit CMOS microprocessor with 69 instructions, 12K-byte
OTP-EPROM for speech and melody data (speech compressed
by a 4-bit ADPCM with approx. three seconds speech duration @
6.0KHz sampling rate), 64-byte working SRAM Other primary
features include two Timer/Counters, 8 Software Selectable I/Os,
and one 8-bit current D/A output. In audio processing, melody
and speech can be mixed into one output. It operates at a wide
voltage range of 2.4V - 5.5V with a Low Voltage Reset function
that automatically resets CPU when operating voltage is less than
2.2V. Plus, a Clock Stop mode is built in for power savings. The
unique power saving mode saves the RAM contents, but freezes
the oscillator to stop executing other functions. The maximum
CPU frequency can run up to 6.0MHz and the instruction cycle is
two clock cycles (min.) ~ six clock cycles (max.). The GPC12A
loads, not only the latest technology, but also the full commitment
and technical support of Generalplus.
8-bit microprocessor
12K-byte OTP-EPROM for program and audio data
64-byte working SRAM
Software-based audio processing
Wide operating voltage: 2.4V - 5.5V @ 4.0MHz
3.6V - 5.5V @ 6.0MHz
Supports ROSC only
Max. CPU clock: 4.0MHz @ 3.0V, 6.0MHz @ 5.0V
Standby mode (Clock Stop mode) for power savings.
Max. 8.0µA @ 5.0V
500ns instruction cycle time @ 4.0MHz CPU clock
Eight general I/Os
Two 12-bit timer/counters
Six INT sources
Key wake -up function
Approx. 3-sec speech @ 6.0KHz sampling rate with ADPCM
One D/A output
Low Voltage Reset
2. BLOCK DIAGRAM
4. APPLICATION FIELD
SCLK
SDIO
serial
interface
Intelligent education toys
Ex. Pattern to voice (animal, car, color, etc.)
Spelling (English or Chinese)
Math
12K-byte
Two Timers
TimeBase
INT control
OTP-EPROM
8-bit
microprocessor
64-byte
SRAM
Advanced toy controller
General speech synthesizer
Industrial controller
Two
8-bit D/A
(current)
AUD
Low
Voltage
Reset
CLK
ROSC
OSC
8
PINS
GENERAL
I/O
PORT
IOD7-6,IOD1-0
(I/O)
IOC7-6,IOC2-1
(I/O)
© Generalplus Technology Inc.
Proprietary & Confidential
3
MAR. 23, 2006
Version: 1.0
GPC12A
5. SIGNAL DESCRIPTIONS*
PIN No.
Mnemonic
Type
Description
Chip
Package
SCLK
SDIO
IOD0
IOD1
IOD6
IOD7
1
2
3
4
5
6
24
1
I
Clock input of serial interface
Data of serial interface.
I/O
I/O
I/O
I/O
I/O
2
PortD is a 4-bit bi-directional programmable Input/Output port with Pull-low or
3
Open-drain option. In input mode, PortD can be either Pure or Pull-low states.
4
In output mode, PortD can be either Buffer or Open-drain PMOS type (source
5
current).
(Key change, Wake up I/O)
**See note 1 and 2 below.
IOC7
IOC6
IOC2
IOC1
7
8
6
7
8
9
I/O
I/O
I/O
I/O
PortC is a 4-bit bi-directional programmable Input/Output port with Pull-high or
Open-drain option. In input mode, PortC can be in either Pure or Pull-high
9
states. In output mode, IOC2, IOC1 can be a Buffer or Open-drain NMOS type
10
(sink current).
IOC7, IOC6 can be a Buffer or Open-drain PMOS type (source current).
IOC1: EXT INT IN
IOC2: EXT COUNT IN
**See note 1 and 2 below.
VDD
11
12
13
14
15
10
11
12
13
14
I
I
I
I
I
Power input
VSS
Ground
ROSC
TEST
RESET
ROSC Resistor input (Resistor must be connected to VDD)
Test pin, NC
This pin is an active low reset to the chip
AUD
VPP
VDDT
VDD
VSS
NC
16
17
15
16
O
I
Audio output
High voltage input for EPROM use
18
17
I
Power input for EPROM use
19
18
I
Power input
Ground
20
19
I
21 - 27
28
22 - 23
20
NC
VDD
VSS
I
I
Power input
Ground
29
21
* Refer to GPC Programming Guide for more information.
**Note: 1.) Two input states can be specified: Pure Input, Pull-High or Pull Low.
2.) Three output states can be specified: Buffer output, Open Drain PMOS output (send), or Open Drain NMOS output (sink).
© Generalplus Technology Inc.
Proprietary & Confidential
4
MAR. 23, 2006
Version: 1.0
GPC12A
5.1. PIN Map
GPC12A SOP - 24#
© Generalplus Technology Inc.
Proprietary & Confidential
5
MAR. 23, 2006
Version: 1.0
GPC12A
6. FUNCTIONAL DESCRIPTIONS
6.1. CPU
In p u t/O u tp u t IO C p o rt : IO C 2 - IO C 1
The microprocessor in GPC12A is a high performance 8-bit
processor equipped Accumulator, Program Counter, X Register,
Stack pointer and Processor Status Register (the same as the
6502 instruction structure). The maximum CPU speed of 6.0MHz
is capable of bringing you the cleaner speech, pleasant music as
well as achieving the best performance.
V
D D
lo g ic _ 2
c o n tro l
9 0 K
o u tp u t
d a ta
b u ffe r o r
O D -N M O S
in p u t d a ta
O D : O p e n D ra in
6.2. OTP EPROM Area
The OTP EPROM area in GPC12A is 12K-byte that can be used
for program as well as data.
In p u t/O u tp u t IO D p o rt : IO D 7 - IO D 6
6.3. RAM Area
in p u t d a ta
The total RAM size is 64-bytes (including Stack) starting from
address $C0 through $FF.
O D -P M O S
o r b u ffe r
o u tp u t
d a ta
6.4. Map of Memory and I/Os
6 0 K
lo g ic _ 4
c o n tro l
*I/O PORT:
*MEMORY MAP (From ROM view)
- PORT IOC $0004
$0000
Hardware register, I/Os
IOD $0005
O D : O p e n D ra in
- I/O CONFIG $0000
$00C0
USER RAM and STACK
$0001
*NMI SOURCE:
$0100
In p u t/O u tp u t IO D p o rt : IO D 1 - IO D 0
UNUSED
- INTA (from TIMER A)
$0400
in p u t d a ta
*INT SOURCE:
Reserved
- INTA (from TIMER A)
- INTB (from TIMER B)
O D -P M O S
o r b u ffe r
$0600
o u tp u t
d a ta
USER'S PROGRAM &
DATA AREA
- CPU CLK / 1024
- CPU CLK / 8192
$2FFF
DUMMY AREA
6 0 K
lo g ic _ 4
c o n tro l
- CPU CLK / 65536
- EXT INT
$7C00
USER'S PROGRAM &
DATA AREA
O D : O p e n D ra in
$7FFF
Note: * Values are for VDD = 5.0V test conditions only.
Note1: $05F0 (bit0): watchdog timer ON/OFF.
Note2: $05F6, $05F7: EPROM checksum.
Note3: $05F8 (bit7): Security bit
6.6. Power Saving Mode
The GPC12A includes a power saving mode (Standby mode) for
those applications that require very low standby current. To enter
standby mode, the Wake-Up Register must be enabled and then
stop the CPU clock by writing the STOP CLOCK Register to enter
standby mode. In such mode, RAM and I/Os will remain in their
previous states until being awaken. Port IOD (7, 6, 1, 0) is the
only wake-up source in the GPC12A. After the GPC12A is
awakening, the internal CPU will go to the RESET State (Tw ≧
65536 x T1) and continue to execute program. Wakeup Reset will
not affect RAM nor I/Os (FIG.1).
6.5. I/O Port Configuration*
In p u t/O u tp u t IO C p o rt : IO C 7 - IO C 6
V
D D
lo g ic _ 2
c o n tro l
9 0 K
o u tp u t
d a ta
b u ffe r o r
O D -P M O S
in p u t d a ta
O D : O p e n D ra in
© Generalplus Technology Inc.
Proprietary & Confidential
6
MAR. 23, 2006
Version: 1.0
GPC12A
SLEEP
Wake-up
T1
CPU CLK
RESET
T
w
FIG. 1
T1 = 1 / (FCPU), Tw ≧65536 x T1
6.7. Low Voltage Reset
The GPC12A has a Low Voltage Reset (LVR) function. In
general, the CPU becomes unstable and malfunctions when the
power voltage drops below certain operating voltage. With the
unique design of Low Voltage Reset in GPC12A, it is able to reset
all functions to the initial operational (stable) state if the VDD
power-supply voltage drops around 2.2V (FIG.2).
T1
CPU CLK
VDD
2.2V
T2
Tw
RESET
T2≧2 * T1
(The LVR function is the same as Power ON Reset or External Reset.)
FIG. 2
6.8. Timer/Counter
The GPC12A has two 12-bit timer/counters, TMA and TMB
respectively. TMA can be specified as a timer or a counter, but
TMB can only be used as a timer. In the timer mode, TMA and
TMB are re-loaded up-counters. When timer rollovers from
$0FFF to $0000, the carry (overflow) signal will make the user’s
preset value to be loaded into timer automatically and up-count
again. At the same time, the carry signal will generate an INT
signal if the corresponding bit is enabled in the INT ENABLE
Register. Suppose TMA is specified as a counter, users can
reset it by loading #0 into the counter. After the counter has been
activated, the value in the counter can also be read at the same
time. The read instruction will not affect the value of the counter
nor reset it.
Clock source of Timer/Counter can be selected as follows:
Timer/Counter
Clock Source
CPU CLOCK (T) or T/4
TMA
12-BIT TIMER
12-BIT COUNTER
12-BIT TIMER
T/64, T/8192, T/65536 or EXT CLK
T or T/4
TMB
MODE SELECT REGISTER
TIMER CLOCK SELECTOR
TMA only, select timer or counter
Select T or T/4
© Generalplus Technology Inc.
Proprietary & Confidential
7
MAR. 23, 2006
Version: 1.0
GPC12A
6.9. Speech and Melody
Since the GPC12A provides a large ROM and wide range of CPU
operating speeds, it is the most suitable device for speech and
melody synthesis.
In melody synthesis, the GPC12A provides a dual tone mode to
obtain melodious music. After selecting the dual tone mode, the
user only needs to program either TMA or TMB, or both TMA and
TMB to generate expected frequency for each channel. The
hardware will toggle the tone wave automatically without entering
into an interrupt service routine. The user can create musical
instruments or sound effects by simply controlling the envelope of
tone output.
In speech synthesis, the GPC12A can use NMI for accurate
sampling frequency. The user can store the speech data in ROM
and play it back with realistic sound quality. Several algorithms
are recommended for high fidelity and compression of sound:
PCM, LOG PCM, and ADPCM.
6.10. Serial interface timing
1: Serial mode program condition: VBUREN =13V, VDDT = 5V, VDD = 5V, VSS = 0V timing as following:
SCLK
SDIO
.
.
.
.
.
R/W
ADDRESS (15:0)
DATA [7:0]
Note: R/W =1 for read mode; R/W =0 for write mode
6.11. Watchdog enable/disable
6.12. Identify code and Security option
$05F0 (bit0): watchdog timer option.
‘1’: disable watchdog timer. Generalplus highly recommend
disabling the watchdog timer.
$05F6 and $05F7: EPROM checksum for identifying use.
Serial mode can read data of $05F6 and $05F7 even security is
on.
‘0’: enable watchdog timer
$05F8 (bit7): security option.
‘1’: security OFF.
‘0’: security ON.
© Generalplus Technology Inc.
Proprietary & Confidential
8
MAR. 23, 2006
Version: 1.0
GPC12A
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics
Symbol
Ratings
DC Supply Voltage
V+
VIN
TA
< 7.0V
Input Voltage Range
Operating Temperature
Storage Temperature
-0.5V to V+ + 0.5V
0℃ to +60℃
-50℃ to +150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational
conditions see AC/DC Electrical Characteristics.
7.2. AC Characteristics (TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
2.0
Max.
4.0
-
-
MHz
MHz
VDD = 2.4V - 3.6V, for 2-battery
VDD = 3.6V - 5.5V, for 3-battery
OSC Frequency
FOSC2
4.0
6.0
7.3. DC Characteristics (VDD = 3.0V, TA = 25°C)
Limit
Typ.
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
Operating Voltage
Operating Current
Standby Current
VDD
IOP
2.4
-
3.6
2.0
2.0
-
V
mA
µA
mA
V
For 2-battery
-
1.5
FCPU = 3.0MHz @ 3.0V, no load
VDD = 3.0V
ISTBY
IAUD
VIH
-
-
-
Audio Output Current
Input High Level
-1.5
VDD = 3.0V,one-channel
VDD = 3.0V
2.0
1.6
-
-
-
-
-
-
Input High Level(IOC2-1)
Input Low Level
VIH
-
V
VDD = 3.0V
VIL
0.8
1.1
V
VDD = 3.0V
Input Low Level (IOC2-1)
Output High Current
(IOC, IOD)
VIL
-
V
VDD = 3.0V
IOH
-1.0
-
-
mA
VDD = 3.0V, VOH = 2.0V
Output Sink Current
(IOC, IOD)
IOL
2.0
-
-
-
-
mA
VDD = 3.0V, VOL = 0.8V
Input Resistor (IOD)
RIN
100
Kohm
Pull Low, VDD = 3.0V, VIN = VDD
7.4. DC Characteristics (VDD = 5.0V, TA = 25°C)
Limit
Typ.
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
Operating Voltage
Operating Current
Standby Current
VDD
IOP
3.6
-
5.5
5.0
8.0*
-
V
mA
µA
mA
V
For 3-battery
-
4.0
FCPU = 4.0MHz @ 5.0V, no load
VDD = 5.0V
ISTBY
IAUD
VIH
-
-
-
Audio Output Current
Input High Level
-3.0
VDD = 5.0V, one-channel
VDD = 5.0V
3.0
2.0
-
-
-
-
-
-
Input High Level (IOC2-1)
Input Low Level
VIH
-
V
VDD = 5.0V
VIL
0.8
1.6
V
VDD = 5.0V
Input Low Level(IOC2-1)
Output High Current
(IOC, IOD)
VIL
-
V
VDD = 5.0V
IOH
-1.0
-
-
mA
VDD = 5.0V, VOH = 4.2V
© Generalplus Technology Inc.
Proprietary & Confidential
9
MAR. 23, 2006
Version: 1.0
GPC12A
Limit
Typ.
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
Output Sink Current
(IOC, IOD)
IOL
4.0
-
-
-
-
mA
VDD = 5.0V, VOL = 0.8V
Input Resistor (IOD)
RIN
60
Kohm
Pull Low, VDD = 5.0V, VIN = VDD
Note*: Regarding EPROM option code bias circuit design, ISTBY on VDD=5V is more than on VDD=3V
© Generalplus Technology Inc.
Proprietary & Confidential
10
MAR. 23, 2006
Version: 1.0
GPC12A
7.5. The Relationship between ROSC and FCPU
7.5.1. VDD = 3.0V
7.6. The Relationship between IOP and FCPU
4
3
2
1
0
6
5
4
3
2
1
0
Vdd=5V
Vdd=3V
0
1
2
3
Fcpu (MHz)
4
5
6
0
200
400
600
800
Rosc (Kohm)
7.7. The Relationship between FCPU and VDD
7.5.2. VDD = 5.0V
7
6
6
5
4
3
2
1
0
Rosc=62KOhm
5
4
3
2
Rosc=180KOhm
1
0
2
2.5
3
3.5
4
4.5
5
5.5
6
0
100
200
300
400
500
600
700
Vdd
Rosc (KOhm)
© Generalplus Technology Inc.
Proprietary & Confidential
11
MAR. 23, 2006
Version: 1.0
GPC12A
8. APPLICATION CIRCUIT
Note1: VDD pin tie together, (11, 19, 28) for chip form, (10, 18, 20) for package
Note2: VSS pin tie together, (12, 20, 29) for chip form, (11, 19, 21) for package
© Generalplus Technology Inc.
Proprietary & Confidential
12
MAR. 23, 2006
Version: 1.0
GPC12A
9. PACKAGE/PAD LOCATIONS
9.1. PAD Assignment
VSS
29
VDD
28
NC
27
NC
26
NC
25
NC
24
NC
23
NC
22
NC
21
VSS
20
VDD
19
VDDT
18
VBUREN
17
AUD
16
RESB
15
TEST
14
CI
13
VSS
12
SCLK
1
SDI O
2
IOD0
3
IOD1
4
IOD6
5
IOD7
6
IOC7
7
IOC6
8
IOC2
9
IOC1
10
VDD
11
This IC substrate should be connected to VSS
Note1: To ensure that the IC functions properly, please bond all of VDD and VSS pins.
Note2: The 0.1µF capacitor between VDD and VSS should be placed to IC as close as possible.
9.2. Ordering Information
Product Number
Package Type
Chip form
Package form - SOP 24
GPC12A-NnnV-C
GPC12A-NnnV-PS10x
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
Note3: Package form number (x = 0 - 9, serial number).
© Generalplus Technology Inc.
Proprietary & Confidential
13
MAR. 23, 2006
Version: 1.0
GPC12A
9.3. Package Information
E
D
X
y
H
24
13
A
A1
L1
pin 1 index
detail X
1
12
e
b
Dimension in inch
Symbol
Min.
0.093
0.004
-
Typ.
0.099
-
Max.
0.104
0.012
-
A
A1
b
0.016
0.600
0.295
0.050
0.406
0.035
-
D
E
0.599
0.291
-
0.614
0.299
-
e
H
L1
y
0.394
0.016
-
0.419
0.050
0.004
© Generalplus Technology Inc.
Proprietary & Confidential
14
MAR. 23, 2006
Version: 1.0
GPC12A
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
Proprietary & Confidential
15
MAR. 23, 2006
Version: 1.0
GPC12A
11. REVISION HISTORY
Date
Revision #
Description
Page
MAR. 23, 2006
1.0
Original
Note: The GPC12A data sheet v1.0 is a continued version of SPC12A data sheet v0.3.
16
© Generalplus Technology Inc.
Proprietary & Confidential
16
MAR. 23, 2006
Version: 1.0
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明