GPCD9L270A [GENERALPLUS]
Multi-Channel Sound Controller with DC-DC Booster;
| 型号： | GPCD9L270A |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | Multi-Channel Sound Controller with DC-DC Booster |
| 文件： | 总18页 (文件大小：1358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPCDXLXXXA
Multi-Channel Sound Controller with
DC-DC Booster
Jun 18, 2013
Version 1.1
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPCDXLXXXA
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 4
2. FEATURES.................................................................................................................................................................................................. 4
3. APPLICATION FIELD.................................................................................................................................................................................. 4
4. BLOCK DIAGRAM ...................................................................................................................................................................................... 5
5. GPCDXLXXXA FAMILY AND DIFFERENT FEATURES LIST..................................................................................................................... 5
6. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 6
6.1. SIGNAL DESCRIPTION FOR GPCDXLXXXA ............................................................................................................................................ 6
7. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 7
7.1. SRAM .................................................................................................................................................................................................. 7
7.2. ROM .................................................................................................................................................................................................... 7
7.3. LOW VOLTAGE RESET ............................................................................................................................................................................ 7
7.4. INTERRUPT............................................................................................................................................................................................ 7
7.5. HARDWARE PWMIO.............................................................................................................................................................................. 7
7.6. I/O........................................................................................................................................................................................................ 7
7.6.1. I/O Configuration....................................................................................................................................................................... 7
7.7. TIMER/COUNTER (TIMER A/TIMER B/TIMER C)........................................................................................................................................ 8
7.8. SLEEP, WAKEUP AND WATCHDOG ........................................................................................................................................................... 8
7.8.1. Sleep and Wakeup.................................................................................................................................................................... 8
7.8.2. Watchdog.................................................................................................................................................................................. 8
7.9. SPEECH AND DAC ................................................................................................................................................................................. 8
7.10.SPI CONTROLLER.................................................................................................................................................................................. 8
7.11.DC-DC BOOSTER.................................................................................................................................................................................. 9
7.12.BATTERY VOLTAGE DETECT / LOW VOLTAGE DETECT .............................................................................................................................. 9
8. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 10
8.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 10
8.2. AC CHARACTERISTICS (TA = 25℃) ...................................................................................................................................................... 10
8.3. POWER CHARACTERISTICS .................................................................................................................................................................. 10
8.3.1. One battery selected, TA = 25℃............................................................................................................................................. 10
8.3.2. Two battery selected, TA = 25℃ ............................................................................................................................................. 10
8.4. REGULATOR CHARACTERISTICS (TA=25℃) ...........................................................................................................................................11
8.5. DC CHARACTERISTICS..........................................................................................................................................................................11
8.5.1. VDD_IO=3.3V, TA=25℃ ..........................................................................................................................................................11
8.5.2. VDD_IO =4.5V, TA=25℃ .........................................................................................................................................................11
8.6. DAC CHARACTERISTICS ...................................................................................................................................................................... 12
8.6.1. One battery selected, VDD_IN=1.5V VDD_DCO=3.3V, RL=8Ω, f=1KHz, TA=25℃................................................................ 12
8.6.2. Two battery selected, VDD_IN=3.0V VDD_DCO=4.5V, RL=8Ω, f=1KHz, TA=25℃................................................................ 12
8.7. PUMP EFFICIENCY ............................................................................................................................................................................... 12
8.7.1. One battery selected, VDD_IN=1.5V, TA = 25℃ ..................................................................................................................... 12
8.7.2. Two battery selected, VDD_IN=3.0V, TA = 25℃ ..................................................................................................................... 12
8.8. VDD_IN V.S. SUPPLIED CURRENT (I(VDD_DCO))................................................................................................................................ 13
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Version: 1.1
GPCDXLXXXA
8.8.1. One battery selected, TA = 25℃............................................................................................................................................. 13
8.8.2. Two battery selected, TA = 25℃ ............................................................................................................................................. 13
8.9. THE RELATIONSHIP BETWEEN ROSC AND FOSC (TA=25℃)....................................................................................................................... 13
9. APPLICATION CIRCUITS......................................................................................................................................................................... 14
9.1. GPCDXLXXXAAPPLICATION CIRCUIT WITH ROSC-MODE ...................................................................................................................... 14
9.2. GPCDXLXXXAAPPLICATION CIRCUIT WITH XTAL-MODE..................................................................................................................... 15
10.PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 16
10.1.ORDERING INFORMATION ..................................................................................................................................................................... 16
11. DISCLAIMER............................................................................................................................................................................................. 17
12.REVISION HISTORY ................................................................................................................................................................................. 18
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Version: 1.1
GPCDXLXXXA
MULTI-CHANNEL SOUND CONTROLLER
WITH DC-DC BOOSTER
1.GENERAL DESCRIPTION
The GPCDXLXXXA features an internal ROM, 512-byte working
SRAM, three 12-bit timers, 24 general I/Os with multi-channel
input and one 14-bit DAC with amplifier. The microprocessor
implements software based on audio processing, functional
control and others. For audio processing, melody and speech
can be mixed into one output. The GPCDXLXXXA is featured
maximum two sets software channel and a high performance SPU
voice engine to play voice with ADPCM/PCM data. It is designed
for wide input voltage range (1.0V~3.6V), and the circuit works at
IRQs & NMI interrupts
Watchdog function (option)
3.0V regulator output
Low Voltage Reset
24 bit-programmable general I/Os
Eight I/Os with high sink current for LED application
All general IOs with 1M pull-low function to prevent current
leakage from error key touch
One 14-bit DAC with amplifier for direct drive speaker
SPU (Sound Processing Unit) engine can output audio data
with 14-bit resolution to perform high quality voice/melody
IR PWM Output
a programmable pumped voltage (3.0V~4.5V).
In addition,
GPCDXLXXXA features sleep mode for power savings. It can be
awakened from sleep mode by interrupt sources or changing IO’s
state. There is also a Serial Peripheral Interface (SPI) controller
built-in GPCDXLXXXA to facilitate communication with other
devices and components.
Hardware PWMIO supports four LED outputs with 256-level
brightness control
Real-time clock
Multi-channel SPU engine with ADPCM/PCM wavetable
Maximum two sets of 14-bit software channel with noise filter
to play high quality sound
2.FEATURES
SPI master interface
Input Voltage: 1.0V ~ 3.6V
Built-in Battery Voltage Detect (BVD) / Low Voltage Detect
(LVD) function
Programmable pumped voltage:
One-battery selected: 3.3V ~ 4.2V
Two-battery selected: 3.3V ~ 4.5V
CPU speed: Max. 8MHz
3.APPLICATION FIELD
FOSC = Max. 16MHz (2 x CPU clock)
RAM size: Max. 512 bytes
Talking instrument controller
General music synthesizer
General purpose controller
High end toy controller
Intelligent education toys
And more
Three 12-bit timer/counter, TMA with capture and comparison
function, TMB/ TMC with comparison function only
(Programmable and Auto Reload)
Clock source with ROSC or XTAL (option)
Sleep mode to reduce power consumption
Key change wake-up function
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Version: 1.1
GPCDXLXXXA
4.BLOCK DIAGRAM
XI
Clock
XO
8-Bit controller
SRAM
Timer / Counter
ROM
Regulator/LVR/Porst
SPI
RESETB
SPU/2 software channel
14-Bit Push-Pull DAC
AUDP
AUDN
PWMIO
24 General I/O,IOA,IOB,IOD
IOD0~7
IOA0~7
IOB0~7
5. GPCDXLXXXA FAMILY AND DIFFERENT FEATURES LIST
Body
ROM size
1MB
SPU Channel
Software Channel
GPCD9L340A
GPCD9L300A
GPCD9L270A
GPCD9L220A
GPCD6L340A
GPCD6L300A
GPCD6L270A
GPCD6L220A
GPCD3L340A
8
8
8
8
4
4
4
4
1
1
1
1
1
2
2
2
2
2
912KB
832KB
672KB
1MB
912KB
832KB
672KB
1MB
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Jun. 18, 2013
Version: 1.1
GPCDXLXXXA
6. SIGNAL DESCRIPTIONS
6.1. Signal Description for GPCDXLXXXA
Mnemonic
IO PORT
Type
Description
Note
IOA7-0
I/O Bi-directional IO ports, can be wakeup pins
I/O Bi-directional IO ports, can be wakeup pins
I/O Bi-directional IO ports, can be wakeup pins
IOA3-0 high sink
IOB7-0
IOB3-0 high sink
IOD7-0
Clock related
XO
O
I
Oscillator crystal output
Keep floating at ROSC mode
XI
Oscillator crystal input/ROSC input
Power/Ground PAD
VDD_IN
P
G
P
G
P
P
P
G
P
G
P
G
P
G
P
G
Power from battery (1.0V~3.6V)
Ground reference for battery
Power output from DC-DC booster (3.3V~4.5V)
Ground reference for DC-DC booster output
regulator power output (3.0V)
regulator power input
VSS_IN
VDD_DCO1,VDD_DCO2
VSS_DC1,VSS_DC2
VDD_RGO
VDD_RGI
VDD_IO
VDD_DCO1, VDD_DCO2 are shorted on PCB
VSS_DC1, VSS_DC2 are shorted on PCB
For core power
Connect to VDD_DCO1/VDD_DCO2
VDD_IO cannot be smaller than VDD_CORE
Power for all IO ports (3.3V~4.5V)
Ground reference for all IO ports
Power for core circuit
VSS_IO
VDD_CORE
VSS_CORE
VDD_DAC
VSS_DAC
VDD_AMP
VSS_AMP
VDD_DRV
VSS_DRV
Others
Connect to VDD_RGO
Ground reference for core circuit
Power for DAC
Connect to VDD_DCO1/VDD_DCO2
Connect to VDD_DCO1/VDD_DCO2
Connect to VDD_DCO1/VDD_DCO2
Ground reference for DAC
Power for audio amplifier
Ground reference for audio amplifier
Power for audio output driver
Ground reference for audio output driver
RESETB
I
I
External reset pin (active low)
For Generalplus test mode.
NC for normal application.
inductor connection for DC-DC (1st group)
inductor connection for DC-DC (2nd group)
Audio output-P
Internal pull-high
Internal pull-low
TEST
LX1
I
I
LX2
AUDP
AUDN
MICIN
O
O
I
Audio output-N
Line-In / Microphone input
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GPCDXLXXXA
7. FUNCTIONAL DESCRIPTIONS
7.1. SRAM
IOA0~3) with brightness control of 256 levels. The clock source
of PWMIO can be selected by user’s request.
The 512-byte SRAM (including Stack) area is located in
$000000~$0002FF.
7.6. I/O
7.2. ROM
The purpose of input and output port is to communicate with
other devices. Maximum 24 programmable I/O ports are built-in
for GPCDXLXXXA, including Port A, B and D. All ports are
general I/Os with programmable wake-up capability. In addition,
these ports also provide some special functions in certain pins.
Please refer to following figure for more information about IO
Sharing.
GPCDXLXXXA is capable of accessing internal 1MB ROM. The
ROM size is depicted in following table:
Body
ROM Size
1MB
ROM Address
GPCD9L340A
GPCD9L300A
GPCD9L270A
GPCD9L220A
GPCD6L340A
GPCD6L300A
GPCD6L270A
GPCD6L220A
GPCD3L340A
0x00840~0xFFFFF
0x00840~0xE3FFF
0x00840~0xCFFFF
0x00840~0xA7FFF
0x00840~0xFFFFF
0x00840~0xE3FFF
0x00840~0xCFFFF
0x00840~0xA7FFF
0x00840~0xFFFFF
912KB
832KB
672KB
1MB
7.6.1. I/O Configuration
The following diagram represents the I/O schematic.
912KB
832KB
672KB
1MB
I/O A, B, D Schematic:
Buffer(R)
Port_Data(W)
7.3. Low Voltage Reset
Register
pull high
pull low
Port_Buffer(W)
Port_DIR(R/W)
Port_ATTR(R/W)
Pin pad
The GPCDXLXXXA provides another important feature - Low
Voltage Reset (LVR). With the LVR function, a reset signal is
generated to reset system when the operating voltage drops
below LVR level.
Control
logic
Data(R)
7.4. Interrupt
Port_Data and Port_Buffer are written into the same register but
reading from different node. To activate key wakeup function,
user should latch data on IOX_Data and enable the key wakeup
function. Wakeup is triggered when the port’s state is different
from the latched data.
The GPCDXLXXXA has two interrupt (INT) modes: IRQ (interrupt
Request) and NMI (Non-Mask Interrupt Request). The interrupt
controller controls fifteen IRQs and seven NMIs. A NMI cannot
be interrupted by any other IRQs.
7.5. Hardware PWMIO
Hardware PWMIO supports four LED outputs from IOB0~3(or
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GPCDXLXXXA
A summary of IO sharing is listed as following.
IO Sharing
IOA
Bit3
IOB
Bit7
Bit6
Bit5
Bit4
Bit2
Bit1
Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Wake up
High sink
PWMIO
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IR(Output)
External INT
External Clock
RTC
V
V
V(TMC)
V(in)
V(TMB)
V(in)
V(TMA)
V
V
IIS out/in
QD
V(in)
V(out)
V(qd2)
V(out)
V(qd1)
V(out)
V(qd1)
V(qd2)
V
CC
TMC
V
TMB
V
TMA
V
TMC
V
TMB
V
TMA
V
1M pull low
V
V
V
V
V
V
V
V
V
IOD
Bit7
Bit6
Bit5
V
Bit4
V
Bit3
Bit2
V
Bit1
V
Bit0
V
Wake up
SPI
V
V
V
V(rx)
V
V(tx) V(ck) V(cs)
V
1M pull low
V
V
V
V
V
V
*Note: QD means quadrature decoder, CC means Capture/Comparison.
7.7. Timer/Counter (Timer A/Timer B/Timer C)
7.8.2. Watchdog
Three 12-bit timers are embedded in GPCDXLXXXA: Timer A,
Timer B and Timer C. These timers all have a 12-bit up counter,
a preloaded register, and programmable clock sources. Timer
A/B can also be the clock source of the software channel. The
clock source of each timer can be set individually. Two clock
sources including CPU clock and external clock can be selected
individually or their combination to be timer’s clock source.
Besides, capture and comparison function are supported by TMA.
Comparison is supported by TMB and TMC.
If the watchdog function is enabled, a reset signal is generated to
reset system when watchdog counter is overflow.
7.9. Speech and DAC
The GPCDXLXXXA uses a high performance SPU voice engine to
achieve multi-channel voice with ADPCM/PCM. A hardware
multiplier is also embedded in this SPU for software usage.
Moreover, there is maximum two sets 14-bit DAC with amplifier for
direct audio output.
7.8. Sleep, Wakeup and Watchdog
7.8.1. Sleep and Wakeup
7.10. SPI Controller
A
Serial Peripheral Interface (SPI) controller is built in
Sleep mode saves power by stopping clock while device is not in
use. When entering into sleep mode, the device runs from
operating mode to standby mode. Wake-up from sleep mode is
to turn back to operating mode.
GPCDXLXXXA to facilitate communication with other devices and
components. There are four control signals on SPI: SPICSN,
SPICLK (SCK), SPIRX (SDI), and SPITX (SDO); these four signals
are shared with PortD0, PortD1, PortD2, and PortD3. While SPI
module is enabled by corresponding control bits, these four pins
cannot be GPIOs and any setting on corresponding GPIO control
register will have no effect. Four types of timing are presented as
follows:
1) Sleep: after power-on reset, IC starts working until a sleep
command is given. When a sleep signal is accepted, IC will turn
off system clock and enter into sleep mode.
2) Wake-up: while a wakeup source is generated, GPCDXLXXXA
wakes up from sleep mode. While wake-up is completed,
program counter will continue to execute the next command.
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GPCDXLXXXA
SPICLK
SPICLK
SPICSN
SPIRX
SPICSN
SPIRX
MSB
MSB
LSB MSB
LSB MSB
Q
MSB
MSB
LSB
LSB
Q
SPITX
SPIOE
SPITX
SPIOE
8 bits
8 bits
Master Mode, SPO = 1, SPH=1
Master Mode, SPO = 0, SPH=0
7.11. DC-DC Booster
SPICLK
The GPCDXLXXXA can be supplied wide input voltage
(1.0V~3.6V) and work with a programmable pumped voltage.
Inside the chip, it is implemented a group of high efficient DC-DC
booster circuit. The DC-DC booster circuit pumps input voltage
to 3.3V~4.5 that supplies chip as working voltage.
SPICSN
SPIRX
Q
MSB
MSB
LSB
LSB
Q
SPITX
SPIOE
7.12. Battery Voltage Detect / Low Voltage Detect
The GPCDXLXXXA is built-in Battery Voltage Detect (BVD)
function. The battery voltage level can be read back by program.
Furthermore, user can set low voltage level and get the Low
Voltage Detect (LVD) flag by program.
8 bits
Master Mode, SPO = 0, SPH=1
SPICLK
SPICSN
SPIRX
MSB
MSB
LSB
Q
SPITX
SPIOE
LSB
8 bits
Master Mode, SPO = 1, SPH=0
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Version: 1.1
GPCDXLXXXA
8. ELECTRICAL SPECIFICATIONS
8.1. Absolute Maximum Ratings
Characteristics
DC Supply Voltage
Input Voltage Range
Operating Temperature
Storage Temperature
Symbol
V+
Ratings
< 7.0V
VIN
-0.5V to V+ + 0.5V
0℃ to +60℃
TA
-50℃ to +150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to the device. For normal operational conditions
see DC Electrical Characteristics.
8.2. AC Characteristics (TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
VDD_IN = 1.0V - 3.6V
Min.
Typ.
Max.
OSC Frequency
FOSC
-
-
16.0
MHz
8.3. Power Characteristics
8.3.1. One battery selected, TA = 25℃
Limit
Typ.
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
I(VDD_DCO)=80mA@VDD_DCO=3.3V
I(VDD_DCO)=30mA@VDD_DCO=4.2V
L=15uH/0.5W (Color Code Inductance)
Input Voltage (Min.) *
VDD_IN
1.0
-
-
V
Input Voltage (Max.)
Operating Voltage**
(pump voltage)
VDD_IN
-
-
-
1.8
4.2
V
V
VDD_DCO
3.3
VDD_IN=1.5V, VDD_DCO=3.3V
FCPU = 8MHz , DAC on, no load
VDD_IN=1.5V, VDD_DCO=4.2V
FCPU = 8MHz , DAC on, no load
VDD_IN=1.5V, VDD_DCO=3.3V
FCPU = 8MHz , DAC off, no load
VDD_IN=1.5V, VDD_DCO=4.2V
FCPU = 8MHz , DAC off, no load
VDD_IN = 1.5V
-
-
-
20
30
13
-
-
-
mA
mA
mA
Operating Current-1
IOP-1
Operating Current-2
Standby Current
IOP-2
-
-
20
-
-
mA
ISTBY
5.0
μA
*As I(VDD_DCO) is greater than the value of test condition; VDD_DCO can be observed voltage drop.
**VDD_DCO is the pumped voltage. It is greater than or equal to input voltage. It is possible to be lower with heavy loading under operating.
8.3.2. Two battery selected, TA = 25℃
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
I(VDD_DCO)=40mA@VDD_DCO=3.3V
I(VDD_DCO)=15mA@VDD_DCO=4.5V
L=15uH/0.5W (Color Code Inductance)
Input Voltage (Min.) *
VDD_IN
1.3
-
-
V
V
Input Voltage (Max.)
Operating Voltage**
VDD_IN
-
-
-
3.6
4.5
VDD_DCO
3.3
VDD_IN=3.0V, VDD_DCO=3.3V
FCPU = 8MHz , DAC on, no load
VDD_IN=3.0V, VDD_DCO=4.5V
FCPU = 8MHz , DAC on, no load
-
-
10
15
-
-
mA
mA
Operating Current-1
IOP-1
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GPCDXLXXXA
Limit
Typ.
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
VDD_IN=3.0V, VDD_DCO=3.3V
FCPU = 8MHz , DAC off, no load
VDD_IN=3.0V, VDD_DCO=4.5V
FCPU = 8MHz , DAC off, no load
VDD15 = 3.0V
-
6
-
mA
Operating Current-2
Standby Current
IOP-2
-
-
9
-
-
mA
ISTBY
10.0
μA
*As I(VDD_DCO) is larger than the value of test condition; VDD_DCO can be observed voltage drop.
**VDD_DCO is the pumped voltage. It is greater than or equal to input voltage. It is possible to be lower with heavy loading under operating.
8.4. Regulator Characteristics (TA=25℃)
Limit
Characteristics
Symbol
Unit
Test condition
Min.
2.3
-
Typ.
Max.
5.5
30
Input Voltage
VDD_RGI
IVDD_RGO
-
-
-
V
mA
V
Maximum Current Output
Output Voltage*
VDD_RGO
2.7
3.3
VDD_RGI > 3.0V*
*As VDD_RGI is smaller than 3.0V+△V, VVDD_RGO=VDD_RGI-△V (△V ~ 0.1V-0.4V as IVDD_RGO=30mA)
8.5. DC Characteristics
8.5.1. VDD_IO=3.3V, TA=25℃
Limit
Characteristics
Input High Level
Symbol
Unit
Test Condition
Min.
Typ.
Max.
VIH
VIL
0.7*VDD_IO
VSS_IO
-
-
VDD_IO
V
V
-
-
Input Low Level
0.3*VDD_IO
Output High Current
IOH
IOL1
IOL2
RPL
RPL2
RPH
-
-
-
-
-
-
6
-
-
-
-
-
-
mA
mA
mA
VDD_IO =3.3V, VOH =0.7*VDD_IO
VDD_IO =3.3V, VOL =0.3*VDD_IO
VDD_IO =3.3V, VOL =0.3*VDD_IO
(IOA[7:0]/IOB[7:0]/IOD[7:0])
Output Low Sink Current
(IOA[7:4]/IOB[7:4]/IOD[7:0])
Output Low Sink Current
(IOA[3:0]/IOB[3:0])
9
18
Input Pull-Low Resistor
(IOA[7:0]/IOB[7:0]/IOD[7:0])
High Input Pull-Low Resistor
(IOA[7:0]/IOB[7:0]/IOD[7:0])
Input Pull-High Resistor
(IOA[7:0]/IOB[7:0]/IOD[7:0])
100
850
100
Kohm VDD_IO =3.3V, Vin =VDD_IO
Kohm VDD_IO =3.3V, Vin =VDD_IO
Kohm VDD_IO =3.3V, Vin =VSS_IO
8.5.2. VDD_IO =4.5V, TA=25℃
Limit
Characteristics
Input High Level
Symbol
Unit
Test Condition
Min.
Typ.
Max.
VIH
VIL
0.7*VDD_IO
VSS_IO
-
-
VDD_IO
V
V
-
-
Input Low Level
0.3*VDD_IO
Output High Current
IOH
-
-
10
16
-
-
mA
mA
VDD_IO =4.5V, VOH =0.7*VDD_IO
VDD_IO =4.5V, VOL =0.3*VDD_IO
(IOA[7:0]/IOB[7:0]/IOD[7:0])
Output Low Sink Current
(IOA[7:4]/IOB[7:4]/ IOD[7:0])
IOL1
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GPCDXLXXXA
Limit
Typ.
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
Output Low Sink Current
(IOA[3:0]/IOB[3:0])
IOL2
RPL1
RPL2
RPH
-
31
-
mA
VDD_IO =4.5V, VOL =0.3*VDD_IO
Input Pull-Low Resistor
(IOA[7:0]/IOB[7:0]/IOD[7:0])
High Input Pull-Low Resistor
(IOA[7:0]/IOB[7:0]/IOD[7:0])
Input Pull-High Resistor
(IOA[7:0]/IOB[7:0]/IOD[7:0])
-
-
-
100
850
100
-
-
-
Kohm VDD_IO =4.5V, Vin =VDD_IO
Kohm VDD_IO =4.5V, Vin =VDD_IO
Kohm VDD_IO =4.5V, Vin =VSS_IO
8.6. DAC Characteristics
8.6.1. One battery selected, VDD_IN=1.5V VDD_DCO=3.3V, RL=8Ω, f=1KHz, TA=25℃
Limit
Characteristics
Symbol
Unit
Min.
Typ.
-
Max.
DAC Resolution
RESO
-
-
-
-
14
-
Bit
%
THD+n (3.3V@0.175W)
Noise at No Signal
-
-
-
0.4
-84
-78
-
dBr A
dBr A
Dynamic Range(-60dB)
-
8.6.2. Two battery selected, VDD_IN=3.0V VDD_DCO=4.5V, RL=8Ω, f=1KHz, TA=25℃
Limit
Characteristics
Symbol
Unit
Min.
Typ.
-
Max.
DAC Resolution
RESO
-
-
-
-
14
-
Bit
%
THD+n (4.5V@0.35W)
Noise at No Signal
Dynamic Range(-60dB)
-
-
-
0.3
-84
-75
-
dBr A
dBr A
-
8.7. Pump Efficiency
8.7.1. One battery selected, VDD_IN=1.5V, TA = 25℃
Limit
Typ.
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
Pump Efficiency
(L=15uH/0.5W)
-
-
80
70
-
-
%
%
I(VDD_DCO)=30mA; VDD_DCO=3.3V
I(VDD_DCO)=100mA; VDD_DCO=3.3V
Eff.
*Use Color Code Inductance
8.7.2. Two battery selected, VDD_IN=3.0V, TA = 25℃
Limit
Typ.
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
Pump Efficiency
(L=15uH/0.5W)
-
-
81
75
-
-
%
%
I(VDD_DCO)=50mA; VDD_DCO=4.5V
I(VDD_DCO)=200mA; VDD_DCO=4.5V
Eff.
*Use Color Code Inductance
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GPCDXLXXXA
8.8. VDD_IN v.s. Supplied Current (I(VDD_DCO))
8.8.1. One battery selected, TA = 25℃
VDD_IN (V)
I(VDD_DCO) (mA)
Condition
1.0
1.2
80
VDD_DCO=3.3V ; L=15uH/0.5W (Color Code Inductance)
VDD_DCO=3.3V ; L=15uH/0.5W (Color Code Inductance)
VDD_DCO=3.3V ; L=15uH/0.5W (Color Code Inductance)
130
200*
1.5
*The max measured current of I(VDD_DCO) is 200mA only.
8.8.2. Two battery selected, TA = 25℃
VDD_IN (V)
I(VDD_DCO) (mA)
Condition
1.5
2.4
10
VDD_DCO=4.5V ; L=15uH/0.5W (Color Code Inductance)
VDD_DCO=4.5V ; L=15uH/0.5W (Color Code Inductance)
200*
*The max measured current of I(VDD_DCO) is 200mA only.
8.9. The Relationship between ROSC and FOSC (TA=25℃)
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GPCDXLXXXA
9.APPLICATION CIRCUITS
9.1. GPCDXLXXXA Application Circuit with ROSC-Mode
GPCDXLXXXA
Note:
1. L1 and L2 should be as close as to VDD_IN/LX1/LX2 as possible. Please use inductance with lower resistance to gain higher efficiency.
15uH/0.5W@IDC(max)>250mA, ESR<1.5ohm is recommended.
2. The value of C3 is dependent on the loading of application. Generally, 47uF should be enough. C3 should be as close as possible to
VDD_DCO1/VDD_DCO2.
3. C4 should be as close as possible to VDD_DAC/VSS_DAC.
4. C5 should be as close as possible to VDD_AMP/VDD_DRV and VSS_AMP/VSS_DRV.
5. The capacitance of C9 can not be large than 0.01uF.
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GPCDXLXXXA
9.2. GPCDXLXXXA Application Circuit with XTAL-Mode
45
LX1
8
SPKN
41
13
LX2
L1*1
15uH
L2*1
15uH
SPKP
GPCDXLXXXA
R1
100ohm
47
VIN
C1
10uF
C2
0.1uF
(Battery)
48
VSS1
44,43
46,42
C3
47~100uF
VSS_D1/VSS_D2
VDDO1/VDDO2
50
27
6
VREG_I
VDDIO
R2
100ohm
V50_DAC
32-29,
26-23
C4
IOA[7:0]
IOB[7:0]
IOD[7:0]
IOA[7:0]
IOB[7:0]
IOD[7:0]
10uF
7
VSS_DAC
40-33
22-15
12,11
V50_AMP / V50_DRV
C5
10uF
9,10
28
VSS_AMP/VSS_DRV
VSSIO
51
RESETB
4
C9
0.01uF
VSS
C6
1uF
49
3
VDD27D
VDD
C7*2
20 ~50pF
2
XI
C8*2
20 ~50pF
1
XO
Note:
1. L1 and L2 should be as close as to VDD_IN/LX1/LX2 as possible. Please use inductance with lower resistance to gain higher efficiency.
15uH/0.5W@IDC(max)>250mA, ESR<1.5ohm is recommended.
2. The values of C7/C8 are for design guidance only; different values may be needed for different crystal/resonator used.
3. The value of C3 is dependent on the loading of application. Generally, 47uF should be enough. C3 should be as close as possible to
VDD_DCO1/VDD_DCO2.
4. C4 should be as close as possible to VDD_DAC/VSS_DAC.
5. C5 should be as close as possible to VDD_AMP/VDD_DRV and VSS_AMP/VSS_DRV.
6. The capacitance of C9 can not be large than 0.01uF.
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GPCDXLXXXA
10. PACKAGE/PAD LOCATIONS
10.1. Ordering Information
Product Number
Package Type
Chip form
GPCDXLXXXA-NnnV-C
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
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GPCDXLXXXA
11. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
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GPCDXLXXXA
12. REVISION HISTORY
Date
Revision #
Description
Page
Jun 18, 2013
May 23, 2013
1.1
1.0
Add “GPCD3L340A”.
Original
5,7
18
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