GPCE048A-NnnV-C [GENERALPLUS]
16-bit Sound Controller With 24K X 16 RO M;
| 型号： | GPCE048A-NnnV-C |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 16-bit Sound Controller With 24K X 16 RO M |
| 文件： | 总25页 (文件大小：3169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPCE048A
16-bit Sound Controller With
24K X 16 ROM
OCT. 04, 2013
Version 1.3
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPCE048A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3
2. BLOCK DIAGRAM ...................................................................................................................................................................................... 3
3. FEATURES.................................................................................................................................................................................................. 3
4. APPLICATION FIELD.................................................................................................................................................................................. 3
5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 4
5.1. PAD ASSIGNMENT ................................................................................................................................................................................. 5
5.2. PIN MAP ............................................................................................................................................................................................... 6
6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 7
6.1. CPU ..................................................................................................................................................................................................... 7
6.2. MEMORY ............................................................................................................................................................................................... 7
6.3. PLL, CLOCK, POWER MODE................................................................................................................................................................... 7
6.4. STANDBY MODE..................................................................................................................................................................................... 7
6.5. LOW VOLTAGE DETECTION AND LOW VOLTAGE RESET............................................................................................................................. 8
6.6. INTERRUPT............................................................................................................................................................................................ 8
6.7. I/O........................................................................................................................................................................................................ 8
6.8. SPECIAL FUNCTION IN PORT................................................................................................................................................................... 9
6.9. TIMER / COUNTER................................................................................................................................................................................ 10
6.10.SLEEP MODE, WAKEUP, HALT MODE, AND WATCHDOG ...........................................................................................................................11
6.11.SOFT RESET PROTECTION ................................................................................................................................................................... 12
6.12.ADC (ANALOG TO DIGITAL CONVERTER) / DAC .................................................................................................................................... 12
6.13.SPI..................................................................................................................................................................................................... 12
6.14.AUDIO ALGORITHM............................................................................................................................................................................... 12
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 13
7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 13
7.2. DC CHARACTERISTICS (VDD_REG = 3.3V, VDDIO = 4.5V (PORTA & B), TA = 25℃)............................................................................ 13
7.3. DC CHARACTERISTICS (VDD_REG = 3.3V, VDDIO = 3.3V (PORTA & B), TA = 25℃)............................................................................ 13
7.4. ADC CHARACTERISTICS (AVDD = 3.3V, TA = 25℃).............................................................................................................................. 14
7.5. DAC CHARACTERISTICS (AVDD = 3.3V, TA = 25℃).............................................................................................................................. 14
7.6. REGULATOR CHARACTERISTICS ( TA = 25℃) ........................................................................................................................................ 15
7.7. PULL HIGH RESISTER AND VDDIO........................................................................................................................................................ 15
7.8. PULL LOW RESISTER AND VDDIO(NORMAL PAD) ................................................................................................................................. 15
7.9. PULL LOW RESISTER AND VDDIO(IOB[7:0] PAD WITH INPUT HIGH)....................................................................................................... 15
7.10.I/O OUTPUT HIGH CURRENT IOH AND VDDIO ........................................................................................................................................ 15
7.11.I/O OUTPUT LOW CURRENT IOL AND VDDIO(NORMAL PAD) ................................................................................................................... 16
7.12.I/O OUTPUT LOW CURRENT IOL AND VDDIO(HIGH DRIVING PAD)............................................................................................................ 16
7.13.DAC OUTPUT CURRENT IOLAND AVDD............................................................................................................................................... 16
8. APPLICATION CIRCUITS......................................................................................................................................................................... 17
8.1. APPLICATION CIRCUIT-(1)..................................................................................................................................................................... 17
8.2. APPLICATION CIRCUIT-(2)..................................................................................................................................................................... 19
8.3. APPLICATION CIRCUIT-(3)..................................................................................................................................................................... 21
9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 23
9.1. ORDERING INFORMATION ..................................................................................................................................................................... 23
9.2. PACKAGE INFORMATION....................................................................................................................................................................... 23
10.DISCLAIMER............................................................................................................................................................................................. 24
11. REVISION HISTORY ................................................................................................................................................................................. 25
© Generalplus Technology Inc.
Proprietary & Confidential
2
Oct. 04, 2013
Version: 1.3
GPCE048A
16-BIT SOUND CONTROLLER
WITH 24K X 16 ROM
1. GENERAL DESCRIPTION
3. FEATURES
GPCE048A, a 16-bit architecture sound controller, features the
newest 16-bit microprocessor, μ’nSP™ (pronounced as
micro-n-SP), developed by Sunplus Technology. This high
processing speed assures the μ’nSP™ is capable of handling
complex digital signal processes easily and rapidly. Therefore,
the GPCE048A is applicable to the areas of digital sound process
and voice recognition. The operating voltage of 2.4V through
5.5V and speed of 0.16MHz through 49.152MHz yield the
GPCE048A to be easily used in varieties of applications. The
memory capacity includes 24K-word ROM plus a 2K-word
16-bit μ’nSP™ microprocessor
CPU Clock: 0.16MHz - 49.152MHz
Operating Voltage: 2.4V - 5.5V
Power regulator build-in with input voltage: 2.4~5.5V, output
voltage: 2.4~3.3V
Mask ROM Operating Voltage: 2.4V - 3.6V
IO PortA & B Operating Voltage: 2.4V - 5.5V
24K-word fast speed ROM
2K-word working SRAM
Software-based audio processing
Standby mode for power saving
Three 16-bit timers/counters
working SRAM.
Other features include 32 programmable
multi-functional I/Os, three 16-bit timers/counters, 32768Hz Real
Time Clock, Low Voltage Reset/Detection, eight channels 12-bit
ADC (one channel built-in MIC amplifier with auto gain controller),
14-bit DAC output and many others.
One 14-bit DAC output
32 general I/Os (bit programmable)
Key wakeup function (IOA0 - 15)
PLL feature for system clock
32768Hz Real Time Clock (RTC)
Eight channels 12-bit AD converter
ADC external top reference voltage
Built-in microphone amplifier and AGC function
Low voltage reset and low voltage detection
Watchdog Enable (option)
2. BLOCK DIAGRAM
Regulator
Fast-speed ROM
un'SP
24K word
16-bits CPU
DAC
DAC
One SPI serial interface I/O
MICIN
MICIP
MICO
OPI
AGC
V_MIC
PLL / Systemclock /
Reset Function
X32I
AD Converter
MIC
X32O
VADREF
4. APPLICATION FIELD
2K(word) Working
SRAM
TimeBase/WatchDog
16-bits Counter/Timer
/ Interrupt
Voice Recognition Products
Intelligent Interactive Talking Toys
Advanced Educational Toys
Kids Learning Products
RESETB
SPI
Memory Mapping & Control
/ GPIOSpecial Function
/ PWM output
General I/O Port
Kids Storybook
IOA[15:0] IOB[15:0]
General Speech Synthesizer
Long Duration Audio Products
Recording / Playback Products
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Oct. 04, 2013
Version: 1.3
GPCE048A
5. SIGNAL DESCRIPTIONS
Mnemonic
PORT A, Port B
IOA[15:0]
PIN No.
LQFP 64 PIN No. Type
Description
26-35, 38-43
28-37, 40-45
I/O IOA[15:0]: bi-directional I/O ports
It can be programmed as wakeup I/O pins
I/O IOB [15:0]: bi-directional I/O ports
IOB [15:0]
4-1, 56-53,
14-11, 8-5
6-3, 64-61,
16-13, 10-7
Power & GND
VDDIOA
VSSIOA
VDDIOB
VSSIOB
AVDD
36
37
9
38
39
11
12
25
23
54
53
P
G
P
G
P
G
P
G
Power VDD for Port A
Power GND for Port A
Power VDD for Port B
10
23
21
50
49
Power GND for Port B
Power VDD for AD,DA + PLL(3.3V)
Power GND for AD,DA + PLL
Power VDD for Core (3.3V)
Power GND for Core
AVSS
VDD
VSS
CLK SYSTEM/ ICE INTERFACE
X32I
48
47
52
51
I
32K Oscillator crystal input
32K Oscillator crystal output
X32O
OPTION
TEST
O
51
24
58
26
I
TEST Mode selection pin, high is test mode and low is normal mode
(Pad internal pull low)
DAC
DAC
O
Audio DAC output
ADC
MICP
19
18
17
16
15
22
20
21
20
19
18
17
24
22
I
I
MIC amplifier input positive (Internal Floating)
MIC amplifier input negative (refer to application circuit)
MIC amplifier output (refer to application circuit)
Audio amplifier negative input (refer to application circuit)
AGC by pass filter (refer to application circuit)
Microphone power supply
MICN
MICOUT
OPI
O
I
AGC
IO
O
O
VMIC
VADREF
PLL
AVREF_DA reference pin
VCOIN
Other Signal
RESETB
VDD_REG
VSS_REG
VDD33_REG
Total: 56 pads
25
27
I
PLL low pass filter input
52
45
44
46
59
47
46
48
I
I
I
System reset pin (active low) (internal 47Kohm pull high resistor)
Positive supply for regulator(2.4V~5.5V)
Ground reference for regulator
I/O 3V power output from regulator
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Version: 1.3
GPCE048A
5.1. PAD Assignment
IOB[12]
IOB[13]
VDD33_REG
VDD_REG
VSS_REG
IOA[0]
IOA[1]
IOA[2]
IOA[3]
IOA[4]
IOA[5]
VSSIOA
VDDIOA
IOA[6]
IOA[7]
IOA[8]
IOA[9]
IOA[10]
IOB[14]
IOB[15]
IOB[0]
IOB[1]
IOB[2]
IOB[3]
VDDIOB
VSSIOB
IOB[4]
IOB[5]
IOB[6]
IOB[7]
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Version: 1.3
GPCE048A
5.2. PIN Map
LQFP64
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
VDD33_REG
NC
NC
1
2
3
VDD_REG
VSS_REG
IOA[0]
IOB[12]
IOB[13]
IOB[14]
IOB[15]
IOB[0]
4
5
45
44
IOA[1]
6
IOA[2]
43
42
41
40
39
7
IOA[3]
IOB[1]
8
GPCE048A
IOA[4]
IOB[2]
IOA[5]
9
IOB[3]
10
VSSIOA
VDDIOB
VSSIOB
IOB[4]
VDDIOA
IOA[6]
11
12
13
14
15
16
38
37
36
IOA[7]
IOB[5]
35
34
33
IOA[8]
IOA[9]
IOB[6]
IOB[7]
IOA[10]
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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Version: 1.3
GPCE048A
6. FUNCTIONAL DESCRIPTIONS
6.1. CPU
6.2. Memory
6.2.1. SRAM
The GPCE048A is equipped with a 16-bit μ’nSP™, the newest
16-bit microprocessor by Sunplus (pronounced as micro-n-SP).
Eight registers are involved in μ’nSP™: R1 - R4 (General-
purpose registers), PC (Program Counter), SP (Stack Pointer),
Base Pointer (BP) and SR (Segment Register). The interrupts
include three FIQs (Fast Interrupt Request) and eight IRQs
(Interrupt Request), plus one software-interrupt, BREAK.
The amount of SRAM is 2K-word (including Stack), ranged from
$0000 through $07FF with access speed of two CPU clock
cycles.
Phase Lock Loop
Fosc/n
CPU Clock
FOSC
32768Hz X'tal
(PLL)
PLL OUT
24.576MHz(default)
20.48MHz
System Clock generator
n:1,2,4,8,16,32,64
(Default : Fosc/8)
32.768MHz
40.96MHz
49.152MHz
b2 b1 b0
b7
b6 b5
b7,b6,b5 of P_SystemClock(W)($2030H)
System clock frequency selection
of P_SystemClock(W)($2030H)
CPU clock frequency selection
6.2.2. ROM
oscillator in normal mode and auto-power-saving mode. In
normal mode, 32768Hz OSC always runs at the highest power
consumption. In auto-power-saving mode, however, it runs at
normal mode for the first 7.5 seconds and switches back to
power-saving mode automatically to save powers.
GPCE048A features a 24K-word high-speed memory with access
speed of two CPU clock cycles.
6.3. PLL, Clock, Power Mode
6.3.1. PLL (Phase Lock Loop)
6.4. Standby Mode
The purpose of PLL is to provide a base frequency (32768Hz)
and to pump the frequency from 20.48MHz to 49.152MHz for
system clock (FOSC). The default PLL frequency is 24.576MHz.
The GPCE048A features a power savings mode (or called
standby mode) for low power applications. To enter standby
mode, the desired key wakeup port (IOA[15:0]) must be
configured to input first. And read the Port_IOA_Data to latch
6.3.1.1. System clock
the IOA state before entering the standby mode.
Also
Basically, the system clock is provided by PLL and programmed
by the Port_SystemClock (W) to determine the clock frequency
for system. The default system clock FOSC = 24.576MHz and
CPU clock is FOSC/8 if not specified. The initial CPU clock is
Fosc/8 after system wakes up and adjusts to desired CPU clock
via programming the Port_SystemClock (W). This avoids ROM
reading failure when system awakens.
remember to enable the corresponding interrupt source(s) for
wakeup. After that, stop the CPU clock by writing $5555 into
Port_System_Sleep(W) to enter standby mode. In such mode,
SRAM and I/Os remain in the previous states until CPU being
awakened. The wakeup sources in GPCE048A include KEY
wake up (IOA[15:0]), RTC wakeup, and IRQ1 - IRQ7. After
GPCE048A is awakened, CPU will continue to execute the
program from the location it slept. Programmer can also enable
or disable the 32768Hz RTC when CPU is in standby mode.
6.3.1.2. 32768Hz RTC
The Real Time Clock (RTC) is normally used in watch, clock or
other time related products. A 2Hz-RTC (0.5 seconds) function
is loaded in GPCE048A. The RTC counts the time as well as to
wake CPU up whenever RTC occurs. Since the RTC is
generated each 0.5 seconds, time can be traced by the number
of RTC occurrences. In addition, GPCE048A supports 32768Hz
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Version: 1.3
GPCE048A
6.5. Low Voltage Detection and Low Voltage Reset
6.5.1. Low voltage detection (LVD)
Interrupt Source Interrupt Name / FIQ Name IRQ Priority
4096Hz
2048Hz
512Hz
64Hz
IRQ6_4KHz/FIQ_4KHz
IRQ6_2KHz/FIQ_2KHz
IRQ6_512Hz/FIQ_512Hz
IRQ7_64Hz/FIQ_64Hz
IRQ7_16Hz_FIQ_16Hz
IRQ7_2Hz/FIQ_2Hz
8
9
The Low Voltage Detection (LVD) reports the circumstance of
present voltage. There are four LVD levels to be selected: 2.6V,
2.8V, 3.0V and 3.2V. Those levels can be programmed via
P_LVD_Ctrl. As an example, suppose LVD is given to 2.8V.
When the voltage drops below 2.8V, the b12 of P_LVD_Ctrl is
read as HIGH. In such state, program can be designed to react
this condition.
10
11
16Hz
12
2Hz
13(Low)
6.7. I/O
Two I/O ports are built in GPCE048A - PortA and PortB, total has
32 bit-programmable I/Os. The PortA is a general purpose I/O
with programmable wakeup capability, i.e. IOA [15:0] is the key
wakeup port. To activate key wakeup function, latch data on
Port_IOA_Data and enable the key wakeup function. Wakeup is
triggered when the PortA state is different from at the time
latched. Furthermore, the I/O ports can be operated at 5V level,
higher than the CPU core which is a 3V level system. Suppose
system operating voltage is running at 3.3V, then VDDIO (power
for I/O) operates from 3.3V to 5.5V. In such condition, the I/O
pad is capable of operating from 0V through VDDIO. The
following diagram is an I/O schematic. Although data can be
written into the same register through Port_Data and Port_Buffer,
they can be read from different places, Buffer (R) and Data (R).
6.5.2. Low voltage reset
In addition to the LVD, the GPCE048A has another important
function, Low Voltage Reset (LVR). With the LVR function, a
reset signal is generated to reset system when the operating
voltage drops below LVR level. Without LVR, the CPU becomes
unstable and malfunctions when the operating voltage drops
below LVR level. The LVR will reset all functions to the initial
operational (stable) states when the voltage drops below LVR
level.
6.6. Interrupt
The GPCE048A has 13 interrupt sources, grouped into two types,
FIQ (Fast Interrupt Request) and IRQ (Interrupt request). The
priority of FIQ is higher than IRQ. FIQ is the high-priority
interrupt while IRQ is the low-priority one. An IRQ can be
interrupted by a FIQ, but not by another IRQ. A FIQ cannot be
interrupted by any other interrupt sources.
Buffer(R)
Port_Data(W)
Register
pull high
pull low
Port_Buffer(W)
Port_DIR(R/W)
Port_ATTR(R/W)
Pin pad
Control
logic
Interrupt Source Interrupt Name / FIQ Name IRQ Priority
Timer A
Timer B
Timer C
SPI
IRQ0_TMA/FIQ_TMA
IRQ1_TMB/FIQ_TMB
IRQ2_TMC/FIQ_TMC
IRQ3_SPI/FIQ_SPI
1(High)
2
3
4
5
6
7
Data(R)
Key wakeup
EXT1
IRQ5_KEY/FIQ_KEY
IRQ5_EXT1/FIQ_EXT1
IRQ5_EXT2/FIQ_EXT2
In addition to a general purpose I/O port function, PortA/B also
shares/carries some special functions. A summary of PortA/B
special functions is listed as follows:
EXT2
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Version: 1.3
GPCE048A
6.8. Special Function in Port
Port
IOA0
IOA1
IOA2
IOA3
IOA4
IOA5
IOA6
IOA7
Special Function
Function Description
Note
IO_PWM
IROUT
IO_PWM Output
Refer to Timer section
IR Output
-
-
-
-
-
-
-
High driving I/O
High driving I/O
High driving I/O
High driving I/O
Feedback Input1
EXT1
-
-
-
-
-
-
-
-
-
Refer to below Example 1
Set IOA8 as floating input mode
IOA8
IOA9
External interrupt source 1 (negative edge triggered)
Work with IOA8 by adding a RC circuit between them
Feedback Output1
Set IOA9 as inverted output
to get an OSC to EXT1 interrupt
Feedback Input2
EXT2
-
External interrupt source 2 (negative edge triggered)
Work with IOA10 by adding a RC circuit between them
to get an OSC to EXT2 interrupts
SPI chip select
Refer to below Example 1
IOA10
IOA11
Set IOA10 as floating input mode
Feedback Output2
Set IOA11 as inverted output
IOA12
IOA13
IOA14
IOA15
IOB0
IOB1
IOB2
IOB3
IOB4
IOB5
IOB6
IOB7
SPI CS
SPI CK
SPI TX
SPI RX
AN0
Refer to SPI section
Refer to SPI section
Refer to SPI section
Refer to SPI section
Refer to ADC section
Refer to ADC section
Refer to ADC section
Refer to ADC section
Refer to ADC section
Refer to ADC section
Refer to ADC section
Refer to ADC section
SPI clock
SPI data output
SPI data input
ADC Channel 0
AN1
ADC Channel 1
AN2
ADC Channel 2
AN3
ADC Channel 3
AN4
ADC Channel 4
AN5
ADC Channel 5
AN6
ADC Channel 6
AN7
ADC Channel 7
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GPCE048A
0
1
FRTC
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
FPLL
EXT2
EXT2
EXT2
EXT2
FRTC
FRTC
FRTC
FRTC
FPLL
Clock Source 1
(Input 1)
FPLL
FPLL
FPLL
b3 b2 b1 b0
P_Timer_Ctrl
Timer A Timerout INT
To interrupt module
16-bit Timer/Counter
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
EXT2
EXT2
64Hz
16Hz
2Hz
1
64Hz
16Hz
2Hz
1
64Hz
16Hz
2Hz
1
P_TimerA_CNTR
Auto reload
Clock Source 2
(Input 2)
P_TimerA_Data
16-bit pre-load register
b3 b2 b1 b0
Refer to the above table, the configuration of IOA9, IOA10, IOA11,
and IOA12 involves feedback function in which an OSC
frequency can be obtained from EXT1 (EXT2) by simply adding a
RC circuit between IOA8 (IOA10) and IOA9 (IOA11).
an appropriated clock source. Timer wills up-count from N, N+1,
N+2… 0XFFFF. An INT signal is generated at the moment of
timer rolling over from “0xFFFF” to “0x0000”, and an INT signal is
processed by INT controller immediately. At the same time, N
will be reloaded into TMA_CNT and start counting again.
6.9. Timer / Counter
In Timer A, the clock Input 1 is a high frequency source and clock
Input 2 is a low frequency clock source. The combination of
GPCE048A provides three 16-bit timers/counters
- TimerA,
TimerB and TimerC or so called universal counters. The clock
source of Timer A/B/C are from clock source Input 1 and clock
source Input 2 (see below table) which perform AND operation to
form the varieties of combinations. When timer overflows, a
timeout signal (TAOUT) is sent to CPU interrupt module to
generate a timer interrupt signal. In addition, Timer A/B/C
hardware interrupt events can be used to latch the DAC audio
output and trigger ADC conversion.
clock Input
1
and
2
provides varieties of speeds to
TimerA/CounterA - “1” representing pass signal (not gating), and
“0” meaning timer deactivated. For instance, if Input 1=”1”, the
clock is depending on Input 2. If Input 1=”0”, the TimerA is
deactivated. The EXT1/ETX2 is the external clock source 1 and
external clock source 2.
Example to Timer A, sending a write signal into TMA_CNT, the
value of TMA_DATA (value=N) will reload into TMA_CNT and set
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GPCE048A
The following clock source A/B/C means clock source for Timer
A/B/C respectively. Generally speaking, the clock source A and
C are fast clock sources and source B comes from RTC system
(32768Hz). Therefore, clock source B can be utilized as a
precise counter for time counting, e.g., the 2Hz clock can be
used for real time counting.
TMXSEL
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Input 1
‘0’
Input 2
‘0’
‘1’
‘1’
FRTC
FPLL
EXT2
EXT2
64Hz
16Hz
2Hz
‘1’
EXT2
EXT2
EXT2
EXT2
FRTC
FRTC
FRTC
FRTC
FPLL
6.9.1. IO PWM
One IO PWM which duty is selected from 1/16 to 14/16.
Example the below figure is a 3/16-duration cycle. The PWMO
64Hz
16Hz
2Hz
‘1’
waveform is made by selecting
a pulse width through
Port_PWM_Ctrl. As a result, each 16 cycles will generate a
pulse width defined in control port. These PWM signals can be
applied for controlling the speed of motor or other devices.
64Hz
16Hz
2Hz
‘1’
FPLL
FPLL
FPLL
TimerA_Timeout
Tpwmo
Tduty
PWMO
Wakeup Source
FIQ source
6.9.2. Timebase
Timebase, generated by 32768Hz crystal oscillator, is
a
Timer A interrupt
Timer B interrupt
Timer C interrupt
SPI interrupt
combination of frequency selection. Furthermore, timebase
generates 4KHz, 2KHz, 512Hz, 64Hz, 16Hz and 2Hz interrupt
sources (FIQ6/IRQ6, FIQ7/IRQ7) for Real-Time-Clock
EXT1/EXT2/KEY
RTC
6.10. Sleep Mode, Wakeup, Halt Mode, and Watchdog
6.10.1. Sleep and wakeup modes
6.10.2. Watchdog Reset
1) Sleep: After power-on reset, IC starts running until a sleep
command is issued. When a sleep command is
accepted, IC will turn the system clock (PLL) off.
After all, it enters sleep mode.
The GPCE048A provides another important feature, watchdog
reset. If the watchdog function is enabled, a reset signal is
generated to reset system when watchdog counter is overflow.
2) Wakeup: CPU awaking from sleep mode requires a wakeup
signal to turn the system clock (PLL) on. The
FIQ/IRQ signal makes CPU to complete the
wakeup process and initialization. The CPU
wakeup source is given in the following table.
The purpose of watchdog is to monitor whether the system
operates normally. Within a certain period, watchdog register
must be cleared. If it is not cleared, CPU assumes the program
has been running in an abnormal condition. As a result, the
CPU will reset the system to the initial state and start running the
program all over again.
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GPCE048A
6.11. Soft Reset Protection
common mode noise by transmitting signals through differential
MIC Inputs (MICN, MICP). Moreover, an external resistor can
be applied to adjust microphone gain and time of AGC operating.
The AD needs to select source of line-in before conversion. The
ADC take pad(AVDD) as voltage reference.
Software reset. Writes $5555 into P_System_Reset will reset
the whole system like hardware reset (pull low RESETB pin),
except a flag will set on in P_System_LVD_Ctrl(R/W).
6.12. ADC (Analog to Digital Converter) / DAC
6.13. SPI
The GPCE048A has eight channels 12-bit ADC (Analog to Digital
Converter). The function of an ADC is to convert analog signal
to digital signal, e.g. a voltage level into a digital word. The eight
channels of ADC can be seven channels of line-in from IOB [7:0]
or one channel microphone (MIC) input through amplifier and
AGC controller. The MIC amplifier circuit is capable of reducing
A
Serial Peripheral Interface (SPI) controller is built in
GPCE048A to facilitate communicating with other devices and
components. There are four control signals on SPI - SPICS
(IOA12), SPICK (IOA13), SDO (IOA14), and SDI (IOA15).
6.14. Audio Algorithm
The following speech types can be used in GPCE048A: PCM,
SACM_DVR1600, SACM_DVR3200, and SACM_DVR4800.
For melody synthesis, the GPCE048A supports SACM_MS01
(FM) and SACM_MS02 (wave-table) synthesizers.
SACM_S200,
SACM_S480,
SACM_S530,
SACM_S720,
SACM_A1600, SACM_A1601, SACM_A3600, SACM_DVR520,
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GPCE048A
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics
Symbol
Ratings
DC Supply Voltage
V+
VIO
VIN
TA
< 4.0V
< 7.0V
PortA/B Pad Supply Voltage
Input Voltage Range
Operating Temperature
Storage Temperature
-0.5V to V+ + 0.5V
0℃ to +60℃
-50℃ to +150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational
conditions see DC Electrical Characteristics.
7.2. DC Characteristics (VDD_REG = 3.3V, VDDIO = 4.5V (PortA & B), TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Operating Voltage
Operating Current
VDD_REG
IOP
2.4
-
5.5
V
-
F
OSC = 49.152MHz,
-
-
18
-
-
mA
AD, DAC disable, no load
4
μA
μA
V
Disable 32KHz crystal
Standby Current
ISTB
9
Enable 32KHz,Disable PLL(FOSC)
Input High Level
VIH
VIL
0.7VDDIO
-
-
-
-
Input Low Level
-
-
-
0.3VDDIO
V
-
Output DAC Current
Output High Current
Output Low Current
(PA[3:0], PB[7:0])
Output Low Current
(PA[7:4])
IAUD
IOH
-4.8
-11
-
-
mA
mA
For one channel DAC
VOH = 0.9VDDIO
IOL
-
-
-
-
-
11
25
-
-
-
-
-
mA
mA
KΩ
KΩ
KΩ
VOL = 0.1VDDIO
-
IOL
Input Pull-Low Resister
(PA15 :0, PB15 :8)
Input Pull-Low Resister
(PB[7:0])
RPL
RPL
RPH
120
1000
110
VIN = VDDIO
VIN = VDDIO
VIN = VSS
Input Pull-High Resister
(PA15 :0, PB15 :0)
7.3. DC Characteristics (VDD_REG = 3.3V, VDDIO = 3.3V (PortA & B), TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Operating Voltage
Operating Current
VDD_REG
IOP
2.4
-
5.5
V
-
F
OSC = 49.152MHz,
-
-
17
-
-
mA
AD, DAC disable, no load
3
μA
μA
V
Disable 32KHz crystal
Standby Current
ISTB
6
Enable 32KHz,Disable PLL(FOSC)
Input High Level
VIH
VIL
0.7VDDIO
-
-
-
-
Input Low Level
-
-
-
0.3VDDIO
V
-
Output DAC Current
Output High Current
IAUD
IOH
-3.5
-7
-
-
mA
mA
For one channel DAC
VOH = 0.9VDDIO
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GPCE048A
Limit
Typ.
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
Output Low Current
(PA[3:0], PB[7:0])
Output Low Current
(PA[7:4])
IOL
-
6
-
mA
mA
KΩ
KΩ
KΩ
VOL = 0.1VDDIO
IOL
-
-
-
-
15
-
-
-
-
-
Input Pull-Low Resister
(PA15 :0, PB15 :8)
Input Pull-Low Resister
(PB[7:0])
RPL
RPL
RPH
180
1400
160
VIN = VDDIO
VIN = VDDIO
VIN = VSS
Input Pull-High Resister
(PA15 :0, PB15 :0)
7.4. ADC Characteristics (AVDD = 3.3V, TA = 25℃)
Limit
Characteristics
Symbol
Unit
Min.
Typ.
Max.
ADC LINE_IN Input Voltage Range from
IOB[7:0]
VINL (Note 1)
VSS-0.3
-
AVDD+0.3
V
ADC Microphone Input Voltage Range
Resolution of ADC
VINM
VSS-0.3
-
-
-
AVDD+0.3
12
V
RESO
bits
Signal-to-Noise Plus Distortion of ADC from
SINAD (Note 3)
-
60
-
dB
Line in
Effective Number of Bit
Integral Non-Linearity of ADC
Differential Non-Linearity of ADC
AD Conversion Rate
ENOB (Note 4)
INL
8.0
9.0
±3.0
±1
-
bits
LSB (Note 2)
LSB
-
-
-
-
-
DNL (Note 6)
FCONV
-
-
-
FCPU/256
42
Hz
Microphone Amplifier Gain
A MIC
dB
Note1: Internal protection diodes clamp the analog input to AVDD and VSS. These diodes allow the analog input to swing from (VSS-0.3V) to (AVDD+0.3V)
without causing damage to the devices.
Note2: LSB means Least Significant Bit. With VINL = 2.6V, 1LSB = 2.6V/2^12 = 0.635mV.
Note3: The SINAD testing condition at VINLp-p = 0.8*AVDD, FCONV = Fcpu/512 = 49MHz/256 = 192KHz, Fin=1.0KHz Sine waves at AVDD = 3.0V from the IOB
[7:0] input.
Note4: ENOB = (SINAD-1.76)/6.02.
Note5: The ADC of GPCE048A can guarantee 12 bits no missing code.
Note6: The microphone amplifier maximum gain = 15 * (60K/(1.5K+REXT) V/V. The REXT is external resistor between OPI and MICOUT. The gain is 132V/V
(=42dB) when REXT is 5.1K.
7.5. DAC Characteristics (AVDD = 3.3V, TA = 25℃)
Limit
Characteristics
Resolution of DAC
Symbol
Unit
Min.
Typ.
-
Max.
RESO
SNR
-
-
-
-
14
bit
dB
Hz
%
Signal to Noise Ratio of DAC
Sample Rate
82
-
-
400K
-
FS
THD+N at FS
FOUT = 1K Hz
0.2
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GPCE048A
7.6. Regulator Characteristics ( TA = 25℃)
Unit
Typ.
Characteristics
Symbol
Unit
Min.
2.4
-
Max.
Input Voltage
VREGI
IREGO
VREGO
IRGES
5.5
60
V
mA
V
Maximum Current Output
Output Voltage
-
3.14
-
3.3
2.5
3.46
-
Standby Current
uA
7.7. Pull High Resister and VDDIO
7.9. Pull Low Resister and VDDIO(IOB[7:0] PAD with
input high)
RPH VS VDDIO
300
RPL VS VDDIO (HIGH RESISTER PAD)
2500
250
200
150
100
50
2000
1500
1000
500
0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDDIO (V)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDDIO (V)
7.8. Pull Low Resister and VDDIO(Normal PAD)
RPL VS VDDIO (NORMAL PAD)
7.10. I/O Output High Current IOH and VDDIO
300
OUTPUT HIGH CURRENT VS VDDIO
16
250
200
150
100
50
14
12
10
8
6
4
0
2
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
VDDIO (V)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDDIO (V)
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GPCE048A
7.11. I/O Output Low Current IOL and VDDIO(Normal
Pad)
7.13. DAC Output Current IOL and AVDD
DAC CURRENT VS VDD
7
6
5
4
3
2
1
0
OUTPUT LOW CURRENT VS VDDIO
0
-2
-4
-6
-8
-10
-12
-14
-16
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDDIO (V)
7.12. I/O Output Low Current IOL and VDDIO(High
driving pad)
OUTPUT LOW CURRENT VS VDDIO(HIGH DRIVING IOA[7:4])
0
-5
-10
-15
-20
-25
-30
-35
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDDIO (V)
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GPCE048A
8. APPLICATION CIRCUITS
8.1. Application Circuit-(1)
8.1.1. Application circuit (1) with regulator
VDDH(2.4v~5.5v)
Battery
1K
VMIC
RESETB
DAC
10uF
RESETB
100uF 0.1uF
0.1uF
3K
0.22uF
MICP
MICN
Speaker
0.1uF
1K
MIC
0.22uF
270
0.027uF
10K
3K
0.1uF
0.22uF
MICOUT
OPI
5.1K
IOA[15:0]
IOA[15:0]
IOB[15:0]
5000pF
IOB[15:0]
AGC
470K
4.7uF
0.1uF
VDDIOA
VDDIOB
VDD_REG
VADREF
X32I
0.1uF
10uF
VDDH (2.4v~5.5v)
Battery
20 pF*
VSS_REG
VSSIOA
VSSIOB
VSS
32768Hz
20 pF*
X32O
10uF
10uF
0.1uF
0.1uF
VCOIN
VDD(3.3v)
VDD33_REG
VDD
3.3K
3300pF
0.1uF
AVDD
AVSS
GPCE048A Application Circuit(MIC_ IN and GPY0030Aaudio amplifier)
Note*: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading, for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
Note: VDD33_REG is output of built-in regulator with maximum current 60 mA. It is recommended that only use it for internal power pad.
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GPCE048A
8.1.2. Application circuit (1) without regulator
Note*: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading, for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
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GPCE048A
8.2. Application Circuit-(2)
8.2.1. Application Circuit-(2) with regulator
Note*: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading, for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
Note: VDD33_REG is output of built-in regulator with maximum current 60 mA. It is recommended that only use it for internal power pad.
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GPCE048A
8.2.2. Application Circuit-(2) without regulator
1K
VMIC
VDDH(2.4v~5.5v)
RESETB
10uF
Battery
RESETB
3K
0.1uF
0.22uF
MICP
MICN
Speaker
MIC
4.7uF
0.22uF
1K
DAC
3K
5000pF
2K
0.22uF
MICOUT
OPI
5.1K
IOA[15:0]
IOB[15:0]
IOA[15:0]
IOB[15:0]
5000pF
AGC
GPCE048A
470K
4.7uF
0.1uF
VDDIOA
VDDIOB
VDDH(2.4v~5.5v)
Battery
VADREF
X32I
0.1uF
10uF
VSSIOA
VSSIOB
20pF*
VDD_REG
VSS_REG
32768Hz
20pF*
VSS
X32O
VDDH(2.4v~3.6v)
Battery
2.2uF
10uF
VDD33_REG
VDD
VCOIN
3.3K
3300pF
AVDD
0.1uF
0.1uF
AVSS
GPCE048A Application Circuit(MIC_IN and with BJT amplifier)
Note*: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading, for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
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GPCE048A
8.3. Application Circuit-(3)
8.3.1. Application Circuit-(3) with regulator
VDDH (2.4v~5.5v)
Battery
VMIC
RESETB
DAC
RESETB
0.1uF
Speaker
4.7uF
MICP
MICN
1K
5000pF
2K
MICOUT
OPI
IOA[15:0]
IOA[15:0]
IOB[15:0]
IOB[15:0]
GPCE048A
AGC
IOB[7:0]
VDDIOA
VDDIOB
IOB[7:0]
(8-Channel Line In)
VADREF
X32I
VDD_REG
0.1uF
20pF*
0.1uF
10uF
.
VDDH(2 4v~5.5v)
Battery
VSS_REG
VSSIOA
VSSIOB
VSS
32768Hz
20pF*
X32O
0.1uF
0.1uF
10uF
10uF
VDD(3.3v)
VDD33_REG
VDD
VCOIN
3.3K
3300pF
0.1uF
AVDD
AVSS
GPCE048A Application Circuit (LINE_IN and with BJT amplifier)
Note*: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading, for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
Note: VDD33_REG is output of built-in regulator with maximum current 60 mA. It is recommended that only use it for internal power pad.
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GPCE048A
8.3.2. Application Circuit-(3) without regulator
Note*: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading, for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
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GPCE048A
9. PACKAGE/PAD LOCATIONS
9.1. Ordering Information
Product Number
Package Type
GPCE048A-NnnV-C
Chip form
GPCE048A-NnnV-QL02x
Halogen Free Package
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
Note3: Package form number (x = 1 - 9, serial number).
9.2. Package Information
LQFP 64 Outline Dimensions
Dimension in mm
Symbol
Min.
Typ.
-
Max.
1.60
0.15
1.45
0.27
0.16
A
A1
A2
b
-
0.05
1.35
0.17
0.09
-
1.40
0.22
-
c1
D
12.00
10.00
12.00
10.00
0.50 BSC.
D1
E
E1
e
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GPCE048A
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or
alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
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GPCE048A
11. REVISION HISTORY
Date
Revision #
Description
Page
Oct. 04, 2013
1.3
1. Add COMAIR logo to the cover page
2. Update X32K crystal's capacitance note in application circuit
Modify 3. FEATURES.
Oct. 13, 2010
Dec. 28, 2009
1.2
1.1
4
12
1. Modify section 6.9.1 I/O PWM.
2. Modify section 6.12 ADC (Analog to Digital Converter) / DAC.
3. Add Application circuits to section 8.
Released edition
13
19,21,23
Mar. 16, 2009
Dec. 18, 2008
Nov. 11, 2008
1.0
0.2
0.1
Modify the Package Information in section 9.2.
Original
18
20
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