GPCE060A-NnnV-C [GENERALPLUS]
16-Bit Sound Controller with 32K x 16 ROM;
| 型号： | GPCE060A-NnnV-C |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 16-Bit Sound Controller with 32K x 16 ROM |
| 文件： | 总26页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPCE060A
16-Bit Sound Controller with
32K x 16 ROM
OCT. 01, 2013
Version 1.4
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPCE060A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 4
2. BLOCK DIAGRAM ...................................................................................................................................................................................... 4
3. FEATURES.................................................................................................................................................................................................. 4
4. APPLICATION FIELD.................................................................................................................................................................................. 4
5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5
5.1. PAD ASSIGNMENT ................................................................................................................................................................................. 6
6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 7
6.1. CPU ..................................................................................................................................................................................................... 7
6.2. MEMORY ............................................................................................................................................................................................... 7
6.2.1. SRAM........................................................................................................................................................................................ 7
6.2.2. ROM.......................................................................................................................................................................................... 7
6.3. PLL, CLOCK, POWER MODE................................................................................................................................................................... 7
6.3.1. PLL (Phase Lock Loop)............................................................................................................................................................. 7
6.4. POWER SAVINGS MODE ......................................................................................................................................................................... 7
6.5. LOW VOLTAGE DETECTION AND LOW VOLTAGE RESET............................................................................................................................. 8
6.5.1. Low voltage detection (LVD) ..................................................................................................................................................... 8
6.5.2. Low voltage reset...................................................................................................................................................................... 8
6.6. INTERRUPT............................................................................................................................................................................................ 8
6.7. I/O........................................................................................................................................................................................................ 8
6.8. TIMER/COUNTER ................................................................................................................................................................................... 9
6.8.1. Timebase ................................................................................................................................................................................ 10
6.9. SLEEP, WAKEUP AND WATCHDOG ......................................................................................................................................................... 10
6.9.1. Wakeup and sleep .................................................................................................................................................................. 10
6.9.2. Watchdog................................................................................................................................................................................ 10
6.10.ADC (ANALOG TO DIGITAL CONVERTER) / DAC .................................................................................................................................... 10
6.11.SERIAL INTERFACE I/O (SIO).................................................................................................................................................................11
6.12.UART ..................................................................................................................................................................................................11
6.13.AUDIO ALGORITHM................................................................................................................................................................................11
6.14.BONDING OPTION SUMMARY .................................................................................................................................................................11
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 12
7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 12
7.2. DC CHARACTERISTICS (VDD = 3.3V, VDDIO = 5.5V (PORTA & B), TA = 25℃) ....................................................................................... 12
7.3. DC CHARACTERISTICS (VDD = 3.3V, VDDIO = 3.3V (PORTA & B), TA = 25℃) ....................................................................................... 12
7.4. DC CHARACTERISTICS (VDD = 2.7V, VDDIO = 2.7V (PORTA & B) , TA = 25℃) ...................................................................................... 13
7.5. DC CHARACTERISTICS (VDD = 2.4V, VDDIO = 2.4V (PORTA & B) , TA = 25℃) ...................................................................................... 13
7.6. ADC CHARACTERISTICS (VDD = 3.3V, TA = 25℃)................................................................................................................................ 14
7.7. DAC CHARACTERISTICS (TA = 25℃).................................................................................................................................................... 14
7.8. PULL HIGH RESISTER AND VDDIO ......................................................................................................................................................... 15
7.9. I/O OUTPUT HIGH CURRENT IOH AND VOH .............................................................................................................................................. 15
7.10.PULL LOW RESISTER AND VDDIO.......................................................................................................................................................... 15
7.11.I/O OUTPUT LOW CURRENT IOL AND VOL ............................................................................................................................................... 15
8. APPLICATION CIRCUITS......................................................................................................................................................................... 16
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Version: 1.4
GPCE060A
8.1. APPLICATION CIRCUIT - (1)................................................................................................................................................................... 16
8.2. APPLICATION CIRCUIT - (2)................................................................................................................................................................... 17
8.3. APPLICATION CIRCUIT - (3)................................................................................................................................................................... 18
8.4. APPLICATION CIRCUIT - (4)................................................................................................................................................................... 19
8.5. APPLICATION CIRCUIT - (5)................................................................................................................................................................... 20
8.6. APPLICATION CIRCUIT - (6)................................................................................................................................................................... 21
9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 22
9.1. ORDERING INFORMATION ..................................................................................................................................................................... 22
9.2. PACKAGE INFORMATION ....................................................................................................................................................................... 22
9.2.1. LQFP 80.................................................................................................................................................................................. 22
10.DISCLAIMER............................................................................................................................................................................................. 25
11. REVISION HISTORY ................................................................................................................................................................................. 26
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Version: 1.4
GPCE060A
16-BIT SOUND CONTROLLER
WITH 32K X 16 ROM
1. GENERAL DESCRIPTION
3. FEATURES
The GPCE060A, a 16-bit architecture product, carries the newest
16-bit microprocessor, μ’nSP™ (pronounced as micro-n-SP),
developed by Sunplus Technology. This high processing speed
assures the μ’nSP™ is capable of handling complex digital signal
processes easily and rapidly. Therefore, the GPCE060A is
applicable to the areas of digital sound process and voice
recognition. The operating voltage of 2.4V through 3.6V and
speed of 0.32MHz through 49.152MHz yield the GPCE060A to be
easily used in varieties of applications. The memory capacity
includes 32K-word fast-speed ROM plus a 2K-word working
SRAM. Other features include 32 programmable multi-functional
I/Os, two 16-bit timers/counters, 32768Hz Real Time Clock, Low
Voltage Reset/Detection, eight channels 10-bit ADC (one channel
built-in MIC amplifier with auto gain controller), 10-bit DAC output
and many others.
16-bit μ’nSP™ microprocessor
CPU clock: 0.32MHz - 49.152MHz
Operating voltage: 3.0V - 3.6V @CPU clock = 49.152Mhz
Operating voltage: 2.4V - 3.6V @CPU clock <=40.96Mhz
IO PortA & B operating voltage: 2.4V - 5.5V
32K-word fast-speed ROM
2K-word working SRAM
Software-based audio processing
Crystal Resonator
Standby mode (Clock Stop mode) for power savings,
Max. 2.0μA @ VDD = 3.6V
Two 16-bit timers/counters
Two 10-bit DAC outputs
32 general I/Os (bit programmable)
14 INT sources with two priority levels
Key wakeup function (IOA0 - 7)
PLL feature for system clock
2. BLOCK DIAGRAM
32768Hz Real Time Clock (RTC)
Eight channels 10-bit AD converter
ADC external top reference voltage
2.0V voltage regulator output, 5mA of driving capability
Serial interface I/O (SIO)
Fast-speed
16-bit Timer/Counter
16-bit
SLEEP
RESET
ROM
x 2
u'nSP
TimerBase
controller
INT control
RAM
VMIC
VEXTREF
VADREF
AGC
MICOUT
MICP
CPU
Clock
VCOIN
Built-in microphone amplifier and AGC function
UART receiver and transmitter (full duplex)
Low voltage reset and low voltage detection
Watchdog enable (bonding option)
10-bit A/D
& AGC
PLL
X32I
X32O
RTC
MICN
OPI
LVD/LVR
WATCHDOG
AUD1
AUD2
10-bit DAC1 Output
10-bit DAC2 Output
UART
SIO
IOB7 (Rx)
IOB10 (Tx)
32 PIN GENERAL I/O PORT
IOB1 (SDA)
IOB0 (SCK)
4. APPLICATION FIELD
Voice recognition products
Intelligent interactive talking toys
Advanced educational toys
Kids learning products
IOA15 - 0
IOB15 - 0
Kids storybook
General speech synthesizer
Long duration audio products
Recording / playback products
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Version: 1.4
GPCE060A
5. SIGNAL DESCRIPTIONS
Mnemonic
PIN No.
Type
Description
IOA [15:8]
IOA [7:0]
46 - 39
34 - 27
I/O
I/O
IOA [15:8]: bi-directional I/O ports.
IOA [7:0] can be software programmed to wakeup I/O pins.
IOA [6:0] can be optioned as ADC Line-in input.
IOB [15:11]: bi-directional I/O ports.
IOB [15:11]
IOB 10
IOB 9
IOB 8
IOB 7
IOB 6
IOB 5
IOB 4
IOB 3
IOB 2
IOB 1
IOB 0
DAC1
DAC2
X32I
50 - 54
57
58
59
60
61
62
63
64
65
66
67
12
13
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
IOB10 can also be selected as UART Transmitter (Tx).
IOB9 can also be Multi-duty cycle output of TimerB (BPWMO).
IOB8 can also be Multi-duty cycle output of TimerA (APWMO).
IOB7 can also be selected as UART receiver (Rx).
IOB6 is a bi-directional I/O ports.
IOB5 can also be selected as feedback signal with EXT2.
IOB4 can also be selected as feedback signal with EXT1.
IOB3 can also be selected as an external interrupt input pin (EXT2)(Negative-edge Triggered).
IOB2 can also be selected as an external interrupt input pin (EXT1)(Negative-edge Triggered).
IOB1 can also be selected as a serial interface data. (SDA)
IOB0 can also be selected as a serial interface clock. (SCK)
Audio DAC1 output.
O
Audio DAC2 output.
I
Oscillator Crystal input.
X32O
VCOIN
AGC
1
O
Oscillator Crystal output.
70
16
19
21
14
I
RC filter connection for PLL.
I
AGC control pin.
MICN
MICP
I
Microphone differential input (negative).
I
Microphone differential input (positive).
V2VREF
O
2.0V output voltage, 5.0mA of driving capability (can be used as external ADC Line_IN top
reference voltage).
MICOUT
OPI
18
O
I
Microphone 1st amplifier output.
Microphone 2nd amplifier input.
17
VEXTREF
VMIC
23
25
I
ADC Line_IN top external reference voltage input pin.
Microphone power supply.
O
O
I
VADREF
VDD
22
AD reference voltage (generated by internal AD converter).
Positive supply for logic.
5, 69
VSS
8, 10, 26, 71
37, 38, 56
35, 36, 48
24
I
Ground reference for logic and I/O pins.
VDDIO
VSSIO
AVDD
AVSS
I
Positive supply for I/O pins.
I
Ground reference for I/O pins.
I
Positive supply for analog circuit including ADC, DAC and 2.0V regulator.
Ground reference for analog circuit including ADC, DAC and 2.0V regulator.
An active low reset to the chip.
15
I
68
I
RESET
SLEEP
TEST
N/C
49
O
I
Sleep mode (active high).
3
Connected to high for test mode, normally connected to GND (test mode disabled) or unconnected.
Not used.
7, 9, 11, 20,
I
47, 55
N/C
4
6
I
I
Do NOT bonding and connect this pin, if user binding this pin, IC will not work.
Connected to high for watchdog disabled, unconnected for watchdog enabled.
WDGOPT*
Note*: WDGOPT is the watchdog option pin, selected by bonding option. Remain WDGOPT float (unconnected to VDD) to
enable the watchdog. In contrast, connecting WDGOPT to VDD will disable watchdog. The reason of placing WDTOPT
adjacent to VDD is to facilitate connection between VDD and WDGOPT when disabling watchdog is necessary. The
layout of WDOGPT option pin is drawn in the right.
VDD
WDGOPT
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Oct. 01, 2013
Version: 1.4
GPCE060A
5.1. PAD Assignment
71 70 69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
1
2
X32O
X32I
54
53
52
51
50
49
48
47
46
45
44
43
42
IOB11
IOB12
IOB13
IOB14
IOB15
SLEEP
VSSIO
N/C
3
TEST
N/C
VDD
4
5
6
WDGOPT
7
N/C
8
VSS
N/C
(0,0)
9
10
11
12
13
14
15
16
17
18
19
20
VSS
N/C
IOA15
IOA14
IOA13
IOA12
DAC1
DAC2
V2VREF
AVSS
AGC
IOA11
OPI
41
40
IOA10
IOA9
MICOUT
MICN
N/C
21 22 23 24 25
26 27 28 29 30 31 32 33 34
35 36 37
38 39
This IC substrate should be connected to VSS
Note1: To ensure the IC functions properly, please bond all of VDD and VSS pins.
Note2: The 0.1μF capacitor between VDD and VSS should be placed to IC as closed as possible.
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Version: 1.4
GPCE060A
6.FUNCTIONAL DESCRIPTIONS
6.1. CPU
The GPCE060A is equipped with a 16-bit μ’nSP™, the newest
16-bit microprocessor by Sunplus and pronounced as micro-n-SP.
Eight registers are involved in μ’nSP™: R1 - R4 (General-purpose
registers), PC (Program Counter), SP (Stack Pointer), Base
Pointer (BP) and SR (Segment Register). The interrupts include
three FIQs (Fast Interrupt Request) and eight IRQs (Interrupt
Request), plus one software-interrupt, BREAK.
Moreover,
a
high performance hardware multiplier with the
capability of FIR filter is also built in to reduce the software
multiplication loading.
6.2. Memory
6.2.1. SRAM
The amount of SRAM is 2K-word (including Stack), ranged from
$0000 through $07FF with access speed of two CPU clock cycles.
Phase Lock Loop
Fosc/n
CPU Clock
FOSC
32768Hz X'tal
(PLL)
PLL OUT
24.576MHz(default)
20.48MHz
System Clock generator
n:1,2,4,8,16,32,64
(Default : Fosc/8)
32.768MHz
40.96MHz
49.152MHz
b2 b1 b0
b7
b6 b5
b7,b6,b5 of P_SystemClock(W)($7013H)
System clock frequency selection
of P_SystemClock(W)($7013H)
CPU clock frequency selection
6.2.2. ROM
The GPCE060A provides
a
32K-word fast-speed ROM with
generated in every 0.5 seconds, time can be traced by the
numbers of RTC occurrence. In addition, GPCE060A supports
32768Hz oscillator in strong mode and auto_weak mode. In
strong mode, 32768Hz OSC always runs at the highest power
consumption. In auto_weak mode, however, it runs in strong
mode for the first 7.5 seconds and changes back to auto_weak
mode automatically to save powers.
access speed of two CPU clock cycles.
6.3. PLL, Clock, Power Mode
6.3.1. PLL (Phase Lock Loop)
The purpose of PLL is to provide a base frequency (32768Hz) and
to pump the frequency from 20.48MHz to 49.152MHz for system
clock (FOSC). The default PLL frequency is 24.576MHz.
6.4. Power Savings Mode
The GPCE060A also offers a power savings mode (standby mode)
for low power application needs. To enter standby mode, the
desired key wakeup port(IOA[7:0]) must be configured to input first.
And read the Port_IOA_Latch(R) to latch the IOA state before
entering the standby mode. Also remember to enable the
corresponding interrupt source(s) for wakeup. After that, stop the
CPU clock by writing the STOP CLOCK Register (b0~b2 of
Port_SystemClock (W)) to enter standby mode. In such mode,
SRAM and I/Os remain in the previous states till CPU being
awoken. The wakeup sources in GPCE060A include Port IOA7 -
0 and IRQ1 - IRQ6. After GPCE060A is awoken, the CPU will
continue to execute the program. Programmer can also enable
or disable the 32768Hz OSC when CPU is in standby mode.
6.3.1.1. System clock
Basically, the system clock is provided by PLL and programmed
by the Port_SystemClock (W) to determine the frequency of clock
for system.
The default system clock FOSC = 24.576MHz and
CPU clock is Fosc/8 if not specified. The initial CPU clock is
Fosc/8 after system wakes up and to be adjusted to desired CPU
clock by programming the Port_SystemClock (W).
6.3.1.2. 32768Hz RTC
The Real Time Clock (RTC) is normally used in watch, clock or
other time related products. A 2Hz-RTC (1/2 second) function is
loaded in GPCE060A. The RTC counts the timing as well as to
wake CPU up whenever RTC occurs.
Since the RTC is
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GPCE060A
6.5. Low Voltage Detection and Low Voltage Reset
6.5.1. Low voltage detection (LVD)
Interrupt Source
Fosc/1024
Timer A
Interrupt Name
Priority
FIQ_PWM/IRQ0_PWM High(FIQ)
FIQ_TMA/ IRQ1_TMA High(FIQ)
FIQ_TMB/ IRQ2_TMB High(FIQ)
The Low Voltage Detection (LVD) reports the circumstance of
present voltage. There are three LVD levels to be selected: 2.5V,
Timer B
EXT2
IRQ3_EXT2
IRQ3_EXT1
IRQ3_KEY
IRQ4_4KHz
IRQ4_2KHZ
IRQ4_1KHz
IRQ5_4Hz
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
2.9V, and 3.3V.
Port_LVD_Ctrl (W). As an example, suppose LVD is given to
2.9V. When the voltage drops below 2.9V, the b15 of
These levels can be programmed via
EXT1
Key change wakeup
4096Hz
Port_LVD_Ctrl is read as HIGH. In such state, program can be
designed to react to this condition.
2048Hz
1024Hz
6.5.2. Low voltage reset
4Hz
In addition to the LVD, the GPCE060A has another important
function, Low Voltage Reset (LVR). With the LVR function, a
reset signal is generated to reset system when the operating
voltage drops below 2.3V for 4 consecutive clock cycles. Without
LVR, the CPU becomes unstable and malfunction when the
operating voltage drops below 2.3V. The LVR will reset all
functions to the initial operational (stable) states when the voltage
drops below 2.3V. A LVR timing diagram is given as follows:
2Hz
IRQ5_2Hz
Time-base 1
Time-base 2
UART (TxRDY or RxRDY)
IRQ6_TMB1
IRQ6_TMB2
UART IRQ
6.7. I/O
Two I/O ports are built in GPCE060A, PortA and PortB. The
PortA is an ordinary I/O with programmable wakeup capability. In
addition to the regular IO function, the PortB can also perform
some special functions in certain pins. Suppose operating
voltage is running at 3.6V (VDD) and VDDIO (power for I/O)
operates from 3.6V (VDD) to 5.5V. In such condition, the I/O pad
is capable of operating from 0V through VDDIO. The following
diagram is an I/O schematic.
Fosc
VDD
2.3V
Tw
Tvdd
RESET
Treset
Buffer(R)
Tw=Fosc x 4 cycle
Tvdd > Tw
Treset = Fosc x512 cycle
Port_Data(W)
Register
pull high
pull low
Port_Buffer(W)
Port_DIR(R/W)
Port_ATTR(R/W)
Pin pad
6.6. Interrupt
Control
logic
The GPCE060A has 14 interrupt sources, grouped into two types,
FIQ (Fast Interrupt Request) and IRQ (Interrupt request). The
priority of FIQ is higher than IRQ. FIQ is the high-priority interrupt
while IRQ is the low-priority one. An IRQ can be interrupted by a
FIQ, but not by another IRQ. A FIQ cannot be interrupted by any
other interrupt sources.
Data(R)
Although data can be written into the same register through
Port_Data and Port_Buffer, they can be read from different places,
Buffer (R) and Data (R). The IOA [7:0] is the key wakeup port.
To activate key wakeup function, latch data on PORT_IOA_Latch
and enable the key wakeup function. Wakeup is triggered when
the PortA state is different from at the time latched. In addition to
an ordinary I/O port, PortB carries some special functions.
summary of PortB special functions is listed as follows:
A
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GPCE060A
Special function in PortB
PortB
IOB0
IOB1
IOB2
Special Function
Function Description
Serial interface clock
Serial interface data
External interrupt source 1(Negative-edge Triggered) IOB2 set as input mode
Note
SCK
SDA
EXT1
Refer to see SIO section
Refer to see SIO section
Feedback Output1 Works with IOB4 by adding a RC circuit between IOB2 set as inverted output
them to get an OSC to EXT1 interrupt
IOB3
EXT2
External interrupt source 2(Negative-edge Triggered) IOB3 set as input mode
Feedback Output2 Works with IOB5 by adding a RC circuit between IOB3 set as inverted output
them to get an OSC to EXT2 interrupt
IOB4
IOB5
IOB7
IOB8
IOB9
IOB10
Feedback Input1
Feedback Input2
Rx
-
-
-
-
UART Receiver
TimerA PWM output
TimerB PWM output
UART Transmitter
Refer to see UART section
Refer to Timer/Counter section
Refer to Timer/Counter section
Refer to UART section
APWMO
BPWMO
Tx
Default state: Pull Low
PWM: Pulse Width Modulation
Refer to the above table, the configuration of IOB2, IOB3, IOB4,
and IOB5 involves feedback function in which an OSC frequency
can be obtained from EXT1 (EXT2) by simply adding a RC circuit
between IOB2 (IOB3) and IOB4 (IOB5).
Initially, write a value of N into a timer and select a desired clock
source, timer will start counting from N, N+1, N+2... through FFFF.
An INT (TimerA/TimerB) signal is generated at the next clock after
reaching “FFFF” and the INT signal is transmitted to INT controller
for further processing. At the same time, N will be reloaded into
timer and start all over again. The clock source A is a high
frequency source and clock source B is a low frequency source.
The combination of clock source A and B provides a variety of
speeds to TimerA. A “1” represents pass signal and not gating.
In contrast, “0” indicates deactivating timer. The EXT1 and EXT2
are the external clock sources. Moreover, counter can generate
time-out signal for input clock source to a four bits (16 levels)
PWM pulse width counter. A variety of clock duration can be
generated and exported from IOB8 (APWMO) and IOB9
(BPWMO).
6.8. Timer/Counter
The GPCE060A provides two 16-bit timers/counters, TimerA and
TimerB. The TimerA is called a universal counter. TimerB is a
general-purpose counter. The clock source of TimerA comes
from the combination of clock source A and clock source B. In
TimerB, the clock source is given from source C. When timer
overflows, an INT signal is sent to CPU to generate a time-out
signal.
Clock of Source A Clock of Source B Clock of Source C
Fosc/2
Fosc/256
32768Hz
8192Hz
4096Hz
1
2048Hz
1024Hz
256Hz
TMB1
4Hz
Fosc/2
Fosc/256
32768Hz
8192Hz
4096Hz
1
The following example is a 3/16-duration cycle. The APWMO
waveform is made by selecting
a
pulse width through
Port_TimerA_Ctrl (W) [9:6]. As a result, each 16 cycles will
generate a pulse width defined in control port. These PWM
signals can be applied for controlling the speed of motor or other
devices.
2Hz
0
1
0
EXT1
EXT2
EXT1
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GPCE060A
TimerA_Timeout
APWMO
Tapwmo
Tduty
6.9.2. Watchdog
Generally speaking, the clock source A and C are fast clock
sources and source B comes from RTC system (32768Hz).
Therefore, clock source B can be utilized as a precise counter for
time counting, e.g., the 2Hz clock can be used for real time
counting.
The purpose of watchdog is to monitor if the system operates
normally. Within a certain period, watchdog must be cleared. If
watchdog is not cleared, CPU assumes the program has been
running in an abnormal condition. As a result, the CPU will reset
the system to the initial state and start running the program all
over again. The watchdog function can be removed by bonding
option. In GPCE060A, the clear period is 0.75 seconds. If
watchdog is cleared within each 0.75 seconds, the system will not
be reset. To clear watchdog, simply write “0bxxxx xxxx xxxx
6.8.1. Timebase
Timebase, generated by 32768Hz, is a combination of frequency
selections. The outputs of timebase block are named to TMB1
and TMB2. TMB1 is frequency for TimerA (Clock source B).
The TMB1 and TMB2 are the sources for Interrupt (IRQ6).
Furthermore, timebases generates additional 2Hz to 4096Hz
interrupt sources (IRQ4 and IRQ5) for Real-Time-Clock (RTC).
xx01” to Port_Watchdog_Clear(W).
The content written to
Port_Watchdog_Clear (W) for watchdog clearance must be
exactly the same as the one illustrated above (0bxxxx xxxx xxxx
xx01). Other values given to the Port_Watchdog_Clear (W) for
watchdog clearance may end up with system reset.
The
TMB2
128Hz
TMB1
8Hz
watchdog function remains enabled during standby mode if the
32768Hz is turned on.
256Hz
16Hz
512Hz
32Hz
6.10. ADC (Analog to Digital Converter) / DAC
1024Hz
64Hz
The GPCE060A has eight channels 10-bit ADC (Analog to Digital
Converter). The function of an ADC is to convert analog signal to
digital signal, e.g. a voltage level into a digital word. The eight
channels of ADC can be seven channels of line-in from IOA [6:0]
or one channel microphone (MIC) input through amplifier and AGC
controller. The MIC amplifier circuit is capable of reducing
common mode noise by transmitting signals through differential
MIC Inputs (MICN, MICP). Moreover, an external resistor can be
applied to adjust microphone gain and time of AGC operating.
The AD needs to select source of line-in before conversion. The
ADC is able to choose the external or internal (=AVDD) top
reference voltage. If constant voltage source is unavailable,
GPCE060A offers a constant voltage 2.0V with 5.0mA driving
ability with a capacitor connected.
Default: 128Hz
Default: 8Hz
6.9. Sleep, Wakeup and Watchdog
6.9.1. Wakeup and sleep
1) Sleep: After power-on reset, IC starts running until a sleep
command occurs. When sleep command is
a
accepted, IC will turn the system clock (PLL) off. After
all, it enters sleep mode.
2) Wakeup: CPU waking up from sleep mode requires a wakeup
signal to turn the system clock (PLL) on. The IRQ
signal makes CPU to complete the wakeup process
and initialization. The key wakeup and interrupt
sources (IRQ1 - IRQ6) can be used for wakeup
sources.
The GPCE060A has two 10-bit D/A with 2.0mA or 3.0mA driving
current for audio outputs, DAC1 and DAC2.
© Generalplus Technology Inc.
Proprietary & Confidential
10
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Version: 1.4
GPCE060A
6.11. Serial interface I/O (SIO)
Serial interface I/O offers one-bit serial interface for
communication. This serial interface is capable of transmitting or
a
receiving data via two I/O pins, IOB0 (SCK) and IOB1 (SDA).
WRITE MODE
write control bit=0
SCK
Ax+1
Ax
Ax-1
A0
Dx+1
Dx
D0
Dx+1
Dx
D0
SDA
SDA
STOP
2nd write P_SIO_Data (W), $701AH
1st write P_SIO_Data (W), $701AH
read control bit = 1
READ MODE
SCK
Ax+1
Ax
Ax-1
A0
Dx+1
Dx
D0
Dx+1
Dx
D0
SDA
SDA
1st Read P_SIO_Data (R), $701AH
STOP
2nd Read P_SIO_DAta (R), $701AH
6.12. UART
UART block provides
a
full-duplex standard interface that
Rx and Tx of UART are shared with IOB7 and IOB10. When
GPCE060A receives and/or transmits a frame of data, the b7
(RxRDY) and/or b6 (TxRDY) in Port_UART_Command2(R) will be
set to “1” and the UART IRQ is activated at the same time.
facilitates the communication with other devices. With this
interface, GPCE can transmit and receive simultaneously. The
maximum baud-rate can be up to 115200bps. This function can
be accomplished by using PortB and Interrupt (UART IRQ). The
start
bit
parity
bit
stop
bit
D0
D1
D2
D3
D4
D5
D6
D7
1-bit Start
8-bit data
1-bit Stop
can be enabled/disable;
also even/odd check
6.13. Audio Algorithm
The following speech types can be used in GPCE060A: PCM,
LOG PCM, SACM_A3200, SACM_S240, SACM_S480,
6.14. Bonding Option Summary
The GPCE060A has the following bonding options:
1). Watchdog function
VDD
SACM_S530, SACM_S720, SACM_A1600, SACM_A2000,
and SACM_A2000_DVR (Digital Voice Recorder). For melody
synthesis, the GPCE060A supports SACM_MS01 (FM) and
SACM_MS02 (wave-table) synthesizers.
WDGOPT
© Generalplus Technology Inc.
Proprietary & Confidential
11
Oct. 01, 2013
Version: 1.4
GPCE060A
7.ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics
Symbol
Ratings
DC Supply Voltage
V+
VIO
VIN
TA
< 4.0V
< 7.0V
PortA/B Pad Supply Voltage
Input Voltage Range
Operating Temperature
Storage Temperature
-0.5V to V+ + 0.5V
0℃ to +60℃
-50℃ to +150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational
conditions see DC Electrical Characteristics.
7.2. DC Characteristics (VDD = 3.3V, VDDIO = 5.5V (PortA & B), TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Operating Voltage
Operating Current
VDD
IOP
2.4
3.3
3.6
V
-
FOSC = 49.152MHz,
-
26
-
mA
AD, DAC disable, no loading
Standby Current
ISTB
VIH
VIL
IOH
IOL
-
-
-
-
-
-
2.0
μA
V
Disable 32KHz crystal
Input High Level
0.7VDDIO
0.3VDDIO
-5.0
-
-
-
-
-
Input Low Level
V
-
Output High Current
Output Low Current
Input Pull-Low Resister
(PA15 :0, PB15 :0)
Input Pull-High Resister
(PA15 :0, PB15 :0)
mA
mA
VOH = 4.0V
VOL = 1.0V
12
RPL
RPH
-
-
110
150
-
-
KΩ
KΩ
VIN = VDDIO
VIN = VSS
7.3. DC Characteristics (VDD = 3.3V, VDDIO = 3.3V (PortA & B), TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Operating Voltage
Operating Current
VDD
IOP
2.4
3.3
3.6
V
-
FOSC = 49.152MHz,
-
26
-
mA
AD, DAC disable, no loading
Standby Current
ISTB
VIH
VIL
IOH
IOL
-
-
-
-
-
-
2.0
μA
V
Disable 32KHz crystal
Input High Level
0.7VDDIO
0.3VDDIO
-2.9
-
-
-
-
-
Input Low Level
V
-
Output High Current
Output Low Current
Input Pull-Low Resister
(PA15 :0, PB15 :0)
Input Pull-High Resister
(PA15 :0, PB15 :0)
mA
mA
VOH = 2.6V
VOL = 0.7V
6.7
RPL
RPH
-
-
175
242
-
-
KΩ
KΩ
VIN = VDDIO
VIN = VSS
© Generalplus Technology Inc.
Proprietary & Confidential
12
Oct. 01, 2013
Version: 1.4
GPCE060A
7.4. DC Characteristics (VDD = 2.7V, VDDIO = 2.7V (PortA & B) , TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Operating Voltage
Operating Current
VDD
IOP
2.4
2.7
3.6
V
-
FOSC = 49.152MHz,
-
17
-
mA
AD, DAC disable, no loading
Standby Current
ISTB
VIH
VIL
IOH
IOL
-
-
-
-
-
-
2.0
μA
V
Disable 32KHz crystal
Input High Level
0.7VDDIO
0.3VDDIO
-1.9
-
-
-
-
-
Input Low Level
V
-
Output High Current
Output Low Current
Input Pull-Low Resister
(PA15 :0, PB15 :0)
Input Pull-High Resister
(PA15 :0, PB15 :0)
mA
mA
VOH = 2.1V
VOL = 0.5V
4.4
RPL
RPH
-
-
230
325
-
-
KΩ
KΩ
VIN = VDDIO
VIN = VSS
7.5. DC Characteristics (VDD = 2.4V, VDDIO = 2.4V (PortA & B) , TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Operating Voltage
Operating Current
VDD
IOP
2.4
2.4
3.6
V
-
FOSC = 49.152MHz,
-
14
-
mA
AD, DAC disable, no loading
Standby Current
ISTB
VIH
VIL
IOH
IOL
-
-
-
-
-
-
2.0
μA
V
Disable 32KHz crystal
Input High Level
0.7VDDIO
0.3VDDIO
-1.5
-
-
-
-
-
Input Low Level
V
-
Output High Current
Output Low Current
Input Pull-Low Resister
(PA15 :0, PB15 :0)
Input Pull-High Resister
(PA15 :0, PB15 :0)
mA
mA
VOH = 1.92V
VOL = 0.48V
3.5
RPL
RPH
-
-
275
395
-
-
KΩ
KΩ
VIN = VDDIO
VIN = VSS
© Generalplus Technology Inc.
Proprietary & Confidential
13
Oct. 01, 2013
Version: 1.4
GPCE060A
7.6. ADC Characteristics (VDD = 3.3V, TA = 25℃)
Unit
Typ.
1.0
Characteristics
Symbol
Unit
Min.
Max.
ADC Power Dissipation for LINE_IN
ADC Power Dissipation for MIC_IN
ADC LINE_IN Input Voltage Range from
IOA[6:0]
IADC
-
-
-
-
mA
mA
1.9
-
VINL (Note 1)
VSS-0.3
-
VDD+0.3
V
ADC Microphone Input Voltage Range
VINM
VSS-0.3
-
-
-
VDD+0.3
VDD+0.3
10
V
V
External ADC Top Voltage
Resolution of ADC
VEXTREF (Note 2)
RESO
2.0
-
bits
Signal-to-Noise Plus Distortion of ADC from
Line In
SINAD (Note 4)
-
56
-
dB
Effective Number of Bit
ENOB (Note 5)
INL
-
-
-
-
-
9.0
-
bits
LSB (Note 3)
LSB
±4.0
±0.5
Integral Non-Linearity of ADC
Differential Non-Linearity of ADC
AD Conversion Rate
-
DNL (Note 6)
FCONV
-
-
-
Fcpu/512
42
Hz
Microphone Amplifier Gain (Note 7)
A MIC
dB
Note1: Internal protection diodes clamp the analog input to VDD and VSS. These diodes allow the analog input to swing from (VSS-0.3V) to (VDD+0.3V)
without causing damages to the devices.
Note2: The ADC performance is limited by the system noise level and therefore, the GPCE060A only guarantees to the 8-bit accuracy when VEXTREF is 2.0V.
Note3: The LSB means Least Significant Bit. VINL = 2.0V, 1LSB = 2.0V/2^10 = 1.953mV.
Note4: The SINAD testing condition at VINLp-p = 0.8*VDD, FCONV = Fcpu/512 = 49MHz/512 = 95KHz, Fin=1.0KHz Sine waves at VDD = 3.0V from the IOA
[6:0] input.
Note5: ENOB = (SINAD-1.76)/6.02.
Note6: The ADC of GPCE060A guarantees no data missed during conversion.
Note7: The microphone amplifier maximum gain = 15 * (60K/(1.5K+REXT) V/V. The REXT is external resistor between OPI and MICOUT. The gain is 132V/V
(=42dB) when REXT is 5.1K.
7.7. DAC Characteristics (TA = 25℃)
Unit
Characteristics
DAC resolution
Test condition
VDD = 3.3V
Symbol
Unit
Min.
Typ.
-
Max.
RESO
SNR
FS
-
-
-
-
-
10
bit
dB
Hz
Signal to Noise Ratio of DAC
Sample Rate
VDD = 3.3V
54
-
-
VDD = 3.3V
100K
Output DAC current
(AUD1, AUD2)
VDD = 3.0V (2.0mA mode)
VDD = 3.0V (3.0mA mode)
2.0
3.0
-
-
IAUD
mA
© Generalplus Technology Inc.
Proprietary & Confidential
14
Oct. 01, 2013
Version: 1.4
GPCE060A
7.8. Pull High Resister and VDDIO
7.10. Pull Low Resister and VDDIO
300
500
400
300
200
100
0
200
100
0
2.4
3.4
4.4
2.4
2.9
3.4
3.9
4.4
4.9
VDD (V)
VDDIO(V)
IO
7.9. I/O Output High Current IOH and VOH
7.11. I/O Output Low Current IOL and VOL
15
10
5
25
20
15
10
5
0
0
0.5
1.5
2.5
3.5
4.5
4.5
0.5
1.5
2.5
VOL(V)
3.5
VOH (V)
© Generalplus Technology Inc.
Proprietary & Confidential
15
Oct. 01, 2013
Version: 1.4
GPCE060A
8. APPLICATION CIRCUITS
8.1. Application Circuit - (1)
Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
© Generalplus Technology Inc.
Proprietary & Confidential
16
Oct. 01, 2013
Version: 1.4
GPCE060A
8.2. Application Circuit - (2)
Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
© Generalplus Technology Inc.
Proprietary & Confidential
17
Oct. 01, 2013
Version: 1.4
GPCE060A
8.3. Application Circuit - (3)
Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
© Generalplus Technology Inc.
Proprietary & Confidential
18
Oct. 01, 2013
Version: 1.4
GPCE060A
8.4. Application Circuit - (4)
Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
© Generalplus Technology Inc.
Proprietary & Confidential
19
Oct. 01, 2013
Version: 1.4
GPCE060A
8.5. Application Circuit - (5)
Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
© Generalplus Technology Inc.
Proprietary & Confidential
20
Oct. 01, 2013
Version: 1.4
GPCE060A
8.6. Application Circuit - (6)
Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
© Generalplus Technology Inc.
Proprietary & Confidential
21
Oct. 01, 2013
Version: 1.4
GPCE060A
9. PACKAGE/PAD LOCATIONS
9.1. Ordering Information
Product Number
Package Type
Chip form
Green Package form - LQFP 80
GPCE060A-NnnV-C
GPCE060A-NnnV-HL04n-W
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
Note3: HL04n-W, HL04 is assign for LQFP80, n is assign for customer, W is watch dog bonding option (W=0 enable, W=1 disable).
9.2. Package information
9.2.1. LQFP 80
D
D1
E
E1
e
b
A2
A1
A
c
L1
Dimension in inch
Symbol
Min.
-
Typ.
Max.
0.063
0.006
0.057
0.011
0.008
A
A1
A2
b
-
-
0.002
0.053
0.007
0.004
0.055
0.009
c
-
D
0.551 BSC.
0.472 BSC.
0.551 BSC.
D1
E
© Generalplus Technology Inc.
Proprietary & Confidential
22
Oct. 01, 2013
Version: 1.4
GPCE060A
Dimension in inch
Typ.
Symbol
Min.
Max.
E1
e
0.472 BSC.
0.020 BSC.
0.039 REF
L1
PAD No.
PAD Name
PAD No.
PAD Name
1
X32O
X32I
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
IOA8
N/C
2
3
TEST
N/C
N/C
4
IOA9
IOA10
IOA11
IOA12
IOA13
IOA14
IOA15
N/C
5
VDD
6
N/C
7
N/C
8
VSS
9
N/C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
VSS
N/C
DAC1
DAC2
V2VREF
AVSS
AGC
N/C
VSSIO
N/C
SLEEP
IOB15
IOB14
IOB13
IOB12
IOB11
NC
OPI
MICOUT
MICN
N/C
MICP
VADREF
VEXTREF
AVDD
VMIC
N/C
N/C
N/C
IN/C
VDDIO
IOB10
IOB9
IOB8
IOB7
IOB6
IOB5
IOB4
IOB3
IOB2
IOB1
IOB0
RESET
VSS
IOA0
IOA1
IOA2
IOA3
IOA4
IOA5
IOA6
IOA7
VSSIO
VSSIO
VDDIO
VDDIO
N/C
VDD
© Generalplus Technology Inc.
Proprietary & Confidential
23
Oct. 01, 2013
Version: 1.4
GPCE060A
PAD No.
PAD Name
PAD No.
PAD Name
79
VCOIN
80
VSS
© Generalplus Technology Inc.
Proprietary & Confidential
24
Oct. 01, 2013
Version: 1.4
GPCE060A
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
Proprietary & Confidential
25
Oct. 01, 2013
Version: 1.4
GPCE060A
11. REVISION HISTORY
Date
Revision #
Description
Page
OCT. 01, 2013
OCT. 12, 2010
MAY 23, 2008
JUL. 05, 2006
1.4
1.3
1.2
1.1
Add COMAIR logo to the cover page
Modify 3. FEATURES
4
16-21
21
Modify 8. APPLICATION CIRCUITS.
1. Modify the 9.2 Ordering Information.
2. Delete the 9.3.2 PLCC84.
24
3. Modify the 8. APPLICATION CIRCUITS.
Original
15-20
27
DEC. 09, 2005
1.0
Note: The GPCE060A data sheet v1.0 is a continued version of SPCE060A data sheet v0.5.
© Generalplus Technology Inc.
Proprietary & Confidential
26
Oct. 01, 2013
Version: 1.4
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