GPCE061A [GENERALPLUS]
16-Bit Sound Controller With 32K X 16 Fla sh Memory;
| 型号： | GPCE061A |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 16-Bit Sound Controller With 32K X 16 Fla sh Memory |
| 文件： | 总29页 (文件大小：2555K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPCE061A
16-Bit Sound Controller With
32K X 16 Flash Memory
OCT. 01, 2013
Version 1.5
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPCE061A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 4
2. BLOCK DIAGRAM ...................................................................................................................................................................................... 4
3. FEATURES.................................................................................................................................................................................................. 4
4. APPLICATION FIELD.................................................................................................................................................................................. 4
5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5
5.1. PAD ASSIGNMENT ................................................................................................................................................................................. 6
6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 7
6.1. CPU ..................................................................................................................................................................................................... 7
6.2. MEMORY ............................................................................................................................................................................................... 7
6.2.1. SRAM........................................................................................................................................................................................ 7
6.2.2. Flash memory ........................................................................................................................................................................... 7
6.3. PLL, CLOCK, POWER MODE................................................................................................................................................................... 7
6.3.1. PLL (Phase Lock Loop)............................................................................................................................................................. 7
6.4. STANDBY MODE..................................................................................................................................................................................... 7
6.5. LOW VOLTAGE DETECTION AND LOW VOLTAGE RESET............................................................................................................................. 8
6.5.1. Low voltage detection (LVD) ..................................................................................................................................................... 8
6.5.2. Low voltage reset...................................................................................................................................................................... 8
6.6. INTERRUPT............................................................................................................................................................................................ 8
6.7. I/O........................................................................................................................................................................................................ 8
6.8. TIMER / COUNTER.................................................................................................................................................................................. 9
6.8.1. Timebase ................................................................................................................................................................................ 10
6.9. SLEEP, WAKEUP AND WATCHDOG ......................................................................................................................................................... 10
6.9.1. Wakeup and sleep .................................................................................................................................................................. 10
6.9.2. Watchdog................................................................................................................................................................................ 10
6.10.ADC (ANALOG TO DIGITAL CONVERTER) / DAC .................................................................................................................................... 10
6.11.SERIAL INTERFACE I/O (SIO).................................................................................................................................................................11
6.12.UART ..................................................................................................................................................................................................11
6.13.AUDIO ALGORITHM................................................................................................................................................................................11
6.14.IDE TOOLS FUNCTION ..........................................................................................................................................................................11
6.15.BONDING OPTION SUMMARY ................................................................................................................................................................ 12
6.15.1. Watchdog function.............................................................................................................................................................. 12
6.16.SECURITY FUNCTION ........................................................................................................................................................................... 12
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 13
7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 13
7.2. DC CHARACTERISTICS (VDD = 3.6V, VDDIO = 3.6V (PORTA & B), TA = 25℃) ....................................................................................... 13
7.3. DC CHARACTERISTICS (VDD = 3.3V, VDDIO = 5.5V (PORTA & B), TA = 25℃) ....................................................................................... 14
7.4. DC CHARACTERISTICS (VDD = 3.3V, VDDIO = 3.3V (PORTA & B), TA = 25℃) ....................................................................................... 14
7.5. ADC CHARACTERISTICS (VDD = 3.3V, TA = 25℃)................................................................................................................................ 15
7.6. V2VREF REGULATOR CHARACTERISTICS (VDD = 3.3V, TA = 25℃) ...................................................................................................... 15
7.7. DAC CHARACTERISTICS (VDD = 3.3V, TA = 25℃)................................................................................................................................ 15
7.8. PULL HIGH RESISTER AND VDDIO ......................................................................................................................................................... 16
7.9. I/O OUTPUT HIGH CURRENT IOH AND VOH .............................................................................................................................................. 16
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Version: 1.5
GPCE061A
7.10.PULL LOW RESISTER AND VDDIO.......................................................................................................................................................... 16
7.11.I/O OUTPUT LOW CURRENT IOL AND VOL ............................................................................................................................................... 16
7.12.DAC OUTPUT CURRENT VS. VDD (2MA MODE WITH 500HM RESISTOR) .................................................................................................. 16
7.13.DAC OUTPUT CURRENT VS. VDD (3MA MODE WITH 500HM RESISTOR) .................................................................................................. 16
8. APPLICATION CIRCUITS......................................................................................................................................................................... 17
8.1. APPLICATION CIRCUIT - (1)................................................................................................................................................................... 17
8.2. APPLICATION CIRCUIT - (2)................................................................................................................................................................... 18
8.3. APPLICATION CIRCUIT - (3)................................................................................................................................................................... 19
8.4. APPLICATION CIRCUIT - (4)................................................................................................................................................................... 20
8.5. APPLICATION CIRCUIT - (5)................................................................................................................................................................... 21
8.6. APPLICATION CIRCUIT - (6)................................................................................................................................................................... 22
8.7. APPLICATION CIRCUIT - (7)................................................................................................................................................................... 23
9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 24
9.1. ORDERING INFORMATION ..................................................................................................................................................................... 24
9.2. PACKAGE INFORMATION ....................................................................................................................................................................... 24
9.2.1. LQFP 80.................................................................................................................................................................................. 24
10.TABLE OF GPCE061/060/040 COMPARISON......................................................................................................................................... 27
11. DISCLAIMER............................................................................................................................................................................................. 28
12.REVISION HISTORY ................................................................................................................................................................................. 29
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Oct. 01, 2013
Version: 1.5
GPCE061A
16-BIT SOUND CONTROLLER
WITH 32K X 16 FLASH MEMORY
1. GENERAL DESCRIPTION
3. FEATURES
The GPCE061A, a 16-bit architecture product, carries the newest
16-bit microprocessor, μ’nSP™ (pronounced as micro-n-SP),
developed by Sunplus Technology. This high processing speed
assures the μ’nSP™ is capable of handling complex digital signal
processes easily and rapidly. Therefore, the GPCE061A is
applicable to the areas of digital sound process and voice
recognition. The operating voltage of 3.0V through 3.6V and
speed of 0.32MHz through 49.152MHz yield the GPCE061A to be
easily used in varieties of applications. The memory capacity
includes 32K-word flash memory plus a 2K-word working SRAM.
Other features include 32 programmable multi-functional I/Os, two
16-bit timers/counters, 32768Hz Real Time Clock, Low Voltage
Reset/Detection, eight channels 10-bit ADC (one channel built-in
MIC amplifier with auto gain controller), 10-bit DAC output and
many others.
16-bit μ’nSP™ microprocessor
CPU clock: 0.32MHz - 49.152MHz
Operating voltage: 3.0V - 3.6V
Program Flash Operating voltage: 3.0V - 3.6V
IO PortA & B operating voltage: 3.0V - 5.5V
32K-word flash memory
2K-word working SRAM
Software-based audio processing
Crystal Resonator
Standby mode (Clock Stop mode) for power savings,
Max. 2.0μA @ VDD = 3.6V
Two 16-bit timers/counters
Two 10-bit DAC outputs
32 general I/Os (bit programmable)
14 INT sources with two priority levels
Key wakeup function (IOA0 - 7)
PLL feature for system clock
2. BLOCK DIAGRAM
32768Hz Real Time Clock (RTC)
Eight channels 10-bit AD converter
ADC external top reference voltage
2.0V voltage regulator output, 5mA of driving capability
Serial interface I/O (SIO)
16-bit
16-bit Timer/Counter
FLASH
RAM
ICE
ICECLK
ICESDA
SLEEP
RESET
u'nSP
and
ICE
x 2
TimerBase
INT control
controller
VMIC
VEXTREF
VADREF
AGC
MICOUT
MICP
CPU
Clock
VCOIN
Built-in microphone amplifier and AGC function
UART receiver and transmitter (full duplex)
Low voltage reset and low voltage detection
Watchdog enable (bonding option)
ICE function for development and down load into flash memory
Security function to protect code to be read and written.
10-bit A/D
& AGC
PLL
X32I
X32O
RTC
MICN
OPI
LVD/LVR
WATCHDOG
AUD1
AUD2
10-bit DAC1 Output
10-bit DAC2 Output
UART
SIO
IOB7 (Rx)
IOB10 (Tx)
IOB1 (SDA)
IOB0 (SCK)
32 PIN GENERAL I/O PORT
IOA15 - 0
IOB15 - 0
4. APPLICATION FIELD
Voice recognition products
Intelligent interactive talking toys
Advanced educational toys
Kids learning products
Kids storybook
General speech synthesizer
Long duration audio products
Recording / playback products
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Version: 1.5
GPCE061A
5. SIGNAL DESCRIPTIONS
Mnemonic
PIN No.
Type
Description
IOA [15:8]
IOA [7:0]
46 - 39
34 - 27
I/O
I/O
IOA [15:8]: bi-directional I/O ports.
IOA [7:0] can be software programmed to wakeup I/O pins.
IOA [6:0] can be optioned as ADC Line-in input.
IOB [15:11]: bi-directional I/O ports.
IOB [15:11]
IOB 10
IOB 9
IOB 8
IOB 7
IOB 6
IOB 5
IOB 4
IOB 3
IOB 2
IOB 1
IOB 0
DAC1
DAC2
X32I
50 - 54
57
58
59
60
61
62
63
64
65
66
67
12
13
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
IOB10 can also be selected as UART Transmitter (Tx).
IOB9 can also be Multi-duty cycle output of TimerB (BPWMO).
IOB8 can also be Multi-duty cycle output of TimerA (APWMO).
IOB7 can also be selected as UART receiver (Rx).
IOB6 is a bi-directional I/O ports.
IOB5 can also be selected as feedback signal with EXT2.
IOB4 can also be selected as feedback signal with EXT1.
IOB3 can also be selected as an external interrupt input pin (EXT2)(Negative-edge Triggered).
IOB2 can also be selected as an external interrupt input pin (EXT1)(Negative-edge Triggered).
IOB1 can also be selected as a serial interface data (SDA).
IOB0 can also be selected as a serial interface clock (SCK).
Audio DAC1 output.
O
Audio DAC2 output.
I
Oscillator Crystal input.
X32O
VCOIN
AGC
1
O
Oscillator Crystal output.
70
16
19
21
14
I
RC filter connection for PLL.
I
AGC control pin.
MICN
MICP
I
Microphone differential input (negative).
Microphone differential input (positive).
I
V2VREF
O
2.0V output voltage, 5.0mA of driving capability (can be used as external ADC Line_IN top
reference voltage).
MICOUT
OPI
18
O
Microphone 1st amplifier output.
Microphone 2nd amplifier input.
17
I
VEXTREF
VMIC
23
I
ADC Line_IN top external reference voltage input pin.
Microphone power supply.
25
O
VADREF
VDD
22
O
AD reference voltage (generated by internal AD converter).
Positive supply for logic.
5, 69
I
VSS
10, 26, 71
I
Ground reference for logic and I/O pins.
Positive supply for I/O pins.
VDDIO
VSSIO
AVDD
37, 38, 56
I
35, 36, 48
I
Ground reference for I/O pins.
24
15
68
49
7
I
Positive supply for analog circuit including ADC, DAC and 2.0V regulator.
Ground reference for analog circuit including ADC, DAC and 2.0V regulator.
An active low reset to the chip.
AVSS
I
RESET
I
O
I
SLEEP
ICE
Sleep mode (active high).
ICE enable (active high).
ICECLK
ICESDA
TEST
8
I
ICE serial interface clock.
9
I/O
I
ICE serial interface data.
3
Connected to high for test mode, normally connected to GND (test mode disabled) or
unconnected.
ROMT
47
I
Flash memory test, normally unconnected.
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GPCE061A
Mnemonic
N/C
PIN No.
Type
Description
55
4
I
I
I
I
Not used.
N/C
Do NOT bonding and connect this pin. If user bonding this pin, IC will not work.
Bonded for watchdog disabled, unbonded for watchdog enabled.
Security fuse.
WDGOPT*
PFUSE, PVIN
6
20, 11
Note*: WDGOPT is the watchdog option pin, selected by bonding option. Remain WDGOPT unbonded to enable the watchdog.
In contrast, bonding this pad will disable watchdog. The reason of placing WDTOPT adjacent to VDD is to facilitate
connection between VDD and WDGOPT when disabling watchdog is necessary.
VDD
WDGOPT
5.1. PAD Assignment
71 70 69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
1
2
X32O
X32I
54
53
52
51
50
49
48
47
46
45
44
43
42
IOB11
IOB12
IOB13
IOB14
3
TEST
4
5
6
N/C
VDD
WDGOPT
IOB15
7
ICE
ICECLK
ICESDA
VSS
SLEEP
8
(0,0)
9
VSSIO
ROMT
10
11
12
13
14
15
16
17
18
19
20
PVIN
IOA15
IOA14
DAC1
DAC2
V2VREF
AVSS
IOA13
IOA12
AGC
IOA11
OPI
41
40
IOA10
IOA9
MICOUT
MICN
PFUSE
21 22 23 24 25
26 27 28 29 30 31 32 33 34
35 36 37
38 39
This IC substrate should be connected to VSS
Note1: To ensure the IC functions properly, please bond all of VDD and VSS pins.
Note2: The 0.1μF capacitor between VDD and VSS should be placed to IC as closed as possible.
Note3: Do NOT bonding and connect N/C pin. If user bonding N/C pin, IC will not work.
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GPCE061A
6.FUNCTIONAL DESCRIPTIONS
6.1. CPU
The GPCE061A is equipped with a 16-bit μ’nSP™, the newest
16-bit microprocessor by Sunplus and pronounced as micro-n-SP.
Eight registers are involved in μ’nSP™: R1 - R4 (General-purpose
registers), PC (Program Counter), SP (Stack Pointer), Base
Pointer (BP) and SR (Segment Register). The interrupts include
three FIQs (Fast Interrupt Request) and eight IRQs (Interrupt
Request), plus one software-interrupt, BREAK.
Moreover,
a
high performance hardware multiplier with the
capability of FIR filter is also built in to reduce the software
multiplication loading.
6.2. Memory
6.2.1. SRAM
The amount of SRAM is 2K-word (including Stack), ranged from
$0000 through $07FF with access speed of two CPU clock cycles.
Phase Lock Loop
Fosc/n
CPU Clock
FOSC
32768Hz X'tal
(PLL)
PLL OUT
24.576MHz(default)
20.48MHz
System Clock generator
n:1,2,4,8,16,32,64
(Default : Fosc/8)
32.768MHz
40.96MHz
49.152MHz
b2 b1 b0
b7
b6 b5
b7,b6,b5 of P_SystemClock(W)($7013H)
System clock frequency selection
of P_SystemClock(W)($7013H)
CPU clock frequency selection
6.2.2. Flash memory
Flash memory ($008000 ~ $00FFFF) is a high-speed memory with
access speed of two CPU clock cycles. FLASH erase and
program functions must be used in IDE tools.
wake CPU up whenever RTC occurs.
Since the RTC is
generated each 0.5 seconds, time can be traced by the numbers
of RTC occurrence. In addition, GPCE061A supports 32768Hz
oscillator in normal mode and auto-power-saving mode. In
normal mode, 32768Hz OSC always runs at the highest power
consumption. In auto-power-saving mode, however, it runs in
normal mode for the first 7.5 seconds and changes back to
power-saving mode automatically to save powers.
6.3. PLL, Clock, Power Mode
6.3.1. PLL (Phase Lock Loop)
The purpose of PLL is to provide a base frequency (32768Hz) and
to pump the frequency from 20.48MHz to 49.152MHz for system
clock (FOSC). The default PLL frequency is 24.576MHz.
6.4. Standby Mode
The GPCE061A also offers a standby mode for low power
application needs. To enter standby mode, the desired key
wakeup port (IOA [7:0]) must be configured to input first. And
read the Port_IOA_Latch(R) to latch the IOA state before entering
the standby mode. Also remember to enable the corresponding
interrupt source(s) for wakeup. After that, stop the CPU clock by
writing the STOP CLOCK Register (b0~b2 of Port_SystemClock
(W)) to enter standby mode. In such mode, SRAM and I/Os
remain in the previous states till CPU being awoken. The
wakeup sources in GPCE061A include Port IOA7 - 0 and IRQ1 -
IRQ6. After GPCE061A is awoken, the CPU will continue to
execute the program. Programmer can also enable or disable
the 32768Hz OSC when CPU is in standby mode.
6.3.1.1. System clock
Basically, the system clock is provided by PLL and programmed
by the Port_SystemClock (W) to determine the frequency of clock
for system. The default system clock FOSC = 24.576MHz and
CPU clock is Fosc/8 if not specified. The initial CPU clock is
Fosc/8 after system wakes up and to be adjusted to desired CPU
clock by programming the Port_SystemClock (W). This avoids
Flash ROM reading failure when system wakes up.
6.3.1.2. 32768Hz RTC
The Real Time Clock (RTC) is normally used in watch, clock or
other time related products. A 2Hz-RTC (1/2 second) function is
loaded in GPCE061A. The RTC counts the timing as well as to
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Version: 1.5
GPCE061A
6.5. Low Voltage Detection and Low Voltage Reset
6.5.1. Low voltage detection (LVD)
Interrupt Source
Key change wakeup
4096Hz
Interrupt Name
Priority
Low
Low
Low
Low
Low
Low
Low
Low
Low
IRQ3_KEY
IRQ4_4KHz
IRQ4_2KHZ
IRQ4_1KHz
IRQ5_4Hz
There are two LVD levels to be selected: 2.9V, and 3.3V. These
levels can be programmed via Port_LVD_Ctrl (W). As an
example, suppose LVD is given to 2.9V. When the voltage drops
below 2.9V, the b15 of Port_LVD_Ctrl is read as HIGH. In such
state, program can be designed to react to this condition.
2048Hz
1024Hz
4Hz
2Hz
IRQ5_2Hz
Time-base 1
Time-base 2
UART (TxRDY or RxRDY)
IRQ6_TMB1
IRQ6_TMB2
UART IRQ
6.5.2. Low voltage reset
In addition to the LVD, the GPCE061A has another important
function, Low Voltage Reset (LVR). With the LVR function, a
reset signal is generated to reset system when the operating
voltage drops below 2.3V for 10 consecutive CPU clock cycles.
Without LVR, the CPU becomes unstable and malfunctions when
the operating voltage drops below 2.3V. The LVR will reset all
functions to the initial operational (stable) states when the voltage
drops below 2.3V. A LVR timing diagram is given as follows:
6.7. I/O
Two I/O ports are built in GPCE061A, PortA and PortB. The
PortA is an ordinary I/O with programmable wakeup capability. In
addition to the regular IO function, the PortB can also perform
some special functions in certain pins. Suppose operating
voltage is running at 3.6V (VDD) and VDDIO (power for I/O)
operates from 3.6V (VDD) to 5.5V. In such condition, the I/O pad
is capable of operating from 0V through VDDIO. However IOB13
and IOB14 are recommended to operate <=3.6V during standby
mode, otherwise these two IOs will have current leakage. The
following diagram is an I/O schematic.
FCPU
VDD
2.3V
Tw
Tvdd
Buffer(R)
RESET
Treset
Tw=FCPU x 10 cycle
Port_Data(W)
Tvdd > Tw
Treset = FCPU x512 cycle
Register
pull high
pull low
Port_Buffer(W)
Port_DIR(R/W)
Port_ATTR(R/W)
Pin pad
Control
logic
6.6. Interrupt
The GPCE061A has 14 interrupt sources, grouped into two types,
FIQ (Fast Interrupt Request) and IRQ (Interrupt request). The
priority of FIQ is higher than IRQ. FIQ is the high-priority interrupt
while IRQ is the low-priority one. An IRQ can be interrupted by a
FIQ, but not by another IRQ. A FIQ cannot be interrupted by any
other interrupt sources.
Data(R)
Although data can be written into the same register through
Port_Data and Port_Buffer, they can be read from different places,
Buffer (R) and Data (R). The IOA [7:0] is the key wakeup port.
To activate key wakeup function, latch data on PORT_IOA_Latch
and enable the key wakeup function. Wakeup is triggered when
the PortA state is different from at the time latched. In addition to
Interrupt Source
Interrupt Name
Priority
PWM Service (Fosc/1024) FIQ_PWM/IRQ0_PWM High(FIQ)
Timer A
Timer B
EXT2
FIQ_TMA/ IRQ1_TMA High(FIQ)
FIQ_TMB/ IRQ2_TMB High(FIQ)
an ordinary I/O port, PortB carries some special functions.
summary of PortB special functions is listed as follows:
A
IRQ3_EXT2
IRQ3_EXT1
Low
Low
EXT1
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GPCE061A
Special function in PortB
PortB
IOB0
IOB1
IOB2
Special Function
Function Description
Serial interface clock
Note
Refer to see SIO section
SCK
SDA
EXT1
Serial interface data
Refer to see SIO section
IOB2 set as input mode
External interrupt source 1(Negative-edge Triggered)
Feedback Output1 Works with IOB4 by adding a RC circuit between IOB2 set as inverted output
them to get an OSC to EXT1 interrupt
IOB3
EXT2
External interrupt source 2(Negative-edge Triggered)
IOB3 set as input mode
Feedback Output2 Works with IOB5 by adding a RC circuit between IOB3 set as inverted output
them to get an OSC to EXT2 interrupt
IOB4
IOB5
IOB7
IOB8
IOB9
IOB10
Feedback Input1
Feedback Input2
Rx
-
-
-
-
UART Receiver
TimerA PWM output
TimerB PWM output
UART Transmitter
Refer to see UART section
Refer to Timer/Counter section
Refer to Timer/Counter section
Refer to UART section
APWMO
BPWMO
Tx
Default state: Pull Low
PWM: Pulse Width Modulation
Refer to the above table, the configuration of IOB2, IOB3, IOB4,
and IOB5 involves feedback function in which an OSC frequency
can be obtained from EXT1 (EXT2) by simply adding a RC circuit
between IOB2 (IOB3) and IOB4 (IOB5).
Initially, write a value of N into a timer and select a desired clock
source, timer will start counting from N, N+1, N+2, ... through
FFFF. An INT (TimerA/TimerB) signal is generated at the next
clock after reaching “FFFF” and the INT signal is transmitted to
INT controller for further processing. At the same time, N will be
reloaded into timer and start all over again. The clock source A is
a high frequency source and clock source B is a low frequency
source. The combination of clock source A and B provides a
variety of speeds to TimerA. A “1” represents pass signal and not
gating. In contrast, “0” indicates deactivating timer. The EXT1
and EXT2 are the external clock sources. Moreover, counter can
generate time-out signal for input clock source to a four bits (16
levels) PWM pulse width counter. A variety of clock duration can
be generated and exported from IOB8 (APWMO) and IOB9
(BPWMO).
6.8. Timer / Counter
The GPCE061A provides two 16-bit timers/counters, TimerA and
TimerB. The TimerA is called a universal counter. TimerB is a
general-purpose counter. The clock source of TimerA comes
from the combination of clock source A and clock source B. In
TimerB, the clock source is given from source C. When timer
overflows, an INT signal is sent to CPU to generate a time-out
signal.
Clock of Source A Clock of Source B Clock of Source C
Fosc/2
Fosc/256
32768Hz
8192Hz
4096Hz
1
2048Hz
1024Hz
256Hz
TMB1
4Hz
Fosc/2
Fosc/256
32768Hz
8192Hz
4096Hz
1
The following example is a 3/16-duration cycle. The APWMO
waveform is made by selecting
a
pulse width through
Port_TimerA_Ctrl (W) [9:6]. As a result, each 16 cycles will
generate a pulse width defined in control port. These PWM
signals can be applied for controlling the speed of motor or other
devices.
2Hz
0
1
0
EXT1
EXT2
EXT1
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GPCE061A
TimerA_Timeout
APWMO
Tapwmo
Tduty
6.9.2. Watchdog
Generally speaking, the clock source A and C are fast clock
sources and source B comes from RTC system (32768Hz).
Therefore, clock source B can be utilized as a precise counter for
time counting, e.g., the 2Hz clock can be used for real time
counting.
The purpose of watchdog is to monitor if the system operates
normally. Within a certain period, watchdog must be cleared. If
watchdog is not cleared, CPU assumes the program has been
running in an abnormal condition. As a result, the CPU will reset
the system to the initial state and start running the program all
over again. The watchdog function can be removed by bonding
option. In GPCE061A, the clear period is 0.75 seconds. If
watchdog is cleared within each 0.75 seconds, the system will not
be reset. To clear watchdog, simply write “xxxx xxxx xxxx xx01B”
6.8.1. Timebase
Timebase, generated by 32768Hz, is a combination of frequency
selections. The outputs of timebase block are named to TMB1
and TMB2. TMB1 is frequency for TimerA (Clock source B).
The TMB1 and TMB2 are the sources for Interrupt (IRQ6).
Furthermore, timebases generates additional 2Hz to 4096Hz
interrupt sources (IRQ4 and IRQ5) for Real-Time-Clock (RTC).
to
Port_Watchdog_Clear(W).
The
content
written
to
Port_Watchdog_Clear(W) for watchdog clearance must be exactly
the same as the one illustrated above (xxxx xxxx xxxx xx01B).
Other values given to the Port_Watchdog_Clear(W) for watchdog
clearance may end up with system reset. The watchdog function
remains enabled during standby mode if the 32768Hz is turned
on.
TMB2
128Hz
TMB1
8Hz
256Hz
16Hz
512Hz
32Hz
6.10. ADC (Analog to Digital Converter) / DAC
1024Hz
64Hz
The GPCE061A has eight channels 10-bit ADC (Analog to Digital
Converter). The function of an ADC is to convert analog signal to
digital signal, e.g. a voltage level into a digital word. The eight
channels of ADC can be seven channels of line-in from IOA [6:0]
or one channel microphone (MIC) input through amplifier and AGC
controller. The MIC amplifier circuit is capable of reducing
common mode noise by transmitting signals through differential
MIC Inputs (MICN, MICP). Moreover, an external resistor can be
applied to adjust microphone gain and time of AGC operating.
The AD needs to select source of line-in before conversion. The
ADC is able to choose the external or internal (=AVDD) top
reference voltage. If constant voltage source is unavailable,
GPCE061A offers a constant voltage 2.0V with 5.0mA driving
ability with a capacitor connected.
Default: 128Hz
Default: 8Hz
6.9. Sleep, Wakeup and Watchdog
6.9.1. Wakeup and sleep
1) Sleep: After power-on reset, IC starts running until a sleep
command occurs. When sleep command is
a
accepted, IC will turn the system clock (PLL) off. After
all, it enters sleep mode.
2) Wakeup: CPU waking up from sleep mode requires a wakeup
signal to turn the system clock (PLL) on. The IRQ
signal makes CPU to complete the wakeup process
and initialization. The key wakeup and interrupt
sources (IRQ1 - IRQ6) can be used for wakeup
sources.
The GPCE061A has two 10-bit D/A with 2.0mA or 3.0mA driving
current for audio outputs, DAC1 and DAC2.
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GPCE061A
6.11. Serial Interface I/O (SIO)
Serial interface I/O offers one-bit serial interface for
communication. This serial interface is capable of transmitting or
a
receiving data via two I/O pins, IOB0 (SCK) and IOB1 (SDA).
WRITE MODE
write control bit=0
SCK
Ax+1
Ax
Ax-1
A0
Dx+1
Dx
D0
Dx+1
Dx
D0
SDA
SDA
STOP
2nd write P_SIO_Data (W), $701AH
1st write P_SIO_Data (W), $701AH
read control bit = 1
READ MODE
SCK
Ax+1
Ax
Ax-1
A0
Dx+1
Dx
D0
Dx+1
Dx
D0
SDA
SDA
1st Read P_SIO_Data (R), $701AH
STOP
2nd Read P_SIO_DAta (R), $701AH
6.12. UART
UART block provides
a
full-duplex standard interface that
Rx and Tx of UART are shared with IOB7 and IOB10. When
GPCE061A receives and/or transmits a frame of data, the b7
(RxRDY) and/or b6 (TxRDY) in Port_UART_Command2(R) will be
set to “1” and the UART IRQ is activated at the same time.
facilitates the communication with other devices. With this
interface, GPCE can transmit and receive simultaneously. The
maximum baud-rate can be up to 115200bps. This function can
be accomplished by using PortB and Interrupt (UART IRQ). The
start
bit
parity
bit
stop
bit
D0
D1
D2
D3
D4
D5
D6
D7
1-bit Start
8-bit data
1-bit Stop
can be enabled/disable;
also even/odd check
6.13. Audio Algorithm
The following speech types can be used in GPCE061A: PCM,
SACM_S200, SACM_S480, SACM_S530, SACM_S720,
6.14. IDE Tools Function
The functions of IDE include the follows:
1). C compiler, Assembly, and Linker.
SACM_A1600, SACM_A1601, SACM_A3600, SACM_DVR520,
SACM_DVR1600, SACM_DVR3200, and SACM_DVR4800. For
melody synthesis, the GPCE061A supports SACM_MS01 (FM)
and SACM_MS02 (wave-table) synthesizers.
2). Download program into FLASH (refer to 8.7.application
circuit-(7)).
3). Single step trace
4). Break point (break point for debugging)
5). Run (execute)
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GPCE061A
6.15. Bonding Option Summary
6.16. Security Function
The GPCE061A has the following bonding option:
Security function is able to protect code to be read or written.
When program is downloaded into flash memory, program can be
read/written from IDE tools. For security purpose, burn fuse to
disable IDE function, where PFUSE supplies 7.0V and PVIN
connects to ground (0V) about one second (Please refer to the
following circuit diagram). After all, the flash memory can no
longer be read or written.
6.15.1. Watchdog function
WDGOPT is the optional pin for watchdog by bonding option.
The shape looks as the figure given below. When watchdog is
selected, WDGOPT is unbonded. If watchdog is not selected,
WDGOPT is bonded. The reason for WDGOPT adjacent to VDD
is that when watchdog is not selected, it is easy to make the
connection between VDD and WDGOPT.
VDD
WDGOPT
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GPCE061A
7.ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics
Symbol
Ratings
DC Supply Voltage
V+
VDDIO
VIN
< 4.0V
< 7.0V
PortA/B Pad Supply Voltage
Input Voltage Range
Operating Temperature
Storage Temperature
-0.5V to V+ + 0.5V
0℃ to +60℃
TA
-50℃ to +150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational
conditions see DC Electrical Characteristics.
7.2. DC Characteristics (VDD = 3.6V, VDDIO = 3.6V (PortA & B), TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Operating Voltage
Operating Current
VDD
IOP
3.0
3.3
3.6
V
-
FOSC = 49.152MHz,
-
-
-
-
33
mA
AD, DAC disable, no load
2.0
5.0
Disable 32KHz crystal
Standby Current
ISTB
μA
Enable 32Khz, Disable PLL (FOSC
)
Input High Level
Input Low Level
Output DAC current
(AUD1, AUD2)
VIH
VIL
0.7VDDIO
-
-
-
-
V
V
-
-
0.3VDDIO
-2.0
2.0mA mode
3.0mA mode
VOH = 2.9V
VOL = 0.7V
For one channel
DAC
IAUD
-
-
mA
-3.0
Output High Current
Output Low Current
Input Pull-Low Resister
(PA15 :0, PB15 :0)
IOH
IOL
-
-
-
-
-3.2
mA
mA
7.0
RPL
RPH
-
-
-
-
165
210
KΩ
KΩ
VIN = VDDIO
VIN = VSS
Input Pull-High Resister
(PA15 :0, PB15 :0)
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GPCE061A
7.3. DC Characteristics (VDD = 3.3V, VDDIO = 5.5V (PortA & B), TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Operating Voltage
Operating Current
VDD
IOP
3.0
3.3
3.6
V
-
FOSC = 49.152MHz,
AD, DAC disable, no loading
Disable 32KHz crystal
When IOB13, IOB14 < = 3.6V
Enable 32Khz, Disable PLL (FOSC
When IOB13, IOB14 < = 3.6V
-
-
-
26
-
-
mA
2.0
5.0
Standby Current
ISTB
μA
)
Input High Level
Input Low Level
Output DAC current
(AUD1, AUD2)
VIH
VIL
0.7VDDIO
-
-
-
V
V
-
0.3VDDIO
-
-2.0
-3.0
-5.0
12
2.0mA mode
3.0mA mode
VOH = 4.0V
VOL = 1.0V
For one channel
DAC
IAUD
-
-
mA
Output High Current
Output Low Current
Input Pull-Low Resister
(PA15:0, PB15:0)
IOH
IOL
-
-
-
-
mA
mA
VIN = VDDIO
VIN = VSS
RPL
RPH
-
-
110
150
-
-
KΩ
KΩ
Input Pull-High Resister
(PA15:0, PB15:0)
7.4. DC Characteristics (VDD = 3.3V, VDDIO = 3.3V (PortA & B), TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Operating Voltage
Operating Current
VDD
IOP
3.0
3.3
3.6
V
-
FOSC = 49.152MHz,
-
-
26
-
-
mA
AD, DAC disable, no loading
2.0
Disable 32KHz crystal
Standby Current
ISTB
μA
5.0
Enable 32Khz, Disable PLL (FOSC)
Input High Level
Input Low Level
Output DAC current
(AUD1, AUD2)
VIH
VIL
0.7VDDIO
-
-
-
V
V
-
-
-
0.3VDDIO
-2.0
-3.0
-2.9
6.7
2.0mA mode
3.0mA mode
For one channel
DAC
IAUD
-
-
mA
Output High Current
Output Low Current
Input Pull-Low Resister
(PA15:0, PB15:0)
IOH
IOL
-
-
-
-
mA
mA
V
OH = 2.6V
OL = 0.7V
V
VIN = VDDIO
VIN = VSS
RPL
RPH
-
-
175
242
-
-
KΩ
KΩ
Input Pull-High Resister
(PA15:0, PB15:0)
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GPCE061A
7.5. ADC Characteristics (VDD = 3.3V, TA = 25℃)
Unit
Typ.
1.0
Characteristics
Symbol
Unit
Min.
Max.
ADC Power Dissipation for LINE_IN
ADC Power Dissipation For MIC_IN
ADC LINE_IN Input Voltage Range from
IOA[6:0]
IADC
-
-
-
-
mA
mA
1.9
-
VINL (Note 1)
VSS - 0.3
-
VDD + 0.3
V
ADC Microphone Input Voltage Range
VINM
VSS - 0.3
-
-
-
VDD + 0.3
VDD + 0.3
10
V
V
External ADC Top Voltage
Resolution of ADC
VEXTREF (Note 2)
RESO
2.0
-
bits
Signal-to-Noise Plus Distortion of ADC from
Line In
SINAD (Note 4)
-
56
-
dB
Effective Number of Bit
ENOB (Note 5)
INL
-
-
-
-
-
9.0
±4.0
±0.5
-
bits
LSB (Note 3)
LSB
Integral Non-Linearity of ADC
Differential Non-Linearity of ADC
AD Conversion Rate
-
DNL (Note 6)
FCONV
-
-
-
FCPU/512
42
Hz
Microphone Amplifier Gain (Note 7)
A MIC
dB
Note1: Internal protection diodes clamp the analog input to VDD and VSS. These diodes allow the analog input to swing from (VSS-0.3V) to (VDD+0.3V)
without causing damages to the devices.
Note2: The ADC performance is limited by the system noise level and therefore, the GPCE061A only guarantees to the 8-bit accuracy when VEXTREF is 2.0V.
Note3: The LSB means Least Significant Bit. VINL = 2.0V, 1LSB = 2.0V/2^10 = 1.953mV.
Note4: The SINAD testing condition at VINLp-p = 0.8*VDD, FCONV = Fcpu/512 = 49MHz/512 = 95KHz, Fin = 1.0KHz Sine waves at VDD = 3.0V from the IOA
[6:0] input.
Note5: ENOB = (SINAD-1.76)/6.02.
Note6: The ADC of GPCE061A guarantees no data missed during conversion.
Note7: The microphone amplifier maximum gain = 15 * (60K / (1.5K + REXT) V/V. The REXT is external resistor between OPI and MICOUT. The gain is
132V/V (=42dB) when REXT is 5.1K.
7.6. V2VREF Regulator Characteristics (VDD = 3.3V, TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
1.8
-
Typ.
2.0
Max.
2.2
-
AVDD = 3.3V, IOUT ≦5mA
Output Voltage Accuracy
Output Current
V2VREF
IOUT
V
mA
V
5.0
AVDD = 3.3V, V2VREF = 2.0V
IOUT ≦5mA, V2VREF = 2.0V
Input Voltage
AVDD
3.0
3.3
3.6
Note1: The V2VREF Regulator output current maximum ≦ 5mA, It is not matching to make a large current driver application. Our suggestion can be used
as external ADC Line_IN reference voltage.
7.7. DAC Characteristics (VDD = 3.3V, TA = 25℃)
Unit
Characteristics
DAC resolution
Symbol
Unit
Min.
Typ.
Max.
10
RESO
SNR
FS
-
-
-
54
-
bit
dB
Hz
V
Signal to Noise Ratio of DAC
Sample Rate
-
-
100K
VDD/2
Output Voltage Accuracy range
VDAC
0
-
Note1: The DAC output voltage in accuracy range have max 10 bits resolution.
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GPCE061A
7.8. Pull High Resister and VDDIO
7.11. I/O Output Low Current IOL and VOL
500
400
300
200
100
25
20
15
10
5
0
0
0.5
1.5
2.5
3.5
4.5
2.4
3.4
VDD (V)
4.4
VOL (V)
IO
7.9. I/O Output High Current IOH and VOH
7.12. DAC output current vs. VDD (2mA mode with
500hm resistor)
15
3
2
1
0
10
5
0
0.5
1.5
2.5
3.5
4.5
VOH (V)
2.4
2.8
3.2
3.6
VDD (V)
7.10. Pull Low Resister and VDDIO
7.13. DAC output current vs. VDD (3mA mode with
500hm resistor)
300
200
100
0
4
3
2
1
0
2.4
3.4
VDD (V)
4.4
IO
2.4
2.8
3.2
3.6
VDD (V)
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8.APPLICATION CIRCUITS
8.1. Application Circuit - (1)
Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
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GPCE061A
8.2. Application Circuit - (2)
Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
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GPCE061A
8.3. Application Circuit - (3)
Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
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GPCE061A
8.4. Application Circuit - (4)
Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
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GPCE061A
8.5. Application Circuit - (5)
Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
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GPCE061A
8.6. Application Circuit - (6)
/
Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
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GPCE061A
8.7. Application Circuit - (7)
100K
Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
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GPCE061A
9.PACKAGE/PAD LOCATIONS
9.1. Ordering Information
Product Number
Package Type
Chip form
Green Package form - LQFP 80
GPCE061A-NnnV-C
GPCE061A-NnnV-HL04n-W
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
Note3: HL04n-W, HL04 is assign for LQFP80, n is assign for customer, W is watch dog bonding option (W=0 enable, W=1 disable).
9.2. Package Information
9.2.1. LQFP 80
Dimension in inch
Symbol
Min.
-
Typ.
Max.
0.063
0.006
0.057
0.011
0.009
0.008
0.006
A
A1
A2
b
-
0.002
0.053
0.007
0.007
0.004
0.004
-
0.055
0.009
b1
c
0.008
-
c1
D
-
0.551 BSC
0.472 BSC
0.551 BSC
0.472 BSC
0.020 BSC
D1
E
E1
e
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GPCE061A
Dimension in inch
Symbol
Min.
Typ.
Max.
L
0.018
0.024
0.030
L1
R1
R2
0.039 REF
0.003
0.003
0.008
0°
-
-
-
0.008
-
S
-
θ
3.5°
-
7°
θ 1
θ 2
θ 3
0°
-
11°
12°
12°
13°
13°
11°
PAD No.
PAD Name
PAD No.
PAD Name
1
X32O
X32I
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
IOA6
IOA7
2
3
TEST
N/C
VSSIO
VSSIO
VDDIO
VDDIO
IOA8
4
5
VDD
6
N/C
7
ICE
8
ICECLK
ICESDA
VSS
N/C
9
N/C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
IOA9
PVIN
IOA10
IOA11
IOA12
IOA13
IOA14
IOA15
N/C
DAC1
DAC2
V2VREF
AVSS
AGC
OPI
MICOUT
MICN
PFUSE
MICP
VADREF
VEXTREF
AVDD
VMIC
N/C
N/C
VSSIO
N/C
SLEEP
IOB15
IOB14
IOB13
IOB12
IOB11
NC
VSS
IOA0
N/C
IOA1
N/C
IOA2
IN/C
IOA3
VDDIO
IOB10
IOB9
IOA4
IOA5
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GPCE061A
PAD No.
PAD Name
PAD No.
PAD Name
67
68
69
70
71
72
73
IOB8
IOB7
IOB6
IOB5
IOB4
IOB3
IOB2
74
75
76
77
78
79
80
IOB1
IOB0
RESET
N/C
VDD
VCOIN
VSS
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GPCE061A
10. TABLE OF GPCE061/060/040 COMPARISON
The information in this table is the different from GPCE061/060/040.
Item
Working Voltage
GPCE040A
GPCE060A
GPCE061A
3.0V ~ 3.6V @ 49.152MHz
3.0V ~ 3.6V
3.0V ~ 5.5V
2.4V ~ 3.6V @ 40.96MHz, 32.768MHz,
24.576MHz, 20.48MHz
2.4V ~ 5.5V
IO Working Voltage
Memory size
24K Words ROM
32K Words ROM
32K Words Flash Memory
MICN/MICP 10K
pull up resistors
Built in (ref. the GPCE060A/040A datasheet Using external resistors (ref. GPCE061A
Ω
application circuit 1)
datasheet application circuit 1)
Pin 7 in LQFP80 package
Pin 8 in LQFP80 package
NC (ref LQFP80 package)
Ground reference for I/O and logic pins (VSS)
(ref LQFP80 package)
ICE, the ICE Enable (ref LQFP80 package)
ICECLK, the ICE serial interface clock. 100K
Ω
pull low resistor is necessary to prevent current
leakage.
(ref LQFP80 package)
Pin 9 in LQFP80 package
Pin20,11 in LQFP80 package
(Pfuse, Pvin)
NC (ref LQFP80 package)
NC (ref LQFP80 package)
ICESDA, the ICE serial interface data
NC in normal mode, for security using (ref.
GPCE061A datasheet)
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GPCE061A
11. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
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GPCE061A
12. REVISION HISTORY
Date
Revision #
Description
Page
OCT. 01, 2013
NOV. 18, 2011
OCT. 13, 2010
MAY 23, 2008
JUL. 11, 2006
1.5
1.4
1.3
1.2
1.1
Add COMAIR logo to the cover page
Modify 8.7 Application Circuit - (7).
Modify 3.FEATURES.
23
4
Modify 8. APPLICATION CIRCUITS.
1. Modify the 9.2 Ordering Information.
2. Delete the 9.3.2 PLCC84.
17-23
24
25
3. Modify the 8. APPLICATION CIRCUITS.
Original
17-23
31
DEC. 19, 2005
1.0
Note: The GPCE061A data sheet v1.0 is a continued version of SPCE061A data sheet v0.8.
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相关型号：
SI9130DB
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