GPCE2064A [GENERALPLUS]
16-bit Sound Controller with 32K X 16 ROM;
| 型号： | GPCE2064A |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 16-bit Sound Controller with 32K X 16 ROM |
| 文件： | 总24页 (文件大小：873K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPCE2064A
16-bit Sound Controller with
32K X 16 ROM
Jun 02, 2016
Version 1.2
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPCE2064A
Table of Contents
PAGE
1
2
3
4
5
GENERAL DESCRIPTION.......................................................................................................................................................................... 4
FEATURES.................................................................................................................................................................................................. 4
APPLICATION FIELD.................................................................................................................................................................................. 4
BLOCK DIAGRAM ...................................................................................................................................................................................... 5
SIGNAL DESCRIPTIONS............................................................................................................................................................................ 6
5.1 PIN MAP ............................................................................................................................................................................................... 7
6
FUNCTION DESCRIPTIONS....................................................................................................................................................................... 8
6.1 CPU ..................................................................................................................................................................................................... 8
6.2 MEMORY ............................................................................................................................................................................................... 8
6.2.1 SRAM........................................................................................................................................................................................ 8
6.2.2 ROM.......................................................................................................................................................................................... 8
6.3 PLL, CLOCK, POWER MODE................................................................................................................................................................... 8
6.3.1 PLL (Phase Lock Loop)............................................................................................................................................................. 8
6.4 STANDBY MODE..................................................................................................................................................................................... 8
6.5 LOW VOLTAGE DETECTION AND LOW VOLTAGE RESET............................................................................................................................. 9
6.5.1 Low voltage detection (LVD) ..................................................................................................................................................... 9
6.5.2 Low voltage reset...................................................................................................................................................................... 9
6.6 INTERRUPT............................................................................................................................................................................................ 9
6.7 I/O........................................................................................................................................................................................................ 9
6.8 SPECIAL FUNCTION IN PORT................................................................................................................................................................. 10
6.9 TIMER / COUNTER................................................................................................................................................................................ 10
6.9.1 IO PWM ...................................................................................................................................................................................11
6.9.2 Timebase .................................................................................................................................................................................11
6.10 SLEEP MODE, WAKEUP, HALT MODE, AND WATCHDOG ...........................................................................................................................11
6.10.1 Sleep and wakeup modes........................................................................................................................................................11
6.10.2 Watchdog Reset.......................................................................................................................................................................11
6.11 SOFT RESET PROTECTION ................................................................................................................................................................... 12
6.12 ADC (ANALOG TO DIGITAL CONVERTER) / DAC .................................................................................................................................... 12
6.13 SPI..................................................................................................................................................................................................... 12
6.14 AUDIO ALGORITHM............................................................................................................................................................................... 12
7
ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 13
7.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 13
7.2 DC CHARACTERISTICS (VDD = 3.3V, VDDIO = 4.5V (PORTA & B), TA = 25℃) ..................................................................................... 13
7.3 DC CHARACTERISTICS (VDD = 3.3V, VDDIO = 3.3V (PORTA & B), TA = 25℃) ..................................................................................... 13
7.4 ADC CHARACTERISTICS (VDD = 3.3V, TA = 25℃) ............................................................................................................................... 14
7.5 DAC CHARACTERISTICS (V50_DAC = 5.0V, TA = 25℃)....................................................................................................................... 14
7.6 REGULATOR CHARACTERISTICS (TA = 25℃) ......................................................................................................................................... 15
7.7 PULL HIGH RESISTER AND VDDIO........................................................................................................................................................ 15
7.8 PULL LOW RESISTER AND VDDIO (NORMAL PAD) ................................................................................................................................ 15
7.9 PULL LOW RESISTER AND VDDIO (IOB[7:0] PAD WITH INPUT HIGH)...................................................................................................... 15
7.10 I/O OUTPUT HIGH CURRENT IOH AND VDDIO ........................................................................................................................................ 15
7.11 I/O OUTPUT LOW CURRENT IOL AND VDDIO (NORMAL PAD) .................................................................................................................. 16
7.12 I/O OUTPUT LOW CURRENT IOL AND VDDIO (HIGH DRIVING PAD)........................................................................................................... 16
7.13 INTERNAL ROSC AND V33_REG ......................................................................................................................................................... 16
8
APPLICATION CIRCUITS......................................................................................................................................................................... 17
8.1 APPLICATION CIRCUIT WITH REGULATOR, XTAL32K SELECTED ............................................................................................................ 17
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GPCE2064A
8.2 APPLICATION CIRCUIT WITH REGULATOR, INTERNAL ROSC32K SELECTED............................................................................................ 18
8.3 APPLICATION CIRCUIT WITHOUT REGULATOR, XTAL32K SELECTED....................................................................................................... 19
8.4 PUSH PULL DAC MIXED WITH ANOTHER DAC ....................................................................................................................................... 20
9
PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 21
9.1 ORDERING INFORMATION ..................................................................................................................................................................... 21
9.2 PACKAGE INFORMATION....................................................................................................................................................................... 21
10 DISCLAIMER............................................................................................................................................................................................. 23
11 REVISION HISTORY ................................................................................................................................................................................. 24
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Version: 1.2
GPCE2064A
16-BIT SOUND CONTROLLER
WITH 32K X 16 ROM
1 GENERAL DESCRIPTION
Three 16-bit timers/counters
One 14-bit DAC with push-pull amplifier. Supports cascade
mode
GPCE2064A, a 16-bit architecture sound controller, features
16-bit ’nSP™ microprocessor developed by Sunplus Technology.
This high processing speed assures the ’nSP™ is capable of
handling complex digital signal processing easily and rapidly.
GPCE2064A is applicable to the areas of digital sound
processing and voice recognition. The operating voltage of 2.4V
through 5.5V and speed of 0.16MHz through 49.152MHz yield
the GPCE2064A to be easily used in varieties of applications.
The memory capacity includes 32K-word ROM plus a 2K-word
32 general I/Os (bit programmable)
Key wakeup function (IOA0 - 15)
PLL feature for system clock
32768Hz Real Time Clock (RTC), crystal or internal resistor
oscillator selected.
Eight channels of 12-bit AD converter
ADC
Built-in microphone amplifier and AGC or PGA function
selected
working SRAM.
Other features include 32 programmable
multi-functional I/Os, three 16-bit timers/counters, 32768Hz Real
Time Clock, Low Voltage Reset/Detection, eight channels 12-bit
ADC (one channel built-in MIC amplifier with auto gain controller),
one 14-bit DAC with push-pull amplifier and many others.
Low voltage reset and low voltage detection
Watchdog Enable (option)
One SPI serial interface I/O
3 APPLICATION FIELD
2 FEATURES
Voice Recognition Product
Intelligent Interactive Talking Toy
Advanced Educational Toy
Kids Learning Product
16-bit ’nSP™ microprocessor
CPU Clock: 0.16MHz - 49.152MHz
Operating Voltage: 2.4V - 5.5V
Power regulator built-in with input voltage: 2.4~5.5V, output
voltage: 2.4~3.3V
Kids Storybook
General Speech Synthesizer
Long Duration Audio Product
Recording / Playback Product
IO PortA & B Operating Voltage: 2.4V - 5.5V
32K-word fast speed ROM
2K-word working SRAM
Software-based audio processing
Two sets of 14-bit software channel with noise filter, mixer and
scalar to play high quality sound
Standby mode for power saving
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GPCE2064A
4 BLOCK DIAGRAM
Regulator
Fast-speed ROM
32K word
un'SP
16-bits CPU
AUDN
Push Pull DAC
AUDP
ACIN
MICIN
MICIP
MICO
OPI
AGC
VMIC
PLL / System clock /
Reset Function
X32I
AD Converter
MIC
X32O
VADREF
2K(word) Working
SRAM
TimeBase/WatchDog
16-bits Counter/Timer
/ Interrupt
RESETB
SPI
Memory Mapping & Control
/ GPIO Special Function
/ PWM output
General I/O Port
IOA[15:0]
IOB[15:0]
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GPCE2064A
5 SIGNAL DESCRIPTIONS
Mnemonic
PORT A, Port B
IOA[15:0]
PIN No.
Type
Description
66-69, 1-4, 7-14
52-45, 42-35
I/O
I/O
IOA[15:0]: bi-directional I/O ports
It can be programmed as wakeup I/O pins
IOB [15:0]: bi-directional I/O ports
IOB [15:0]
Power & GND
VDD_IOA
VSS_IOA
5
P
G
P
G
P
G
P
P
G
P
P
I
Power VDD for Port A
6
Power GND for Port A
VDD_IOB
VSS_IOB
43
Power VDD for Port B
44
Power GND for Port B
V33_ADC
VSS_ADC
V33_REG
VDD_REG
VSS_REG
VDD_DAC
VDD_PDAC
VSS_DAC
VSS_ PDAC
27
Power VDD for AD(3.3V)
26
Power GND for AD
16
3V power output from regulator
Positive supply for regulator(2.4V~5.5V)
Ground reference for regulator
Positive 5V supply for push-pull DAC
Positive 5V supply for push-pull DAC post driver
Ground reference for push-pull DAC
Ground reference for push-pull DAC post driver
15
18
59
57, 58
64
53, 54, 62, 63
I
CLK SYSTEM/ ICE INTERFACE
XTI
24
23
I
32KHz Oscillator crystal input
32K Oscillator crystal output
XTO
O
OPTION
TEST
TEST2
TEST3
25
17
20
I
I
I
TEST Mode selection pin, do not connect the pin
TEST2 Mode selection pin, do not connect the pin
TEST3 Mode selection pin, do not connect the pin
R32K or Xtal32K select. Connected to VSS when Xtal32K is selected, and
connected to V33_REG when R32K is selected.
R32SEL
19
I
DAC
AUDP
AUDN
ACIN
60, 61
55, 56
65
O
O
U
Audio output of push pull DAC
Audio output of push pull DAC
Audio analog mixer in
ADC
MICP
34
33
32
31
30
28
29
I
I
MIC amplifier input positive (Internal Floating)
MIC amplifier input negative (refer to application circuit)
MIC amplifier output (refer to application circuit)
Audio amplifier negative input (refer to application circuit)
AGC by pass filter (refer to application circuit)
Microphone power supply
MICN
MICOUT
OPI
O
I
AGC
IO
O
O
VMIC
VADREF
PLL
AVREF_DA reference pin
VCOIN
Other Signal
RESETB
21
22
I
I
PLL low pass filter input
System reset pin (active low) (internal 47Kohm pull high resistor)
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GPCE2064A
5.1 PIN Map
LQFP80
NC
IOA[15]
1
2
3
60
59
58
IOB[15]
IOB[14]
IOB[13]
IOB[12]
IOA[14]
IOA[13]
4
5
57
56
55
54
53
52
51
IOA[12]
IOA[11]
IOA[10]
6
IOB[11]
7
IOA[9]
IOA[8]
IOB[10]
IOB[9]
8
9
VDD_IOA
VSS_IOA
IOA[7]
IOB[8]
10
VSS_IOB
VDD_IOB
11
12
13
14
15
16
17
18
19
20
50
49
48
47
46
GPCE2064
IOA[6]
IOA[5]
IOA[4]
IOB[7]
IOB[6]
IOB[5]
IOB[4]
IOA[3]
IOA[2]
IOA[1]
IOA[0]
45
IOB[3]
IOB[2]
IOB[1]
IOB[0]
MICP
44
43
42
41
NC
NC
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GPCE2064A
6 FUNCTION DESCRIPTIONS
6.1 CPU
6.2 Memory
6.2.1 SRAM
The GPCE2064A is equipped with a 16-bit ’nSP™, the newest
16-bit microprocessor by Sunplus (pronounced as micro-n-SP).
Eight registers are involved in ’nSP™: R1 - R4 (General-
purpose registers), PC (Program Counter), SP (Stack Pointer),
Base Pointer (BP) and SR (Segment Register). The interrupts
include three FIQs (Fast Interrupt Request) and eight IRQs
(Interrupt Request), plus one software-interrupt, BREAK.
The amount of SRAM is 2K-word (including Stack), ranged from
$0000 through $07FF with access speed of two CPU clock
cycles.
Phase Lock Loop
Fosc/n
CPU Clock
FOSC
32768Hz X'tal
(PLL)
PLL OUT
24.576MHz(default)
20.48MHz
System Clock generator
n:1,2,4,8,16,32,64
(Default : Fosc/8)
32.768MHz
40.96MHz
49.152MHz
b2 b1 b0
b7 b6 b5
b7,b6,b5 of P_SystemClock(W)($2030H)
System clock frequency selection
of P_SystemClock(W)($2030H)
CPU clock frequency selection
6.2.2 ROM
32768Hz crystal oscillator in normal mode and auto-power-saving
mode. In normal mode, 32768Hz OSC always runs at the
GPCE2064A features a 32K-word high-speed memory with
access speed of two CPU clock cycles.
highest power consumption.
In auto-power-saving mode,
however, it runs at normal mode for the first 7.5 seconds and
switches back to power-saving mode automatically to save
powers.
6.3 PLL, Clock, Power Mode
6.3.1 PLL (Phase Lock Loop)
The purpose of PLL is to provide a base frequency (32768Hz)
and to pump the frequency from 20.48MHz to 49.152MHz for
system clock (FOSC). The default PLL frequency is 24.576MHz.
6.4 Standby Mode
The GPCE2064A features a power savings mode (or called
standby mode) for low power applications. To enter standby
mode, the desired key wakeup port (IOA[15:0]) must be
configured to input first. And read the Port_IOA_Data to latch
6.3.1.1 System clock
Basically, the system clock is provided by PLL and programmed
by the Port_SystemClock (R/W) to determine the clock frequency
for system. The default system clock FOSC = 24.576MHz and
CPU clock is FOSC/8 if not specified. The initial CPU clock is
Fosc/8 after system wakes up and adjusts to desired CPU clock
via programming the Port_SystemClock (R/W). This avoids
ROM reading failure when system awakes.
the IOA state before entering the standby mode.
Also
remember to enable the corresponding interrupt source(s) for
wakeup. After that, stop the CPU clock by writing $5555 into
Port_System_Sleep(W) to enter standby mode. In such mode,
SRAM and I/Os remain in the previous states until CPU being
awakened. The wakeup sources in GPCE2064A include KEY
wakeup (IOA[15:0]), RTC wakeup, FIQ and IRQ0 - IRQ7. After
GPCE2064A is awakened, CPU will continue to execute the
program from where it slept. Programmer can also enable or
disable the 32768Hz RTC when CPU is in standby mode.
6.3.1.2 32768Hz RTC
The Real Time Clock (RTC) is normally used in watch, clock or
other time related products. A 2Hz-RTC (0.5 seconds) function
is loaded in GPCE2064A. The RTC counts the time as well as
to wake CPU up whenever RTC occurs. Since the RTC is
generated each 0.5 seconds, time can be traced by the number
of RTC occurrences.
In addition, GPCE2064A supports
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GPCE2064A
6.5 Low Voltage Detection and Low Voltage Reset
6.5.1 Low voltage detection (LVD)
6.7 I/O
Two I/O ports are built in GPCE2064A - PortA and PortB, total
has 32 bit-programmable I/Os. The PortA is a general purpose
I/O with programmable wakeup capability, i.e. IOA [15:0] is the
key wakeup port. To activate key wakeup function, latch data on
Port_IOA_Data and enable the key wakeup function. Wakeup is
triggered when the PortA state is different from at the time
latched. Furthermore, the I/O ports can be operated at 5V level,
higher than the CPU core which is a 3V level system. Suppose
system operating voltage is running at 3.3V, VDDIO (power for
I/O) operates from 3.3V to 5.5V. In such condition, the I/O pad
is capable of operating from 0V through VDDIO. The following
diagram is an I/O schematic. Although data can be written into
the same register through Port_Data and Port_Buffer, they can
be read from different places, Buffer (R) and Data (R).
The Low Voltage Detection (LVD) reports the circumstance of
present voltage. There are four LVD levels to be selected: 2.6V,
2.8V, 3.0V and 3.2V. Those levels can be programmed via
P_LVD_Ctrl. As an example, suppose LVD is given 2.8V.
When the voltage drops below 2.8V, the b12 of P_LVD_Ctrl is
read as HIGH. In such state, program can be designed to react
this condition.
6.5.2 Low voltage reset
In addition to the LVD, the GPCE2064A has another important
function, Low Voltage Reset (LVR). With the LVR function, a
reset signal is generated to reset system when the operating
voltage drops below LVR level. Without LVR, the CPU becomes
unstable and malfunctions when the operating voltage drops
below LVR level. The LVR will reset all functions to the initial
operational (stable) states when the voltage drops below LVR
level.
Buffer(R)
Port_Data(W)
Register
pull high
pull low
Port_Buffer(W)
Port_DIR(R/W)
Port_ATTR(R/W)
Pin pad
Control
logic
6.6 Interrupt
The GPCE2064A has 13 interrupt sources, grouped into two
types, FIQ (Fast Interrupt Request) and IRQ (Interrupt request).
The priority of FIQ is higher than IRQ. FIQ is a high-priority
interrupt while IRQ is the low-priority one. An IRQ can be
interrupted by a FIQ, but not by another IRQ. A FIQ cannot be
interrupted by any other interrupt sources.
Data(R)
In addition to a general purpose I/O port function, PortA/B also
shares/carries some special functions. A summary of PortA/B
special functions is listed as follows:
Interrupt Source Interrupt Name / FIQ Name IRQ Priority
Timer A
Timer B
Timer C
SPI
IRQ0_TMA/FIQ_TMA
IRQ1_TMB/FIQ_TMB
IRQ2_TMC/FIQ_TMC
IRQ3_SPI/FIQ_SPI
1(High)
2
3
4
Key wakeup
EXT1
IRQ5_KEY/FIQ_KEY
IRQ5_EXT1/FIQ_EXT1
IRQ5_EXT2/FIQ_EXT2
IRQ6_4KHz/FIQ_4KHz
IRQ6_2KHz/FIQ_2KHz
IRQ6_512Hz/FIQ_512Hz
IRQ7_64Hz/FIQ_64Hz
IRQ7_16Hz_FIQ_16Hz
IRQ7_2Hz/FIQ_2Hz
5
6
EXT2
7
4096Hz
2048Hz
512Hz
64Hz
8
9
10
11
16Hz
12
2Hz
13(Low)
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GPCE2064A
6.8 Special Function in Port
Port
IOA0
IOA1
IOA2
IOA3
IOA4
IOA5
IOA6
IOA7
Special Function
Function Description
Note
IO_PWM
IROUT
IO_PWM Output
Refer to Timer section
IR Output
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
High driving I/O
High driving I/O
High driving I/O
High driving I/O
Feedback Input1
EXT1
-
Refer to below Example 1
Set IOA8 as floating input mode
Set IOA9 as inverted output
IOA8
External interrupt source 1 (negative edge triggered)
Work with IOA8 by adding a RC circuit between them
IOA9
IOA10
IOA11
Feedback Output1
to get an OSC to EXT1 interrupt
Feedback Input2
EXT2
-
External interrupt source 2 (negative edge triggered)
Work with IOA10 by adding a RC circuit between them
to get an OSC to EXT2 interrupts
SPI chip select
Refer to below Example 1
Set IOA10 as floating input mode
Feedback Output2
Set IOA11 as inverted output
IOA12
IOA13
IOA14
IOA15
IOB0
SPI CS
SPI CK
SPI TX
SPI RX
AN0
Refer to SPI section
Refer to SPI section
Refer to SPI section
Refer to SPI section
Refer to ADC section
Refer to ADC section
Refer to ADC section
Refer to ADC section
Refer to ADC section
Refer to ADC section
Refer to ADC section
Refer to ADC section
SPI clock
SPI data output
SPI data input
ADC Channel 0
IOB1
AN1
ADC Channel 1
IOB2
AN2
ADC Channel 2
IOB3
AN3
ADC Channel 3
IOB4
AN4
ADC Channel 4
IOB5
AN5
ADC Channel 5
IOB6
AN6
ADC Channel 6
IOB7
AN7
ADC Channel 7
IOA[15:0],
IOB[15:0]
Io toggle
Io toggle function
Refer to IO Special Functions section
Refer to the above table, the configuration of IOA9, IOA10, IOA11, and IOA12 involves feedback function in which an OSC frequency can be obtained from
EXT1 (EXT2) by simply adding a RC circuit between IOA8 (IOA10) and IOA9 (IOA11).
6.9 Timer / Counter
GPCE2064A provides three 16-bit timers/counters - TimerA,
TimerB and TimerC or so called universal counters. The clock
source of Timer A/B/C are from clock source Input 1 and clock
source Input 2 (see below table) which perform AND operation to
form the varieties of combinations. When timer overflows, a
timeout signal (TAOUT) is sent to CPU interrupt module to
generate a timer interrupt signal. In addition, Timer A/B/C
hardware interrupt events can be used to latch the DAC audio
output and trigger ADC conversion.
value of TMA_DATA (value=N) will reload into TMA_CNT and set
an appropriated clock source. Timer wills up-count from N, N+1,
N+2… 0XFFFF. An INT signal is generated at the moment of
timer rolling over from “0xFFFF” to “0x0000”, and an INT signal is
processed by INT controller immediately. At the same time, N
will be reloaded into TMA_CNT and start counting again.
In Timer A, the clock Input 1 is a high frequency source and clock
Input 2 is a low frequency clock source. The combination of
clock Input 1 and input 2 provides varieties of speeds to
Example to Timer A, sending a write signal into TMA_CNT, the
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GPCE2064A
TimerA/CounterA - “1” representing pass signal (not gating), and
“0” meaning timer deactivated. For instance, if Input 1=”1”, the
clock is depending on Input 2. If Input 1=”0”, the TimerA is
deactivated. The EXT1/ETX2 is the external clock source 1 and
external clock source 2.
TMXSEL
1100
Input 1
FPLL
Input 2
64Hz
16Hz
2Hz
1101
FPLL
1110
FPLL
1111
FPLL
‘1’
The following clock source A/B/C means clock source for Timer
A/B/C respectively. Generally speaking, the clock source A and
C are fast clock sources and source B comes from RTC system
(32768Hz). Therefore, clock source B can be utilized as a
precise counter for time counting, e.g., the 2Hz clock can be
used for real time counting.
TMXSEL
0000
0001
0010
0011
0100
0101
0110
0111
Input 1
‘0’
Input 2
‘0’
‘1’
‘1’
FRTC
FPLL
EXT2
EXT2
64Hz
16Hz
2Hz
‘1’
EXT2
EXT2
EXT2
EXT2
FRTC
FRTC
FRTC
FRTC
6.9.1 IO PWM
One IO PWMs which duty is selected from 1/256 to 254/256.
Example the below figure is a 3/256-duration cycle. The PWMO
1000
1001
1010
1011
64Hz
16Hz
2Hz
‘1’
waveform is made by selecting
a pulse width through
Port_PWM_Ctrl. As a result, each 256 cycles will generate a
pulse width defined in control port. These PWM signals can be
applied for controlling the speed of motor or other devices.
1
2
3
4
5
6
7
8
9
251
252
253
254
255
256
1
2
3
4
5
TimerA_Timeout
PWMO
...
Tp.w..mo
Tduty
...
Wakeup Source
FIQ source
6.9.2 Timebase
Timebase, generated by 32768Hz crystal oscillator, is
a
Timer A interrupt
Timer B interrupt
Timer C interrupt
SPI interrupt
combination of frequency selection. Furthermore, timebase
generates 4KHz, 2KHz, 512Hz, 64Hz, 16Hz and 2Hz interrupt
sources (FIQ6/IRQ6, FIQ7/IRQ7) for Real-Time-Clock
EXT1/EXT2/KEY
RTC
6.10 Sleep Mode, Wakeup, Halt Mode, and Watchdog
6.10.1 Sleep and wakeup modes
6.10.2 Watchdog Reset
1) Sleep: After power-on reset, IC starts running until a sleep
command is issued. When a sleep command is
accepted, IC will turn the system clock (PLL) off.
After all, it enters sleep mode.
The GPCE2064A provides another important feature, watchdog
reset. If the watchdog function is enabled, a reset signal is
generated to reset system when watchdog counter is overflow.
2) Wakeup: CPU awaking from sleep mode requires a wakeup
signal to turn the system clock (PLL) on. The
FIQ/IRQ signal makes CPU to complete the
The purpose of watchdog is to monitor whether the system
operates normally. Within a certain period, watchdog register
must be cleared. If it is not cleared, CPU assumes the program
has been running in an abnormal condition. As a result, the
CPU will reset the system to the initial state and start running the
program all over again.
wakeup process and initialization.
The CPU
wakeup source is given in the following table.
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GPCE2064A
6.11 Soft Reset Protection
circuit is capable of reducing common mode noise by transmitting
signals through differential MIC Inputs (MICN, MICP). Moreover,
an external resistor can be applied to adjust microphone gain and
time of AGC operating. The AD needs to select source of line-in
before conversion. The ADC takes pad (VDD_ADC) as voltage
reference.
Software reset. Writes $5555 into P_System_Reset will reset
the whole system like hardware reset (pull low RESETB pin),
except a flag will set on in P_System_LVD_Ctrl(R/W).
6.12 ADC (Analog to Digital Converter) / DAC
The GPCE2064A has eight channels 12-bit ADC (Analog to
Digital Converter). The function of an ADC is to convert analog
signal to digital signal, e.g. a voltage level into a digital word.
The eight channels of ADC can be eight channels of line-in from
IOB [7:0] or one channel microphone (MIC) input through
amplifier PGA controller, and AGC controller. The MIC amplifier
6.13 SPI
A
Serial Peripheral Interface (SPI) controller is built in
GPCE2064A to facilitate communicating with other devices and
components. There are four control signals on SPI - SPICS
(IOA12), SPICK (IOA13), SDO (IOA14), and SDI (IOA15).
SPICK(POL=0)
SPICK(POL=1)
PHASE = 0
SDO
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
SDI
SPICS
SPICK(POL=0)
SPICK(POL=1)
PHASE = 1
SDO
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
SDI
SPICS
6.14 Audio Algorithm
The following speech types can be used in GPCE2064A: PCM,
SACM_S200, SACM_S480, SACM_S530, SACM_A1600,
SACM_A1601, SACM_A1800, SACM_A3400pro, SACM_A3600,
SACM_DVR3200, and SACM_DVR4800. For melody synthesis,
the GPCE2064A supports SACM_MS01 (FM) and SACM_MS02
(wave-table) synthesizers.
SACM_DVR520,
SACM_DVR1600,
SACM_DVR1800,
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GPCE2064A
7 ELECTRICAL SPECIFICATIONS
7.1 Absolute Maximum Ratings
Characteristics
Symbol
Ratings
DC Supply Voltage
V+
VIO
VIN
TA
< 4.0V
< 7.0V
PortA/B Pad Supply Voltage
Input Voltage Range
Operating Temperature
Storage Temperature
-0.5V to V+ + 0.5V
0℃ to +60℃
-50℃ to +150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to the device. For normal operational conditions
see DC Electrical Characteristics.
7.2 DC Characteristics (VDD = 3.3V, VDDIO = 4.5V (PortA & B), TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Operating Voltage
Operating Current
VDD
IOP
2.7
3.3
3.6
V
-
FOSC = 49.152MHz,
-
-
13
-
-
mA
AD, DAC disable, non-loading
5
A
A
V
Disable 32KHz crystal
Standby Current
ISTB
10
Enable 32KHz,Disable PLL(FOSC)
Input High Level
VIH
VIL
IOH
0.7VDDIO
-
-
-
-
Input Low Level
-
-
0.3VDDIO
-
V
-
Output High Current
Output Low Current
(PA[3:0], PB[7:0])
Output Low Current
(PA[7:4])
-20
mA
VOH = 0.7VDD
IOL
-
20
40
-
mA
mA
K
K
K
HZ
VOL = 0.3VDD
VOL = 0.3VDD
VIN = VDD
IOL
-
-
Input Pull-Low Resister
(PA15:0, PB15:8)
Input Pull-Low Resister
(PB[7:0])
RPL
-
120
-
RPL
-
-
1200
110
-
-
VIN = VDD
Input Pull-High Resister
(PA15:0, PB15:0)
Internal ROSC frequency
deviation
RPH
⊿F/F
VIN = VSS
-3%
32768
+3%
V33_REG = 3.3V
7.3 DC Characteristics (VDD = 3.3V, VDDIO = 3.3V (PortA & B), TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Operating Voltage
Operating Current
VDD
IOP
2.7
3.3
3.6
V
-
FOSC = 49.152MHz,
-
-
13
-
-
mA
AD, DAC disable, non-loading
3
A
A
V
Disable 32KHz crystal
Standby Current
ISTB
6
Enable 32KHz,Disable PLL(FOSC)
Input High Level
Input Low Level
VIH
VIL
IOH
0.7VDDIO
-
-
-
-
-
-
0.3VDDIO
-
V
-
Output High Current
-11
mA
VOH = 0.7VDD
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GPCE2064A
Limit
Typ.
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
Output Low Current
(PA[3:0], PB[7:0])
Output Low Current
(PA[7:4])
IOL
-
11
25
-
mA
mA
K
K
K
HZ
VOL = 0.3VDD
IOL
-
-
VOL = 0.3VDD
VIN = VDD
Input Pull-Low Resister
(PA15:0, PB15:8)
Input Pull-Low Resister
(PB[7:0])
RPL
-
120
-
RPL
-
-
1200
110
-
-
VIN = VDD
Input Pull-High Resister
(PA15:0, PB15:0)
Internal ROSC frequency
deviation
RPH
⊿F/F
VIN = VSS
-3%
32768
+3%
V33_REG = 3.3V
7.4 ADC Characteristics (VDD = 3.3V, TA = 25℃)
Limit
Characteristics
Symbol
Unit
Min.
Typ.
Max.
ADC LINE_IN Input Voltage Range from
IOB[7:0]
VINL (Note 1)
VSS-0.3
-
VDD+0.3
V
ADC Microphone Input Voltage Range
Resolution of ADC
VINM
VSS-0.3
-
-
-
VDD+0.3
12
V
RESO
bits
Signal-to-Noise Plus Distortion of ADC from
Line in
SINAD (Note 3)
-
55
-
dB
Effective Number of Bit
ENOB (Note 4)
INL
8.0
9.0
±8.0
±3
-
bits
LSB (Note 2)
LSB
Integral Non-Linearity of ADC
Differential Non-Linearity of ADC
AD Conversion Rate
-
-
-
-
-
DNL (Note 6)
FCONV
-
-
-
FCPU/256
42(Note 5)
Hz
Microphone Amplifier Gain
A MIC
dB
Note1: Internal protection diodes clamp the analog input to VDD and VSS. These diodes allow the analog input to swing from (VSS-0.3V) to (VDD+0.3V)
without causing damage to the devices.
Note2: LSB means Least Significant Bit. With VINL = 2.6V, 1LSB = 2.6V/2^12 = 0.635mV.
Note3: The SINAD testing condition at VINLp-p = 0.8*VDD, FCONV = Fcpu/512 = 49MHz/256 = 192KHz, Fin=1.0KHz Sine waves at VDD = 3.0V from the IOB
[7:0] input.
Note4: ENOB = (SINAD-1.76)/6.02.
Note5: The microphone amplifier maximum gain = 15 * (60K/(1.5K+REXT) V/V. The REXT is external resistor between OPI and MICOUT. The gain is
132V/V (=42dB) when REXT is 5.1K.
7.5 DAC Characteristics (V50_DAC = 5.0V, TA = 25℃)
Limit
Characteristics
Symbol
Unit
Min.
Typ.
-
Max.
DAC Resolution
RESO
-
-
-
-
14
-
bit
%
THD+n (5V @0.6W)
Noise at No Signal
Dynamic Range(-60dB)
-
-
-
1
-97
-82
-
dBr A
dBr A
-
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GPCE2064A
7.6 Regulator Characteristics (TA = 25℃)
Limit
Characteristics
Input Voltage
Symbol
Unit
Test Condition
Min. Typ. Max.
VREGI
IREGO
VREGO
IRGES
2.3
-
4.5
-
5.5
60
3.3
-
V
mA
V
VDD5V (Regulator in )= 4.5V, VDD (Regulator out ) <100mV
Maximum Current Output
Output Voltage
2.3
-
3.3
2.5
Standby Current
uA
7.7 Pull High Resister and VDDIO
7.9 Pull Low Resister and VDDIO (IOB[7:0] PAD with
input high)
113
113
112
112
112
112
112
111
111
111
1102.35
1102.30
1102.25
1102.20
1102.15
1102.10
1102.05
1102.00
2
3
4
5
6
VDD(V)
2
3
4
5
6
VDD(V)
7.8 Pull Low Resister and VDDIO (Normal PAD)
7.10 I/O Output High Current IOH and VDDIO
111.5
111.4
111.3
111.2
111.1
111.0
110.9
110.8
110.7
110.6
Test Condition: VOH = 0.7 * VDDIO
35
30
25
20
15
10
5
2
3
4
5
6
VDD(V)
0
2
3
4
5
6
VDD(V)
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GPCE2064A
7.11 I/O Output Low Current IOL and VDDIO (Normal
Pad)
7.13 Internal ROSC and V33_REG
Internal ROSC
Test Condition: VOL = 0.3 * VDDIO (Normal PAD)
100.10%
100.00%
99.90%
99.80%
99.70%
99.60%
99.50%
99.40%
99.30%
0
-5
32768HZ
-10
-15
-20
-25
-30
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
3.1
3.2
3.3
V33_REG(V)
2
3
4
5
6
VDD(V)
7.12 I/O Output Low Current IOL and VDDIO (High
driving pad)
Test Condition: VOL = 0.3 * VDDIO (High Driving PAD)
0
-10
-20
-30
-40
-50
-60
-70
2
3
4
5
6
VDD(V)
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GPCE2064A
8 APPLICATION CIRCUITS
8.1 Application Circuit with Regulator, XTAL32K Selected
1K
VMIC
RESETB
10uF
RESETB
0.1uF
3K
0.22uF
MICP
MICN
MIC
0.22uF
AUDN
AUDP
8Ω SPEAKER
3K
0.22uF
MICOUT
OPI
R32SEL
5.1K
IOA[15:0]
IOB[15:0]
IOA[15:0]
IOB[15:0]
5000pF
VDD_DAC
AGC
VDD_PDAC
470K
4.7uF
0.1uF
GPCE2064A
VDD_IOA
VDD_IOB
VDD_REG
VADREF
0.1uF
10uF
(2.4v~5.5v)
Battery
*1
*1
20 ~50pF
VSS_REG
X32I
VSS_IOA
VSS_IOB
VSS_DAC
VSS_PDAC
32768Hz
20 ~50pF
X32O
VCOIN
0.1uF
0.1uF
10uF
10uF
3.3K
V33_REG*2
V33_ADC
VDD(3.3v)
3300pF
0.1uF
VSS_ADC
GPCE2064A Application Circuit(MIC_IN )
Note1: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
Note2: VDD33_REG is output of built-in regulator with maximum current 60mA. It is recommended that only use it for internal power pad.
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Version: 1.2
GPCE2064A
8.2 Application Circuit with Regulator, Internal ROSC32K Selected
VMIC
RESETB
RESETB
0.1uF
MICP
MICN
AUDN
8Ω SPEAKER
AUDP
MICOUT
OPI
IOA[15:0]
IOB[15:0]
IOA[15:0]
IOB[15:0]
GPCE2064A
VDD_DAC
AGC
VDD_PDAC
VDD_IOA
VDD_IOB
VDD_REG
IOB[7:0]
IOB[7:0]
(8- Channel Line In)
VADREF
0.1uF
0.1uF
10uF
(2.4v~5.5v)
Battery
VSS_REG
VSS_IOA
VSS_IOB
VSS_DAC
VSS_PDAC
0.1uF
0.1uF
10uF
10uF
VCOIN
VDD(3.3v)
V33_REG
3.3K
R32SEL
3300pF
0.1uF
V33_ADC
VSS_ADC
GPCE2064A Application Circuit(LINE_IN )
Note1: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
Note2: VDD33_REG is output of built-in regulator with maximum current 60mA. It is recommended that only use it for internal power pad.
© Generalplus Technology Inc.
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Version: 1.2
GPCE2064A
8.3 Application Circuit without Regulator, XTAL32K Selected
VMIC
RESETB
RESETB
0.1uF
MICP
MICN
AUDN
AUDP
8Ω SPEAKER
R32SEL
MICOUT
OPI
IOA[15:0]
IOA[15:0]
IOB[15:0]
IOB[15:0]
GPCE2064A
VDD_DAC
AGC
VDD_PDAC
VDD_IOA
IOB[7:0]
IOB[7:0]
VDDH(2.4v~5.5v)
Battery
( 8-Channel Line In )
VDD_IOB
0.1uF
10uF
VADREF
X32I
0.1uF
VSS_IOA
VSS_IOB
VSS_DAC
VSS_PDAC
20 ~ 50pF*
VDD_REG
VSS_REG
32768Hz
20 ~ 50pF*
X32O
VDDH(2.4v~3.6v)
Battery
2.2uF
10uF
VCOIN
3.3K
V33_REG
V33_ADC
VSS_ADC
3300pF
0.1uF
0.1uF
GPCE2064A Application Circuit(LINE_IN)
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Version: 1.2
GPCE2064A
8.4 Push Pull DAC Mixed with another DAC
Rf
Internal Circuit
R2R
DAC
Req
RinA
Internal
Vsource
AUDN
Speaker
AUDP
-
3.18K
127.7K
V50/2
+
VDACO
Rf2
VEXT
CEXT
Resd
1.2K
REXT
ACIN
External
Vsource
Rin2
-
External
V50/2
+
VDACO
VEXT
VAUDN
R f
R f
R eq R inA
R EXT R ESD
VDACO
VEXT
R f
R f
3.18 K 127 .7K
R EXT 1.2K
V AUDP V AUDN
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Version: 1.2
GPCE2064A
9 PACKAGE/PAD LOCATIONS
9.1 Ordering Information
Product Number
Package Type
GPCE2064A-NnnV-C
Chip form
GPCE2064A-NnnV-QL04x
Halogen Free Package
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
Note3: Package form number (x = 1 - 9, serial number).
9.2 Package Information
LQFP 80 Outline Dimensions
Dimension in mm
Symbol
Min.
Typ.
Max.
1.60
0.15
1.45
0.27
0.16
A
A1
A2
b
-
-
0.05
1.35
0.17
0.09
-
-
-
c1
D
-
14.00 BSC
12.00 BSC
D1
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Version: 1.2
GPCE2064A
Dimension in mm
Typ.
Symbol
Min.
Max.
E
E1
e
14.00 BSC
12.00 BSC
0.50 BSC.
-
L
0.45
0.75
L1
1 REF
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Version: 1.2
GPCE2064A
10 DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or
alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
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Version: 1.2
GPCE2064A
11 REVISION HISTORY
Date
Revision #
Description
Page
Jun 02, 2016
1.2
Modify pin descriptions of chapter 5.
1. Add 5.2 PIN Map.
6
7
2. Modify 7.2 & 7.3 DC Characteristics.
3. Add 7.13 diagram.
13, 14
16
May 10, 2012
Oct. 12, 2011
1.1
1.0
4. Modify 8.3 diagram
19
5. Modify 9 PACKAGE/PAD LOCATIONS.
Original
21, 22
23
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Version: 1.2
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