GPFA64F1 [GENERALPLUS]
8--ch 64KB ROM Musiic Syntthesiizer;
| 型号： | GPFA64F1 |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 8--ch 64KB ROM Musiic Syntthesiizer |
| 文件： | 总14页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPFA64F1
8-ch 64KB ROM Music Synthesizer
Oct. 12, 2015
Version 1.0
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPFA64F1
Table of Contents
PAGE
TABLE OF CONTENTS .......................................................................................................................................................................................... 2
8-CH 64KB ROM MUSIC SYNTHESIZER ........................................................................................................................................................ 3
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3
2. BLOCK DIAGRAM ...................................................................................................................................................................................... 3
3. FEATURES.................................................................................................................................................................................................. 3
4. APPLICATION FIELDS ............................................................................................................................................................................... 3
5. SIGNAL DESCRIPTION.............................................................................................................................................................................. 4
6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 5
6.1. MEMORY MAPPING ................................................................................................................................................................................ 5
6.2. CPU ..................................................................................................................................................................................................... 5
6.3. OSCILLATOR .......................................................................................................................................................................................... 5
6.4. I/O PORT CONFIGURATION ..................................................................................................................................................................... 5
6.5. KEY AND AUTO WAKE-UP ....................................................................................................................................................................... 6
6.6. INTERRUPT............................................................................................................................................................................................ 6
6.7. GENERATION OF SPEECH AND MELODY .................................................................................................................................................. 6
6.8. POWER DOWN AND HALT MODE ............................................................................................................................................................. 6
6.9. MAIN VOLUME CONTROL FUNCTION........................................................................................................................................................ 6
6.10.AUD CONTROL FUNCTION ..................................................................................................................................................................... 6
6.11.LOW VOLTAGE RESET ............................................................................................................................................................................ 6
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................... 7
7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................... 7
7.2. DC CHARACTERISTICS........................................................................................................................................................................... 7
7.3. THE RELATIONSHIPS BETWEEN THE FOSC AND THE VDD .......................................................................................................................... 8
7.3.1. TA=25℃ .................................................................................................................................................................................... 8
7.4. THE RELATIONSHIPS BETWEEN THE VDD AND THE IOP ............................................................................................................................. 8
7.4.1. TA=25℃(internal DAC and Amplifier active)............................................................................................................................. 8
8. APPLICATION CIRCUIT ............................................................................................................................................................................. 9
8.1. GPFA64F1 APPLICATION CIRCUITS-(1): APPLICATION CIRCUIT WITHOUT EXTERNAL RESISTOR FOR VOLUME CONTROL ............................ 9
8.2. GPFA64F1 APPLICATION CIRCUITS-(2): APPLICATION CIRCUIT WITH EXTERNAL RESISTOR FOR VOLUME CONTROL ................................ 10
8.3. GPFA64F1 APPLICATION CIRCUITS-(3): APPLICATION CIRCUIT FOR MICROPHONE AUDIO INPUT ..............................................................11
9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 12
9.1. ORDERING INFORMATION ..................................................................................................................................................................... 12
10.DISCLAIMER............................................................................................................................................................................................. 13
11. REVISION HISTORY ................................................................................................................................................................................. 14
© Generalplus Technology Inc.
Proprietary & Confidential
2
Oct. 12, 2015
Version: 1.0
GPFA64F1
8-CH 64KB ROM MUSIC SYNTHESIZER
1. GENERAL DESCRIPTION
3. FEATURES
The GPFA64F1, a fully CMOS integrated circuit, adopts advanced
design and process technology to combine an 8-bit RISC
processor, an 8-channel music synthesizer, 64K bytes program
ROM, 224 bytes working SRAM, timer/counter and I/Os interface
in a single chip. The sound processing logic is a unique design
to achieve high quality melody effect. It can simulate all types of
musical instruments by programming the tone ROM and
controlling the envelope slope of each channel. Every channel
can also be defined as a speech channel to produce percussion,
animal sounds, gun-fire, explosions and other special sound
effects in PCM to accompany the main music rhythm.
8-bit microprocessor
Features 8 channel speech / melody
Operating voltage: 2.2V - 5.5V
Eight general inputs / outputs, IOAB0~7(IOAB3 is high sink)
Eight input pins, IOCD2 and IOEF0~6
Sleep signal output
Two audio output pins drive speaker directly
Watchdog mode (code option)
224 bytes SRAM
64K bytes program ROM
Power down mode with system and auto wake-up clock stop
Halt mode with system clock stop but auto wake-up clock
working
2. BLOCK DIAGRAM
Built-in 14.318MHz ROSC
Power-on reset
AUDN
Music
64KB ROM
Volume adjustment by 3-bit software control or external resistor
Key-change and auto wakeup capability
Low voltage reset
Synthesizer
AUDP
8-bit RISC
Controller
224B SRAM
IOSC
4. APPLICATION FIELDS
Electric piano
Music clock
IO Port (8-GPIO, 8-input)
Music box
Children’s storybooks
IOAB0~7
(I/O)
IOCD2
(I)
IOEF0~6
(I)
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3
Oct. 12, 2015
Version: 1.0
GPFA64F1
5. SIGNAL DESCRIPTION
Mnemonic
Type
Description
VDD1
VDD2
VDD3
VSS1
I
I
I
I
I
I
I
I
Positive supply voltage
Ground input
VSS3
RESETB
VM
Reset input, active low, internal pull high
Capacitor input ,should connect it with 0.1uF capacitor to AVSS
Capacitor input, should connect it with 50nF capacitor to AUDN
LFC
AUDN
AUDP
IOCD2
IOEF0-6
IOAB0-7
SLEEP
AVSS1
AVSS2
AVDD
O
Audio output
I
I
Data input pins
I/O
O
Programmable input/output pins
Sleep output signal
I
Analog VSS
I
Analog VDD
Note: AVDD/AVSS1-2/AUDN/AUDP pads are highly recommended to be double-bonded.
© Generalplus Technology Inc.
Proprietary & Confidential
4
Oct. 12, 2015
Version: 1.0
GPFA64F1
6. FUNCTIONAL DESCRIPTIONS
6.1. Memory Mapping
6.4. I/O Port Configuration
CPU Address
IOAB.0-7: Input/Output Port
$0000
I / O SRAM
$01FF
Logic
Control
$0200
USER_
PROGRAM_
AREA_1
$7FFF
Output
data
$8000
Buffer
USER_
Input
Data
DATA BANK
$BFFF
$C000
USER_
PROGRAM_
BANK
Logic
Control
$FFFF
Note : CPU USER_PROGRAM_AREA_1 address is the same as ROM address
output
enable
64K ROM
USER_PROGRAM_AREA_1
$0200-$7FFF
$0200-$7FFF
6.2. CPU
The 8-bit microprocessor in GPFA64F1 is a high performance
processor equipped with Accumulator, Program Counter,
IOCD.2: Input Port
X
Register, Stack pointer and Processor Status Register (this is the
same as the 6502 instruction structure). GPFA64F1 is able to
perform with 7.16MHz (max.) depending on the application
specifications.
Input Data
VDD
6.3. Oscillator
The GPFA64F1 features an internal 14.318MHz ROSC for system
clock source and it will take less cost and component for user’s
systems. In addition to 14.318MHz system clock, GPFA64F1
also features a 41KHz-ROSC that will be the auto wakeup clock
source. The wake-up frequency can be 2.5Hz, 5Hz, 10Hz and
20Hz based on the settings of bit2 and bit3 in
P_07H_SleepWakeup. Note that the 41KHz ROSC can be
activated only when the system is under sleep mode and the
related control register, P_07_SleepWakeup, bit-1 is written as “1”.
Note: *The frequency deviation for auto wake-up clock may be +-30%
IOEF.0-6: Input Port
Logic
Control
RIN
RIN
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Oct. 12, 2015
Version: 1.0
GPFA64F1
6.5. Key and Auto Wake-up
register. Thus, CPU will enter standby and the RAM and I/O
retain in their previous state until being awakened. If auto
wake-up is needed, the 41KHz ROSC enable bit,
P_07H_SleepWakeup bit-1, should be written as “1” then stop
the CPU clock but keep auto wake-up clock source activating by
writing the SLPSTAR register.
CPU waking up from sleep mode requires a wake-up signal to turn
the system clock on. The wake-up sources of GPFA64F1 include
IOEF.0-6 key change and auto wake-up.
6.6. Interrupt
The GPFA64F1 has two interrupt modes: FIQ (Fast Interrupt
Request) and IRQ (Interrupt Request). The priority of FIQ is
higher than IRQ. FIQ is the high-priority interrupt while IRQ is the
low-priority one. An IRQ can be interrupted by a FIQ, but not by
another IRQ. A FIQ cannot be interrupted by any other interrupt
source. The interrupt controller handles 7 INTs sources as
follows:
6.9. Main Volume Control Function
The main volume adjustment of GPFA64F1 provides 3-bit (8 level)
software control to adjust D/A output voltage. The software
volume control register is P_09_Vol_Ctrl bit0-2 and its default
value is #05H that is about 60% of maximum volume. Users can
adjust volume by writing different values into P_09_Vol_Ctrl bit0-2.
The larger value written, the larger volume is implemented.
Interrupt Source
Priority
6.10. AUD Control Function
Channel 3 interrupt
Channel 2 interrupt
Channel 1 interrupt
Channel 0 interrupt
T11 interrupt
IRQ
GPFA64F1 facilitates AUD output to drive speaker directly. In
order to eliminate the start-up noise, it is not allowed to turn on the
AUD enable control registers, P_00H_DACOP_EN bit0-1, at the
same time. Users should write the control registers with an
interval which is not less than 10us. The AUD turn-on procedure
should be as followings:
IRQ
IRQ
FIQ/IRQ (by program)*
IRQ
(system CLK/4096)
T8 interrupt
IRQ
IRQ
1. Set envelope data=00H, DAC data=80H.
(system CLK/512)
External interrupt
2. Set P_00H_DACOP_EN = 01H.
3. Delay 10us.
Note: *User can set the priority to be FIQ or IRQ by program.
4. Set P_00H_DACOP_EN = 03H.
6.7. Generation of Speech and Melody
If users disable AUD output, it is also not allowed to turn-off the
AUD control register at the same time, or the unexpected noise
might be generated as well. The AUD turn-off procedure should
be as follows:
The fixed address of RAM area $0020 - $005F is designed as
address pointers and
a
data buffer for the 8-channel
When a channel is defined as
speech/melody generation.
speech, user sets the 16-bit address pointer pointing to the ROM
area. The data can directly be sent to DA in direct output mode.
The EA register is used to control the volume of the speech at
AUD output. If a channel is defined as a melody channel, user
should set the channel to normal speech mode, fetch the chord
and decode the note first. After that, user should set that channel
to melody mode and select the tone ROM for programming and
controlling the envelope to choose an instrument. Then, play the
data to DA buffer in synchronous rhythm with the change of the
time base (tempo).
1. Set envelope data=00H, DAC data=80H.
2. Set P_00H_DACOP_EN = 01H.
3. Delay 10us.
4. Set P_00H_DACOP_EN = 00H.
6.11. Low Voltage Reset
The Low Voltage Reset (LVR), prevents system running into
malfunction state, will intend to reset all functions back to the initial
states if the system power drops extremely low.
6.8. Power Down and Halt Mode
GPFA64F1 supports a power saving mode for those applications
requiring very low stand-by current. Simply enables the wake-up
sources, and then stops the CPU clock by writing the SLPSTAR
© Generalplus Technology Inc.
Proprietary & Confidential
6
Oct. 12, 2015
Version: 1.0
GPFA64F1
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics
Symbol
Ratings
DC Supply Voltage
Input Voltage Range
Operating Temperature
Storage Temperature
VDD
VIN
< 7.0V
-0.5V to VDD + 0.5V
0℃ to +60℃
TA
-50℃ to +150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Ratings table may cause permanent damage to the device. For normal operational conditions
see AC/DC Electrical Characteristics.
7.2. DC Characteristics
Limit
Characteristics
Operating Voltage
Symbol
Unit
Test Condition
Min.
Typ.
Max.
VDD
IOP1
2.2
-
12.1
6.2
5.5
V
-
-
-
-
-
-
-
-
mA
mA
mA
mA
A
FCPU = 7.16MHz @ 5.0V, no load
FCPU = 7.16MHz @ 3.0V, no load
FCPU = 7.16MHz @ 5.0V, no load
FCPU = 7.16MHz @ 3.0V, no load
VDD = 5.0V
Operating Current-1
(internal DAC and Amplifier active)
Operating Current-2
-
6.0
-
-
IOP2
(internal DAC and Amplifier inactive)
2.3
Standby Current
OSC Frequency
ISTBY
-
3.0
-
VDD = 3.3V@25℃
FOSC2
14.318
MHz
(FOSC2 (VDD_CORE)-14.318Mhz)
/14.318MHz, VDD_CORE =3.3V,
For Internal OSC
⊿FOSC2
/
Frequency lot deviation
-3.5
-
3.5
%
FOSC2
Input High Level
Input Low Level
Output High Current
(IOAB[7:0])
VIH
VIL
0.7*VDD
-
-
V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.3*VDD
V
-
15.7
6.7
-
-
-
-
-
-
-
-
-
-
-
mA
VDD = 5.0V, VOH = 4.0V
VDD = 3.0V, VOH = 2.4V
VDD = 5.0V, VOL = 1.0V
VDD = 3.0V, VOL = 0.6V
VDD = 5.0V, VOL = 1.0V
VDD = 3.0V, VOL = 0.6V
VDD = 5.0V, VIN = VDD
VDD = 3.0V, VIN = VDD
VDD = 5.0V, VIN = VDD
VDD = 3.0V, VIN = VDD
VDD = 3.3V@25℃
IOH
mA
Output Sink Current
(IOAB[7:4,2:0])
40.0
18.0
55.1
25.6
110
225
110
225
7.16
mA
IOL
mA
mA
Output Sink Current
(IOAB[3])
IOL
mA
Input Pull-Low Resistor
(IOEF[6:0])
Kohm
Kohm
Kohm
Kohm
MHz
RPL
Input Pull-Low Resistor
(IOCD2)
RPL
CPU Clock
FCPU
© Generalplus Technology Inc.
Proprietary & Confidential
7
Oct. 12, 2015
Version: 1.0
GPFA64F1
7.3. The Relationships between the FOSC and the VDD
7.4. The Relationships between the VDD and the IOP
7.3.1. TA=25℃
7.4.1. TA=25℃(internal DAC and Amplifier active)
16000
14000
12000
10000
14
12
10
8
Iop(mA)
Fosc(KHz)
8000
6000
4000
2000
0
6
4
2
0
1
2
3
4
5
6
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VDD(V)
VDD(V)
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Version: 1.0
GPFA64F1
8. APPLICATION CIRCUIT
8.1. GPFA64F1 Application Circuits-(1): Application Circuit without External Resistor for Volume Control
Reset Switch
AVDD
VM
+ C1
C6
C2
-
RESETB
0.1
100
0.1
AVSS1-2
C4 0.1
VSS1/VSS3
C5
0.1
GPFA64F1
VDD1-3
AUDP
AUDN
Speaker
IOAB[7:0]
IOCD[2]
IOAB[7:0]
C3
50n
IOCD[2]
LFC
IOEF[6:0]
SLEEP
IOEF[6:0]
SLEEP
Notes:
1. VDD1-3, AVDD must connect to power input port directly.
2. VSS1/VSS3, AVSS1-2 must connect to power input port directly.
3. For system stability, it is recommended to connect capacitors as illustrated. It is not allowed
to remove C1~C3 due to possible performance or function issue. C4~C6 may be ignored
depending on applications and PCB layout.
4. It is recommended C1=100uF but users could try other values depending on the application.
5. If C5/C6 used, C5/C6 should be as close as possible to VDD1-3、VSS1/VSS3 and AVDD、AVSS1-2.
© Generalplus Technology Inc.
Proprietary & Confidential
9
Oct. 12, 2015
Version: 1.0
GPFA64F1
8.2. GPFA64F1 Application Circuits-(2): Application Circuit with External Resistor for Volume Control
Reset Switch
AVDD
VM
+ C1
C6
C2
RESETB
-
0.1
100
0.1
AVSS1-2
C4 0.1
VSS1/VSS3
C5
0.1
GPFA64F1
VDD1-3
AUDP
AUDN
Speaker
IOAB[7:0]
IOCD[2]
IOAB[7:0]
5K
IOCD[2]
C3 50n R1
IOEF[6:0]
SLEEP
IOEF[6:0]
SLEEP
LFC
Notes:
1. VDD1-3, AVDD must connect to power input port directly.
2. VSS1/VSS3, AVSS1-2 must connect to power input port directly.
3. For system stability, it is recommended to connect capacitors as illustrated. It is not allowed
to remove C1~C3 due to possible performance or function issue. C4~C6 may be ignored
depending on applications and PCB layout.
4. It is recommended C1=100uF but users could try other values depending on the application.
5. If C5/C6 used, C5/C6 should be as close as possible to VDD1-3、VSS1/VSS3 and AVDD、AVSS1-2.
6. Connecting variable resistor, R1(max.=5K), between LFC and AUDN for volume control
© Generalplus Technology Inc.
Proprietary & Confidential
10
Oct. 12, 2015
Version: 1.0
GPFA64F1
8.3. GPFA64F1 Application Circuits-(3): Application Circuit for Microphone Audio Input
Reset Switch
AVDD
+ C1
C6
VM
C2
-
RESETB
0.1
100
0.1
AVSS1-2
C4 0.1
VSS1/VSS3
C5
0.1
GPFA64F1
VDD1-3
AUDP
AUDN
Speaker
IOAB[7:0]
IOCD[2]
IOAB[7:0]
C3
50n
IOCD[2]
LFC
IOEF[6:0]
SLEEP
IOEF[6:0]
SLEEP
VDD
SLEEP
1K
270K
3K
10u
6
1
4
3
5
GPY0032
2K
1K
0.22u
VSS
8
NC
VDD
7
2
1u
Microphone
VSS
Notes:
1. VDD1-3, AVDD must connect to power input port directly.
2. VSS1/VSS3, AVSS1-2 must connect to power input port directly.
3. For system stability, it is recommended to connect capacitors as illustrated. It is not allowed
to remove C1~C3 due to possible performance or function issue. C4~C6 may be ignored
depending on applications and PCB layout.
4. It is recommended C1=100uF but users could try other values depending on the application.
5. If C5/C6 used, C5/C6 should be as close as possible to VDD1-3、VSS1/VSS3 and AVDD、AVSS1-2.
6. For microphone audio input application, external circuit is as illustrated. The SHUTDOWN
signal to GPY0032 could be GPFA120F1 SLEEP output.
© Generalplus Technology Inc.
Proprietary & Confidential
11
Oct. 12, 2015
Version: 1.0
GPFA64F1
9. PACKAGE/PAD LOCATIONS
9.1. Ordering Information
Product Number
Package Type
GPFA64F1-NnnV-A
Chip form
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
© Generalplus Technology Inc.
Proprietary & Confidential
12
Oct. 12, 2015
Version: 1.0
GPFA64F1
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
Proprietary & Confidential
13
Oct. 12, 2015
Version: 1.0
GPFA64F1
11. REVISION HISTORY
Date
Revision #
Description
Page
Oct. 12, 2015
1.0
Original
14
© Generalplus Technology Inc.
Proprietary & Confidential
14
Oct. 12, 2015
Version: 1.0
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