GPL16218B-NnnV-C [GENERALPLUS]
Advanced Game / ELA SoC with ïu nSP 2.0;
| 型号： | GPL16218B-NnnV-C |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | Advanced Game / ELA SoC with ïu nSP 2.0 |
| 文件： | 总21页 (文件大小：1120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPL16218B
Advanced Game / ELA SoC with
’nSP® 2.0
Nov. 21, 2016
Version 1.0
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPL16218B
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 4
2. BLOCK DIAGRAM ...................................................................................................................................................................................... 4
3. FEATURES.................................................................................................................................................................................................. 4
4. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5
4.1. PAD ASSIGNMENT ................................................................................................................................................................................. 9
4.2. PIN MAP.............................................................................................................................................................................................. 10
5. FUNCTIONAL DESCRIPTIONS................................................................................................................................................................ 11
5.1. CPU ....................................................................................................................................................................................................11
5.2. MEMORY ..............................................................................................................................................................................................11
5.2.1. Internal SRAM..........................................................................................................................................................................11
5.2.2. External memory......................................................................................................................................................................11
5.3. PLL, CLOCK, POWER MODE..................................................................................................................................................................11
5.3.1. PLL (Phase Lock Loop)............................................................................................................................................................11
5.3.2. System Clock...........................................................................................................................................................................11
5.4. POWER SAVINGS MODE ........................................................................................................................................................................11
5.5. PICTURE PROCESS UNIT (PPU) ............................................................................................................................................................11
5.6. SOUND PROCESS UNIT ........................................................................................................................................................................ 12
5.7. VIDEO OUTPUT INTERFACE................................................................................................................................................................... 12
5.7.1. STN-LCD Interface ................................................................................................................................................................. 12
5.7.2. TFT-LCD Interface .................................................................................................................................................................. 12
5.7.3. TV encoder ............................................................................................................................................................................. 12
5.8. INTERRUPT.......................................................................................................................................................................................... 12
5.9. GPIO.................................................................................................................................................................................................. 12
5.10.TIMER / COUNTER................................................................................................................................................................................ 12
5.11.WATCHDOG ......................................................................................................................................................................................... 12
5.12.SERIAL INTERFACE............................................................................................................................................................................... 13
5.12.1. Serial Peripheral Interface (SPI)......................................................................................................................................... 13
5.12.2. USB Device Function ......................................................................................................................................................... 13
5.13.IDE TOOLS FUNCTION ......................................................................................................................................................................... 13
5.14.SD/MMC CONTROLLER ....................................................................................................................................................................... 13
5.15.REAL TIME CLOCK (RTC)..................................................................................................................................................................... 13
5.16.ANALOG CONTROL............................................................................................................................................................................... 13
5.16.1. DAC Control ....................................................................................................................................................................... 13
6. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 14
6.1. ABSOLUTE MAXIMUM RATING ............................................................................................................................................................... 14
6.2. DC CHARACTERISTICS......................................................................................................................................................................... 14
6.3. VIDEO DAC CHARACTERISTICS............................................................................................................................................................ 14
6.4. AUDIO DAC CHARACTERISTICS............................................................................................................................................................ 15
6.5. REGULATOR CHARACTERISTICS............................................................................................................................................................ 15
7. RECOMMENDED BOARD LAYOUT......................................................................................................................................................... 16
7.1. POWER AND GROUND .......................................................................................................................................................................... 16
7.2. CRYSTAL AND PLL ............................................................................................................................................................................... 16
© Generalplus Technology Inc.
Proprietary & Confidential
2
Nov. 21, 2016
Version: 1.0
GPL16218B
7.3. ANALOG SECTION................................................................................................................................................................................ 16
8. APPLICATION CIRCUIT.................................................................................................................................................................................. 17
8.1. FOR TV PLUG-AND-PLAY SIMPLE ELA/GAME 2D APPLICATION .............................................................................................................. 17
9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 18
9.1. ORDERING INFORMATION ..................................................................................................................................................................... 18
9.2. PACKAGE INFORMATION ....................................................................................................................................................................... 18
10.DISCLAIMER............................................................................................................................................................................................. 20
11. REVISION HISTORY ................................................................................................................................................................................. 21
© Generalplus Technology Inc.
Proprietary & Confidential
3
Nov. 21, 2016
Version: 1.0
GPL16218B
Advanced Game / ELA SoC with
’nSP® 2.0
1. GENERAL DESCRIPTION
3. FEATURES
The Generalplus GPL16218B is highly integrated system-on-a
’nSP® 2.0 16-bit CPU with frequency up to 96MHz.
4K bytes I-cache.
chip and it targets
a
cost-effective, high performance
micro-controller solution for game, education and e-learning
applications. It embeds ’nSP® 2.0 (16-bit CPU developed by
Sunplus Technology) with 4KB I-cache, picture process unit (PPU),
TV encoder with QVGA output, 16 channels sound process unit
(SPU), ROM/SRAM/NOR FLASH controller, two channel DMA
controller, six-channel 16-bit timers, SD/MMC memory interface,
USB device, mono STN-LCD and TFT-LCD interface, interrupt
controller, SPI master controller, programmable I/O ports, 16-bit
DAC for audio playback, PLL, de-flicker, divider and embedded
12K*16 bits SRAM, and 4K*16 ROM, all in a single compact
Integrated circuit.
12k*16 bits SRAM for programming or LCD frame buffers.
4K*16 bits ROM for boot code.
Picture Process Unit (PPU)
Four Text layers + 256 Sprites
QVGA output
Line base or Frame base operation
De-flicker for TV output
Up-to 4096x4096 Text Size
Alpha-channel sprite
Sound Process Unit (SPU)
Sixteen hardware PCM/ADPCM channels
Built-in sound compressor
By providing a complete set of common system peripherals, the
Generalplus GPL16218B chip minimizes overall system costs and
eliminates the need to configure additional components. The
GPL16218B provides not only the high-speed performance and
low cost for a system, but it also integrates several powerful tools
into the development system, such as development system with C
language, assembly compiler, linker, source debugger functions
and project management tools.
Static memory controller. (ROM/SRAM/NOR FLASH/Page
Memory)
Two-channel DMA controller.
Mono and 16 gray STN-LCD controller.
TFT-LCD controller which can be UPS051(serial RGB),
UPS052(serial RGB dummy), parallel RGB, i80(8-bit/16-bit
system bus) I/F type, and CCIR601/CCIR656.
29 sources Interrupt Controller.
Universal Serial Bus (USB) 2.0 full speed compliant device
with built-in transceiver.
2. BLOCK DIAGRAM
Watch-dog timer.
32-bit by 32-bit signed divider
ROM/RAM/
NOR FLASH
Controller
Real-time clock.
Deflicker
2-ch DMA
SPI Master
Six 16-bit timers.
SD/MMC memory interface.
USB
device
6 Timers
SPI master interface.
Controller
51 Programmable general I/O ports with pull-high/low control.
Power manager.
16-ch SPU
’nSP™ 2.0
With ICE
USB Transceiver
2K*16 I-Cache
SRAM 12K*16
ROM 4K*16
System Control
Built-in 3.0V to 1.8V Regulator.
Low voltage reset.
PPU
RTC
PLL
Regulator
16-bit DACx2
Signed divider
96MHz, 27MHz and 12MHz PLL.
16-bit stereo DAC(2ch) for audio playback.
TV encoder which support NTSC/PAL output.
TV Encoder
STN/TFT-LCD
SD/MMC Controller
© Generalplus Technology Inc.
Proprietary & Confidential
4
Nov. 21, 2016
Version: 1.0
GPL16218B
4. SIGNAL DESCRIPTIONS
Left Side
No
Package No
Name
Group
Type
Normal Function Description
GPIO Group
1
2
DVSS
BKCSB0
XA3
Digital GND
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Digital PWR
Digital GND
Digital PWR
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Digital GND
MODE
P
Digital ground
2
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
External memory chip select 0
External memory address pin 3
External memory address pin 2
External memory address pin 1
External memory chip select 1
External memory address pin 0
External memory address pin 10
External memory address pin 11
External memory chip select 2
External memory address pin 12
External memory address pin 13
External memory address pin 14
3.3V digital power
IOD0
3
4
4
5
XA2
5
6
XA1
6
7
BKCSB1
XA0
IOD1
IOD2
7
8
8
9
XA10
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
XA11
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
BKCSB2
XA12
XA13
XA14
DVCC33
DVSS
DVCC18
BKWEB
BKOEB
XA15
P
Digital ground
P
1.8V digital power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
External memory write enable pin
External memory output enable pin
External memory address pin 15
External memory address pin 16
External memory address pin 17
External memory address pin 18
External memory address pin 19
External memory address pin 20
External memory address pin 21
External memory address pin 22
External memory address pin 23
Digital ground
IOD7
IOD8
XA16
XA17
IOD9
XA18
IOD10
IOD11
IOD12
IOD13
IOD14
IOD15
XA19
XA20
XA21
XA22
XA23
DVSS
TEST
I
Test mode control signal. Input floating; it must
be tied with ground under normal operation.
© Generalplus Technology Inc.
Proprietary & Confidential
5
Nov. 21, 2016
Version: 1.0
GPL16218B
Bottom Side
No
Package No
Name
Group
Type
Normal Function Description
GPIO Group
30
31
31
32
RESETB
IOB2
SYSTEM
MODE
I/O
I/O
Reset input pin. (Low active)
BM2: Boot mode selection pin 2.
IOB2
(0: use 6MHz crystal, usually for TV application,
1: use internal PLL, usually for other application w/o TV)
32
33
IOB1
MODE
I/O
BM1: Boot mode selection pin 1.
1 : Internal ROM Boot (SPI boot)
IOB1
IOB0
0 : Chip Select 0 Memory Boot
BM0: Boot mode selection pin 0.
(This pin must be pull low with a resistor)
Embedded ICE data pin. Default is floating.
In development phase, connect it with a capacitor to GND.
In production phase, connect it with a resistor to GND.
Embedded ICE clock pin. Default is floating.
In development phase, connect it with a capacitor to GND.
In production phase, connect it with a resistor to GND.
TFT-LCD’s D7
33
34
34
35
IOB0
MODE
ICE
I/O
I/O
ICEDA
35
36
ICECK
ICE
O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
IOA7
IOA6
Key/LCD
Key/LCD
Key/LCD
Key/LCD
Key/LCD
Key/LCD
Key/LCD
Key/LCD
Key/LCD
Digital PWR
Digital GND
Digital PWR
Key/LCD
Key/LCD
Key/LCD
Key/LCD
Key/LCD
Key/LCD
Key/LCD
SD2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOA7
IOA6
IOA5
IOA4
IOA3
IOA2
IOA1
IOA0
IOA8
TFT-LCD’s D6
IOA5
TFT-LCD’s D5
IOA4
TFT-LCD’s D4
IOA3
TFT-LCD’s D3
IOA2
TFT-LCD’s D2
IOA1
TFT-LCD’s D1
IOA0
TFT-LCD’s D0
IOA8
TFT-LCD’s D8
DVCC33
DVSS
DVCC18
IOA9
PWR 3.3V digital power
PWR Digital ground
PWR 1.8V digital power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TFT-LCD’s D9
TFT-LCD’s D10
TFT-LCD’s D11
TFT-LCD’s D12
TFT-LCD’s D13
TFT-LCD’s D14
TFT-LCD’s D15
SD2 data0
IOA9
IOA10
IOA11
IOA12
IOA13
IOA14
IOA15
IOC8
IOA10
IOA11
IOA12
IOA13
IOA14
IOA15
IOC8
IOC7
SD2
SD2 clock
IOC7
IOC6
SD2
SD2 command
SD2 data2
IOC6
IOC10
IOC9
SD2
IOC10
IOC9
SD2
SD2 data1
IOC5
SD2
SD2 data3
IOC5
IOC11
IOC12
PLLV33
X32KO
X32KI
Key change A input
Key change B input
IOC11
IOC12
Key change A
Key change B
PLL
PWR 3.3V PLL power
PLL
O
I
32768 Hz crystal output pin
32768 Hz crystal input pin
PLL
© Generalplus Technology Inc.
Proprietary & Confidential
6
Nov. 21, 2016
Version: 1.0
GPL16218B
Right Side
No
Package No
Name
Group
Type
Normal Function Description
GPIO Group
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
PLLVSS
X6MI
PLL
PLL
PWR
A/I
PLL ground
6MHz crystal input pin or 12M PLL filter pin
6MHz crystal output pin
1.8V power for PLL
X6MO
PLLV18
DVSS
PLL
O
PLL
P
Digital GND
DAC
PWR
A/O
A/O
PWR
A/O
PWR
PWR
A/I
Digital ground
DACOL
DAVREF
AVSS
Left channel audio output
DAC reference voltage pin
DAC ground
DAC
DAC
DACOR
AVDD
DAC
Right channel audio output
3.3V DAC power
DAC
VAVSS
VDVREF
VRSET
VCBU
VCBL
VDAC
VDAC
VDAC
VDAC
VDAC
VDAC
VDAC
Regulator
Regulator
Regulator
Digital PWR
Digital GND
SPI
VDAC ground
Video DAC reference voltage
Video DAC current source adjustment
Video DAC reference voltage
Video DAC reference voltage
Video DAC output
IOE2
IOE1
A/I
A/I
A/I
VAOUT
VAVDD
DVCC33
DVSS
A/O
PWR
PWR
PWR
A/O
PWR
PWR
I/O
IOE0
3.3V VDAC power
3.3V Regulator power
Regulator ground
DVCC18
DVCC18
DVSS
Regulator 1.8V output
1.8V digital power
Digital ground
IOB7
SPIRX: SPI data input
SPITXD: SPI data output
SPICLK: SPI clock
IOB7
IOB6
IOB5
IOB3
IOB6
SPI
I/O
IOB5
SPI
I/O
IOB3
LCD
I/O
TFT DCLK
DVCC33
AVCC33
DP
Digital PWR
USB
PWR
PWR
I/O
3.3V digital power
3.3V USB power
USB
DP pin of USB PHY
DN pin of USB PHY
DN
USB
I/O
© Generalplus Technology Inc.
Proprietary & Confidential
7
Nov. 21, 2016
Version: 1.0
GPL16218B
Top Side
No
Package No
Name
Group
Type
Normal Function Description
GPIO Group
96
97
AVSS
DVSS
IOB8
XD7
USB
PWR
PWR
I/O
USB ground
97
98
Digital GND
EINT
Digital ground
98
99
External INT0; Light gun input
External memory data pin 7
External memory data pin 6
External memory data pin 5
External memory data pin 4
External memory data pin 3
External memory data pin 2
External memory data pin 1
External memory data pin 0
External memory data pin 15
3.3V digital power
IOB8
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
1
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Digital PWR
Memory I/F
Memory I/F
Memory I/F
Digital GND
Digital PWR
Memory I/F
Memory I/F
Memory I/F
Digital PWR
Memory I/F
General I/O
General I/O
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
Memory I/F
I/O
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
XD6
I/O
XD5
I/O
XD4
I/O
XD3
I/O
XD2
I/O
XD1
I/O
XD0
I/O
XD15
DVCC33
XD14
XD13
XD12
DVSS
DVCC18
XD11
XD10
XD9
I/O
PWR
I/O
External memory data pin 14
External memory data pin 13
External memory data pin 12
Digital ground
I/O
I/O
PWR
PWR
I/O
1.8V digital power
External memory data pin 11
External memory data pin 10
External memory data pin 9
3.3V digital power
I/O
I/O
DVCC33
XD8
PWR
I/O
External memory data pin 8
General-purposed I/O C0
General-purposed I/O C1
External memory address pin 9
External memory address pin 8
External memory address pin 7
External memory chip select 4
External memory address pin 6
External memory address pin 5
External memory address pin 4
External memory chip select 3
IOC0
IOC1
XA9
I/O
IOC0
IOC1
I/O
I/O
XA8
I/O
XA7
I/O
BKCSB4
XA6
I/O
IOD4
IOD3
I/O
XA5
I/O
XA4
I/O
BKCSB3
I/O
© Generalplus Technology Inc.
Proprietary & Confidential
8
Nov. 21, 2016
Version: 1.0
GPL16218B
4.1. PAD Assignment
This IC substrate should be connected to VSS
Note1: To assure IC functions properly, please bond all of VDD and VSS pins.
Note2: The 0.1F capacitor between VDD and VSS should be placed to IC as closed as possible.
© Generalplus Technology Inc.
Proprietary & Confidential
9
Nov. 21, 2016
Version: 1.0
GPL16218B
4.2. Pin Map
Package Pin Sequence - LQFP 128 Package Top View
BKCSB3
DN
DP
DVSS
BKCSB0
XA3
AVCC33
DVCC33
IOB3
XA2
IOB5
XA1
IOB6
BKCSB1
XA0
IOB7
DVSS
DVCC18
XA10
XA11
DVCC18
DVSS
BKCSB2
XA12
DVCC33
VAVDD
XA13
XA14
GPL16218A
VAOUT
VCBL
DVCC33
DVSS
LQFP128
VCBU
DVCC18
BKWEB
VRSET
VDVREF
VAVSS
AVDD
BKOEB
XA15
XA16
XA17
XA18
XA19
XA20
XA21
XA22
XA23
DVSS
TEST
RESETB
IOB2
DACOR
AVSS
DAVREF
DACOL
DVSS
PLLV18
X6MO
X6MI
PLLVSS
X32KI
X32KO
© Generalplus Technology Inc.
Proprietary & Confidential
10
Nov. 21, 2016
Version: 1.0
GPL16218B
5. FUNCTIONAL DESCRIPTIONS
5.1. CPU
5.4. Power Savings Mode
The GPL16218B is equipped with a 16-bit ’nSP™ 2.0, a powerful
16-bit microprocessor by SUNPLUS and pronounced as
micro-n-SP. Sixteen registers are involved in ’nSP™ 2.0: R1 -
R4 (General-purpose registers), PC (Program Counter), SP (Stack
Pointer), Base Pointer (BP), SR (Segment Register) and R8 - R15
(General-purpose register). The interrupts include three FIQs
(Fast Interrupt Request) and eight IRQs (Interrupt Request), plus
one software-interrupt, BREAK. GPL16218B is also built-in a 4K
bytes I-cache which is able to boost the performance significantly.
The GPL16218B provide four power savings modes: Normal, Wait,
Halt and Sleep. The following table indicates the function
operating status in these modes.
Mode
Normal
Wait
CPU System RTC POWEREN After wakeup
ON
ON
ON
ON
ON
ON
ON
-
OFF
OFF
OFF
OFF
Next Instruction
Reset CPU
Halt
OFF
OFF
OFF
ON
OFF
OFF
OFF
Halt2
Sleep
ON
Next Instruction
Reset System
OFF
5.2. Memory
Enter the Wait/Halt/Halt2/Sleep mode, is done by writing
designated value to specific port. Possible wake-up triggers are
interrupt, timer, or key-status changes.
5.2.1. Internal SRAM
The amount of SRAM is a 12K-word (stack included), ranged from
0x0000 through 0x2FFF with access speed of one CPU clock
cycle. Since this SRAM is located in CPU’s local bus, the system
bus will not be taken over when this SRAM is accessed by CPU.
This SRAM can be accessed freely by CPU/PPU/DMA /LCD.
5.5. Picture Process Unit (PPU)
GPL16218B equips a powerful process engine which has the
following features.
Item
Features
5.2.2. External memory
Text
1. Maximum 4 text layers at the same time.
2. Supports text size up to 4096x4096.
3. Supports Text rotate and scale effect.
4. Supports horizontal/vertical compression effect.
5. Supports horizontal movement effect.
6. Supports 64-level alpha blending.
The memory space is separated into 5 banks; each bank can be
up to 256 pages, and 64K words per page. The controller can
support up to 80M words of NOR flash memories. Each bank
can be programmed as ROM/SRAM/NOR Flash.
Layer
5.3. PLL, Clock, Power Mode
5.3.1. PLL (Phase Lock Loop)
Sprite
1. Maximum 256 sprites at the same time.
2. Each sprite supports 64-level rotate function.
3. Each sprite supports 64-level zoom in/out
function from 1/32 to 8.75 times.
There are three PLLs embedded in GPL16218B: 1st PLL pumping
up to 96MHz, 2nd to 27MHz, and 3rd PLL up to 12MHz. The
output frequency of fast PLL is programmable and ranged from
15MHz ~ 96MHz (3MHz per step).
4. Each sprite supports 64-level alpha blending.
5. Each sprite supports 3 kinds of mosaic effect.
6. Supports alpha channel function.
7. All above functions can combine at the same
time.
5.3.2. System Clock
The system clock can be selected from 32768 or 12M or 96M
(determined by fast PLL’s output frequency) by register setting.
Furthermore, a clock divider, which can divide clocks up to 1/128,
is provided to reduce power consumption.
Color
1. Text layer and sprites support 4/16/64/256-color
palette and RGB1555/RGB565/YUYV/RGBG
bitmap mode.
2. 1024 palette entry for text layers and sprites.
3. Supports 16/24-bit level of palette index color.
1. Supports QVGA at line/frame base mode.
Operation
Mode
Other
1. Supports light gun interface.
2. Supports sprite DMA function.
3. Supports de-flicker for TV output.
Features
© Generalplus Technology Inc.
Proprietary & Confidential
11
Nov. 21, 2016
Version: 1.0
GPL16218B
5.6. Sound Process Unit
Buffer(R)
GPL16218B equips a 16-channel SPU and each channel of SPU
Port_Data(W)
Port_Buffer(W)
Port_DIR(R/W)
Port_ATTR(R/W)
supports PCM8/PCM16/ADPCM36.
A
dynamic volume
Register
pull high
Pin pad
compressor is also embedded to magnify the overall volume. For
software application, GPL16218B is also capable for wide-band
(sample rate >= 16kHz) low bit rate algorithm.
Control
logic
pull low
5.7. Video Output Interface
5.7.1. STN-LCD Interface
Data(R)
The STN-LCD driver interface built-in GPL16218B supports up-to
320 X 240 LCD panel and supports 1/4 bits data bus for
monochrome/gray-scale STN. Memory interface type CSTN is
also supported.
5.10. Timer / Counter
The GPL16218B provides six 16-bit timers/counters, TimerA to
TimerF. The clock source of each timer can be set individually.
For Timer A to TimerD, an INT will be sent to CPU when timer
overflows. Besides, Capture, Comparison and PWM functions
are also provided by TimerA/TimerB/TimerC.
5.7.2. TFT-LCD Interface
The GPL16218B supports TFT-LCD controller.
The LCM
interface includes parallel RGB (5-6-5), serial delta RGB, serial
stripe RGB, CPU (MPU) type, and CCIR601/CCIR656. The
horizontal resolution reaches up to 320 pixels, and the vertical
resolution up to 240 pixels. The TFT controller mainly provides 4
timing control pins and 8 or 16 data pins to control external TFT
panel and they are VSYNC, HSYNC, DE, DCLK, and DATA.
Clock Source A
Fosc/2
Clock Source B
2048Hz
1024Hz
256Hz
Fosc/256
32768Hz
8192Hz
Time Base B
Time Base A
0
4096Hz
1
5.7.3. TV encoder
Another Timer
INT1
1
The GPL16218B supports TV composite output. Both NTSC and
PAL outputs are supported. The output resolution can be up to
640 x 480. A 10-bit video DAC is also embedded in GPL16218B
which can utilize minimum system cost and best performance.
INT2
The GPL16218B is embedded with a time base controller which is
used to generate the slow and precisely interrupt form 32768Hz
crystal. The following table shows the available time base.
5.8. Interrupt
TimeBase A
TimeBase B
8Hz
TimeBase C
128Hz
The GPL16218B has 29 interrupt sources, grouped into two types,
FIQ (Fast Interrupt Request) and IRQ (Interrupt request). The
priority of FIQ is higher than IRQ. FIQ is the high-priority interrupt
while IRQ is the low-priority one. An IRQ can be interrupted by a
FIQ, but not by another IRQ. A FIQ cannot be interrupted by any
other interrupt sources. Some of the interrupt sources can be
programmed as FIQ or IRQ via register settings.
--
1Hz
2Hz
4Hz
16Hz
256Hz
32Hz
512Hz
64Hz
1024Hz
5.11. Watchdog
The purpose of watchdog is to monitor if the system operates
normally. Within a certain period of time, watchdog must be
cleared. If not, CPU assumes the program has been running into
an abnormal condition. Thus, CPU will reset the system to the
initial state and start running the program all over again. In
GPL16218B, the clear period is software programmable. If
watchdog is cleared before expired, the system will not be reset.
5.9. GPIO
Five I/O ports are built in GPL16218B: IOA, IOB, IOC, IOD, and
IOE. Each I/O pin has its normal function and is described in the
signal description section. When the normal function of the I/O is
disabled, it will switch to GPIO function automatically. The
following diagram is a GPIO schematic.
© Generalplus Technology Inc.
Proprietary & Confidential
12
Nov. 21, 2016
Version: 1.0
GPL16218B
5.12. Serial Interface
SCLK
5.12.1. Serial Peripheral Interface (SPI)
The SPI interface is a master interface that enables synchronous
serial communication with slave/master peripherals. Two 8-byte
FIFOs are used for transmitting and receiving data. Four types of
timings are supported and shown in the following diagram.
SFRM
SSPRXD
Q
MSB
MSB
LSB
LSB
Q
SSPTXD
SSPOE
8 bits
SCLK
SFRM
SPO = 1, SPH = 1
SSPRXD
SSPTXD
MSB
MSB
LSB
LSB
Q
5.12.2. USB Device Function
GPL16218B provides USB device function which is compatible
with USB 1.1 and USB 2.0 full speed standard. An USB
transceiver is built-in for devices function. A FIFO with size of
128x8 is used for bulk-in and bulk-out transfer and an 8-byte FIFO
is used for pipe transfer control. Interrupt IN/OUT pipes are also
supported. The DMA transfer is enabled for bulk-in/out to
maximize the transfer performance.
8 bits
SSPOE
SPO = 0, SPH = 0
SCLK
5.13. IDE Tools Function
SFRM
The functions of IDE include the follows:
1). C compiler, Assembly, and Linker
2). Single step trace
SSPRXD
Q
MSB
MSB
LSB
LSB
Q
3). Break point (break point for debugging)
4). Run (execute)
SSPTXD
SSPOE
8 bits
5.14. SD/MMC Controller
GPL16218B provides SD/MMC controllers which is compatible
with MMC system specification version 2.3 and SD Memory Card
specification 1.1. The controller supports automatically CRC
generation and check, 1-bit and 4-bit transfer, interrupt generation
when buffer empty/full, DMA transfer for page read/write.
SPO = 0, SPH = 1
SCLK
SFRM
5.15. Real Time Clock (RTC)
The RTC block provides the alarm function, schedule function,
and hour/minute/second/half-second interrupt function.
SSPRXD
MSB
LSB
LSB
Q
SSPTXD
SSPOE
MSB
5.16. Analog Control
5.16.1. DAC Control
8 bits
A 16-bit stereo DAC (2ch) is embedded in GPL16218B. For both
left and right channels, a 16x16 FIFO is used to prevent sound
glitch when CPU is busy. The left and right channels do not need
to have the same sample rate. A single DMA channel can utilize
the stereo playback.
SPO = 1, SPH = 0
© Generalplus Technology Inc.
Proprietary & Confidential
13
Nov. 21, 2016
Version: 1.0
GPL16218B
6. ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Rating
Rating
Symbol
Value
Unit
Supply Voltage 1
DVCC33
PLL_V33
AVDD
DVCC18
PLL_V18
VIN
-0.3 to 4.0
V
Supply Voltage 2
Supply Voltage 3
-0.3 to 4.0
V
V
-0.3 to 2.16
Input Voltage
-0.3 to 4.0
0 to 70
V
℃
℃
Operating Temperature
Storage Temperature
TA
TSTG
-40 to +150
6.2. DC Characteristics
Limits
Typ.
Characteristic
Symbol
Unit
Condition
Min.
Max.
3.6
Operating Voltage 1
DVCC33
PLL_V33
AVDD
DVCC18
PLL_V18
IOP
2.7/3.01
2.7
3.0
3.0
1.8
V
V
V
-
-
-
Operating Voltage 2
Operating Voltage 3
3.3
1.62
1.98
1002
803
-
mA
A
@96MHz, 3.3V, all clocks on
-
-
Operating Current
Power Down Current
High Input Voltage
Low Input Voltage
Crystal Frequency 1
Crystal Frequency 2
System Clock
IPD
1003
Sleep Mode@1.5V
-
-
-
-
-
-
VIH
0.7DVDD33
DVDD33
V
-
VIL
VSS
0.8
-
V
-
-
-
32768
6.04
48
Hz
-
FCRYSTAL
FSYS
MHz
MHz
256Hz5
96
Note1: When USB function is enabled, the minimum voltage of DVCC33/PLL_V33 is 3.0V.
Note2: Operating current depends on software code. In this test case, the following macro is turned on: Video DAC, Audio DAC, 96MHz PLL and 27MHz PLL.
Note3: Regulator is in sleep mode.
Note4: 6M Crystal is needed when USB function or TV function is enabled.
Note5: By setting clock divider and changing system clock to 32768 mode.
6.3. Video DAC Characteristics
Limits
Characteristic
Unit
Condition
Min.
Typ.
Max.
-
-
-
-
-
-
-
-
-
Resolution
INL
10
±1
Bit
-
-
LSB max
±0.5
-
-
DNL
LSB max
-
Input Capacitor
Voltage Reference Range
VRSET
-
10
1.235
0.617
0
pF
V
1.14
1.33
0.570
0.665
V
Offset Error
-
-
-
-
-
-
-
-
V
-
-
-
Gain Error
25
LSB
pV
ns
Glitch Energy
Conversion Rate
50
30
© Generalplus Technology Inc.
Proprietary & Confidential
14
Nov. 21, 2016
Version: 1.0
GPL16218B
6.4. Audio DAC Characteristics
Characteristic
Limits
Unit
Condition
Min.
Typ.
Max.
-
-
-
-
-
-
-
-
Resolution
16
Bit
Vp-p
-
Full Scale Output Voltage
THD+N (f = 1kHz)
Noise at No Signal
Frequency Response
0.6*VDDDA
-
-
-
0.1
90
-
-85
20
dBv
Hz
19200
6.5. Regulator Characteristics
Characteristics
Unit
Typ.
3.0
70
Symbol
Unit
Min.
2.7
-
Max.
Input Voltage
VREGI
IREGO
VREGO
IREGS
3.6
100
1.89
-
V
mA
V
Maximum Current Output
Output Voltage
1.51
1.8
10
Standby Current
-
uA
Note1: To save more power, it is recommended switching to 1.5V before entering the halt/sleep mode and switching to 1.8V in normal operation mode.
© Generalplus Technology Inc.
Proprietary & Confidential
15
Nov. 21, 2016
Version: 1.0
GPL16218B
7. RECOMMENDED BOARD LAYOUT
7.1. Power and Ground
When the 6MHz crystal is disabled, please refer to the following
diagram for crystal circuit scheme.
All digital power and ground should be connected. The decoupling
capacitor of 0.1F and 10F should be connected to each power
pin of the IC as the following diagram. The power of analog parts
should be connected from power source with high quality.
X6MI
X32KO
X32KI
7.5K
32768 Hz
IOB[2]
GPL16218B
CL2*
CL2*
3.3n
47n
PLL_V33
DVCC18 (5 pins)
0.1 F
10 F
0.1 F
10 F
DVSS
PLLGND
DVCC33 (11 pins)
DVSS
PLL_V18
PLLGND
0.1 F
7.3. Analog Section
10 F
0.1 F
10 F
A specific AGND ground plane, connected via a signal trace to
GND ground, should be provided. No digital signal should cross
the AGND plane. DAVREF should be connected to a 1F
capacitor and VDVREF should be connected to a 0.1F capacitor.
7.2. Crystal and PLL
When the 32768Hz crystal is disabled, usually for TV and USB
applications, please refer to the following diagram for the crystal
circuit scheme.
X6MO
X6MI
X32KO
X32KI
Optional
IOB[2]
6MHz
32768 Hz
CL1*
CL1*
CL2
*
CL2*
Note*: Please refer to the crystal’s application circuit.
© Generalplus Technology Inc.
Proprietary & Confidential
16
Nov. 21, 2016
Version: 1.0
GPL16218B
8. Application Circuit
8.1. For TV Plug-and-Play Simple ELA/Game 2D Application
Hand-Held LCD
Simple ELA/Game
2D QVGA
SD Card
USB
TFT/STN
VAVDD
Light Gun
Optional
DVCC33
RESET
Optional
10uF
VSS
10 Ω
VCBU
VCBL
0.1uF 0.1uF 0.1uF
VSS
VDVREF
0.1uF
100uF
BM0
BM1
BM2
390Ω
Optional
100kΩ
VRSET
AVSS
0.1uF
100kΩ
100kΩ
100uF
AVSS
(
VAOUT
VSS
VSS
VSS
75Ω
Video Vss
Mask ROM
1uF
1uF
BKCSB
BKOEB
DACOR
DACOL
CSB
OEB
DATA
ADR
XD[15..0]
XA[23..0]
X6MO
X6MI
6MHz
22pF
VSS
22pF
VSS
X32KI
32768Hz
X32KO
GPL16218B
12pF
VSS
12pF
VSS
Optional
*Number of capacitance depends on the power consumption of whole system (including IC, memory, external component)
© Generalplus Technology Inc.
Proprietary & Confidential
17
Nov. 21, 2016
Version: 1.0
GPL16218B
9. PACKAGE/PAD LOCATIONS
9.1. Ordering Information
Product Number
Package Type
GPL16218B - NnnV - C
Chip Form
GPL16218B - NnnV - QL09x
Halogen Free Package
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
Note3: Package form number (x = 1 - 9, serial number).
9.2. Package Information
LQFP 128
Symbol
Millimeter
Nom.
--
Min.
--
Max.
A
1.60
© Generalplus Technology Inc.
Proprietary & Confidential
18
Nov. 21, 2016
Version: 1.0
GPL16218B
Symbol
Millimeter
Nom.
Min.
0.05
1.35
0.13
0.09
Max.
0.15
1.45
0.23
0.20
A1
A2
b
--
1.40
0.16
C
--
D
16.00 BSC
14.00 BSC
16.00 BSC
14.00 BSC
0.40 BSC
0.60
D1
E
E1
e
L
0.45
0.75
L1
θ
1.00 REF
3.5°
0°
7°
© Generalplus Technology Inc.
Proprietary & Confidential
19
Nov. 21, 2016
Version: 1.0
GPL16218B
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
Proprietary & Confidential
20
Nov. 21, 2016
Version: 1.0
GPL16218B
11. REVISION HISTORY
Date
Revision #
Description
Add ICEDA, ICECK pin description in 4.SIGNAL DESCRIPTION.
1. Modify pin descriptions.
Page
5
Nov. 21, 2016
Nov. 19, 2008
1.0
0.4
5
2. Modify pad assignment.
9
Jul. 01, 2008
Jun. 03, 2008
May. 05, 2008
0.3
0.2
0.1
1. Modify test pin descriptions.
5
2. Modify package number.
5-8
12
16
19
1. Modify operating current and power down current.
2. Modify application circuit.
Preliminary version.
© Generalplus Technology Inc.
Proprietary & Confidential
21
Nov. 21, 2016
Version: 1.0
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