GPL31B2 [GENERALPLUS]
64KB LCD Controller/Driver;
| 型号： | GPL31B2 |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 64KB LCD Controller/Driver CD |
| 文件： | 总15页 (文件大小：413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPL31B2
64KB LCD Controller/Driver
MAR. 18, 2010
Version 1.1
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPL31B2
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3
2. BLOCK DIAGRAM ...................................................................................................................................................................................... 3
3. FEATURES.................................................................................................................................................................................................. 3
4. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 4
4.1. PAD ASSIGNMENT ................................................................................................................................................................................. 5
5. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 6
5.1. MAP OF MEMORY AND I/OS .................................................................................................................................................................... 6
5.2. ROM AREA ........................................................................................................................................................................................... 6
5.3. OPERATING STATES ............................................................................................................................................................................... 6
5.4. TIME-BASE-SETTING REGISTER ............................................................................................................................................................. 6
5.5. TIMER/COUNTER ................................................................................................................................................................................... 7
5.6. SPEECH AND MELODY............................................................................................................................................................................ 7
5.7. LCD CONTROLLER/DRIVER.................................................................................................................................................................... 7
5.8. VOLTAGE DOUBLER/REGULATOR ............................................................................................................................................................ 7
5.9. PWM OUTPUT....................................................................................................................................................................................... 7
5.10.LOW VOLTAGE RESET ............................................................................................................................................................................ 8
5.11.WATCHDOG TIMER (WDT) ..................................................................................................................................................................... 8
5.12.LOW VOLTAGE DETECT .......................................................................................................................................................................... 8
5.13.MASK OPTIONS...................................................................................................................................................................................... 8
5.13.1. 32768 crystal oscillator......................................................................................................................................................... 8
5.13.2. Low voltage detect................................................................................................................................................................ 8
5.14.SEG[43:41] CAN BE OPTIONED TO IOEF[7:5] ........................................................................................................................................ 8
5.15.BUILT-IN REGULATOR CAN BE DISABLED ................................................................................................................................................. 8
6. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................... 9
6.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................... 9
6.2. DC CHARACTERISTICS (VDD = 3.0V, TA = 25℃) .................................................................................................................................... 9
6.3. DC CHARACTERISTICS (VDD = 4.5V, TA = 25℃) .................................................................................................................................... 9
6.4. THE RELATIONSHIPS BETWEEN THE ROSC AND THE FCPU......................................................................................................................... 10
6.4.1. VDD = 3.0V, TA = 25℃............................................................................................................................................................ 10
6.4.2. VDD = 4.5V, TA = 25℃............................................................................................................................................................ 10
6.5. THE RELATIONSHIPS BETWEEN THE FCPU AND THE IOP ............................................................................................................................ 10
6.6. THE RELATIONSHIPS BETWEEN THE FCPU AND THE VDD......................................................................................................................... 10
7. APPLICATION CIRCUITS......................................................................................................................................................................... 11
7.1. APPLICATION CIRCUIT – (1) ...................................................................................................................................................................11
7.2. APPLICATION CIRCUIT – (2) .................................................................................................................................................................. 12
8. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 13
8.1. ORDERING INFORMATION ..................................................................................................................................................................... 13
9. DISCLAIMER............................................................................................................................................................................................. 14
10.REVISION HISTORY ................................................................................................................................................................................. 15
© Generalplus Technology Inc.
Proprietary & Confidential
2
MAR. 18, 2010
Version: 1.1
GPL31B2
64KB LCD CONTROLLER/DRIVER
1. GENERAL DESCRIPTION
3. FEATURES
The GPL31B2, an 8-bit CMOS single chip microprocessor,
contains RAM, ROM, I/Os, interrupt/wakeup controller, timer, 8-bit
PWM audio output and automatic display controller/ driver for LCD.
With a dual channel PWM driver, attractive sound effects can be
generated easily. Built-in voltage doubler and voltage regulator
provide robust and adjustable (16-level) LCD supply voltage to get
the best display quality for specific panels. Furthermore, a
software controllable standby mode is also implemented for power
Built-in 8-bit CPU
─ 160 bytes SRAM
─ 64K bytes ROM
─ Max. CPU clock: 3.0MHz @ 2.4V – 5.5V
─ Programmable CPU clock frequency, 1/2, 1/4, 1/8, 1/16,
1/32 or 1/64 of R-oscillator’s clock frequency is available
─ Provides 7 interrupt sources
Built-in 8-bit 2-channel PWM outputs
saving.
The GPL31B2 is designed with state-of-the-art
Built-in 32.768KHz Crystal / R-oscillator
─ Crystal or R-oscillator (mask option)
technology to fulfill the requirements of LCD applications
especially for hand-held products.
─ Crystal oscillator switches from strong to Weak mode
automatically
─ Internal time base generator
2. BLOCK DIAGRAM
Built-in System R-oscillator
─ Only one resistor is needed
32.768KHz
ROSC
Two 16 bits timer/counters
Low Voltage Reset / Low Voltage Detect
─ Provides 2.3V low voltage reset function
─ 2.4V/2.6V low voltage detect (Mask option)
Interrup/wakeup
Control
32.768KHz
Oscillator
&
AUDP
AUDN
Time Base
Low Voltage Reset
Low power consumption
Two 16-bit
Auto Reload
Timers
─ Operating current: 1.0mA/1.0MHz @ 3.0V
─ Very low standby current : ISTBY < 1.0μA @ 3.0V
64K bytes
ROM
IOCD3 - 0
(I/O)
In standby mode: stop all oscillators
Max. 12 general purpose I/O
8-bit
RISC
Processor
160 bytes RAM
─ SEG[43:41] can be optioned to IOEF[7:5]
─ 8 IO pins support Key wake-up mode
IOEF4 - 0
(I/O)
LCD RAM
44 Segments X 5 Commons LCD Driver
LCD controller / driver
─ 44 segments x 5 commons, max. 220 dots
─ Programmable bias option (1/2,1/3 bias) and duty option
COM4 - 0
SEG43 - 0
(1/2,1/3,1/4,1/5 duty)
─ Built-in voltage doubler and regulator to generate VLCD
voltage for LCD driver(Built-in regulator can be disabled)
─ Adjustable 16-level VLCD for various panels
1/3 bias: VLCD (3.0V - 6.0V)
1/2 bias: VLCD (2.0V - 4.0V)
─ Built-in regulator can be disabled
1/3 bias: VLCD = VDD ;VDD2 =2/3 VDD ;VDD1 =1/3 VDD
1/2 bias: VLCD = VDD ;VDD1 =1/2 VDD
© Generalplus Technology Inc.
Proprietary & Confidential
3
MAR. 18, 2010
Version: 1.1
GPL31B2
4. SIGNAL DESCRIPTIONS
Mnemonic
PIN No.
Type
Description
SEG43 - 0
COM4 - 0
IOEF1 - 0
IOEF4 - 2
IOCD3 - 0
ROSC
5 - 48
49 - 53
74 - 73
3 - 1
68 - 65
63
O
O
LCD driver segment output
LCD driver common output
I/O
I/O port (provide key wake-up function)
I/O
I
I/O port
System R-oscillator input, connect to VDD through resistor
System reset input
RESET
AVDD
62
I
71
P
O
O
P
I
PWM power supply input
PWM audio output
AUDP
70
AUDN
72
PWM audio output
AVSS
69
PWM ground input
X32I
61
32.768KHz crystal input, or connect to VDD through resistor as R-oscillator input
(Mask option)
X32O
TEST
VDD
60
59
4
O
I
32.768KHz crystal output
Test mode input
P
P
I
Power supply voltage input
VSS
64
54
55
58
56
57
Ground input
VLCD
VDD1
VDD2
CUP1
CUP2
LCD voltage, connect to VSS through a capacitor
Connect coupling capacitors for charge pump
I
I
Charge pump capacitor interconnection pins for LCD voltage generation
Note1: Legend: I = Input, O = Output, P = Power
Note2: SEG43 - 41 can be optioned to IOEF7 - 5, IOEF7 - 0 provide key wake-up function
Note3: Provides 220 bits read/writable LCD RAM buffer
Note4: 32.768KHz Crystal oscillator can be optioned to R-oscillator (connect to VDD through resistor).
© Generalplus Technology Inc.
Proprietary & Confidential
4
MAR. 18, 2010
Version: 1.1
GPL31B2
4.1. PAD Assignment
This IC substrate should be connected to VSS
Note1: To ensure that the IC functions properly, please bond all of VDD and VSS pins.
Note2: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible.
© Generalplus Technology Inc.
Proprietary & Confidential
5
MAR. 18, 2010
Version: 1.1
GPL31B2
5. FUNCTIONAL DESCRIPTIONS
5.1. Map of Memory and I/Os
wake-up, 4Hz/8Hz/ 16Hz/32Hz wake-up and 2Hz/1Hz wake-up.
If any wake-up event occurs, execution of the next instruction
continues in the operating state. In standby mode, all modules
will be shut down, and RAM and I/Os remain in their previous
states. Therefore current consumption is minimized. By writing
to SLEEP register but keeps 32768 oscillator running, the system
is in HALT state. CPU clock is halted while it waits for an event
(key press, timer overflow) to generate a wake-up in HALT state.
The 32768 related modules (timer/counter, LCD driver…) may
remain active in the halt state. Following figure is a state diagram
for the GPL31B2.
*I/O PORT:
*
MEMORY MAP
─
─
IOCD Port $0004
IOEF Port $0005
$0000
I/O & Registers
$001F
$0020
* I/O CONFIG
LCD RAM Buffer
reserved
IOCD_ Config $0000
─
─
$003D
IOEF_ Config $0019
$0060
SRAM
reserved
* NMI SOURCE:
$00FF
$0200
INT1 ( from TIMER 1 )
─
* INT SOURCE
Test Program
INT0 ( from TIMER 0 )
─
─
─
─
─
─
─
$05FF
$0600
INT1 ( from TIMER 1 )
T16Hz ( 4Hz /8Hz /16Hz /32Hz
)
Program ROM
Bank #0
T2Hz ( 2Hz /1Hz
128Hz
)
Write to SLEEP register,
32768 oscillator OFF
$7FFA
$7FFF
2KHz
NMI/Reset/IRQ Vector
OPERATING
STANDBY
EXTINT ( from IOCD1 pin )
Program ROM
Bank #1
Wake-up or user reset
*
WAKEUP SOURCE
IOEF Port Change
─
─
─
─
$FFFA
$FFFF
NMI/Reset/IRQ Vector
TIMER 0 Overflow
T16Hz ( 4Hz /8Hz /16Hz /32Hz
T2 Hz ( 2Hz /1Hz )
)
5.2. ROM Area
HALT
GPL31B2 is a ROM based micro-controller with 220 dots LCD
driver. The large ROM space can be defined as a program ROM,
LCD font and audio data continuously without any limitation. To
access the higher bank ROM area, user can program the BANK
SELECT register ($07) to 1, then fetch the data from address
$8000 to $FFFF.
State Diagram of GPL31B2
After the chip is awakened from halt/standby state, CPU will
continue to execute the next instruction. The RAM and I/O status
will not be changed by wake-up.
5.3. Operating States
5.4. Time-Base-Setting Register
The GPL31B2 provides three operating states: standby, halt, and
operating state. Following table shows the differences between
the three operating states.
Writing to TIME-SETTING register can program the time source of
CPU wake-up and interrupt. For example, the programmer can
change 2Hz wake-up and interrupt into 1Hz wake-up and interrupt
by writing 80H into $0A.
Operating
ON
Halt
OFF
Standby
OFF
CPU
Thus, the system will wake up to service every second. Also,
T16Hz (one of counter‘s clock source and wake-up & interrupt)
can be one of 4Hz, 8Hz, 16Hz or 32Hz by setting bit0 and bit1 of
TIME-SETTING register ($0A). At power on state, the default
value of T16Hz is 4Hz and T2Hz is 2Hz.
32768 oscillator
LCD driver
ON
ON
OFF
ON
ON/OFF
OFF
In operating state, all modules (CPU, 32768 oscillator,
timer/counter, LCD driver…) are activated. The halt/standby
state is entered by writing the SLEEP register ($09). There are
four wake-up sources in GPL31B2: port IOEF wake-up, TIMR0
© Generalplus Technology Inc.
Proprietary & Confidential
6
MAR. 18, 2010
Version: 1.1
GPL31B2
5.5. Timer/Counter
GPL31B2 contains two 16-bit timer/counters, TM0 and TM1
respectively. In the timer mode, TM0 and TM1 are reloadable
up-counters. When the timer overflows from $FFFF to $0000,
the carry signal will generate the INT signal if the corresponding
bit is enabled in INT ENABLE register ($0D). The timer will
automatically reload the value assigned by the program and up
count continuously. If TM0 is specified as a counter, the user can
reset the counter by loading 0 into register $10 and $11 and
loading 0 into the counter by writing any data to $12. After the
counter is activated, the counter’s value can also be read from
above registers ($10 and $11) and the read instruction will not
affect the counter's value or reset it.
The clock source of the timer/counter are selected as the following:
Timer/Counter
Address
Clock Source
$0010
$0011
$0012
$0010
$0011
$0012
$0013
$0014
$0015
$000B
16-BIT Timer
R-oscillator Output, the CARRY of timer 1
TM0
TM1
Clock source A: IOCD0, R-oscillator Output, VDD, 32768Hz.
Clock source B: IOCD1, VDD, T16Hz, 128Hz.
16-BIT Counter
16-BIT Timer
Note: T16Hz can be one of 4Hz, 8Hz, 16Hz and 32Hz by setting $0A (time-setting register)
R-oscillator Output, 32768 Hz
Mode Select Register
Select TM0 & TM1 configuration
5.8. Voltage Doubler/Regulator
5.6. Speech and Melody
Since GPL31B2 can provide a large ROM size and wide CPU
operation speed, it is suitable for speech and melody synthesis.
For speech synthesis, this chip can provide INT for precise
sampling frequency. Users can record or synthesize the sound
and digitize the data into the ROM. The sound can be played
back in the sequence designed by the internal user's program.
Several algorithms are recommended for high fidelity and good
To get the best LCD quality, the LCD supply voltage should not
change with the system power. The GPL31B2 provides a robust
and adjustable (16-level) LCD supply voltage. Users can get
desired VLCD to fit specific LCD panels by changing the output
reference voltage (program $16). The available VLCD voltage
range are summarized as the following table:
Bias
Min. VLCD ($16 = 00h)
Max. VLCD ($16 = 0Fh)
compression of sound: such as PCM and ADPCM.
For melody
synthesis, GPL31B2 provides dual tone mode. Once in the dual
tone mode, users only need to program the tone frequency of
each channel by writing to timer/counter TM0 and TM1, and set
the envelope of each channel. The hardware will toggle the tone
wave automatically without users’ care.
1/2 bias
1/3 bias
2.0V
3.0V
4.0V
6.0V
Note1: If the LCD display is uneven with a large panel load, connect a
resistor between the VDD1 pin and ground is suggested.
Note2: To make sure the chip work properly, the following equation must be
satisfied.
Min. (VLCD) > VDD,Otherwise, VDD will change the VLCD
.
5.7. LCD Controller/Driver
If User doesn’t care LCD supply voltage with the system power, or
concern power consumption, the built-in regulator can be disabled.
And then VLCD = VDD, VDD1 = 1/2VDD(1/2 Bias); VLCD = VDD,
VDD2 = 2/3VDD, VDD1 = 1/3VDD (1/3 Bias).
GPL31B2 contains a LCD controller and driver for 220dots LCD
display. Users can set the LCD configuration (bias, duty, display
mode) by writing LCD control register ($18). Once the LCD
configuration is initialized, the desired pattern can be displayed by
filling the LCD buffer with appropriate data. The LCD driver can
still operate during halt mode by keeping 32768 oscillator running.
Furthermore, programmer can turn off the LCD display through
LCD control register for power saving. The LCD driver in
GPL31B2 is designed to fit most LCD's specifications. 1/2 or 1/3
bias is available from the LCD driver. Meanwhile, the display
duty can be programmed as 1/2, 1/3, 1/4 or 1/5 duty.
5.9. PWM Output
Internally, GPL31B2 has one pair of PWM outputs supporting two
sound channels. Each channel can be set to play speech or tone
individually. GPL31B2 uses Pulse Width Modulation that is able
to drive speaker or buzzer directly without any buffer or
amplification circuit.
© Generalplus Technology Inc.
Proprietary & Confidential
7
MAR. 18, 2010
Version: 1.1
GPL31B2
5.10. Low Voltage Reset
5.13. Mask Options
5.13.1. 32768 crystal oscillator
The GPL31B2 provides a low voltage reset function. The system
will enter into LVRST state if and only if the power supply voltage
VDD is lower than 2.3V.
1). X’TAL
2). R-oscillator
5.11. Watchdog Timer (WDT)
5.13.2. Low voltage detect
An on chip watchdog timer is available on GPL31B2. The WDT
is designed for recovering from system abnormal operation. If
the system is hanged, WDT will generate a system reset to restart
system after 1 second. If WDT is enabled, the WDT should be
cleared every two seconds to avoid accidental reset. The WDT
can be cleared by writing the specified value 0FH to port $0F.
Note that the WDT only works when 32768 Hz clock is available.
1). 2.4V
2). 2.6V
5.14. SEG[43:41] Can be Optioned to IOEF[7:5]
5.15. Built-in Regulator Can be Disabled
5.12. Low Voltage Detect
Furthermore, a Low Voltage Detect function is built in GPL31B2.
Once, the control register $17 bit7 is set to 1 (enable), the
programmer can compare VDD voltage level with reference
voltage 2.4V/2.6V from reading $17 bit0.
Note1: 50us delay time is recommended for voltage detect circuit
stabilization.
Note2: Be sure to turn off voltage detect circuit if not needed to minimize
power consumption.
© Generalplus Technology Inc.
Proprietary & Confidential
8
MAR. 18, 2010
Version: 1.1
GPL31B2
6. ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics
Symbol
Ratings
DC Supply Voltage
V+
VIN
TA
< 7.0V
Input Voltage Range
Operating Temperature
Storage Temperature
-0.5V to V+ + 0.5V
0℃ to +60℃
-50℃ to +150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational
conditions see AC/DC Electrical Characteristics.
6.2. DC Characteristics (VDD = 3.0V, TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test condition
Min.
Typ.
-
Max.
Operating Voltage
Operating Current
Standby Current
VDD
IOP
2.4
3.6
V
For 2-battery application
VDD = 3.0V, FCPU = 600KHz
VDD = 3.0V
-
1.2
-
-
mA
μA
ISTBY
-
1.0
-
-50
-90
60
110
-
-
VDD = 3.0V, VOH = 2.5V
VDD = 3.0V, VOH = 2.0V
VDD = 3.0V, VOL = 0.5V
VDD = 3.0V, VOL = 1.0V
VDD = 3.0V
IOH
mA
mA
-
-
Audio Output Current
-
-
IOL
-
-
Input High Level
Input Low Level
Output High I
Output Sink I
VIH
VIL
IOH
IOL
2.0
-
0.8
-
V
V
-
-
-
-
VDD = 3.0V
-2.0
2.5
mA
mA
VDD = 3.0V, VOH = 2.4V
VDD = 3.0V, VOL = 0.8V
-
6.3. DC Characteristics (VDD = 4.5V, TA = 25℃)
Limit
Typ.
-
Characteristics
Symbol
Unit
Test condition
Min.
Max.
Operating Voltage
Operating Current
Standby Current
VDD
IOP
3.6
5.5
V
For 3-battery application
VDD = 4.5V, FCPU = 600KHz
VDD = 4.5V
-
2.4
-
-
mA
μA
mA
mA
V
ISTBY
IOH
-
1.0
-
-100
70
-
-
VDD = 4.5V, VOH = 3.5V
VDD = 4.5V, VOL = 0.8V
VDD = 4.5V
Audio Output Current
IOL
-
-
Input High Level
Input Low Level
Output High I
Output Sink I
VIH
VIL
3.0
-
0.8
-
-
-
-
-
V
VDD = 4.5V
IOH
-2.0
2.5
mA
mA
VDD = 4.5V, VOH = 3.5V
VDD = 4.5V, VOL = 0.8V
IOL
-
© Generalplus Technology Inc.
Proprietary & Confidential
9
MAR. 18, 2010
Version: 1.1
GPL31B2
6.4. The Relationships between the ROSC and the FCPU
6.4.1. VDD = 3.0V, TA = 25℃
6.4.2. VDD = 4.5V, TA = 25℃
4
3
2
1
0
4
3
2
1
0
0
200
400
600
800
0
200
400
600
800
ROSC (K ohms)
ROSC (KohmS)
6.5. The Relationships between the FCPU and the IOP
6.6. The Relationships between the FCPU and the VDD
3
3
VDD=4.5V
Rosc=100Kohms
2.5
2.5
2
1.5
1
2
1.5
1
Rosc=470Kohms
0.5
VDD=3.0V
0.5
0
0
2.2
2.7
3.2
3.7
4.2
4.7
5.2
5.7
0
0.5
1
1.5
2
2.5
3
3.5
VDD (V)
Fcpu (MHz)
© Generalplus Technology Inc.
Proprietary & Confidential
10
MAR. 18, 2010
Version: 1.1
GPL31B2
7. APPLICATION CIRCUITS
7.1. Application Circuit – (1)
SEG8
SEG7
SEG6
SEG5
SEG4
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG3
SEG2
SEG1
SEG0
SEG40
SEG41
SEG42
SEG43
COM4
COM3
COM2
COM1
COM0
TEST
IOCD3
IOCD2
IOCD1
IOCD0
Note*1: These capacitor values are for design guidance only. Different capacitor value may be required for different crystal/resonator used.
© Generalplus Technology Inc.
Proprietary & Confidential
11
MAR. 18, 2010
Version: 1.1
GPL31B2
7.2. Application Circuit – (2)
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
COM4
COM3
COM2
COM1
COM0
IOCD3
IOCD2
IOCD1
IOCD0
TEST
Note*1: These capacitor values are for design guidance only. Different capacitor value may be required for different crystal/resonator used.
© Generalplus Technology Inc.
Proprietary & Confidential
12
MAR. 18, 2010
Version: 1.1
GPL31B2
8. PACKAGE/PAD LOCATIONS
8.1. Ordering Information
Product Number
Package Type
GPL31B2-NnnV-C
Chip form
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
© Generalplus Technology Inc.
Proprietary & Confidential
13
MAR. 18, 2010
Version: 1.1
GPL31B2
9. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
Proprietary & Confidential
14
MAR. 18, 2010
Version: 1.1
GPL31B2
10. REVISION HISTORY
Date
Revision #
Description
Page
6
MAR. 18, 2010
NOV. 06, 2007
1.1
1.0
Modify 5.1. Map of Memory and I/Os.
Original
15
© Generalplus Technology Inc.
Proprietary & Confidential
15
MAR. 18, 2010
Version: 1.1
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明