GPLB39B-NnnV-C [GENERALPLUS]
LCD CONTROLLER;
| 型号： | GPLB39B-NnnV-C |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | LCD CONTROLLER CD |
| 文件： | 总19页 (文件大小：983K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPLB39B
LCD CONTROLLER
JAN. 07, 2008
Version 1.5
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPLB39B
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3
2. FEATURES.................................................................................................................................................................................................. 3
3. APPICATION FIELD.................................................................................................................................................................................... 3
4. BLOCK DIAGRAM ...................................................................................................................................................................................... 4
5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5
5.1. PAD ASSIGNMENT ................................................................................................................................................................................. 6
6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 7
6.1. MEMORIES ............................................................................................................................................................................................ 7
6.2. MAP OF MEMORY AND I/OS .................................................................................................................................................................... 7
6.3. OPERATING STATES ............................................................................................................................................................................... 7
6.4. SPEECH AND MELODY............................................................................................................................................................................ 8
6.5. LCD CONTROLLER/DRIVER.................................................................................................................................................................... 8
6.6. LCD VOLTAGE GENERATION................................................................................................................................................................... 8
6.7. PWM OUTPUT....................................................................................................................................................................................... 8
6.8. SERIAL SRAM INTERFACE ..................................................................................................................................................................... 8
6.9. BUS MEMORY INTERFACE....................................................................................................................................................................... 9
6.10.VOLTAGE REGULATOR............................................................................................................................................................................ 9
6.11.ASYNCHRONOUS SERIAL INTERFACE ...................................................................................................................................................... 9
6.12.LOW VOLTAGE DETECTION..................................................................................................................................................................... 9
6.13.WATCHDOG TIMER (WDT) ..................................................................................................................................................................... 9
6.14.SERIAL PERIPHERAL INTERFACE (SPI).................................................................................................................................................... 9
6.15.MASK OPTIONS.................................................................................................................................................................................... 10
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 11
7.1. ABSOLUTE MAXIMUM RATINGS ..............................................................................................................................................................11
7.2. DC CHARACTERISTICS..........................................................................................................................................................................11
8. APPLICATION CIRCUITS......................................................................................................................................................................... 12
8.1. 6144 DOTS LCD DRIVER, 96 SEGMENTS × 64 COMMONS WITH EXTERNAL SERIAL SRAM, REGULATOR DISABLED - (1).......................... 12
8.2. 6144 DOTS LCD DRIVER, 96 SEGMENTS × 64 COMMONS WITH EXTERNAL BUS ROM, REGULATOR DISABLED - (2) ................................ 13
8.3. 6144 DOTS LCD DRIVER, 96 SEGMENTS × 64 COMMONS WITH EXTERNAL BUS FLASH, REGULATOR ENABLED - (3)................................ 14
8.4. 6144 DOTS LCD DRIVER, 96 SEGMENTS × 64 COMMONS WITH BUS EXTENDER, REGULATOR DISABLED - (4)......................................... 15
8.5. SERIAL COMMUNICATIONS BETWEEN TWO GPLB39BS - (5)................................................................................................................... 16
8.6. SERIAL COMMUNICATIONS BETWEEN GPLB39B AND USB CONTROLLER- (6) ......................................................................................... 16
9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 17
9.1. ORDERING INFORMATION ..................................................................................................................................................................... 17
10.DISCLAIMER............................................................................................................................................................................................. 18
11. REVISION HISTORY ................................................................................................................................................................................. 19
© Generalplus Technology Inc.
Proprietary & Confidential
2
JAN. 07, 2008
Version: 1.5
GPLB39B
LCD CONTROLLER
1. GENERAL DESCRIPTION
The GPLB39B, an 8-bit CMOS microprocessor, contains 8128
bytes working RAM, 2M bytes ROM, 21 I/Os, interrupt/wakeup
controller, UART for serial communication, Serial SRAM interface
and Bus memory interface for memory expansion, and automatic
display controller/driver for LCD. It also features one PWM driver
with two audio channels to produce attractive sound effects easily.
Its large ROM area can be used to store both program and audio
data. The built-in UART and SPI speeds up data transmission
between two devices. Furthermore, a SLEEP (power-down)
function is also built in to extend power life. The GPLB39B is
designed with state-of-the-art technology to fulfill LCD application
needs, especially for hand-held products.
Wide operating voltage range:
− 2.4V - 3.6V
− 3.6V - 5.5V
Peripherals
− Max. 21 I/O pins (PA[7:0], PB[7:0], PC[4:0])
. Dedicated I/Os: PA[4:0]
. Shared pin I/Os:
PA[7:5]/SPI SCK/SDI/SDO
PB[7:0]/BMI AD Bus [7:0]
PC[1:0]/BMI MC[1:0]/SSRAM SDA, SCK
PC[3:2]/UART Rx/Tx
PC[4]/external interrupt
COM[48:63]/SEG[96:111]
− 32.768KHz oscillator circuit for RTC
− RC-oscillator (only one resistor is needed)
− Two 16-bit reloadable timer/counters
− 2-channel PWM audio outputs
− Watchdog Timer for reliable operation
Low-power consumption:
2. FEATURES
Built-in 8-bit processor
− 8128 bytes SRAM with individual Power Pad
− 2M bytes ROM
− Max. operating speed: 4.0MHz @ 2.4V - 3.6V
6.0MHz @ 3.6V - 5.5V
− 1000μA typical @ 3.0V, FCPU = 1.0MHz, FOSC = 4.0MHz
− 80μA typical halt current @ 3.0V
− <1.0μA typical standby current @ 3.0V
− CPU clock is software programmable, can be /1, /2, /4, /8,
/16, /32, /64 R-oscillator clock frequency
− 6 wake-up sources
− 7 interrupt sources
3. APPICATION FIELD
Asynchronous serial interface (UART)
Serial SRAM interface
Hand held games
Bus memory interface
Scientific calculator
Serial peripheral interface (SPI)
Built-in voltage regulator for external memory devices
Key scan function
Talking calculator, Talking clock
Talking instrument controller
General speech synthesizer
Data Bank
− SEG[15:0] can be used to send key scan output
Programmable LCD driver
− 112x8, 112x16, 112x32, 112x48, 96x64 dots
− 1/4, 1/5, 1/6, 1/7, 1/8, 1/9 bias; 1/8, 1/16, 1/32, 1/48, 1/64
duty capability
− 14x64 bytes dedicated LCD RAM
− Built-in voltage regulator to generate VLCD for LCD driver
− 32-level contrast control
Power saving SLEEP mode
Low voltage detector
− 8-level 2.9V ~ 2.2V/4.35V ~ 3.3V detection
− 2.2V Low voltage reset
© Generalplus Technology Inc.
Proprietary & Confidential
3
JAN. 07, 2008
Version: 1.5
GPLB39B
4. BLOCK DIAGRAM
32KHz
ROSC32
ROSC
AUDA
PWM
Driver
AUDB
RC-Oscillator
32 KHz
System Clock Gen.
SDO/PA5
SDI/PA6
SCK/PA7
Oscillator
&
SPI
Time base
Rx/PC3
Tx/PC2
UART
Power Supply
Voltage Detect
Serial
SRAM
I/F
SDA/PC1
SCK/PC0
Two 16-bit /
Auto-reload
Timers
1M bytes
ROM
8
2
BUS
AD[7:0]/PB[7:0]
MC[1:0]/PC[1:0]
Mem I/F
8-bit
2560 bytes
RAM
Voltage
Regulator
micro-processor
VROUT
(I/O)
8
PA[7:0]
8
8
Max.20
PB[7:0]
PC[4:0]
I/O Ports
LCD RAM 896 bytes
64 Commons X 112 Segments LCD Driver
COM[47:0]
SEG[111:0]
Note1: COM[48:63] share pins with SEG[96:111].
Note2: PB[7:0] share pins with Bus memory interface Addr/Data bus.
Note3: PC[1:0] share pins with Bus memory interface MC[1:0]. Also share pins with Serial SRAM interface SDA/SCK.
Note4: PC[3:2] share pins with UART Rx/Tx.
Note5: PA[7:5] share pins with SPI SCK/SDI/SDO.
© Generalplus Technology Inc.
Proprietary & Confidential
4
JAN. 07, 2008
Version: 1.5
GPLB39B
5. SIGNAL DESCRIPTIONS
Total: 214 pins
Mnemonic
SEG95 - 0
PIN No.
Type
Description
199 - 213
2 - 82
O
LCD driver segment output. SEG15 - 0 share pin with key scan port.
LCD driver common output. SEG96 - 111 can be optioned to COM48 - 64.
LCD driver common output. COM47 - 0.
COM48 - 63 /
SEG 96 - 111
COM19 - 0
COM23 - 20
COM47 - 24
PA4 - 0
O
O
198 - 183
103 - 84
107 - 104
182 - 159
142 - 146
139 - 141
I/O
I/O
Port A 4- 0 is a bi-directional I/O port, which can be software programmed as wake up I/O.
Port A 7- 5 is a bi-directional I/O port, which can be software programmed as wake up I/O.
Share pin with SPI SCK/SDI/SDO.
PA7 - 5
PB7 - 0
136 - 129
128
I/O
I/O
Port B is a bi-directional I/O port. Share pin with Bus Memory Interface Addr/Data.
Port C is a bi-directional I/O port. Share pin with Bus Memory MC1 - 0. Also share pin
with SDA/SCK.
PC1 / MC1 / SDA
PC0 / MC0 / SCK
PC3 / Rx
127
148
I/O
I/O
I/O
I
UART input. Share pin with PC3.
PC2 / Tx
147
UART output. Share pin with PC2.
PC4
149
Port C 4 is a bi-directional I/O port. It can be used as an external interrupt.
ROSC input, connect to VDD through a resistor.
ROSC
124
123
I
System reset input, low active.
RESET
AUDA, AUDB
X32I
152, 150
122
O
I
PWM audio output.
32.768KHz crystal input or connects to VDD through a resistor (option).
32.768KHz crystal output.
X32O
120
O
I
TESTP
121
Test input.
CAP1P, CAP1N
CAP2P, CAP2N
VPP
117, 116
114, 115
113
P
P
P
P
P
P
LCD voltage generation. Charge pump capacitor interconnection pins.
LCD voltage generation. Charge pump capacitor interconnection pins.
LCD voltage generation. Voltage generated by charge pump.
LCD voltage generation. The source of Charge pump.
LCD voltage generation. The highest Voltage for LCD display.
Internal regulator output. Enable or disable via masking option.
Should be connected to VDD if internal Regulator is disabled.
Positive supply for logic and IO pins.
VCI
118
VLCD
112
VROUT
126
VDD
138
125
P
P
P
P
P
P
P
P
O
I
VDD
Analog power pin.
VDD1
83
Positive supply for SRAM only.
VDD2
214
Positive supply for Segment / Common Pads only.
Ground reference for logic and IO pins.
VSSx2
137, 119
1
VSS2
Ground reference for Segment / Common Pads only.
Positive supply for PWM driver.
PVDD
151
PVSS
153
Ground reference for PWM driver.
V1, V2, V3, V4
TPAD1-TPAD5
108 - 111
154 - 158
LCD Bias voltage output.
Test Pads.
Legend: I = Input, O = Output, P = Power
© Generalplus Technology Inc.
Proprietary & Confidential
5
JAN. 07, 2008
Version: 1.5
GPLB39B
5.1. PAD Assignment
The IC substrate should be connected to VSS
Note1: To ensure that the IC functions properly, please bond all of VDD and VSS pins.
Note2: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible.
Note3: The power and ground pads should be double wire bonded to reduce ground bouncing.
© Generalplus Technology Inc.
Proprietary & Confidential
6
JAN. 07, 2008
Version: 1.5
GPLB39B
6. FUNCTIONAL DESCRIPTIONS
6.1. Memories
The GPLB39B contains 2M-byte ROM and 8128-byte SRAM.
Cooperating with Generalplus bus extender, GPBA01B, the
external memory, either RAM or ROM, can be extended up to
4MB. Serial SRAM interface is also provided in GPLB39B, thus
SRAM space can be extended by using Generalplus Serial SRAM,
GPRS256B or GPRS512C.
6.2. Map of Memory and I/Os
*NMI SOURCE:
- LV DETECT
- TIMER1
CPU View
ROM View
0H
0L
1H
$000000 - $003FFF
$004000 - $007FFF
$008000 - $00BFFF
$00C000 - $00FFFF
$010000 - $013FFF
$014000 - $017FFF
I/O &
Reg.
0
$0000-$003F
$0040-$1FFF
$3C00-$3FFF
RAM
1
2
*INT SOURCE:
- EXT INT
1L
DPRAM
2H
2L
- TBL (2/4/8/16Hz)
- TBH (128/256/512/1KHz)
- TIMER0
ROM
$4000-$7FFF
$8000-$BFFF
(Bank)L
. . .
- TIMER1
32
- UART TX
ROM
- UART RX
$1F8000 - $1FBFFF
$1FF000 - $1FFFFF
63H
63L
(Bank)H
63
ROM
$C000-$FFF9
$FFFA-$FFFF
0L
Bank Address: $0
$C000-$FFFF always mapping into 0L
Interrupt
1. $4000-$BFFF can be external memory if MEXT ($03.7) = 1 and Bank port ($00.7) = 1.
2. $C000-$FFFF can be external memory if MEXT ($03.7) = 1 and EXC($0b.1) = 1.
3. User program should start from $C800. $C000-$C7FF is the test program area.
4. User program interrupt vector: $FFFA ~ $FFFF
5. Test program interrupt vector: $FFF2 ~ $FFF7
6.3. Operating States
6.3.2. Standby mode
There are three operation modes involved in GPLB39B: standby,
halt and operating. The following table shows the differences
between these modes.
Write “07H” to P_04H_CPU_Clk_Ctrl Register ($04) and turn off
32768Hz oscillator to activate standby mode. The standby mode
is a mode where the device is placed in its lowest current
consumption state. In standby mode, all functions are turned off;
in addition, RAM and I/Os will remain in their previous states.
Operating
ON
Halt
OFF
Standby
OFF
CPU
6.3.3. Halt mode
32768Hz oscillator
LCD driver
ON
ON
OFF
Write “07H” to P_04H_CPU_Clk_Ctrl Register ($04) but still keeps
32768Hz oscillator running to enter halt mode. In halt mode,
CPU clock halts and waits for an event (e.g. key press, timer
overflow) to wake up. The 32768Hz related functions, such as
timer/counter and LCD driver, may remain active in the halt mode.
ON
ON/OFF
OFF
6.3.1. Operating mode
In operating state, all functions (CPU, 32768Hz oscillator,
timer/counter, LCD driver…) are activated. Generally speaking,
this mode consumes the highest current.
© Generalplus Technology Inc.
Proprietary & Confidential
7
JAN. 07, 2008
Version: 1.5
GPLB39B
The following figure is the GPLB39B state diagram:
Users should be noted that VPP and VLCD voltage difference
should be larger than 0.5V (VPP-VLCD>0.5V) to optimize
voltage regulator performance. Also, VDD should be higher
than VPP/3 to keep VPP stable.
Write $07h to
CPU_Clk_Ctrl register,
32768 oscillator OFF
OPERATING
STANDBY
Wake-up or user reset
6.7. PWM Output
Internally, the GPLB39B has a pair of PWM drivers, supporting
two sound channels. Each channel is able to play speech or tone
individually. The PWM drivers can directly drive speaker or
buzzer without buffer or amplification circuit.
HALT
6.8. Serial SRAM Interface
The Serial SRAM interface is able to expand the data storage
SRAM. The Control Registers are ranged from $30-$36. Note
that the pins of SDA and SCK are shared with PC [1:0] and
therefore, users should set PC[1:0] as Serial SRAM interface by
writing to Port $27[1:0].
GPLB39B State Diagram
6.4. Speech and Melody
For speech synthesis, the GPLB39B provides several timer
interrupts for a precise sampling frequency. The sound data can
be stored into ROM and be played back. Several algorithms are
recommended for high fidelity and good compression of sound
such as PCM and ADPCM.
SCK
SDA
data line
change of data
stable;
data valid
For melody synthesis, the GPLB39B provides a dual tone mode.
Once in the dual tone mode, users only need to program the tone
frequency for each channel by writing to the timer/counter TM0
and TM1, and set the envelope of each channel. The hardware
will toggle the tone wave automatically.
allowed
SCK
SDA
6.5. LCD Controller/Driver
START condition (S)
STOP condition (P)
The GPLB39B contains
a 6144-dot LCD controller/driver.
Programmers are able to define the LCD configuration by setting
up the LCD Control Register. Once the LCD configuration is
completed, the desired pattern can be displayed by filling the LCD
buffer with proper data. The LCD driver can also operate during
sleep by keeping 32768Hz oscillator running. The LCD driver in
GPLB39B supports 1/8 - 1/64 duty and 1/4 - 1/9 bias.
6.8.1. Read/Write timing
SCK
SDA
R/WA23
A0 D7 D6 D5 D4 D3 D2 D1 D0
start
stop
6.6. LCD Voltage Generation
The GPLB39B offers a voltage regulator and a charge-pumping
circuit. The charge-pumping circuit provides VPP as the power
source for voltage regulator. The voltage regulator generates the
LCD bias voltages (VLCD, V1~V4) needed for the LCD driver.
VPP and VLCD can be adjusted by program settings. Enabling
the voltage regulator and charge-pumping circuit gets a stable
VLCD that will not be affected by VDD. The VLCD is adjustable
from 4.4V to 5.7V (in 1/4, 1/5bias), 5.28V to 6.83V (in 1/6, 1/7
bias), or 6.2V to 8.06V (in 1/8, 1/9 bias) with 32 levels.
6.8.2. Continuous Read/Write timing
SCK
R/WA23
A0 D7 D6
D0 D7
D0 D7
D0 D7
D0
SDA
addr
addr+1
addr+n
start
stop
© Generalplus Technology Inc.
Proprietary & Confidential
8
JAN. 07, 2008
Version: 1.5
GPLB39B
6.9. Bus Memory Interface
Baud Rate(bps)
Min. Frosc(Hz)
A built-in Bus memory interface is available on GPLB39B.
Through the use of Bus memory interface, user can expand the
memory space by using an external Bus memory (SRAM, mask
ROM or Flash). The Bus memory interface includes 10 signal
pins: MC1, MC0 and AD BUS[7:0] which shared pad with port B.
Before using the Bus memory interface, users should set MEXT=1
($03.7) and BANK register ($0), then access address $4000-BFFF
to read or write data from external bus memory. Note that when
using Bus memory interface, CPU clock setting can not be set as
1200
2400
24000
48000
4800
96000
9600
192000
384000
768000
1024000
1152000
2048000
2304000
19200
38400
51200
57600
102400
115200
FOSC/1, should be /2 or slower.
MC1
MC0
AD BUS [7:0]
If the auto calibration is not selected, users can get desired baud
rates by writing appropriate values to pre-scalar registers.
Non-standard baud rates can be obtained by this method. In the
non-calibration mode, users should understand that the
R-oscillator frequency may alter due to manufacturing process
variations, supply voltage, operating temperature and tolerance of
external R components used.
L
L
L
H
L
Data for Write
Data for Read
H
H
AL (Address Low byte)
AH (Address High byte)
H
6.10. Voltage Regulator
The GPLB39B offers a voltage regulator, which supplies power
source for external memory devices. The voltage regulator can
output four voltage levels, 2.5V/2.6V/2.7V/3.0V via mask option.
The output voltage level should be properly selected based on the
electrical characteristics of external memory devices involved.
6.12. Low Voltage Detection
The GPLB39B provides an 8-level (Software programmable) low
voltage detector to detect low voltage events. Users can turn on
the low detection to monitor VDD periodically to check if it is lower
than the given value. In addition, if LV NMI is enabled, a NMI will
be issued to notify CPU if power voltage drops below the given
value. Also, the voltage detector will generate a system reset if
power supply voltage drops below 2.2V. When LVR function is
enabled, care must be taken not to turn off 32kHz crystal oscillator.
Otherwise an unexpected reset may occur when 32kHz crystal is
being turned on again.
6.11. Asynchronous Serial Interface
The GPLB39B supports
a
1-channel UART for serial
UART
communications. The bit-rate is up to 115.2kbps.
operation is controlled by UART command registers.
Configurations such as Tx/Rx interrupt, parity check, parity
even/odd and clock source can be configured in the command
registers. Two interrupts are generated by Rx and Tx. The Rx
or Tx interrupt activates when a byte is received or transmitted.
Reading the status register informs whether the interrupt is
generated by Rx or Tx. Frame, overrun and parity errors are
detected as each byte is received and all error status can be read
from status register.
6.13. Watchdog Timer (WDT)
An on chip watchdog timer is also available in the GPLB39B.
The WDT is designed to recover the system from abnormal
operation. In some cases, if WDT is not cleared within one
second, the WDT will generate a system reset to restart system.
If WDT is enabled, the WDT should be cleared periodically to
avoid accidental reset. The WDT can be cleared through
software programming. Note that the WDT only works when
32768Hz clock is activated.
The UART supports clock auto calibration. If auto calibration is
selected, standard baud rate from 1.2kbps to 115.2kbps are
available. The baud rate is selected by writing to the baud rate
control registers. The supported baud rates and their minimum
R-oscillator clock frequency requirements are shown in the table
below.
6.14. Serial Peripheral Interface (SPI)
GPLB39B provide
a serial interface to communicate with
SPCP825A USB controller. These pins are share with PA7(SCK),
PA6(SDI) and PA5(SDO) pins. PA 7~5 were set as SCK, SDI
and SDO automatically when SPI was enabled.
© Generalplus Technology Inc.
Proprietary & Confidential
9
JAN. 07, 2008
Version: 1.5
GPLB39B
6.15. Mask Options
6.15.1. 32768 oscillator
6.15.3. Voltage regulator for external memory devices
1). X’TAL
1). Enable
2). Disable
2). R-oscillator
6.15.2. Watchdog timer
6.15.4. Regulator output voltage selection
1). Enable
2). Disable
1). 2.5V
2). 2.6V
3). 2.7V
4). 3.0V
© Generalplus Technology Inc.
Proprietary & Confidential
10
JAN. 07, 2008
Version: 1.5
GPLB39B
7.ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics
Symbol
Ratings
DC Supply Voltage
V+
VIN
TA
< 7.0V
Input Voltage Range
Operating Temperature
Storage Temperature
-0.5V to V+ + 0.5V
0℃ to + 60℃
-50℃ to + 150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational
conditions see AC/DC Electrical Characteristics.
7.2. DC Characteristics
Limit
Characteristics
Symbol
VDD
IOP
Unit
Test Condition
Min.
2.4
Typ.
Max.
3.6
-
-
V
V
For 2-battery
For 3-battery
Operating Voltage
3.6
5.5
F
CPU = 1.0MHz @ 3.0V
Operating Current
-
-
1000
80
-
-
μA
μA
FROSC = 4.0MHz, no load
VDD = 3.0V, 32K X’tal ON,
LCD ON, no LCD panel
VDD = 3.0V, all off
Halt Current
IHALT
ISTBY
IOH
Standby Current
Audio Output Current
-
-
-20
-40
20
40
-
1.0
μA
mA
mA
mA
mA
V
-
-
VDD = 3.0V, VOH = 2.5V
VDD = 3.0V, VOH = 2.0V
VDD = 3.0V, VOL = 0.5V
VDD = 3.0V, VOL = 1.0V
VDD = 3.0V
-
-
-
-
Audio Output Current
IOL
-
-
Input High Level
VIH
VIL
IOH
IOL
2.0
-
Input Low Level
-
-
0.8
V
VDD = 3.0V
Output High Current (I/O)
Output Sink Current (I/O)
-1.0
-
-
mA
mA
V
VDD = 3.0V, VOH = 2.4V
VDD = 3.0V, VOL = 0.8V
VDD = 3.0V, 1/4,1/5 bias, no load
VDD = 3.0V, 1/6,1/7 bias, no load
VDD = 3.0V, 1/8,1/9 bias, no load
1.0
-
-
5.70
6.83
8.06
-
4.4
-
LCD Driver Voltage
(VLCD - VSS)
VLCD
5.28
-
V
6.20
-
V
-
-
-
-
-
-
-
-
2.5
2.6
2.7
3.0
-
-
Output voltage is selected by bonding
option
Regulator Output Voltage
VREG
V
-
-
Regulator Output Voltage Drop
OSC Resistor
VRDROP
ROSC
100
-
mV
KΩ
IL = 1.0mA, VDD = 3.6V
FOSC = 2.0MHz @ 3.0V
FCPU = FOSC/1 @ 2.4V
FCPU = FOSC/1 @ 3.6V
160
-
4.0
6.0
MHz
MHz
CPU Clock
FCPU
-
Note: VLCD should be higher than VDD to prevent forward biasing the p-n junction of I/O output PMOS.
© Generalplus Technology Inc.
Proprietary & Confidential
11
JAN. 07, 2008
Version: 1.5
GPLB39B
8. APPLICATION CIRCUITS
8.1. 6144 Dots LCD Driver, 96 Segments × 64 Commons with External Serial SRAM, Regulator Disabled - (1)
Note*1: Pin VROUT should be connected to VDD if internal Regulator is disabled.
Note*2: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
Note*3: Usually, these resistors/capacitors may not be needed when large LCD panel is connected. Different resistor/capacitor values may be required for
different LCD panel connected.
© Generalplus Technology Inc.
Proprietary & Confidential
12
JAN. 07, 2008
Version: 1.5
GPLB39B
8.2. 6144 Dots LCD Driver, 96 Segments × 64 Commons with External Bus ROM, Regulator Disabled - (2)
Note*1: Detail settings of these pins please refer to the data sheet of GPR3206A.
Note*2: Pin VROUT should be connected to VDD if internal Regulator is disabled.
Note*3: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
Note*4: Usually, these resistors/capacitors may not be needed when large LCD panel is connected. Different resistor/capacitor values may be required for
different LCD panel connected.
© Generalplus Technology Inc.
Proprietary & Confidential
13
JAN. 07, 2008
Version: 1.5
GPLB39B
8.3. 6144 Dots LCD Driver, 96 Segments × 64 Commons with External Bus Flash, Regulator Enabled - (3)
Note*1: Detail settings of these pins please refer to the data sheet of GPR1024A.
Note*2: Pin VROUT should be connected to VDD if internal Regulator is disabled.
Note*3: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
Note*4: Usually, these resistors/capacitors may not be needed when large LCD panel is connected. Different resistor/capacitor values may be required for
different LCD panel connected.
© Generalplus Technology Inc.
Proprietary & Confidential
14
JAN. 07, 2008
Version: 1.5
GPLB39B
8.4. 6144 Dots LCD Driver, 96 Segments × 64 Commons with Bus Extender, Regulator Disabled - (4)
Note*1: Pin VROUT should be connected to VDD if internal Regulator is disabled.
Note*2: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
Note*3: Usually, these resistors/capacitors may not be needed when large LCD panel is connected. Different resistor/capacitor values may be required for
different LCD panel connected.
© Generalplus Technology Inc.
Proprietary & Confidential
15
JAN. 07, 2008
Version: 1.5
GPLB39B
8.5. Serial Communications between two GPLB39Bs - (5)
Tx
Rx
Tx
GPLB39B
Rx
GPLB39B
8.6. Serial Communications between GPLB39B and GPUSB101A Controller- (6)
PA7
PA6
SPI_CLK
SPI_Tx
GPLB39B
GPUSB101A
SPI_Rx
PA5
PA4
SPI_CSN
© Generalplus Technology Inc.
Proprietary & Confidential
16
JAN. 07, 2008
Version: 1.5
GPLB39B
9. PACKAGE/PAD LOCATIONS
9.1. Ordering Information
Product Number
Package Type
GPLB39B-NnnV-C
Chip form
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
© Generalplus Technology Inc.
Proprietary & Confidential
17
JAN. 07, 2008
Version: 1.5
GPLB39B
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
Proprietary & Confidential
18
JAN. 07, 2008
Version: 1.5
GPLB39B
11. REVISION HISTORY
Date
Revision #
Description
Modify the diagrams in section 8. APPLICATION CIRCUITS.
Modify the description to section 6.12.
1. Modify the note4 to section 8.1 and 8.3.
2. Modify the note3 to section 8.2 and 8.4.
Modify the descriptions to section 2, 6.1 and 8.4.
Application circuits are modified.
Page
12 - 16
8
JAN. 07, 2008
DEC. 13, 2006
1.5
1.4
9, 11
JAN. 11, 2006
1.3
10, 12
1, 4, 11
8-11
DEC. 19, 2005
SEP. 23, 2005
1.2
1.1
Original
MAR. 02, 2005
1.0
18
Note: The GPLB39B data sheet v1.0 is a continued version of SPLB39B data sheet v0.1.
© Generalplus Technology Inc.
Proprietary & Confidential
19
JAN. 07, 2008
Version: 1.5
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