GPLB51A24B1-NnnV-C [GENERALPLUS]
1000/2000 Dots Mono/LCD Controller/Driver with 8-CH SPU;
| 型号： | GPLB51A24B1-NnnV-C |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 1000/2000 Dots Mono/LCD Controller/Driver with 8-CH SPU CD |
| 文件： | 总25页 (文件大小：8032K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPLB52A24B1
GPLB51A24B1
1000/2000 Dots Mono/LCD
Controller/Driver with 8-CH SPU
Aug 20, 2013
Version 1.2
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPLB52A24B1/
GPLB51A24B1
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 4
2. BLOCK DIAGRAM ...................................................................................................................................................................................... 4
2.1. GPLB52A24B1 .................................................................................................................................................................................... 4
2.2. GPLB51A24B1 .................................................................................................................................................................................... 4
3. FEATURES.................................................................................................................................................................................................. 4
4. APPICATION FIELD.................................................................................................................................................................................... 5
5. SIGNAL DESCRIPTION.............................................................................................................................................................................. 6
5.1. GPLB52A24B1 .................................................................................................................................................................................... 6
5.2. GPLB51A24B1 .................................................................................................................................................................................... 7
5.3. PAD ASSIGNMENT ................................................................................................................................................................................. 8
6. FUNCTIONAL DESCRIPTIONS................................................................................................................................................................ 10
6.1. MEMORIES .......................................................................................................................................................................................... 10
6.2. MAP OF MEMORY AND I/OS .................................................................................................................................................................. 10
6.3. OPERATING STATES ............................................................................................................................................................................. 10
6.3.1. Operating mode ...................................................................................................................................................................... 10
6.3.2. Standby mode......................................................................................................................................................................... 10
6.3.3. Halt mode.................................................................................................................................................................................11
6.4. SPEECH AND MELODY, PWM AND DAC .................................................................................................................................................11
6.5. LCD CONTROLLER/DRIVER...................................................................................................................................................................11
6.6. LCD VOLTAGE GENERATION..................................................................................................................................................................11
6.7. LOW VOLTAGE DETECTION....................................................................................................................................................................11
6.8. WATCHDOG TIMER (WDT) ....................................................................................................................................................................11
6.9. SPI CONTROLLER.................................................................................................................................................................................11
6.10.MASK OPTIONS.................................................................................................................................................................................... 12
6.10.1. 32768Hz oscillator.............................................................................................................................................................. 12
6.10.2. System clock oscillator ....................................................................................................................................................... 12
6.10.3. Internal VDD regulator........................................................................................................................................................ 12
6.10.4. LCD dots............................................................................................................................................................................. 12
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 13
7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 13
7.2. DC CHARACTERISTICS (VDD5V=4.5V, FOR 3-BATTERY APPLICATION, INTERNAL REGULATOR ENABLED OUTPUT, TA=25℃) ...................... 13
7.3. DC CHARACTERISTICS (VDD5V=VDD=3.0V, FOR 2-BATTERY APPLICATION, INTERNAL REGULATOR OUTPUT DISABLED, TA=25℃) ........... 14
7.4. THE RELATIONSHIP BETWEEN THE ROSC AND THE FOSC, TA = 25℃.......................................................................................................... 15
7.5. THE RELATIONSHIP BETWEEN THE F32K AND THE R32K, TA = 25℃ ...................................................................................................... 15
7.6. THE RELATIONSHIP BETWEEN THE FCPU AND THE IOP .............................................................................................................................. 15
7.6.1. VDD = 3.0V, TA = 25℃............................................................................................................................................................ 15
8. APPLICATION CIRCUITS......................................................................................................................................................................... 16
8.1. 2048 DOTS LCD DRIVER, 64 SEGMENTS × 32 COMMONS, FOR 3-BATTERY APPLICATION, INTERNAL 3.3V REGULATOR ENABLED, 12-BIT
DAC ENABLED, ROSC14M XTAL32K SELECTED- (1) .................................................................................................................................. 16
8.2. 2048 DOTS LCD DRIVER, 64 SEGMENTS × 32 COMMONS, INTERNAL 3.3V REGULATOR DISABLED, FOR 2-BATTERY APPLICATION, 12-BIT
DAC ENABLED, ROSC14M XTAL32K SELECTED - (2) ................................................................................................................................. 17
© Generalplus Technology Inc.
Proprietary & Confidential
2
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
8.3. 2048 DOTS LCD DRIVER, 64 SEGMENTS × 32 COMMONS, FOR 3-BATTERY APPLICATION, INTERNAL 3.3V REGULATOR ENABLED, 10-BIT
PWM DRIVER ENABLED, XTAL12M ROSC32K SELECTED - (3).................................................................................................................... 18
8.4. 1628 DOTS LCD DRIVER, 74 SEGMENTS ×22 COMMONS, FOR 3-BATTERY APPLICATION, INTERNAL 3.3V REGULATOR ENABLED, 10-BIT
PWM DRIVER ENABLED, XTAL12M ROSC32K SELECTED - (4).................................................................................................................... 19
8.5. DAC OUTPUT WITH GENERALPLUS AUDIO DRIVER GPY0030B (FOR HIGH QUALITY AUDIO OUTPUT) - (4) ................................................ 20
8.6. CURRENT MODE DAC SPEAKER DRIVER WITH BJT............................................................................................................................... 21
8.7. SERIAL COMMUNICATIONS BETWEEN GPLB52A24B1/GPLB51A24B1 AND GPUSB101A USB CONTROLLER- (6) ................................. 22
9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 23
9.1. ORDERING INFORMATION ..................................................................................................................................................................... 23
10.DISCLAIMER............................................................................................................................................................................................. 24
11. REVISION HISTORY ................................................................................................................................................................................. 25
© Generalplus Technology Inc.
Proprietary & Confidential
3
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
1000/2000 DOTS MONO/LCD CONTROLLER/
DRIVER WITH 8CH SPU
1. GENERAL DESCRIPTION
2.2. GPLB51A24B1
3 2 K H z
The
GPLB52A24B1/
GPLB51A24B1,
an
8-bit
CMOS
R O S C /X I
X O
3 2 K H
z
microprocessor, features 1536 bytes working RAM, 1M bytes
ROM memory, 24 I/Os, interrupt/wakeup controller, 2 set 16-bit
timers, SPI interface, 1 set of 12-bit DAC, 1 set of 10-bit PWM,
1 0 -b it
P W M
R
- O s c illa to r/X ta l
A U D A
A U D B
D
riv e r
3 2
K H z
S
y s te m lo c k e n .
C
G
O
s c illa to r
&
1 2 -b it
D A C
D A C O
T im
e
b a s e
D
riv e r
C
S
N
/P
K /P B 5
/P B 6
I/P B 7
B 4
P
o w e r
S
D
u p p ly
e te c to r
S
S
S
C
D
D
S
P
I
V
o lta g e
O
and automatic display controller/driver for mono/LCD.
GPLB52A24B1 contains up to 64 segments and 32 commons,
forming maximum of 2048 dots LCD resolution, and
The
T
w o 1 6 -b it /
1 M
b y te s
A
u to -re lo a d
T im e rs
R
O M
S
P U
a
8 - b it
m
ic ro -p ro c e s s o r
GPLB51A24B1 contains up to 74 segments and 22 commons,
forming a maximum of 1628 dots LCD. The microprocessor can
implement software for audio processing, functional control and
others. In audio processing, melody and speech can be mixed
into one output. The GPLB52A24B1/ GPLB51A24B1 also carries
a high performance SPU voice engine to achieve 8-channel voice
with ADPCM/PCM data. It operates over a wide voltage range
from 2.4V through 5.5V, plus Low Voltage Reset function to assure
system is still functioning properly when power drops below a
specific level. Also, it features one 10-bit PWM driver and one
12-bit DAC with 8 audio channels to produce attractive sound
effects easily. Its large ROM area can be used to store both
program and audio data. There is a Serial Peripheral Interface
(SPI) controller built-in to facilitate communicating with other
devices. Furthermore, a SLEEP (power-down) function is also
1 5 3 6 b y te s
( I/O
)
R
A
M
8
8
6
P A 7 -0
P B 7 - 0
M
I/O
a x .2 2
o rts
L C
D
R
S
A
M
5 1 2 b y te s
P
P C 5 -0
2 2
C
o m
m
o n s
X
7 4
e g m e n ts o n o L C
m
D
D
riv e r
C O
M 2 1 - 0
S E G 7 3 -0
3. FEATURES
8-bit micro-processor
1536 bytes SRAM
1M bytes ROM
Operating voltage: 2.4V – 5.5V
Max. CPU operating speed:
– 8.0MHz @ 2.4V with 16MHz X’TAL
– 8.0MHz @ 2.4V with 16MHz ROSC
Programmable CPU clock: /2, /4, /8, /16, /32, /64 and /128
R-oscillator clock frequency
built in to extend battery life.
The GPLB52A24B1/
GPLB51A24B1 is designed with state-of-the-art technology to
fulfill LCD application needs, especially for hand-held products.
Six wake-up sources
Nine IRQ & two NMI Interrupts
Internal built-in regulator to supply core power (3.3V, for
3-battery application). Also it can turn off internal built-in
regulator, and use external 3.6V power to supply core power
(for 2-battery application).
2. BLOCK DIAGRAM
2.1. GPLB52A24B1
3 2 K H z
R O S C /X I
X O
3 2 K H z
Programmable LCD driver
1 0 - b it P W
riv e r
M
LCD size table:
R
-O s c illa to r/X ta l
A U D A
A U D B
D
3 2
K H z
S
y s te m lo c k e n.
C
G
O
s c illa to r
&
1 2 - b it
D
A C
D A C O
GPLB52A24B1
GPLB51A24B1
T im
e
b a s e
D r iv e r
C
S N /P B 4
P o w e r S u p p ly
V o lta g e e te c to r
S C K /P B 5
S D O /P B 6
S D I/P B 7
S
P I
D
Segment
Common
LCD Dots
64
32
74
22
T w
o 1 6 - b it /
1 M
b y te s
A u to -re lo a d
T im e rs
R
O M
2048
1628
S P
U
8 - b it
– Supports from 1/2 duty up to 1/32 duty
– 512 bytes dedicated LCD RAM
m
ic ro -p ro c e s s o r
1 5 3 6 b y te s
(I/O
)
R
A
M
8
8
6
P A 7 -0
P B 7 -0
P C 5 -0
M
a x .2 2
L C
D
R
S
A
M
5 1 2 b y te s
I/O P o r ts
– Supports normal type-B & type-C LCD waveform with or
without key scan
3 2
C
o m
m
o n s
X
6 4
e g m e n ts o n o L C D D r iv e r
m
C O M 3 1 -0
S E G 6 3 - 0
– Built-in voltage regulator to generate VLCD for LCD driver
– 32-level contrast control (VLCD=2.95V~6.85V)
– Power saving SLEEP mode
© Generalplus Technology Inc.
Proprietary & Confidential
4
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
Low Voltage Detector
Powerful 8-ch Sound Processing Unit(SPU)
– Variable tone-color sampling rate:
4-level (2.4V/2.6V/3.0V/3.3V) voltage detector
2.2V Low Voltage Reset
maximum
54KHz@CPU_Clock=7MHz
– 8-voice polyphony
Peripherals
– Max. 22 I/O pins (PA[7:0], PB[7:0], PC[5:0])
– Built-in 32.768KHz oscillator circuit for real time clock
function (X’tal or R-osc)
– Supports PCM/ADPCM tone-color table
4. APPICATION FIELD
– Built-in R-oscillator for system operating clock (external
resistor is needed)
Handheld LCD game
Educational toys (Electronic Learning Aids)
Data bank
– Internal time base generator
– Two 16-bit reloadable timer/counters
– Watchdog timer
Dictionary
– 12-bit DAC output and 10-bit PWM audio outputs
– Key scan function
Translator
– SEG[15:0] can be used to send key scan output
– IR carrier output
– One SPI serial interface I/O
© Generalplus Technology Inc.
Proprietary & Confidential
5
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
5. SIGNAL DESCRIPTION
5.1. GPLB52A24B1
Mnemonic
PIN No.
Type
Description
SEG63 – 57
SEG56 – 0
COM31– 22
COM21– 16
COM15 – 0
PA7 – 0
140-146
1-57
O
LCD driver segment output. SEG15 - 0 share pin with key scan port.
139-130
129-124
58-73
O
O
LCD driver common output.
LCD driver common output. COM21 - 0.
101-94
I/O
PA7-0 is a bi-directional I/O port, which can be software programmed as
wake up I/O.
PB0/ECLK
PB1/EXTI
PB2
86
87
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
PB0 is a shared pin with external timer clock input ECLK.
PB1 is a shared pin with external timer clock input EXTI.
PB2 is a bi-directional I/O port.
88
PB3
89
PB3 is a shared pin with IR carrier output IRO.
PB4 is a shared pin with SPI chip select SPI_CSN.
PB5 is a shared pin with SPI clock output SCK.
PB6 is a shared pin with SPI data output SDO.
PB7 is a shared pin with SPI data input SDI.
PC7-0 is a bi-directional I/O port.
PB4/SPI_CSN
PB5/SCK
PB6/SDO
PB7/SDI
PC5 - 0
90
91
92
93
85-80
106
ROSC/XI
Crystal input or ROSC input, connect to VDD(3V) through
a
resistor(option).
XO
105
108
78,75
74
O
I
Crystal output.
RESETB
AUDA, AUDB
DACO
System reset input, low active.
PWM audio output.
DAC output.
O
O
I
X32I
109
32.768KHz crystal input or connects to VDD(3V) through a resistor
(option).
X32O
110
111
O
I
32.768KHz crystal output.
TEST
Test input. Reserved for Generalplus testing.
LCD voltage generation. Charge pump capacitor interconnection pins.
LCD voltage generation. Charge pump capacitor interconnection pins.
LCD voltage generation. Voltage generated by charge pump.
LCD voltage generation.
CAP1P, CAP1N
CAP2P, CAP2N
VOUT
V4
114,115
116,117
118
P
P
P
P
P
P
P
P
P
P
P
P
P
P
120
V3
121
LCD voltage generation.
V2
122
LCD voltage generation.
V1
123
LCD voltage generation.
VLCD
119
LCD voltage generation. The highest voltage for LCD display.
Positive supply for regulator input.
VDD5V
VSSO
VDDA
VSSA
103
102
Ground for regulator.
113
Power for charge pump and IO pins.
112
Ground for charge pump and IO pins.
Positive supply for DAC (3.3V), connect to VDD.
3.3V power output from regulator. Regulator can be turned off when
external 3.3V is supplied.
VDDDAC
VDD
79
104
VSS
107
P
Ground reference for logic.
© Generalplus Technology Inc.
Proprietary & Confidential
6
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
Mnemonic
PIN No.
77
Type
P
Description
Positive supply for PWM driver.
PVDD
PVSS
76
P
Ground reference for PWM driver and for DAC.
Legend: I = Input, O = Output, P = Power
5.2. GPLB51A24B1
Mnemonic
SEG63 – 57
PIN No.
Type
Description
140-146
1-57
O
LCD driver segment output. SEG15 - 0 share pin with key scan port.
SEG56 – 0
SEG64-73
COM21– 16
COM15 – 0
PA7 – 0
139-130
129-124
58-73
O
O
LCD driver common output.
LCD driver common output. COM21 - 0.
101-94
I/O
PA7-0 is a bi-directional I/O port, which can be software programmed as
wake up I/O.
PB0/ECLK
PB1/EXTI
PB2
86
87
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PB0 is a shared pin with external timer clock input ECLK.
PB1 is a shared pin with external timer clock input EXTI.
PB2 is a bi-directional I/O port.
88
PB3
89
PB3 is a shared pin with IR carrier output IRO.
PB4 is a shared pin with SPI chip select SPI_CSN.
PB5 is a shared pin with SPI clock output SCK.
PB6 is a shared pin with SPI data output SDO.
PB7 is a shared pin with SPI data input SDI.
PC7-0 is a bi-directional I/O port.
PB4/SPI_CSN
PB5/SCK
PB6/SDO
PB7/SDI
PC5 - 0
90
91
92
93
85-80
ROSC/XI
Crystal input or ROSC input, connect to VDD(3V) through
a
106
I
resistor(option).
XO
105
108
O
I
Crystal output.
RESETB
AUDA, AUDB
DACO
System reset input, low active.
PWM audio output.
DAC output.
78,75
74
O
O
X32I
32.768KHz crystal input or connects to VDD(3V) through a resistor
(option).
109
I
X32O
110
111
O
I
32.768KHz crystal output.
TEST
Test input. Reserved for Generalplus testing.
LCD voltage generation. Charge pump capacitor interconnection pins.
LCD voltage generation. Charge pump capacitor interconnection pins.
LCD voltage generation. Voltage generated by charge pump.
LCD voltage generation.
CAP1P, CAP1N
CAP2P, CAP2N
VOUT
V4
114,115
116,117
118
P
P
P
P
P
P
P
P
P
P
P
P
120
V3
121
LCD voltage generation.
V2
122
LCD voltage generation.
V1
123
LCD voltage generation.
VLCD
119
LCD voltage generation. The highest voltage for LCD display.
Positive supply for regulator input.
VDD5V
VSSO
VDDA
VSSA
103
102
Ground for regulator.
113
Power for charge pump and IO pins.
112
Ground for charge pump and IO pins.
© Generalplus Technology Inc.
Proprietary & Confidential
7
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
Mnemonic
PIN No.
79
Type
P
Description
VDDDAC
VDD
Positive supply for DAC (3.3V), connect to VDD.
104
P
3.3V power output from regulator. Regulator can be turned off when
external 3.3V is supplied.
VSS
107
77
P
P
P
Ground reference for logic.
PVDD
PVSS
Positive supply for PWM driver.
76
Ground reference for PWM driver and for DAC.
Legend: I = Input, O = Output, P = Power
5.3. PAD Assignment
GPLB52A24B1
This IC substrate should be connected to VSS or floated
Note: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible.
© Generalplus Technology Inc.
Proprietary & Confidential
8
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
GPLB51A24B1
G P L B 5 1 A 2 4 B 1
This IC substrate should be connected to VSS or floated
Note: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible.
© Generalplus Technology Inc.
Proprietary & Confidential
9
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
6. FUNCTIONAL DESCRIPTIONS
6.1. Memories
The GPLB52A24B1/ GPLB51A24B1 contains 1M-byte ROM and 1536-byte SRAM.
6.2. Map of Memory and I/Os
*NMI SOURCE:
- LV DETECT
C P U V iew
$00000 - $03FFF
$04000 - $07FFF
0L
- TIMER1
SP U R A M
0
0H
G P R A M
$0000-$05FF
$1000-$11FF
$08000 - $0B FFF
$0C 000 - $0FFFF
$10000 - $13FFF
$14000 - $17FFF
1L
*INT SOURCE:
- TBL (2/4/8/16Hz)
- TBH (128/256/512/1KHz)
- TIMER0
1
1H
D P R A M
2L
2
2H
- TIMER1
IO R eg
$3000-$3FFF
- SPI
. . .
- SPU
R O M
$4000-
$7FFF
- FP (LCD frame)
(B ank)L
$F8000 - $FB FFF
$FC 000 - $FFFFF
31L
31H
31
256
R O M
$8000-
$B FFF
(B ank)H
SPU table , Test
program
$C 000-$C BB F
$C B C 0-C B FF
TEST interrupt
vector
R O M
$C C 00-$FFB F
$FFC 0-$FFE F
interrupt vector
N M I and reset
vector
$FFFA -$FFFD
$FFFE -$FFFF
B ank A ddress: $0
$C 000-$FFFF alw ays m apping into 0L
1. User program should start from $CC00. $C000-$CBFF is the test program area. $C000-$C103 is SPU ADPCM table data.
2. User program interrupt vector: $FFC0 ~ $FFEF.
3. Test program interrupt vector: $CBC0 ~ $CBFF.
6.3. Operating States
6.3.1. Operating mode
There are three operation modes involved in GPLB52A24B1/
GPLB51A24B1 standby, halt and operating. The following table
shows the differences between these modes.
In operating state, all functions (CPU, 32768Hz oscillator,
timer/counter, LCD driver…) are activated. Generally speaking,
this mode consumes the highest power.
6.3.2. Standby mode
Operating
ON
Halt
OFF
Standby
OFF
CPU
Write “07H” to P_3001H_ClkCtrl Register ($3001) and turn off
32768Hz oscillator to activate standby mode. The standby mode
is a mode where the device is placed in its lowest current
consumption state. In standby mode, all functions are turned off;
32768Hz oscillator
LCD driver
ON
ON
OFF
ON
ON/OFF
OFF
© Generalplus Technology Inc.
Proprietary & Confidential
10
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
6.6. LCD Voltage Generation
in addition, RAM and I/Os will remain in their previous states.
To achieve highly integrated circuit and save external components
as possible, the GPLB52A24B1/GPLB51A24B1 has built-in
charge pump circuit and operational amplifiers to generate LCD’s
bias voltages VLCD, V4, V3, V2 and V1. The charge pump
circuit can generate VPP approx. to 8V. With VPP as power
source, an operational amplifier is further to provide LCD panel’s
power supply, VLCD. The level of VLCD can be adjusted by
software. It is suggested that VLCD must be 0.7V higher than
VDD or abnormal operation will occur.
6.3.3. Halt mode
Write “07H” to P_3001H_ClkCtrl Register ($3001) but still keeps
32768Hz oscillator running to enter halt mode. In halt mode,
CPU clock halts and waits for an event (e.g. key press, timer
overflow) to wake up. The 32768Hz related functions, such as
timer/counter and LCD driver, may remain active in the halt mode.
The following figure is the GPLB52A24B1/ GPLB51A24B1 state
diagram:
6.7. Low Voltage Detection
Write $07h to
CPU_Clk_Ctrl register,
The GPLB52A24B1/GPLB51A24B1 provides a 4-level (Software
programmable) low voltage detector to detect low voltage events.
Users can turn on the low voltage detection that monitors VDD
periodically to check whether it is lower than the given value. In
addition, if LV NMI is enabled, an NMI will be issued to notify CPU
if power voltage drops below the given value. Also, the voltage
detector will generate a system reset if power supply voltage
drops below 2.2V.
32768 oscillator OFF
OPERATING
STANDBY
Wake-up or user reset
HALT
6.8. Watchdog Timer (WDT)
An on-chip watchdog timer is also available in the
GPLB52A24B1/GPLB51A24B1. The WDT is designed to recover
the system from unexpected operations. In some cases, if WDT
is not cleared within one second, the WDT will generate a system
reset to restart system. If WDT is enabled, the WDT should be
cleared periodically to avoid accidental reset. The WDT can be
cleared through software programming. Note that the WDT only
works when 32768Hz clock is activated.
GPLB52A24B1/ GPLB51A24B1 State Diagram
6.4. Speech and Melody, PWM and DAC
The GPLB52A24B1/GPLB51A24B1 uses a high performance SPU
voice engine to archive 8-channel voice with ADPCM/PCM code.
The SPU also supports automatic zero-crossing concatenate
function. A hardware multiplier is also embedded in this SPU for
software usage. The fixed addresses of RAM area $0000 -
$007F is designed as address pointers and a data buffer for the
8-channel speech/melody generation. There is one 12-bit D/A
converter with 4mA driving current capability for audio output,
DACO. There is one 10-bit PWM for audio outputs, AUDA and
AUDB.
6.9. SPI Controller
A
Serial Peripheral Interface (SPI) controller is built in
GPLB52A24B1/GPLB51A24B1 to facilitate communicating with
other devices. There are four control signals on SPI including
SPICSN, SPICLK (SCK), SPIRX (SDI), and SPITX (SDO). The
four signals are shared with PortB4, PortB5, PortB6 and PortB7.
While SPI module is enabled by corresponding control bit, these
four pins cannot be GPIOs and any setting on corresponding
GPIO control register will have no effect. Four types of operation
mode are supported as follows:
6.5. LCD Controller/Driver
The GPLB52A24B1/GPLB51A24B1 contains a 2048-dot LCD
controller/driver and supports monochrome LCD control.
Programmers are able to define the LCD configuration by setting
up the LCD Control Register. Once the LCD configuration is
completed, the desired pattern can be displayed by filling the LCD
buffer with proper data. The LCD driver can also operate during
sleep by keeping 32768Hz oscillator running. The LCD driver in
GPLB52A24B1/GPLB51A24B1 supports 1/2 – 1/32 duty and 1/3 -
1/7 bias.
© Generalplus Technology Inc.
Proprietary & Confidential
11
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
SPICLK
SPICLK
SPICSN
SPIRX
SPICSN
SPIRX
Q
MSB
MSB
LSB
LSB
Q
MSB
MSB
LSB MSB
LSB MSB
SPITX
SPIOE
SPITX
SPIOE
8 bits
8 bits
Master Mode, SPO = 1, SPH=1
Master Mode, SPO = 0, SPH=0
6.10. Mask Options
SPICLK
SPICSN
6.10.1. 32768Hz oscillator
1). X’TAL
2). R-oscillator
SPIRX
SPITX
Q
MSB
MSB
LSB
LSB
Q
6.10.2. System clock oscillator
1). R-oscillator
2). X’TAL
8 bits
6.10.3. Internal VDD regulator
SPIOE
1). Internal VDD regulator on
2). Internal VDD regulator off
Master Mode, SPO = 0, SPH=1
6.10.4. LCD dots
1). 32 commons x 64 segments
2). 22 commons x 74 segments
SPICLK
SPICSN
SPIRX
SPITX
MSB
MSB
LSB
Q
LSB
8 bits
SPIOE
Master Mode, SPO = 1, SPH=0
© Generalplus Technology Inc.
Proprietary & Confidential
12
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics
Symbol
Ratings
DC Supply Voltage
V+
VIN
TA
< 7.0V
Input Voltage Range
Operating Temperature
Storage Temperature
-0.5V to V+ + 0.5V
0℃ to +70℃
-50℃ to +150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational
conditions see AC/DC Electrical Characteristics.
7.2. DC Characteristics (VDD5V=4.5V, for 3-battery application, internal regulator enabled output, TA=25℃)
Limit
Characteristics
Operating Voltage
Symbol
Unit
Test Condition
Min.
Typ.
Max.
VDD5V
2.7
-
5.5
V
For 3-battery
CPU = 6.0MHz @ 4.5V
F
IOP1
-
-
5
6
-
-
mA
mA
FXTAL = 12.0MHz, no load, DAC disabled,
PWM disabled.
Operating Current
FCPU = 8.0MHz @ 4.5V
IOP2
FROSC 16.0MHz, no load, DAC
=
disabled, PWM disabled.
VDD5V = 4.5V, 32K X’tal ON, Strobe off,
LCD ON, 1/7 Bias, VLCD=6.37V, no
LCD panel.
IHALT1
-
-
40
15
-
-
μA
μA
Halt Current
VDD5V = 4.5V, 32K X’tal ON, Strobe off,
LCD OFF, no LCD panel.
IHALT2
ISTBYR
IOH
Standby Current (Regulator on)
PWM Audio Output Current
-
-
-60
-170
60
160
-
10
μA
mA
mA
mA
mA
V
VDD5V = 4.5V, VDD regulator on, all off
VDD5V = 4.5V, VOH = 4.05V
VDD5V = 4.5V, VOH = 3.15V
VDD5V = 4.5V, VOL = 0.45V
VDD5V = 4.5V, VOL = 1.35V
VDD5V = 4.5V
-
-
-
-
-
-
PWM Audio Output Current
IOL
-
0.7VDD
-
-
Input High Level
VIH
VIL
IOH
IOL
-
Input Low Level
-
0.3VDD
V
VDD5V = 4.5V
Output High Current (I/O)
-7.0
4.0
-
-
-
mA
mA
VDD5V = 4.5V, VOH = 3.15V
VDD5V = 4.5V, VOL = 1.35V
Output Sink Current (I/O)
Input Pull-Low Resistor
PA(weak pull)
-
200
65
RPL
-
-
-
-
KΩ
KΩ
VIN =4.5V
PA(strong pull)
PB,PC
65
Input Pull-High Resistor
PA(weak pull)
240
45
45
-
RPH
VIN = 0V
PA(strong pull)
PB,PC
LCD Driver Voltage
(VLCD - VSS)
2.46
5.67
6.75
-
V
V
VDD5V = 4.5V, 1/5 bias, no load
VDD5V = 4.5V, 1/6 bias, no load
FOSC = 14MHz @ 4.5V
VLCD
2.93
-
OSC Resistor
CPU Clock
ROSC
FCPU
-
-
37
-
KΩ
MHz
8.0
FCPU = FOSC/2 @ 2.4V
Note: VLCD should be higher than VDD to prevent forward biasing the p-n junction of I/O output PMOS.
© Generalplus Technology Inc.
Proprietary & Confidential
13
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
7.3. DC Characteristics (VDD5V=VDD=3.0V, for 2-battery application, internal regulator output disabled, TA=25℃)
Limit
Characteristics
Operating Voltage
Symbol
Unit
Test Condition
Min.
Typ.
Max.
VDD5V
2.4
-
3.6
V
For 2-battery
CPU = 6.0MHz @ 3.0V
F
IOP1
-
-
5
6
-
-
mA
mA
FXTAL = 12.0MHz, no load, DAC disabled,
PWM disabled.
Operating Current
FCPU = 8.0MHz @ 3.0V
IOP2
FROSC 16.0MHz, no load, DAC
=
disabled, PWM disabled.
VDD5V = 3.0V, 32K X’tal ON, Strobe off,
LCD ON, 1/7 Bias, VLCD=6.37V, no
LCD panel
IHALT1
-
-
30
10
-
-
μA
μA
Halt Current
VDD5V = 3.0V, 32K X’tal ON, Strobe off,
LCD OFF, no LCD panel
VDD5V = 3.0V, all off
IHALT2
ISTBY
IOH
Standby Current (Regulator off)
PWM Audio Output Current
-
1
-30
-90
30
80
-
2
μA
mA
mA
mA
mA
V
-
-
VDD5V = 3.0V, VOH = 2.7V
VDD5V = 3.0V, VOH = 2.1V
VDD5V = 3.0V, VOL = 0.3V
VDD5V = 3.0V, VOL = 0.9V
VDD5V = 3.0V
-
-
-
-
PWM Audio Output Current
IOL
-
0.7VDD
-
-
Input High Level
Input Low Level
Output High Current (I/O)
Output Sink Current (I/O)
Input Pull-Low Resistor
PA(weak pull)
VIH
VIL
IOH
IOL
-
-
0.3VDD
V
VDD5V = 3.0V
-3.0
3.0
-
-
-
mA
mA
VDD5V = 3.0V, VOH = 2.1V
VDD5V = 3.0V, VOL = 0.9V
-
165
55
RPL
-
-
-
-
KΩ
KΩ
V
V
IN = 3.0V
PA(strong pull)
PB,PC
55
Input Pull-High Resistor
PA(weak pull)
380
70
70
-
RPH
IN = 0V
PA(strong pull)
PB,PC
LCD Driver Voltage
(VLCD - VSS)
2.46
5.67
6.75
-
V
V
VDD5V = 3.0V, 1/5 bias, no load
VDD5V = 3.0V, 1/6 bias, no load
FOSC = 14MHz @ 3.0V
VLCD
2.93
-
OSC Resistor
CPU Clock
ROSC
FCPU
-
-
37
-
KΩ
MHz
8.0
FCPU = FOSC/2 @ 2.4V
Note: VLCD should be higher than VDD to prevent forward biasing the p-n junction of I/O output PMOS.
© Generalplus Technology Inc.
Proprietary & Confidential
14
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
7.4. The Relationship between the ROSC and the FOSC
,
7.6. The Relationship between the FCPU and the IOP
TA = 25℃
7.6.1. VDD = 3.0V, TA = 25℃
Fcpu vs Iop
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
Fcpu(MHz)
7.5. The Relationship between the F32K and the
R32K , TA = 25℃
© Generalplus Technology Inc.
Proprietary & Confidential
15
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
8. APPLICATION CIRCUITS
8.1. 2048 Dots LCD Driver, 64 Segments × 32 Commons, for 3-battery application, Internal 3.3V Regulator Enabled,
12-bit DAC Enabled, ROSC14M XTAL32K Selected- (1)
LCD Panel (32x64)
VDDB
AUDA
AUDB
PVDD
PVSS
(PWM Power)
(PWM Ground)
25pF * 1
X32I
VDD5V
VDDA
X32O
25pF * 1
VDDDAC
VDD
VSSB
GPLB52A24B1
0.1u
47u
10u
VSSO
VSS
Speaker
47
VDD
SPN
SPP
VSS
INN
IO port
DACO
VSSA
RESET
VSSB
CE
GPY0030B
0.1
0.22u
DACO
VSSB
VREF
ACIN
R3
R4
1K
0.1μF
VSSB
0.01u
470
C12
8
6
VSSB
SEG0
* 2
SEG1
SEG2
SEG14
SEG15
1/3, 1/4, 1/5,1/6, 1/7 Bias
0.1
0.1
0.1
0.1
0.1
1uF
F
V1
V2
V3
V4
VLCD
VOUT
F
.....
F
F
F
.....
PA1
PA2
PA3
PA4
PA5
CAP1P
0.1
0.1
F
CAP1N
CAP2P
CAP2N
VSSB
.....
.....
F
.....
.....
Note*1: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~60K and CL1=CL2 =26~36pF (including
PCB parasitic loading; for example, user should apply additional 20~30pF on X32I and X32O if PCB parasitic loading is 6pF)
Note*2: These capacitor values are for design guidance only. The ratio of capacitance of VOUT to the capacitance of CAP1N/CAP1P/CAP2N/CAP2P is
recommended to be 10:1. Generally, capacitance of VLCD and V1~V4 is 0.1uF and can’t larger than capacitance of VOUT. But for larger LCD panel, 1uF
capacitance for VLCD and V1~V4, 2.2uF capacitance for VOUT and 0.22uF capacitance for CAP1P/CAP1N/CAP2P/CAP2N is recommended.
© Generalplus Technology Inc.
Proprietary & Confidential
16
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
8.2. 2048 Dots LCD Driver, 64 Segments × 32 Commons, Internal 3.3V Regulator Disabled, for 2-battery application,
12-bit DAC Enabled, ROSC14M XTAL32K Selected - (2)
Note*1: VDD should not exceed 3.6V.
Note*2: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~60K and CL1=CL2 =26~36pF (including
PCB parasitic loading, for example, user should apply additional 20~30pF on X32I and X32O if PCB parasitic loading is 6pF)
Note*3: These capacitor values are for design guidance only. The ratio of capacitance of VOUT to the capacitance of CAP1N/CAP1P/CAP2N/CAP2P is
recommended to be 10:1. Generally, capacitance of VLCD and V1~V4 is 0.1uF and can’t larger than capacitance of VOUT. But for larger LCD panel, 1uF
capacitance for VLCD and V1~V4, 2.2uF capacitance for VOUT and 0.22uF capacitance for CAP1P/CAP1N/CAP2P/CAP2N is recommended.
© Generalplus Technology Inc.
Proprietary & Confidential
17
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
8.3. 2048 Dots LCD Driver, 64 Segments × 32 Commons, for 3-battery application, Internal 3.3V Regulator Enabled,
10-bit PWM Driver Enabled, XTAL12M ROSC32K Selected - (3)
LCD Panel (32x64)
20pF * 1
20pF * 1
12MHz
VDDB
AUDA
AUDB
PVDD
PVSS
(PWM Powr)
(PWGroud)
0.1μF
VDD
X32I
30pF
VDD5V
VDDA
X32O
GPLB52A24B1
VDDDAC
VDD
VDD
0.1u
47u
10u
VSSO
VSS
RESET
VSSA
VSSB
0.1μF
6
8
VSSB
VSSB
SEG0
SEG1
SEG2
SEG14
SEG15
.....
* 2
1/3, 1/4, 1/5,1/6, 1/7 Bias
0.1 F
V1
.....
0.1 F
V2
PA1
0.1 F
V3
0.1 F
V4
VLCD
VOUT
.....
.....
0.1 F
1uF
PA2
PA3
PA4
PA5
CAP1P
0.1 F
0.1 F
CAP1N
CAP2P
CAP2N
VSSB
.....
.....
Note*1: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
Note*2: These capacitor values are for design guidance only. The ratio of capacitance of VOUT to the capacitance of CAP1N/CAP1P/CAP2N/CAP2P is
recommended to be 10:1. Generally, capacitance of VLCD and V1~V4 is 0.1uF and can’t larger than capacitance of VOUT. But for larger LCD panel, 1uF
capacitance for VLCD and V1~V4, 2.2uF capacitance for VOUT and 0.22uF capacitance for CAP1P/CAP1N/CAP2P/CAP2N is recommended.
© Generalplus Technology Inc.
Proprietary & Confidential
18
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
8.4. 1628 Dots LCD Driver, 74 Segments ×22 Commons, for 3-battery application, Internal 3.3V Regulator Enabled,
10-bit PWM Driver Enabled, XTAL12M ROSC32K Selected - (4)
LCD Panel (22x74)
20pF * 1
20pF * 1
12MHz
VDDB
AUDA
AUDB
PVDD
PVSS
(PWM Powr)
(PWGroud)
0.1μF
VDD
X32I
30pF
VDD5V
VDDA
X32O
GPLB51A24B1
VDDDAC
VDD
VDD
0.1u
47u
10u
VSSO
VSS
RESET
VSSA
VSSB
0.1μF
6
8
VSSB
VSSB
SEG0
SEG1
SEG2
SEG14
SEG15
.....
* 2
1/3, 1/4, 1/5,1/6, 1/7 Bias
0.1 F
V1
.....
0.1 F
V2
PA1
0.1 F
V3
0.1 F
V4
VLCD
VOUT
.....
.....
0.1 F
1uF
PA2
PA3
PA4
PA5
CAP1P
0.1 F
0.1 F
CAP1N
CAP2P
CAP2N
VSSB
.....
.....
Note*1: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
Note*2: These capacitor values are for design guidance only. The ratio of capacitance of VOUT to the capacitance of CAP1N/CAP1P/CAP2N/CAP2P is
recommended to be 10:1. Generally, capacitance of VLCD and V1~V4 is 0.1uF and can’t larger than capacitance of VOUT. But for larger LCD panel, 1uF
capacitance for VLCD and V1~V4, 2.2uF capacitance for VOUT and 0.22uF capacitance for CAP1P/CAP1N/CAP2P/CAP2N is recommended.
© Generalplus Technology Inc.
Proprietary & Confidential
19
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
8.5. DAC Output with Generalplus Audio Driver GPY0030B (for high quality audio output) - (4)
© Generalplus Technology Inc.
Proprietary & Confidential
20
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
8.6. Current Mode DAC Speaker Driver with BJT
VDD5V
RB1: 10K ~ 50K
RB2: 820 ~ 1.5K
VDD5V
C1: 0.1 F ~ 1 F
RB1: 680 ~ 1.5K
C1: 0.1 F ~ 1
F
4
~ 8
32
~ 64
RB1
C1
DACO
C1
DACO
RB2
8050
8050
RB1
Figure 1
Figure 2
VDD5V
VDD5V
RB1: 2K~10K C1: 1 F~10
RB2: ~ 1K C2: ~ 0.1 F
F
RB1: 2K~10K C1: 1 F~10 F
RB2: ~ 1K
C2: ~ 0.1 F
4
~8
4
~64
RB
C2
Enable
C2
DACO
RB1
DACO
8050
8050
C1
C1
RB2
RB2
Figure 3
Figure 4
VDD5V
RB1: ~ 360 (Vol)
RE1: ~ 4.7
4
~64
DACO
8050
RE1
1N4148
RB1
Figure 5
Figure 1: The simplest CKT uses with low impedance speaker. It has high operation current, but the cost is the cheapest.
Figure 2: It is the same as Figure 1 but a high impedance speaker is used.
Figure 3: The CKT has low pass filter. It can provide higher speech quality, but it always takes high operation current.
Figure 4: Improved version of Figure 3. The standby current can be controlled by enable pin.
Figure 5: The current mirror mode. It is able to control the volume. In addition, it has more stable and lower operation current than Figure 1-3.
© Generalplus Technology Inc.
Proprietary & Confidential
21
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
8.7. Serial Communications between GPLB52A24B1/GPLB51A24B1 and GPUSB101A USB Controller- (6)
PB5
PB7
SPI_CLK
SPI_TX
GPUSB101A
GPLB52A24B1
SPI_RX
PB6
PB4
SPI_CSN
© Generalplus Technology Inc.
Proprietary & Confidential
22
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
9. PACKAGE/PAD LOCATIONS
9.1. Ordering Information
Product Number
Package Type
Chip form
GPLB51A24B1 - NnnV - C
GPLB52A24B1 - NnnV - C
Chip form
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
© Generalplus Technology Inc.
Proprietary & Confidential
23
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
Proprietary & Confidential
24
Aug 20, 2013
Version: 1.2
GPLB52A24B1/
GPLB51A24B1
11. REVISION HISTORY
Date
Revision #
Description
update application circuit and it note for 32K XTAL
Page
Aug 20, 2013
Jun 14, 2012
Jun. 10, 2011
1.2
1.1
1.0
Add section of 7.2~7.4
Original
13
23
© Generalplus Technology Inc.
Proprietary & Confidential
25
Aug 20, 2013
Version: 1.2
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