GPM8F1033A-nnnA-T [GENERALPLUS]
30/20-pin Microcontroller with 128/64/32/18KB Flash Memory;
| 型号： | GPM8F1033A-nnnA-T |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 30/20-pin Microcontroller with 128/64/32/18KB Flash Memory 微控制器 |
| 文件： | 总103页 (文件大小：1559K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPM8F1129A
GPM8F1065A
GPM8F1033A
GPM8F1019A
30/20-pin Microcontroller with
128/64/32/18KB Flash Memory
Jan. 21, 2015
Version 1.0
Generalplus Technology Inc. reserves the right to change this documentation without prior notice. Information provided by Generalplus Technology Inc. is
believed to be accurate and reliable. However, Generalplus Technology Inc. makes no warranty for any errors which may appear in this document. Contact
Generalplus Technology Inc. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by Generalplus
Technology Inc. for any infringement of patent or other rights of third parties which may result from its use. In addition, Generalplus products are not
authorized for use as critical components in life support devices/systems or aviation devices/systems, where a malfunction or failure of the product may
reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPM8F1129/1065/1033/1019A
Table of Contents
PAGE
ITable of Contents ........................................................................................................................................................................................... 2
30/20 PIN 8-BIT MICROCONTROLLER .......................................................................................................................................................... 5
WITH 128/64/32/18KB FLASH......................................................................................................................................................................... 5
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 5
2. FEATURES.................................................................................................................................................................................................. 5
3. BLOCK DIAGRAM...................................................................................................................................................................................... 7
3.1. GPM8F1129A ..................................................................................................................................................................................... 7
3.2. GPM8F1065A ..................................................................................................................................................................................... 8
3.3. GPM8F1033A ..................................................................................................................................................................................... 9
3.4. GPM8F1019A ................................................................................................................................................................................... 10
4. SIGNAL DESCRIPTIONS ......................................................................................................................................................................... 11
4.1. PIN MAP ............................................................................................................................................................................................ 13
5. FUNCTIONAL DESCRIPTIONS................................................................................................................................................................ 14
5.1. CPU .................................................................................................................................................................................................. 14
5.1.1. CPU Features ......................................................................................................................................................................... 14
5.1.2. Arithmetic Logic Unit (ALU)..................................................................................................................................................... 14
5.1.3. Accumulator A register............................................................................................................................................................ 14
5.1.4. B Register ............................................................................................................................................................................... 14
5.1.5. Program Status Word (PSW) .................................................................................................................................................. 14
5.1.6. Program Counter (PC)............................................................................................................................................................ 14
5.2. MEMORY ............................................................................................................................................................................................ 16
5.2.1. Introduction ............................................................................................................................................................................. 16
5.2.2. Program Memory Allocation.................................................................................................................................................... 16
5.2.3. Data Memory Allocation.......................................................................................................................................................... 23
5.2.4. Memory Related SFR ............................................................................................................................................................. 24
5.2.4.1. Program write enable bit .............................................................................................................................................. 24
5.2.4.2. Data pointer registers................................................................................................................................................... 24
5.2.4.3. Stack pointer ................................................................................................................................................................ 24
5.3. SPECIAL FUNCTION REGISTERS (SFR) ................................................................................................................................................ 28
5.4. POWER SAVING MODE ........................................................................................................................................................................ 30
5.4.1. Introduction ............................................................................................................................................................................. 30
5.4.2. IDLE mode.............................................................................................................................................................................. 30
5.4.3. STOP mode ............................................................................................................................................................................ 30
5.5. INTERRUPT SYSTEM............................................................................................................................................................................ 32
5.6. RESET SOURCE .................................................................................................................................................................................. 39
5.6.1. Introduction ............................................................................................................................................................................. 39
5.6.2. Power-On Reset (POR) .......................................................................................................................................................... 39
5.6.3. Low Voltage Reset (LVR)........................................................................................................................................................ 39
5.6.4. Low Voltage Detection (LVD) .................................................................................................................................................. 39
5.6.5. Pad Reset (PAD_RST)............................................................................................................................................................ 39
5.6.6. Watchdog Timer Reset (WDT_RST)....................................................................................................................................... 40
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5.6.7. Other Reset Sources .............................................................................................................................................................. 41
5.7. CLOCK SOURCE.................................................................................................................................................................................. 45
5.8. SLOW CLOCK...................................................................................................................................................................................... 47
5.9. I/O PORTS.......................................................................................................................................................................................... 47
5.10. TIMER MODULE................................................................................................................................................................................... 54
5.10.1. Introduction......................................................................................................................................................................... 54
5.10.2. Timer 0/1 ............................................................................................................................................................................ 55
5.10.2.1. Timer 0: Mode 0(13-Bit Timer) ..................................................................................................................................... 58
5.10.2.2. Timer 0: Mode 1(16-bit Timer)...................................................................................................................................... 59
5.10.2.3. Timer 0: Mode 2(8-Bit Timer with Auto-reload Function).............................................................................................. 60
5.10.2.4. Timer 0: Mode 3(Two 8-Bit Timers).............................................................................................................................. 61
5.10.2.5. Timer 1: Mode 0(13-Bit Timer) ..................................................................................................................................... 61
5.10.2.6. Timer 1: Mode 1(16-Bit Timer) ..................................................................................................................................... 62
5.10.2.7. Timer 1: Mode 2(8-Bit Timer with Auto-reload Function).............................................................................................. 63
5.10.2.8. Timer 1: Mode 3 ........................................................................................................................................................... 63
5.10.3. Timer 2 ............................................................................................................................................................................... 64
5.10.3.1. Timer Mode .................................................................................................................................................................. 64
5.10.3.2. Reload of Timer 2......................................................................................................................................................... 64
5.10.3.3. Compare Functions...................................................................................................................................................... 65
5.10.3.4. Capture Functions........................................................................................................................................................ 67
5.10.3.5. Timer 2 Related Registers............................................................................................................................................ 68
5.11. UART0 .............................................................................................................................................................................................. 71
5.11.1.UART0: Mode 0(Synchronous Shift register).......................................................................................................................... 71
5.11.2.UART0: Mode 1(8-Bit UART, Variable Baud Rate, Timer1 Clock Source).............................................................................. 72
5.11.3.UART0: Mode 2(9-Bit UART, Fixed Baud Rate) ..................................................................................................................... 72
5.11.4.UART0: Mode 3(9-Bit UART, Variable Baud Rate, Timer1 Clock Source).............................................................................. 72
5.11.5.UART0 Related Registers....................................................................................................................................................... 72
5.12. SPI .................................................................................................................................................................................................... 74
5.13. I2C .................................................................................................................................................................................................... 78
5.13.1. I2C Bus Protocol................................................................................................................................................................. 78
5.13.2. Bus Arbitration Procedures................................................................................................................................................. 79
5.14. CARRIER MODULATOR/DEMODULATOR TIMER ...................................................................................................................................... 82
5.14.1. Carrier Generator ............................................................................................................................................................... 83
5.14.2. Modulator............................................................................................................................................................................ 84
5.14.2.1. PWM output with carrier signal mode .......................................................................................................................... 86
5.14.2.2. PWM output without carrier signal mode ..................................................................................................................... 86
5.14.2.3. Direct control mode...................................................................................................................................................... 86
5.14.3. Output control..................................................................................................................................................................... 86
5.14.4. Extended space operation.................................................................................................................................................. 87
5.14.5. Carrier detect and demodulator.......................................................................................................................................... 90
5.15. ALPHABETICAL LIST OF INSTRUCTION SET............................................................................................................................................ 93
5.15.1. Arithmetic Operations......................................................................................................................................................... 93
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5.15.2. Logic Operations ................................................................................................................................................................ 93
5.15.3. Boolean Operations............................................................................................................................................................ 94
5.15.4. Data Transfers.................................................................................................................................................................... 94
5.15.5. Program Branches.............................................................................................................................................................. 96
6. ELECTRICAL CHARACTERISTICS......................................................................................................................................................... 97
6.1. ABSOLUTE MAXIMUM RATING .............................................................................................................................................................. 97
6.2. DC CHARACTERISTICS (VDD = 5V, TA = 25℃) .................................................................................................................................... 97
6.3. DC CHARACTERISTICS (VDD = 3.3V, TA = 25℃) ................................................................................................................................. 97
6.4. AC CHARACTERISTICS (TA = 25℃)...................................................................................................................................................... 98
7. APPLICATION CIRCUITS......................................................................................................................................................................... 99
8. PACKAGE/PAD LOCATIONS................................................................................................................................................................. 100
8.1. ORDERING INFORMATION .................................................................................................................................................................. 100
8.2. PACKAGE INFORMATION .................................................................................................................................................................... 101
9. DISCLAIMER........................................................................................................................................................................................... 103
10.REVISION HISTORY............................................................................................................................................................................... 104
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GPM8F1129/1065/1033/1019A
30/20 PIN 8-BIT MICROCONTROLLER
WITH 128/64/32/18KB FLASH
1. GENERAL DESCRIPTION
Power On Reset (POR)
Low Voltage Reset (LVR)
The GPM8F1129A/GPM8F1065A/GPM8F1033A/GPM8F1019A,
a highly integrated microcontroller, integrates a pipelined 1T 8051
Pad Reset (PAD_RST)
Watchdog Reset (WDT_RST)
Software Reset (S/W_RST)
CPU,
1.5K-byte
XRAM,
256-byte
IDM
SRAM
and
128K/64K/32K/18K-byte program Flash memory.
It also
Stop mode Reset (STOP_RST)
Miss Clock Reset (MISS_CLK_RST)
Flash Related Error Reset (FLASH_ERR_RST)
contains a maximum of 23 programmable multi-functional I/Os,
Timer0/1/2, UART0, SPI (master), I2C, and CMDT for a variety of
applications. It operates over a wide voltage range from 1.8V
through 5.5V and wide temperature range from -5℃ ~ 70℃. It
Programmable Watchdog Timer
A time-base generator
An event timer
features two power management modes for power saving
purpose. To make development and debug work more easily, an
on-chip debug circuit is included to facilitate full speed in-system
debug. For more details about GPM8F series, please refer to
the feature list in the following section.
System supervisor
I/O Ports
Max. 23 multifunction bi-directional I/Os
Each incorporate with pull-up resistor, pull-down resistor,
output high, output low or floating input, depending on
the settings in the corresponding registers
I/O ports with 12mA current sink
2. FEATURES
CPU
I/O ports with 12mA current drive
High speed, high performance 1T 8051
Two 16-bit Timer/Counter (Timer 0/1)
100% software compatible with industry standard 8051
Pipeline RISC architecture enhances executing
instructions 10 times faster than standard 8051
Up to 16MHz clock operation
Timer mode with clock source selectable
Auto reload 8-bit timers
One Powerful Timer2 with 16-bit Compare/Capture Unit
Timer mode with clock source selectable
Auto reload 16-bit timers
Memories
1.5K bytes XRAM
Event capturing
256 bytes internal Data Memory (IDM) SRAM
Up to 128/64/32/18K bytes Flash with high endurance
Minimum of 100K progam/erase cycles
Minimum of 10 years data retention
Page size 1kB
Digital signals generator
Pulse width modulation and measurement
UART0
One synchronous mode
Three asynchronous modes
SPI (master mode)
Programming lock level for software security
Programmable phase and polarity of master clock
Clock Management
Programmable master clock frequency
Auto read/write function
Internal oscillator: 16MHz±1.5% @ 2.0V~5.5V
Crystal input with 1MHz~16MHz
Max SPI clock: 4MHz (FOSC /4) @16MHz
Slow Clock
I2C (master/slave mode)
Internal oscillator: 4KHz
Carrier Modulator/Demodulator Timer (CMDT)
Power Management
One 8-bit Timer A for carrier generation and detection
One 16-bit Timer B for envelop generation and detection
Drives IR_TX pin for remote control communication
Receive IR signal from IR_RX pin
One STOP mode for power saving
One IDLE mode for only peripheral operation
Interrupt Management
Up to 9 internal interrupt sources
Built-in Low Voltage Reset
Trigger level: 1.9V
Built-in low Voltage Detect
Programmable level: 2.3V, 2.5V, 3.3V, 3.5V
Up to 5 external interrupt sources
Up to 8 keyboard Interrupt sources
Reset Management
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On-chip Debug Unit
C compatible Development Tools
IDM
CPU OSC.
Speed Flash
(MHz) (Byte)
XDM
Part NO.
Voltage(V)
CMDT IR Tx/Rx
IO No.
PKG
(Byte)
(Byte)
INT
XTAL
GPM8F1129A
GPM8F1065A
GPM8F1033A
GPM8F1019A
1.8~5.5
1.8~5.5
1.8~5.5
1.8~5.5
16
16
16
16
128K
64K
32K
18K
256
256
256
256
1.5k
1.5k
1.5k
1.5k
Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
23/15 SSOP30/SSOP20
23/15 SSOP30/SSOP20
23/15 SSOP30/SSOP20
23/15 SSOP30/SSOP20
3. BLOCK DIAGRAM
3.1. GPM8F1129A
ICESCK/RESET
ICESDA
Power
saving
(P13)XTI
XTAL
circuit
8-bit CPU & ICE
(P12)XTO
controller
128K bytes Flash
Internal OSC
VDD
VSS
VREG
1.5K Bytes XRAM
Timer01
Regulator & POR & LVR
Watchdog Timer
RESET Management
Timer2
CMDT
P3[4:0]
PORT 3[4:0]
PORT 2[3:0]
PORT 1[7:2]
PORT 0[7:0]
IR_TX(P21 or P34)
IR_RX(P20)
P2[3:0]
P1[7:2]
P0[7:0]
Interrupt Management
I2C
256-byte IDM
UART
SPI
(Master Mode)
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3.2. GPM8F1065A
ICESCK/RESET
Power
saving
(P13)XTI
XTAL
circuit
8-bit CPU & ICE
ICESDA
(P12)XTO
controller
64K bytes Flash
Internal OSC
VDD
VSS
VREG
1.5K Bytes XRAM
Timer01
Regulator & POR & LVR
Watchdog Timer
RESET Management
Timer2
P3[4:0]
PORT 3[4:0]
PORT 2[3:0]
PORT 1[7:2]
PORT 0[7:0]
IR_TX(P21 or P34)
P2[3:0]
P1[7:2]
P0[7:0]
CMDT
IR_RX(P20)
Interrupt Management
I2C
256-byte IDM
UART
SPI
(Master Mode)
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3.3. GPM8F1033A
ICESCK/RESET
Power
saving
(P13)XTI
XTAL
circuit
8-bit CPU & ICE
ICESDA
(P12)XTO
controller
32K bytes Flash
Internal OSC
VDD
VSS
VREG
1.5K Bytes XRAM
Timer01
Regulator & POR & LVR
Watchdog Timer
RESET Management
Timer2
P3[4:0]
PORT 3[4:0]
PORT 2[3:0]
PORT 1[7:2]
PORT 0[7:0]
IR_TX(P21 or P34)
P2[3:0]
P1[7:2]
P0[7:0]
CMDT
IR_RX(P20)
Interrupt Management
I2C
256-byte IDM
UART
SPI
(Master Mode)
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3.4. GPM8F1019A
ICESCK/RESET
Power
saving
(P13)XTI
XTAL
circuit
8-bit CPU & ICE
ICESDA
(P12)XTO
controller
18K bytes Flash
Internal OSC
VDD
VSS
VREG
1.5K Bytes XRAM
Timer01
Regulator & POR & LVR
Watchdog Timer
RESET Management
Timer2
P3[4:0]
PORT 3[4:0]
PORT 2[3:0]
PORT 1[7:2]
PORT 0[7:0]
IR_TX(P21 or P34)
P2[3:0]
P1[7:2]
P0[7:0]
CMDT
IR_RX(P20)
Interrupt Management
I2C
256-byte IDM
UART
SPI
(Master Mode)
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4. SIGNAL DESCRIPTIONS
SSOP30:
Type: I = Input, O = Output, S = Supply
Pin Name SSOP30
Type
NA
I/O
S
Description
NC
P23
1
Not connected
2
Port 2’s bit 3/ I2CSDA
Regulator output
VREG
ICESDA
ICESCK
P12
3
4
I/O
I/O
I/O
S
ICE data input/output
ICE clock input/ RESET
Port 1’s bit 2/ XTO
Ground
5
6
VSS
P13
7
8
I/O
S
Port 1’s bit 3/ XTI
VDD
P14
9
Power 5V input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NA
Port 1’s bit 4/ MOSI
Port 1’s bit 5/ SPSCK
Port 1’s bit 6/ MISO
Port 1’s bit 7/ SPCSB
Port 3’s bit 0/ RXD/ INT3
Port 3’s bit 1/ TXD/ INT4
Port 3’s bit 2/ INT0
Port 0’s bit 0/ KBI_0
Port 0’s bit 1/ KBI_1
Port 0’s bit 2/ KBI_2
Port 0’s bit 3/ KBI_3
Port 0’s bit 6/ KBI_4
Port 0’s bit 7/ KBI_5
Port 0’s bit 6/ KBI_6
Port 0’s bit 7/ KBI_7
Port 3’s bit 3/ INT1
P15
P16
P17
P30
P31
P32
P00
P01
P02
P03
P04
P05
P06
P07
P33
P34
Port 3’s bit 4/ INT2/ CMPO/ IR_TX
Port 2’s bit 0/ IR_RX
Port 2’s bit 1/ IR_TX
P20
P21
P22
Port 2’s bit 2/ I2CSCK
Not connected
NC
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GPM8F1129/1065/1033/1019A
SSOP20:
Type: I = Input, O = Output, S = Supply
Pin Name SSOP20
Type
S
Description
VREG
ICESDA
ICESCK
VSS
VDD
P34
1
2
Regulator output
ICE data input/output
ICE clock input/ RESET
Ground
I/O
I/O
S
3
4
5
S
Power 5V input
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 3’s bit 4/ INT2/ CMPO/ IR_TX
Port 3’s bit 3/ INT1
P33
7
P30
8
Port 3’s bit 0/ RXD/ INT3
Port 3’s bit 1/ TXD/ INT4
Port 3’s bit 2/ INT0
P31
9
P32
10
11
12
13
14
15
16
17
18
19
20
P00
Port 0’s bit 0/ KBI_0
Port 0’s bit 1/ KBI_1
Port 0’s bit 2/ KBI_2
Port 0’s bit 3/ KBI_3
Port 0’s bit 6/ KBI_4
Port 0’s bit 7/ KBI_5
Port 0’s bit 6/ KBI_6
Port 0’s bit 7/ KBI_7
Port 2’s bit 0/ IR_RX
Port 2’s bit 1/ IR_TX
P01
P02
P03
P04
P05
P06
P07
P20
P21
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4.1. PIN Map
SSOP30:
NC
30
29
28
27
1
2
3
4
5
6
7
8
NC
P22/I2CSCK
P21/IR_TX
I2CSDA/P23
VREG
ICESDA
P20/IR_RX
26
25
24
23
22
21
20
19
P34/INT2/CMPO
ICESCK/RESET
XTO/P12
P33/INT1
P07/KBI7
P06/KBI6
P05/KBI5
P04/KBI4
P03/KBI3
P02/KBI2
VSS
XTI/P13
SSOP30
VDD
9
MOSI/P14
SPSCK/P15
MISO/P16
10
11
12
13
14
P01/KBI1
18
17
16
SPCSB/P17
P00/KBI0
P32/INT0
INT3/RxD/P30
INT4/TxD/P31 15
SSOP20:
1
2
20
19
18
17
16
15
14
13
12
11
P21/IR_TX
P20/IR_RX
P07/KBI7
P06/KBI6
P05/KBI5
P04/KBI4
VREG
ICESDA/P11
ICESCK/RESET
3
4
VSS
VDD
5
SSOP20
6
P34/INT2/CCP0
7
P33/INT1
P03/KBI3
P02/KBI2
P30/INT3/RxD
8
9
P31/INT4/TxD
P32/INT0
P01/KBI1
P00/KBI0
10
Note:
The pins which are not used is SSOP20 must be configured to avoid current leakage.
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5. FUNCTION DESCRIPTION
5.1. CPU
The CPU is an ultra-high performance, high speed embedded
microcontroller. Pipelined architecture enables the CPU 10 times
faster than standard architecture. This performance can also be
exploited to great advantage in low power application where the
core can be clocked over ten times slower than original
implementation for no performance penalty.
such as increment, decrement, BCD-decimal-add-adjust and
compare.
Within logic unit, operation such as AND, OR,
Exclusive OR, complement and rotation are performed. The
Boolean processor performs the bit operations as set, clear,
complement, jump-if-not-set, jump-if-set-and-clear and move
to/from carry.
The CPU is fully compatible with industry standard 8051
microcontroller, maintaining all instruction mnemonics and binary
5.1.3. Accumulator A register
compatibility.
It incorporates some great architectural
The accumulation is the 8-bit general-purpose register, which can
be operated with data transfer, temporary saving, condition
judgment, etc.
enhancements, allowing the CPU instructions execution with high
performance and high speed.
5.1.1. CPU Features
5.1.4. B Register
100 % software compatible with industry 8051
24 times faster multiplication operation
12 times faster addition operation
The B register is used during multiplying and dividing operations.
In other cases, it may be used as normal SFR.
5.1.5. Program Status Word (PSW)
The CPU is fully compatible with industry standard 8051
microcontroller, maintaining all instruction mnemonics and binary
The PSW contains several bits that reflect the current state of the
CPU which is similar to the flag-register of general CPU.
compatibility.
It incorporates some great architectural
enhancements, allowing the CPU instructions execution with high
performance and high speed.
5.1.6. Program Counter (PC)
The program counter is a 16-bit wide register. It consists of two
8-bit registers which are PCH and PCL. This register indicates
the address of next instruction to be executed. In Reset state, the
content of 0x0000 is stored into program counter.
The arithmetic section of the processor performs extensive data
manipulation and is comprised of an 8-bit arithmetic logic unit
(ALU), an ACC(0xE0) register, B(0xF0) register and PSW(0xD0)
register.
The GPM8F1129A supports both LARGE mode and FLAT mode.
The program counter is a 16-bit register in LARGE mode, but
23-bit register in FLAT mode. Switching between LARGE and
FLAT modes is performed by appropriate writing into AM bit of
ACON (0x9D) register.
5.1.2. Arithmetic Logic Unit (ALU)
The ALU performs the arithmetic and logic operations during one
instruction execution. Typical arithmetic operations are addition,
subtraction, multiplication and division. Additional operations are
ACC
Address: 0xE0
Accumulator A Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
ACC[7:0]
0
0
0
Bit
Function
Type
R/W
Description
Condition
7:0
ACC[7:0]
Accumulator A
Table 5-1 The ACC register
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B
Address: 0xF0
B Register
Bit
7
0
6
0
5
4
0
3
2
0
1
0
0
0
Function
Default
B[7:0]
0
0
Bit
Function
Type
R/W
Description
Condition
7:0
B[7:0]
B
Table 5-2 The B register
PSW
Address: 0xD0
Program Status Word Register
Bit
7
CY
0
6
AC
0
5
F0
0
4
RS1
0
3
RS0
0
2
OV
0
1
0
P
0
Function
Default
F1
0
Bit
7
Function
Type
R/W
R/W
R
Description
Condition
CY
AC
Carry flag
6
Auxiliary carry flag
Reserved
5
--
4:3
RS[1:0]
R/W
Register bank select bits
RS[1:0]
00
Function description
Bank 0, data address 0x00-0x07
Bank 1, data address 0x08-0x0F
Bank 2, data address 0x10-0x17
Bank 3, data address 0x18-0x1F
01
10
11
2
1
0
OV
--
R/W
R
Overflow flag
Reserved
Parity flag
P
R/W
Table 5-3 The PSW register
ACON
Bit
Address: 0x9D
Address Control Register
7
--
0
6
--
0
5
--
0
4
--
0
3
--
0
2
--
0
1
0
--
0
Function
Default
AM
0
Bit
7:2
1
Function
Type
R/W
R/W
Description
Reserved
Condition
--
AM
Addressing Mode
0: 16-bit Addressing Mode - LARGE
1: 23-bit Contiguous Addressing Mode - FLAT
Reserved
0
--
R/W
Table 5-4 The ACON register (GPM8F1129A only)
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5.2. Memory
5.2.1. Introduction
After each reset, CPU starts execution in the program memory at
location 0x0000 or loader zone based on the value of 0x8E in
Flash or 0xCF in SFR. The value of JMP_LZ is 0xFF in default,
and CPU will jump to loader zone after reset. Each interrupt has
its own start address for service routine. The Flash memory can
be programmed in-system, through the SCK/SDA interface or by
software using the MOVX instruction when PWE= 1. Flash data
cannot be programmed from a ‘0’ to a ‘1’, and can only be
recognized by erase operation. Therefore, flash data will typically
be erased (set to 0xFF) before being programmed. The write and
erase operations are executed using PSIDLE (Pseudo-idle) mode
to be automatically timed by hardware without data polling to
determine the end of the write and erase operation.
The GPM8F1129/1065/1033/1019A has three separated address
spaces for program memory and data memory. The program
memory is on-chip, re-programmable Flash memory and contains
up to 128/ 64/ 32/ 18K bytes spaces. The data memory is divided
into 1.5K bytes of external RAM, 256 bytes IDM SRAM with 128
bytes of SFR which can be read and written. The upper IDM and
SFR use the same access address in different access ways,
described in Figure 5-2.
5.2.2. Program Memory Allocation
The GPM8F1129/ 1065/ 1033/ 1019A implement 128/ 64/ 32/
18KB program memory size. The program memory allocation is
divided into four parts, including first page, normal page, data flash
and loader zone. The address space between 0x00000 and
0x03FF is called FIRST_PAGE. It is used for reset vector, IRQ
vectors, passwords and CONFIG_BYTE. The CONFIG_BYTE is
For software security consideration, user can set the
programmable Flash level by FL_LEVEL register to limit the code
area that avoids inadvertently erased or written by software; the
protected region is called READONLY_PAGE.
located in 0x008F of program memory.
The content of
The GPM8F1129/ 1065/ 1033/ 1019A implements three control
bytes for boot loader applications (i.e. JMP_LZ, LZ_SEL and
CONFIG_BYTE also can be read from CONFIG_BYTE register
(0xB7) of SFR. The definition of CONFIG_BYTE is shown in
Table 5-5. The address space between 0x88 and 0x8b is used
for passwords (i.e. PASSWD0~PASSWD3). If CONFIG_BYTE[0]
is programmed to be ‘0’, the whole chip memory is protected and
any page erase or program by two wire serial interface is not
allowed. The only thing user can do is to erase the entire chip.
A user can choose to allow or disallow the read operation of whole
chip memory in code lock state by setting CONFIG_BYTE[3] to “0”.
If CONFIG_BYTE[3] is set to “0” and user-entered passwords
match contents of PASSWD0~PASSWD3, the whole chip memory
can be read even in code lock state. The address space between
0x0400 and 0x01CFFF/0xCFFF/0x4FFF/0x17FF is used for user
code area. The last 12K bytes are used for data flash and loader
zone.
DF_SEL).
The JMP_LZ/LZ_SEL/DF_SEL is allocated in
The reset vector of
0x8E/0x8D/0x8C of program memory.
GPM8F1129/ 1065/ 1033/ 1019A can be changed to 0x1FC00/
0xFC00/ 0x7C00/ 0x4400 by writing #0xFF to JMP_LZ (0x8E of
program memory). The LZ_SEL is used to protect the content of
loader zone. The DF_SEL is used to protect the content of data
flash when CPU is executing loader code. CPU should execute
“JLMP 0x1FC00(GMP8F1129A)
/
0xFC00(GMP8F1065A)
/
0x7C00(GMP8F1033A) / 0x4400(GMP8F1019A)” instruction or
write #0xFF to JMP_LZ before executing loader code. The
FIRST_PAGE can be programmed or erased, when the loader
code is in progress, Table 5-8, Table 5-9 and Table 5-10 show the
definition of JMP_LZ, LZ_SEL and DF_SEL respectively.
0x00000
0x003FF
0x00400
0x0000
0x03FF
0x0400
0x0000
0x03FF
0x0400
0x0000
0x03FF
0x0400
First Page
First Page
First Page
First Page
Normal Page
Normal Page
Normal Page
Normal Page
0x1CFFF
0x1D000
0x17FF
0x1800
0xCFFF
0xD000
0x4FFF
0x5000
Data Flash+
Loader Zone
(12KBytes)
Data Flash+
Loader Zone
(12KBytes)
Data Flash+
Loader Zone
(12KBytes)
Data Flash+
Loader Zone
(12KBytes)
0x1FFFF
0xFFFF
0x7FFF
0x47FF
GPM8F1129A
GPM8F1019A
GPM8F1065A
GPM8F1033A
Figure 5-1 Program memory organization
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CONFIG_BYTE
Bit
Address: 0xB7
CONFIG_BYTE Register
7
--
1
6
--
1
5
--
1
4
--
1
3
PWENB
1
2
--
1
1
IOSEL
1
0
Function
Default
CODE_UNLOCK
1
Bit
7:4
3
Function
--
Type
R
Description
Condition
Reserved
PWENB
R/W
Password mechanism enable bit
0: Passwords mechanism enable
1: Passwords mechanism disable
Reserved
2
1
--
R
IOSEL
R/W
IO initial state selection bit
0: Input pull high
1: floating
0
CODE_UNLOCK
R/W
Program memory protection enable bits
0: CODE is locked
1: CODE is unlocked
Note: default value of CONFIG_BYTE = 0xFF
Table 5-5 CONFIG_BYTE description
FL_LEVEL
Address: 0xED
Flash Level Register
Bit
7
1
6
1
5
4
1
3
2
1
1
1
0
1
Function
Default
FLASH_LEVEL[6:0]
1
1
Bit
7
Function
--
Type
R/W
R/W
Description
Condition
Reserved
6:0
FLASH_LEVEL[6:0]
FLASH_LEVEL, it determines the number of 1K page is read
only, shown in the following table.
Note 1. Only FLASH_LEVEL[4:0] is useful in GPM8F1019A
Note 2. Only FLASH_LEVEL[4:0] is useful in GPM8F1033A
Note 3. Only FLASH_LEVEL[5:0] is useful in GPM8F1065A
Note 4. Only FLASH_LEVEL[6:0] is useful in GPM8F1129A
Table 5-6 The FL_LEVEL register
FLASH_LEVEL
0x00
Note
FLASH_LEVEL
0x40
Note
no page is read only
address < 0x10400 is read only
address < 0x10800 is read only
address < 0x10C00 is read only
address < 0x11000 is read only
address < 0x11400 is read only
address < 0x11800 is read only
address < 0x11C00 is read only
address < 0x12000 is read only
address < 0x12400 is read only
address < 0x12800 is read only
0x01
address < 0x800 is read only
address < 0xC00 is read only
address < 0x1000 is read only
address < 0x1400 is read only
address < 0x1800 is read only
address < 0x1C00 is read only
address < 0x2000 is read only
address < 0x2400 is read only
address < 0x2800 is read only
0x41
0x02
0x42
0x03
0x43
0x04
0x44
0x05
0x45
0x06
0x46
0x07
0x47
0x08
0x48
0x09
0x49
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FLASH_LEVEL
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
Note
FLASH_LEVEL
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
Note
address < 0x2C00 is read only
address < 0x3000 is read only
address < 0x3400 is read only
address < 0x3800 is read only
address < 0x3C00 is read only
address < 0x4000 is read only
address < 0x4400 is read only
address < 0x4800 is read only
address < 0x4C00 is read only
address < 0x5000 is read only
address < 0x5400 is read only
address < 0x5800 is read only
address < 0x5C00 is read only
address < 0x6000 is read only
address < 0x6400 is read only
address < 0x6800 is read only
address < 0x6C00 is read only
address < 0x7000 is read only
address < 0x7400 is read only
address < 0x7800 is read only
address < 0x7C00 is read only
address < 0x8000 is read only
address < 0x8400 is read only
address < 0x8800 is read only
address < 0x8C00 is read only
address < 0x9000 is read only
address < 0x9400 is read only
address < 0x9800 is read only
address < 0x9C00 is read only
address < 0xA000 is read only
address < 0xA400 is read only
address < 0xA800 is read only
address < 0xAC00 is read only
address < 0xB000 is read only
address < 0xB400 is read only
address < 0xB800 is read only
address < 0xBC00 is read only
address < 0xC000 is read only
address < 0xC400 is read only
address < 0xC800 is read only
address < 0xCC00 is read only
address < 0xD000 is read only
address < 0xD400 is read only
address < 0xD800 is read only
address < 0xDC00 is read only
address < 0x12C00 is read only
address < 0x13000 is read only
address < 0x13400 is read only
address < 0x13800 is read only
address < 0x13C00 is read only
address < 0x14000 is read only
address < 0x14400 is read only
address < 0x14800 is read only
address < 0x14C0 is read only
address < 0x15000 is read only
address < 0x15400 is read only
address < 0x15800 is read only
address < 0x15C00 is read only
address < 0x16000 is read only
address < 0x16400 is read only
address < 0x16800 is read only
address < 0x16C00 is read only
address < 0x17000 is read only
address < 0x17400 is read only
address < 0x17800 is read only
address < 0x17C00 is read only
address < 0x18000 is read only
address < 0x18400 is read only
address < 0x18800 is read only
address < 0x18C00 is read only
address < 0x19000 is read only
address < 0x19400 is read only
address < 0x19800 is read only
address < 0x19C00 is read only
address < 0x1A000 is read only
address < 0x1A400 is read only
address < 0x1A800 is read only
address < 0x1AC00 is read only
address < 0x1B000 is read only
address < 0x1B400 is read only
address < 0x1B800 is read only
address < 0x1BC00 is read only
address < 0x1C000 is read only
address < 0x1C400 is read only
address < 0x1C800 is read only
address < 0x1CC00 is read only
address < 0x1D000 is read only
address < 0x1D400 is read only
address < 0x1D800 is read only
address < 0x1DC00 is read only
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FLASH_LEVEL
0x37
Note
FLASH_LEVEL
0x77
Note
address < 0xE000 is read only
address < 0xE400 is read only
address < 0xE800 is read only
address < 0xEC00 is read only
address < 0xF000 is read only
address < 0xF400 is read only
address < 0xF800 is read only
address < 0xFC00 is read only
address < 0x10000 is read only
address < 0x1E000 is read only
address < 0x1E400 is read only
address < 0x1E800 is read only
address < 0x1EC00 is read only
address < 0x1F000 is read only
address < 0x1F400 is read only
address < 0x1F800 is read only
address < 0x1FC00 is read only
address < 0x20000 is read only
0x38
0x78
0x39
0x79
0x3A
0x7A
0x3B
0x7B
0x3C
0x7C
0x3D
0x7D
0x3E
0x7E
0x3F
0x7F
Table 5-7 The description of FL_LEVEL register
JMP_LZ
Address: 0x008E
(Program Memory)
5
Jump to Loader Zone Control Register
Bit
7
1
6
1
4
1
3
1
2
1
1
1
0
1
Function
Default
JMP_LZ[7:0]
1
Bit
Function
Type
Description
CPU jumps to loader zone control bits
Condition
7:0
JMP_LZ[7:0]
R/W
#0x55: After each reset, CPU starts execution in the program
memory at location 0x0000
#0xFF: After each reset, CPU starts execution in the program
memory at location 0x1FC00 (GPM8F1129A)/
0xFC00(GPM8F1065A)/
0x7C00(GPM8F1033A)/
0x4400(GPM8F1019A)
Table 5-8 The JMP_LZ register
LZ_SEL
Address: 0x008D
(Program Memory)
Loader Zone Area Control Register
Bit
7
--
1
6
--
1
5
--
1
4
--
1
3
--
1
2
1
1
0
1
Function
Default
LZ_SEL[2:0]
1
Bit
7:3
2:0
Function
--
Type
R
Description
Condition
Reserved
LZ_SEL[2:0]
R/W
Loader zone area control bits
GPM8F1129A:
000
001
No loader zone selected
The size of loader zone is 1K bytes (0x1FC00~0x1FFFF)
and it cannot be programmed by software.
010
011
The size of loader zone is 2K bytes (0x1F800~0x1FFFF)
and it cannot be programmed by software.
The size of loader zone is 3K bytes (0x1F400~0x1FFFF)
and it cannot be programmed by software.
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Bit
Function
Type
Description
Condition
100
The size of loader zone is 4K bytes (0x1F000~0x1FFFF)
and it cannot be programmed by software.
GPM8F1065A:
000
001
No loader zone selected
The size of loader zone is 1K bytes (0xFC00~0xFFFF) and
it cannot be programmed by software.
010
011
100
The size of loader zone is 2K bytes (0xF800~0xFFFF) and
it cannot be programmed by software.
The size of loader zone is 3K bytes (0xF400~0xFFFF) and
it cannot be programmed by software.
The size of loader zone is 4K bytes (0xF000~0xFFFF) and
it cannot be programmed by software.
GPM8F1033A:
000
001
No loader zone selected
The size of loader zone is 1K bytes (0x7C00~0x7FFF) and
it cannot be programmed by software.
010
011
100
The size of loader zone is 2K bytes (0x7800~0x7FFF) and
it cannot be programmed by software.
The size of loader zone is 3K bytes (0x7400~0x7FFF) and
it cannot be programmed by software.
The size of loader zone is 4K bytes (0x7000~0x7FFF) and
it cannot be programmed by software.
GPM8F1019A:
000
001
No loader zone selected
The size of loader zone is 1K bytes (0x4400~0x47FF) and
it cannot be programmed by software.
010
011
100
The size of loader zone is 2K bytes (0x4000~0x47FF) and
it cannot be programmed by software.
The size of loader zone is 3K bytes (0x3C00~0x47FF) and
it cannot be programmed by software.
The size of loader zone is 4K bytes (0x3800~0x47FF) and
it cannot be programmed by software.
Table 5-9 The LZ_SEL register
DF_SEL
Address: 0x008C
Data Flash Area Control Register
(Program Memory)
Bit
7
--
1
6
--
1
5
--
1
4
--
1
3
1
2
1
1
1
0
1
Function
DF_SEL[3:0]
Default
Bit
7:4
3:0
Function
--
Type
Description
Condition
R
Reserved
Data flash area control bits.
DF_SEL[2:0]
R/W
The data flash cannot be programmed when loader code is in progress.
GPM8F1129A:
0000
No loader zone and data flash selected
19
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Bit
Function
Type
Description
Condition
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
The size of loader zone + data flash is 1K bytes
(0x1FC00~0x1FFFF).
The size of loader zone + data flash is 2K bytes
(0x1F800~0x1FFFF).
The size of loader zone + data flash is 3K bytes
(0x1F400~0x1FFFF).
The size of loader zone + data flash is 4K bytes
(0x1F000~0x1FFFF).
The size of loader zone + data flash is 5K bytes
(0x1EC00~0x1FFFF).
The size of loader zone + data flash is 6K bytes
(0x1E800~0x1FFFF).
The size of loader zone + data flash is 7K bytes
(0x1E400~0x1FFFF).
The size of loader zone + data flash is 8K bytes
(0x1E000~0x1FFFF).
The size of loader zone + data flash is 9K bytes
(0x1DC00~0x1FFFF).
The size of loader zone + data flash is 10K bytes
(0x1D800~0x1FFFF).
The size of loader zone + data flash is 11K bytes
(0x1D400~0x1FFFF).
The size of loader zone + data flash is 12K bytes
(0x1D000~0x1FFFF).
GPM8F1065A:
0000
0001
No loader zone and data flash selected
The size of loader zone + data flash is 1K bytes
(0xFC00~0xFFFF).
0010
0011
0100
0101
0110
0111
1000
1001
1010
The size of loader zone + data flash is 2K bytes
(0xF800~0xFFFF).
The size of loader zone + data flash is 3K bytes
(0xF400~0xFFFF).
The size of loader zone + data flash is 4K bytes
(0xF000~0xFFFF).
The size of loader zone + data flash is 5K bytes
(0xEC00~0xFFFF).
The size of loader zone + data flash is 6K bytes
(0xE800~0xFFFF).
The size of loader zone + data flash is 7K bytes
(0xE400~0xFFFF).
The size of loader zone + data flash is 8K bytes
(0xE000~0xFFFF).
The size of loader zone + data flash is 9K bytes
(0xDC00~0xFFFF).
The size of loader zone + data flash is 10K bytes
(0xD800~0xFFFF).
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Bit
Function
Type
Description
Condition
1011
1100
The size of loader zone + data flash is 11K bytes
(0xD400~0xFFFF).
The size of loader zone + data flash is 12K bytes
(0xD000~0xFFFF).
GPM8F1033A:
0000
0001
No loader zone and data flash selected
The size of loader zone + data flash is 1K bytes
(0x7C00~0x7FFF).
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
The size of loader zone + data flash is 2K bytes
(0x7800~0x7FFF).
The size of loader zone + data flash is 3K bytes
(0x7400~0x7FFF).
The size of loader zone + data flash is 4K bytes
(0x7000~0x7FFF).
The size of loader zone + data flash is 5K bytes
(0x6C00~0x7FFF).
The size of loader zone + data flash is 6K bytes
(0x6800~0x7FFF).
The size of loader zone + data flash is 7K bytes
(0x6400~0x7FFF).
The size of loader zone + data flash is 8K bytes
(0x6000~0x7FFF).
The size of loader zone + data flash is 9K bytes
(0x5C00~0x7FFF).
The size of loader zone + data flash is 10K bytes
(0x5800~0x7FFF).
The size of loader zone + data flash is 11K bytes
(0x5400~0x7FFF).
The size of loader zone + data flash is 12K bytes
(0x5000~0x7FFF).
GPM8F1019A:
0000
0001
No loader zone and data flash selected
The size of loader zone + data flash is 1K bytes
(0x4400~0x47FF).
0010
0011
0100
0101
0110
0111
The size of loader zone + data flash is 2K bytes
(0x4000~0x47FF).
The size of loader zone + data flash is 3K bytes
(0x3C00~0x47FF).
The size of loader zone + data flash is 4K bytes
(0x3800~0x47FF).
The size of loader zone + data flash is 5K bytes
(0x3400~0x47FF).
The size of loader zone + data flash is 6K bytes
(0x3000~0x47FF).
The size of loader zone + data flash is 7K bytes
(0x2C00~0x47FF).
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Bit
Function
Type
Description
Condition
1000
1001
1010
1011
1100
The size of loader zone + data flash is 8K bytes
(0x2800~0x47FF).
The size of loader zone + data flash is 9K bytes
(0x2400~0x47FF).
The size of loader zone + data flash is 10K bytes
(0x2000~0x47FF).
The size of loader zone + data flash is 11K bytes
(0x1C00~0x47FF).
The size of loader zone + data flash is 12K bytes
(0x1800~0x47FF).
Table 5-10 The DF_SEL register
FLASHCON
Bit
Address: 0xB7
Flash Control Register
7
--
0
6
--
0
5
4
--
0
3
--
0
2
--
0
1
P_ERASE
0
0
PROG
0
Function
Default
--
0
Bit
7:2
1
Function
--
Type
R/W
R/W
Description
Condition
Reserved
P_ERASE
Flash page erase enable bit
0: Flash page erase is disabled
1: Flash page erase is enabled
Flash program enable bit
0
PROG
R/W
0: Flash program is disabled
1: Flash program is enabled
Table 5-11 The FLASHCON register
5.2.3. Data Memory Allocation
Data memory address allocations on the GPM8F1129/ 1065/
1033/ 1019A are divided into two parts. The first part is 1.5K
bytes of external RAM and the second one is 256 byte IDM shown
in Figure 5-2. The lowest internal data memory (IDM) consists of
four register banks with eight registers each. A bit addressable
segment with 128 bits (16 bytes) begins at 0x20. The address
from 0x30 to 0x7F is not defined and can be utilized freely by user.
The last 128 bytes of data memory can be used by different
addressing modes. With the indirect addressing mode, address
from 0x80 to 0xFF shared with stack space is addressed. With
the direct addressing mode, the SFR addressing from 0x80 to
0xFF is accessed. The SFR memory map is shown in Table
5-12.
0xFF
Upper Internal RAM
shared with Stack
SFR
Special Function
Registers
space
(indirect addressing)
(direct addressing)
0x80
0x30
RAM
1.5KB
Lower Internal RAM shared with Stack space
(direct & indirect addressing)
Bit addressable area
4 banks, R0-R7 each
0x20
0x00
XRAM: 1.5KB
IDM: (256B) and SFR
Figure 5-2 Data memory organization
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Note1: Black: standard 8051 register; gray: additional register;
0xF8
0xF0
0xE8
0xE0
EIP
B
IOSCCON
IOSCT0
IOSCT1
SPICON
SPITXD
SPIRXD
BODYID
EIE
ACC
EXIPOL
P0_SC
EXIMOD
P3_SC
KEYCODE
P0_TKEY
I2CSTS
FLASHCON
P3_TKEY
I2CADR
FL_LEVEL
TKEY_XOR
I2CDAT
0xD8 WDCON
0xD0 PSW
0xC8 T2CON
0xC0 CCL
0xB8 IP
I2CCON
I2CDEB
CCEN
T2IF
CCH
CRCL
CRCH
TL2
TH2
JMP_LZ
CMPO_INV TMBIF
MARKL
TMAIF
P0_PD
P3_PD
MARKH
PERIOD
P1_PU
SPACEL
DUTY
P1_PD
SRCON
ACON
DPX1
SPACEH
WKUEN
SYSCON0
FLASHERRF
P2_PU
RXCON
0xB0 P3
CMDTCON
KBIEN
CAPCON
CONFIG_BYTE
SYSCON1
0xA8 IE
P0_PU
P3_PU
0xA0 P2
0x98
0x90
0x88
0x80
SCON0
P1
SBUF0
EIF
P2_PD
BIF
DPX0
TL1
RSTSTS
TH0
BIP
TCON
P0
TMOD
SP
TL0
TH1
CKCON
DPS
RSTCON
PCON
DPL0
DPH0
DPL1
DPH1
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
Table 5-12 SFR memory map
5.2.4. Memory Related SFR
5.2.4.2. Data pointer registers
Dual data pointer registers are implemented to speed up data
block copy. DPTR0 and DPTR1 are located in four SFR
The following sub-sections describe program, external and internal
memories related SFRs of 8051 core and their functionality. For
other information about standard SFRs, please refer to appropriate
peripheral section.
addresses. Active DPTR register is selected by SEL bit (DPS[0]).
If SEL=0, DPTR0 is selected, else DPTR1.
5.2.4.3. Stack pointer
5.2.4.1. Program write enable bit
The 8051 has 8-bit stack pointer called SP (0x81) located in the
internal RAM space. It is incremented before data is stored
during PUSH and CALL execution and decremented after data is
popped during POP, RET and RETI execution. In the other words,
it always points to the last valid stack byte. The SP is accessed
as any other SFRs. Figure 5-3 shows an example when PUSH A
is executed and Figure 5-4 shows an example when POP PSW is
executed.
The Program Write Enable (PWE) bit, located in PCON register bit
4, is used during MOVX instructions. When PWE bit is set to
logic 1, the MOVX @DPTR, an instruction writes data located in
accumulator register into program memory addressed by DPTR
register. Program memory can only be read by MOVC regardless
of PWE bit.
SP
SP
08H
07H
23H
21H
08H
07H
38H
21H
08H
07H
ACC
23H
ACC
23H
After execution
Before execution
Figure 5-3 Stack byte order for PUSH A instruction
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SP
SP
07H
08H
65H
21H
08H
07H
65H
21H
08H
07H
PSW
65H
PSW
23H
After execution
Figure 5-4 Stack byte order for POP PSW instruction
Before execution
PCON
Bit
Address: 0x87
Power Configuration Register
7
6
SMOD1
0
5
CPU_IDLE
0
4
PWE
0
3
2
--
0
1
STOP
0
0
--
0
Function
Default
SMOD0
0
STOP_RST_EN
0
Bit
7
Function
SMOD0
Type
Description
Condition
R/W
R/W
R/W
UART0 baud rate bit when clocked by Timer1
UART0 baud rate bit when clocked by Timer1
IDLE mode enable bit
6
SMOD1
5
CPU_IDLE
0: IDLE mode disabled ;
1: IDLE mode entered
4
3
PWE
R/W
R/W
Program Write Enable (PWE)
0: Disable Flash write activity during MOVX instruction
1: Enable Flash write activity during MOVX instruction
Wakeup state selection bit
0: Next instruction state after wakeup
1: Reset state afer wakeup
Reserved
STOP_RST_EN
2
1
--
R/W
R/W
STOP
STOP mode enable bit
0: Disabled
1: Enabled
0
--
R/W
Reserved
Table 5-13 The PCON register
DPH0
Bit
Address: 0x83
Data Pointer Register - high byte
7
0
6
0
5
4
0
3
2
1
0
0
Function
Default
DPTR0[15:8]
0
0
0
0
Bit
Function
Type
Description
Condition
7:0
DPTR0[15:8]
R/W
Data pointer register DPTR0 - high byte
Table 5-14 The DPH0 register
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DPL0
Bit
Address: 0x82
Data Pointer Register - low byte
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
DPTR0[7:0]
0
0
0
Bit
Function
Type
R/W
Description
Condition
7:0
DPTR0[7:0]
Data pointer register DPTR0 - low byte
Table 5-15 The DPL0 register
DPX0
Bit
Address: 0x93
Data Pointer Extended Register
7
0
6
0
5
4
3
2
1
0
0
0
Function
Default
DPTR0[23:16] (GPM8F1129/1065A only)
0
0
0
0
Bit
Function
Type
Description
Condition
7:0
DPTR0[23:16]
R/W
Data pointer extended register
Table 5-16 The DPX0 register
DPH1
Bit
Address: 0x85
Data Pointer 1 Register - high byte
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
DPTR1[15:8]
0
0
0
Bit
Function
Type
Description
Condition
7:0
DPTR1[15:8]
R/W
Data pointer 1 register DPTR1 - high byte
Table 5-17 The DPH1 register
DPL1
Bit
Address: 0x84
Data Pointer 1 Register - low byte
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
DPTR0[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
DPTR1[7:0]
R/W
Data pointer 1 register DPTR1 - low byte
Table 5-18 The DPL1 register
DPX1
Bit
Address: 0x95
Data Pointer Extended 1 Register
7
0
6
0
5
4
3
2
1
0
0
0
Function
Default
DPTR1[23:16] (GPM8F1129/1065A only)
0
0
0
0
Bit
Function
Type
Description
Condition
7:0
DPTR1[23:16]
R/W
Data pointer extended 1 register
Table 5-19 The DPX1 register
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DPS
Address: 0x86
Data Pointer Select Register
Bit
7
ID1
0
6
ID0
0
5
TSL
0
4
-
3
-
2
-
1
-
0
SEL
0
Function
Default
0
0
0
0
Bit
Function
Type
Description
Condition
7:6
ID[1:0]
R/W
Increment/decrement function selection.
See Table 5-21
5
TSL
R/W
Toggle select enable bit
0: DPTR related instructions do not affect state of SEL bit
1: DPTR related instructions to toggle the SEL bit
Reserved
4:1
0
--
R/W
R/W
SEL
Active data pointer select bit
See Table 5-21
Table 5-20 The DPS register
ID1
ID0
SEL=0
INC DPTR0
SEL=1
0
0
1
1
0
1
0
1
INC DPTR1
INC DPTR1
DEC DPTR1
DEC DPTR1
DEC DPTR0
INC DPTR0
DEC DPTR0
Table 5-21 DPTR0/DPTR1 operations
SP
Address: 0x81
Stack Pointer Register
Bit
7
0
6
0
5
4
0
3
2
1
1
0
1
Function
Default
SP[7:0]
0
0
1
Bit
Function
Type
Description
Condition
7:0
SP[7:0]
R/W
Stack pointer
Table 5-22 The SP register
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5.3. Special Function Registers (SFR)
GPM8F1129/1065/1033/1019A has up to 94 control registers for
special function registers. All of the SFRs are used by MCU
and peripheral function block for controlling the desired
operation. Some of the SFRs contain control and status bits for
peripheral module such as Timer unit, Interrupt control unit, etc.
Some of bits in SFRs are read only, so writing to those bits will
not have any effect on corresponding bits. Some SFRs have
key code design that KEYCODE register must be written with
correct key codes, in sequence, before writing a value to it for
software security reason.
The following table shows the
summary of the SFRs. The detailed information of each SFRs
are explained in each peripheral section.
Key Reset
Addr
Function
7
6
5
4
3
2
1
0
Code Value
0x80
0x81
0x82
0x83
0x84
0x85
0x86
P0
0xFF
0x07
0x00
0x00
0x00
0x00
0x00
Port 0
Stack Pointer
SP
DPL0
DPH0
DPL1
DPH1
DPS
Data pointer register DPTR0 — low byte
Data pointer register DPTR0 — high byte
Data pointer register DPTR1 — low byte
Data pointer register DPTR1 — high byte
ID1
ID0
TSL
CPU_
IDLE
TF0
--
--
STOP_RST
_EN
--
--
SEL
--
0x87
PCON
0x00
SMOD0
SMOD1
PWE
--
STOP
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
TCON
TMOD
TL0
0x00
0x00
0x00
0x00
0x00
0x00
0x01
TF1
--
TR1
--
TR0
M10
IE1
--
--
IE0
--
M11
--
M01
M00
Timer 0 Load value – low byte
Timer 1 Load value – low byte
TL1
TH0
Timer 0 Load value – high byte
Timer 1 Load value – high byte
TH1
CKCON
WD1
DF_EP_
ENB
WD0
LZ_EP_
ENB
P16
WDFM
T1M
T0M
--
CHIP_E_
ENB
--
--
MISS_CLK_ FLASH_ERR
FLASH_FLOW
0x8F
RSTCON
0x10
4F,72,7A
XADDR_ENB FP_EP_ENB
ENB
--
_ ENB
--
_ ENB
P15
--
0x90
0x91
0x93
P1
EIF
0xff
P17
P14
--
P13
P12
0x00
0x00
KBIF
--
LVDF
INT4F
INT3F
INT2F
DPX0
Data pointer extended register(GPM8F1129/1065A only)
MISS_CLK
_RST
STOP_
RST
FLASH_
0x94
RSTSTS
0x00
--
S/W_RST WDT_RST LVR_RST RAD_RST
ERR_RST
0x95
0x96
0x97
0x98
0x99
0x9D
0x9E
0x9F
0xA0
0xA2
0xA3
0xA5
DPX1
BIP
0x00
0x00
0x00
0x00
0x00
Data pointer extended 1 register(GPM8F1129/1065A only)
--
--
--
--
--
--
--
--
--
--
PTMB
TMBIF
RB08
PTMA
TMAIF
TI0
PI2C
--
BIF
SCON0
SBUF0
ACON
P2_PU
P2_PD
P2
SM00
SM01
SM02
REN0
TB08
RI0
UART 0 buffer
AA,55 0x00
0x00
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
AM
--
--
--
P23_PU
P23_PD
P223
P22_PU
P22_PD
P22
P21_PU
P21_PD
P21
P20_PU
P20_PD
P20
0x00
--
--
--
0xFF
--
P3_PU
P3_PD
SRCON
0x00
--
--
P34_PU
P34_PD
--
P33_PU
P33_PD
P3_SR
P32_PU
P32_PD
P2_SR
P31_PU
P31_PD
P1_SR
P30_PU
P30_PD
P0_SR
0x00
0x0F
--
FLASH_
FLOW_F
0xA6
FLASHERRF
0x00 DF_EP_ F LZ_EP_ F
XADDR_F FP_EP_F CHIP_E_F
--
--
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Key Reset
Code Value
Addr
Function
7
6
5
4
3
2
1
0
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
IE
0x00
0x00
EA
ECCP
ET2
ES0
ET1
EX1
ET0
EX0
KBIEN
KBIEN[7:0]
P0_PU
P0_PD
P1_PU
P1_PD
SYSCON0
0x00
P07_PU
P07_PD
P06_PU
P06_PD
P16_PU
P16_PD
P05_PU
P05_PD
P15_PU
P15_PD
P04_PU
P04_PD
P14_PU
P14_PD
P03_PU
P03_PD
P13_PU
P13_PD
P02_PU
P02_PD
P12_PU
P12_PD
P01_PU
P00_PU
0x00
P01_PD
P00_PD
0x00
P17_PU
--
--
--
--
--
--
0x00
P17_PD
FF,00 0x00
LVDENB LVDSEL1 LVDSEL0 LVRENB
LVD_STATUS
CLKOUT_EN
I2C_AUT
O_RW
SYSCON1
0x00
--
--
--
ADorDA
SPI_EN
I2CEN
IRTX_SW
--
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0XB6
P3
0xFF
--
--
P34
P33
P32
P31
P30
CMDTCON
CAPCON
TMAIF
0x00 IRTX_EN TX_STATE ENVDET
EXSPC
TMBEN
TMAEN
POLARITY
PWM_MODE
0x00
0x00
CAPB_EN
--
TMB_DIV[1:0]
TMA_DIV[1:0]
CAPB_MODE
RXOUT_INV CAPA_MODE
--
--
CAPAIF
PERIOD[7:0]
DUTY[7:0]
TMAOIF
FALLIF
RISEIF
TMAIE
PERIOD
DUTY
0x00
0x00
WKUEN
AF,50 0x9F
0xFF
--
--
KB_WKUEN
WD_WKUEN
INT4_WKUEN INT3_WKUEN INT2_WKUEN INT1_WKUEN INT0_WKUEN
0xB7 CONFIG_BYTE
--
--
--
PS0
PWENB
PT1
--
PX1
IOSEL
PT0
CODE_UNLOCK
PX0
0xB8
0xB9
0xBA
0xBB
0xBC
0xBD
0xBE
0XBF
0xC0
0xC1
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
0xD8
0xDA
0xDB
0xDC
0xDD
0xDE
0xE0
0xE1
0xE2
IP
CMPO_INV
TMBIF
MARKL
MARKH
SPACEL
SPACEH
RXCON
CCL
0x00
--
--
--
--
PT2
--
0x00
--
--
--
--
CC_INVEN
TMBIE
0x00
ENVDETIF
MASK_oe
FCAPBIF
RCAPBIF
TMBOIF
SPACEIF
MARKIF
0x00
MARK[7:0]
0x00
MARK[15:8]
SPACE[7:0]
SPACE[15:8]
0x00
0x00
0x00
--
RXOUT
FILTER_SEL[1:0]
--
--
--
--
0x00
Timer2cc capture low byte
Timer2cc capture high byte
CCH
0x00
T2CON
T2IF
0x00
T2PS
--
I3FR
--
--
--
T2R
CCF
--
--
T2CM
--
--
--
T2I
0x00
TF2
CRCL
0x00
CRC register – Low byte
CRC register – High Byte
CRCH
TL2
0x00
0x00
Timer 2 Load value – low byte
Timer 2 Load value – high byte
TH2
0x00
CCEN
0x01
--
--
--
--
JMP_LZ[7:0]
RS1 RS0
--
--
CM
--
JMP_LZ
PSW
0xFF
0x00
CY
--
AC
--
--
OV
--
--
P
WDCON
I2CCON
I2CSTS
I2CADR
I2CDAT
I2CDEB
ACC
AA,55 0x00
0x00
--
--
WDIF
EWT
RWT
ACKEN
CLKSEL
I2CIE
BUSY
I2CIF
TXCLK[3:0]
0x00
MODE[1:0]
DataEN
Addr[7:1]
ArbS
SS
GC
ACK
0x00
--
0x00
Data[7:0]
0x00
DEBCLK[7:0]
ACC register
P0_SC[7:0]
0x00
P0_SC
P3_SC
0x00
0x00
--
--
--
P3_SC[4:0]
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Key Reset
Code Value
Addr
Function
7
6
5
4
3
2
1
0
0xE3
0xE4
0xE5
0xE8
0xE9
0xEA
0xEB
0xEC
0xED
0xF0
0xF8
P0_TKEY
P3_TKEY
TKEY_XOR
EIE
P0_TKEY[7:0]
--
--
--
--
--
--
--
--
--
P3_TKEY[4:0]
--
--
--
--
TKEY_XOR
0x00
0x00
0x00
0x00
0x00
0xFF
0x00
0x00
EKBI
--
EWDI
--
ELVD
EINT4
EINT3
EINT2
EXIPOL
EXIMOD
KEYCODE
FLASHCON
FL_LEVEL
B
INT4POL INT3POL INT2POL INT1POL INT0POL
INT4MOD INT3MOD INT2MOD INT1MOD INT0MOD
KEYCODE[7:0]
--
--
--
--
--
--
--
--
--
P_ERASE
PROG
FLASH_LEVEL[6:0]
B register
EIP
PKBI
--
--
--
PWDI
XTAL_PAD
_EN
--
--
--
PLVD
OSC_SEL
--
PINT4
PINT3
PINT2
0xF9
IOSCCON
0x00
0x00
--
CLKDIV[1:0]
XFCN[1:0]
0xFA
0xFB
0xFC
0xFD
0xFE
0xFF
IOSCT0
IOSCT1
SPICON
SPITXD
SPIRXD
BODYID
--
--
--
--
--
OSC_TRIM[6:0]
--
0x00
0x00
0x00
PHASE
SPI_CLK_SEL[1:0]
SPI TX Data[7:0]
SPI RX Data[7:0]
SPI_RD
PO_LARITY
CSB_KEEP
SPI_START
5.4. Power Saving Mode
5.4.1. Introduction
SYSCLK, resulting in a fully static condition. No processing is
possible, timers are stopped, and no serial communication is
Although GPM8F1129/1065/1033/1019A is
a
high-speed
executed.
Processor operation will be postponed on the
microcontrollers designed for maximum performance, it also
provide Power Management Unit (PMU) with two advanced
power conservation modes. These modes are IDLE mode, and
STOP mode. In order to reduce the current consumption when
system does not need to be active, STOP mode can be utilized.
For more information about these two modes, please see the
following two sections.
instruction that sets the STOP bit. STOP mode can be exited in
the following ways:
A
non-clocked interrupt such as the external interrupts
INT0-INT4 and keyboard/key-scan IO can be used. Except for
watchdog timer, other clocked interrupts such as internal timers,
and serial ports do not operate in STOP mode. Processor
operation will resume with the fetching of the interrupt vector
associated with the interrupt that causes the exit from STOP
mode. When the interrupt service routine is completed, RETI
returns the program to the instruction immediately following the
one that invoked the STOP mode. When INT0-INT4 and
keyboard/key-scan IO are used for wakeup source, WKUEN
register must be set which tabled in Table 5-25. There are two
selections of the place of instruction execution after wakeup
when entering STOP mode and the control bit is in PCON[3]. If
STOP_RST_EN is set to ‘1’, reset state will take place after
wakeup, otherwise, next instruction will be executed.
5.4.2. IDLE mode
The IDLE mode reduces power consumption by turning off the
clock provided to the microcontroller, causing MCU to stop to
execute following instruction. IDLE mode is entered by setting
the CPU_IDLE bit (PCON[5]). In this mode, peripheral clock is
not turned off, so peripheral device can still work normally.
5.4.3. STOP mode
STOP mode is the lowest power states that the microcontroller
can enter. It is achieved by cutting-off frequency provided to
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System Clock
Peripheral clock
Wakeup source
After wakeup
RUN Mode
IDLE Mode
Register setting Register setting
--
--
OFF
OFF
ON
1. All wakeup sources
2. All interrupt sources
1. All wakeup sources
Next instruction state
STOP Mode
OFF
Reset state or next instruction state base on PCON[3]
Table 5-23 Three operation modes for GPM8F1129/1065/1033/1019A
PCON
Bit
Address: 0x87
Power Configuration Register
7
6
SMOD1
0
5
CPU_IDLE
0
4
PWE
0
3
2
--
0
1
STOP
0
0
--
0
Function
Default
SMOD0
0
STOP_RST_EN
0
Bit
7
Function
SMOD0
Type
Description
Condition
R/W
R/W
R/W
UART0 baud rate bit when clocked by Timer1
UART0 baud rate bit when clocked by Timer1
IDLE mode enable bit
6
SMOD1
5
CPU_IDLE
0: IDLE mode disabled ;
1: IDLE mode entered
4
3
PWE
R/W
R/W
Program Write Enable (PWE)
0: Disable Flash write activity during MOVX instruction
1: Enable Flash write activity during MOVX instruction
Wakeup state selection bit
0: Next instruction state after wakeup
1: Reset state afer wakeup
Reserved
STOP_RST_EN
2
1
--
R/W
R/W
STOP
STOP mode enable bit
0: Disabled
1: Enabled
0
--
R/W
Reserved
Table 5-24 The PCON register
WKUEN
Bit
Address: 0xB6
Wake Up Enable Register
7
6
5
4
3
2
1
0
Function
Default
Key Code
KB_WKUEN WD_WKUEN
--
0
INT4_WKUEN INT3_WKUEN INT2_WKUEN INT1_WKUEN INT0_WKUEN
1
0
1
1
1
1
1
0xAF, 0x50
Bit
7
Function
KB_WKUEN
WD_WKUEN
--
Type
Description
Condition
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Keyboard / key-scan pin wake up enable control
Watchdog wakeup enable control
6
5
Reserved
4
INT4_WKUEN
INT3_WKUEN
INT2_WKUEN
INT1_WKUEN
INT0_WKUEN
INT4 PAD wakeup enable control, active high
INT3 PAD wakeup enable control, active high
INT2 PAD wakeup enable control, active high
INT1 PAD wakeup enable control, active high
INT0 PAD wakeup enable control, active high
3
2
1
0
Table 5-25 The WKUEN register
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GPM8F1129/1065/1033/1019A
5.5. Interrupt System
The GPM8F1129/1065/1033/1019A provides up to five external
interrupt sources, nine internal interrupt sources and eight
keyboard change interrupt sources. Each external interrupt pin
can be set enable/disable, edge/level and polarity trigger and
individually. The keyboard change interrupt is activated at any
transition on keyboard inputs which user selects in KBIEN (0xA9).
User should read P0 for latching P0 status before setting EKBI bit
of EIE(0xE8). GPM8F1129/1065/1033/1019A also equips two
levels of interrupt priority control. Interrupt requests are sampled
each system clock at the rising edge of clock control. Each
interrupt vector can be individually enabled or disabled by setting
or clearing a corresponding bit in the special function registers
(SFRs). The IE contains global interrupt system disable(0) /
enable(1) bit called EA. In general, once an interrupt event
occurs, the corresponding flag bit will be set. The related
registers of interrupt flag are described as below.
If the related interrupt control bit is set to enable interrupt, an
interrupt request signal will be generated and then CPU executes
service routine. If the related interrupt control bit is disabled,
programmer can still observe the corresponding flag bit, but no
interrupt request signal will be generated. The interrupt flag bits
must be cleared in the interrupt service routine to prevent program
from deadlock in interrupt service routine. With any instruction,
interrupts pending during the previous instruction is served.
Before entering interrupt service routine, the system saves the
current PC address into top of stack pointer and jumps to
corresponding vector to execute the interrupt service. After
finishing the interrupt service, the system abstract the return PC
address from the top of the stack to execute the following
instruction. For more details, please refer to related block.
Interrupt flag
IE0
Function
Active level/edge
Falling/Rising/Low/High Hardware
Hardware
Falling/Rising/Low/High Hardware
Flag resets
Vector
0x03
0x0B
0x13
0x1B
0x23
0x2B
0x33
0x3B
0x43
Vector number
Priority
Device pin INT 0
Internal Timer 0
Device pin INT 1
Internal Timer 1
Internal UART0
Internal Timer A
Internal Timer B
Internal Timer 2
Keyboard pin
0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
TF0
-
IE1
TF1
-
-
-
-
-
-
Hardware
TI0 & RI0
TMAOIF
TMBOIF
T2IF
Software(cleared by 0)
Software(cleared by 0)
Software(cleared by 0)
Software(cleared by 0)
Software(cleared by 0)
Software(cleared by 0)
KBIF
Key-scan pin
INT2F
I2CIF
LVDF
INT3F
INT4F
WDIF
Device pin INT 2
Internal I2C
Falling/Rising/Low/High Software(cleared by 0)
0x4B
0x53
0x5B
0x63
0x6B
0x73
9
10
11
12
13
14
15
-
-
Software(cleared by 0)
Software(cleared by 0)
10
11
12
13
14
Low Voltage Detection
Device pin INT 3
Device pin INT 4
Internal Watchdog
Falling/Rising/Low/High Software(cleared by 0)
Falling/Rising/Low/High Software(cleared by 0)
-
Software(cleared by 0)
IP
Address: 0xB8
Interrupt Priority Register
Bit
7
--
0
6
--
0
5
PT2
0
4
PS0
0
3
PT1
0
2
PX1
0
1
PT0
0
0
PX0
0
Function
Default
Bit
7:6
5
Function
--
Type
R/W
R/W
R/W
R/W
R/W
Description
Condition
Reserved
PT2
Timer 2 priority level control (1: high level)
UART0 priority level control (1: high level)
Timer 1 priority level control (1: high level)
INT1 priority level control (1: high level)
4
PS0
PT1
3
2
PX1
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Bit
1
Function
PT0
Type
R/W
R/W
Description
Condition
Timer 0 priority level control (1: high level)
INT0 priority level control (1: high level)
Table 5-26 IP register
0
PX0
EIP
Address: 0xF8
Extended Interrupt Priority Register
Bit
7
PKBI
0
6
--
0
5
PWDI
0
4
--
0
3
PLVD
0
2
PINT4
0
1
PINT3
0
0
PINT2
0
Function
Default
Bit
7
Function
PKBI
--
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Condition
Keyboard interrupt level control (1: high level)
Reserved
6
5
PWDI
--
Watchdog priority level control (1: high level)
Reserved
4
3
PLVD
PINT4
PINT3
PINT2
LVD priority level control (1: high level)
INT4 priority level control (1: high level)
INT3 priority level control (1: high level)
INT2 priority level control (1: high level)
Table 5-27 EIP register
2
1
0
BIP
Address: 0x96
Additional Interrupt Priority Register
Bit
7
--
0
6
5
--
0
4
--
0
3
--
0
2
PTMB
0
1
PTMA
0
0
PI2C
0
Function
Default
--
0
Bit
7:3
2
Function
--
Type
R/W
R/W
R/W
R/W
Description
Condition
Reserved
PTMB
PTMA
PI2C
Timer B priority level control (1: high level)
Timer A priority level control (1: high level)
IC2 priority level control (1: high level)
Table 5-28 BIP register
1
0
IE
Address: 0xA8
Interrupt Enable Register
Bit
7
EA
0
6
ECCP
0
5
ET2
0
4
ES0
0
3
ET1
0
2
EX1
0
1
ET0
0
0
EX0
0
Function
Default
Bit
7
Function
EA
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Condition
Enable global interrupts
6
ECCP
ET2
Enable Timer2 compare/capture interrupts
Enable Timer2 interrupt
5
4
ES0
Enable UART0 interrupt
3
ET1
Enable Timer 1 interrupt
2
EX1
Enable INT1 interrupt
1
ET0
Enable Timer 0 interrupt
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Bit
Function
Type
Description
Enable INT0 interrupt
Table 5-29 IE register
Condition
0
EX0
R/W
EIE
Address: 0xE8
Extended Interrupt Enable Register
Bit
7
EKBI
0
6
-
5
4
3
ELVD
0
2
EINT4
0
1
EINT3
0
0
EINT2
0
Function
Default
EWDI
--
0
0
0
Bit
7
Function
EKBI
--
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Condition
Enable keyboard/key-scan pin interrupt
Reserved
6
5
EWDI
--
Enable watchdog interrupt
Reserved
4
3
ELVD
EINT4
EINT3
EINT2
Enable LVD interrupts
Enable INT4 interrupts
Enable INT3 interrupts
Enable INT2 interrupts
Table 5-30 EIE register
2
1
0
TCON
Bit
Address: 0x88
Timer0/1 Configuration Register
7
TF1
0
6
TR1
0
5
TF0
0
4
TR0
0
3
IE1
0
2
--
0
1
IE0
0
0
--
0
Function
Default
Bit
7
Function
TF1
Type
R/W
R/W
Description
Condition
Timer 1 interrupt (overflow) flag
Timer 1 run control bit
6
TR1
0: disabled ;
1: enabled
5
4
TF0
TR0
R/W
R/W
Timer 0 interrupt (overflow) flag
Timer 0 run control bit
0: disabled ;
1: enabled
3
2
1
0
IE1
--
R/W
R/W
R/W
R/W
INT1 interrupt flag
Reserved
IE0
--
INT0 interrupt flag
Reserved
Table 5-31 TCON register
TMAIF
Bit
Address: 0xB3
Timer A Interrupt Flag Register
7
--
0
6
5
--
0
4
CAPAIF
0
3
TMAOIF
0
2
FALLIF
0
1
RISEIF
0
0
TMAIE
0
Function
Default
--
0
Bit
Function
Type Description
Condition
7:5
4
--
R/W Reserved
CAPAIF
R/W Timer A capture flag
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Bit
Function
Type Description
Condition
3
2
1
0
TMAOIF
FALLIF
RISEIF
TMAIE
R/W Timer A overflow flag
R/W Falling edge flag of carrier output
R/W Rising edge flag of carrier output
R/W Timer A interrupt enable bit
Table 5-32 TMAIF register
TMBIF
Bit
Address: 0xBA
Timer B Interrupt Flag Register
7
6
MASK_oe
0
5
FCAPBIF
0
4
RCAPBIF
0
3
TMBOIF
0
2
SPACEIF
0
1
MARKIF
0
0
TMBIE
0
Function
Default
ENVDETIF
0
Bit
Function
Type Description
Condition
7
6
ENVDETIF
MASK_oe
R/W ENVDET rising and falling flag
R/W Timer B capture flag masking enable bit
0: RCAPBIF, FCAPBIF is not masked
1: RCAPBIF, FCAPBIF is masked
R/W Timer B falling capture flag
R/W Timer B rising capture flag
R/W Timer B overflow flag
5
4
3
2
1
0
FCAPBIF
RCAPBIF
TMBOIF
SPACEIF
MARKIF
TMBIE
R/W Space flag when count of timer B is matched to space register
R/W Mark flag when count of timer B is matched to mark register
R/W Timer B interrupt enable bit
Table 5-33 TMBIF register
EIF
Address: 0x91
Extended Interrupt Flag
Bit
7
KBIF
0
6
--
0
5
--
0
4
--
0
3
LVDF
0
2
INT4F
0
1
INT3F
0
0
INT2F
0
Function
Default
Bit
7
Function
KBIF
Type
Description
Condition
R/W
R/W
R/W
R/W
R/W
R/W
Keyboard pin (P00~P07) change/ key-scan pin interrupt flag
6:4
3
--
Reserved
LVDF
INT4F
INT3F
INT2F
LVD interrupt flag
INT4 interrupt flag
INT3 interrupt flag
INT2 interrupt flag
Table 5-34 EIF register
2
1
0
BIF
Address: 0x97
Additional interrupt flag
Bit
7
--
0
6
--
0
5
--
0
4
--
0
3
--
0
2
TMBIF
0
1
TMAIF
0
0
--
0
Function
Default
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Bit
7:3
2
Function
--
Type
R/W
R
Description
Condition
Reserved
TMBIF
TMAIF
--
Timer B interrupt flag, cleared by 0 in TMBIF register
Timer A interrupt flag, cleared by 0 in TMAIF register
Reserved
1
R
0
R/W
Table 5-35 BIF register
EXIPOL
Bit
Address: 0xE9
External Interrupt Polarity Control Register
7
--
0
6
--
0
5
4
INT4POL
0
3
INT3POL
0
2
INT2POL
0
1
INT1POL
0
0
INT0POL
0
Function
Default
--
0
Bit
7:5
4
Function
--
Type
R/W
R/W
Description
Condition
Reserved
INT4 polarity select
INT4POL
0: Falling edges/ low level
1: Rising edges/ high level
INT3 polarity select
3
2
1
0
INT3POL
INT2POL
INT1POL
INT0POL
R/W
R/W
R/W
R/W
0: Falling edges/ low level
1: Rising edges/ high level
INT2 polarity select
0: Falling edges/ low level
1: Rising edges/ high level
INT1 polarity select
0: Falling edges/ low level
1: Rising edges/ high level
INT0 polarity select
0: Falling edges/ low level
1: Rising edges/ high level
Table 5-36 EXIPOL register
EXIMODE
Bit
Address: 0xEA
External Interrupt Mode Control Register
7
--
0
6
--
0
5
4
INT4MOD
0
3
INT3MOD
0
2
INT2MOD
0
1
INT1MOD
0
0
INT0MOD
0
Function
Default
--
0
Bit
7:5
4
Function
--
Type
R/W
R/W
Description
Condition
Reserved
INT4 detection mode
INT4MOD
0: Edge-only detection.
1: Edge-and-level detection.
INT3 detection mode
3
2
INT3MOD
INT2MOD
R/W
R/W
0: Edge-only detection.
1: Edge-and-level detection.
INT2 detection mode
0: Edge-only detection.
1: Edge-and-level detection.
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Bit
Function
Type
Description
Condition
INT1 detection mode
1
INT1MOD
R/W
0: Edge-only detection.
1: Edge-and-level detection.
INT0 detection mode
0
INT0MOD
R/W
0: Edge-only detection.
1: Edge-and-level detection.
Table 5-37 EXIMOD register
WDCON
Bit
Address: 0xD8
Watchdog Control Register
7
--
0
6
--
0
5
4
--
0
3
WDIF
0
2
--
0
1
EWT
0
0
RWT
0
Function
Default
--
0
Bit
7:4
3
Function
--
Type
R/W
R/W
R/W
R/W
Description
Condition
Reserved
WDIF
--
Watchdog interrupt flag
Reserved
2
1
EWT
Watchdog timer reset enable bit
0: Disable;
Reset watchdog timer
0: NA; 1: Reset
Table 5-38 WDCON register
1: Enable
0
RWT
R/W
SCON0
Bit
Address: 0x98
UART0 Configuration Register
7
SM00
0
6
SM01
0
5
SM02
0
4
REN0
0
3
TB08
0
2
RB08
0
1
TI0
0
0
RI0
0
Function
Default
Bit
7:6
5
Function
SM0[1:0]
SM02
Type
Description
Mode and baud rate setting
Condition
R/W
R/W
R/W
R/W
R/W
Enables a multiprocessor communication feature
Enable serial reception.
4
REN0
3
TB08
The 9th transmitted data bit in Modes 2 and Mode 3
In Mode 0 this bit is not used
2
RB08
In Mode 1, if SM02 is 0, RB08 is the stop bit.
In Mode 2 and Mode 3, it is the 9th data bit received
UART0 transmitter interrupt flag
1
0
TI0
RI0
R/W
R/W
UART0 receiver interrupt flag
Table 5-39 SCON0 register
KBIEN
Bit
Address: 0xA9
Keyboard Pin Enable Register
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
KBIEN[7:0]
0
0
0
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Bit
Function
Type
Description
Condition
7:0
KBIEN[7:0]
R/W
Keyboard pin enable
0: Set KBIx function disable,
1: Set KBIx function enable
Table 5-40 KBIEN register
I2CCON
Address: 0xDA
I2C Control Register
Bit
7
ACKEN
0
6
CLKSEL
0
5
4
I2CIF
0
3
2
0
1
0
0
0
Function
I2CIE
0
TXCLK[3:0]
Default
0
Bit
Function
Type Description
Condition
I2C-bus acknowledgement enable bit
0: Disable ACK generation
7
ACKEN
CLKSEL
I2CIE
R/W
R/W
R/W
R/W
1: Enable ACK generation
Source clock of I2C-bus transmit clock pre-scaler (scaling unit) selection bit
0: I2CCLK=SYSCLK/16"
6
5
4
1: I2CCLK= SYSCLK /512"
I2C Bus TX/RX Interrupt Enable
0: Disable
1: Enable
I2C Bus TX/RX Interrupt Flag
I2CIF
Clear by the software
A I2C bus interrupt occurs
1. When a 1-byte transmitting or receiving operation is terminated.
2. When a general call or slave address match occurs.
3. If bus arbitration fails.
I2C-Bus transmit clock pre-scaler.
Transmit clock frequency is determined by this 4-bit pre-scaler value,
according to the following formula:
TX clock = I2CCLK/(TXCLK[7:4]+1)
NOTES:
3:0
TXCLK[3:0]
R/W
1. I2CCLK is determined by CLKSEL
Table 5-41 I2CCON register
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GPM8F1129/1065/1033/1019A
5.6. Reset Source
5.6.1. Introduction
There are eight types of reset sources for the
GPM8F1129/1065/1033/1019A: Power-On Reset (POR), Low
Voltage Reset (LVR), Pad Reset (RAD_RST), Watchdog Timer
Reset (WDT_RST), Software Reset (S/W_RST), STOP mode
Reset (STOP_RST), Flash Error Reset (FLASH_ERR_RST), and
missing system clock Reset (MISS_CLK_RST).
shows the block diagram of each reset source.
Figure 5-5
LVR_POR
Macro
RESET_pad
PAD_RST
LVR
RST filter
POR
rst
WDT_RST
S/W_RST
8051
STOP_RST
FLASH_ERR_RST
clkrun
Missing Clock
Detect
MISS_CLK_RST
RESET
module
SYSRESET
Figure 5-5 Reset sources
5.6.2. Power-On Reset (POR)
5.6.4. Low Voltage Detection (LVD)
A POR is generated when VDD is rising from 0v. When VDD
rises to an acceptable level (~1.5V), the power on reset circuit
will start a power-on sequence. After that, the system starts to
activate and will operate in target speed. The POR will reset
whole chip and registers.
In order to allow software to notify early that a power failure is
about to occur, the LVD flag bit can be monitored. Built-in
voltage detection circuit controls the LVD flag. The LVD flag is
set while VDD supply is below LVD voltage and is cleared when
the VDD supply is over LVD voltage. The LVD voltage can be
2.3V, 2.5V, 3.3V or 3.5V by setting LVDSEL[1:0] bits.
5.6.3. Low Voltage Reset (LVR)
5.6.5. Pad Reset (PAD_RST)
The on-chip Low Voltage Reset (LVR) circuitry forces the system
entering reset state when power supplying voltage falls below
the specific LVR trigger voltage. This function prevents MCU
from working at an invalid operating voltage range. To enable
or disable this function, the related enable bit can be set. If this
function is enabled, the LVR circuit will monitor power level while
chip is operating. And the LVR voltage level is 1.9V. If the
power is lower than the specific level for a certain period of time,
the system reset will take place and go to initial state.
The GPM8F1129/1065/1033/1019A provides an external pin to
force the system returning to its initial status. The RESET pin is
high active as shown in Figure 5-6. When the RESET pin
equals to VDD for over 1ms, system will be forced to enter reset
state, execute instruction from address 0x0000 or loader zone
based on the value of 0x8E in Flash or 0xCF in SFR and all
registers go to default state.
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GPM8F1129/1065/1033/1019A
VDD
External Internal
30pF
RESET pin
Figure 5-6 Pad reset circuit
5.6.6. Watchdog Timer Reset (WDT_RST)
On-chip watchdog circuitry makes the device entering reset state
when MCU goes into unknown state and has no watchdog cleared
information. This function prevents the MCU to be stuck in an
abnormal condition. The WDT can be enabled or disabled
through WDCON register bit 1. At any time prior to reaching its
user selected terminal value, software can set the Reset Watchdog
Timer (WDCON[0]) bit. If RWT is set before the timeout is
reached, the timer will start over. If timeout is reached without
RWT being set, the watchdog will reset the CPU. Hardware will
automatically clear RWT after software sets it. When the reset
occurs, the Watchdog Timer Reset Flag (RSTSTS[2]) will
automatically be set to indicate the cause of the reset, however
software must clear this bit manually.
accidental writes.
KEYCODE register is located at 0xEB.
Correct sequence, 0xAA and 0x55, is required before write to
WDCON register. Reading from such register is not protected.
The Watchdog has four timeout selections based on the internal
16K clock frequency. Therefore, the actual timeout interval is
dependent on the SYSCLK frequency. The selections are a
pre-selected number of clocks and can be set by CKCON[7:6]. In
addition, CKCON[5] can be used to set these four timeout
selections in fast mode or not, which is implemented in
GPM8F1129/1065A only. When CPU wakeups from ILDE mode
or STOP mode, software needs to delay about 100us to enter
ILDE mode or STOP mode again due to 1T of 16KHz clock source.
Figure 5-7 shows the block diagram of Watchdog timer.
WDCON register is a key code design register that prevent it from
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32ms
2ms
128ms
4ms
2048ms
16ms
512ms
8ms
29
25
22
2
22
2
22
2
IOSC_16K
CKCON(0x8E)
1
0
1
0
1
0
0
1
EIE (0xE8)
WDT Clear
RSTSTS (0x94)
WDCON (0xD8)
512 CLK delay
WDT RST
WDT Interrupt
Figure 5-7 The block diagram of Watchdog timer
5.6.7. Other Reset Sources
Other reset sources include Software Reset (S/W_RST), STOP
mode Reset (STOP_RST), Flash Error Reset (FLASH_ERR_RST),
and missing system clock Reset (MISS_CLK_RST). Software
Reset triggers when writing KEY code to KEYCODE register.
The key codes are 0x3c and 0xc3. The timing does not matter,
but the key codes must be written in order before SW reset takes
place. STOP mode Reset is enabled by setting PCON[3] bit.
This is the reset when system is reset from STOP mode. Flash
Error Reset is the reset when six flash related errors arise. The
first error is to execute whole chip erase by software. The second
error is to erase/program first page. The third error is access the
wrong address. The forth error occurs when flash is programmed
in a wrong way. The fifth error is erase/program pure loader zone
and the sixth error is to erase/program data flash or loader zone.
Each flash error related reset source can be enabled or disabled
by clearing or setting a bit in the RSTCON(0x94) as shown in
Table 5-47. The corresponding flag when flash error reset occurs
can be observed in FLASHERRF register which is shown in Table
5-48. Missing system clock Reset is the reset when system clock
is missed over 4095 IOSC clocks if external crystal is utilized as
clock source. There are seven reset status flag can be monitored
by RSTSTS register which is shown as Table 5-49.
SYSCON0
Bit
Address: 0xAE
SYSTEM control0 Register
7
LVD_STATUS
0
6
LVDENB
0
5
LVDSEL1
0
4
LVDSEL0
0
3
LVRENB
0
2
1
--
0
0
--
0
Function
Default
Key Code
CLKOUT_EN
0
FF,00
Bit
7
Function
LVD_STATUS
LVDENB
Type
Description
Condition
R
LVD status
6
R/W
LVD enable control
0: enable LVD function
1: disable LVD function
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Bit
Function
Type
Description
Condition
5:4
LVDSEL[1:0]
R/W
LVD voltage selection bits
00: 2.3V
01: 2.5V
10: 3.3V
11: 3.5V
3
LVRENB
R/W
LVR enable control
0: enable LVR function
1: disable LVR function
Clock output enable bit (SYSCLK is output on P34)
Reserved
2
CLKOUT_EN
--
R/W
R/W
1:0
Table 5-42 SYSCON0 register
WDCON
Bit
Address: 0xD8
Watchdog Control Register
7
--
0
6
--
0
5
--
0
4
--
0
3
WDIF
0
2
--
0
1
EWT
0
0
RWT
0
Function
Default
Bit
7:4
3
Function
--
Type
R/W
R/W
R/W
R/W
Description
Condition
Reserved
WDIF
--
Watchdog interrupt flag
Reserved
2
1
EWT
Watchdog timer reset enable bit
0: Disable
1: Enable
0
RWT
R/W
Reset watchdog timer
0: NA
1: Reset
Table 5-43 WDCON register
KEYCODE
Bit
Address: 0xEB
KEYCODE Register
7
0
6
0
5
4
0
3
Keycode register
0
2
0
1
0
0
0
Function
Default
0
Bit
Function
Type
Description
Condition
0
KEYCODE[7:0]
R/W
Keycode register
Note: Some protected registers are required to write correct key code to KEYCODE register before writing data to them.
Table 5-44 KEYCODE register
CKCON
Bit
Address: 0x8E
Clock Control Register
7
WD1
0
6
WD0
0
5
WDFM
0
4
T1M
0
3
T0M
0
2
--
0
1
--
0
0
--
1
Function
Default
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Bit
Function
Type
Description
Condition
7:6
WD[1:0]
R/W
Watchdog timeout selection bits
If WDFM=0:
WD[1:0]
00
Timeout
32ms
01
128ms
512ms
2048ms
10
11
If WDFM=1: (GPM8F1129/1065A only)
WD[1:0]
00
Timeout
2ms
01
8ms
10
16ms
32ms
11
5
4
WDFM
T1M
T0M
--
R/W
R/W
R/W
R/W
Watchdog fast mode selection bit (GPM8F1129/1065A only)
0: watchdog fast mode is disabled
1: watchdog fast mode is enabled
Division selection of the system clock that drives Timer 1
0: Timer 1 uses a system clock frequency
1: Timer 1 uses a divided-by-2 of the system clock frequency
Division selection of the system clock that drives Timer 0
0: Timer 0 uses a system clock frequency
1: Timer 0 uses a divide-by-2 of the system clock frequency
Reserved
3
2:0
Table 5-45 CKCON register
PCON
Bit
Address: 0x87
Power Configuration Register
7
SMOD0
0
6
5
CPU_IDLE
0
4
PWE
0
3
2
--
0
1
STOP
0
0
--
0
Function
Default
SMOD1
0
STOP_RST_EN
0
Bit
7
Function
SMOD0
Type
Description
Condition
R/W
R/W
R/W
UART0 baud rate bit when clocked by Timer1
UART0 baud rate bit when clocked by Timer1
IDLE mode enable bit
6
SMOD1
5
CPU_IDLE
0: IDLE mode disabled ;
1: IDLE mode entered
4
3
PWE
R/W
R/W
Program Write Enable (PWE)
0: Disable Flash write activity during MOVX instruction
1: Enable Flash write activity during MOVX instruction
Wakeup state selection bit
0: Next instruction state after wakeup
1: Reset state afer wakeup
Reserved
STOP_RST_EN
2
1
--
R/W
R/W
STOP
STOP mode enable bit
0: Disabled
1: Enabled
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Bit
Function
Type
Description
Condition
0
--
R/W
Reserved
Table 5-46 PCON register
RSTCON
Bit
Address: 0x8F
Flash Error RESET Enable Control Register
7
6
5
4
3
2
1
0
FLASH_ERR_
_ENB
Function
FLASH_FLOW_
DF_EP_ ENB
XADDR_ENB
1
CHIP_E_ENB
0
LZ_EP_ENB
0
FP_EP_ENB
0
MISS_CLK_ENB
0
ENB
0
Default
0
0
Key Code
4F,72,7A
Bit
Function
Type
Description
Condition
7
DF_EP_ ENB
R/W
Data flash or loader zone erase/program reset disable control bit
0: enable 1: disable
6
5
4
3
2
1
0
LZ_EP_ ENB
R/W
Loader zone erase/program reset disable control bit
0: enable 1: disable
FLASH_FLOW_ ENB
XADDR_ENB
R/W
R/W
R/W
R/W
R/W
R/W
Error flash flow/READONLY_PAGE program reset disable control bit
0: enable 1: disable
Error flash address access reset disable control bit
0: enable 1: disable
FP_EP_ENB
First page erase/program reset disable control bit
0: enable 1: disable
CHIP_E_ ENB
Whole chip erase reset disable control bit
0: enable 1: disable
MISS_CLK _ ENB
FLASH_ERR _ ENB
Miss clock reset disable control bit (GPM8F1129/1065A only)
0: enable 1: disable
Global Flash related error reset disable control bit
0: enable 1: disable
Table 5-47 RSTCON register
FLASHERRF
Bit
Address: 0xA6
Flash Error RESET Status Flag Register
7
6
5
4
3
FP_EP_F
0
2
CHIP_E_F
0
1
--
0
0
--
0
Function
Default
DF_EP_ F
0
LZ_EP_ F
0
FLASH_FLOW_F XADDR_F
0
0
Bit
7
Function
DF_EP_ F
LZ_EP_ F
FLASH_FLOW_F
XADDR_F
FP_EP_F
CHIP_E_F
--
Type
Description
Condition
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Error data flash or loader zone erase/program reset flag
Error loader zone erase/program reset flag
Error flash flow/ READONLY_PAGE program reset flag
Error flash address access reset flag
Error first page erase/program reset flag
Error Macro erase reset flag
6
5
4
3
2
1
Reserved
0
--
Reserved
Table 5-48 FLASHERRF register
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RSTSTS
Bit
Address: 0x94
RESET Status Flag Register
7
--
0
6
5
4
3
S/W_RST
0
2
WDT_RST
0
1
LVR_RST
0
0
RAD_RST
0
Function
Default
MISS_CLK_RST
0
STOP_RST
0
FLASH_ERR_RST
0
Bit
7
Function
--
Type
Description
Condition
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
6
MISS_CLK_RST
STOP_RST
FLASH_ERR_RST
SW_RST
RESET from system clock missing clock
RESET from STOP mode
RESET from FLASH error
RESET from SW RST
5
4
3
2
WDT_RST
LVR_RST
RESET from WDT
1
RESET from LVR
0
PAD_RST
RESET from RESET PAD
Table 5-49 RSTSTS register
5.7. Clock Source
GPM8F1129/1065/1033/1019A has two clock sources including
internal oscillator (16MHz) and external crystal. These two clocks
are chosen to be system clock source by controlling related SFR.
In addition, a clock divisor for the system clock source is contained
to obtain different frequencies. There are four selections totally
and can be selected by users. The block diagram of clock source
is shown in Figure 5-8.
PER_CPU_STOP
CLK_DIV[1:0]
OSC_SEL[0]
XTAL_PAD_EN
clko_per
peripheral
clkgate
STOP
XI
IOSC_CLK
RIXCLK
DIV1~DIV8
XOSC_CLK
XO
clko
DP8051
CPU
clkgate
Figure 5-8 The block diagram of clock sources
If crystal mode is utilized, different frequencies can be selected by
IOSCT0[1:0] as shown in Table 5-51 and software should delay a
period of time according to different crystals for clock stable time.
If internal oscillator mode is utilized, trimming frequencies is
possible through IOSCT1[6:0]. Each step of frequency is 0.5%.
The IOSCT1 register is shown in Table 5-52.
IOSCCON
Bit
Address: 0xF9
IOSC Control Register
7
--
0
6
--
0
5
4
--
0
3
OSC_SEL
0
2
--
0
1
0
0
0
Function
Default
XTAL_PAD_EN
0
CLKDIV[1:0]
Bit
Function
Type
Description
Reserved
7:6
5
--
R/W
R/W
R/W
XTAL_PAD_EN
--
If using XTAL, XTAL_PAD_EN should be set first for OSC_SEL selection.
Reserved
4
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Bit
Function
Type
Description
3
OSC_SEL
R/W
0: Internal ROSC
1: External XTAL
If using XTAL, OSC_SEL should be set after XOSC_CLK is stable.
2
--
R/W
R/W
Reserved
1:0
CLK_DIV[1:0]
System Clock source divider
CLK_DIV
Clock control
00
01
10
11
SYSCLK_SOURCE
SYSCLK_SOURCE/2
SYSCLK_SOURCE/4
SYSCLK_SOURCE/8
Table 5-50 The IOSCCON register
IOSCT0
Bit
Address: 0xFA
IOSC Timing 0 Register
7
--
0
6
--
0
5
--
0
4
--
0
3
--
0
2
1
0
0
0
Function
Default
XFCN[1:0]
0
Bit
Function
Type
Description
Condition
7:6
5:3
2:0
--
--
R/W
R/W
R/W
Reserved
Reserved
XFCN[1:0]
External XTAL Frequency control bit (XTAL_PAD_EN must be “1”)
GPM8F1019A / GPM8F1033A:
XFCN
00
XTAL(HZ)
1MHz<F<4MHz
4MHz<F<8MHz
8MHz<F<12MHz
12MHz<F<16MHz
01
10
11
GPM8F1065A / GPM8F1129A:
XFCN
00
XTAL(HZ)
1MHz<F<4MHz
4MHz<F<8MHz
8MHz<F<16MHz
16MHz<F<32MHz
01
10
11
Table 5-51 The IOSCT0 register
IOSCT1
Bit
Address: 0xFB
IOSC Timing 1 Register
7
6
5
4
3
2
1
0
Function
Default
--
OSC_TRIM[6:0]
Bit
7
Function
--
Type
R/W
R/W
Description
Condition
Reserved
6:0
OSC_TUNE[6:0]
Internal OSC frequency trimming bit, 0.5% each step
Table 5-52 The IOSCT1 register
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SYSCON0
Bit
Address: 0xAE
SYSTEM control0 Register
7
LVD_STATUS
0
6
LVDENB
0
5
LVDSEL1
0
4
LVDSEL0
0
3
LVRENB
0
2
1
--
0
0
--
0
Function
Default
Key Code
CLKOUT_EN
0
FF, 00
Bit
7
Function
LVD_STATUS
LVDENB
Type
Description
Condition
R
LVD status
6
R/W
LVD enable control
0: enable LVD function
1: disable LVD function
LVD voltage selection bits
00: 2.3V
5:4
LVDSEL[1:0]
R/W
R/W
01: 2.5V
10: 3.3V
11: 3.5V
3
LVRENB
LVR enable control
0: enable LVR function
1: disable LVR function
2
CLKOUT_EN
--
R/W
R/W
Clock output enable bit (SYSCLK is output on P34)
Reserved
1:0
Table 5-53 SYSCON0 register
5.8. Slow Clock
P3 are controlled by 0xA2 and 0xA3. Read and write accesses to
the I/O port are performed via their corresponding SFRs P0(0x80),
P1(0x90), P2(0xA0) and P3(0xB0). When PU and PD are
enabled at the same time, the port can output high or low
depending on the data. Table 5-54 and Table 5-55 show the truth
GPM8F1129/1065/1033/1019A equipped with one internal
low-frequency oscillator (4KHz) for slow time interrupt.
5.9. I/O Ports
table of analog pad and digital pad respectively.
In
The GPM8F1129/1065/1033/1019A has four ports, including
standard Port 0, Port 1, Port 2 and Port 3. These port pins may
be multiplexed with an alternate function for the peripheral features
on the device. In general, when an initial reset state occurs, all
ports are used as a general purpose input port with open-drain
structure. All the ports can be programmable pull high/low by PU
and PD registers. The PU and PD registers of Port 0 are
controlled by 0xAA and 0xAB, the PU and PD registers of Port 1
are controlled by 0xAC and 0xAD, the PU and PD registers of Port
2 are controlled by 0x9E and 0x9F and the PU and PD registers of
GPM8F1129/1065/1033/1019A, P1[3:2] are used for external
crystal input and output. The built-in pull high/low resister is
50KΩ.
In addition to this, there is a register, SRCON
(GPM8F1129/1065A only), for slew rate control (0xA5) of P0~P3.
If IO ports are needed to change immediately without slew rate
control, the corresponding control bit of each port can be set to ‘0’.
The default state of SRCON register is ‘0xFF’ with 30ns slew rate
control. Figure 5-9 and Figure 5-10 show the block diagrams of
analog pad and digital pad respectively.
PU
0
PD
0
DATA
XTAL_PAD_EN
PAD
0
1
0
1
0
1
0
0
0
0
0
0
0
0
Driving Low
Floating
0
0
0
1
Driving Low
Pull low
0
1
1
0
Driving Low
Pull high
1
0
1
1
Driving Low
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PU
1
PD
1
DATA
XTAL_PAD_EN
PAD
1
x
0
1
Driving High
Floating
x
x
Table 5-54 The truth table of analog pad
PU
PD
0
DATA
PAD
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
Driving Low
Floating
0
1
Driving Low
Pull low
1
0
Driving Low
Pull high
0
1
Driving Low
Driving High
1
Table 5-55 The truth table of digital pad
XTAL_PAD_EN
ANAIP
OE=~DATA | (PU &PD)
DATA
50K
PU & ~PD
IP
50K
PD & ~PU
Figure 5-9 The block diagram of analog pad
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OE=~DATA | (PU&PD)
DATA
PU & ~PD
50K
IP
50K
PD & ~PU
Figure 5-10 The block diagram of digital pad
GPM8F1129/1065/1033/1019A can use M-type and T-type
should scan each TKEY IO status and store its responding
TKEY_XOR register to P0_TKEY (0xE3) and P3_TKEY(0xE4)
registers before the CPU enters stop mode. User can read the
TKEY_XOR register to determine the result of the current scan
operation. Figure 5-12 shows the block diagram of TKEY_XOR
register. If the status of key scan operation is different from the
content of P0_TKEY and P3_TKEY, system will wake up. If the
pin is set as scan key, the external interrupt function (P30~P34)
and keyboard pin function (P00~P07) are disabled. The number
of keys support via T-keys feature is n (n – 1 ) / 2(n= total I/Os
required). Figure 5-11 shows the T-type keyboard scan method.
keyboard application. In M-type application, each Port0 can be
configured as keyboard pin individual by setting KBIEN register
(0xA9). In stop mode, any change in these keyboard pins will
cause system wakeup by setting KB_WKUEN bit of WKUEN
register. Therefore, user should read Port0 to latch keyboard pin
data before CPU enters stop mode.
In T-type keyboard
application, Port0 and Port3 can be selected as scan key
independently by configuring P0_SC, and P3_SC respectively. If
the port is configures as scan key, it work as input with pull-high
resistor and output fixed frequency low pulse in stop mode. User
F4k
P00
P01
P02
P03
OL
PH
PH
OL
OL
PH
PH
OL
PH
OL
PH
PH
OL
PH
OL
PH
PH
PH
OL
PH
PH
OL
PH
OL
PH
PH
PH
OL
P32
P33
P34
PH
PH
PH
PH
OL
PH
PH
Figure 5-11 T-type keyboard scan method
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P3_SC (0xE2)
P0_SC (0xE1)
TKEY_XOR (0xE5)
P00
P01
P02
P33
P34
Figure 5-12 TKEY_XOR register
P0
Address: 0x80
Port0 Register
Bit
7
6
5
P05
1
4
P04
1
3
2
P02
1
1
P01
1
0
P00
1
Function
Default
P07
1
P06
1
P03
1
Bit
Function
Type
Description
Condition
7:0
P0[7:0]
R/W
Port0
Table 5-56 P0 register
P1
Address: 0x90
Port1 Register
Bit
7
P17
1
6
P16
1
5
P15
1
4
P14
1
3
P13
1
2
P12
1
1
--
1
0
--
1
Function
Default
Bit
7:2
1:0
Function
P1[7:2]
--
Type
R/W
R/W
Description
Condition
Port1
Reserved
Table 5-57 P1 register
P2
Address: 0xA0
Port2 Register
Bit
7
--
1
6
--
1
5
--
1
4
--
1
3
P23
1
2
P22
1
1
P21
1
0
P20
1
Function
Default
Bit
7:4
3:0
Function
--
Type
Description
Condition
R/W
R/W
Reserved
Port2
P2[3:0]
Table 5-58 P2 register
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P3
Address: 0xB0
Port3 Register
Bit
7
--
1
6
--
1
5
--
1
4
P34
1
3
P33
1
2
P32
1
1
P31
1
0
P30
1
Function
Default
Bit
7:5
4:0
Function
--
Type
Description
Condition
R/W
R/W
Reserved
Port3
P3[4:0]
Table 5-59 P3 register
P0_PU
Bit
Address: 0xAA
Port0 pull up configuration Register
7
P07_PU
0
6
P06_PU
0
5
P05_PU
0
4
P04_PU
0
3
P03_PU
0
2
P02_PU
0
1
P01_PU
0
0
P00_PU
0
Function
Default
Bit
Function
Type
R/W
Description
Port0 pull up control bits
0: floating; 1: pull up
Table 5-60 P0_PU register
Condition
7:0
P0_PU[7:0]
P0_PD
Bit
Address: 0xAB
Port0 pull down configuration Register
7
P07_PD
0
6
P06_PD
0
5
P05_PD
0
4
P04_PD
0
3
P03_PD
0
2
P02_PD
0
1
P01_PD
0
0
P00_PD
0
Function
Default
Bit
Function
Type
R/W
Description
Condition
7:0
P0_PD[7:0]
Port0 pull down control bits
0: floating
1: pull down
Note: If P0_PU and P0_PD are set to ‘1’ simultaneously, P0 will be output mode.
Table 5-61 P0_PD register
P1_PU
Bit
Address: 0xAC
Port1 pull up configuration Register
7
P17_PU
0
6
P16_PU
0
5
P15_PU
0
4
P14_PU
0
3
P13_PU
0
2
P12_PU
0
1
--
0
0
--
0
Function
Default
Bit
Function
Type
Description
Condition
7:2
P1_PU[7:2]
R/W
Port1 pull up control bits
0: floating;
Reserved
1: pull up
1:0
--
R/W
Table 5-62 P1_PU register
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P1_PD
Bit
Address: 0xAD
Port1 pull down configuration Register
7
P17_PD
0
6
P16_PD
0
5
P15_PD
0
4
P14_PD
0
3
P13_PD
0
2
P12_PD
0
1
--
0
0
--
0
Function
Default
Bit
Function
Type
Description
Condition
7:2
P1_PD [7:2]
R/W
Port1 pull down control bits
0: floating;
Reserved
1: pull down
1:0
--
R/W
Note: If P1_PU and P1_PD are setting to ‘1’ simultaneously, P1 will be output mode.
Table 5-63 P1_PD register
P2_PU
Bit
Address: 0x9E
Port2 pull up configuration Register
7
--
0
6
--
0
5
--
0
4
--
0
3
P23_PU
0
2
P22_PU
0
1
P21_PU
0
0
Function
Default
P20_PU
0
Bit
7:4
3:0
Function
--
Type
Description
Condition
R/W
R/W
Reserved
Port2 pull up control bits
0: floating; 1: pull up
Table 5-64 P2_PU register
P2_PU [3:0]
P2_PD
Bit
Address: 0x9F
Port2 pull down configuration Register
7
--
0
6
--
0
5
--
0
4
--
0
3
P23_PD
0
2
P22_PD
0
1
P21_PD
0
0
Function
Default
P20_PD
0
Bit
7:4
3:0
Function
--
Type
Description
Condition
R/W
Reserved
Port2 pull down control bits
0: floating; 1: pull down
Note: If P2_PU and P2_PD are setting to ‘1’ simultaneously, P2 will be output mode.
Table 5-65 P2_PD register
P2_PD [3:0]
R/W
P3_PU
Bit
Address: 0xA2
Port3 pull up configuration Register
7
--
0
6
--
0
5
--
0
4
P34_PU
0
3
P33_PU
0
2
P32_PU
0
1
P31_PU
0
0
Function
Default
P30_PU
0
Bit
7:5
4:0
Function
--
Type
Description
Condition
R/W
R/W
Reserved
Port3 pull up control bits
0: floating; 1: pull up
Table 5-66 P3_PU register
P3_PU[4:0]
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P3_PD
Bit
Address: 0xA3
Port3 pull down configuration Register
7
--
0
6
--
0
5
--
0
4
P34_PD
0
3
P33_PD
0
2
P32_PD
0
1
P31_PD
0
0
P30_PD
0
Function
Default
Bit
7:5
4:0
Function
--
Type
Description
Condition
R/W
R/W
Reserved
P3_PU[4:0]
Port3 pull up control bits
0: floating
1: pull up
Note: If P3_PU and P3_PD are setting to ‘1’ simultaneously, P3 will be output mode.
Table 5-67 P3_PD register
SRCON
Bit
Address: 0xA5
Slew Rate Control Register
7
--
0
6
--
0
5
--
0
4
--
0
3
P3_SR
1
2
P2_SR
1
1
P1_SR
1
0
P0_SR
1
Function
Default
Bit
7:4
3
Function
--
Type
Description
Condition
R/W
R/W
Reserved
P3_SR
Port3 slew rate control bit
0: slew rate control disable
1: slew rate control enable 30ns
Port2 slew rate control bit
0: slew rate control disable
1: slew rate control enable 30ns
Port1 slew rate control bit
0: slew rate control disable
1: slew rate control enable 30ns
Port0 slew rate control bit
0: slew rate control disable
1: slew rate control enable 30ns
2
1
0
P2_SR
P1_SR
P0_SR
R/W
R/W
R/W
Table 5-68 SRCON register
P0_SC
Bit
Address: 0xE1
Port0 Key Scan Control Register
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
P0_SC[7:0]
0
0
0
Bit
Function
Type
Description
Port0 key scan control
Condition
7:0
P0_SC[7:0]
R/W
0: Port0x no key scan function
1: Port0x with key scan function
Table 5-69 P0_SC register
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P3_SC
Bit
Address: 0xE2
Port3 Key Scan Control Register
7
--
0
6
--
0
5
--
0
4
0
3
2
1
0
0
0
Function
Default
P3_SC[4:0]
0
0
Bit
Function
Type Description
Condition
7:5
4:0
--
R/W Reserved
P3_SC[4:0]
R/W Port3 key scan control
0: Port3x no key scan function
1: Port3x with key scan function
Table 5-70 P3_SC register
P0_TKEY
Bit
Address: 0xE3
Port0 TKEY Compare Register
7
0
6
0
5
4
0
3
P0_TKEY[7:0]
0
2
1
0
0
0
Function
Default
0
0
Bit
Function
Type
Description
Condition
7:0
P0_ TKEY [7:0]
R/W
Port0 TKEY compare register
Table 5-71 P0_TKEY register
P3_TKEY
Bit
Address: 0xE4
Port3 TKEY Compare Register
7
0
6
0
5
4
0
3
P3_TKEY[7:0]
0
2
1
0
0
0
Function
Default
0
0
Bit
Function
Type
Description
Condition
7:0
P3_ TKEY [7:0]
R/W
Port3 TKEY compare register
Table 5-72 P3_TKEY register
TKEY_XOR
Bit
Address: 0xE5
TKEY_XOR Register
7
--
0
6
--
0
5
4
--
0
3
--
0
2
--
0
1
--
0
0
Function
Default
--
0
TKEY_XOR
Bit
Function
Type Description
Condition
7:1
0
--
R/W Reserved
TKEY_XOR
R/W XOR operation result of TKEY IO
Table 5-73 TKEY_XOR register
5.10. Timer Module
5.10.1. Introduction
these three timers are up-count timers and 16-bit timer/counter.
Each timer’s function is described in the following sections.
GPM8F1129/1065/1033/1019A is equipped with three timers.
They are Timer 0, Timer 1 and Timer 2 respectively. In addition,
Timer 2 also features Compare/Capture/Reload function. All of
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5.10.2. Timer 0/1
registers are TMOD(0x89), TCON(0x88) and CKCON(0x8E)
registers. In the timer mode, timer registers are incremented
every 1/2 SYSCLK periods depends on CKCON(0x8E) setting,
when appropriate timer is enabled.
Timer 0 and Timer 1 are fully compatible with the standard 8051
timers. Each timer consists of two 8-bit registers TH0(0x8C),
TL0(0x8A), TH1(0x8D), TL1(0x8B). Timers 0 and Timer 1 work in
the same three modes except for mode 3 and the related control
TH0
Address: 0x8C
Timer0 High Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TH0[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
TH0[7:0]
R/W
Timer 0 Load value – high byte
Table 5-74 TH0 register
TL0
Address: 0x8A
Timer0 Low Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TL0[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
TL0[7:0]
R/W
Timer 0 Load value – low byte
Table 5-75 TL0 register
TH1
Address: 0x8D
Timer1 High Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TH1[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
TH1[7:0]
R/W
Timer 1 Load value – high byte
Table 5-76 TH1 register
TL1
Address: 0x8B
Timer1 Low Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TL1[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
TL1[7:0]
R/W
Timer 1 Load value – low byte
Table 5-77 TL1 register
TMOD
Address: 0x89
Timer0/1 Control Mode Register
Bit
7
--
0
6
--
0
5
M11
0
4
M10
0
3
--
0
2
--
0
1
0
Function
Default
M01
0
M00
0
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Bit
Function
Type
Description
Condition
7:6
5:4
3:2
1:0
--
R/W
R/W
R/W
R/W
Reserved
M1[1:0]
--
Mode select bits of timer 1, which is tabled as Table 5-79
Reserved
M0[1:0]
Mode select bits of timer 0, which is tabled as Table 5-79
Table 5-78 TMOD register
M1
0
M0
0
Mode
Function description
0
1
2
TH0/1 operates as 8-bit timer with a divisor of 32 pre-scaler served by lower 5-bit of TL0/1.
16-bit timer. TH0/1 and TL0/1 are cascaded
0
1
1
0
TL0/1 operates as 8-bit timer with 8-bit auto-reload by TH0/1
TL0 is configured as 8-bit timer controlled by the standard Timer 0 bits. TH0 is an 8-bit timer
controlled by the Timer 1 controls bits. Timer 1 holds its count.
1
1
3
Table 5-79 Four modes of Timer 0 and Timer 1
TCON
Bit
Address: 0x88
Timer0/1 Configuration Register
7
TF1
0
6
TR1
0
5
TF0
0
4
TR0
0
3
IE1
0
2
--
0
1
IE0
0
0
--
0
Function
Default
Bit
7
Function
Type Description
Condition
TF1
TR1
R/W
R/W
Timer 1 interrupt (overflow) flag
Timer 1 run control bit
0: disabled
6
1: enabled
5
4
TF0
TR0
R/W
R/W
Timer 0 interrupt (overflow) flag
Timer 0 run control bit
0: disabled
1: enabled
3
2
1
0
IE1
--
R/W
R/W
R/W
R/W
INT1 interrupt flag
Reserved
IE0
--
INT0 interrupt flag
Reserved
Table 5-80 TCON register
CKCON
Address: 0x8E
Clock Control Register
Bit
7
WD1
0
6
WD0
0
5
WDFM
0
4
T1M
0
3
T0M
0
2
--
0
1
--
0
0
--
1
Function
Default
Bit
Function
Type
Description
Condition
7:6
WD[1:0]
R/W
Watchdog timeout selection bits
If WDFM=0:
WD[1:0]
00
Timeout
32ms
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Bit
Function
Type
Description
128ms
Condition
01
10
11
512ms
2048ms
If WDFM=1: (GPM8F1129/1065A only)
WD[1:0]
00
Timeout
2ms
01
8ms
10
16ms
32ms
11
5
4
WDFM
T1M
T0M
--
R/W
R/W
R/W
R/W
Watchdog fast mode selection bit (GPM8F1129/1065A only)
0: watchdog fast mode is disabled
1: watchdog fast mode is enabled
Division selection of the system clock that drives Timer 1
0: Timer 1 uses a system clock frequency
1: Timer 1 uses a divided-by-2 of the system clock frequency
Division selection of the system clock that drives Timer 0
0: Timer 0 uses a system clock frequency
1: Timer 0 uses a divide-by-2 of the system clock frequency
Reserved
3
2:0
Table 5-81 CKCON register
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5.10.2.1. Timer 0: Mode 0(13-Bit Timer)
In this mode, Timer 0 register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, Timer 0 interrupt flag
TF0 is set. The counted input is enabled to the Timer 0 when
TR0(TCON[4]) = 1. The 13-bit register consists of all 8 bits of
TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are
indeterminate and should be ignored. Figure 5-13 shows the
block diagram of Timer 0 for Mode 0.
TH0(0x8C)
TL0(0x8A)
CKCON(0x8E)
SYSCLK
clock
Interrupt request
division
13-bit upper counter
SYSCLK/2
selection
TCON(0x88)
Figure 5-13 The block diagram of Timer 0 for Mode 0
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5.10.2.2. Timer 0: Mode 1(16-bit Timer)
Mode 1 is the same as Mode 0, except that the timer register is
running with all 16 bits. The block diagram of Mode 1 is shown in
Figure 5-14.
TH0(0x8C)
TL0(0x8A)
CKCON(0x8E)
SYSCLK
clock
Interrupt request
division
16-bit upper counter
SYSCLK/2
selection
TCON(0x88)
Figure 5-14 The block diagram of Timer 0 for Mode 1
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5.10.2.3. Timer 0: Mode 2(8-Bit Timer with Auto-reload Function)
Mode 2 configures the timer register as an 8-bit counter (TL0) with
automatic reloads, as shown in Figure 5-15. Overflow from TL0
not only sets TF0, but also reloads TL0 with the contents of TH0,
which is loaded by software. The reload leaves TH0 unchanged.
TL0(0x8A)
CKCON(0x8E)
SYSCLK
clock
division
selection
Interrupt request
8-bit upper counter
SYSCLK/2
TCON(0x88)
Set
TH0(0x8C)
Figure 5-15 The block diagram of Timer 0 for Mode 2
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5.10.2.4. Timer 0: Mode 3(Two 8-Bit Timers)
Timer 0 in Mode 3 establishes TL0 and TH0 as two separate
counters. The block diagram for Mode 3 on Timer 0 is shown in
Figure 5-16. TL0 uses the Timer 0 control bits: CT0, TR0, and
TF0. TH0 is locked into a timer function and uses the TR1 and
TF1 flags from Timer 1 and controls Timer 1 interrupt. Mode 3 is
provided for applications requiring an extra 8-bit timer/counter.
When Timer 0 is in Mode 3, Timer 1 can be turned off by switching
it into its own Mode 3, or can still be used by the serial channel as
a baud rate generator, or in any application where interrupt from
Timer 1 is not required.
TH0(0x8C)
CKCON(0x8E)
Interrupt request
8-bit upper counter
TL0(0x8A)
TCON(0x88)
SYSCLK
clock
division
selection
SYSCLK/2
8-bit upper counter
Interrupt request
Figure 5-16 The block diagram of Timer 0 for Mode 3
5.10.2.5. Timer 1: Mode 0(13-Bit Timer)
In this mode, the Timer 1 register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, Timer 1 interrupt flag
TF1 is set. The counted input is enabled to the Timer1 when
TR1(TCON[6]) = 1. The 13-bit register consists of all 8 bits of
TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are
indeterminate and should be ignored. Figure 5-17 shows the
block diagram of Timer1 for Mode 0.
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TH1(0x8D)
TL1(0x8B)
CKCON(0x8E)
SYSCLK
clock
Interrupt request
division
selection
13-bit upper counter
SYSCLK/2
TCON(0x88)
Figure 5-17 The block diagram of Timer 1 for Mode 0
5.10.2.6. Timer 1: Mode 1(16-Bit Timer)
Mode 1 is the same as Mode 0, except that the timer register is
running with all 16 bits. The block diagram of Mode 1 is shown in
Figure 5-18.
TH1(0x8D)
TL1(0x8B)
CKCON(0x8E)
SYSCLK
clock
Interrupt request
division
selection
16-bit upper counter
SYSCLK/2
TCON(0x88)
Figure 5-18 The block diagram of Timer 1 for Mode 1
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5.10.2.7. Timer 1: Mode 2(8-Bit Timer with Auto-reload Function)
Mode 2 configures the timer register as an 8-bit counter (TL1) with
automatic reloads, as shown in Figure 5-19. Overflow from TL1
not only sets TF1, but it also reloads TL1 with the contents of TH1,
which is loaded by software. The reload leaves TH1 unchanged.
TL1(0x8B)
CKCON(0x8E)
SYSCLK
clock
Interrupt request
division
8-bit upper counter
SYSCLK/2
selection
TCON(0x88)
Set
TH1(0x8D)
Figure 5-19 The block diagram of Timer 1 for Mode 2
5.10.2.8. Timer 1: Mode 3
Timer 1 in Mode 3 has no timer function. The effect is the same as setting TR1=0.
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5.10.3. Timer 2
Timer 2 is a 16-bit-wide register which can operate as a timer.
The additional Capture/Reload feature is one of the most powerful
peripheral units of the core. It can be used for event capturing
such as pulse generation, pulse width measuring etc. Figure
5-20 shows the block diagram of compare and capture function for
Timer 2.
T2CON(0xC8)
T2IF(0xC9)
Interrupt request
SYSCLK
16-bit upper counter
TL2
TH2
SYSCLK/2
CMPO(P34)
Compare
Capture
16-bit
comparator
P34
CCL/CCH
CRCL/CRCH
Figure 5-20 The block diagram of compare and capture function for Timer 2
5.10.3.1.Timer Mode
5.10.3.2.Reload of Timer 2
In timer function, the count rate is derived from the oscillator
frequency. A pre-scalar offers the possibility of selecting a count
rate of 1 or 1/2 of an oscillator frequency. Thus, the 16-bit timer
register (consisted of TH2 and TL2) either increases in every 1
clock periods or in every 2 clock periods. The pre-scalar is
selected by bit T2PS of T2CON.
The reload mode for timer 2 is selected by T2R bit of T2CON.
When timer 2 rolls over from all 1’s to all 0’s, not only TF2 is set
but also timer 2 registers is loaded with the 16-bit value from CRC
register.
Required CRC value can be set by software.
Reloading occurs in the same clock cycle when TF2 is set. Thus,
it will overwrite the count value 0x0000.
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16 - bit timer
TH2(0xCD)
TL2(0xCC)
T2IF(0xC9)
T2CON(0xC8)
Timer2
interrupt
request
CRCH(0xCB)
CRCL(0xCA)
Figure 5-21 The block diagram of reload function for Timer 2
5.10.3.3. Compare Functions
The 16-bit value stored in a compare/capture register is compared
with the contents of the timer register. If the count value in the
timer register matches the stored value, an appropriate output
signal is generated on a corresponding port pin, and an interrupt is
Compare Mode 0
In compare mode 0, when the timer matches the contents of
compare register, an output signal changes from low to high. It
goes back to a low level when the timer overflows. In addition,
CCP_INVEN bit of CMPO_INV register can also control the
polarity of P34. Figure 5-22 shows a functional diagram of a port
register in compare mode. The P34 register is directly controlled
by the two signals: timer overflow and compare.
requested.
The contents of a compare register can be
considered as time stamp at which a dedicated output reacts in a
predefined way (either with a positive or negative transition).
Variation of this time stamp somehow changes the wave of a
rectangular output signal at a port pin. This may - as a variation
of the duty cycle of a periodic signal - be used for pulse width
modulation as well as for a continually controlled generation of any
Compare Mode 1
In compare mode 1, the software adaptively determines the
transition of the output signal. It is commonly used when output
signals are not related to a constant signal period. In compare
mode 1, both transitions of a signal can be controlled. If mode 1
is enabled, and the software writes to an appropriate output
register of P34, a new value will not appear at the output pin until
the next compare match occurs. User can select this way
whether the output signal should make a new transition or should
keep its old value, until the Timer 2 counter matches the stored
compare value. Figure 5-23 shows a functional diagram of Timer
2 in compare mode 1.
kind of square waveforms.
Two compare modes are
implemented to cover a wide range of possible applications. The
compare mode is selected by bit T2CM in special function register
T2CON. In all compare modes, the new value arrives at certain
pin of P34 within the same clock cycle in which the internal
compare signal is activated.
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Compare Register CC
CCH(0xC1)
CCL(0xC0)
Interrupt
CMPO_INV(0xB9)
Set Register
16-bit comparator
Reset Register
Q
P34
16 - bit timer2
T2IF(0xC9)
T2CON(0xC8)
TH2(0xCD)
TL2(0xCC)
Overflow
Interrupt
Figure 5-22 The block diagram of compare mode 0 for Timer 2
Compare Register CC
CCH(0xC1)
CCL(0xC0)
Interrupt
Shadow Register
16-bit comparator
Port Register Circuit
Output Register
P34
16 - bit timer2
TH2(0xCD)
TL2(0xCC)
T2IF(0xC9)
T2CON(0xC8)
Interrupt
Figure 5-23 The block diagram of compare mode 1 for Timer 2
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5.10.3.4. Capture Functions
The compare/capture register can be used to latch the current
16-bit value of the timer 2 registers TL2 and TH2. Two different
modes are provided for this function.
Capture mode 1
In mode 1, a capture will occur upon writing to the low order byte
of the 16-bit capture register (CCL). This mode is provided to
allow software reading of timer 2 contents on-the fly. The capture
occurs in response to a write instruction to the low order byte of a
capture register. The write-to-register signal (e.g. write-to-CCL)
is used to initiate a capture. The value written to the dedicated
capture register is irrelevant for this function. The contents of
timer 2 will be latched into the capture register in the cycle
following the write instruction. In this mode, no interrupt request
will be generated. Figure 5-24 shows functional diagrams of the
timer 2 capture function.
Capture Mode 0
In mode 0, an external event latches timer 2 contents to the
compare/capture register. A positive or negative transition on the
CAPTURE pin caused a capture, depending on the bit I3FR of
T2CON. If I3FR flag is cleared, a capture occurs in response to a
negative transition; otherwise, a capture occurs in response to a
positive transition on CAPTURE pin.
T2IF(0xC9)
T2CON(0xC8)
16 - bit timer
TH2(0xCD)
TL2(0xCC)
Overflow
Interrupt
Input clock
mode0
mode1
0
1
CAPTURE
(P34)
Capture
CCH(0xC1)
CCL(0xC0)
Write to CCL
Figure 5-24 The block diagram of Timer 2 capture mode 0 for CCL and CCH
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5.10.3.5. Timer 2 Related Registers
T2CON
Address: 0xC8
Timer2 Configuration Register
Bit
7
T2PS
0
6
I3FR
0
5
--
0
4
T2R
0
3
--
0
2
T2CM
0
1
--
0
0
T2I
0
Function
Default
Bit
Function
Type
Description
Condition
7
T2PS
R/W
Pre-scaler selection bit
0: SYSCLK
1: SYSCLK/2
6
I3FR
R/W
Interrupt edge activity selection bit of compare 0 function in combination
with capture 0 function and register CRC
Compare 0:
0: a negative transition on compare0 output can generate interrupt
1: a positive transition on compare0 output can generate interrupt
Capture 0 :
0: capture to CC register occurs on a negative transition of CAPTURE pin
1: capture to CC register occurs on a positive transition of CAPTURE pin
5
4
3
2
--
T2R
--
R/W
R/W
R/W
R/W
Reserved
Timer 2 auto-reload mode enable bit
Reserved
T2CM
Compare mode selection bit for registers CC
0: compare mode 0 is selected
1: compare mode 1 is selected
Reserved
1
0
--
R/W
R/W
T2I
Timer 2 input selection bit
0: No input selected, timer 2 is stopped
1: Timer function input frequency
SYSCLK (T2PS=0)
SYSCLK/2 (T2PS=1)
Table 5-82 T2CON register
CCEN
Address: 0xCE
Compare/Capture Enable Register
Bit
7
--
0
6
--
0
5
--
0
4
--
0
3
--
0
2
--
0
1
CMH
0
0
CML
1
Function
Default
Bit
7:2
1:0
Function
Type
R/W
R/W
Description
Condition
--
Reserved
CM
Compare/capture mode for CC register
CMH
CML
Function
0
0
1
1
0
1
0
1
Compare/capture disabled
Capture on falling/rising edge of CAPTURE pin
Compare enabled
Capture on write operation into register CCL
Table 5-83 CCEN register
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T2IF
Address: 0xC9
Timer 2 Interrupt Flag Register
Bit
7
--
0
6
--
0
5
--
0
4
CCF
0
3
--
0
2
--
0
1
--
0
0
TF2
0
Function
Default
Bit
7:1
4
Function
Type
R/W
R/W
R/W
R/W
Description
Condition
--
CCF
--
Reserved
Compare and capture flag. Cleared by the software
Reserved
3:1
0
TF2
Timer 2 overflow flag. Cleared by the software
Table 5-84 T2IF register
CCH
Address: 0xC1
Timer 2 CC Register - high byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CC[15:8]
0
0
0
Bit
Function
Type
Description
Condition
7:0
CC[15:8]
R/W
Timer2 compare/capture - high byte
Table 5-85 The CCH register
CCL
Address: 0xC0
Timer 2 CC Register - low byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CC[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
CC[7:0]
R/W
Timer2 compare/capture - low byte
Table 5-86 The CCL register
CRCH
Address: 0xCB
CRC Register - high byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CRC[15:8]
0
0
0
Bit
Function
Type
Description
Condition
7:0
CRC[15:8]
R/W
CRC - high byte
Table 5-87 The CRCH register
CRCL
Address: 0xCA
CRC Register - low byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CRC[7:0]
0
0
0
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Bit
Function
Type
Description
Condition
7:0
CRC[7:0]
R/W
CRC - low byte
Table 5-88 The CRCL register
TH2
Address: 0xCD
Timer 2 High Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TH2[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
TH2[7:0]
R/W
Timer 2 Load value – high byte
Table 5-89 TH2 register
TL2
Address: 0xCC
Timer 2 Low Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TL2[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
TL2[7:0]
R/W
Timer 2 Load value – low byte
Table 5-90 TL2 register
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5.11. UART0
UART0 has the same functionality as a standard 8051 UART.
The serial port is full duplex, meaning it can transmit and receive
concurrently. It is reception with double-buffer, meaning it can
This feature is enabled by setting SM02 bit in SCON0 register.
The master processor first sends out an address byte, which
identifies the target slave. An address byte differs from a data
byte in that the 9th bit is 1 in an address byte and 0 in a data byte.
With SM02 = 1, no slave will be interrupted by a data byte. An
address byte will interrupt all slaves. The addressed slave will
clear its SM02 bit and prepare to receive the data bytes that will
be coming. The slaves that were not being addressed leave their
SM02 set and ignoring the incoming data.
commence reception of
a second byte before a previously
received byte has been read from the receive register. Writing to
SBUF0 loads the transmit register, and reading SBUF0 reads a
physically separate receive register. Figure 5-25 shows the block
diagram of UART module. The serial port can operate in 4
modes: one synchronous and three asynchronous modes. Mode
2 and 3 has a special feature for multiprocessor communications.
Mode0
1/12
Mode1 and Mode3
1/2
RXD(P30)
UART Reception control circuit
1/4
SYSCLK
1/(256-TH1)
½ *(256-TH1)
1/16
1/64
TXD(P31)
UART Transmission control
circuit
T1M
SMOD0 & SMOD1
Mode2
SMOD0
1/32
1/64
Figure 5-25 The block diagram of UART module
5.11.1. UART0: Mode 0(Synchronous Shift register)
This mode is used as shift register IO control, and not for real
communication application. The baud rate is fixed at 1/12 of
the system clock frequency and TXD0(P31) output is a shift
clock. Eight bits are transmitted with LSB first. Reception is
initialized by setting the flags in SCON0 as follows: RI0 =0 and
REN0 =1. Figure 5-26 shows the timing diagram of UART0
transmission mode 0.
TXD0(P31)
RXD0(P30)
D0
D1
D2
D3
D4
D5
D6
D7
Figure 5-26 The timing diagram of UART0 transmission mode 0
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5.11.2. UART0: Mode 1(8-Bit UART, Variable Baud Rate, Timer1 Clock Source)
In mode 1, TXD0 serves as serial output. 10 bits are transmitted:
a start bit (always 0), 8 data bits (LSB first), and a stop bit (always
1). On receiving, a start bit synchronizes the reception, 8 data
bits are available by reading SBUF0 and stop bit sets the flag
RB08 in the SFR SCON0. The baud rate is variable and
depends from Timer 1 mode. The SMOD0 and SMOD1 bits of
PCON (0x87) are used to set the baud rate as T1ov/2 or T1ov/4 or
T1ov/16 or T1ov/64. Figure 5-27 shows the format of UART0
transmission mode 1.
TXD0(P31)
START D0
D1
D2
D3
D4
D5
D6
D7
STOP
Figure 5-27 The format of UART0 transmission mode 1
5.11.3. UART0: Mode 2(9-Bit UART, Fixed Baud Rate)
This mode is similar to Mode 1 with two differences. The baud
rate is fixed at 1/32 or 1/64 of system clock frequency, and 11 bits
are transmitted or received: a start bit (0), 8 data bits (LSB first), a
programmable 9th bit, and a stop bit (1). The 9th bit can be used
to control the parity of the UART0 interface: at transmission, bit
TB08 in SCON0 is output as the 9th bit, and at receive, the 9th bit
affects RB08 in SCON0. Figure 5-28 shows the format of UART0
transmission mode 2.
TB8 STOP
TXD0(P31)
START D0
D1
D2
D3
D4
D5
D6
D7
Figure 5-28 The format of UART0 transmission mode 2
5.11.4. UART0: Mode 3(9-Bit UART, Variable Baud Rate, Timer1 Clock Source)
The only difference between Mode 2 and Mode 3 is that the baud
rate is a variable in Mode 3. When REN0 =1 data receiving is
enabled. The baud rate is variable and depends from Timer 1
mode. The SMOD0 and SMOD1 bits of PCON (0x87) are used
to set the baud rate as T1ov/2 or T1ov/4 or T1ov/16 or T1ov/64.
Figure 5-29 shows the format of UART0 transmission mode 1.
TB8 STOP
TXD0(P31)
START D0
D1
D2
D3
D4
D5
D6
D7
Figure 5-29 The format of UART0 transmission mode 3
5.11.5. UART0 Related Registers
The UART0 related registers are: SBUF0(0x99), SCON0(0x98),
PCON(0x87), IE(0xA8) and IP(0xB8). The UART0 data buffer
(SBUF0) consists of two separate registers: transmit and receive
registers. A data writes into the SBUF0 sets this data in UART0
output register and starts a transmission. A data reads from
SBUF0, reads data from the UART0 receive register.
SBUF0
Bit
Address: 0x99
UART0 Buffer Register
7
0
6
0
5
4
0
3
2
1
0
0
Function
Default
SBUF0[7:0]
0
0
0
0
Bit
Function
Type Description
Condition
2:0
SBUF0[7:0]
R/W
UART 0 buffer
Table 5-91 SBUF0 register
SCON0
Address: 0x98
UART0 Configuration Register
Bit
7
SM00
0
6
SM01
0
5
SM02
0
4
REN0
0
3
TB08
0
2
RB08
0
1
0
RI0
0
Function
Default
TI0
0
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Bit
7:6
5
Function
SM0[1:0]
SM02
Type
R/W
R/W
R/W
R/W
R/W
Description
Condition
Mode and baud rate setting which described as below table
Enables a multiprocessor communication feature
Enable serial reception.
4
REN0
3
TB08
The 9th transmitted data bit in Modes 2 and Mode 3
In Mode 0 this bit is not used
2
RB08
In Mode 1, if SM02 is 0, RB08 is the stop bit.
In Mode 2 and Mode 3, it is the 9th data bit received
UART0 transmitter interrupt flag
1
0
TI0
RI0
R/W
R/W
UART0 receiver interrupt flag
Table 5-92 SCON0 register
SM00
SM01
Mode
Function
Shift register
8-bit UART
9-bit UART
Baud rate
0
0
1
0
1
0
0
1
2
SYSCLK/12
variable
SYSCLK/32(SMOD0=0)
SYSCLK/64(SMOD0=1)
variable
1
1
3
9-bit UART
variable: in Mode1 and Mode 3(T1M=0)
SMOD1
SMOD0
Baud rate
0
0
1
0
1
0
1
T1ov/64(T1ov=SYSCLK/(256-TH1))
T1ov/16(T1ov=SYSCLK/(256-TH1))
T1ov/4(T1ov=SYSCLK/(256-TH1))
T1ov/2(T1ov=SYSCLK/(256-TH1))
1
Note: if SMOD1=SMOD0=1, TH1 should be over than 0x10.
Baud rate setting example (SYSCLK = 16MHz, T1M=0)
Bit rate
4800
Baud rate
T1ov/16
T1ov/16
T1ov/16
T1ov/16
T1ov/2
Timer reload setting (TH1)
0x30(48)
Actual rate
4807.69
Error deviation (%)
0.16%
0.16%
0.16%
0.16%
-0.08%
0.64%
9600
0x98(152)
9615.38
19200
38400
57600
115200
0xCC(204)
19230.77
38461.54
57553.96
115942.03
0xE6(230)
0x75(117)
T1ov/2
0xBB(187)
Baud rate setting example (SYSCLK = 8MHz)
Bit rate
4800
Baud rate
T1ov/16
T1ov/16
T1ov/16
T1ov/16
T1ov/2
Timer reload setting (TH1)
0x98(152)
Actual rate
4807.69
Error deviation (%)
0.16%
9600
0xCC(204)
9615.38
0.16%
19200
38400
57600
115200
0xE6(230)
19230.77
38461.54
57971.01
114285.71
0.16%
0xF3(243)
0.16%
0xBB(187)
0.64%
T1ov/2
0xDD(221)
-0.79%
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PCON
Bit
Address: 0x87
Power Configuration Register
7
SMOD0
0
6
SMOD1
0
5
CPU_IDLE
0
4
PWE
0
3
2
--
0
1
STOP
0
0
--
0
Function
Default
STOP_RST_EN
0
Bit
7
Function
SMOD0
Type
Description
Condition
R/W
R/W
R/W
UART0 baud rate bit when clocked by Timer1
UART0 baud rate bit when clocked by Timer1
IDLE mode enable bit
6
SMOD1
5
CPU_IDLE
0: IDLE mode disabled ;
1: IDLE mode entered
4
3
PWE
R/W
R/W
Program Write Enable (PWE)
0: Disable Flash write activity during MOVX instruction
1: Enable Flash write activity during MOVX instruction
Wakeup state selection bit
0: Next instruction state after wakeup
1: Reset state afer wakeup
Reserved
STOP_RST_EN
2
1
--
R/W
R/W
STOP
STOP mode enable bit
0: Disabled
1: Enabled
0
--
R/W
Reserved
Table 5-93 PCON register
5.12. SPI
A
Serial Peripheral Interface (SPI) controller is built in
In master mode, the shifting clock (SPSCK) is generated by SPI
block. There are two control bits to control the clock phase and
polarity. The transmission starts immediately after SPI_START is
set(SPICON[0]=1,0xFC). The SPI shifts the 8-bit data from MSB
to LSB through the MOSI pin during 8 SCK cycles. Programmer
can read SPI data from MISO control register by setting SPI_RD
=1. The following four diagrams depict the timing scheme on SPI
master mode for different operation types (polarity control bit
equals “1” or “0”, phase control bit equals “1” or “0”). The related
registers are SYSCON1 register, SPICON register, SPITXD
register and SPIRXD registers which are tabled as Table 5-96 to
Table 5-97.
GPM8F1129/1065/1033/1019A to facilitate communicating with
other devices and components. The SPI controller includes four
master modes. There are four control signals on SPI including
SPCSB, SPSCK, MOSI and MISO, these four pins cannot be
GPIOs, while SPI module is enabled by corresponding control bit.
In other words, any setting on corresponding GPIO control register
will have no effect. The SPI provides following features.
Programmable phase and polarity of master clock
Programmable master SPSCK clock frequency
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SPCSB
SPSCK
MOSI
LSB
LSB
MSB
MSB
MISO
8 bit
Figure 5-30 Master Mode, POLARITY=0, PHASE=0
SPCSB
SPSCK
MOSI
LSB
LSB
MSB
MSB
MISO
Figure 5-31 Master Mode, POLARITY=0, PHASE=1
SPCSB
SPSCK
LSB
LSB
MOSI
MISO
MSB
MSB
8 bit
Figure 5-32 Master Mode, POLARITY=1, PHASE=0
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SPCSB
SPSCK
LSB
LSB
MOSI
MISO
MSB
MSB
8 bit
Figure 5-33 Master Mode, POLARITY=1, PHASE=1
SYSCON1
Bit
Address: 0xAF
System Control Register 1
7
--
0
6
--
0
5
ADorDA
0
4
SPI_EN
0
3
I2CEN
0
2
1
--
0
0
--
0
Function
Default
I2C_AUTO_RW
0
Bit
Function
Type Description
Condition
7:6
5
--
--
R
Reserved
ADorDA
I2C Address or Data indication bit for slave mode
0: Address
1: Data
4
SPI_EN
R/W SPI signals forward to P1[7:4] enable
P1[4]: SPI_TX
P1[5]: SPI_CLK
P1[6]: SPI_RX
P1[7]: SPI_CSB
Change P2[3:2] to I2C usage.
0: P2[3:2] is used as GPIO.
1: P2[3:2] is used as I2C interface.
3
2
I2CEN
R/W
I2C_AUTO_RW
R/W I2C auto read write mode enable bit (for slave mode)
0: Disable
1: Enable
1
0
IRTX_SW
R/W IRTX pin selection bit
0: IRTX pin in on P21
1: IRTX pin in on P34
--
--
Reserved
Table 5-94 SYSCON1 register
SPICON
Bit
Address: 0xFC
SPI Control Register
7
6
5
4
3
2
--
0
1
0
Function
Default
POLARITY
0
PHASE
0
SPI_CLK_SEL[1:0]
CSB_KEEP
0
SPI_RD
0
SPI_START
0
0
0
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Bit
Function
Type Description
Condition
7
POLARITY
R/W SPI CLK initial state
0: low state;
1: high state
6
PHASE
R/W SPI CLK type control
0: 1st edge sample; 1: 2nd edge sample
5:4
SPI_CLK_SEL[1:0]
R/W SPI Clock output selection:
00: SYSCLK/2
01: SYSCLK/4
10: SYSCLK/8
11: SYSCLK/16
3
CSB_KEEP
R/W SPCSB keep low state control bit
0: SPCSB keeps low state only in communication
1: SPCSB always keeps low state
2
1
0
--
--
Reserved
SPI_RD
R/W SPI read command
Read: busy flag
SPI_START
R/W
0 = SPI is not busy
1 = SPI is busy
Write: SPI start bit
1: SPI starts to transmit or receive
Table 5-95 SPICON register
SPITXD
Bit
Address: 0xFD
SPI Output Buffer Register
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
SPITXD[7:0]
0
0
0
Bit
Function
Type
R/W
Description
SPI output buffer
Condition
7:0
SPITXD
Table 5-96 SPITXD register
SPIRXD
Bit
Address: 0xFE
SPI Input Buffer Register
7
0
6
0
5
4
0
3
SPIRXD[7:0]
0
2
1
0
0
0
Function
Default
0
0
Bit
Function
Type
Description
SPI input buffer
Condition
7:0
SPIRXD
R/W
Table 5-97 SPIRXD register
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5.13. I2C
An
I2C
Interface
(I2C)
is
equipped
in
maximum number of devices connected to the bus is dictated by
the maximum allowable capacitance on the lines, 400 pF, and
the protocol's addressing limit of 16 K.
GPM8F1129/1065/1033/1019A. Only two wires (SCK and SDA)
are needed to implement the protocol. The multi-master
I2C-bus controller provides
a mechanism to communicate
5.13.1. I2C Bus Protocol
between bus masters and peripheral devices by using two
signals, a serial data line (SDA) and a serial clock line (SCK).
To avoid all possibilities of confusion, data loss and blockage of
information, the master and slave devices must have a defined
A Start condition can transfer a one-byte serial data over the
SDA line, and a stop condition can terminate the data transfer.
A “Start” condition is a high-to-low transition of SDA line while
SCK is high. A “Stop” condition is a Low-to-High transition of
the SDA line while SCK is high. Start and Stop conditions are
always generated by the master. The I2C-bus is busy when a
protocol.
In multi-master I2C-bus mode, multiple
microprocessors can receive or transmit serial data to or from
slave devices. The master that initiates a data transfer over
the I2C-bus is responsible for terminating the transfer. It is
possible to combine several masters, in addition to several
slaves onto an I2C-bus to form a multi-master system. If more
than one master simultaneously tries to control the line, an
arbitration procedure decides which master gets priority. The
Start condition is generated.
A few clocks after a Stop
condition, the I2C-bus will be free, again. Figure 5-34 shows
Start and Stop conditions.
I2CSDA
I2CSCK
Start
Stop
Condition
Condition
Figure 5-34 Start and Stop conditions
When a master initiates a Start condition, it should send a slave
address to notify the slave device. The one byte of address field
consists of a 7-bit address and a 1-bit transfer direction indicator
(that is, write or read). If bit 8 is 0, it indicates a write
operation(transmit operation); if bit 8 is 1, it indicates a request for
data read(receive operation). Every byte placed on the SDA line
should be eight bits in length. The number of bytes which can be
transmitted per transfer is unlimited. The first byte following a
Start condition should have the address field. The address field
can be transmitted by the master when the I2C-bus is operating in
The master should generate the clock pulse required to transmit
the ACK bit. Figure 5-35 and Figure 5-36 shows the format of
I2C data transmission.
In the master mode, after the data is transferred, the I2C-bus
interface will wait until pending interrupt is cleared. Until the
interrupt is cleared, the SCL line will be held low. After the
interrupt is cleared, the SCL line will be released. After the CPU
receives the interrupt request, it should write a new data into
I2CDAT register before clear the pending interrupt. In the receive
mode, after a data is received, the I2C-bus interface will wait until
pending interrupt is cleared. Until the pending interrupt is cleared,
the SCL line will be held low. After the pending interrupt is
cleared, the SCL line will be released. After the CPU receives
the interrupt request, it should read the data from I2CDAT register
before clear the pending interrupt.
master mode.
Each byte should be followed by an
acknowledgement (ACK) bit. The MSB bit of the serial data and
addresses are always sent first. To finish a one-byte transfer
operation completely, the receiver should send an ACK bit to the
transmitter. The ACK pulse should occur at the ninth clock of the
SCL line. Eight clocks are required for the one-byte data transfer.
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ACK from Receiver
MSB
Slave Address 7 bits
S
R/W
A
DATA(1Byte)
A
P
MSB
Start
Condition
“0”
Write
Stop
Condition
Figure 5-35 Write mode with 7-bits address
ACK from Receiver
ACK from Master
MSB
Slave Address 7 bits
S
R/W
A
DATA(1Byte)
A
P
MSB
Start
Condition
“1”
Read
Stop
Condition
Data from Receiver
Figure 5-36 Read mode 7-bits address
5.13.2. Bus Arbitration Procedures
Arbitration takes place on the SDA line to prevent the contention
on the bus between two masters. If a master with a SDA High
level detects another master with a SDA active Low level, it will not
initiate a data transfer because the current level on the bus does
not correspond to its own. The arbitration procedure will be
extended until the SDA line turns high. However when the
masters simultaneously lower the SDA line, each master should
evaluate whether or not the mastership is allocated to itself. For
the purpose of evaluation, each master should detect the address
bits. While each master generates the slaver address, it should
also detect the address bit on the SDA line because the lowering
of SDA line is stronger than maintaining high on the line. For
example, one master generates a Low as first address bit, while
the other master is maintaining High. In this case, both masters
will detect low on the bus because “Low” is stronger than “High”
even if first master is trying to maintain high on the line. When
this occurs, low-generating (as the first bit of address) master will
get the mastership and high-generating (as the first bit of address)
master should withdraw the mastership. If both masters generate
low as the first bit of address, there should be arbitration for
second address bit, again. This arbitration will continue to the
end of last address bit.
SYSCON1
Bit
Address: 0xAF
System Control Register 1
7
--
0
6
--
0
5
ADorDA
0
4
SPI_EN
0
3
I2CEN
0
2
1
--
0
0
--
0
Function
Default
I2C_AUTO_RW
0
Bit
Function
Type Description
Condition
7:6
5
--
--
R
Reserved
ADorDA
I2C Address or Data indication bit for slave mode
0: Address
1: Data
4
3
SPI_EN
I2CEN
R/W SPI signals forward to P1[7:4] enable
P1[4]: SPI_TX
P1[5]: SPI_CLK
P1[6]: SPI_RX
P1[7]: SPI_CSB
R/W Change P2[3:2] to I2C usage.
0: P2[3:2] is used as GPIO.
1: P2[3:2] is used as I2C interface.
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Bit
Function
Type Description
Condition
2
I2C_AUTO_RW
R/W I2C auto read write mode enable bit (for slave mode)
0: Disable
1: Enable
1
0
IRTX_SW
R/W IRTX pin selection bit
0: IRTX pin in on P21
1: IRTX pin in on P34
--
--
Reserved
Table 5-98 SYSCON1 register
I2CCON
Address: 0xDA
I2C Control Register
Bit
7
ACKEN
0
6
5
I2CIE
0
4
I2CIF
0
3
2
0
1
0
0
0
Function
CLKSEL
0
TXCLK[3:0]
Default
0
Bit
Function
Type Description
Condition
I2C-bus acknowledgement enable bit
0: Disable ACK generation
7
ACKEN
R/W
R/W
R/W
R/W
1: Enable ACK generation
Source clock of I2C-bus transmit clock pre-scaler selection bit
0: I2CCLK=SYSCLK/16
6
5
4
CLKSEL
I2CIE
1: I2CCLK= SYSCLK /512
I2C Bus TX/RX Interrupt Enable
0: Disable
1: Enable
I2C Bus TX/RX Interrupt Flag
Clear by the software
I2CIF
A I2C bus interrupt occurs
1. When a 1-byte transmitting or receiving operation is terminated.
2. When a general call or slave address match occurs.
3. If bus arbitration fails.
3:0
TXCLK[3:0]
R/W I2C-Bus transmit clock pre-scaler.
Transmit clock frequency is determined by this 4-bit pre-scaler value,
according to the following formula:
TX clock = I2CCLK/(TXCLK[3:0]+1)
NOTES:
1. I2CCLK is determined by CLKSEL
Table 5-99 I2CCON register
I2CSTS
Address: 0xDB
I2C Status Register
Bit
7
6
0
5
BUSY
0
4
DataEN
0
3
ArbS
0
2
SS
0
1
GC
0
0
ACK
0
Function
Default
MODE[1:0]
0
Bit
Function
Type Description
Condition
I2C-bus master/slave Tx/Rx mode select bits:
7:6
MODE[1:0]
R/W
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Bit
Function
Type Description
00 = Slave receive mode.
Condition
01 = Slave transmit mode.
10 = Master receive mode.
11 = Master transmit mode.
NOTE:
Under following two situations, the I2C mode will change to
slave receive mode automatically.
In slave mode, receives slave address 0x00.
In master mode, detects bus arbitration failed.
R/W Read:
5
BUSY
I2C-Bus busy signal status bit:
0 = I2C-bus not busy
1 = I2C-bus busy
Write:
0: I2C-bus interface STOP signal generation
1:
a. I2C-bus interface START signal generation
b. If BUSY is set by software as an active Master, a
repeated START will be generated after the next ACK cycle
I2C-bus data output enable/disable bit:
0 = Disable Rx/Tx
4
3
2
DataEn
ArbS
SS
R/W
R
1 = Enable Rx/Tx
I2C-bus arbitration procedure status flag bit:
0 = Bus arbitration status okay
1 = Bus arbitration failed during serial I/O
I2C-bus address-as-slave status flag bit:
0 = START/STOP condition is generated
1 = Received slave address matches the address value
in the I2CADR.
R
I2C-bus address zero status flag bit (General call):
0=START/STOP condition is generated
1=Received slave address is "0x00"
I2C-bus last-received bit status flag bit:
0 = Last-received bit is "0" (ACK is received)
1 = Last-received bit is "1" (ACK is not received)
1
0
GC
R
R
ACK
Table 5-100 I2CSTS register
I2CADR
Address: 0xDC
I2C Address Register
Bit
7
0
6
0
5
4
3
2
1
0
0
--
0
Function
Addr[7:1]
0
Default
0
0
0
Bit
Function
Type Description
Condition
7-bit slave address, latched from the I2C-bus:
It is allowable to read IAR value at any time
— Slave address = [7:1]
7:1
Addr[7:1]
R/W
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Bit
Function
Type Description
— Not mapped = [0]
Reserved
Condition
0
--
--
Table 5-101 I2CADR register
I2CDAT
Address: 0xDD
I2C Data Register
Bit
7
0
6
5
4
0
3
2
0
1
0
0
0
Function
Default
Data[7:0]
0
0
0
Bit
Function
Type Description
Condition
8-bit data shift register for I2C-bus TX/RX operation:
It is allowable to read the I2CDAT value at any time.
7:0
Data[7:0]
R/W
Table 5-102 I2CDAT register
I2CDEB
Address: 0xDE
I2C De-bounce Clock Register
Bit
7
0
6
0
5
4
0
3
DEBCLK[7:0]
0
2
1
0
0
0
Function
Default
0
0
Bit
Function
Type Description
De-bounce Clock
Condition
7:0
DEBCLK[7:0]
R/W
I2C input signal will be latched every DEBCLK cycles of system clock.
1~256: 1~256 cycles of system clock
Table 5-103 I2CDEB register
5.14. Carrier Modulator/Demodulator Timer
In GPM8F1129/1065/1033/1019A, there are two timers, timer A
and timer B, for Carrier Modulator/Demodulator Timer module.
One is an 8-bit up counter and one is a 16-bit up counter. Timer
A is special for generating carrier signal and capturing the
frequency of input signal in IR control application. Timer B is
used as modulator/demodulator for envelop generation and
detection. Three operation modes, including PWM output with
carrier mode, PWM output with no carrier mode, and direct control
mode, are included, which will be described in the following
sections. Moreover, one space extension function is realized in
CMDT module. Figure 5-37 shows the overall block diagram of
CMDT module and Table 5-104 lists the features of Timer A and
Timer B.
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TMB_DIV[1:0]
TMACLK
Fosc
Filter
TMBCLK
FOSC/1
FOSC/16
FOSC/64
FTMACAR
TMBCLK
Carrier Detect
(Timer A)
Demodulator
(Timer B)
RXOUT
TMA_DIV[1:0]
TMACLK
TMBCLK
FOSC/1
FOSC/2
FOSC/4
FOSC/8
Modulator
Out
Carrier
Out
TMACLK
Carrier Generator
(Timer A)
Modulator
(Timer B)
Output
Control
IR_TX
Figure 5-37 The block diagram of CMDT module
Timer
Timer A
Timer B
Feature 1
Feature 2
Feature 3
Feature 4
Feature 5
Feature 6
Readable and writable
Clock source selectable
Readable and writable
Clock source selectable
Interrupt-on-overflow from #$FF to #$00
Support PWM with carrier signal mode
NA
Interrupt-on-overflow from #$FFFF to #$0000
Support PWM without carrier signal mode
Gate the output with PWM with carrier signal mode
Detection of input envelop signal in IR control application
Detection of input carrier signal in IR control application
Table 5-104 The features of Timer A and Timer B
5.14.1. Carrier Generator
Timer A is used as carrier generator and consists of an 8-bit
register. It is an up counter with input clock selectable (Fosc/1,
Fosc/2, Fosc/4, and Fosc/8), which can be configured by control of
TMA_DIV[1:0]. The resolution of timer A is from 62.5ns to 500ns
based on different setting of TMA_DIV[1:0] with 16MHz internal
oscillator. The carrier signal is generated by PERIOD register
and DUTY register. PERIOD register controls carrier period and
DUTY register controls the duty of carrier signal. After enabling
Timer A, it starts to count and the carrier output is driving high.
After each increment, the contents of the counter are compared
with duty register and period register. If the count value in the
timer register is larger than duty value, a low output signal is
generated at carrier out. If the count value in the timer register is
reached to period value, a high output is produced and the counter
is reset and continues to increase. The periodic signal, carrier
output, is generated in this way. The rising flag and falling flag
(RISEIF and FALLIF) are set respectively at the rising edge and
falling edge of carrier signal, this provides user a means to update
new period and duty registers. Figure 5-38 and Figure 5-39 show
the block and timing diagram of Timer A module. Table 5-105
lists the resolution and frequency range of the carrier signal with
16MHz internal oscillator.
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DUTY Register (duty values)
TMA_DIV[1:0]
FOSC/1
FOSC/2
FOSC/4
FOSC/8
TMACLK
8-bit counter (Timer A)
PERIOD Register (period values)
Figure 5-38 The block diagram of Timer A module
TMA_CNT
PERIOD
DUTY
0
Carrier signal
Figure 5-39 The timing diagram of Timer A module
TMA_DIV[1:0]
2’b00(16MHz)
2’b01(8MHz)
2’b10(4MHz)
2’b11(2MHz)
Carrier generator resolution
Minimum carrier frequency
62.75KHz
Maximum carrier frequency
0.0625us
0.125us
0.25us
0.5us
8MHz
4MHz
2MHz
1MHz
31.37KHz
15.69KHz
7.84KHz
Table 5-105 The resolution and frequency range of the carrier signal with 16MHz internal oscillator.
Carrier frequency
15KHz
TMA_DIV[1:0]
Period register setting
0x85(133)
Actual frequency
15.0376KHz
36.0360KHz
38.0952KHz
40.0000KHz
56.3380KHz
40.0000KHz
Error deviation (%)
0.25%
2’b11(TMACLK=2MHz)
2’b10(TMACLK=4MHz)
2’b10(TMACLK=4MHz)
2’b10(TMACLK=4MHz)
2’b10(TMACLK=4MHz)
2’b10(TMACLK=4MHz)
36KHz
0x6F(111)
0.10%
38KHz
0x69(105)
0.25%
40KHz
0x64(100)
0.00%
56KHz
0x47(71)
0.60%
100KHz
0x04(4)
0.00%
Table 5-106 Carrier frequency setting example
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5.14.2. Modulator
Modulator module is realized by Timer B, it is special for envelope
signal generation with gating the carrier onto the modulator output
in IR controller application. The 16-bit timer is an up counter with
input clock selectable (Fosc/1, Fosc/16, Fosc/64, FTMACAR) via
TMB_DIV[2:0]. The minimum resolution of timer B is 62.5ns with
signal is generated at a modulator out. For example, if counter is
compared with MARK register now, a match will cause the
modulator output to be driven low, the counter continues to
increase and the compare register is directed to the SPACE
register until next match is achieved. When match is reached,
counter is reset and the modulator output would be driven high.
The flags of MARK and SPACE (MARKIF and SPACEIF) are set
respectively when a compared is match, this provides user a
means to update new MARK and SPACE registers in advance.
Figure 5-40 and Figure 5-41 show the block and timing diagram of
Timer B module. Table 5-107 lists the resolution and the period
range of the envelop signal with 16MHz internal oscillator.
Fosc/1 setting by TMB_DIV[2:0].
generated by counting the number of input clocks for both mark
and space times. The mark and space time values are
The envelop signal is
programmable by two MARK/SPACE data registers. After each
increment, the contents of the counter are compared with
mark/space data registers. If the count value in the timer register
matches the stored mark/space value, an appropriate output
MARK Register (high time values)
TMB_DIV[1:0]
FOSC/1
FOSC/16
TMBCLK
16-bit counter (Timer B)
FOSC/64
FTMACAR
SPACE Register (low time values)
Figure 5-40 The block diagram of Timer B module
TMB_CNT
SPACE
MARK
0
ENVELOP
Figure 5-41 The timing diagram of Timer B module
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TMB_DIV[1:0]
2’b00(16MHz)
2’b01(1MHz)
2’b10(0.25MHz)
2’b11
Envelop resolution
Minimum envelop period
Maximum envelop period
62.5ns
1us
125ns(MARK=62.5ns/SPACE=62.5ns)
2us(MARK=1us/SPACE=1us)
8us(MARK=4us/SPACE=4us)
2÷FTMACARR
81.92us(MARK=40.96us/SPACE=40.96us)
131.07ms(MARK=65.535ms/SPACE=65.535ms)
524.28ms
4us
(65535*2)÷FTMACARR
carrier frequency
Table 5-107 The resolution and period range of the envelop signal with 16MHz internal oscillator
5.14.2.1. PWM output with carrier signal mode
In the PWM output with carrier signal mode, user can
independently defines the duty and the frequency of carrier signal
by duty and period registers. The modulator gate is open and the
carrier output is transmitted to IR_TX. The enable bit of Timer A
should be set first by TMAEN bit in order to start the function of
timer A. Figure 5-42 shows the timing diagram of PWM output
with carrier signal mode.
Carrier output
Mark
Modulator
gate
Space
PWM output with
carrier signal
Figure 5-42 The timing diagram of PWM output with carrier signal mode
5.14.2.2. PWM output without carrier signal mode
In the PWM output without carrier signal mode, the mark and
space period is based on the mark and space counts of timer B
resolution. It is similar to PWM output with carrier signal mode,
the only difference is the carrier signal is not transmitted to IR_TX.
The PWM output is logic 1 in the mark period and is logic 0 in the
space period.
Carrier output
Mark
Modulator
gate
Space
PWM output without
carrier signal
Figure 5-43 The timing diagram of PWM output without carrier signal mode
5.14.2.3. Direct control mode
5.14.3. Output control
This mode enables user to directly control the state of the IR_TX
pin by writing to the TX_STATE bit by software. In this mode,
TMAEN and TMBEN bit must be disabled and IRTX_EN must
be enabled to accomplish this function which the output of
IR_TX is totally controlled by the TX_STATE bit.
The output control block controls the state of IR_TX no matter
carrier modulator/demodulator timer is enabled or disabled. If
carrier modulator/demodulator timer is enabled, a polarity bit
controls the high true or low true of IR_TX output. If carrier
modulator/demodulator timer is disabled, the state of IR_TX is
only controlled by the TX_STATE bit.
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is equal to the number multiplied by 65536 plus space times(216
×n+Nspace). Clearing EXSPC bit will return modulator to the
normal operation. Figure 5-44 shows the timing diagram of
extended space operation. Setting EXSPC should be during
Mark period, and clearing EXSPC should be before timer 2
overflow(TMBOIF).
5.14.4. Extended space operation
In PWM output with carrier signal mode and PWM output
without carrier signal mode, the space period can be extended
than the expected value of the space registers. Setting the
EXSPC bit will force the modulator output into the extended
space mode and the following mark and space period will be
treated as space period. The length of extended space period
Clear EXSPC
S e t E X S P C
TMBOIF
T M B O I F
SPACE
2nd TMBOIF
1st TMBOIF
M a r k
216 *n+Nspace (n=2)
Figure 5-44 The timing diagram of extended space operation
CMDTCON
Bit
Address: 0xB1
CMDT Control Register
7
IRTX_EN
0
6
5
ENVDET
0
4
EXSPC
0
3
2
1
TMBEN
0
0
TMAEN
0
Function
Default
TX_STATE
0
PWM_MODE POLARITY
0
0
Bit
Function
Type Description
Condition
7
IRTX_EN
R/W IR_TX pin enable bit
0: P21 is used as GPIO
1: P21 is used as IR_TX pin
6
TX_STATE
R/W The state of IR_TX when TMAEN,TMBEN=0 and IRTX_EN=1
0: Low state
1: High state
5
4
3
ENVDET
EXSPC
R
Envelop status
R/W Extended space operation enable bit
R/W Modulator output mode
PWM_MODE
0: PWM output with carrier signal mode
1: PWM output without carrier signal mode
R/W The polarity of IR_TX when IR_TX pin is enabled
0: IR_TX is IR_TX
2
POLARITY
1: IR_TX is inverse of IR_TX
1
0
TMBEN
TMAEN
R/W Timer B timer function enable bit
R/W Timer A timer function enable bit
Table 5-108 CMDTCON register
SYSCON1
Bit
Address: 0xAF
System Control Register 1
7
--
0
6
--
0
5
ADorDA
0
4
SPI_EN
0
3
I2CEN
0
2
1
--
0
0
--
0
Function
Default
I2C_AUTO_RW
0
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Bit
Function
Type Description
Condition
7:6
5
--
--
R
Reserved
ADorDA
I2C Address or Data indication bit for slave mode
0: Address
1: Data
4
SPI_EN
R/W SPI signals forward to P1[7:4] enable
P1[4]: SPI_TX
P1[5]: SPI_CLK
P1[6]: SPI_RX
P1[7]: SPI_CSB
Change P2[3:2] to I2C usage.
0: P2[3:2] is used as GPIO.
1: P2[3:2] is used as I2C interface.
3
2
I2CEN
R/W
I2C_AUTO_RW
R/W I2C auto read write mode enable bit (for slave mode)
0: Disable
1: Enable
1
0
IRTX_SW
R/W IRTX pin selection bit
0: IRTX pin in on P21
1: IRTX pin in on P34
--
--
Reserved
Table 5-109 SYSCON1 register
CAPCON
Bit
Address: 0xB2
CAPTURE Control Register
7
6
5
4
0
3
2
1
0
0
Function
Default
CAPB_MODE CAPB_EN
TMB_DIV[1:0]
RXOUT_INV CAPA_MODE
TMA_DIV[1:0]
0
0
0
0
0
0
Bit
Function
Type Description
Condition
7
CAPB_MODE
R/W 0: Timer B captures at every changing state
1: Timer B captures at 1st CAPAIF and TMAOIF
R/W Timer B capture function enable bit
R/W Timer B input clock selection
00: SYSCLK/1
6
CAPB_EN
5:4
TMB_DIV[1:0]
01: SYSCLK/16
10: SYSCLK/64
11: FTMACAR
3
2
RXOUT_INV
CAPA_MODE
TMA_DIV[1:0]
R/W 0: RXOUT = RXOUT_p
1: RXOUT = ~RXOUT_p
R/W 0: capture mode is off
1: RXOUT captures at every rising edge
R/W Timer A input clock selection
00: SYSCLK/1
1:0
01: SYSCLK/2
10: SYSCLK/4
11: SYSCLK/8
Table 5-110 CAPCON register
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TMAIF
Bit
Address: 0xB3
Timer A Interrupt Flag Register
7
--
0
6
--
0
5
--
0
4
CAPAIF
0
3
TMAOIF
0
2
FALLIF
0
1
RISEIF
0
0
TMAIE
0
Function
Default
Bit
Function
Type Description
Condition
7:5
4
--
R/W Reserved
CAPAIF
TMAOIF
FALLIF
RISEIF
TMAIE
R/W Timer A capture flag
R/W Timer A overflow flag
3
2
R/W Falling edge flag of carrier output
R/W Rising edge flag of carrier output
R/W Timer A interrupt enable bit
1
0
Table 5-111 TMAIF register
PERIOD
Bit
Address: 0xB4
Carrier Period Register
7
0
6
0
5
4
0
3
PERIOD[7:0]
0
2
1
0
0
0
Function
Default
0
0
Bit
Function
Type Description
Condition
7:0
PERIOD
R/W Carrier period register
Table 5-112 PERIOD register
DUTY
Bit
Address: 0xB5
Carrier Duty Register
7
0
6
0
5
4
0
3
2
0
1
0
0
0
Function
Default
DUTY[7:0]
0
0
Bit
Function
Type Description
Condition
7:0
DUTY
R/W Carrier duty register
Table 5-113 DUTY register
TMBIF
Bit
Address: 0xBA
Timer B Interrupt Flag Register
7
6
MASK_oe
0
5
FCAPBIF
0
4
RCAPBIF
0
3
TMBOIF
0
2
SPACEIF
0
1
MARKIF
0
0
TMBIE
0
Function
Default
ENVDETIF
0
Bit
Function
Type Description
Condition
7
6
ENVDETIF
MASK_oe
R/W ENVDET rising and falling flag
R/W Timer B capture flag masking enable bit
0: RCAPBIF, FCAPBIF is not masked
1: RCAPBIF, FCAPBIF is masked
R/W Timer B falling capture flag
R/W Timer B rising capture flag
R/W Timer B overflow flag
7
5
4
3
FCAPBIF
RCAPBIF
TMBOIF
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Bit
Function
Type Description
Condition
2
1
0
SPACEIF
MARKIF
TMBIE
R/W Space flag when count of timer B is match to space register
R/W Mark flag when count of timer B is match to mark register
R/W Timer B interrupt enable bit
Table 5-114 TMBIF register
MARKH
Bit
Address: 0xBC
MSB of Mark Register
7
1
6
1
5
4
0
3
2
1
0
0
0
Function
Default
MARK[15:8]
0
0
0
MARKL
Bit
Address: 0xBB
LSB of Mark Register
7
0
6
0
5
4
0
3
2
0
1
0
0
0
Function
Default
MARK[7:0]
0
0
Table 5-115 MARK register
SPACEH
Bit
Address: 0xBE
MSB of Space Register
7
1
6
1
5
4
0
3
SPACE[15:8]
0
2
1
0
0
0
Function
Default
0
0
SPACEL
Bit
Address: 0xBD
LSB of Space Register
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
SPACE[7:0]
0
0
0
Table 5-116 SPACE register
5.14.5. Carrier detect and demodulator
In IR learning function application, Timer A and Timer B should be
configured as capture mode for measuring the period and envelop
of input signal from IR_RX pin. Timer A is an 8 bit up count timer
which counts from a 0x00 value with input clock and captures at
every rising edge for the information of carrier period. The count
of timer A is captured to DUTY register. Timer B is a 16-bit up
counter and is used to capture the information of envelop. The
capture mode of Timer B should be set to ‘0’ first to determine
what kind of input signal it is(PWM output with carrier mode or
PWM output without carrier mode). In this mode, Timer B
captures at every changing state with CAPB_MODE=0. The
counts of timer B are captured to MARK register at falling edge of
RXOUT, and are captured to SPACE register at rising edge of
RXOUT. After several captures, if no TMAOIF occurs, input
signal is supposed to be PWM output with carrier mode. At this
time, user needs to change capture mode of Timer B to ‘1’ to
capture ENVDET signal. In this mode, TMAOIF would capture
the count of timer B to MARK registers and reset timer B and 1st
CAPAIF would capture the count of timer B to SPACE registers.
In this case, Timer A contents must be reloaded with 0xFF-T
-OFFSET by software and OFFSET value is decided by user for
the count margin. When the timer A overflows, the overflow
interrupt (TMAOIF) occurs(that’s over 256* TMACLK), it makes
ENVDET changed to “0”, so check ENVDET bit can know whether
envelope exist or not. As to space period, If the counter for
space period is over 0xFFFF, then its length equals to
nTMBOIF*0xFFFF + space value. Figure 5-45 and Figure 5-46
show the block diagram and timing diagram of carrier detect and
envelop detecting operation. Figure 5-47 shows the timing
diagram of envelop detect for PWM output without carrier mode.
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Period Register
MARKH Register
MARKH Register
TMA_DIV[1:0]
FOSC/1
CAPB_MODE
CAPIF_TMB
TMBOIF
FCAPBIF
TMAOIF
FOSC/2
FOSC/4
FOSC/8
8-bit counter (Timer A)
TMBCLK
16-bit counter (Timer B)
CAPAIF
Capture
RXOUT
DUTY Register
SPACEH Register
SPACEL Register
CAPA_EN
RCAPBIF
1st CAPAIF
CAPB_MODE
Figure 5-45 The block diagram of carrier detect operation
CAPB_MODE=0
CAPB_MODE=1
TMAOIF
TMAOIF
In CAPB_MODE=1,
1. TMAOIF and1st CAPAIF will resert Timer B
2. CAPAIF will not be apprered
T0
T1 T2 T3 T4 T5 T6
RXOUT
MASK_oe =1
CAPAIF
TMA_CNT
T5+T6
FF-T-OFFSET , T=(T1+T2+T3+T4+T5+T6)/3
T3+T4
T1+T2
0
DUTY
T1+T2
T3+T4
T5+T6
0
*
If MASK_oe is enabled,
either RCAPBIF or FCAPBIF will not be appeared
RCAPBIF
FCAPBIF
TMB_CNT
t0+t1+t2+t3+t4+t5
t0+t1+t2+t3+t4
t0+t1+t2+t3
t0+t1+t2
t0+t1
t0
0
tn+1
SPACE
t0
0
t0+t1+t2
*
t0+t1+t2+t3+t4
MARK
0
t0+t1
t0+t1+t2+t3+…+tn
*
TMBOIF
t0+t1+t2+t3 t0+t1+t2+t3+t4+t5
ENVDET
MARK register
SPACE register
tn+1
(Times of Timer B overflow)*0xFFFF + space value
Figure 5-46 The timing diagram of envelop detect for PWM output with carrier mode
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TMAOIF
CAPB_MODE=0
T0 T1
T2
T3
T4
T5
RXOUT
CAPAIF
Ta
Ta
T3+T4
DUTY
0
*
FF
00
TMA_CNT
*
*
RCAPBIF
FCAPBIF
TMB_CNT
T0+T1+T2
T0+T1
T0
0
SPACE
0
T0+T1+T2
T0+T1+T2+T3
T0
MARK
T0+T1+T2+T3+T4
T0+T1
T0+T1+T2+T3
0
ENVDET
Figure 5-47 The timing diagram of envelop detect for PWM output without carrier mode
RXCON
Bit
Address: 0xBF
Receive Control Register
7
--
0
6
RXOUT
0
5
4
3
--
0
2
--
0
1
0
--
0
Function
Default
FILTER_SEL[1:0]
--
0
0
0
Bit
Function
Type Description
Condition
7
6
--
R/W Reserved
RXOUT
R
RXOUT status
5:4
FILTER_SEL[1:0]
R/W RXOUT filter selection bits
00: 0ns
01: 125ns
10: 375ns
11: 875ns
5:0
--
R/W Reserved
5:0
Table 5-117 RXCON register
91
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Version: 1.0
GPM8F1129/1065/1033/1019A
5.15. Alphabetical List of Instruction Set
5.15.1. Arithmetic Operations
Mnemonic
ADD A,Rn
ADD A,direct
ADD A,@Ri
ADD A,#data
ADDC A,Rn
ADDC A,direct
ADDC A,@Ri
ADDC A,#data
SUBB A,Rn
SUBB A,direct
SUBB A,@Ri
SUBB A,#data
INC A
Description
Code
0x28-0x2F
0x25
Bytes
Cycles
Add register to accumulator
Add direct byte to accumulator
Add indirect RAM to accumulator
Add immediate data to accumulator
Add register to accumulator with carry flag
Add direct byte to A with carry flag
Add indirect RAM to A with carry flag
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment accumulator
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
1
2
1
1
1
1
1
2
2
2
1
2
2
2
1
2
2
2
1
2
3
3
1
2
3
3
1
2
6
3
0x26-0x27
0x24
0x38-0x3F
0x35
0x36-0x37
0x34
0x98-0x9F
0x95
0x96-0x97
0x94
0x04
INC Rn
Increment register
0x08-0x0F
0x05
INC direct
INC @Ri
Increment direct byte
Increment indirect RAM
0x06-0x07
0x14
DEC A
Decrement accumulator
DEC Rn
Decrement register
0x18-0x1F
0x15
DEC direct
DEC @Ri
INC DPTR
MUL A,B
Decrement direct byte
Decrement indirect RAM
0x16-0x17
0xA3
Increment data pointer
Multiply A and B
0xA4
DIV A,B
Divide A by B
0x84
DA A
Decimal adjust accumulator
0xD4
5.15.2. Logic Operations
Mnemonic
ANL A,Rn
Description
Code
0x58-0x5F
0x55
Bytes
Cycles
AND register to accumulator
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
1
2
2
2
3
3
1
2
2
2
3
3
1
2
2
2
ANL A,direct
ANL A,@Ri
AND direct byte to accumulator
AND indirect RAM to accumulator
AND immediate data to accumulator
AND accumulator to direct byte
AND immediate data to direct byte
OR register to accumulator
0x56-0x57
0x54
ANL A,#data
ANL direct,A
ANL direct,#data
ORL A,Rn
0x52
0x53
0x48-0x4F
0x45
ORL A,direct
ORL A,@Ri
ORL A,#data
ORL direct,A
ORL direct,#data
XRL A,Rn
OR direct byte to accumulator
OR indirect RAM to accumulator
OR immediate data to accumulator
OR accumulator to direct byte
0x46-0x47
0x44
0x42
OR immediate data to direct byte
Exclusive OR register to accumulator
Exclusive OR direct byte to accumulator
Exclusive OR indirect RAM to accumulator
Exclusive OR immediate data to accumulator
0x43
0x68-0x6F
0x65
XRL A,direct
XRL A,@Ri
0x66-0x67
0x64
XRL A,#data
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Mnemonic
XRL direct,A
XRL direct,#data
CLR A
Description
Code
0x62
0x63
0xE4
0xF4
0x23
0x33
0x03
0x13
0xC4
Bytes
Cycles
Exclusive OR accumulator to direct byte
Exclusive OR immediate data to direct byte
Clear accumulator
2
3
1
1
1
1
1
1
1
3
3
1
1
1
1
1
1
1
CPL A
Complement accumulator
RL A
Rotate accumulator left
RLC A
Rotate accumulator left through carry
Rotate accumulator right
RR A
RRC A
Rotate accumulator right through carry
Swap nibbles within the accumulator
SWAP A
5.15.3. Boolean Operations
Mnemonic
CLR C
Description
Code
0xC3
0xC2
0xD3
0xD2
0xB3
0xB2
0x82
0xB0
0x72
0xA0
0xA2
0x92
Bytes
Cycles
Clear carry flag
1
2
1
2
1
2
2
2
2
2
2
2
1
3
1
3
1
3
2
2
2
2
2
3
CLR bit
Clear direct bit
SETB C
Set carry flag
SETB bit
CPL C
Set direct bit
Complement carry flag
Complement direct bit
AND direct bit to carry flag
AND complement of direct bit to carry
OR direct bit to carry flag
OR complement of direct bit to carry
Move direct bit to carry flag
Move carry flag to direct bit
CPL bit
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
MOV bit,C
5.15.4. Data Transfers
Mnemonic
MOV A,Rn
Description
Code
0xE8-0xEF
0xE5
Bytes
Cycles
Move register to accumulator
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
4
1
1
2
2
2
1
3
2
2
2
3
3
3
2
3
2
3
4
5
MOV A,direct
Move direct byte to accumulator
Move indirect RAM to accumulator
Move immediate data to accumulator
Move accumulator to register
MOV A,@Ri
0xE6-0xE7
0x74
MOV A,#data
MOV Rn,A
0xF8-0xFF
0xA8-0xAF
0x78-0x7F
0xF5
MOV Rn,direct
MOV Rn,#data
MOV direct,A
Move direct byte to register
Move immediate data to register
Move accumulator to direct byte
Move register to direct byte
MOV direct,Rn
MOV direct1,direct2
MOV direct,@Ri
MOV direct,#data
MOV @Ri,A
0x88-0x8F
0x85
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate data to direct byte
Move accumulator to indirect RAM
Move direct byte to indirect RAM
Move immediate data to indirect RAM
Load 16-bit constant into active DPH and DPL in LARGE mode
Load 16-bit constant into active DPH and DPL in Flat mode
Move code byte relative to DPTR to accumulator
0x86-0x87
0x75
0xF6-0xF7
0xA6-0xA7
0x76-0x77
0x90
MOV @Ri,direct
MOV @Ri,#data
MOV DPTR,#data16
MOV DPTR,#data24
MOVC A,@A+DPTR
0x90
0x93
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Mnemonic
Description
Code
Bytes
Cycles
MOVC A,@A+PC
Move code byte relative to PC to accumulator
0x83
1
4
3*
3
XDM
MOVX A,@Ri
Move external RAM (8-bit address) to A
Move external RAM (16-bit address) to A
0xE2-0xE3
0xE0
1
1
SXDM
XDM
2*
2
MOVX A,@DPTR
SXDM
Move A to external XDM (8-bit ODE inside ROM/RAM
4*
5*
address)
Other cases
MOVX @Ri,A
0xF2-0xF3
1
1
Move A to external SXDM (8-bit
address)
All cases
3
Move A to external XDM (16-bit CODE inside ROM/RAM
3*
4*
address)
Other cases
MOVX @DPTR,A
0xF0
Move A to external SXDM (16-bit
address)
All cases
2
PUSH direct
POP direct
Push direct byte onto IDM stack
Pop direct byte from IDM stack
Exchange register with accumulator
Exchange direct byte with accumulator
0xC0
0xD0
2
2
1
2
1
1
3
2
2
3
3
3
XCH A,Rn
0xC8-0xCF
0xC5
XCH A,direct
XCH A,@Ri
XCHD A,@Ri
Exchange indirect RAM with accumulator
0xC6-0xC7
0xD6-0xD7
Exchange low-order nibble indirect RAM with A
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5.15.5. Program Branches
Mnemonic
ACALL addr11
ACALL addr19
LCALL addr16
LCALL addr23
RET
Description
Code
0x11-0xF1
0x11-0xF1
0x12
Bytes
2
Cycles
Absolute subroutine call (For GPM8F1033A/1019A)
Absolute subroutine call (For GPM8F1129A/1065A)
Long subroutine call (For GPM8F1033A/1019A)
Long subroutine call (For GPM8F1129A/1065A)
Return from subroutine (For GPM8F1033A/1019A)
Return from subroutine (For GPM8F1129A/1065A)
Return from interrupt (For GPM8F1033A/1019A)
Return from interrupt (For GPM8F1129A/1065A)
Absolute jump
4
5
4
6
4
5
4
5
3
4
3
5
4
4
3
3
5
5
5
5
4
4
5
4
5
1
3
3
0x12
4
0x22
1
RET
0x22
1
RETI
0x32
1
RETI
0x32
1
AJMP addr11
LJMP addr16
SJMP rel
0x01-0xE1
0x02
2
Long jump
3
Short jump (relative address)
0x80
2
JMP @A+DPTR
JZ rel
Jump indirect relative to the DPTR
Jump if accumulator is zero
0x73
1
0x60
2
JNZ rel
Jump if accumulator is not zero
0x70
2
JC rel
Jump if carry flag is set
0x40
2
JNC
Jump if carry flag is not set
0x50
2
JB bit,rel
Jump if direct bit is set
0x20
3
JNB bit,rel
Jump if direct bit is not set
0x30
3
JBC bit,direct rel
CJNE A,direct rel
CJNE A,#data rel
CJNE Rn,#data rel
CJNE @Ri,#data rel
DJNZ Rn,rel
DJNZ direct,rel
NOP
Jump if direct bit is set and clear bit
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to reg. and jump if not equal
Compare immediate to ind. and jump if not equal
Decrement register and jump if not zero
Decrement direct byte and jump if not zero
No operation
0x10
3
0xB5
3
0xB4
3
0xB8-0xBF
0xB6-0xB7
0xD8-0xDF
0xD5
3
3
2
3
0x00
1
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GPM8F1129/1065/1033/1019A
6. ELECTRICAL CHARACTERISTICS
6.1. Absolute Maximum Rating
Limit
Characteristics
Symbol
Unit
°C
Condition
Min.
Typ.
Max.
-65
-
150
Flash memory blank status
Flash memory programming
already performed
Storage Temperature
TSTG
°C
-40
-
150
6.2. DC Characteristics (VDD = 5V, TA = 25℃)
Limit
Typ.
Characteristics
Symbol
Unit
Condition
Min.
Max.
Operating Voltage
Operating Current
VDD
IOP
1.8
5
6
5
5.5
8
V
-
-
mA FCPU = 16MHz @ 5.5V, no load
mA FCPU = 8MHz @ 5.5V, no load
7
VDD = 5.5V, TKEY disabled
-
-
-
-
-
-
-
-
5.0
7.0
uA
and LVR disabled
VDD = 5.5V, TKEY enabled
uA
and LVR disabled
Standby Current
ISTBY
VDD = 5.5V, LVR enabled and
9.0
uA
TKEY disabled
VDD = 5.5V, TKEY enabled
10.0
uA
and LVR enabled
Input High Level
Input Low Level
VIH
VIL
0.7VDD
-
-
V
V
VDD = 5.0V
-
-
0.3VDD
VDD = 5.0V
Output High Level
Output Low Level
VOH
VOL
RPH
RPL
VLVR
0.8VDD
-
-
-
0.2VDD
70
V
IOH = -12mA at VDD = 5.0V
IOL = 12mA at VDD = 5.0V
VDD =5.0V
-
30
V
Input Pull High Resistor
Input Pull High Resistor
Low Voltage Reset
50
KΩ
KΩ
V
30
50
70
VDD = 5.0V
1.9×(1-5%)
2.3/2.5/3.3/3.5×
(1-5%)
VLVR
1.9
1.9×(1+5%)
2.3/2.5/3.3/3.5×
(1+5%)
--
2.3/2.5/
3.3/3.5
--
Low Voltage Detect
VLVD
V
V
Flash operation voltage
VFLASH
6.3. DC Characteristics (VDD = 3.3V, TA = 25℃)
Limit
Typ.
Characteristics
Symbol
Unit
Condition
Min.
Max.
Operating Voltage
Operating Current
VDD
IOP
1.8
3.3
6
3.6
8
V
-
-
mA FCPU = 16MHz @ 3.6V, no load
mA FCPU = 8MHz @ 3.6V, no load
5
7
VDD = 3.6V, TKEY disabled
-
-
-
-
-
4.0
6.0
8.0
uA
and LVR disabled
VDD = 3.6V, TKEY enabled
Standby Current
ISTBY
uA
and LVR disabled
VDD = 3.6V, LVR enabled and
-
uA
TKEY disabled
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Limit
Characteristics
Symbol
Unit
Condition
Min.
Typ.
Max.
VDD = 3.6V, TKEY enabled
and LVR enabled
VDD = 3.3V
-
-
9.0
uA
Input High Level
Input Low Level
VIH
VIL
0.7VDD
-
-
V
V
-
-
0.3VDD
VDD = 3.3V
Output High Level
Output Low Level
VOH
VOL
RPH
RPL
VLVR
0.8VDD
-
-
-
0.2VDD
70
V
IOH = -7mA at VDD = 3.3V
IOL = 7mA at VDD = 3.3V
VDD =3.3V
-
30
V
Input Pull High Resistor
Input Pull High Resistor
Low Voltage Reset
50
KΩ
KΩ
V
30
50
70
VDD = 3.3V
1.9×(1-5%)
2.3/2.5/3.3/3.5×
(1-5%)
VLVR
1.9
1.9×(1+5%)
2.3/2.5/3.3/3.5×
(1+5%)
--
2.3/2.5/
3.3/3.5
--
Low Voltage Detect
VLVD
V
V
Flash operation voltage
VFLASH
6.4. AC Characteristics (TA = 25℃)
Limit
Typ.
Characteristics
Symbol
Unit
Condition
Min.
Max.
INOSC Frequency
FOSC
16×(1-1.5%)
16
16×(1+1.5%)
MHz VDD = 2.0~5.5V
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7. APPLICATION CIRCUITS
M-Type Keyboard
P00
P01
P02
P03
P04
P05
P06
P07
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P30
P31
P32
P33
P34
GPM8F1129A
VDD
+
GPM8F1065A
GPM8F1033A
GPM8F1019A
P21 or P34
P20
IR
Receiver
0~10 Ω
VREG
VSS
1uF
-
T-Type Keyboard
P00
P01
P02
P03
P04
P05
P06
P07
GPM8F1129A
GPM8F1065A
GPM8F1033A
GPM8F1019A
VDD
+
P21 or P34
IR
Receiver
P30
P31
P32
P33
P34
P20
0~10Ω
VREG
1uF
-
VSS
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Version: 1.0
GPM8F1129/1065/1033/1019A
8. PACKAGE/PAD LOCATIONS
8.1. Ordering Information
Product Number
GPM8F1129A – nnnA – HG09x
GPM8F1065A – nnnA – HG09x
GPM8F1033A – nnnA – HG09x
GPM8F1019A – nnnA – HG09x
GPM8F1129A – nnnA – T
Package Type
Green Package
Green Package
Green Package
Green Package
-
Packing Information
Tube
Tube
Tube
Tube
Wafer
GPM8F1065A – nnnA – T
-
Wafer
GPM8F1033A – nnnA – T
-
Wafer
GPM8F1019A – nnnA – T
-
Wafer
GPM8F1129A – nnnA – EG09x
GPM8F1065A – nnnA – EG09x
GPM8F1033A – nnnA – EG09x
Green Package
Green Package
Green Package
Green Package
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
GPM8F1019A – nnnA – EG09x
Note:
1. nnn: code number from 000 to 999. To run mass production code, please apply a new code from our sales assistant first. And if no nnnA number, it means
a chip without code inside. Ex: GPM8F1129A-HG091 is a standard chip.
2. x: package serial number from 0 to 9. It will depend on the top side mark.
3. Product naming rule: ex: GPM8F1019A-nnnA-HG09x.
GPM 8 F 1 019A – nnnA - H G09 1
GeneralPlus Microcontroller
Package serial number
8051 CPU core
G09: SSOP30 package type
H: green package with tube packing
E: green package with tape and reel packing learning function.
Flash type programming memory
Mass production code number.
Remote control project
ROM size. 019 means 18K Bytes ROM
with learning function.
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Version: 1.0
GPM8F1129/1065/1033/1019A
8.2. Package Information
SSOP 30
Millimeter
Symbol
Min.
--
Nom.
Max.
2.0
A
A1
A2
b
--
--
0.05
1.65
0.22
0.09
9.90
7.40
5.00
--
1.75
--
1.85
0.38
0.21
10.50
8.20
5.60
c
--
D
10.20
7.80
5.30
0.65 BSC
0.75
1.25 REF
--
E
E1
e
L
0.55
0.95
L1
R1
θ°
0.09
--
0°
4°
8°
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GPM8F1129/1065/1033/1019A
SSOP 20
UNIT:INCH
Symbol
Min.
0.053
0.004
-
Nom.
0.064
0.006
-
Max.
0.069
0.010
0.059
0.012
0.010
0.344
0.244
0.157
A
A1
A2
b
0.008
0.007
0.337
0.228
0.150
--
C
--
D
0.341
0.236
0.154
0.025 BSC
0.025
0.041 REF
-
E
E1
e
L
0.016
0.050
L1
θ°
0°
8°
© Generalplus Technology Inc.
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GPM8F1129/1065/1033/1019A
9.DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
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GPM8F1129/1065/1033/1019A
10. REVISION HISTORY
Date
Revision #
Description
Page
93
Nov. 28, 2011
Jun. 22, 2012
0.1
0.2
Original
1. Modify FL_LEVEL register description on page 16
2. Add FLASHCON register description on page 22
3. Add SRCON register description on page 51
4. Modify Figure 5-46 and Figure 5-47
97
5. Modify Table 10-1 description on page 90
6. Add Flash program/erase voltage on page 91 and page 92
7. Add GPM8F1129A and GPM8F1065A ordering information on page 95
1. Add DPX0/DPX1 register description
Jul 10, 2012
0.3
98
2. Modify Figure 5-35 and Figure 5-36
3. Add more chip information in chapter 8.1.
Aug. 29, 2012
Nov. 26, 2013
Dec. 08, 2014
0.4
0.5
0.6
1. Add KEYCODE data at ACON register on page 27
1. Add Alphabetical list of instruction set on page 92 ~ page 95
98
102
104
1. Add Storage Temperature information
2. Modify the block diagram of watchdog timer in Figure 5-7
3. Update RSTCON register description
4. Add pad reset deglitch time on page 38
5. Add SSOP20 Pin map and PKG information
Jan. 21, 2015
1.0
Update SYSCON1 register description
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Version: 1.0
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