GPM8F2702A-HS03x [GENERALPLUS]
16-pin 8-bit Microcontroller with 2KB EEPROM;
| 型号： | GPM8F2702A-HS03x |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 16-pin 8-bit Microcontroller with 2KB EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 微控制器 |
| 文件： | 总67页 (文件大小：927K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-pin 8-bit Microcontroller with
2KB EEPROM
Preliminary
Dec. 16, 2011
Version 0.2
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
Preliminary
GPM8F2702A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 4
2. FEATURES.................................................................................................................................................................................................. 4
3. BLOCK DIAGRAM ...................................................................................................................................................................................... 5
4. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 6
4.1. PIN DESCRIPTIONS ................................................................................................................................................................................ 6
4.2. PIN MAP ............................................................................................................................................................................................... 6
5. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 7
5.1. CENTRAL PROCESSING UNIT.................................................................................................................................................................. 7
5.1.1. CPU Introduction....................................................................................................................................................................... 7
5.1.2. CPU Features ........................................................................................................................................................................... 7
5.1.3. Arithmetic Logic Unit (ALU)....................................................................................................................................................... 7
5.1.4. Accumulator A Register............................................................................................................................................................. 7
5.1.5. B Register ................................................................................................................................................................................. 7
5.1.6. Program Status Word (PSW) .................................................................................................................................................... 7
5.1.7. Program Counter (PC).............................................................................................................................................................. 7
5.2. MEMORY ORGANIZATION........................................................................................................................................................................ 8
5.2.1. Introduction ............................................................................................................................................................................... 8
5.2.2. Program Memory Allocation...................................................................................................................................................... 8
5.2.3. Data Memory Allocation...........................................................................................................................................................11
5.2.4. Memory Related SFR ..............................................................................................................................................................11
5.3. SPECIAL FUNCTION REGISTERS (SFR) ................................................................................................................................................. 15
5.4. CLOCK SOURCE................................................................................................................................................................................... 17
5.5. POWER SAVING MODE ......................................................................................................................................................................... 19
5.5.1. Introduction ............................................................................................................................................................................. 19
5.5.2. IDLE Mode.............................................................................................................................................................................. 19
5.5.3. STOP Mode ............................................................................................................................................................................ 19
5.6. INTERRUPT SYSTEM............................................................................................................................................................................. 20
5.6.1. Introduction ............................................................................................................................................................................. 20
5.7. RESET SOURCES................................................................................................................................................................................. 24
5.7.1. Introduction ............................................................................................................................................................................. 24
5.7.2. Power-On Reset (POR) .......................................................................................................................................................... 24
5.7.3. Low Voltage Reset (LVR)........................................................................................................................................................ 24
5.7.4. Pad Reset (PAD_RST)............................................................................................................................................................ 24
5.7.5. Watchdog Timer Reset (WDT_RST)....................................................................................................................................... 25
5.7.6. Other Reset Sources .............................................................................................................................................................. 26
5.8. I/O PORTS........................................................................................................................................................................................... 29
5.8.1. Introduction ............................................................................................................................................................................. 29
5.9. TIMER MODULE ................................................................................................................................................................................... 35
5.9.1. Introduction ............................................................................................................................................................................. 35
5.9.2. Timer 0/1 ................................................................................................................................................................................. 35
5.9.3. Timer 2 .................................................................................................................................................................................... 41
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Preliminary
GPM8F2702A
5.10.UART0 ............................................................................................................................................................................................... 49
5.10.1. UART0: Mode 0(Synchronous Shift register) ..................................................................................................................... 49
5.10.2. UART0: Mode 1(8-Bit UART, Variable Baud Rate, Timer1 Clock Source) ......................................................................... 50
5.10.3. UART0: Mode 2(9-Bit UART, Fixed Baud Rate)................................................................................................................. 50
5.10.4. UART0: Mode 3(9-Bit UART, Variable Baud Rate, Timer1 Clock Source) ......................................................................... 50
5.10.5. UART0 Related Registers .................................................................................................................................................. 50
5.11.ADC ................................................................................................................................................................................................... 52
5.11.1.ADC Control............................................................................................................................................................................ 52
5.11.2.ADC Related Register............................................................................................................................................................. 53
5.12.BUILT-IN COMPARATORS....................................................................................................................................................................... 56
5.13.ALPHABETICAL LIST OF INSTRUCTION SET............................................................................................................................................. 60
5.13.1. Arithmetic Operations......................................................................................................................................................... 60
5.13.2. Logic Operations ................................................................................................................................................................ 60
5.13.3. Boolean Operations............................................................................................................................................................ 61
5.13.4. Data Transfers.................................................................................................................................................................... 61
5.13.5. Program Branches.............................................................................................................................................................. 62
6. ELECTRICAL CHARACTERISTICS ......................................................................................................................................................... 63
6.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 63
6.2. AC CHARACTERISTICS (TA = 25℃)....................................................................................................................................................... 63
6.3. DC CHARACTERISTICS (VDD = 5V, TA = 25℃) ..................................................................................................................................... 63
6.4. ADC CHARACTERISTICS ...................................................................................................................................................................... 63
6.5. COMPARATOR CHARACTERISTICS......................................................................................................................................................... 64
7. PACKAGE INFORMATION ....................................................................................................................................................................... 65
7.1. ORDERING INFORMATION ..................................................................................................................................................................... 65
7.2. PACKAGE INFORMATION ....................................................................................................................................................................... 65
8. DISCLAIMER............................................................................................................................................................................................. 66
9. REVISION HISTORY ................................................................................................................................................................................. 67
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Preliminary Version: 0.2
Preliminary
GPM8F2702A
16-PIN 8-BIT MICROCONTROLLER WITH 2KB EEPROM
1. GENERAL DESCRIPTION
The GPM8F2702A is
a
highly integrated microcontroller.
−
−
−
Stop mode Reset (STOP_RST)
Besides integrating a pipelined 1T 8051 CPU, 128 Byte IDM
SRAM and 2K Byte program EEPROM, it also includes 14
programmable multi-functional I/Os, Timer0/1/2, UART, and two
comparators and one up to 6+1 channel (6 channel external ADC
Miss Clock Reset (MISS_CLK_RST)
Flash Related Error Reset (FLASH_ERR_RST)
Programmable Watchdog Timer
−
−
−
A time-base generator
An event timer
input
+
1
channel internal 1.23v) of 12-bit ADC for
general-purpose application. It operates over a wide voltage
range of 2.0V - 5.5V with different clock sources. It has two
modes in power management unit. The detail are described in
the following sections.
System supervisor
I/O Ports
−
Max 13 multifunction bi-directional I/Os
z Each incorporate with pull-up resistor, pull-down resistor,
output high, output low or floating input, depending on
programmer’s settings on the corresponding registers
z I/O ports with 20mA current sink
2. FEATURES
z I/O ports with 8mA current drive
CPU
−
One single output low I/O
−
High speed, high performance 1T 8051
z with pull-up resistor, pull-down resistor, output low or
floating input, depending on programmer’s settings on the
corresponding registers
z 100% software compatible with industry standard 8051
z Pipeline RISC architecture makes instruction execution
10 times faster than standard 8051
z I/O ports with 20mA current sink
−
−
−
Up to 16MHz clock operation, @4.5~5.5
Two 16-bit Timer/Counter (Timer 0/1)
Up to 8MHz clock operation, @ 2.7~5.5
−
−
−
Timer mode with clock source selectable
Auto reload 8 bit timers
Up to 4MHz clock operation, @ 2.0~5.5
Memories
Externally gated event counters
−
−
128 Bytes internal Data Memory (IDM) SRAM
One Powerful Timer2 with 16-bit Compare/Capture Unit
2K Bytes EEPROM with high endurance
z Minimum 100,000 program/erase cycles
z Minimum 10 years data retention
−
−
−
−
−
−
Timer mode with clock source selectable
Auto reload 16 bit timers
Externally gated event counters
Event capturing
−
Programming lock level for software security
Clock Management
Digital signals generator
−
−
Internal oscillator: 16MHz±2%, @ 2.0V~5.5V
Crystal input with 4MHz~16MHz
Pulse width modulation and measurement
UART0
Power Management
−
−
One synchronous mode
Three asynchronous modes
−
−
1 STOP mode for power saving
1 IDLE mode for only peripheral operation
A/D Converter
Interrupt Management
−
−
One 6+1 channel 12-bit resolution ADC
Max conversion clock : 2MHz (FOSC /8) @16MHz
−
−
Up to 9 interrupt sources
Up to 3 external interrupt sources
Built-in Comparators
Reset Management
−
−
Two comparators with input offset < 10mV
Internal 4-bit reference voltage generator
−
−
Power On Reset (POR)
Low Voltage Reset (LVR)
z Three trigger level (1.92V/2.61V/4.25V)
Pad Reset (PAD_RST)
*Note:
−
−
−
The lowest operating voltage (4.5/2.7/2.0) is defined by the selection of
LVR trigger level.
Watchdog Reset (WDT_RST)
Software Reset (SW_RST)
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GPM8F2702A
3. BLOCK DIAGRAM
Power
saving
XI/P01
OSC
8-bit CPU
XO/P02
circuit
controller
2K bytes
EEPROM
POR & LVR
VDD
VSS
Watchdog Timer
Timer01
Timer2
RESET Management
Comparator Circuit
ADC Circuit
Interrupt Management
PORT 3[7:0]
PORT 0[5:0]
P3[7:0]
P0[5:0]
128-byte IDM SRAM
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GPM8F2702A
4. SIGNAL DESCRIPTIONS
4.1. Pin Descriptions
Type：I = Input, O = Output, S = Supply
Pin Name
VDD
P30
SOP16
Type
S
Description
1
2
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
S
Port 3 bit 0 / RXD0 / VF0
Port 3 bit 1 / TXD0 / CF0
Port 3 bit 2 / VF1 / INT0 / VPP/ RESET
Port 3 bit 3 / INT1 / CAPTURE0
Port 3 bit 4 / T0 / CAPTURE1
Port 3 bit 5 / CF1 / T1
P31
3
P32
4
P33
5
P34
6
P35
7
P36
8
Port 3 bit 6 / CF2 / VF3 / GATE0 / SCK (2 wire serial bus clock input line)
P37
9
Port 3 bit 7 / VF2 / GATE1 / SDA (2 wire serial bus data input/output line)
P05
10
11
12
13
14
15
16
Port 0 bit 5 / AD5 / CAPTURE3
Port 0 bit 4 / AD4 / CAPTURE2
Port 0 bit 3 / AD3
P04
P03
P02
Port 0 bit 2 / AD2 / XTO
Port 0 bit 1 / AD1 / XTI
Port 0 bit 0 / AD0
P01
P00
VSS
Ground
4.2. PIN Map
SOP16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VSS
VDD
VF0/P30
CF0/P31
P00/AD0
P01/AD1/XTI
P02/AD2/XTO
P03/AD3
RESET/INT0/VPP/VF1/P32
INT1/CAPTURE0/P33
CAPTURE1/P34
GMP8F2702A
SOP16
P04/AD4/CAPTURE2
P05/AD5/CAPTURE3
P37/VF2/SDA
CF1/P35
SCK/CF2/VF3/P36
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GPM8F2702A
5. FUNCTIONAL DESCRIPTIONS
5.1. Central Processing Unit
5.1.1. CPU Introduction
addition, subtraction, multiplication and division.
operations are such as increment,
BCD-decimal-add-adjust and compare.
Additional
decrement,
Within logic unit,
The CPU is an ultra high performance, high speed embedded
microcontroller. It is designed with a special concern about
operation such as AND, OR, Exclusive OR, complement and
rotation are performed. The Boolean processor performs the bit
operations as set, clear, complement, jump-if-not-set,
jump-if-set-and-clear and move to/from carry.
performance to power consumption.
Pipelined architecture
enables the CPU 10 timers faster compared to standard
architecture. This performance can also be exploited to great
advantage in low power application where the core can be clocked
over ten times slower than original implementation for no
performance penalty.
5.1.4. Accumulator A Register
The accumulation is the 8-bit general-purpose register, which can
be operated with data transfer, temporary saving, condition
judgment, etc.
5.1.2. CPU Features
100 % software compatible with industry 8051
24 times faster multiplication
5.1.5. B Register
The B register is used during multiply and divide operations. In
other cases, it may be used as normal SFR.
12 times faster addition
The CPU is fully compatible with industry standard 8051
microcontroller, maintaining all instruction mnemonics and binary
5.1.6. Program Status Word (PSW)
compatibility.
It incorporates some great architectural
enhancements, allowing the CPU execution of instructions with
high performance and high speed. The arithmetic section of the
processor performs extensive data manipulation and is comprised
of the 8-bit arithmetic logic unit (ALU), an ACC(0xE0) register,
B(0xF0) register and PSW(0xD0) register.
The PSW contains several bits that reflect the current state of the
CPU which is similar to the flag-register of general CPU.
5.1.7. Program Counter (PC)
The program counter is a 16-bit wide register. It consists of two
8-bit registers which registers are PCH and PCL. This register
indicates the address of next instruction to be executed. In Reset
state, the content of program counter is stored with 0x0000.
5.1.3. Arithmetic Logic Unit (ALU)
The ALU performs the arithmetic and logic operations during
execution of an instruction. Typical arithmetic operations are
ACC
Address: 0xE0
Accumulator A Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
ACC[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
ACC[7:0]
R/W
Accumulator A register
Table 5-1 The ACC register
B
Address: 0xF0
B Register
Bit
7
0
6
0
5
4
0
3
2
0
1
0
0
0
Function
Default
B[7:0]
0
0
Bit
Function
Type
Description
Condition
7:0
B[7:0]
R/W
B register
Table 5-2 The B register
7
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GPM8F2702A
PSW
Address: 0xD0
Program Status Word Register
Bit
7
CY
0
6
AC
0
5
F0
0
4
RS1
0
3
RS0
0
2
OV
0
1
F1
0
0
P
0
Function
Default
Bit
7
Function
CY
Type
Description
Condition
R/W
R/W
R/W
R/W
Carry flag
6
AC
Auxiliary carry flag
5
F0
General purpose flag 0
Register bank select bits
4:3
RS[1:0]
RS[1:0]
Function description
00
Bank 0, data address 0x00-0x07
Bank 1, data address 0x08-0x0F
Bank 2, data address 0x10-0x17
Bank 3, data address 0x18-0x1F
01
10
11
2
1
0
OV
F1
P
R/W
R/W
R/W
Overflow flag
General purpose flag 1
Parity flag
Table 5-3 The PSW register
5.2. Memory Organization
5.2.1. Introduction
reset pin. If the P32 is set as external reset pin, P32_PU bit of
P3_PU and P32_PD bit of P3_PD are force to “0” and “1”
respectively. User also can select GPIO as pull low or pull high
after reset status by setting the PUEN bit of CONFIG_BYTE.
The GPM8F2702A has three separated address spaces for
program memory and data memory. The program memory is
on-chip, re-programmable EEPROM memory and contains up to
2K bytes spaces. The data memory is divided into 128 bytes of
internal data memory (IDM) and 128 bytes special function register
(SFR). The IDM and SFR use the different access address.
The SFR space can be accessed by using the direct addressing
instructions only. The detailed description of IDM and SFR are
shown is described in 5.2.3.
After each reset, the CPU starts execution in the program memory
at location 0x0000. Each interrupt has its own start address for
service routine. The EEPROM memory can be programmed
in-system, through the SCK/SDA interface or by software using the
MOVX instruction when PWE= 1. The EEPROM can be written
as SRAM without erasing first. The program operations executed
using PSIDLE (Pseudo-idle) mode to be automatically timed by
hardware without needing data polling to determine the end of the
program operation. The WTST (0x92) register is used to setting
the access time of program memory. Users must set the content
of WTST[2:0] ≧ 3’b100 before write data to program memory.
5.2.2. Program Memory Allocation
The GPM8F2702A implements 2KB memory size. It begins at
address 0x000 and ends on address 0x7FF. The last address
0x7FF is used for CONFIG_BYTE whose definition of each bit is
described in Table 5-4. User can lock the whole chip by
CODE_LOCK bit of CONFIG_BYTE.
If CODE_LOCK is
For software security consideration, user can set the
programmable Flash level by FL_LEVEL (0xED) register to limit
the code area to avoid inadvertently erase or write by software and
the protect region is called READONLY_PAGE.
programmed to be ‘0’, the program memory is protected and any
program by two wire serial interface is not allowed. The only one
thing user can do is to whole chip erase. Figure 5-1 shows the
program memory map of 2KB EEPROM. The RSTPIN_ENB bit
of CONFIG_BYTE is used to set the P32 as GPIO or dedicated
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GPM8F2702A
0x7FF
0x7FE
CONFIG_BYTE
Code Area
0x000
GPM8F2702A
Figure 5-1 Program memory organization
CONFIG_BYTE
Bit
Address: 0x7FF (Program Memory)
CONFIG_BYTE Register
7
--
1
6
--
1
5
--
1
4
PUEN
1
3
--
1
2
1
--
1
0
Function
Default
RSTPIN_ENB
1
CODE_LOCK
1
Bit
Function
Type
Description
Condition
7:5
--
R
Reserved
GPIO IO pull up or low select bit
0: set all GPIO as pull low after reset status
1: set all GPIO as pull high after reset status
Reserved
4
3
2
PUEN
--
R/W
R
External reset pin enable bit
0: set P32 as external reset pin
1: set P32 as GPIO
RSTPIN_ENB
R/W
1
0
--
R
Reserved
CODE_LOCK
R/W
Program memory protection enable bit
0 : CODE is locked
1 : CODE is unlocked
Table 5-4 The CONFIG_BYTE register
P3_PU
Bit
Address: 0xA2
Port3 pull up configuration Register
7
6
5
4
3
2
1
0
Function
Default
P37_PU
Note1
P36_PU
Note1
P35_PU
Note1
P34_PU
Note1
P33_PU
Note1
P32_PU
Note1
P31_PU
Note1
P30_PU
Note1
Bit
Function
Type
R/W
Description
Condition
7:0
P3_PU[7:0]
Port3 pull up control bits
0 : floating
1 : pull up
Table 5-5 P3_PU register
P3_PD
Bit
Address: 0xA3
Port3 pull down configuration Register
7
6
5
4
3
2
1
0
Function
Default
P37_PD
Note1
P36_PD
Note1
P35_PD
Note1
P34_PD
Note1
P33_PD
Note1
P32_PD
Note2
P31_PD
Note1
P30_PD
Note1
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GPM8F2702A
Bit
Function
Type
Description
Condition
7:0
P3_PD[7:0]
R/W
Port3 pull down control bits
0 : floating
1 : pull down
Note1: If P3_PU and P3_PD are setting to ‘1’ simultaneously, P3 will be output mode
Note2: P30_PU~P37_PU/ P30_PD~P31_PD and P33_PD~P37_PD are all “0” during reset status, and they can be set or clear by setting the PUEN bit of
CONFIG_BYTE after reset status.
Note3: P32_PD is “1” during reset status, and it can be set or clear by setting the PUEN bit of CONFIG_BYTE after reset status. If the P32 is set as external
reset pin (RSTPIN_ENB bit of CONFIG_BYTE is set to “0”), P32_PU and P32_PD are force to “0” and “1” respectively.
Table 5-6 P3_PD register
WTST
Bit
Address: 0x92
Program Memory Wait States Register
7
--
0
6
--
0
5
--
0
4
--
0
3
--
0
2
1
WTST[2:0]
0
0
0
Function
Default
1
Bit
7:3
2:0
Function
--
Type
Description
Condition
R/W
R/W
Reserved
WTST[2:0]
Program memory access time
000 : 1CLK
001 : 2CLK
010 : 3CLK
011 : 4CLK
100 : 5CLK
101 : 6CLK
110 : 7CLK
111 : 8CLK
Table 5-7 The WTST register
FL_LEVEL
Bit
Address: 0xED
Flash Level Register
7
--
0
6
--
0
5
4
--
0
3
--
0
2
1
1
0
Function
Default
--
0
FLASH_LEVEL[2:0]
1
1
Bit
7:3
2:0
Function
--
Type
R/W
R/W
Description
Condition
Reserved
FLASH_LEVEL[2:0]
Flash level select bits
FLASH_LEVEL (Locked page)
Note
0
1
2
3
4
5
6
7
address < 0x100 is read only
address < 0x200 is read only
address < 0x300 is read only
address < 0x400 is read only
address < 0x500 is read only
address < 0x600 is read only
address < 0x700 is read only
All pages are read only
Table 5-8 The FL_LEVEL register
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5.2.3. Data Memory Allocation
Data memory address allocations on the GPM8F2702A are
divided into two parts. The first part is 128 bytes of IDM and the
second one is 128 byte SFR shown in Figure 5-2. The lowest
internal data memory (IDM) consists of four register banks with
eight registers each. A bit addressable segment with 128 bits (16
bytes) begins at 0x20. The address from 0x30 to 0x7F is not
defined and can be utilized freely by user. With the direct
addressing mode, the SFR addressing from 0x80 to 0xFF is
accessed. The SFR memory map is shown in Table 5-9.
0xFF
SFR
Special Function
Registers
Reserved
(indirect addressing)
(direct addressing)
0x80
Lower Internal RAM shared with Stack space
(direct & indirect addressing)
0x30
Bit addressable area
4 banks, R0-R7 each
0x20
0x00
IDM (128B) and SFR
Figure 5-2 Data memory organization
Note: Black: standard 8051 register; gray: additional register;
0xF8
0xF0
0xE8
0xE0
0xD8
0xD0
0xC8
0xC0
0xB8
0xB0
0xA8
0xA0
0x98
0x90
0x88
0x80
IOSCCON
ADCON
IOSCT0
ADCFG
IOSCT1
ADAEN
TA
B
ADOL
ADOH
ADLB
ADUB
EIE
FLASHCON
FL_LEVEL
ACC
WDCON
PSW
T2CON
CCL0
IP
T2IF
CCH0
BIP
CRCL
CRCH
TL2
TH2
CCEN
CCL3
CCL1
CCH1
CCL2
CCH2
CCH3
CMPICON
CMPAEN
VCMPCON
CCMPCON
P3
WKUEN
IE
SYSCON
FLASHERRF
P3_PU
P0_PU
WTST
TL0
P3_PD
P0_PD
SCON0
SBUF0
EIF
RSTSTS
TH0
TCON
P0
TMOD
SP
TL1
TH1
CKCON
DPS
RSTCON
PCON
DPL0
DPH0
DPL1
DPH1
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
Table 5-9 SFR memory map
5.2.4. Memory Related SFR
accumulator register into program memory addressed by DPTR
register. Program memory can be read by MOVC only regardless
of PWE bit.
The following sub-sections describe program, external and internal
memories related SFRs of 8051 core and their functionality. For
other information about standard SFRs, please refer to appropriate
peripheral section.
5.2.4.2. Program Wait State Register
Wait States register holds the information about program memory
access time. It allows the 8051 core operation with fast and slow
program memories. The default value of WTST[2:0] is 3’b100.
5.2.4.1. Program Write Enable Bit
The Program Write Enable (PWE) bit, located in PCON register bit
4, is used during MOVX instructions. When PWE bit is set to
logic 1, the MOVX @DPTR, A instruction writes data located in
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5.2.4.3. Data Pointer Registers
internal RAM space. It is incremented before data is stored
during PUSH and CALL execution and decremented after data is
popped during POP, RET and RETI execution. In the other words,
it always points to the last valid stack byte. The SP is accessed
as any other SFRs. Figure 5-3 shows an example when PUSH A
is executed and Figure 5-4 shows an example when POP PSW is
executed.
Dual data pointer registers are implemented to speed up data
block copying. DPTR0 and DPTR1 are located in four SFR
addresses. Active DPTR register is selected by SEL bit (DPS[0]).
If SEL=0 then DPTR0 is selected otherwise DPTR1.
5.2.4.4. Stack Pointer
The 8051 has 7-bit stack pointer called SP (0x81) located in the
SP
SP
08H
07H
23H
21H
08H
07H
38H
21H
08H
07H
ACC
23H
ACC
23H
After execution
Before execution
Figure 5-3 Stack byte order for PUSH A instruction
SP
SP
07H
08H
65H
21H
08H
07H
65H
21H
08H
07H
PSW
65H
PSW
23H
After execution
Figure 5-4 Stack byte order for POP PSW instruction
Before execution
PCON
Bit
Address: 0x87
Power Configuration Register
7
SMOD0
0
6
--
0
5
CPU_IDLE
0
4
PWE
0
3
2
--
0
1
STOP
0
0
--
0
Function
Default
STOP_RST_EN
0
Bit
7
Function
SMOD0
--
Type
Description
Condition
R/W
R/W
R/W
UART0 double baud rate bit when clocked by Timer1
Reserved
6
5
CPU_IDLE
IDLE mode enable bit
0: IDLE mode disabled ;
1: IDLE mode entered
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Bit
Function
Type
Description
Condition
4
PWE
R/W
Program Write Enable (PWE)
0: Disable Flash write activity during MOVX instruction
1: Enable Flash write activity during MOVX instruction
Wakeup state selection bit
0: Next instruction state after wakeup
1: Reset state afer wakeup
Reserved
3
STOP_RST_EN
R/W
2
1
--
R/W
R/W
STOP
STOP mode enable bit
0: Disabled
1: Enabled
0
--
R/W
Reserved
Table 5-10 The PCON register
WTST
Address: 0x92
Program Memory Wait States Register
Bit
7
--
0
6
--
0
5
4
--
0
3
2
1
0
0
Function
Default
--
0
--
0
WTST[2:0]
0
1
Bit
7:3
2:0
Function
--
Type
R/W
R/W
Description
Condition
Reserved
WTST[2:0]
Program memory access time
000 : 1CLK
001 : 2CLK
010 : 3CLK
011 : 4CLK
100 : 5CLK
101 : 6CLK
110 : 7CLK
111 : 8CLK
Table 5-11 The WTST register
DPH0
Address: 0x83
Data Pointer Register - high byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
DPTR0[15:8]
0
0
0
Bit
Function
Type
Description
Condition
7:0
DPTR0[15:8]
R/W
Data pointer register DPTR0 - high byte
Table 5-12 The DPH0 register
DPL0
Address: 0x82
Data Pointer Register - low byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
DPTR0[7:0]
0
0
0
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Bit
Function
Type
Description
Data pointer register DPTR0 - low byte
Table 5-13 The DPL0 register
Condition
7:0
DPTR0[7:0]
R/W
DPH1
Address: 0x85
Data Pointer 1 Register - high byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
DPTR1[15:8]
0
0
0
Bit
Function
Type
Description
Condition
7:0
DPTR1[15:8]
R/W
Data pointer 1 register DPTR1 - high byte
Table 5-14 The DPH1 register
DPL1
Address: 0x84
Data Pointer 1 Register - low byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
DPTR1[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
DPTR1[7:0]
R/W
Data pointer 1 register DPTR1 - low byte
Table 5-15 The DPL1 register
DPS
Address: 0x86
Data Pointer Select Register
Bit
7
ID1
0
6
ID0
0
5
TSL
0
4
-
3
-
2
-
1
-
0
SEL
0
Function
Default
0
0
0
0
Bit
7:6
5
Function
ID[1:0]
TSL
Type
R/W
R/W
Description
Condition
Increment/decrement function select.
See Table 5-17
Toggle select enable bit
0 : DPTR related instructions do not affect state of SEL bit
1 : DPTR related instructions to toggle the SEL bit
Reserved
4:1
0
--
R/W
R/W
SEL
Active data pointer select bit
See Table 5-17
Table 5-16 The DPS register
ID1
0
ID0
SEL=0
INC DPTR0
SEL=1
0
1
0
1
INC DPTR1
INC DPTR1
DEC DPTR1
DEC DPTR1
0
DEC DPTR0
1
INC DPTR0
1
DEC DPTR0
Table 5-17 DPTR0/DPTR1 operations
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SP
Address: 0x81
Stack Pointer Register
Bit
7
--
0
6
0
5
4
0
3
2
1
1
0
1
Function
Default
SP[6:0]
0
0
1
Bit
7
Function
--
Type
Description
Condition
R/W
R/W
Reserved
6:0
SP[6:0]
Stack pointer
Table 5-18 The SP register
5.3. Special Function Registers (SFR)
GPM8F2702A has up to 69 control registers for special function
registers. All of the SFRs are used by MCU and peripheral
function block for controlling the desired operation. Some of the
SFRs contain control and status bits for peripheral module such as
Timer unit, Interrupt control unit, etc. Some of bits in SFRs are
read only, so write to those bits don't have any effect on
corresponding bits. Some SFRs have key code design that TA
(0xEB) register must be written with correct key codes, in
sequence, before writing a value to it for software security. The
following table shows the summary of the SFRs. The detailed
information of each SFRs are explained in each peripheral section.
Key
Reset
Value
Addr
Function
7
6
5
4
3
2
1
0
Code
0x80
0x81
0x82
0x83
0x84
0x85
0x86
P0
0xFF
0x07
0x00
0x00
0x00
0x00
0x00
--
--
--
P05
P04
P03
P02
P01
P00
SP
Stack Pointer[6:0]
DPL0
DPH0
DPL1
DPH1
DPS
Data pointer register DPTR0 - low byte
Data pointer register DPTR0 - high byte
Data pointer register DPTR1 - low byte
Data pointer register DPTR1 - high byte
ID1
ID0
--
TSL
-
-
-
-
SEL
--
STOP_
RST_EN
IE1
0x87
PCON
0x00
SMOD0
CPU_IDLE
PWE
--
STOP
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
TCON
TMOD
TL0
0x00
0x00
0x00
0x00
0x00
0x00
0x01
TF1
TR1
CT1
TF0
M11
TR0
M10
IT1
IE0
IT0
GATE1
GATE0
CT0
M01
M00
Timer 0 Load value – low byte
Timer 1 Load value – low byte
Timer 0 Load value – high byte
Timer 1 Load value – high byte
TL1
TH0
TH1
CKCON
WD1
WD0
--
--
T1M
T0M
--
--
--
--
--
0x4F,
0x72,
0x7A
CB_P_
ENB
FLASH_
ERR_
MISS_CLK_
ENB
FLASH_
0x8F
RSTCON
0x00
--
FLOW_ ENB XROM_ENB
ERR_ ENB
0x91
0x92
EIF
0x00
0x04
INTKEYF
--
--
--
--
--
--
--
--
--
--
--
WTST
WTST[2:0]
MISS_
CLK_RST
SM01
STOP_
RST
SM02
FLASH_
ERR_RST
REN0
0x94
RSTSTS
0x00
--
SW_RST WDT_RST LVR_RST
PAD_RST
RI0
0x98
0x99
0x9A
0x9B
SCON0
SBUF0
P0_PU
P0_PD
0x00
0x00
SM00
TB08
RB08
TI0
UART 0 buffer
Note0
Note0
--
--
--
--
P05_PU
P05_PD
P04_PU
P04_PD
P03_PU
P03_PD
P02_PU
P02_PD
P01_PU
P01_PD
P00_PU
P00_PD
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Key
Reset
Value
Addr
Function
7
6
5
4
3
2
1
0
Code
0xA2
0xA3
P3_PU
P3_PD
Note1
Note2
P37_PU
P37_PD
P36_PU
P36_PD
P35_PU
P35_PD
FLASH_
FLOW_F
ET2
P34_PU
P34_PD
ERR_
XROM_F
ES0
P33_PU
P33_PD
P32_PU
P32_PD
P31_PU
P31_PD
P30_PU
P30_PD
0xA6
FLASHERRF
0x00
CB_P_F
--
--
--
--
--
0xA8
0xAE
0xB0
IE
SYSCON
P3
0x00
EA
LVRENB
P37
--
--
ET1
--
EX1
--
ET0
LVRSEL1
P31
EX0
LVRSEL0
P30
0xFF,0x00 0x00
0xFF
--
--
P36
P35
P34
P33
P32
INTKEY_
WKUEN
--
INT1_
INT0_
0XB6
WKUEN
0xAF,0x50 0x83
--
--
--
--
--
WKUEN
PT0
WKUEN
PX0
0xB8
0xB9
0xBA
0xBB
0xBC
0xBD
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xD0
IP
BIP
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
--
--
--
--
PT2
PS0
PT1
--
PX1
--
--
--
--
--
--
P_CMP_KEY
CCMPIE
P_ADC
VCMPIE
P30_AEN
VCPEN
CCPEN
CMPICON
CMPAEN
VCMPCON
CCMPCON
CCL0
--
CCMPIF
P35_AEN
VCMPIF
--
P37_AEN
P36_AEN
P32_AEN P31_AEN
VFOUT
VCMP_SEL3 VCMP_SEL2
VFSEL1
CFSEL1
VFSEL0
CFSEL0
VCMP_SEL1 VCMP_SEL0
CCMP_SEL1 CCMP_SEL0
CFOUT CCMP_SEL3 CCMP_SEL2
Timer2cc compare/capture 0 low byte
Timer2cc compare/capture 0 high byte
Timer2cc compare/capture 1 low byte
Timer2cc compare/capture 1 high byte
Timer2cc compare/capture 2 low byte
Timer2cc compare/capture 2 high byte
Timer2cc compare/capture 3 low byte
Timer2cc compare/capture 3 high byte
CCH0
CCL1
CCH1
CCL2
CCH2
CCL3
CCH3
T2CON
T2IF
T2PS
--
I3FR
--
T2CM1
--
T2R
--
--
--
T2CM0
--
--
--
T2I
TF2
CRCL
CRCH
TL2
CRC register – Low byte
CRC register – High Byte
Timer 2 Load value – low byte
Timer 2 Load value – high byte
TH2
CCEN
PSW
CMH3
CY
CML3
AC
CMH2
F0
CML2
RS1
CMH1
RS0
CML1
OV
CMH0
F1
CML0
P
0xAA
0x00
,0x55
0xD8
WDCON
--
--
--
--
--
--
EWT
RWT
0xE0
0xE8
0xEB
0xEC
0xED
0xF0
0xF1
0xF2
0xF3
0xF4
0xF5
0xF6
ACC
EIE
0x00
0x00
0x00
0x00
0x07
0x00
0x00
0x00
0x00
0x00
0x80
0x00
ACC register
--
EKEYI
--
--
--
--
--
--
--
--
TA
Timed Access protection register
FLASHCON
FL_LEVEL
B
--
--
--
--
--
--
--
--
--
--
PROG
FLASH_LEVEL[2:0]
B register
ADCON
ADCFG
ADAEN
ADOL
WINF
READYF
--
WIN_SEL
CH_SEL[2:0]
P05_AEN
WINIE
ADIE
--
PSIDLE START
--
--
SHCLK[1:0]
ADCLK[1:0]
P04_AEN
P03_AEN
--
P02_AEN P01_AEN
-- --
P00_AEN
--
ADO[3:0]
ADOH
ADLB
ADO[11:4]
ADLB[7:0]
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GPM8F2702A
Key
Reset
Value
Addr
Function
7
6
5
4
3
2
1
0
Code
0xF7
0xF9
ADUB
0x00
0x02
ADUB[7:0]
XTAL_PAD
IOSCCON
--
--
--
XTAL_EN
--
CLKDIV[2:0]
--
_EN
--
0xFA
0xFB
IOSCT0
IOSCT1
0x00
0x6F
--
--
--
XFCN
OSC_TRIM[2:0]
OSC_TUNE[4:0]
Note1: P00_PU ~ P05_PU/P00_PD~P05_PD are all “0” during reset status, and they can be set or clear by PUEN bit of CONFIG_BYTE after reset status.
Note2: P30_PU~P37_PU/ P30_PD~P31_PD and P33_PD~P37_PD are all “0” during reset status, and they can be set or clear by setting the PUEN bit of
CONFIG_BYTE after reset status.
Note3: P32_PD is “1” during reset status, and it can be set or clear by setting the PUEN bit of CONFIG_BYTE after reset status. If the P32 is set as external
reset pin (RSTPIN_ENB bit of CONFIG_BYTE is set to “0”), P32_PU and P32_PD are force to “0” and “1” respectively.
5.4. Clock Source
GPM8F2702A has two clock sources including internal oscillator
(16MHz) and external crystal. These two clocks are chosen to be
system clock source by controlling XTAL_EN bit of IOSCCON
register. In addition, a clock divisor for the system clock source is
selection totally and can be controlled by CLKDIV[2:0] bits of
IOSCCON register. The block diagram of clock source and
detailed description of IOSCCON register are shown in Figure 5-5
and Table 5-19 respectively.
contained to obtain different frequencies.
There are eight
IOSCCON(0xF9)
PCON(0x87)
DIV2~DIV64
CLKGATE
PERIPHERAL
XI
IOSC_CLK
0
CLK
GENERATOR
SYSCLK_SOURCE
XOSC_CLK
1
XO
CLKGATE
CPU
DIV1.5
Figure 5-5 The block diagram of clock sources
If crystal mode is utilized, different frequencies can be selected by
IOSCT0[0] as tabled in Table 5-20 and software should delay
period of time according to different crystals for clock stable time.
In order to enter stop mode, XTAL_PAD_EN should be turned off
before PCON[1] is set to ‘1’. If internal oscillator mode is utilized,
tuning frequencies is possible through IOSCT1[7:0].
If
IOSCT1[7:5] is used for trimming bit, each step of frequency is
10%. If IOSCT1[4:0] is used for trimming bit, each step of
frequency is 1% for fine-tuning. The IOSCT1 register is shown in
Table 5-21.
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IOSCCON
Bit
Address: 0xF9
IOSC Control Register
7
--
0
6
--
0
5
4
3
--
0
2
1
0
0
Function
Default
XTAL_PAD_EN XTAL_EN
CLKDIV[2:0]
1
0
0
0
Bit
7:6
5
Function
--
Type
R/W
R/W
Description
Reserved
XTAL_PAD_EN
If using XTAL, XTAL_PAD_EN should be set to “1”
XTI and XTO can be analog PAD.
External crystal select bit
0: ROSC
4
XTAL_EN
R/W
1: XTAL
3
--
R/W
R/W
Reserved
2:0
CLK_DIV
System clock source divider
CLK_DIV
000
Clock control
SYSCLK_SOURCE
SYSCLK_SOURCE/2
SYSCLK_SOURCE/4
SYSCLK_SOURCE/8
SYSCLK_SOURCE/16
SYSCLK_SOURCE/32
SYSCLK_SOURCE/64
SYSCLK_SOURCE/1.5
001
010
011
100
101
110
111
Table 5-19 The IOSCCON register
IOSCT0
Bit
Address: 0xFA
IOSC Timing 0 Register
7
--
0
6
--
0
5
--
0
4
--
0
3
--
0
2
--
0
1
--
0
0
XFCN
0
Function
Default
Bit
Function
Type
Description
Condition
7:1
0
--
R/W
R/W
Reserved
XFCN
External crystal frequency control bit
(XTAL_PAD_EN need to be set to 1)
XFCN
XTAL(HZ)
0
1
4MHz<F<8MHz
8MHz<F<16MHz
Table 5-20 The IOSCT0 register
IOSCT1
Bit
Address: 0xFB
IOSC Control Timing 1 Register
7
6
5
4
0
3
2
1
1
0
1
Function
Default
OSC_TRIM[2:0]
1
OSC_TUNE[4:0]
1
0
1
1
Bit
Function
Type
Description
Condition
7:5
OSC_TRIM[2:0]
R/W
Internal OSC frequency trimming bit, 10% each step
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GPM8F2702A
Bit
Function
Type
Description
Internal OSC frequency trimming bit, 1% each step
Table 5-21 The IOSCT1 register
Condition
4:0
OSC_TUNE[4:0]
R/W
5.5. Power Saving Mode
5.5.1. Introduction
Processor operation will be postponed on the instruction that sets
the STOP bit. STOP mode can be exited in the following ways:
Although GPM8F2702A is a high-speed microcontrollers designed
for maximum performance, it also provide Power Management
Unit (PMU) with two advanced power conservation modes.
These modes are IDLE mode, and STOP mode. In order to
reduce the current consumption when system does not need to be
active, STOP mode can be utilized. For more information about
these two modes, please see the following two sections.
i.
When the RSTPIN_ENB bit of CONFIG_BYTE is set to “0”
and RESET pin (P32) equals to VDD.
ii. A non-clocked interrupt such as the external interrupts
INT0~INT1 and P0 key change interrupt can be used.
Clocked interrupts such as the watchdog timer, internal timers, and
serial ports do not operate in STOP mode. Processor operation
will resume with the fetching of the interrupt vector associated with
the interrupt that caused the exit from STOP mode. When the
interrupt service routine is completed, RETI returns the program to
the instruction immediately following the one that invoked the
STOP mode. When INT0~INT1 and P0 key change interrupt are
used for wakeup source, WKUEN register must be set which
tabled in Table 5-24. There are two selections of the place of
instruction execution after wakeup when entering STOP mode and
the control bit is in POCN[3]. If STOP_RST_EN is set to ‘1’, reset
state will take place after wakeup, otherwise, next instruction will
5.5.2. IDLE Mode
The IDLE Mode reduces power consumption by turning off the
clock provided to the microcontroller, causing MCU to stop to
execute following instruction. IDLE mode is entered by setting
the CPU_IDLE bit (PCON[5]). In this mode, peripheral clock is
not turned off, so peripheral device can still work normally.
5.5.3. STOP Mode
STOP mode is the lowest power states that the microcontroller can
enter. It is achieved by cutting-off frequency provided to SYSCLK,
resulting in a fully static condition. No processing is possible,
timers are stopped, and no serial communication is executed.
be executed.
GPM8F2702A.
Table 5-22 shows the three modes in
System Clock
Register setting
OFF
Peripheral Clock
Register setting
ON
After Wakeup
RUN Mode
IDLE Mode
STOP Mode
--
Next instruction state
OFF
OFF
Reset state or next instruction state base on PCON[3]
Table 5-22 The three operation modes for GPM8F2702A
PCON
Bit
Address: 0x87
Power Configuration Register
7
SMOD0
0
6
--
0
5
CPU_IDLE
0
4
PWE
0
3
2
--
0
1
STOP
0
0
--
0
Function
Default
STOP_RST_EN
0
Bit
7
Function
SMOD0
--
Type
R/W
R/W
R/W
Description
Condition
UART0 double baud rate bit when clocked by Timer1
Reserved
6
5
CPU_IDLE
IDLE mode enable bit
0: IDLE mode disabled ;
1: IDLE mode entered
4
PWE
R/W
Program Write Enable (PWE)
0: Disable Flash write activity during MOVX instruction
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GPM8F2702A
Bit
Function
Type
Description
1: Enable Flash write activity during MOVX instruction
Wakeup state selection bit
0: Next instruction state after wakeup
1: Reset state afer wakeup
Reserved
Condition
3
STOP_RST_EN
R/W
2
1
--
R/W
R/W
STOP
STOP mode enable bit
0: Disabled
1: Enabled
0
--
R/W
Reserved
Table 5-23 The PCON register
WKUEN
Address: 0xB6
Wake Up Enable Register
Bit
7
6
--
0
5
--
0
4
--
0
3
2
--
0
1
0
Function
INTKEY_WKUEN
1
--
0
INT1_WKUEN
1
INT0_WKUEN
1
Default
Key Code
0xAF, 0x50
Bit
7
Function
INTKEY_WKUEN
--
Type
R/W
R/W
R/W
R/W
Description
Condition
P0 key change wake up enable control
Reserved
6:2
1
INT1_WKUEN
INT0_WKUEN
INT1 PAD wake up enable control, active high
INT0 PAD wake up enable control, active high
0
Table 5-24 The WKUEN register
5.6. Interrupt System
5.6.1. Introduction
The GPM8F2702A provides 9 types of interrupt sources (including
6 interrupt sources of standard 8051 and additional 3 interrupt
sources) with two levels interrupt priority control which tabled in
Table 5-25. For standard 8051 interrupt sources, each interrupt
can be in high or low level priority group by setting or clearing a bit
in the IP(0xB8) registers. INT0 has the top priority in default state
and user can choose the related interrupt source to be the top
priority by IP register. For additional interrupt sources, high or low
level priority group is set or cleared a bit in the BIP(0xB9).
Interrupt requests are sampled each system clock at the rising
edge of clock control. Each interrupt vector can be individually
enabled or disabled by setting or clearing a corresponding bit in
the IE(0xA8), EIE(0xE8). The IE contains global interrupt system
disable(0) / enable(1) bit called EA. In general, once an interrupt
event occurs, the corresponding flag bit will be set. The related
registers of interrupt flag are described as below. If the related
interrupt control bit is set to enable interrupt, an interrupt request
signal will be generated and then CPU executes service routine.
If the related interrupt control bit is disabled, programmer still can
observe the corresponding flag bit, but no interrupt request signal
will be generated. The interrupt flag bits must be cleared in the
interrupt service routine to prevent program from deadlock in
interrupt service routine. With any instruction, interrupts pending
during the previous instruction is served.
Before entering
interrupt service routine, the system saves the current PC address
into top of stack pointer and jumps to corresponding vector to
execute the interrupt service. After finishing the interrupt service,
the system abstract the return PC address from the top of the
stack to execute the following instruction.
As to additional three interrupt sources, each interrupt vector can
be individually enabled or disabled by setting or clearing a
corresponding bit in the ADCON(0xF1), CMPICON(0xBA) and
EIE(0xE8).
The corresponding flag can be found in
ADCON(0xF1), CMPICON(0xBA) and EIF(0x91).
description, please refer to related block.
For detail
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Interrupt Flag
Function
Active Level/Edge
Flag Resets
Hardware
Vector Vector Number Priority
IE0
Device pin INT 0
Internal Timer 0
Device pin INT 1
Internal Timer 1
Internal UART0
Low/Falling
0x03
0x0B
0x13
0x1B
0x23
0x2B
0x33
0x3B
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
TF0
-
Hardware
IE1
Low/Falling
Hardware
TF1
-
-
-
-
-
Hardware
TI0 & RI0
TF2
Software(cleared by 0)
Software(cleared by 0)
Software(cleared by 0)
Software (cleared by 0)
Internal Timer2
WINF & READYF
CCMPIF & VCMPIF
INTKEYF
ADC interrupt
Comparator interrupt
P0 key change interrupt
Note1: INT0 and INT1 interrupt pins are activated at low level or by a falling edge
Note2: P0 key change interrupt is activated at any transition on P0. User should read P0 for latching P0 status before setting EKEYI bit of EIE(0xE8).
Table 5-25 Summaries of all interrupt sources
IP
Address: 0xB8
Interrupt Priority Register
Bit
7
-
6
--
0
5
PT2
0
4
PS0
0
3
PT1
0
2
PX1
0
1
PT0
0
0
Function
Default
PX0
0
0
Bit
7:6
5
Function
--
Type
Description
Condition
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
PT2
PS0
PT1
PX1
PT0
PX0
Timer 2 priority level control (1: high level)
UART0 priority level control (1: high level)
Timer 1 priority level control (1: high level)
INT1 priority level control (1: high level)
Timer 0 priority level control (1: high level)
INT0 priority level control (1: high level)
Table 5-26 IP register
4
3
2
1
0
BIP
Address: 0xB9
Additional Interrupt Priority Register
Bit
7
--
0
6
--
0
5
--
0
4
--
0
3
--
0
2
--
0
1
0
P_ADC
0
Function
Default
P_CMP_KEY
0
Bit
7:2
1
Function
Type
R/W Reserved
Description
Condition
--
P_CMP_KEY
P_ADC
R/W Comparator interrupt and P0 key change interrupt priority level control (1: high level)
R/W ADC interrupt priority level control (1: high level)
0
Table 5-27 BIP register
IE
Address: 0xA8
Interrupt Enable Register
Bit
7
EA
0
6
--
0
5
ET2
0
4
ES0
0
3
ET1
0
2
EX1
0
1
ET0
0
0
EX0
0
Function
Default
Bit
7
Function
Type
R/W
R/W
Description
Condition
EA
--
Enable global interrupts
Reserved
6
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Bit
5
Function
ET2
Type
R/W
R/W
R/W
R/W
R/W
R/W
Description
Condition
Enable Timer 2 interrupt
Enable UART0 interrupt
Enable Timer 1 interrupt
Enable INT1 interrupt
Enable Timer 0 interrupt
Enable INT0 interrupt
4
ES0
3
ET1
2
EX1
1
ET0
0
EX0
Table 5-28 IE register
EIE
Address: 0xE8
Extended Interrupt Enable Register
Bit
7
EKEYI
0
6
--
0
5
4
--
0
3
--
0
2
--
0
1
--
0
0
--
0
Function
Default
--
0
Bit
7
Function
EKEYI
--
Type
R/W
R/W
Description
Condition
Enable P0 key change interrupt
Reserved
6:0
Table 5-29 EIE register
TCON
Address: 0x88
Timer0/1 Configuration Register
Bit
7
TF1
0
6
TR1
0
5
TF0
0
4
TR0
0
3
IE1
0
2
IT1
0
1
IE0
0
0
Function
Default
IT0
0
Bit
7
Function
TF1
Type
R/W
R/W
Description
Condition
Timer 1 interrupt (overflow) flag
Timer 1 run control bit
0: disabled ;
6
TR1
1: enabled
5
4
TF0
TR0
R/W
R/W
Timer 0 interrupt (overflow) flag
Timer 0 run control bit
0: disabled ;
1: enabled
3
2
1
0
IE1
IT1
IE0
IT0
R/W
R/W
R/W
R/W
INT1 interrupt flag
INT1 level (at 0)/ edge (at 1) sensitivity
INT0 interrupt flag
INT0 level (at 0)/ edge (at 1) sensitivity
Table 5-30 TCON register
T2IF
Address: 0xC9
Timer 2 Interrupt Flag Register
Bit
7
--
0
6
--
0
5
--
0
4
--
0
3
--
0
2
--
0
1
--
0
0
Function
Default
TF2
0
Bit
Function
Type
Description
Condition
7:1
--
R/W
Reserved
Timer 2 overflow flag
Cleared by the software
0
TF2
R/W
Table 5-31 T2IF register
22
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GPM8F2702A
SCON0
Bit
Address: 0x98
UART0 Configuration Register
7
SM00
0
6
--
0
5
SM02
0
4
REN0
0
3
TB08
0
2
RB08
0
1
TI0
0
0
RI0
0
Function
Default
Bit
7:6
5
Function
SM0[1:0]
SM02
Type
R/W
R/W
R/W
R/W
R/W
Description
Condition
Mode and baud rate setting
Enables a multiprocessor communication feature
Enable serial reception.
4
REN0
3
TB08
The 9th transmitted data bit in Modes 2 and Mode 3
In Mode 0 this bit is not used
2
RB08
In Mode 1, if SM02 is 0, RB08 is the stop bit.
In Mode 2 and Mode 3, it is the 9th data bit received
UART0 transmitter interrupt flag
1
0
TI0
RI0
R/W
R/W
UART0 receiver interrupt flag
Table 5-32 SCON0 register
EIF
Address: 0x91
Extended Interrupt Flag Register
Bit
7
INTKEYF
0
6
--
0
5
4
--
0
3
2
1
--
0
0
--
0
Function
Default
--
0
--
--
0
0
Bit
7
Function
INTKEYF
--
Type
R/W
R/W
Description
Condition
P0 key change interrupt flag
Reserved
6:0
Table 5-33 EIF register
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5.7. Reset Sources
5.7.1. Introduction
Reset (SW_RST), STOP mode Reset (STOP_RST), Flash Error
Reset (FLASH_ERR_RST), and missing system clock Reset
(MISS_CLK_RST). Figure 5 6 shows the block diagram of each
reset source.
There are eight types of reset sources for the GPM8F2702A
including Power-On Reset (POR), Low Voltage Reset (LVR), Pad
Reset (PAD_RST), Watchdog Timer Reset (WDT_RST), Software
LVR_POR
Macro
RESET_pad
PAD_RST
RST filter
LVR
POR
rst
WDT RST
SW RST
8051
STOP RST
FLASH ERR RST
clkrun
MISS CLK RST
Missing Clock
Detect
RESET
module
RESET_all
SYSRESET
Figure 5-6 Reset sources
5.7.2. Power-On Reset (POR)
chip is operating. If the power is lower than the specific level for a
specific period, the system reset will take place and go to initial
state. The trigger level of LVR can be selected by SYSCON[1:0].
Table 5-35 shows the three trigger levels in GPM8F2702A.
A POR is generated when VDD is rising from 0v. When VDD
rises to an acceptable level (~1.5V), the power on reset circuit will
starts a power-on sequence. After that, the system starts to
activate and will operate in target speed. The POR will reset
whole chip and registers.
5.7.4. Pad Reset (PAD_RST)
The GPM8F2702A provides an external pin to force the system
returning to its initial status when the RSTPIN_ENB bit of
CONFIG_BYTE is set to “0”. If the P32 is set as reset pin, its pull
low resistor is forced to enable automatically (the bit2 of
P3_PU/P3_PD is forced to 0/1). The RESET pin is high active as
shown in Figure 5-7. When the RESET pin equals to VDD,
system will be forced to enter reset state, execute instruction from
address 0x0000 and all registers go to default state.
5.7.3. Low Voltage Reset (LVR)
The on-chip Low Voltage Reset (LVR) circuitry forces the system
entering reset state when power supplying voltage falls below the
specific LVR trigger voltage. This function prevents MCU from
working at an invalid operating voltage range.
To enable or disable this function, SYSCON[7] can be set. If this
function is enabled, the LVR circuit will monitor power level while
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VDD
External
Internal
30pF
RESET pin
Figure 5-7 Pad reset circuit
CONFIG_BYTE
Bit
Address: 0x7FF (Program Memory)
CONFIG_BYTE Register
7
--
1
6
--
1
5
--
1
4
PUEN
1
3
--
1
2
1
--
1
0
Function
Default
RSTPIN_ENB
1
CODE_LOCK
1
Bit
Function
Type
Description
Condition
7:5
--
R
Reserved
GPIO IO pull up or low select bit
4
PUEN
R/W
0: set all GPIO as pull low after reset status
1: set all GPIO as pull high after reset status
3
2
--
R
Reserved
External reset pin enable bit
0: set P32 as external reset pin
1: set P32 as GPIO
RSTPIN_ENB
R/W
1
0
--
R
Reserved
CODE_LOCK
R/W
Program memory protection enable bit
0: CODE is locked
1: CODE is unlocked
Table 5-34 The CONFIG_BYTE register
5.7.5. Watchdog Timer Reset (WDT_RST)
On-chip watchdog circuitry makes the device entering reset state
when MCU goes into unknown state and has no watchdog cleared
information. This function prevents the MCU to be stuck in an
abnormal condition. The WDT can be enabled or disabled
through WDCON register bit 1. At any time prior to reaching its
user selected terminal value, software can set the Reset Watchdog
Timer (WDCON[0]) bit. If RWT is set before the timeout is
reached, the timer will start over. If timeout is reached without
RWT being set, the watchdog will reset the CPU. Hardware will
automatically clear RWT after software sets it. When the reset
occurs, the Watchdog Timer Reset Flag (RSTSTS[2]) will
automatically be set to indicate the cause of the reset, however
software must clear this bit manually. WDCON register is a timed
access register that prevent it from accidental writes. TA is
located at 0xEB. Correct sequence, 0xAA and 0x55, is required
before write to WDCON register. Reading from such register is
not protected. The Watchdog has four timeout selections based
on the system clock frequency. The selections are a pre-selected
number of clocks and can be set by CKCON[7:6]. Therefore, the
actual timeout interval is dependent on the SYSCLK frequency.
Figure 5-8 shows the block diagram of Watchdog timer.
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clk
217
23
23
23
WDT Clear
CKCON(0x8E)
RSTSTS (0x94)
512 CLK delay
WDCON (0xD8)
WDT RST
Figure 5-8 The block diagram of Watchdog timer
5.7.6. Other Reset Sources
Other reset sources includes Software Reset (SW_RST), STOP
mode Reset (STOP_RST), Flash Error Reset (FLASH_ERR_RST),
and missing system clock Reset (MISS_CLK_RST). Software
Reset is occurred when writing key codes, 0x3c and 0xc3, to TA
register (0xEB). The timing does not matter, but the key codes
must be written in order before SW reset take place. STOP mode
Reset is enabled by setting PCON[3] bit. This is the reset source
when system is reset from STOP mode.
address (>0x7FF).
The second error is when flash is
programmed in a wrong way or to program READONLY_PAGE.
The third error is to program CONFIG_BYTE. Each flash error
related reset source can be enabled or disabled by clearing or
setting a bit in the RSTCON (0x94) as shown in Table 5-40. The
corresponding flag when flash error reset occurs can be observed
in FLASHERRF register which is shown in Table 5-41. Missing
system clock Reset is the reset when system clock is missed over
4095 IOSC clocks if external crystal is utilized as clock source.
There are seven reset status flag can be monitored by RSTSTS
register which is shown as Table 5-42.
Flash Error Reset is the reset source when three flash related
errors are arisen. The first error is to access the exceeding ROM
SYSCON
Address: 0xAE
System Control Register
Bit
7
LVRENB
0
6
--
0
5
--
0
4
--
0
3
--
0
2
--
0
1
LVRSEL1
0
0
LVRSEL0
0
Function
Default
Key Code
0xFF, 0x00
Bit
Function
Type
Description
Condition
7
LVRENB
R/W
LVR enable control
0 : enable LVR function
1 : disable LVR function
Reserved
6:0
1:0
--
R/W
R/W
LVRSEL[1:0]
LVR trigger level select bit
LVRSEL[1:0]
LVR Trigger Level
<1.92V
00
01
10
11
<2.61V
<4.25V
<1.92V
Table 5-35 SYSCON register
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WDCON
Address: 0xD8
Watchdog Control Register
Bit
7
--
0
6
--
0
5
--
0
4
--
0
3
--
0
2
--
0
1
EWT
0
0
RWT
0
Function
Default
Key Code
0xAA, 0x55
Bit
7:2
1
Function
--
Type
Description
Condition
R/W
R/W
Reserved
EWT
Watchdog timer reset enable bit
0: Disable
1: Enable
0
RWT
R/W
Reset watchdog timer
0: NA
1: Reset
Table 5-36 WDCON register
TA
Address: 0xEB
Timed Access Protection Register
Bit
7
0
6
0
5
4
3
2
1
0
0
0
Function
Default
Timed Access protection register
0
0
0
0
Bit
Function
Type
Description
Condition
0
TA[7:0]
R/W
Timed Access protection register
Note: Some protected registers are needed to write correct key code to TA register before write data to them.
Table 5-37 TA register
CKCON
Bit
Address: 0x8E
Clock Control Register
7
WD1
0
6
WD0
0
5
--
0
4
T1M
0
3
T0M
0
2
--
0
1
--
0
0
--
1
Function
Default
Bit
Function
Type
Description
Condition
7:6
WD[1:0]
R/W
Watchdog timeout selection bits
WD[1:0]
Watchdog internal
Number of clocks
131072
00
217
220
223
226
01
1048576
10
8388608
11
67108864
5
4
--
R/W
R/W
Reserved
T1M
Division selection of the system clock that drives Timer 1
0: Timer 1 uses a divide-by-12 of the system clock frequency
1: Timer 1 uses a divide-by-4 of the system clock frequency
Division selection of the system clock that drives Timer 0
0: Timer 0 uses a divide-by-12 of the system clock frequency
1: Timer 0 uses a divide-by-4 of the system clock frequency
Reserved
3
T0M
--
R/W
R/W
2:0
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Table 5-38 CKCON register
PCON
Bit
Address: 0x87
Power Configuration Register
7
SMOD0
0
6
--
0
5
CPU_IDLE
0
4
PWE
0
3
2
--
0
1
STOP
0
0
--
0
Function
Default
STOP_RST_EN
0
Bit
7
Function
SMOD0
--
Type
R/W
R/W
R/W
Description
Condition
UART0 double baud rate bit when clocked by Timer1
Reserved
6
5
CPU_IDLE
IDLE mode enable bit
0: IDLE mode disabled ;
1: IDLE mode entered
4
3
PWE
R/W
R/W
Program Write Enable (PWE)
0: Disable Flash write activity during MOVX instruction
1: Enable Flash write activity during MOVX instruction
Wakeup state selection bit
0: Next instruction state after wakeup
1: Reset state afer wakeup
Reserved
STOP_RST_EN
2
1
--
R/W
R/W
STOP
STOP mode enable bit
0: Disabled
1: Enabled
0
--
R/W
Reserved
Table 5-39 PCON register
RSTCON
Address: 0x8F
Flash Error RESET Enable Control Register
Bit
7
6
5
4
3
--
0
2
--
0
1
MISS_CLK
_ENB
0
0
FLASH_ERR
__ENB
0
FLASH_FLOW
ERR_XROM
_ENB
Function
CB_P_ENB
0
--
0
_ENB
0
Default
0
Key Code
0x4F, 0x72, 0x7A
Bit
7
Function
CB_P_ENB
--
Type
Description
Condition
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CONFIG_BYTE program reset disable control bit
Reserved
6
5
4
3
2
1
0
FLASH_FLOW_ ENB
ERR_XROM_ENB
--
Error flash flow/ READONLY_PAGE program reset disable control bit
Error ROM address exceed reset disable control bit
Reserved
--
Reserved
MISS_CLK _ ENB
FLASH_ERR _ ENB
Miss clock reset disable control bit
Global Flash related error reset disable control bit
Table 5-40 RSTCON register
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FLASHERRF
Bit
Address: 0xA6
Flash Error RESET Status Flag Register
7
CB_P_F
0
6
--
0
5
4
3
--
0
2
--
0
1
--
0
0
--
0
Function
Default
FLASH_FLOW_F ERR_XROM_F
0
0
Bit
7
Function
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Condition
CB_P_F
Error CONFIG_BYTE program reset flag
Reserved
6
--
5
FLASH_FLOW_F
Error flash flow/READONLY_PAGE program reset flag
4
ERR_XROM_F
Error ROM address exceed reset flag
3
--
--
--
--
Reserved
2
Reserved
1
Reserved
0
Reserved
Table 5-41 FLASHERRF register
RSTSTS
Address: 0x94
RESET Status Flag Register
Bit
7
6
5
4
3
SW_RST
0
2
WDT_RST
0
1
0
MISS_CLK_
FLASH_ERR_
Function
Default
--
0
STOP_RST
0
LVR_RST
0
RAD_RST
RST
0
RST
0
0
Bit
7
Function
--
Type
Description
Condition
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
6
MISS_CLK_RST
STOP_RST
FLASH_ERR_RST
SW_RST
RESET from system clock missing clock
RESET from STOP mode
RESET from FLASH error
RESET from SW RST
5
4
3
2
WDT_RST
LVR_RST
RESET from WDT
1
RESET from LVR
0
PAD_RST
RESET from RESET PAD
Table 5-42 RSTSTS register
5.8. I/O Ports
5.8.1. Introduction
The GPM8F2702A has two ports, including standard Port 0, Port 3.
These port pins may be multiplexed with an alternate function for
the peripheral features on the device. In general, when an initial
reset state occurs, all ports are used as a general purpose input
port with open-drain structure. User can select IO as pull low or
pull high after reset status by setting the PUEN bit of
CONFIG_BYTE. All the ports can be programmable pull high/low
by PU and PD registers. The PU and PD registers of Port 0 are
controlled by 0x9A and 0x9B and the PU and PD registers of P3
are controlled by 0xA2 and 0xA3. Read and write accesses to
the I/O port are performed via their corresponding SFRs P0(0x80)
and P3(0xB0). When PU and PD are enabled at the same time,
the port can output high or low depending on the data. Table
5-43 and Table 5-44 show the truth table of analog pad and digital
pad respectively.
In GPM8F2702A, P0[7:0], P3[2:0] and
P3[7:5]can be analog pad for special function. P0[7:0] are used
for ADC input. P3[2:0] and P3[7:5] are used for compare input.
The detail descriptions of analog function are in corresponding
sections. The built-in pull high/low resister is 50KΩ typically. All
of port pins in GPM8F2702A are implemented with 30ns slew rate
control. Figure 5-9 and Figure 5-10 show the block diagrams of
analog pad and digital pad respectively.
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Preliminary
GPM8F2702A
PU
0
PD
0
DATA
ANAEN
PAD
0
1
0
1
0
1
0
1
x
0
0
0
0
0
0
0
0
1
Driving Low
Floating
0
0
0
1
Driving Low
Pull low
0
1
1
0
Illegal
1
0
Pull high
Driving Low
Driving High
Floating
1
1
1
1
x
x
Table 5-43 The truth table of analog pad
PU
PD
0
DATA
PAD
0
0
0
0
1
1
1
1
0
Driving Low
Floating
0
1
1
0
Driving Low
Pull low
1
1
0
0
Illegal
0
1
Pull high
1
0
Driving Low
Driving High
1
1
Table 5-44 The truth table of digital pad
ANAEN
ANAIP
DATA
PU
IP
50K
PD
50K
Figure 5-9 The block diagram of analog pad
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GPM8F2702A
DATA
PU
IP
50K
PD
50K
Figure 5-10 The block diagram of digital pad
CONFIG_BYTE
Bit
Address: 0x7FF (Program Memory)
CONFIG_BYTE Register
7
--
1
6
--
1
5
--
1
4
PUEN
1
3
--
1
2
1
--
1
0
Function
Default
RSTPIN_ENB
1
CODE_LOCK
1
Bit
Function
Type
Description
Condition
7:5
--
R
Reserved
GPIO IO pull up or low select bit
0: set all GPIO as pull low after reset status
1: set all GPIO as pull high after reset status
Reserved
4
3
2
PUEN
--
R/W
R
External reset pin enable bit
0: set P32 as external reset pin
1: set P32 as GPIO
RSTPIN_ENB
R/W
1
0
--
R
Reserved
CODE_LOCK
R/W
Program memory protection enable bit
0: CODE is locked
1: CODE is unlocked
Table 5-45 The CONFIG_BYTE register
P0
Address: 0x80
Port0 Register
Bit
7
--
1
6
--
1
5
P05
1
4
P04
1
3
P03
1
2
P02
1
1
0
P00
1
Function
Default
P01
1
Bit
7:6
5:0
Function
--
Type
R/W
R/W
Description
Condition
Reserved
Port0
P0[5:0]
Table 5-46 P0 register
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GPM8F2702A
P3
Address: 0xB0
Port3 Register
Bit
7
P37
1
6
P36
1
5
P35
1
4
P34
1
3
P33
1
2
P32
1
1
P31
1
0
P30
1
Function
Default
Bit
Function
Type
R/W
Description
Condition
7:0
P3[7:0]
Port3
Table 5-47 P3 register
P0_PU
Bit
Address: 0x9A
Port0 pull up configuration Register
7
--
0
6
--
0
5
4
3
2
1
0
Function
Default
P05_PU
Note1
P04_PU
Note1
P03_PU
Note1
P02_PU
Note1
P01_PU
Note1
P00_PU
Note1
Bit
7:6
5:0
Function
--
Type
R/W
R/W
Description
Condition
Reserved
P0_PU[5:0]
Port0 pull up control bits
0: floating
1: pull up
Table 5-48 P0_PU register
P0_PD
Address: 0x9B
Port0 pull down configuration Register
Bit
7
--
0
6
--
0
5
4
3
2
1
0
Function
Default
P05_PD
Note1
P04_PD
Note1
P03_PD
Note1
P02_PD
Note1
P01_PD
Note1
P00_PD
Note1
Bit
7:6
5:0
Function
--
Type
R/W
R/W
Description
Condition
Reserved
P0_PD[5:0]
Port0 pull down control bits
0: floating
1: pull down
Note1: If P0_PU and P0_PD are setting to ‘1’ simultaneously, P0 will be output mode
Note2: P00_PU ~ P05_PU/P00_PD~P05_PD are all “0” during reset status, and they can be set or clear by PUEN bit of CONFIG_BYTE after reset status.
Table 5-49 P0_PD register
P3_PU
Bit
Address: 0xA2
Port3 pull up configuration Register
7
6
5
4
3
2
1
0
Function
Default
P37_PU
Note1
P36_PU
Note1
P35_PU
Note1
P34_PU
Note1
P33_PU
Note1
P32_PU
Note1
P31_PU
Note1
P30_PU
Note1
Bit
Function
Type
R/W
Description
Condition
7:0
P3_PU[7:0]
Port3 pull up control bits
0: floating
1: pull up
Table 5-50 P3_PU register
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GPM8F2702A
P3_PD
Bit
Address: 0xA3
Port3 pull down configuration Register
7
6
5
4
3
2
1
0
Function
Default
P37_PD
Note1
P36_PD
Note1
P35_PD
Note1
P34_PD
Note1
P33_PD
Note1
P32_PD
Note2
P31_PD
Note1
P30_PD
Note1
Bit
Function
Type
R/W
Description
Condition
7:0
P3_PD[7:0]
Port3 pull down control bits
0: floating
1: pull down
Note1: If P3_PU and P3_PD are setting to ‘1’ simultaneously, P3 will be output mode
Note2: P30_PU~P37_PU/ P30_PD~P31_PD and P33_PD~P37_PD are all “0” during reset status, and they can be set or clear by setting the PUEN bit of
CONFIG_BYTE after reset status.
Note3: P32_PD is “1” during reset status, and it can be set or clear by setting the PUEN bit of CONFIG_BYTE after reset status. If the P32 is set as external
reset pin (RSTPIN_ENB bit of CONFIG_BYTE is set to “0”), P32_PU and P32_PD are force to “0” and “1” respectively.
Table 5-51 P3_PD register
ADAEN
Bit
Address: 0xF3
ADC Analog PAD Enable Register
7
--
0
6
--
0
5
P05_AEN
0
4
P04_AEN
0
3
P03_AEN
0
2
P02_AEN
0
1
P01_AEN
0
0
P00_AEN
0
Function
Default
Bit
Function
Type
Description
Condition
7:6
5
--
R/W
R/W
Reserved
P05_AEN
P05 analog PAD enable control bit
0: P05 can be I/O PAD
1: P05 can be analog PAD
P04 analog PAD enable control bit
0: P04 can be I/O PAD
4
3
2
1
0
P04_AEN
P03_AEN
P02_AEN
P01_AEN
P00_AEN
R/W
R/W
R/W
R/W
R/W
1: P04 can be analog PAD
P03 analog PAD enable control bit
0: P03 can be I/O PAD
1: P03 can be analog PAD
P02 analog PAD enable control bit
0: P02 can be I/O PAD
1: P02 can be analog PAD
P01 analog PAD enable control bit
0: P01 can be I/O PAD
1: P01 can be analog PAD
P00 analog PAD enable control bit
0: P00 can be I/O PAD
1: P00 can be analog PAD
Table 5-52 ADAEN register
IOSCCON
Bit
Address: 0xF9
IOSC Control Register
7
--
0
6
--
0
5
4
XTAL_EN
0
3
--
0
2
1
0
0
Function
Default
XTAL_PAD_EN
0
CLKDIV[2:0]
1
0
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GPM8F2702A
Bit
Function
Type
Description
7:6
5
--
R/W
R/W
Reserved
XTAL_PAD_EN
If using XTAL, XTAL_PAD_EN should be set to “1”
XTI and XTO can be analog PAD.
0: ROSC
4
XTAL_EN
R/W
1: XTAL
3
--
R/W
R/W
Reserved
2:0
CLK_DIV
System Clock source divider
CLK_DIV
000
Clock control
SYSCLK_SOURCE
SYSCLK_SOURCE/2
SYSCLK_SOURCE/4
SYSCLK_SOURCE/8
SYSCLK_SOURCE/16
SYSCLK_SOURCE/32
SYSCLK_SOURCE/64
SYSCLK_SOURCE/1.5
001
010
011
100
101
110
111
Table 5-53 The IOSCCON register
CMPAEN
Address: 0xBB
Comparator Analog PAD Enable Register
Bit
7
6
--
0
5
P37_AEN
0
4
P36_AEN
0
3
P35_AEN
0
2
P32_AEN
0
1
P31_AEN
0
0
P30_AEN
0
Function
--
0
Default
Bit
Function
Type
Description
Reserved
Condition
7:6
5
--
R/W
R/W
P37_AEN
P37 analog PAD enable control bit
0: P37 can be I/O PAD
1: P37 can be analog PAD
P36 analog PAD enable control bit
0: P36 can be I/O PAD
4
3
2
1
0
P36_AEN
P35_AEN
P32_AEN
P31_AEN
P30_AEN
R/W
R/W
R/W
R/W
R/W
1: P36 can be analog PAD
P35 analog PAD enable control bit
0: P35 can be I/O PAD
1: P35 can be analog PAD
P32 analog PAD enable control bit
0: P32 can be I/O PAD
1: P32 can be analog PAD
P31 analog PAD enable control bit
0: P31 can be I/O PAD
1: P31 can be analog PAD
P30 analog PAD enable control bit
0: P30 can be I/O PAD
1: P30 can be analog PAD
Table 5-54 CMPAEN register
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GPM8F2702A
5.9. Timer Module
5.9.1. Introduction
TL0(0x8A), TH1(0x8D), TL1(0x8B). Timers 0 and Timer 1 work in
the same three modes except for mode 3 and the related control
registers are TMOD(0x89), TCON(0x88) and CKCON(0x8E)
registers. In the timer mode, timer registers are incremented
every 4/12 SYSCLK periods depends on CKCON(0x8E) setting,
when appropriate timer is enabled. In the counter mode, the
timer registers are incremented every falling transition on theirs
corresponding input pins: T0 or T1. The input pins are sampled
every CLK period.
GPM8F2702A is equipped with three timers. They are Timer 0,
Timer 1 and Timer 2 respectively. In addition, Timer 2 also
features Compare/Capture/Reload function. All of these three
timers are up-count timers and 16-bit timer/counter. Each timer’s
function is described in the following sections.
5.9.2. Timer 0/1
Timer 0 and Timer 1 are fully compatible with the standard 8051
timers. Each timer consists of two 8-bit registers TH0(0x8C),
TH0
Address: 0x8C
Timer0 High Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TH0[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
TH0[7:0]
R/W
Timer 0 Load value – high byte
Table 5-55 TH0 register
TL0
Address: 0x8A
Timer0 Low Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TL0[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
TL0[7:0]
R/W
Timer 0 Load value – low byte
Table 5-56 TL0 register
TH1
Address: 0x8D
Timer1 High Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TH1[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
TH1[7:0]
R/W
Timer 1 Load value – high byte
Table 5-57 TH1 register
TL1
Address: 0x8B
Timer1 Low Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TL1[7:0]
0
0
0
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GPM8F2702A
Bit
Function
Type
Description
Timer 1 Load value – low byte
Table 5-58 TL1 register
Condition
7:0
TL1[7:0]
R/W
TMOD
Address: 0x89
Timer0/1 Control Mode Register
Bit
7
GATE1
0
6
CT1
0
5
M11
0
4
M10
0
3
GATE0
0
2
CT0
0
1
M01
0
0
M00
0
Function
Default
Bit
Function
Type
Description
Condition
7
GATE1
R/W
Gating control
0: Timer 1 enabled while TR1 control bit is set
1: Timer 1 enabled while GATE1 pin is high and TR1 control bit is set
Counter or timer select bit
6
CT1
R/W
0: Timer mode, internally clocked
1: Counter mode, Timer 1 clock source is from T1 pin
Mode select bits of timer 1, which is tabled as Table 5-60
Gating control
5:4
3
M1[1:0]
GATE0
R/W
R/W
0: Timer 0 enabled while TR0 control bit is set
1: Timer 0 enabled while GATE0 pin is high and TR0 control bit is set
Counter or timer select bit
2
CT0
R/W
R/W
0: Timer mode, internally clocked
1: Counter mode, Timer 0 clock source is from T0 pin
Mode select bits of timer 0, which is tabled as Table 5-60
1:0
M0[1:0]
Table 5-59 TMOD register
M1
M0
Mode
Function description
0
0
0
TH0/1 operates as 8-bit timer/counter with a divide by 32 prescaler served by lower
5-bit of TL0/1.
0
1
1
1
0
1
1
2
3
16-bit timer/counter. TH0/1 and TL0/1 are cascaded
TL0/1 operates as 8-bit timer/counter with 8-bit auto-reload by TH0/1
TL0 is configured as 8-bit timer/counter controlled by the standard Timer 0 bits. TH0
is an 8-bit timer controlled by the Timer 1 controls bits. Timer 1 holds its count.
Table 5-60 Four modes of Timer 0 and Timer 1
TCON
Address: 0x88
Timer0/1 Configuration Register
Bit
7
6
TR1
0
5
TF0
0
4
TR0
0
3
IE1
0
2
IT1
0
1
IE0
0
0
IT0
0
Function
Default
TF1
0
Bit
7
Function
TF1
Type
R/W
R/W
Description
Condition
Timer 1 interrupt (overflow) flag
Timer 1 run control bit
0: disabled
6
TR1
1: enabled
5
TF0
R/W
Timer 0 interrupt (overflow) flag
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GPM8F2702A
Bit
Function
Type
Description
Condition
4
TR0
R/W
Timer 0 run control bit
0: disabled
1: enabled
3
2
1
0
IE1
IT1
IE0
IT0
R/W
R/W
R/W
R/W
INT1 interrupt flag
INT1 level (at 0)/ edge (at 1) sensitivity
INT0 interrupt flag
INT0 level (at 0)/ edge (at 1) sensitivity
Table 5-61 TCON register
CKCON
Address: 0x8E
Clock Control Register
Bit
7
WD1
0
6
WD0
0
5
4
T1M
0
3
T0M
0
2
--
0
1
--
0
0
--
1
Function
Default
--
0
Bit
Function
Type
Description
Condition
7:6
WD[1:0]
R/W
Watchdog timeout selection bits
WD[1:0]
00
Watchdog internal
Number of clocks
131072
217
220
223
226
01
1048576
10
8388608
11
67108864
5
4
--
R/W
R/W
Reserved
T1M
Division selection of the system clock that drives Timer 1
0: Timer 1 uses a divide-by-12 of the system clock frequency
1: Timer 1 uses a divide-by-4 of the system clock frequency
Division selection of the system clock that drives Timer 0
0: Timer 0 uses a divide-by-12 of the system clock frequency
1: Timer 0 uses a divide-by-4 of the system clock frequency
Reserved
3
T0M
--
R/W
R/W
2:0
Table 5-62 CKCON register
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5.9.2.1. Timer 0: Mode 0(13-Bit Timer/Counter)
In this mode, Timer 0 register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, Timer 0 interrupt flag
TF0 is set. The counted input is enabled to the Timer 0 when
TR0(TCON[4]) = 1 and either GATE0(TMOD[3]) = 0 or GATE0
input pin(P36)= 1. (Setting GATE0(TMOD[3]) = 1 allows the Timer
0 to be controlled by external input GATE0(P36), to facilitate pulse
width measurements). The 13-bit register consists of all 8 bits of
TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are
indeterminate and should be ignored. Figure 5-11 shows the
block diagram of Timer 0 for Mode 0.
CKCON(0x8E)
TH0(0x8C)
TL0(0x8A)
SYSCLK/12
clock
division
SYSCLK/4
selection
timer
Interrupt request
counter
switch
13-bit upper counter
T0(P34)
TMOD(0x89)
TCON(0x88)
GATE0(P36)
Figure 5-11 The block diagram of Timer 0 for Mode 0
5.9.2.2. Timer 0: Mode 1(16-Bit Timer/Counter)
Mode 1 is the same as Mode 0, except that the timer register is
running with all 16 bits. The block diagram of Mode 1 is shown in
Figure 5-12.
CKCON(0x8E)
TH0(0x8C)
TL0(0x8A)
SYSCLK/12
clock
division
SYSCLK/4
selection
Interrupt request
timer
counter
16-bit upper counter
switch
T0(P34)
TMOD(0x89)
TCON(0x88)
GATE0(P36)
Figure 5-12 The block diagram of Timer 0 for Mode 1
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5.9.2.3. Timer 0: Mode 2(8-Bit Timer/Counter with Auto-reload Function)
Mode 2 configures the timer register as an 8-bit counter (TL0) with
not only sets TF0, but also reloads TL0 with the contents of TH0,
automatic reloads, as shown in Figure 5-13. Overflow from TL0
which is loaded by software. The reload leaves TH0 unchanged.
TL0(0x8A)
CKCON(0x8E)
SYSCLK/12
clock
division
SYSCLK/4
selection
timer
counter
switch
Interrupt request
8-bit upper counter
T0(P34)
TMOD(0x89)
TCON(0x88)
Set
TH0(0x8C)
GATE0(P36)
Figure 5-13 The block diagram of Timer 0 for Mode 2
5.9.2.4. Timer 0: Mode 3(Two 8-Bit Timers/Counters)
Timer 0 in Mode 3 establishes TL0 and TH0 as two separate
counters. The block diagram for Mode 3 on Timer 0 is shown in
Figure 5-14. TL0 uses the Timer 0 control bits: CT0, GATE0,
TR0, and TF0. TH0 is locked into a timer function and uses the
TR1 and TF1 flags from Timer 1 and controls Timer 1 interrupt.
Mode 3 is provided for applications requiring an extra 8-bit
timer/counter. When Timer 0 is in Mode 3, Timer 1 can be turned
off by switching it into its own Mode 3, or can still be used by the
serial channel as a baud rate generator, or in any application
where interrupt from Timer 1 is not required.
TH0(0x8C)
Interrupt request
8-bit upper counter
CKCON(0x8E)
TL0(0x8A)
TCON(0x88)
SYSCLK/12
clock
division
SYSCLK/4
selection
timer
counter
switch
8-bit upper counter
T0(P34)
Interrupt request
TMOD(0x89)
GATE0(P36)
Figure 5-14 The block diagram of Timer 0 for Mode 3
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GPM8F2702A
5.9.2.5. Timer 1: Mode 0(13-Bit Timer/Counter)
In this mode, the Timer 1 register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, Timer 1 interrupt flag
TF1 is set. The counted input is enabled to the Timer1 when
TR1(TCON[6]) = 1 and either GATE1(TMOD[7]) = 0 or GATE1
Timer1 to be controlled by external input GATE1(P37), to facilitate
pulse width measurements). The 13-bit register consists of all 8
bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1
are indeterminate and should be ignored. Figure 5-15 shows the
block diagram of Timer1 for Mode 0.
input pin(P37)= 1. (Setting GATE1(TMOD[7]) = 1 allows the
CKCON(0x8E)
TH1(0x8D)
TL1(0x8B)
SYSCLK/12
clock
division
SYSCLK/4
selection
timer
Interrupt request
counter
switch
13-bit upper counter
T1(P35)
TMOD(0x89)
TCON(0x88)
GATE1(P37)
Figure 5-15 The block diagram of Timer 1 for Mode 0
5.9.2.6. Timer 1: Mode 1(16-Bit Timer/Counter)
Mode 1 is the same as Mode 0, except that the timer register is
running with all 16 bits. The block diagram of Mode 1 is shown in
Figure 5-16.
CKCON(0x8E)
TH1(0x8D)
TL1(0x8B)
SYSCLK/12
clock
division
SYSCLK/4
selection
timer
counter
switch
Interrupt request
16-bit upper counter
T1(P35)
TMOD(0x89)
TCON(0x88)
GATE1(P37)
Figure 5-16 The block diagram of Timer 1 for Mode 1
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Preliminary
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5.9.2.7. Timer 1: Mode 2(8-Bit Timer/Counter with Auto-reload Function)
Mode 2 configures the timer register as an 8-bit counter (TL1) with
not only sets TF1, but also reloads TL1 with the contents of TH1,
automatic reloads, as shown in Figure 5-17. Overflow from TL1
which is loaded by software. The reload leaves TH1 unchanged.
CKCON(0x8E)
TL1(0x8B)
SYSCLK/12
clock
division
SYSCLK/4
selection
timer
Interrupt request
counter
switch
8-bit upper counter
T1(P35)
TMOD(0x89)
TCON(0x88)
Set
TH1(0x8D)
GATE1(P37)
Figure 5-17 The block diagram of Timer 1 for Mode 2
5.9.2.8. Timer 1: Mode 3
The additional Compare/Capture/Reload feature is one of the
most powerful peripheral units of the core. It can be used for all
kinds of digital signal generator and event capturing like pulse
generator, pulse width modulation, pulse width measuring etc.
Figure 5-18 shows the block diagram of compare/capture function
Timer 1 in Mode 3 is has no timer function. The effect is the
same as setting TR1=0.
5.9.3. Timer 2
for Timer 2.
The Timer 2, which is a 16-bit-wide register, can operate as timer.
T2CON(0xC8)
T2IF(0xC9)
Interrupt request
SYSCLK
16-bit upper counter
TL2
TH2
SYSCLK/2
Compare0
16-bit
16-bit
16-bit
16-bit
Compare1
Compare2
Compare3
P33
P34
P04
comparator
comparator
comparator
comparator
Capture0
Capture1
Capture2
Capture3
P05
CCL0/CCH0
CCL3/CCH3
CCL2/CCH2
CCL1/CCH1
CRCL/CRCH
Figure 5-18 The block diagram of compare/capture function for Timer 2
41
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Preliminary
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5.9.3.1. Timer Mode
5.9.3.2. Reload of Timer 2
In timer function, the count rate is derived from the oscillator
frequency. A prescaler offers the possibility of selecting a count
rate of 1 or 1/2 of an oscillator frequency. Thus, the 16-bit timer
register (consisted of TH2 and TL2) is either incremented in every 1
clock periods or in every 2 clock periods. The prescaler is selected
by bit T2PS of T2CON.
The reload mode for timer 2 is selected by T2R bit of T2CON.
When timer 2 rolls over from all 1’s to all 0’s, not only TF2 is set but
also timer 2 registers is loaded with the 16-bit value from CRC
register. Required CRC value can be preset by software. The
reload occurs in the same clock cycle in which TF2 is set, thus
overwriting the count value 0x0000.
16 - bit timer
TH2(0xCD)
TL2(0xCC)
T2IF(0xC9)
T2CON(0xC8)
Timer2
interrupt
request
CRCH(0xCB)
CRCL(0xCA)
Figure 5-19 The block diagram of reload function for Timer 2
5.9.3.3. Compare Functions
The 16-bit value stored in a compare/capture register is compared
with the contents of the timer register. If the count value in the
timer register matches the stored value, an appropriate output
signal is generated at a corresponding port pin, and an interrupt is
compare mode 0 and mode 1 are selected by bit T2CM0 and
T2CM1 in special function register T2CON. In all compare
modes, the new value arrives at certain pin of P3[4:3] and P0[5:4]
within the same clock cycle in which the internal compare signal is
activated.
requested.
The contents of a compare register can be
considered as time stamp at which a dedicated output reacts in a
predefined way (either with a positive or negative transition).
Variation of this time stamp somehow changes the wave of a
rectangular output signal at a port pin. This may - as a variation
of the duty cycle of a periodic signal - be used for pulse width
modulation as well as for a continually controlled generation of any
Compare Mode 0
In mode 0, upon matching the timer and compare register
contents, an output signal changes from low to high. It goes back
to a low level on timer overflow. Figure 5-20 shows a functional
diagram of a port register in compare mode 0. The port register
is directly controlled by the two signals: timer overflow and
compare.
kind of square waveforms.
Two compare modes are
implemented to cover a wide range of possible applications. The
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Compare Register CCx
Set Register
16-bit comparator
Reset Register
Q
Q
Q
Q
P0.4
P3.3
P0.5
P3.4
16 - bit timer2
TH2(0xCD)
TL2(0xCC)
T2IF(0xC9)
Overflow
Interrupt
Figure 5-20 The block diagram of compare mode 0 for Timer 2
Compare Mode 1
In compare mode 1, the 8-bit comparator is selected. Upon
matching the timer and compare register (CCLx) contents, an
output signal changes from low to high. It goes back to a low
level on timer overflow. In mode 1, the CCHx is used as reload
register of CCLx. It means that the CCLx register is loaded with
the 8-bit value from CCHx register. Figure 5-21 shows a
functional diagram of Timer 2 in compare mode 1.
Compare Register CCLx
Compare Register CCHx
Set Register
8-bit comparator
Reset Register
Q
Q
Q
Q
P0.5
P0.4
P3.4
P3.3
TH2(0xCD)
TL2(0xCC)
Interrupt
TL2
Overflow
TH2
Overflow
T2IF(0xC9)
Figure 5-21 The block diagram of compare mode 1 for Timer 2
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5.9.3.4. Capture Functions
Each of compare/capture registers include CC0, CC1, CC2 and
CC3 register can be used to latch the current 16-bit value of the
timer 2 registers TL2 and TH2. Two different modes are provided
for this function.
Capture Mode 1
In mode 1, a capture will occur upon writing to the low order byte
of the dedicated 16-bit capture register. This mode is provided to
allow software reading of timer 2 contents on-the fly. The capture
occurs in response to a write instruction to the low order byte of a
capture register. The write-to-register signal (e.g. write-to-CCL0)
is used to initiate a capture. The value written to the dedicated
capture register is irrelevant for this function. The timer 2
contents will be latched into the appropriate capture register in the
cycle following the write instruction. In this mode, no interrupt
request will be generated.
Capture Mode 0
In mode 0, an external event latches timer 2 contents to a
dedicated capture register. The external event causing a capture
is
z
for the CC registers 1 to 3: a positive transition on pins
CAPTURE1 to CAPTURE3
z
for the CC0 register: a positive or negative transition on the
CAPTURE0 pin, depending on the bit I3FR of T2CON. If
the I3FR flag is cleared, a capture occurs in response to a
negative transition; otherwise, a capture occurs in response
to a positive transition on CAPTURE0 pin.
Figure 5-22 and Figure 5-23 show functional diagrams of the timer
2 capture function.
T2IF(0xC9)
16 - bit timer
TH2(0xCD)
TL2(0xCC)
T2CON(0xC8)
Input clock
Overflow
Interrupt
mode0
mode1
0
1
CAPTURE0
(P33)
Capture
CCH0(0xC1)
CCL0(0xC0)
Write to CCL0
Figure 5-22 The block diagram of Timer 2 capture mode 0 for CCL0 and CCH0
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T2IF(0xC9)
16 - bit timer
TH2(0xCD)
TL2(0xCC)
Input clock
Overflow
Interrupt
mode0
mode1
CAPTUREx
(CAPTURE1=P34)
(CAPTURE2=P04)
(CAPTURE3=P05)
Capture
CCHx(0xC3,0xC5,0xC7)
CCLx(0xC2,0xC4,0xC6)
Write to CCLx
Figure 5-23 The block diagram of Timer 2 capture mode 0 for CCLx and CCHx (x=1, 2, 3)
5.9.3.5. Timer 2 Related Registers
T2CON
Address: 0xC8
Timer2 Configuration Register
Bit
7
T2PS
0
6
I3FR
0
5
T2CM1
0
4
T2R
0
3
--
0
2
T2CM0
0
1
--
0
0
Function
Default
T2I
0
Bit
7
Function
T2PS
Type
R/W
R/W
Description
Condition
Prescaler select bit
0: SYSCLK
1: SYSCLK/2
6
I3FR
Interrupt edge activity selection bit of compare 0 function in combination with
capture 0 function and register CRC
Capture 0:
0: capture to CRC register occurs on a positive transition of CAPTURE0 pin
1: capture to CRC register occurs on a positive transition of CAPTURE0 pin
Compare mode select bit for registers CRC, CC1, CC2, and CC3
0: Compare mode 1 is disable
5
T2CM1
R/W
1: Compare mode 1 is enable and compare mode 0 is force to disable
Timer 2 auto-reload mode enable bit
4:3
3
T2R
--
R/W
R/W
R/W
Reserved
2
T2CM0
Compare mode select bit for registers CRC, CC1, CC2, and CC3
0: compare mode 0 is enable
1: compare mode 0 is disable
1
--
R/W
Reserved
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GPM8F2702A
Bit
Function
Type
Description
Condition
0
T2I
R/W
Timer 2 input selection bit
0: No input selected, timer 2 is stopped
1: Timer function input frequency
SYSCLK (T2PS=0)
SYSCLK/2 (T2PS=1)
Table 5-63 T2CON register
CCEN
Address: 0xCE
Compare/Capture Enable Register
Bit
7
6
CML3
0
5
CMH2
0
4
CML2
0
3
CMH1
0
2
CML1
0
1
CMH0
0
0
CML0
0
Function
Default
CMH3
0
Bit
Function
Type
Description
Compare/capture mode for CC3 register
Condition
CMH3
CML3
Function
0
0
1
1
0
1
0
1
Compare/capture disabled
7:6
CM3[1:0]
CM2[1:0]
CM1[1:0]
CM0[1:0]
R/W
Capture on falling/rising edge of CAPTURE3 pin
Compare enabled
Capture on write operation into register CCL3
Compare/capture mode for CC2 register
CMH2
CML2
Function
0
0
1
1
0
1
0
1
Compare/capture disabled
5:4
3:2
1:0
R/W
R/W
R/W
Capture on falling/rising edge of CAPTURE2 pin
Compare enabled
Capture on write operation into register CCL2
Compare/capture mode for CC1 register
CMH1
CML1
Function
0
0
1
1
0
1
0
1
Compare/capture disabled
Capture on falling/rising edge of CAPTURE1 pin
Compare enabled
Capture on write operation into register CCL1
Compare/capture mode for CC0 register
CMH0
CML0
Function
0
0
1
1
0
1
0
1
Compare/capture disabled
Capture on falling/rising edge of CAPTURE0 pin
Compare enabled
Capture on write operation into register CCL0
Table 5-64 CCEN register
T2IF
Address: 0xC9
Timer 2 Interrupt Flag Register
Bit
7
--
0
6
--
0
5
--
0
4
--
0
3
--
0
2
--
0
1
--
0
0
TF2
0
Function
Default
Bit
Function
Type
Description
Condition
7:1
--
R/W
Reserved
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GPM8F2702A
Bit
Function
Type
Description
Condition
Timer 2 overflow flag
0
TF2
R/W
Cleared by the software
Table 5-65 T2IF register
CCH0
Address: 0xC1
Timer 2 CC0 Register - high byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CC0[15:8]
0
0
0
Bit
Function
Type
R/W
Description
Condition
7:0
CC0[15:8]
Timer2 compare/capture 0 - high byte
Table 5-66 The CCH0 register
CCL0
Address: 0xC0
Timer 2 CC0 Register - low byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CC0[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
CC0[7:0]
R/W
Timer2 compare/capture 0 - low byte
Table 5-67 The CCL0 register
CCH1
Address: 0xC3
Timer 2 CC1 Register - high byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CC1[15:8]
0
0
0
Bit
Function
Type
Description
Condition
7:0
CC1[15:8]
R/W
Timer2 compare/capture 1 - high byte
Table 5-68 The CCH1 register
CCL1
Address: 0xC2
Timer 2 CC1 Register - low byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CC1[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
CC1[7:0]
R/W
Timer2 compare/capture 1 - low byte
Table 5-69 The CCL1 register
CCH2
Address: 0xC5
Timer 2 CC2 Register - high byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CC2[15:8]
0
0
0
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Bit
Function
Type
Description
Timer2 compare/capture 2 - high byte
Table 5-70 The CCH2 register
Condition
7:0
CC2[15:8]
R/W
CCL2
Address: 0xC4
Timer 2 CC2 Register - low byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CC2[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
CC2[7:0]
R/W
Timer2 compare/capture 2 - low byte
Table 5-71 The CCL2 register
CCH3
Address: 0xC7
Timer 2 CC3 Register - high byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CC3[15:8]
0
0
0
Bit
Function
Type
Description
Condition
7:0
CC3[15:8]
R/W
Timer2 compare/capture 3 - high byte
Table 5-72 The CCH3 register
CCL3
Address: 0xC6
Timer 2 CC3 Register - low byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CC3[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
CC3[7:0]
R/W
Timer2 compare/capture 3 - low byte
Table 5-73 The CCL3 register
CRCH
Address: 0xCB
CRC Register - high byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
CRC[15:8]
0
0
0
Bit
Function
Type
Description
Condition
7:0
CRC[15:8]
R/W
CRC - high byte
Table 5-74 The CRCH register
CRCL
Address: 0xCA
CRC Register - low byte
Bit
7
0
6
0
5
4
0
3
2
1
0
0
Function
Default
CRC[7:0]
0
0
0
0
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GPM8F2702A
Bit
Function
Type
Description
Condition
7:0
CRC[7:0]
R/W
CRC - low byte
Table 5-75 The CRCL register
TH2
Address: 0xCD
Timer 2 High Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TH2[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
TH2[7:0]
R/W
Timer 2 Load value – high byte
Table 5-76 TH2 register
TL2
Address: 0xCC
Timer 2 Low Byte Register
Bit
7
0
6
0
5
4
0
3
2
1
0
0
0
Function
Default
TL2[7:0]
0
0
0
Bit
Function
Type
Description
Condition
7:0
TL2[7:0]
R/W
Timer 2 Load value – low byte
Table 5-77 TL2 register
5.10. UART0
and 0 in a data byte. With SM02 = 1, no slave will be interrupted
by a data byte. An address byte will interrupt all slaves. The
addressed slave will clear its SM02 bit and prepare to receive the
data bytes that will be coming. The slaves that were not being
addressed leave their SM02 set and ignoring the incoming data.
UART0 has the same functionality as a standard 8051 UART.
The serial port is full duplex, meaning it can transmit and receive
concurrently. It is reception with double-buffer, meaning it can
commence reception of a second byte before a previously
received byte has been read from the receive register. Writing to
SBUF0 loads the transmit register, and reading SBUF0 reads a
physically separate receive register. The serial port can operate
in 4 modes: one synchronous and three asynchronous modes.
5.10.1. UART0: Mode 0(Synchronous Shift register)
This mode is used as shift register IO control, and not for real
communication application. The baud rate is fixed at 1/12 of the
system clock frequency and TXD0(P31) output is a shift clock.
Eight bits are transmitted with LSB first. Reception is initialized
by setting the flags in SCON0 as follows: RI0 =0 and REN0 =1.
Figure 5-24 shows the timing diagram of UART0 transmission
mode 0.
Mode
2 and 3 has a special feature for multiprocessor
communications. This feature is enabled by setting SM02 bit in
SCON0 register. The master processor first sends out an
address byte, which identifies the target slave. An address byte
differs from a data byte in that the 9th bit is 1 in an address byte
TXD0(P31)
RXD0(P30)
D0
D1
D2
D3
D4
D5
D6
D7
Figure 5-24 The timing diagram of UART0 transmission mode 0
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5.10.2. UART0: Mode 1(8-Bit UART, Variable Baud Rate, Timer1 Clock Source)
In mode 1, TXD0 serves as serial output. 10 bits are transmitted:
a start bit (always 0), 8 data bits (LSB first), and a stop bit (always
1). On receiving, a start bit synchronizes the reception, 8 data
bits are available by reading SBUF0 and stop bit sets the flag
RB08 in the SFR SCON0. The baud rate is variable and
depends from Timer 1 mode. The SMOD0 bit of PCON (0x87) is
used to set the baud rate as T1ov/32 or T1ov/16. Figure 5-25 shows
the format of UART0 transmission mode 1.
TXD0(P31)
START
D0
D1
D2
D3
D4
D5
D6
D7
STOP
Figure 5-25 The format of UART0 transmission mode 1
5.10.3. UART0: Mode 2(9-Bit UART, Fixed Baud Rate)
This mode is similar to Mode 1 with two differences. The baud
rate is fixed at 1/32 or 1/64 of system clock frequency, and 11 bits
are transmitted or received: a start bit (0), 8 data bits (LSB first), a
programmable 9th bit, and a stop bit (1). The 9th bit can be used
to control the parity of the UART0 interface: at transmission, bit
TB08 in SCON0 is output as the 9th bit, and at receive, the 9th bit
affects RB08 in SCON0. Figure 5-26 shows the format of UART0
transmission mode 2.
TB8 STOP
D1
D2
D3
D4
D5
D6
D7
TXD0(P31)
START
D0
Figure 5-26 The format of UART0 transmission mode 2
5.10.4. UART0: Mode 3(9-Bit UART, Variable Baud Rate, Timer1 Clock Source)
The only difference between Mode 2 and Mode 3 is that the baud
rate is a variable in Mode 3. When REN0 =1 data receiving is
enabled. The baud rate is variable and depends from Timer 1
mode. The SMOD0 bit of PCON (0x87) is used to set the baud
rate as T1ov/32 or T1ov/16.
TB8 STOP
D1
D2
D3
D4
D5
D6
D7
TXD0(P31)
START
D0
Figure 5-27 The format of UART0 transmission mode 3
5.10.5. UART0 Related Registers
The UART0 related registers are: SBUF0(0x99), SCON0(0x98),
PCON(0x87), IE(0xA8) and IP(0xB8). The UART0 data buffer
(SBUF0) consists of two separate registers: transmit and receive
registers. A data writes into the SBUF0 sets this data in UART0
output register and starts a transmission. A data reads from
SBUF0, reads data from the UART0 receive register.
SBUF0
Bit
Address: 0x99
UART0 Buffer Register
7
0
6
0
5
4
0
3
2
1
0
0
Function
Default
SBUF0[7:0]
0
0
0
0
Bit
Function
Type
R/W
Description
Condition
2:0
SBUF0[7:0]
UART 0 buffer
Table 5-78 SBUF0 register
SCON0
Address: 0x98
UART0 Configuration Register
Bit
7
SM00
0
6
SM01
0
5
SM02
0
4
REN0
0
3
TB08
0
2
RB08
0
1
0
RI0
0
Function
Default
TI0
0
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Bit
7:6
5
Function
SM0[1:0]
SM02
Type
R/W
R/W
R/W
R/W
R/W
Description
Condition
Mode and baud rate setting which described as below table
Enables a multiprocessor communication feature
Enable serial reception.
4
REN0
3
TB08
The 9th transmitted data bit in Modes 2 and Mode 3
In Mode 0 this bit is not used
2
RB08
In Mode 1, if SM02 is 0, RB08 is the stop bit.
In Mode 2 and Mode 3, it is the 9th data bit received
UART0 transmitter interrupt flag
1
0
TI0
RI0
R/W
R/W
UART0 receiver interrupt flag
Table 5-79 SCON0 register
SM00
SM01
Mode
Function
Shift register
8-bit UART
9-bit UART
Baud Rate
0
0
1
0
1
0
0
1
2
SYSCLK/12
variable
SYSCLK/32(SMOD0=0)
SYSCLK/64(SMOD0=1)
variable
1
1
3
9-bit UART
Variable : in Mode1 and Mode 3
Timer
Baud Rate
Timer 1 overflow rate
Timer 1 overflow rate
T1ov/32 (SMOD0=0)
T1ov/16 (SMOD0=1)
PCON
Bit
Address: 0x87
Power Configuration Register
7
SMOD0
0
6
--
0
5
4
PWE
0
3
2
--
0
1
STOP
0
0
--
0
STOP_RST_
Function
Default
CPU_IDLE
0
EN
0
Bit
7
Function
SMOD0
--
Type
R/W
R/W
R/W
Description
Condition
UART0 double baud rate bit when clocked by Timer1
Reserved
6
5
CPU_IDLE
IDLE mode enable bit
0: IDLE mode disabled ;
1: IDLE mode entered
4
3
PWE
R/W
R/W
Program Write Enable (PWE)
0: Disable Flash write activity during MOVX instruction
1: Enable Flash write activity during MOVX instruction
Wakeup state selection bit
0: Next instruction state after wakeup
1: Reset state afer wakeup
Reserved
STOP_RST_EN
2
1
--
R/W
R/W
STOP
STOP mode enable bit
0: Disabled
1: Enabled
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Bit
Function
Type
Description
Condition
0
--
R/W
Reserved
Table 5-80 PCON register
IE
Address: 0xA8
Interrupt Enable Register
Bit
7
EA
0
6
--
0
5
ET2
0
4
ES0
0
3
ET1
0
2
EX1
0
1
ET0
0
0
EX0
0
Function
Default
Bit
7
Function
EA
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Condition
Enable global interrupts
Reserved
6
--
5
ET2
ES0
ET1
EX1
ET0
EX0
Enable Timer 2 interrupt
Enable UART0 interrupt
Enable Timer 1 interrupt
Enable INT1 interrupt
Enable Timer 0 interrupt
Enable INT0 interrupt
4
3
2
1
0
Table 5-81 IE register
IP
Address: 0xB8
Interrupt Priority Register
Bit
7
-
6
--
0
5
4
PS0
0
3
PT1
0
2
PX1
0
1
PT0
0
0
PX0
0
Function
Default
PT2
0
0
Bit
7:6
5
Function
--
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Condition
Reserved
PT2
PS0
PT1
PX1
PT0
PX0
Timer 2 priority level control (1: high level)
UART0 priority level control (1: high level)
Timer 1 priority level control (1: high level)
INT1 priority level control (1: high level)
Timer 0 priority level control (1: high level)
INT0 priority level control (1: high level)
Table 5-82 IP register
4
3
2
1
0
5.11. ADC
5.11.1. ADC Control
There is one Analog-to-Digital-Converter (ADC) in GPM8F2702A.
It provides general purpose usages such as voice record feature
and any other analog functions.
Seven channels of 12-bit SAR ADC are built in GPM8F2702A.
They are defined as general-purpose line input P00~P05 and one
internal 1.23V. These six channels are very suitable for system
voltage detection and other general-purpose usages. Figure
5-28 and Figure 5-29 show the related timing and block diagrams.
6+1 Channels, 12-bit resolution ADC
Supports programming sample hold and ADC clock function
Supports ADC output window detection
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GPM8F2702A
ADEN
ADCLK
SHCLK
READY
ADCLK=SYSCLK/8 ~SYSCLK/64=1T
2/4/8/16T
> 10T or 14T
Figure 5-28 The timing diagram of ADC control
VDD VSS
P00
P01
P02
P03
P04
P05
READY
1.23V
ADO[11:0]
ADC
CH_SEL[2:0]
ADEN
SHCLK
ADCLK
Figure 5-29 The block diagram of ADC
5.11.2. ADC Related Register
ADCON
Address: 0xF1
ADC Control Register
Bit
7
WINF
0
6
READYF
0
5
WIN_SEL
0
4
WINIE
0
3
ADIE
0
2
--
0
1
PSIDLE
0
0
START
0
Function
Default
Bit
Function
Type
Description
Condition
7
6
5
WINF
R/W
R/W
R/W
Window detect flag
READYF
WIN_SEL
ADC transfer ready flag
ADC output window selection
0: ADC output is between ADLB and ADUB
1: ADC output isn’t between ADLB and ADUB
ADC window interrupt enable
4
3
WINIE
ADIE
R/W
R/W
ADC transfer ready interrupt enable
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GPM8F2702A
Bit
Function
Type
Description
Condition
2
1
0
--
R/W
R/W
R/W
Reserved
PSIDLE
START
IDLE mode enable bit (ADC start transfer with suspending CPU clock)
ADC start transfer control
Table 5-83 ADCON register
ADCFG
Address: 0xF2
ADC Configuration Register
Bit
7
--
0
6
0
5
4
3
2
1
0
0
0
Function
Default
CH_SEL[2:0]
0
SHCLK[1:0]
ADCLK[1:0]
0
0
0
Bit
Function
Type
Description
Condition
7
--
R/W
R/W
Reserved
6:4
CH_SEL[2:0]
ADC channel selection
0: P00 is selected
1: P01 is selected
2: P02 is selected
3: P03 is selected
4: P04 is selected
5: P05 is selected
6: Internal 1.23V is selected
7: Reserved
3:2
1:0
SHCLK[1:0]
R/W
R/W
ADC sample and hold period
0: 2T of ADCLK
1: 4T of ADCLK
2: 8T of ADCLK
3: 16T of ADCLK
ADCLK
ADC clock selection
0: ADC conversion clock = 2MHz (FOSC /8)
1: ADC conversion clock = 1MHz (FOSC /16)
2: ADC conversion clock = 512KHz (FOSC /32)
3: ADC conversion clock = 256KHz (FOSC /64)
Table 5-84 ADCFG register
ADAEN
Address: 0xF3
ADC Analog PAD Enable Register
Bit
7
--
0
6
--
0
5
P05_AEN
0
4
P04_AEN
0
3
P03_AEN
0
2
P02_AEN
0
1
0
P00_AEN
0
Function
Default
P01_AEN
0
Bit
Function
Type
Description
Condition
7:6
5
--
R/W
R/W
Reserved
P05_AEN
P05 analog PAD enable control bit
0: P05 can be I/O PAD
1: P05 can be analog PAD
P04 analog PAD enable control bit
0: P04 can be I/O PAD
4
P04_AEN
R/W
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GPM8F2702A
Bit
Function
Type
Description
1: P04 can be analog PAD
Condition
3
P03_AEN
R/W
P03 analog PAD enable control bit
0: P03 can be I/O PAD
1: P03 can be analog PAD
P02 analog PAD enable control bit
0: P02 can be I/O PAD
2
1
0
P02_AEN
P01_AEN
P00_AEN
R/W
R/W
R/W
1: P02 can be analog PAD
P01 analog PAD enable control bit
0: P01 can be I/O PAD
1: P01 can be analog PAD
P00 analog PAD enable control bit
0: P00 can be I/O PAD
1: P00 can be analog PAD
Table 5-85 ADAEN register
ADOL
Address: 0xF4
ADC Output Low Data Register
Bit
7
0
6
0
5
4
0
3
--
0
2
--
0
1
--
0
0
--
0
Function
Default
ADO[3:0]
0
Bit
7:4
3:0
Function
--
Type
R/W
R/W
Description
Condition
Reserved
ADC output data[3:0]
Table 5-86 ADOL register
ADO[3:0]
ADOH
Address: 0xF5
ADC Output High Data Register
Bit
7
1
6
0
5
4
0
3
2
1
0
0
0
Function
Default
ADO[11:4]
0
0
0
Bit
Function
Type
Description
Condition
7:0
ADO[11:4]
R/W
ADC output data[11:4]
Table 5-87 ADOH register
ADLB
Address: 0xF6
ADC Low Boundary register
Bit
7
0
6
5
4
0
3
2
1
0
Function
Default
ADLB[7:0]
0
0
0
0
0
0
Bit
Function
Type
Description
Condition
7:0
ADLB
R/W
ADC low boundary, compare to ADO[11:4]
Table 5-88 ADLB register
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GPM8F2702A
ADUB
Bit
Address: 0xF7
ADC UP Boundary register
7
0
6
0
5
4
0
3
ADUB[7:0]
0
2
1
0
0
0
Function
Default
0
0
Bit
Function
Type
Description
Condition
7:0
ADUB
R/W
ADC up boundary, compare to ADO[11:4]
Table 5-89 ADUB register
5.12. Built-in Comparators
In GPM8F2702A, built-in two comparators are very suitable for
voltage detection and other general-purpose usages and the
related control registers are CMPICON, CMPAEN, VCMPCON
and CCMPCON. Figure 5-30 shows the diagram of built-in
comparators. The VCMPIE and CCMPIE bits are used to enable
voltage comparator (VCMP) interrupt and current comparator
(CCMP) interrupt respectively. VCMPIF and CCMPIF are their
corresponding interrupt flags. Any transition from low to high on
output of VCMP/CCMP (VFOUT/CFOUT), the VCMPIF/CCMPIF is
set. The input of VCMP and CCMP can be selected by
VFSEL[1:0] and CFSEL [1:0] bits respectively. User can select
reference
voltage
of
VCMP/CCMP
by
VCMP_SEL[3:0]/CCMP_SEL[3:0]. The output of VCMP/CCMP is
shown in VFOUT/CFOUT bit. The detailed description is shown
in Table 5-92 and Table 5-93.
VCMPCON (0xBC)
VF0 (P30)
VVP
VF1 (P32)
VF2 (P37)
+
-
VFOUT
VCMP
CF2/VF3 (P36)
CF1 (P35)
CF0 (P31)
CVP
+
-
CFOUT
CCMP
VCMP_SEL[3:0]
1.23V
0
1
.
.
.
.
1.23*16/16
1.23*15/16
.
.
.
.
.
.
.
.
.
.
14
CCMPCON (0xBD)
15
.
.
0
1
1.23*2/16
.
.
.
.
.
14
15
CCMP_SEL[3:0]
Figure 5-30 Built-in comparator diagram
56
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GPM8F2702A
CMPICON
Bit
Address: 0xBA
Comparator Interrupt Control Register
7
--
0
6
--
0
5
--
0
4
--
0
3
CCMPIF
0
2
VCMPIF
0
1
CCMPIE
0
0
VCMPIE
0
Function
Default
Bit
Function
Type
Description
Condition
7:4
3
--
R/W
R/W
Reserved
CCMPIF
Current comparator (CCMP) interrupt flag
Cleared by the software
Set as CFOUT form low to high
Voltage comparator (VCMP) interrupt flag
Cleared by the software
2
1
0
VCMPIF
CCMPIE
VCMPIE
R/W
R/W
R/W
Set as VFOUT form low to high
Enable Current comparator (CCMP) interrupt
0: CCMP interrupt disable
1: CCMP interrupt enable
Enable Voltage comparator (VCMP) interrupt
0: VCMP interrupt disable
1: VCMP interrupt enable
Table 5-90 CMPICON register
CMPAEN
Bit
Address: 0xBB
Comparator Analog PAD Enable Register
7
--
0
6
--
0
5
P37_AEN
0
4
P36_AEN
0
3
P35_AEN
0
2
P32_AEN
0
1
P31_AEN
0
0
P30_AEN
0
Function
Default
Bit
Function
Type
Description
Condition
7:6
5
--
R/W
R/W
Reserved
P37_AEN
P35 analog PAD enable control bit
0: P35 can be I/O PAD
1: P35 can be analog PAD
P36 analog PAD enable control bit
0: P36 can be I/O PAD
4
3
2
1
0
P36_AEN
P35_AEN
P32_AEN
P31_AEN
P30_AEN
R/W
R/W
R/W
R/W
R/W
1: P36 can be analog PAD
P35 analog PAD enable control bit
0: P35 can be I/O PAD
1: P35 can be analog PAD
P32 analog PAD enable control bit
0: P32 can be I/O PAD
1: P32 can be analog PAD
P31 analog PAD enable control bit
0: P31 can be I/O PAD
1: P31 can be analog PAD
P30 analog PAD enable control bit
0: P30 can be I/O PAD
1: P30 can be analog PAD
Table 5-91 CMPAEN register
57
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GPM8F2702A
VCMPCON
Bit
Address: 0xBC
Voltage Comparator Control Register
7
VFOUT
0
6
5
4
3
2
VFSEL1
0
1
VFSEL0
0
0
VCMPEN
0
Function
Default
VCMP_SEL3 VCMP_SEL2 VCMP_SEL1 VCMP_SEL0
0
0
0
0
Bit
Function
Type
Description
Condition
7
VFOUT
R/W
R/W
Voltage comparator output
6:3
VCMP_SEL[3:0]
Reference voltage select bit
VCMP_SEL
0000
0001
0010
0011
0100
0101
0110
0111
Reference Voltage
select CVP input
select 1.23V * 2/16
select 1.23V * 3/16
select 1.23V * 4/16
select 1.23V * 5/16
select 1.23V * 6/16
select 1.23V * 7/16
select 1.23V * 8/16
select 1.23V * 9/16
select 1.23V * 10/16
select 1.23V * 11/16
select 1.23V * 12/16
select 1.23V * 13/16
select 1.23V * 14/16
select 1.23V * 15/16
select 1.23V * 16/16
1000
1001
1010
1011
1100
1101
1110
1111
2:1
VFSEL[1:0]
R/W
Voltage comparator input select bits
VFSEL
VCMP input
00
select VF0 (P30)
select VF1 (P32)
select VF2 (P37)
select VF3 (P36)
01
10
11
0
VCMPEN
R/W
Voltage comparator enable bit
0: VCMP Disable
1: VCMP Enable
Table 5-92 VCMPCON register
CCMPCON
Bit
Address: 0xBD
Current Comparator Control Register
7
CFOUT
0
6
5
4
3
2
CFSEL1
0
1
CFSEL0
0
0
CCMPEN
0
Function
Default
CCMP_SEL3 CCMP_SEL2 CCMP_SEL1 CCMP_SEL0
0
0
0
0
Bit
Function
Type
Description
Condition
7
CFOUT
R/W
Current comparator output
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GPM8F2702A
Bit
Function
Type
Description
Reference voltage select bit
Condition
6:3
CCMP_SEL[3:0]
R/W
CCMP_SEL
0000
0001
0010
0011
0100
0101
0110
0111
Reference Voltage
select VVP input
select 1.23V * 2/16
select 1.23V * 3/16
select 1.23V * 4/16
select 1.23V * 5/16
select 1.23V * 6/16
select 1.23V * 7/16
select 1.23V * 8/16
select 1.23V * 9/16
select 1.23V * 10/16
select 1.23V * 11/16
select 1.23V * 12/16
select 1.23V * 13/16
select 1.23V * 14/16
select 1.23V * 15/16
select 1.23V * 16/16
1000
1001
1010
1011
1100
1101
1110
1111
2:1
CFSEL[1:0]
R/W
Current comparator input select bits
CFSEL
CCMP input
00
select CF0 (P31)
select CF1 (P35)
select CF2 (P36)
select CF0 (P31)
01
10
11
0
CCMPEN
R/W
Current comparator enable bit
0: CCMP Disable
1: CCMP Enable
Table 5-93 CCMPCON register
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GPM8F2702A
5.13. Alphabetical List of Instruction Set
5.13.1. Arithmetic Operations
Mnemonic
ADD A,Rn
ADD A,direct
ADD A,@Ri
ADD A,#data
ADDC A,Rn
ADDC A,direct
ADDC A,@Ri
ADDC A,#data
SUBB A,Rn
SUBB A,direct
SUBB A,@Ri
SUBB A,#data
INC A
Description
Code
0x28-0x2F
0x25
Bytes
Cycles
Add register to accumulator
Add direct byte to accumulator
Add indirect RAM to accumulator
Add immediate data to accumulator
Add register to accumulator with carry flag
Add direct byte to A with carry flag
Add indirect RAM to A with carry flag
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment accumulator
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
1
2
1
1
1
1
1
2
2
2
1
2
2
2
1
2
2
2
1
2
3
3
1
2
3
3
1
2
6
3
0x26-0x27
0x24
0x38-0x3F
0x35
0x36-0x37
0x34
0x98-0x9F
0x95
0x96-0x97
0x94
0x04
INC Rn
Increment register
0x08-0x0F
0x05
INC direct
INC @Ri
Increment direct byte
Increment indirect RAM
0x06-0x07
0x14
DEC A
Decrement accumulator
DEC Rn
Decrement register
0x18-0x1F
0x15
DEC direct
DEC @Ri
INC DPTR
MUL A,B
Decrement direct byte
Decrement indirect RAM
0x16-0x17
0xA3
Increment data pointer
Multiply A and B
0xA4
DIV A,B
Divide A by B
0x84
DA A
Decimal adjust accumulator
0xD4
5.13.2. Logic Operations
Mnemonic
Description
Code
0x58-0x5F
0x55
Bytes
Cycles
ANL A,Rn
AND register to accumulator
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
1
2
2
2
3
3
1
2
2
2
3
3
1
2
2
ANL A,direct
ANL A,@Ri
ANL A,#data
ANL direct,A
ANL direct,#data
ORL A,Rn
AND direct byte to accumulator
AND indirect RAM to accumulator
AND immediate data to accumulator
AND accumulator to direct byte
AND immediate data to direct byte
OR register to accumulator
0x56-0x57
0x54
0x52
0x53
0x48-0x4F
0x45
ORL A,direct
ORL A,@Ri
ORL A,#data
ORL direct,A
ORL direct,#data
XRL A,Rn
OR direct byte to accumulator
OR indirect RAM to accumulator
OR immediate data to accumulator
OR accumulator to direct byte
0x46-0x47
0x44
0x42
OR immediate data to direct byte
Exclusive OR register to accumulator
Exclusive OR direct byte to accumulator
Exclusive OR indirect RAM to accumulator
0x43
0x68-0x6F
0x65
XRL A,direct
XRL A,@Ri
0x66-0x67
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GPM8F2702A
Mnemonic
XRL A,#data
XRL direct,A
XRL direct,#data
CLR A
Description
Code
0x64
0x62
0x63
0xE4
0xF4
0x23
0x33
0x03
0x13
0xC4
Bytes
Cycles
Exclusive OR immediate data to accumulator
Exclusive OR accumulator to direct byte
Exclusive OR immediate data to direct byte
Clear accumulator
2
2
3
1
1
1
1
1
1
1
2
3
3
1
1
1
1
1
1
1
CPL A
Complement accumulator
RL A
Rotate accumulator left
RLC A
Rotate accumulator left through carry
Rotate accumulator right
RR A
RRC A
Rotate accumulator right through carry
Swap nibbles within the accumulator
SWAP A
5.13.3. Boolean Operations
Mnemonic
CLR C
Description
Code
0xC3
0xC2
0xD3
0xD2
0xB3
0xB2
0x82
0xB0
0x72
0xA0
0xA2
0x92
Bytes
Cycles
Clear carry flag
1
2
1
2
1
2
2
2
2
2
2
2
1
3
1
3
1
3
2
2
2
2
2
3
CLR bit
Clear direct bit
SETB C
Set carry flag
SETB bit
CPL C
Set direct bit
Complement carry flag
Complement direct bit
AND direct bit to carry flag
AND complement of direct bit to carry
OR direct bit to carry flag
OR complement of direct bit to carry
Move direct bit to carry flag
Move carry flag to direct bit
CPL bit
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
MOV bit,C
5.13.4. Data Transfers
Mnemonic
Description
Code
Bytes
Cycles
MOV A,Rn
Move register to accumulator
0xE8-0xEF
0xE5
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
2
2
2
1
3
2
2
2
3
3
3
2
3
2
3
MOV A,direct
Move direct byte to accumulator
Move indirect RAM to accumulator
Move immediate data to accumulator
Move accumulator to register
MOV A,@Ri
0xE6-0xE7
0x74
MOV A,#data
MOV Rn,A
0xF8-0xFF
0xA8-0xAF
0x78-0x7F
0xF5
MOV Rn,direct
MOV Rn,#data
MOV direct,A
MOV direct,Rn
MOV direct1,direct2
MOV direct,@Ri
MOV direct,#data
MOV @Ri,A
Move direct byte to register
Move immediate data to register
Move accumulator to direct byte
Move register to direct byte
0x88-0x8F
0x85
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate data to direct byte
Move accumulator to indirect RAM
Move direct byte to indirect RAM
Move immediate data to indirect RAM
Load 16-bit constant into active DPH and DPL in LARGE mode
0x86-0x87
0x75
0xF6-0xF7
0xA6-0xA7
0x76-0x77
0x90
MOV @Ri,direct
MOV @Ri,#data
MOV DPTR,#data16
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GPM8F2702A
Mnemonic
Description
Code
0x93
0x83
Bytes
Cycles
MOVC A,@A+DPTR
MOVC A,@A+PC
Move code byte relative to DPTR to accumulator
Move code byte relative to PC to accumulator
1
1
5
4
XDM
3*
3
MOVX A,@Ri
Move external RAM (8-bit address) to A
Move external RAM (16-bit address) to A
0xE2-0xE3
0xE0
1
1
SXDM
XDM
2*
2
MOVX A,@DPTR
SXDM
CODE inside ROM/RAM
Other cases
4*
5*
Move A to external XDM (8-bit address)
Move A to external SXDM (8-bit address)
MOVX @Ri,A
0xF2-0xF3
0xF0
1
1
All cases
3
CODE inside ROM/RAM
Other cases
3*
4*
2
Move A to external XDM (16-bit address)
MOVX @DPTR,A
Move A to external SXDM (16-bit address)
Push direct byte onto IDM stack
All cases
PUSH direct
POP direct
XCH A,Rn
0xC0
0xD0
2
2
1
2
1
1
3
Pop direct byte from IDM stack
2
Exchange register with accumulator
Exchange direct byte with accumulator
Exchange indirect RAM with accumulator
Exchange low-order nibble indirect RAM with A
0xC8-0xCF
0xC5
2
XCH A,direct
XCH A,@Ri
XCHD A,@Ri
3
0xC6-0xC7
0xD6-0xD7
3
3
5.13.5. Program Branches
Mnemonic
ACALL addr11
LCALL addr16
RET
Description
Code
Bytes
Cycles
Absolute subroutine call
0x11-0xF1
0x12
2
3
1
1
2
3
2
1
2
2
2
2
3
3
3
3
3
3
3
2
3
1
4
4
4
4
3
4
3
5
4
4
3
3
5
5
5
5
4
4
5
4
5
1
Long subroutine call
Return from subroutine
0x22
RETI
Return from interrupt
0x32
AJMP addr11
LJMP addr16
SJMP rel
Absolute jump
0x01-0xE1
0x02
Long jump
Short jump (relative address)
Jump indirect relative to the DPTR
Jump if accumulator is zero
Jump if accumulator is not zero
Jump if carry flag is set
0x80
JMP @A+DPTR
JZ rel
0x73
0x60
JNZ rel
0x70
JC rel
0x40
JNC
Jump if carry flag is not set
0x50
JB bit,rel
Jump if direct bit is set
0x20
JNB bit,rel
Jump if direct bit is not set
0x30
JBC bit,direct rel
CJNE A,direct rel
CJNE A,#data rel
CJNE Rn,#data rel
CJNE @Ri,#data rel
DJNZ Rn,rel
DJNZ direct,rel
NOP
Jump if direct bit is set and clear bit
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to reg. and jump if not equal
Compare immediate to ind. and jump if not equal
Decrement register and jump if not zero
Decrement direct byte and jump if not zero
No operation
0x10
0xB5
0xB4
0xB8-0xBF
0xB6-0xB7
0xD8-0xDF
0xD5
0x00
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Preliminary Version: 0.2
Preliminary
GPM8F2702A
6. ELECTRICAL CHARACTERISTICS
6.1. Absolute Maximum Ratings
Characteristics
Symbol
Ratings
DC Supply Voltage
V+
VIN
< 6.0V
-0.5V to V+ + 0.5V
-40℃ to +85℃
70mA
Input Voltage Range
Operating Temperature
VDD Total MAX Current
VSS Total MAX Current
TA
IVDDM
IVSSM
120mA
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational
conditions see AC/DC Electrical Characteristics.
6.2. AC Characteristics (TA = 25℃)
Limit
Characteristics
Symbol
Unit
Condition
Min.
Typ.
Max.
INOSC Frequency
FOSC
16/8/4×(1-2%)
16/8/4
16/8/4×(1+2%)
MHz
VDD = 2.0~5.5V
6.3. DC Characteristics (VDD = 5V, TA = 25℃)
Limit
Typ.
Characteristics
Symbol
Unit
Condition
Min.
Max.
Operating Voltage
Operating Current
Standby Current
VDD
IOP
VLVR
5
25
2.0
-
5.5
V
-
-
mA FCPU = 16MHz @ 5.5V, no load
ISTBY
VIH
-
5.0
uA
V
VDD = 5.5V
Input High Level
0.7VDD
-
0.3VDD
-
VDD = 5.0V
Input Low Level
VIL
-
-
V
VDD = 5.0V
Output High Level
Output Low Level
Input Pull High Resistor
Input Pull High Resistor
Low Voltage Reset
VOH
VOL
RPH
RPL
0.8VDD
-
V
IOH = -8mA at VDD = 5.0V
IOL = 20mA at VDD = 5.0V
VDD = 5.0V
-
30
-
0.2VDD
70
V
50
50
KΩ
KΩ
30
70
VDD = 5.0V
1.92/2.61/4.5
×(1-5%)
1.92/2.61/4.25
×(1+5%)
VLVR
1.92/2.61/4.25
V
6.4. ADC Characteristics
Characteristics
Resolution
Symbol
Min.
Typ.
Max.
Unit
Bit
Condition
-
EINL
EDNL
-
-
-
12
Integral Linearity Error
Differential Linearity Error
No Missing Code
-
±2
±3
LSB
LSB
bits
V
VDD =5V
VDD =5V
-
±2
±3
-
12
-
VDD =2.0~5.5V
ADC input voltage range
ADC Operating current
ADC clock period
VADCIN
IAD
0
-
VDD
-
-
1.5
mA
us
VDD =5.5V
TAD
TCON
-
0.5
-
-
ADC Conversion time
Input channel
16
-
-
-
TAD
SHCLK = 2TAD
-
6+1
channel
V
Internal 1.23V
-
1.23×(1-5%)
1.23
1.23×(1+5%)
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Preliminary Version: 0.2
Preliminary
GPM8F2702A
6.5. Comparator Characteristics
Characteristics
Input Offset
Symbol
Min.
Typ.
Max.
Unit
mV
MHz
uA
Condition
Voff
BW
Icmp
-
-
-
1
10
Unit Gain Bandwidth
Typical Active Current
Internal 1.23V
-
-
VDD =5V
-
-
100
VDD =5.5V
1.23×(1-5%)
1.23
1.23×(1+5%)
V
© Generalplus Technology Inc.
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Preliminary Version: 0.2
Preliminary
GPM8F2702A
7. PACKAGE INFORMATION
7.1. Ordering Information
Product Number
Package Type
Green Package
GPM8F2702A- HS03x
Note1: Package form number (x = 1 - 9, serial number).
7.2. Package Information
SOP 16
Symbols
Min.
0.053
0.004
0.386
0.150
0.228
0.016
0
Max.
0.069
0.010
0.394
0.157
0.244
0.050
8
A
A1
D
E
H
L
θ°
Unit: Inch
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Preliminary Version: 0.2
Preliminary
GPM8F2702A
8.DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
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Preliminary Version: 0.2
Preliminary
GPM8F2702A
9. REVISION HISTORY
Date
Revision #
Description
Page
65
Dec. 16, 2011
Dec. 02, 2010
0.2
0.1
Add 7.2 Package Information.
Original
71
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Preliminary Version: 0.2
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