GPR25L12806F-QS13x [GENERALPLUS]
3V, 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY;
| 型号： | GPR25L12806F-QS13x |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 3V, 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY |
| 文件： | 总50页 (文件大小：968K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3V, 128M-BIT [x 1/x 2/x 4] CMOS
MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
Jul. 30, 2018
Version 1.0
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPR25L12806F
Contents
1. FEATURES ..................................................................................................................................................4
2. GENERAL DESCRIPTION ..........................................................................................................................5
3. MEMORY ORGANIZATION.........................................................................................................................7
4. DEVICE OPERATION..................................................................................................................................8
5. DATA PROTECTION .................................................................................................................................10
6. STATUS REGISTER ..................................................................................................................................12
7. COMMANDS DESCRIPTION ....................................................................................................................14
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
WRITE ENABLE (WREN) (06H).............................................................................................................17
WRITE DISABLE (WRDI) (04H)..............................................................................................................17
WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ........................................................................17
READ STATUS REGISTER (RDSR) (05H OR 35H OR 15H)......................................................................18
WRITE STATUS REGISTER (WRSR) (01H OR 31H OR 11H)....................................................................18
READ DATA BYTES (READ) (03H) ........................................................................................................19
READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH).....................................................................20
DUAL OUTPUT FAST READ (3BH) ..........................................................................................................20
QUAD OUTPUT FAST READ (6BH) .........................................................................................................21
7.10. DUAL I/O FAST READ (BBH) .................................................................................................................22
7.11. QUAD I/O FAST READ (EBH).................................................................................................................23
7.12. SET BURST WITH WRAP (77H) ..............................................................................................................25
7.13. PAGE PROGRAM (PP) (02H) .................................................................................................................26
7.14. QUAD PAGE PROGRAM (32H)................................................................................................................26
7.15. SECTOR ERASE (SE) (20H) ..................................................................................................................27
7.16. 32KB BLOCK ERASE (BE) (52H)...........................................................................................................28
7.17. 64KB BLOCK ERASE (BE) (D8H) ..........................................................................................................29
7.18. CHIP ERASE (CE) (60/C7H)..................................................................................................................29
7.19. DEEP POWER-DOWN (DP) (B9H)..........................................................................................................30
7.20. RELEASE FROM DEEP POWER-DOWN AND READ DEVICE ID (RDI) (ABH) ...............................................30
7.21. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ..............................................................................32
7.22. READ IDENTIFICATION (RDID) (9FH) .....................................................................................................33
7.23. PROGRAM/ERASE SUSPEND (PES) (75H)..............................................................................................33
7.24. PROGRAM/ERASE RESUME (PER) (7AH)...............................................................................................34
7.25. ERASE SECURITY REGISTERS (44H)......................................................................................................35
7.26. PROGRAM SECURITY REGISTERS (42H).................................................................................................35
7.27. READ SECURITY REGISTERS (48H)........................................................................................................36
7.28. ENABLE RESET (66H) AND RESET (99H) ...............................................................................................37
8. ELECTRICAL CHARACTERISTICS.........................................................................................................38
8.1. POWER-ON TIMING ..........................................................................................................................38
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GPR25L12806F
8.2. INITIAL DELIVERY STATE.................................................................................................................38
8.3. ABSOLUTE MAXIMUM RATINGS .....................................................................................................38
8.4. CAPACITANCE MEASUREMENT CONDITIONS..............................................................................39
8.5. DC CHARACTERISTICS....................................................................................................................40
8.6. AC CHARACTERISTICS....................................................................................................................42
9. ORDERING INFORMATION......................................................................................................................47
9.1.
10.
VALID PART NUMBERS ..........................................................................................................................47
PACKAGE INFORMATION....................................................................................................................48
10.1. PACKAGE OUTLINE FOR SOP 8L (208MIL)............................................................................................48
11.
12.
DISCLAIMER .........................................................................................................................................49
REVISION HISTORY..............................................................................................................................50
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GPR25L12806F
1. FEATURES
◆
128M-bit Serial Flash
◆
Fast Program/Erase Speed
-16384K-byte
-Page Program time: 0.6ms typical
-Sector Erase time: 50ms typical
-Block Erase time: 0.2/0.3s typical
-Chip Erase time: 60s typical
-256 bytes per programmable page
◆
Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#/ RESET#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#/ RESET#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆
◆
◆
Flexible Architecture
-Uniform Sector of 4K-byte
-Uniform Block of 32/64k-byte
◆
◆
◆
High Speed Clock Frequency
-104MHz for Standard and Dual SPI fast read with 30PF load
-Dual I/O Data transfer up to 208Mbits/s
-Quad I/O Data transfer up to 416Mbits/s
Low Power Consumption
-25mA maximum active current
-5uA maximum power down current
Software/Hardware Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
-Top/Bottom Block protection
Advanced Security Features
-3x1024-Byte Security Registers With OTP Locks
◆
◆
Single Power Supply Voltage
-Full voltage range:2.7~3.6V
Allows XIP (execute in place) Operation
-Continuous Read With 8/16/32/64-byte Wrap
Package Information
-SOP8 (208mil)
◆ Minimum 100,000 Program/Erase Cycles
◆ Data Retention
-20-year data retention typical
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GPR25L12806F
2. GENERAL DESCRIPTION
The GPR25L12806F (128M-bit) Serial flash supports the
standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI),
I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#/ RESET#). The Dual
I/O data is transferred with speed of 208Mbits/s and the Quad
I/O & Quad output data is transferred with speed of 416Mbits/s.
CONNECTION DIAGRAM
CS#
1
2
3
4
8
7
6
5
VCC
HOLD#/
RESET#
(IO3)
SO
(IO1)
Top View
WP#
(IO2)
SCLK
SI
(IO0)
VSS
8–LEAD SOP
Note:
(1) Only for special order, Pin 3 of 16-LEAD SOP package is RESET# pin.
PIN DESCRIPTION
Pin Name
CS#
I/O
I
Description
Chip Select Input
SO (IO1)
WP# (IO2)
VSS
I/O
I/O
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
SI (IO0)
I/O
I
Data Input (Data Input Output 0)
Serial Clock Input
SCLK
HOLD#/RESET# (IO3)
VCC
I/O
Hold or Reset Input (Data Input Output 3)
Power Supply
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
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GPR25L12806F
BLOCK DIAGRAM
Write Control
Logic
WP#(IO2)
Status
Register
Flash
Memory
HOLD#/
RESET#(IO3)
High Voltage
Generators
SPI
Command &
Control Logic
SCLK
CS#
Page Address
Latch/Counter
Column Decode And
256-Byte Page Buffer
SI(IO0)
SO(IO1)
Byte Address
Latch/Counter
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GPR25L12806F
3. MEMORY ORGANIZATION
GPR25L12806F
Each device has
Each block has
Each sector has
Each page has
16M
64K
64/32K
256/128
16/8
4K
16
-
256
bytes
pages
sectors
blocks
-
-
-
4096
256/512
-
-
UNIFORM BLOCK SECTOR ARCHITECTURE
GPR25L12806F 64K Bytes Block Sector Architecture
Block
Sector
Address range
4095
……
4080
4079
……
4064
……
……
……
……
……
……
47
FFF000H
FFFFFFH
255
……
FF0000H
FEF000H
……
……
FF0FFFH
FEFFFFH
……
254
……
……
2
FE0000H
……
FE0FFFH
……
……
……
……
……
……
……
……
……
……
……
02F000H
……
02FFFFH
……
……
32
020000H
01F000H
……
020FFFH
01FFFFH
……
31
1
……
16
010000H
00F000H
……
010FFFH
00FFFFH
……
15
0
……
0
000000H
000FFFH
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GPR25L12806F
4. DEVICE OPERATION
SPI Mode
require the non-volatile Quad Enable bit(QE) in Status Register to
be set.
Standard SPI
The GPR25L12806F features a serial peripheral interface on 4
signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data
Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and
3 are supported. Input data is latched on the rising edge of SCLK
and data shifts out on the falling edge of SCLK.
Hold
The HOLD/RST bit is used to determine whether HOLD# or
RESET# function should be implemented on the hardware pin for
8-pin packages. When HOLD/RST=0, the pin7 acts as HOLD#, the
HOLD# function is only available when QE=0, If QE=1, The
HOLD# functions is disabled, the pin acts as dedicated data I/O
pin.
Dual SPI
The GPR25L12806F supports Dual SPI operation when using the
“Dual Output Fast Read” and “Dual I/O Fast Read” (3BH and BBH)
commands. These commands allow data to be transferred to or
from the device at twice the rate of the standard SPI. When using
the Dual SPI command the SI and SO pins become bidirectional
I/O pins: IO0 and IO1.
The HOLD# signal goes low to stop any serial communications
with the device, but doesn’t stop the operation of write status
register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling
edge of the HOLD# signal, with SCLK signal being low (if SCLK is
not being low, HOLD operation will not start until SCLK being low).
The HOLD condition ends on rising edge of HOLD# signal with
SCLK being low (If SCLK is not being low, HOLD operation will not
end until SCLK being low).
Quad SPI
The GPR25L12806F supports Quad SPI operation when using the
“Quad Output Fast Read”,” Quad I/O Fast Read”, “Quad I/O Word
Fast Read”(6BH,EBH)commands. These commands allow data to
be transferred to or from the device at four times the rate of the
standard SPI. When using the Quad SPI command the SI and SO
pins become bidirectional I/O pins: IO0 and IO1, and WP# and
HOLD#/RESET# pins become IO2 and IO3. Quad SPI commands
The SO is high impedance, both SI and SCLK don’t care during
the HOLD operation, if CS# drives high during HOLD operation, it
will reset the internal logic of the device. To re-start communication
with chip, the HOLD# must be at high and then CS# must be at
low.
Figure1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
RESET
HOLD/RST=1. On the SOP16 package, a dedicated RESET# pin
is provided and it is independent of QE bit setting.
The RESET# pin allows the device to be reset by the control. For
the WSON8 package, the pin7 can be configured as a RESET#
pin depending on the status register setting, which need QE=0 and
The RESET# pin goes low for a period of tRLRH or longer will reset
the flash. After reset cycle, the flash is at the following states:
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GPR25L12806F
-Standby mode
on.
-All the volatile bits will return to the default status as power
Figure2. RESET Condition
CS#
RESET#
RESET
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GPR25L12806F
5. DATA PROTECTION
The GPR25L12806Fprovide the following data protection methods:
-The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits
define the section of the memory array that can be read
but not change.
◆
Write Enable (WREN) command: The WREN command
is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up
◆
◆
Hardware Protection Mode: WP# goes low to protect the
writable bit of Status Register.
-Write Disable (WRDI)
Deep Power-Down Mode: In Deep Power-Down Mode,
all commands are ignored except the Release from Deep
Power-Down Mode command and reset command
(66H+99H).
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
Software Protection Mode:
◆
Table 5.1. GPR25L12806F Protected area size (CMP=0)
Memory Content
Status Register Content
BP4
X
BP3
X
BP2
BP1
BP0
Blocks
NONE
Addresses
NONE
Density
NONE
256KB
512KB
1MB
Portion
NONE
0
0
0
0
0
0
1
1
0
1
0
1
0
0
252 to 255
248 to 255
240 to 255
FC0000H-FFFFFFH
F80000H-FFFFFFH
F00000H-FFFFFFH
Upper 1/64
Upper 1/32
Upper 1/16
0
0
0
0
0
0
0
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
X
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
X
0
1
0
1
X
0
224 to 255
192 to 255
128 to 255
0 to 3
0 to 7
0 to 15
0 to 31
0 to 63
0 to 127
0 to 255
255
E00000H-FFFFFFH
C00000H-FFFFFFH
800000H-FFFFFFH
000000H-03FFFFH
000000H-07FFFFH
000000H-0FFFFFH
000000H-1FFFFFH
000000H-3FFFFFH
000000H-7FFFFFH
000000H-FFFFFFH
FFF000H-FFFFFFH
FFE000H-FFFFFFH
FFC000H-FFFFFFH
FF8000H-FFFFFFH
FF8000H-FFFFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
000000H-007FFFH
000000H-007FFFH
2MB
4MB
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
8MB
256KB
512KB
1MB
2MB
4MB
8MB
16MB
4KB
Top Block
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
255
8KB
255
16KB
32KB
32KB
4KB
255
255
0
0
8KB
0
16KB
32KB
32KB
0
0
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GPR25L12806F
Table 5.2. GPR25L12806F Protected area size (CMP=1)
Memory Content
Status Register Content
BP4
X
BP3
X
BP2
BP1
BP0
Blocks
0 to 255
0 to 251
0 to 247
0 to 239
Addresses
Density
ALL
Portion
ALL
0
0
0
0
0
0
1
1
0
1
0
1
000000H-FFFFFFH
000000H-FBFFFFH
000000H-F7FFFFH
000000H-EFFFFFH
000000H-DFFFFFH
000000H-BFFFFFH
000000H-7FFFFFH
040000H-FFFFFFH
080000H-FFFFFFH
100000H-FFFFFFH
200000H-FFFFFFH
400000H-FFFFFFH
800000H-FFFFFFH
NONE
0
0
16128KB
15872KB
15MB
Lower 63/64
Lower 31/32
Lower 15/16
0
0
0
0
0
0
0
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
X
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
X
0
1
0
1
X
0
0 to 223
0 to 191
0 to 127
4 to 255
8 to 255
16 to 255
32 to 255
64 to 255
128 to 255
NONE
14MB
12MB
Lower 7/8
Lower 3/4
8MB
Lower 1/2
16128KB
15872KB
15MB
Upper 63/64
Upper 31/32
Upper 15/16
Upper 7/8
14MB
12MB
Upper 3/4
8MB
Upper 1/2
NONE
NONE
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
0 to 255
000000H-FFEFFFH
000000H-FFDFFFH
000000H-FFBFFFH
000000H-FF7FFFH
000000H-FF7FFFH
001000H-FFFFFFH
002000H-FFFFFFH
004000H-FFFFFFH
008000H-FFFFFFH
008000H-FFFFFFH
16380KB
16376KB
16368KB
16352KB
16352KB
16380KB
16376KB
16368KB
16352KB
16352KB
L-4095/4096
L-2047/2048
L-1023/1024
L-511/512
L-511/512
U-4095/4096
U-2047/2048
U-1023/1024
U-511/512
U-511/512
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GPR25L12806F
6. STATUS REGISTER
S23
S22
S21
S20
S19
S18
LPE
S17
S16
HOLD/RST
DRV1
DRV0
Reserved
Reserved
Reserved
Reserved
S15
S14
S13
LB3
S12
LB2
S11
LB1
S10
S9
S8
SUS1
CMP
SUS2
QE
SRP1
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
BP4
BP3
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit.
the Write Status Register (WRSR) command. When the Block
Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant
memory area (as defined in Table1).becomes protected against
Page Program (PP), Sector Erase (SE) and Block Erase (BE)
commands. The Block Protect (BP4, BP3, BP2, BP1, and BP0)
bits can be written provided that the Hardware Protected mode has
not been set. The Chip Erase (CE) command is executed, only if
the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or
the Block Protect (BP2, BP1, and BP0) bits are 1 and CMP=1.
SRP1, SRP0 bits.
The Write in Progress (WIP) bit indicates whether the memory is
busy in program/erase/write status register progress. When WIP
bit sets to 1, means the device is busy in program/erase/write
status register progress, when WIP bit sets 0, means the device is
not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the
internal Write Enable Latch. When set to 1 the internal Write
Enable Latch is set, when set to 0 the internal Write Enable Latch
is reset and no Write Status Register, Program or Erase command
is accepted.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile
Read/Write bits in the status register. The SRP bits control the
method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable
protection.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits are non-
volatile. They define the size of the area to be software protected
against Program and Erase commands. These bits are written with
SRP1
SRP0
#WP
Status Register
Description
The Status Register can be written to after a Write Enable command,
WEL=1.(Default)
0
0
X
Software Protected
WP#=0, the Status Register locked and cannot be written to.
0
0
1
1
0
1
Hardware Protected
WP#=1, the Status Register is unlocked and can be written to after
a Write Enable command, WEL=1.
Hardware Unprotected
Status Register is protected and cannot be written to again until the
next Power-Down, Power-Up cycle.
1
1
0
1
X
X
Power Supply Lock-Down(1)(2)
One Time Program(2)
Status Register is permanently protected and cannot be written to.
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order.
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GPR25L12806F
QE bit.
CMP bit
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the
The CMP bit is a non-volatile Read/Write bit in the Status Register
(S14). It is used in conjunction with the BP4-BP0 bits to provide
more flexibility for the array protection. Please see the Status
registers Memory Protection table for details. The default setting is
CMP=0.
Status Register that allows Quad operation. When the QE bit is set
to 0 (Default) the WP# pin and HOLD# / RESET# pin are enable.
When the QE pin is set to 1, the Quad IO2 and IO3 pins are
enabled. (The QE bit should never be set to 1 during standard SPI
or Dual SPI operation if the WP# or HOLD# / RESET# pins are tied
directly to the power supply or ground)
SUS1, SUS2 bits
The SUS1 and SUS2 bit are read only bits in the status register
(S15 and S10) that are set to 1 after executing an Program/Erase
Suspend (75H) command (The Erase Suspend will set the SUS1
to 1,and the Program Suspend will set the SUS2 to 1). The SUS1
and SUS2 bit are cleared to 0 by Program/Erase Resume (7AH)
command, software reset (66H+99H) command as well as a
power-down, power-up cycle.
LB3, LB2, LB1, bits.
The LB3, LB2, LB1, bits are non-volatile One Time Program (OTP)
bits in Status Register (S13-S11) that provide the write protect
control and status to the Security Registers. The default state of
LB3-LB1are 0, the security registers are unlocked. The LB3-LB1
bits can be set to 1 individually using the Write Register instruction.
The LB3-LB1 bits are One Time Programmable, once they are set
to 1, the Security Registers will become read-only permanently.
DRV1/DRV0
The DRV1&DRV0 bits are used to determine the output driver
strength for the Read operations.
DRV1,DRV0
Driver Strength
00
01
10
11
100%
75%
50% (default)
25%
HOLD/RST bit
acts as dedicated data I/O pin.
The HOLD/RST bit is used to determine whether HOLD# or
RESET# function should be implemented on the hardware pin for
8-pin packages. When HOLD/RST=0, the pin acts as HOLD#,
When the HOLD/RST=1, the pin acts as RESET#. However, the
HOLD# or RESET# function are only available when QE=0, If
QE=1, The HOLD# and RESET# functions are disabled, the pin
LPE bit
The Low Power Enable (LPE) bit is a non-volatile writable bit,
indicating the status of Low Power Mode (LPM). When LPE bit sets
to 1, it means the device is in Low Power Mode, when LPE bit sets
0 (default), it means the device is not in Low Power Mode.
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7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the
device, beginning with the most significant bit on the first rising
edge of SCLK after CS# is driven low. Then, the one-byte
command code must be shifted in to the device, with most
significant bit first on SI, and each bit being latched on the rising
edges of SCLK.
and Read Device ID, the shifted-in command sequence is followed
by a data-out sequence. CS# can be driven high after any bit of
the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase,
Chip Erase, Write Status Register, Write Enable, Write Disable or
Deep Power-Down command, CS# must be driven high exactly at
a byte boundary, otherwise the command is rejected, and is not
executed. That is CS# must be driven high when the number of
clock pulses after CS# being driven low is an exact multiple of eight.
For Page Program, if at any time the input byte is not a full byte,
nothing will happen and WEL will not be reset.
See Table 7.1., every command sequence starts with a one-byte
command code. Depending on the command, this might be
followed by address bytes, or by data bytes, or by both or none.
CS# must be driven high after the last bit of the command
sequence has been completed. For the command of Read, Fast
Read, Read Status Register or Release from Deep Power-Down,
Table 7.1. Commands (Standard/Dual/Quad SPI)
Command Name
Byte 1
06H
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
Write Enable
Write Disable
04H
Volatile SR
50H
Write Enable
Read Status Register-1
Read Status Register-2
Read Status Register-3
Write Status Register-1
Write Status Register-2
Write Status Register-3
Read Data
05H
35H
15H
01H
31H
11H
03H
0BH
3BH
(S7-S0)
(S15-S8)
(S23-S16)
S7-S0
(continuous)
(continuous)
S15-S8
S23-S16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
(D7-D0)
dummy
dummy
(Next byte)
(D7-D0)
(D7-D0)(1)
(continuous)
(continuous)
(continuous)
Fast Read
Dual Output
Fast Read
Dual I/O
BBH
6BH
EBH
A23-A8(2)
A23-A16
A7-A0
M7-M0(2)
(D7-D0)(1)
A7-A0
(continuous)
(continuous)
(continuous)
Fast Read
Quad Output
A15-A8
dummy
(D7-D0)(3)
Next byte
Fast Read
Quad I/O
A23-A0
dummy(5)
(D7-D0)(3)
Fast Read
M7-M0(4)
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
Page Program
Quad Page Program
Sector Erase
02H
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
D7-D0
D7-D0
32H
20H
Block Erase(32K)
Block Erase(64K)
Chip Erase
52H
D8H
C7/60H
66H
Enable Reset
Reset
99H
Set Burst with Wrap
77H
dummy(8)
W7-W0
Program/Erase Suspend
Program/Erase Resume
75H
7AH
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Release From Deep
Power-Down, And
Read Device ID
Release From Deep
Power-Down
ABH
ABH
dummy
dummy
dummy
dummy
(DID7-
(continuous)
DID0)
Deep Power-Down
Manufacturer/
B9H
90H
dummy
00H
(MID7-
MID0)
(DID7-DID0)
(continuous)
(continuous)
Device ID
Read Identification
(JDID15-
JDID8)
(JDID7-
JDID0)
A7-A0
A7-A0
9FH
(MID7-MID0)
Erase Security Registers(7)
Program Security
44H
42H
A23-A16
A23-A16
A15-A8
A15-A8
D7-D0
D7-D0
Registers(7)
Read Security Registers(7)
48H
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
NOTE:
1. Dual Output data
IO0=(D6,D4,D2,D0)
IO1=(D7,D5,D3,D1)
2. Dual Input Address
IO0=A22,A20,A18,A16,A14,A12,A10,A8 A6,A4,A2,A0,M6,M4,M2,M0
IO1=A23,A21,A19,A17,A15,A13,A11,A9 A7,A5,A3,A1,M7,M5,M3,M1
3. Quad Output Data
IO0=(D4,D0,…..)
IO1=(D5,D1,…..)
IO2=(D6,D2,…..)
IO3=(D7,D3,…..)
4. Quad Input Address
IO0=A20,A16,A12,A8, A4,A0,M4,M0
IO1=A21,A17,A13,A9, A5,A1,M5,M1
IO2=A22,A18,A14,A10,A6,A2,M6,M2
IO3=A23,A19,A15,A11,A7,A3,M7,M3
5. Fast Read Quad I/O Data
IO0=(x,x,x,x, D4, D0,…)
IO1=(x,x,x,x, D5, D1,…)
IO2=(x,x,x,x, D6, D2,…)
IO3=(x,x,x,x, D7, D3,…)
6. Fast Word Read Quad I/O Data
IO0=(x,x, D4, D0,…)
IO1=(x,x, D5, D1,…)
IO2=(x,x, D6, D2,…)
IO3=(x,x, D7, D3,…)
7. Security Registers Address:
Security Register1: A23-A16=00H, A15-A10=000100b, A9-A0=Byte Address;
Security Register2: A23-A16=00H, A15-A10=001000b, A9-A0=Byte Address;
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Security Register3: A23-A16=00H, A15-A10=001100b, A9-A0=Byte Address.
8. Dummy bits and Wrap Bits
IO0=(x,x, x,x, x,x, W4,x)
IO1=(x,x, x,x, x,x, W5, x)
IO2=(x,x, x,x, x,x, W6, x)
IO3=(x,x, x,x, x,x, x, x)
9.Address, Continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID
IO0=(A20, A16, A12, A8, A4, A0, M4, M0, x,x, x,x, MID4, MID0, DID4, DID0, …)
IO1=(A21, A17, A13, A9, A5, A1, M5, M1, x,x, x,x, MID5, MID1, DID5, DID1, …)
IO2=(A22, A18, A14, A10, A6, A2, M6, M2,x,x, x,x, MID6, MID2, DID6, DID2, …)
IO3=(A23, A19, A15, A11, A7, A3, M7, M3, x,x, x,x, MID7, MID3, DID7, DID3, …)
Table 7.2. Table of ID Definitions for GPR25L12806F
Operation Code
MID7-MID0
ID15-ID8
ID7-ID0
18
9FH
90H
ABH
C8
C8
40
17
17
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7.1. Write Enable (WREN) (06H)
(BE), Chip Erase (CE), Write Status Register (WRSR) and
Erase/Program Security Registers command. The Write Enable
(WREN) command sequence: CS# goes low sending the Write
Enable command CS# goes high.
The Write Enable (WREN) command is for setting the Write Enable
Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set
prior to every Page Program (PP), Sector Erase (SE), Block Erase
Figure3. Write Enable Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
Command
06H
High-Z
SO
7.2.
Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch
(WEL) bit. The Write Disable command sequence: CS# goes
lowSending the Write Disable command CS# goes high. The
WEL bit is reset by following condition: Power-up and upon
completion of the Write Status Register, Page Program, Sector
Erase, Block Erase, Chip Erase, Erase/Program Security
Registers and Reset commands.
Figure4. Write Disable Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
Command
04H
High-Z
SO
7.3.
Write Enable for Volatile Status Register (50H)
The non-volatile Status Register bits can also be written to as
volatile bits. This gives more flexibility to change the system
configuration and memory protection schemes quickly without
waiting for the typical non-volatile bit write cycles or affecting the
endurance of the Status Register non-volatile bits. The Write
Enable for Volatile Status Register command must be issued prior
to a Write Status Register command, and any other commands
cannot be inserted between them. Otherwise, Write Enable for
Volatile Status Register will be cleared. The Write Enable for
Volatile Status Register command will not set the Write Enable
Latch bit, it is only valid for the Write Status Register command to
change the volatile Status Register bit values.
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Figure5. Write Enable for Volatile Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
Command(50H)
High-Z
SI
SO
7.4.
Read Status Register (RDSR) (05H or 35H or 15H)
The Read Status Register (RDSR) command is for reading the
Status Register. The Status Register may be read at any time,
even while a Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress, it is
recommended to check the Write in Progress (WIP) bit before
sending a new command to the device. It is also possible to read
the Status Register continuously. For command code “05H”/ “35H”
/ “15H”, the SO will output Status Register bits S7~S0/ S15-S8 /
S16-S23.
Figure6. Read Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Command
SI
05H or 35H or 15H
Register0/1/2
Register0/1/2
SO
High-Z
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
7.5. Write Status Register (WRSR) (01H or 31H or 11H)
The Write Status Register (WRSR) command allows new values
to be written to the Status Register. Before it can be accepted, a
Write Enable (WREN) command must previously have been
executed. After the Write Enable (WREN) command has been
decoded and executed, the device sets the Write Enable Latch
(WEL).
not executed. As soon as CS# is driven high, the self-timed Write
Status Register cycle (whose duration is tW) is initiated. While the
Write Status Register cycle is in progress, the Status Register may
still be read to check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-timed Write
Status Register cycle, and is 0 when it is completed. When the
cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command has no effect on S20,
S19, S17, S16, S15, S10, S1 and S0 of the Status Register. CS#
must be driven high after the eighth of the data byte has been
latched in. If not, the Write Status Register (WRSR) command is
The Write Status Register (WRSR) command allows the user to
change the values of the Block Protect (BP4, BP3, BP2, BP1, and
BP0) bits, to define the size of the area that is to be treated as
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read-only. The Write Status Register (WRSR) command also
allows the user to set or reset the Status Register Protect (SRP1
and SRP0) bits in accordance with the Write Protect (WP#) signal.
The Status Register Protect (SRP1 and SRP0) bits and Write
Protect (WP#) signal allow the device to be put in the Hardware
Protected Mode. The Write Status Register (WRSR) command is
not executed once the Hardware Protected Mode is entered.
Figure7. Write Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Command
01H/31H/11H
Status Register in
SI
7
6
5
4
3
2 1 0
MSB
High-Z
SO
7.6.
Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte
address (A23-A0), and each bit is latched-in on the rising edge of
SCLK. Then the memory content, at that address, is shifted out on
SO, each bit being shifted out, at a Max frequency fR, during the
falling edge of SCLK. Then the memory content at that address is
shifted out on SO. The first byte addressed can be at any location.
The address is automatically incremented to the next higher
address after each byte of data is shifted out. The whole memory
can, therefore, be read with a single Read Data Bytes (READ)
command. Any Read Data Bytes (READ) command, while an
Erase, Program or Write cycle is in progress, is rejected without
having any effects on the cycle that is in progress.
Figure8. Read Data Bytes Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
03H
24-bit address
23 22 21
MSB
SI
3
2
1
0
Data Out1
Data Out2
High-Z
SO
7
6
5
4
3
2
1
0
MSB
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7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is
for quickly reading data out. It is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising
edge of SCLK. Then the memory content, at that address, is
shifted out on SO, each bit being shifted out, at a Max frequency
fC, during the falling edge of SCLK. The first byte addressed can
be at any location. The address is automatically incremented to the
next higher address after each byte of data is shifted out.
Figure9. Read Data Bytes at Higher Speed Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
0BH
24-bit address
23 22 21
SI
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
7.8.
Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte
address (A23-A0) and a dummy byte, each bit being latched in
during the rising edge of SCLK, then the memory contents are
shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure 10. The first
byte addressed can be at any location. The address is
automatically incremented to the next higher address after each
byte of data is shifted out.
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Figure10. Dual Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
3BH
24-bit address
23 22 21
SI
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
SCLK
SI
6
4
2
0
6
4
2
0
6
7
Data Out1
Data Out2
SO
7
5
3
1
7
5
3
1
MSB
MSB
7.9.
Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte
address (A23-A0) and a dummy byte, each bit being latched in
during the rising edge of SCLK, then the memory contents are
shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The
command sequence is shown in followed Figure11. The first byte
addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is
shifted out.
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Figure11. Quad Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
6BH
24-bit address
23 22 21
SI(IO0)
3
2
1
0
SO(IO1)
High-Z
High-Z
High-Z
WP#(IO2)
HOLD#(IO3)
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
SCLK
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Byte1 Byte2 Byte3 Byte4
7.10. Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output
Fast Read command but with the capability to input the 3-byte
address (A23-0) and a “Continuous Read Mode” byte 2-bit per
clock by SI and SO, each bit being latched in during the rising edge
of SCLK, then the memory contents are shifted out 2-bit per clock
Dual I/O Fast Read with “Continuous Read Mode”
cycle from SI and SO. The command sequence is shown in
followed Figure12. The first byte addressed can be at any location.
The address is automatically incremented to the next higher
address after each byte of data is shifted out.
The Dual I/O Fast Read command can further reduce command
overhead through setting the “Continuous Read Mode” bits (M7-4)
after the input 3-byte address (A23-A0). If the “Continuous Read
Mode” bits (M5-4)= (1, 0), then the next Dual I/O Fast Read
command (after CS# is raised and then lowered) does not require
the BBH command code. The command sequence is shown in
followed Figure12a. If the “Continuous Read Mode” bits (M5-4) do
not equal (1, 0), the next command requires the first BBH
command code, thus returning to normal operation. A “Continuous
Read Mode” Reset command can be used to reset (M5-4) before
issuing normal command.
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Figure12. Dual I/O Fast Read Sequence Diagram (M5-4≠(1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
BBH
SI(IO0)
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
SO(IO1)
7
Dummy
M7-4
A23-16
A15-8
A7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
SO(IO1)
Byte1
Byte2
Byte3
Byte4
Figure12a. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
6
4
2
0
6
4
2
0
6
4
5
2
3
0
1
6
7
4
5
7
5
3
1
7
5
3
1
7
A23-16
A15-8
A7-0
M7-4
Dummy
CS#
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
SO(IO1)
Byte1
Byte2
Byte3
Byte4
7.11. Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast
Read command but with the capability to input the 3-byte address
(A23-0) and a “Continuous Read Mode” byte and 4-dummy clock4-
bit per clock by IO0, IO1, IO2, IO3, each bit being latched in during
the rising edge of SCLK, then the memory contents are shifted out
4-bit per clock cycle from IO0, IO1, IO2, IO3. The command
sequence is shown in followed Figure13. The first byte addressed
can be at any location. The address is automatically incremented
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to the next higher address after each byte of data is shifted out.
The Quad Enable bit (QE) of Status Register (S9) must be set to
Quad I/O Fast Read with “Continuous Read Mode”
enable for the Quad I/O Fast read command.
The Quad I/O Fast Read command can further reduce command
overhead through setting the “Continuous Read Mode” bits (M7-0)
after the input 3-byte address (A23-A0). If the “Continuous Read
Mode” bits (M5-4) = (1, 0), then the next Quad I/O Fast Read
command (after CS# is raised and then lowered) does not require
the EBH command code. The command sequence is shown in
followed Figure13a. If the “Continuous Read Mode” bits (M5-4) do
not equal to (1, 0), the next command requires the first EBH
command code, thus returning to normal operation. A “Continuous
Read Mode” Reset command can be used to reset (M5-4) before
issuing normal command.
Figure13. Quad I/O Fast Read Sequence Diagram (M5-4≠(1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
EBH
SI(IO0)
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SO(IO1)
5
6
7
WP#(IO2)
HOLD#(IO3)
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
Figure13a. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI(IO0)
4
0
4
0
4
0
4
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
SO(IO1)
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
WP#(IO2)
HOLD#(IO3)
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI Mode
The Quad I/O Fast Read command can be used to access a
specific portion within a page by issuing “Set Burst with Wrap” (77H)
commands prior to EBH. The “Set Burst with Wrap” (77H)
command can either enable or disable the “Wrap Around” feature
for the following EBH commands. When “Wrap Around” is enabled,
the data being accessed can be limited to either an8/16/32/64-byte
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section of a 256-byte page. The output data starts at the initial
address specified in the command, once it reaches the ending
boundary of the 8/16/32/64-byte section, the output will wrap
around the beginning boundary automatically until CS# is pulled
high to terminate the command.
quickly fetch a critical address and then fill the cache afterwards
within a fixed length (8/16/32/64-byte) of data without issuing
multiple read commands. The “Set Burst with Wrap” command
allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-W5 is
used to specify the length of the wrap around section within a page.
The Burst with Wrap feature allows applications that use cache to
7.12. Set Burst with Wrap (77H)
The Set Burst with Wrap command is used in conjunction with
“Quad I/O Fast Read” and “Quad I/O Word Fast Read” command
to access a fixed length of 8/16/32/64-byte section within a 256-
byte page.
The Set Burst with Wrap command sequence: CS# goes low
Send Set Burst with Wrap command Send 24 dummy bits
Send 8 bits “Wrap bits” CS# goes high.
W4=0
W4=1 (default)
W6,W5
Wrap Around
Wrap Length
Wrap Around
Wrap Length
0, 0
0, 1
1, 0
1, 1
Yes
Yes
Yes
Yes
8-byte
16-byte
32-byte
64-byte
No
No
No
No
N/A
N/A
N/A
N/A
If the W6-W4 bits are set by the Set Burst with Wrap command, all
the following “Quad I/O Fast Read” and “Quad I/O Word Fast Read”
command will use the W6-W4 setting to access the 8/16/32/64-
byte section within any page. To exit the “Wrap Around” function
and return to normal read operation, another Set Burst with Wrap
command should be issued to set W4=1.
Figure14. Set Burst with Wrap Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Command
77H
SI(IO0)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
5
6
x
x
x
x
x
SO(IO1)
x
x
x
WP#(IO2)
HOLD#(IO3)
W6-W4
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7.13. Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory.
A Write Enable (WREN) command must previously have been
executed to set the Write Enable Latch (WEL) bit before sending
the Page Program command.
same page. If less than 256 data bytes are sent to device, they are
correctly programmed at the requested addresses without having
any effects on the other bytes of the same page. CS# must be
driven high after the eighth bit of the last data byte has been
latched in; otherwise the Page Program (PP) command is not
executed.
The Page Program (PP) command is entered by driving CS# Low,
followed by the command code, three address bytes and at least
one data byte on SI. If the 8 least significant address bits (A7-A0)
are not all zero, all transmitted data that goes beyond the end of
the current page are programmed from the start address of the
same page (from the address whose 8 least significant bits (A7-
A0) are all zero). CS# must be driven low for the entire duration of
the sequence. The Page Program command sequence: CS# goes
low sending Page Program command 3-byte address on SI
at least 1 byte data on SI CS# goes high. The command
sequence is shown in Figure15. If more than 256 bytes are sent to
the device, previously latched data are discarded and the last 256
data bytes are guaranteed to be programmed correctly within the
As soon as CS# is driven high, the self-timed Page Program cycle
(whose duration is tPP) is initiated. While the Page Program cycle
is in progress, the Status Register may be read to check the value
of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit
is 1 during the self-timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed,
the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) is
not executed.
Figure15. Page Program Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
02H
24-bit address
23 22 21
MSB
Data Byte 1
SI
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
7.14. Quad Page Program (32H)
The Quad Page Program command is for programming the
memory using four pins: IO0, IO1, IO2, and IO3. To use Quad Page
Program the Quad enable in status register Bit9 must be set
(QE=1).A Write Enable (WREN) command must previously have
been executed to set the Write Enable Latch (WEL) bit before
sending the Page Program command. The quad Page Program
command is entered by driving CS# Low, followed by the
command code (32H), three address bytes and at least one data
byte on IO pins.
The command sequence is shown in Figure16. If more than 256
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bytes are sent to the device, previously latched data are discarded
and the last 256 data bytes are guaranteed to be programmed
correctly within the same page. If less than 256 data bytes are sent
to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the
same page. CS# must be driven high after the eighth bit of the last
data byte has been latched in; otherwise the Quad Page Program
(PP) command is not executed.
Program cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write in
Progress (WIP) bit is 1 during the self-timed Quad Page Program
cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Quad Page Program command applied to a page which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) is
not executed.
As soon as CS# is driven high, the self-timed Quad Page Program
cycle (whose duration is tPP) is initiated. While the Quad Page
Figure16.Quad Page Program Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
32H
24-bit address
23 22 21
MSB
Byte1 Byte2
SI(IO0)
3
2
1
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Byte11Byte12
SCLK
Byte253
Byte256
SI(IO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
7.15. Sector Erase (SE) (20H)
The Sector Erase (SE) command is erased the all data of the
chosen sector. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit. The
Sector Erase (SE) command is entered by driving CS# low,
followed by the command code, and 3-address byte on SI. Any
address inside the sector is a valid address for the Sector Erase
(SE) command. CS# must be driven low for the entire duration of
the sequence.
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The Sector Erase command sequence: CS# goes low sending
Sector Erase command 3-byte address on SI CS# goes high.
The command sequence is shown in Figure17. CS# must be
driven high after the eighth bit of the last address byte has been
latched in; otherwise the Sector Erase (SE) command is not
executed. As soon as CS# is driven high, the self-timed Sector
Erase cycle (whose duration is tSE) is initiated. While the Sector
Erase cycle is in progress, the Status Register may be read to
check the value of the Write in Progress (WIP) bit. The Write in
Progress (WIP) bit is 1 during the self-timed Sector Erase cycle,
and is 0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset. A
Sector Erase (SE) command applied to a sector which is protected
by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit is not
executed.
Figure17. Sector Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
20H
24 Bits Address
23 22
MSB
SI
2
1
0
7.16. 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is erased the all data of the
chosen block. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit. The
32KB Block Erase (BE) command is entered by driving CS# low,
followed by the command code, and three address bytes on SI.
Any address inside the block is a valid address for the 32KB Block
Erase (BE) command. CS# must be driven low for the entire
duration of the sequence.
byte has been latched in; otherwise the 32KB Block Erase (BE)
command is not executed. As soon as CS# is driven high, the self-
timed Block Erase cycle (whose duration is tBE) is initiated. While
the Block Erase cycle is in progress, the Status Register may be
read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Block Erase
cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is
reset. A 32KB Block Erase (BE) command applied to a block which
is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0)
bits is not executed.
The 32KB Block Erase command sequence: CS# goes low
sending 32KB Block Erase command 3-byte address on SI
CS# goes high. The command sequence is shown in Figure18.
CS# must be driven high after the eighth bit of the last address
Figure18. 32KB Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
52H
24 Bits Address
23 22
MSB
SI
2
1
0
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7.17. 64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is erased the all data of the
chosen block. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit. The
64KB Block Erase (BE) command is entered by driving CS# low,
followed by the command code, and three address bytes on SI.
Any address inside the block is a valid address for the 64KB Block
Erase (BE) command. CS# must be driven low for the entire
duration of the sequence.
byte has been latched in; otherwise the 64KB Block Erase (BE)
command is not executed. As soon as CS# is driven high, the self-
timed Block Erase cycle (whose duration is tBE) is initiated. While
the Block Erase cycle is in progress, the Status Register may be
read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Block Erase
cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is
reset. A 64KB Block Erase (BE) command applied to a block which
is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0)
bits is not executed.
The 64KB Block Erase command sequence: CS# goes low
sending 64KB Block Erase command 3-byte address on SI
CS# goes high. The command sequence is shown in Figure19.
CS# must be driven high after the eighth bit of the last address
Figure19. 64KB Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
D8H
24 Bits Address
23 22
MSB
SI
2
1
0
7.18. Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is erased the all data of the chip.
A Write Enable (WREN) command must previously have been
executed to set the Write Enable Latch (WEL) bit .The Chip Erase
(CE) command is entered by driving CS# Low, followed by the
command code on Serial Data Input (SI). CS# must be driven Low
for the entire duration of the sequence.
the self-timed Chip Erase cycle (whose duration is tCE) is initiated.
While the Chip Erase cycle is in progress, the Status Register may
be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Chip Erase
cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is
reset. The Chip Erase (CE) command is executed if the Block
Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block
Protect (BP2, BP1, and BP0) bits are 1 and CMP=1. The Chip
Erase (CE) command is ignored if one or more sectors are
protected
The Chip Erase command sequence: CS# goes low sending
Chip Erase command CS# goes high. The command sequence
is shown in Figure20. CS# must be driven high after the eighth bit
of the command code has been latched in; otherwise the Chip
Erase command is not executed. As soon as CS# is driven high,
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Figure20. Chip Erase Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
Command
60H or C7H
7.19. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way
to put the device in the lowest consumption mode (the Deep
Power-Down Mode). It can also be used as an extra software
protection mechanism, while the device is not in active use, since
in this mode, the device ignores all Write, Program and Erase
commands. Driving CS# high deselects the device, and puts the
device in the Standby Mode (if there is no internal cycle currently
in progress). But this mode is not the Deep Power-Down Mode.
The Deep Power-Down Mode can only be entered by executing
the Deep Power-Down (DP) command. Once the device has
entered the Deep Power-Down Mode, all commands are ignored
except the Release from Deep Power-Down and Read Device ID
(RDI) (ABH) or Enable Reset (66H) and Reset (99H) commands.
These commands can release the device from this mode. The
Release from Deep Power-Down and Read Device ID (RDI)
command releases the device from deep power down mode , also
allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down,
and the device is in the Standby Mode after Power-Up. The Deep
Power-Down (DP) command is entered by driving CS# low,
followed by the command code on SI. CS# must be driven low for
the entire duration of the sequence.
The Deep Power-Down command sequence: CS# goes low
sending Deep Power-Down command CS# goes high. The
command sequence is shown in Figure21. CS# must be driven
high after the eighth bit of the command code has been latched in;
otherwise the Deep Power-Down (DP) command is not executed.
As soon as CS# is driven high, it requires a delay of tDP before the
supply current is reduced to ICC2 and the Deep Power-Down Mode
is entered. Any Deep Power-Down (DP) command, while an Erase,
Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure21. Deep Power-Down Sequence Diagram
CS#
SCLK
SI
tDP
0
1 2 3 4 5 6 7
Command
B9H
Stand-by mode Deep Power-down mode
7.20. Release from Deep Power-Down and Read Device ID (RDI) (ABH)
is issued by driving the CS# pin low, shifting the instruction code
The Release from Power-Down and Read Device ID command is a
multi-purpose command. It can be used to release the device from
the Power-Down state or obtain the devices electronic identification
(ID) number.
“ABH” and driving CS# high as shown below. Release from
Power-Down will take the time duration of tRES1 (See AC
Characteristics) before the device will resume normal operation
and other command are accepted. The CS# pin must remain
high during the tRES1 time duration.
To release the device from the Power-Down state, the command
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When used only to obtain the Device ID while not in the Power-
Down state, the command is initiated by driving the CS# pin low
and shifting the instruction code “ABH” followed by 3-dummy byte.
The Device ID bits are then shifted out on the falling edge of SCLK
with most significant bit (MSB) first as shown below. The Device
ID value is listed in Manufacturer and Device Identification table.
The Device ID can be read continuously. The command is
completed by driving CS# high.
and obtain the Device ID, the command is the same as
previously described, except that after CS# is driven high it
must remain high for
a time duration of tRES2 (See AC
Characteristics). After this time duration the device will resume
normal operation and other command will be accepted. If the
Release from Power-Down / Device ID command is issued while
an Erase, Program or Write cycle is in process (when WIP equal
1) the command is ignored and will not have any effects on the
current cycle.
When used to release the device from the Power-Down state
Figure22. Release Power-Down Sequence Diagram
CS#
SCLK
SI
tRES1
0
1
2
3
4
5
6
7
Command
ABH
Deep Power-down mode
Stand-by mode
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Figure23. Release Power-Down/Read Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38
SCLK
tRES2
Command
ABH
3 Dummy Bytes
SI
23 22
MSB
2
1
0
Device ID
SO
High-Z
7
6
5
4
3
2
1
0
MSB
Deep Power-down Mode Stand-by Mode
7.21. Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to
the Release from Power-Down / Device ID command that provides
both the JEDEC assigned Manufacturer ID and the specific Device
ID.
the command code “90H” followed by a 24-bit address (A23-A0) of
000000H. After which, the Manufacturer ID and the Device ID are
shifted out on the falling edge of SCLK with most significant bit
(MSB) first as shown in Figure24. If the 24-bit address is initially
set to 000001H, the Device ID will be read first.
The command is initiated by driving the CS# pin low and shifting
Figure24. Read Manufacture ID/ Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
24-bit address
23 22 21
SI
90H
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
Device ID
Manufacturer ID
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
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7.22. Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit
manufacturer identification to be read, followed by two bytes of
device identification. The device identification indicates the
memory type in the first byte, and the memory capacity of the
device in the second byte. The Read Identification (RDID)
command while an Erase or Program cycle is in progress is not
decoded, and has no effect on the cycle that is in progress. The
Read Identification (RDID) command should not be issued while
the device is in Deep Power-Down Mode.
The device is first selected by driving CS# low. Then, the 8-bit
command code for the command is shifted in. This is followed by
the 24-bit device identification, stored in the memory. Each bit is
shifted out on the falling edge of Serial Clock. The command
sequence is shown in Figure25. The Read Identification (RDID)
command is terminated by driving CS# high at any time during data
output. When CS# is driven high, the device is in the Standby
Mode. Once in the Standby Mode, the device waits to be selected,
so that it can receive, decode and execute commands.
Figure25. Read Identification ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
9FH
Command
Manufacturer ID
7
6
5
4
3
2
1
0
SO
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Memory Type
JDID15-JDID8
Capacity
JDID7-JDID0
MSB
MSB
7.23. Program/Erase Suspend (PES) (75H)
The Program/Erase Suspend command “75H”, allows the system
to interrupt a page program or sector/block erase operation and
then read data from any other sector or block. The Write Status
Register command (01H/31H/11H) and Erase/Program Security
Registers command (44H, 42H) and Erase commands (20H, 52H,
D8H, C7H, 60H) and Page Program command (02H, 32H) are not
allowed during Program suspend. The Write Status Register
command (01H/31H/11H) and Erase Security Registers command
(44H) and Erase commands (20H, 52H, D8H, C7H, 60H) are not
allowed during Erase suspend. Program/Erase Suspend is valid
only during the page program or sector/block erase operation. A
maximum of time of “tsus” (See AC Characteristics) is required to
suspend the program/erase operation.
The Program/Erase Suspend command will be accepted by the
device only if the SUS2/SUS1 bit in the Status Register equal to 0
and WIP bit equal to 1 while a Page Program or a Sector or Block
Erase operation is on-going. If the SUS2/SUS1 bit equal to 1 or
WIP bit equal to 0, the Suspend command will be ignored by the
device. The WIP bit will be cleared from 1 to 0 within “tsus” and the
SUS2/SUS1 bit will be set from 0 to 1 immediately after
Program/Erase Suspend. A power-off during the suspend period
will reset the device and release the suspend state. The command
sequence is show in Figure26.
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Figure26. Program/Erase Suspend Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
tSUS
Command
75H
High-Z
SO
Accept read command
7.24. Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume
the program or sector/block erase operation after a Program/Erase
Suspend command. The Program/Erase command will be
accepted by the device only if the SUS2/SUS1 bit equal to 1 and
the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status
register will be cleared from 1 to 0 immediately, the WIP bit will be
set from 0 to 1 within 200ns and the Sector or Block will complete
the erase operation or the page will complete the program
operation. The Program/Erase Resume command will be ignored
unless a Program/Erase Suspend is active. The command
sequence is show in Figure27.
Figure27. Program/Erase Resume Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
Command
7AH
SO
Resume Erase/Program
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GPR25L12806F
7.25. Erase Security Registers (44H)
The GPR25L12806F provides three 1024-byte Security Registers
which can be erased and programmed individually. These
registers may be used by the system manufacturers to store
security and other important information separately from the main
memory array.
latched in; otherwise the Erase Security Registers command is not
executed. As soon as CS# is driven high, the self-timed Erase
Security Registers cycle (whose duration is tSE) is initiated. While
the Erase Security Registers cycle is in progress, the Status
Register may be read to check the value of the Write in Progress
(WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed
Erase Security Registers cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset. The Security Registers Lock Bit
(LB3-1) in the Status Register can be used to OTP protect the
security registers. Once the LB bit is set to 1, the Security
Registers will be permanently locked; the Erase Security Registers
command will be ignored.
The Erase Security Registers command is similar to Sector/Block
Erase command. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL)
bit.
The Erase Security Registers command sequence: CS# goes low
sending Erase Security Registers command CS# goes high.
The command sequence is shown in Figure28. CS# must be
driven high after the eighth bit of the command code has been
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-10
0 0
A9-0
Security Register #1
Security Register #2
Security Register #3
Do not care
Do not care
Do not care
00H
0 0
00H
0 0
Figure28. Erase Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
44H
24 Bits Address
23 22
MSB
SI
2
1
0
7.26. Program Security Registers (42H)
The Program Security Registers command is similar to the Page
Program command. It allows from 1 to 1024 bytes Security
Registers data to be programmed. A Write Enable (WREN)
command must previously have been executed to set the Write
Enable Latch (WEL) bit before sending the Program Security
Registers command. The Program Security Registers command is
entered by driving CS# Low, followed by the command code (42H),
three address bytes and at least one data byte on SI. As soon as
CS# is driven high, the self-timed Program Security Registers
cycle (whose duration is tPP) is initiated. While the Program
Security Registers cycle is in progress, the Status Register may be
read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Program
Security Registers cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security
Registers will be permanently locked. Program Security Registers
command will be ignored.
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
A11-10
0 0
A9-0
Security Register #1
Security Register #2
Byte Address
Byte Address
00H
0 0
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GPR25L12806F
Security Register #3
00H
0 0 1 1
0 0
Byte Address
Figure29. Program Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
42H
24-bit address
23 22 21
MSB
Data Byte 1
SI
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
SI
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
7.27. Read Security Registers (48H)
MSB
MSB
The Read Security Registers command is similar to Fast Read
command. The command is followed by a 3-byte address (A23-A0)
and a dummy byte, each bit being latched-in during the rising edge
of SCLK. Then the memory content, at that address, is shifted out
on SO, each bit being shifted out, at a Max frequency fC, during
the falling edge of SCLK. The first byte addressed can be at any
location. The address is automatically incremented to the next
higher address after each byte of data is shifted out. Once the A9-
A0 address reaches the last byte of the register (Byte 3FFH), it will
reset to 000H, the command is completed by driving CS# high.
Address
A23-16
00H
A15-12
A11-10
0 0
A9-0
Security Register #1
Security Register #2
Security Register #3
0 0 0 1
0 0 1 0
0 0 1 1
Byte Address
Byte Address
Byte Address
00H
0 0
00H
0 0
Figure30. Read Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
48H
24-bit address
23 22 21
SI
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
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GPR25L12806F
Figure31. The Global Block/Sector Unlock Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5 6 7
Command
98H
High-Z
SO
7.28. Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation
will be terminated and the device will return to its default power-on
state and lose all the current volatile settings, such as Volatile
Status Register bits, Write Enable Latch status (WEL),
Program/Erase Suspend status, Read Parameter setting (P7-P0),
Continuous Read Mode bit setting (M7-M0) and Wrap Bit Setting
(W6-W4).
command CS# goes high CS# goes low Sending Reset
command CS# goes high. Once the Reset command is
accepted by the device, the device will take approximately tRST
/
tRST_E to reset. During this period, no command will be accepted.
Data corruption may happen if there is an on-going or suspended
internal Erase or Program operation when Reset command
sequence is accepted by the device. It is recommended to check
the BUSY bit and the SUS bit in Status Register before issuing the
Reset command sequence.
The “Enable Reset (66H)” and the “Reset (99H)” commands can
be issued in either SPI mode. The “Reset (99H)” command
sequence as follow: CS# goes low Sending Enable Reset
Figure32. Enable Reset and Reset command Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6 7
Command
66H
Command
99H
High-Z
SO
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GPR25L12806F
8. ELECTRICAL CHARACTERISTICS
8.1.
POWER-ON TIMING
Figure 33. Power-on Timing Sequence Diagram
Vcc(max)
Vcc(min)
VWI
Chip Selection is not allowed
Device is fully
accessible
tVSL
Time
Table 8.1. Power-Up Timing and Write Inhibit Threshold
Parameter
Symbol
Min
Max
Unit
ms
tVSL
VWI
VCC(min) To CS# Low
Write Inhibit Voltage
5
1.5
2.5
V
8.2.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register bits are set
to 0, except DRV1 bit (S22) is set to 1.
8.3.
ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
Ambient Operating Temperature
Storage Temperature
-40 to 85
℃
℃
V
-65 to 150
Applied Input/Output Voltage
Transient Input/Output Voltage (note: overshoot)
VCC
-0.6 to VCC+0.4
-2.0 to VCC+2.0
-0.6 to 4.2
V
V
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GPR25L12806F
Figure 34. Maximum Negative/positive Overshoot Diagram
Maximum Negative Overshoot Waveform
20ns
Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
8.4.
CAPACITANCE MEASUREMENT CONDITIONS
Symbol
Parameter
Min
Typ.
Max
6
Unit
Conditions
CIN
COUT
CL
Input Capacitance
pF
pF
pF
ns
V
VIN=0V
Output Capacitance
8
VOUT=0V
Load Capacitance
30
Input Rise And Fall time
Input Pulse Voltage
5
0.1VCC to 0.8VCC
0.2VCC to 0.7VCC
0.5VCC
Input Timing Reference Voltage
Output Timing Reference Voltage
V
V
Figure 35. Input Test Waveform and Measurement Level
Input timing reference level
0.7VCC
Output timing reference level
0.5VCC
0.8VCC
0.1VCC
AC Measurement Level
0.2VCC
Note: Input pulse rise and fall time are <5ns
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GPR25L12806F
8.5.
DC CHARACTERISTICS
(T= -40℃~85℃, VCC=2.7~3.6V, Normal Mode)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Standby Current
Test Condition
Min.
Typ.
Max.
±2
Unit.
μA
ILO
±2
μA
ICC1
CS#=VCC,
20
1
50
μA
VIN=VCC or VSS
CS#=VCC,
ICC2
Deep Power-Down Current
5
μA
mA
mA
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 104MHz,
15
13
20
18
Q=Open(*1 I/O)
CLK=0.1VCC / 0.9VCC
at 80MHz,
ICC3
Operating Current (Read)
Q=Open(*1,*2,*4 I/O)
CS#=VCC
ICC4
ICC5
ICC6
ICC7
ICC8
VIL
Operating Current (PP)
Operating Current(WRSR)
Operating Current (SE)
Operating Current (BE)
Operating Current (CE)
Input Low Voltage
25
25
mA
mA
mA
mA
mA
V
CS#=VCC
CS#=VCC
25
CS#=VCC
25
CS#=VCC
25
0.2VCC
VCC+0.4
0.2
VIH
Input High Voltage
0.7VCC
VCC-0.2
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL =100uA
V
IOH =-100μA
V
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GPR25L12806F
(T= -40℃~85℃, VCC=2.7~3.6V, Low Power Mode)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Standby Current
Test Condition
Min.
Typ.
Max.
±2
Unit.
μA
ILO
±2
μA
ICC1
CS#=VCC,
20
50
μA
VIN=VCC or VSS
CS#=VCC,
ICC2
Deep Power-Down Current
0.1
5
μA
mA
mA
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 104MHz,
13
10
18
15
Q=Open(*1 I/O)
CLK=0.1VCC / 0.9VCC
at 80MHz,
ICC3
Operating Current (Read)
Q=Open(*1,*2,*4 I/O)
CS#=VCC
ICC4
ICC5
ICC6
ICC7
ICC8
VIL
Operating Current (PP)
Operating Current(WRSR)
Operating Current (SE)
Operating Current (BE)
Operating Current (CE)
Input Low Voltage
15
15
mA
mA
mA
mA
mA
V
CS#=VCC
CS#=VCC
15
CS#=VCC
15
CS#=VCC
15
0.2VCC
VCC+0.4
0.2
VIH
Input High Voltage
0.7VCC
VCC-0.2
V
VOL
VOH
Output Low Voltage
IOL =100uA
V
Output High Voltage
IOH =-100μA
V
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GPR25L12806F
8.6.
AC CHARACTERISTICS
(T= -40℃~85℃, VCC=2.7~3.6V, CL=30pf, Normal Mode)
Symbol
Parameter
Serial Clock Frequency For: Fast Read(0BH), on 2.7V-3.6V power
supply
Min.
Typ.
Max.
Unit.
FC
DC.
104
MHz
Serial Clock Frequency For: Dual Output(3BH), Quad Output(6BH),
Dual I/O(BBH), Quad I/O(EBH), Quad I/O Word ,on 2.7V-3.0V power
supply
fC1
DC.
80
MHz
Serial Clock Frequency For: Dual Output (3BH), Quad Output(6BH),
Dual I/O(BBH), Quad I/O(EBH), Quad I/O Word ,on 3.0V-3.6V power
supply
fC2
DC.
DC.
104
80
MHz
MHz
Serial Clock Frequency For: Read(03H), Read Manufacturer ID/device
ID(90H), Read Identification(9FH)
fR
tCLH
tCLL
Serial Clock High Time
4.5
4.5
0.1
0.1
5
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
Serial Clock Low Time
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
tCLQV
tWHSL
tSHWL
tDP
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
CS# Active Hold Time
5
CS# Not Active Setup Time
5
CS# Not Active Hold Time
5
CS# High Time (read/write)
20
Output Disable Time
6
Output Hold Time
1.0
2
Data In Setup Time
Data In Hold Time
2
HOLD# Low Setup Time (relative to Clock)
HOLD# High Setup Time (relative to Clock)
HOLD# High Hold Time (relative to Clock)
HOLD# Low Hold Time (relative to Clock)
HOLD# Low To High-Z Output
5
5
5
5
6
6
7
HOLD# Low To Low-Z Output
Clock Low To Output Valid
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High To Deep Power-Down Mode
CS# High To Standby Mode Without Electronic Signature Read
CS# High To Standby Mode With Electronic Signature Read
CS# High To Next Command After Suspend
20
100
20
30
30
20
tRES1
tRES2
tSUS
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GPR25L12806F
tRST
tRST_E
tW
CS# High To Next Command After Reset (except from erase)
CS# High To Next Command After Reset (from erase)
Write Status Register Cycle Time
Byte Program Time( First Byte)
30
12
μs
ms
ms
μs
μs
ms
ms
s
5
30
tBP1
tBP2
tPP
30
50
Additional Byte Program Time ( After First Byte)
Page Programming Time
2.5
0.6
50
12
4
tSE
Sector Erase Time
500
2.0
2.5
200
tBE
Block Erase Time(32K Bytes)
0.2
0.3
60
tBE
Block Erase Time(64K Bytes)
s
tCE
Chip Erase Time(GPR25L12806F)
s
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GPR25L12806F
(T= -40℃~85℃, VCC=2.7~3.6V, CL=30pf, Low Power Mode)
Symbol
Parameter
Serial Clock Frequency For: Fast Read(0BH), on 2.7V-3.6V power
supply
Min.
Typ.
Max.
Unit.
FC
DC.
104
MHz
Serial Clock Frequency For: Dual Output(3BH), Quad Output(6BH),
Dual I/O(BBH), Quad I/O(EBH), Quad I/O Word, on 2.7V-3.0V power
supply
fC1
DC.
80
MHz
Serial Clock Frequency For: Dual Output (3BH), Quad Output(6BH),
Dual I/O(BBH), Quad I/O(EBH), Quad I/O Word, on 3.0V-3.6V power
supply
fC2
DC.
DC.
104
80
MHz
MHz
Serial Clock Frequency For: Read(03H), Read Manufacturer ID/device
ID(90H), Read Identification(9FH)
fR
tCLH
tCLL
Serial Clock High Time
4.5
4.5
0.1
0.1
5
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
ms
Serial Clock Low Time
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
tCLQV
tWHSL
tSHWL
tDP
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
CS# Active Hold Time
5
CS# Not Active Setup Time
5
CS# Not Active Hold Time
5
CS# High Time (read/write)
20
Output Disable Time
6
Output Hold Time
1.0
2
Data In Setup Time
Data In Hold Time
2
HOLD# Low Setup Time (relative to Clock)
HOLD# High Setup Time (relative to Clock)
HOLD# High Hold Time (relative to Clock)
HOLD# Low Hold Time (relative to Clock)
HOLD# Low To High-Z Output
5
5
5
5
6
6
7
HOLD# Low To Low-Z Output
Clock Low To Output Valid
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High To Deep Power-Down Mode
CS# High To Standby Mode Without Electronic Signature Read
CS# High To Standby Mode With Electronic Signature Read
CS# High To Next Command After Suspend
CS# High To Next Command After Reset (except from erase)
CS# High To Next Command After Reset (from erase)
20
100
50
50
50
50
50
30
tRES1
tRES2
tSUS
tRST
tRST_E
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GPR25L12806F
tW
tBP1
tBP2
tPP
tSE
tBE
tBE
tCE
Write Status Register Cycle Time
Byte Program Time( First Byte)
Additional Byte Program Time ( After First Byte)
Page Programming Time
15
60
80
150
40
5
ms
μs
μs
ms
ms
s
8
1.6
100
0.3
0.5
150
Sector Erase Time
800
2
Block Erase Time(32K Bytes)
Block Erase Time(64K Bytes)
Chip Erase Time(GPR25L12806F)
3
s
400
s
Figure36. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tCLCH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
SI
MSB
High-Z
LSB
SO
Figure37. Output Timing
CS#
tCLH
tSHQZ
SCLK
tCLQV
tCLQV
tCLQX
tCLL
tCLQX
SO
SI
LSB
Least significant address bit (LIB) in
Figure38. Hold Timing
CS#
tCHHL
tHLCH
tHHCH
tHHQX
SCLK
tCHHH
tHLQZ
SO
HOLD#
SI do not care during HOLD operation.
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GPR25L12806F
Figure39 RESET Timing
tRB1
tRB2
CS#
RESET#
tRLRH
tRHSL
Reset Timing
Symbol
tRLRH
Parameter
Setup
MIN
Speed
Unit.
us
Reset pulse width
1
50
5
tRHSL
Reset high time before read
MIN
ns
tRB1
Reset recovery time(For NOT busy mode)
Reset recovery time(For busy mode)
MAX
MAX
us
tRB2
60
us
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GPR25L12806F
9. ORDERING INFORMATION
9.1.
Valid Part Numbers
Product Number
GPR25L12806F-QS13x
Package Type
SOP 8L 208mil-Halogen Free Package
Note: x = 1 - 9, serial number.
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GPR25L12806F
10. PACKAGE INFORMATION
10.1. Package Outline for SOP 8L (208MIL)
D
8
5
E
E1
L1
L
1
4
“A”
θ
b
Base Metal
A
A2
c
Detail “A”
A1
b
e
Dimensions
Symbol
Unit
A
A1
A2
b
c
D
E
E1
e
L
L1
θ
Min
-
-
0.05
0.15
0.25
1.70
1.80
1.90
0.31
0.41
0.51
0.15
0.20
0.25
5.13
5.23
5.33
7.70
7.90
8.10
5.18
5.28
5.38
0.50
-
0°
-
mm
Nom
Max
1.27
1.31
2.16
0.85
8°
Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.
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GPR25L12806F
11. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
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GPR25L12806F
12. REVISION HISTORY
Date
Revision
Description
Page
Jul. 30, 2018
1.0
Original
All
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Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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