GPR25L162B_技术文档

GPR25L162B

16M-BIT [x1 / x2] CMOS SERIAL FLASH

Apr. 09, 2014

Version 1.4

GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS

TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may

appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No

responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.

In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a

malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.

GPR25L162B

Table of Contents

PAGE

1. FEATURES.................................................................................................................................................................................................. 4

1.1. GENERAL............................................................................................................................................................................................ 4

1.2. PERFORMANCE...................................................................................................................................................................................... 4

1.3. SOFTWARE FEATURES ........................................................................................................................................................................... 4

1.4. HARDWARE FEATURES .......................................................................................................................................................................... 4

2. GENERAL DESCRIPTION.......................................................................................................................................................................... 5

3. PIN CONFIGURATIONS ............................................................................................................................................................................. 5

3.1. 8-PIN SOP (150MIL, 200MIL) ................................................................................................................................................................ 5

4. PIN DESCRIPTION...................................................................................................................................................................................... 5

5. BLOCK DIAGRAM ...................................................................................................................................................................................... 6

6. MEMORY ORGANIZATION ........................................................................................................................................................................ 7

7. DEVICE OPERATION ................................................................................................................................................................................. 8

8. DATA PROTECTION................................................................................................................................................................................... 9

9. HOLD FEATURE....................................................................................................................................................................................... 11

10.COMMAND DESCRIPTION ...................................................................................................................................................................... 12

10.1.WRITE ENABLE (WREN)...................................................................................................................................................................... 13

10.2.WRITE DISABLE (WRDI) ...................................................................................................................................................................... 13

10.3.READ STATUS REGISTER (RDSR)........................................................................................................................................................ 13

10.4.WRITE STATUS REGISTER (WRSR)...................................................................................................................................................... 13

10.5.READ DATA BYTES (READ)................................................................................................................................................................. 14

10.6.READ DATA BYTES AT HIGHER SPEED (FAST_READ) ......................................................................................................................... 14

10.7.DUAL OUTPUT MODE (DREAD) ........................................................................................................................................................... 14

10.8.SECTOR ERASE (SE)........................................................................................................................................................................... 15

10.9.BLOCK ERASE (BE) ............................................................................................................................................................................. 15

10.10. CHIP ERASE (CE) ........................................................................................................................................................................... 15

10.11. PAGE PROGRAM (PP) ..................................................................................................................................................................... 15

10.12. DEEP POWER-DOWN (DP)............................................................................................................................................................... 16

10.13. RELEASE FROM DEEP POWER-DOWN (RDP), READ ELECTRONIC SIGNATURE (RES)......................................................................... 16

10.14. READ IDENTIFICATION (RDID) ......................................................................................................................................................... 16

10.15. READ ELECTRONIC MANUFACTURER ID & DEVICE ID (REMS).......................................................................................................... 16

10.16. ENTER SECURED OTP (ENSO)....................................................................................................................................................... 17

10.17. EXIT SECURED OTP (EXSO) .......................................................................................................................................................... 17

10.18. READ SECURITY REGISTER (RDSCUR)........................................................................................................................................... 17

10.19. WRITE SECURITY REGISTER (WRSCUR)......................................................................................................................................... 17

11.POWER-ON STATE .................................................................................................................................................................................. 18

11.1.INITIAL DELIVERY STATE ...................................................................................................................................................................... 18

12.ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 19

12.1.ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 19

12.2.CAPACITANCE TA = 25°C, F = 1.0 MHZ................................................................................................................................................ 19

12.3.DC CHARACTERISTICS......................................................................................................................................................................... 21

12.4.AC CHARACTERISTICS......................................................................................................................................................................... 21

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12.5.TIMING ANALYSIS................................................................................................................................................................................. 23

13.RECOMMENDED OPERATING CONDITIONS ........................................................................................................................................ 32

13.1.AT DEVICE POWER-UP AND POWER-DOWN........................................................................................................................................... 32

14.ERASE AND PROGRAMMING PERFORMANCE.................................................................................................................................... 33

14.1.DATA RETENTION ................................................................................................................................................................................ 33

15.LATCH-UP CHARACTERISTICS ............................................................................................................................................................. 33

16.PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 34

16.1.ORDERING INFORMATION ..................................................................................................................................................................... 34

16.2.PACKAGE INFORMATION ....................................................................................................................................................................... 35

16.2.1. Package Outline for SOP 8L (150MIL)............................................................................................................................... 35

16.2.2. Package Outline for SOP 8L (200MIL)............................................................................................................................... 36

17.DISCLAIMER............................................................................................................................................................................................. 37

18.REVISION HISTORY................................................................................................................................................................................. 38

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16M-BIT [x 1/ x 2] CMOS SERIAL FLASH

1. FEATURES

1.1. GENERAL

- Deep power-down mode 5uA (typical)

y Typical 100,000 erase/program cycles

y 20 years of data retention

y Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program operations

y Serial Peripheral Interface compatible -- Mode 0 and Mode 3

y 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (Dual Output

mode) structure

1.3. Software Features

y Input Data Format

- 1-byte Command code

y Advanced Security Features

y 512 Equal Sectors with 4K byte each

- Any Sector can be erased individually

y 32 Equal Blocks with 64K byte each

- Any Block can be erased individually

y Program Capability

- Block lock protection

- The BP3-BP0 status bit defines the size of the area to be

software protection against program and erase instructions

- Additional 512 bit secured OTP for unique identifier

y Auto Erase and Auto Program Algorithm

- Automatically erases and verifies data at selected sector

- Automatically programs and verifies data at selected page by

an internal algorithm that automatically times the program

pulse widths (Any page to be programmed should have page

in the erased state first)

- Byte base

- Page base (256 bytes)

y Latch-up protected to 100mA from -1V to V_CC+1V

y GPR25L162B is compatible with MX25L1606E

1.2. Performance

y Status Register Feature

y High Performance

y Electronic Identification

- Fast access time: 86MHz serial clock

- Serial clock of Dual Output mode : 80MHz

- Fast program time: 1.4ms(typ.) and 5ms(max.)/page

- Byte program time: 9us (typical)

- JEDEC 1-byte manufacturer ID and 2-byte device ID

- RES command for 1-byte Device ID

- REMS commands for 1-byte manufacturer ID and 1-byte

device ID

- Fast erase time: 60ms(typ.) /sector ; 0.7s(typ.) /block

y Low Power Consumption

1.4. Hardware Features

- Low active read current: 25mA(max.) at 86MHz

- Low active programming current: 20mA (max.)

- Low active erase current: 20mA (max.)

- Low standby current: 25uA (max.)

y

PACKAGE

- 8-pin SOP (150mil)

- 8-pin SOP (200mil)

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2. GENERAL DESCRIPTION

3. PIN CONFIGURATIONS

3.1. 8-PIN SOP (150mil, 200mil)

The device feature a serial peripheral interface and software

protocol allowing operation on a simple 3-wire bus. The three

bus signals are a clock input (SCLK), a serial data input (SI), and

a serial data output (SO). Serial access to the device is enabled

by CS# input.

When it is in Dual Output read mode, the SI and SO pins become

SIO0 and SIO1 pins for data output.

The device provides sequential read operation on whole chip.

After program/erase command is issued, auto program/ erase

algorithms which program/ erase and verify the specified page or

sector/block locations will be executed. Program command is

executed on byte basis, or page basis, or word basis for erase

command is executes on sector, or block, or whole chip basis.

4. PIN DESCRIPTION

Symbol

Description

CS#

Chip Select

Serial Data Input (for 1 x I/O)/ Serial Data Input

& Output (for Dual Output mode)

Serial Data Output (for 1 x I/O)/ Serial Data

Output (for Dual Output mode)

Clock Input

SI/SIO0

To provide user with ease of interface, a status register is

included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program

or erase operation via WIP bit.

SO/SIO1

SCLK

WP#

Write protection

Hold, to pause the device without deselecting

the device

HOLD#

Advanced security features enhance the protection and security

functions, please see security features section for more details.

When the device is not in operation and CS# is high, it is put in

standby mode.

VCC

GND

+ 3.3V Power Supply

Ground

The GPR25L162B reliably stores memory contents even after

typical 100,000 program and erase cycles.

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5. BLOCK DIAGRAM

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6. MEMORY ORGANIZATION

Table 1. Memory Organization

Block

Sector

511

:

Address Range

1FF000h

:

1FFFFFh

:

31

30

496

495

:

1F0000h

1EF000h

:

1F0FFFh

1EFFFFh

:

480

1E0000h

1E0FFFh

:

15

:

00F000h

:

00FFFFh

:

3

2

1

0

003000h

002000h

001000h

000000h

003FFFh

002FFFh

001FFFh

000FFFh

0

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7. DEVICE OPERATION

1. Before a command is issued, status register should be

checked to ensure device is ready for the intended operation.

2. When incorrect command is inputted to this LSI, this LSI

becomes standby mode and keeps the standby mode until

next CS# falling edge. In standby mode, SO pin of this LSI

should be High-Z. The CS# falling time needs to follow

tCHCL spec.

5. For the following instructions: RDID, RDSR, RDSCUR,

READ, FAST_READ, DREAD, RES, and REMS the shift-

ed-in instruction sequence is followed by

a data-out

sequence. After any bit of data being shifted out, the CS#

can be high. For the following instructions: WREN, WRDI,

WRSR, SE, BE, CE, PP, RDP, DP, ENSO, EXSO, and

WRSCUR, the CS# must go high exactly at the byte

boundary; otherwise, the instruction will be rejected and not

executed.

3. When correct command is inputted to this LSI, this LSI

becomes active mode and keeps the active mode until next

CS# rising edge.

6. During the progress of Write Status Register, Program, Erase

operation, to access the memory array is neglected and not

affect the current operation of Write Status Register, Program,

Erase.

4. Input data is latched on the rising edge of Serial Clock(SCLK)

and data shifts out on the falling edge of SCLK. The

difference of Serial mode 0 and mode 3 is shown in Figure 1.

Figure1. Serial Modes Supported

Note:

CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase.

The combination of CPOL bit and CPHA bit decides which Serial mode is supported.

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8. DATA PROTECTION

The device is designed to offer protection against accidental

erasure or programming caused by spurious system level signals

that may exist during power transition. During power up the

device automatically resets the state machine in the standby mode.

In addition, with its control register architecture, alteration of the

memory contents only occurs after successful completion of

specific command sequences. The device also incorporates

several features to prevent inadvertent write cycles resulting from

VCC power-up and power-down transition or system noise.

-

Block Erase (BE) command completion

Chip Erase (CE) command completion

•

Deep Power Down Mode: By entering deep power down mode,

the flash device also is under protected from writing all

commands except Release from deep power down mode

command (RDP) and Read Electronic Signature command

(RES).

Advanced Security Features: there are some protection and

security features which protect content from inadvertent write

and hostile access.

•

Valid command length checking: The command length will be

checked whether it is at byte base and completed on byte

boundary.

I. Block lock protection

•

Write Enable (WREN) command: WREN command is required

to set the Write Enable Latch bit (WEL) before other command

to change data. The WEL bit will return to reset stage under

following situation:

- The Software Protected Mode (SPM):

Use (BP3, BP2, BP1, BP0) bits to allow part of memory to be

protected as read only. The protected area definition is shown as

table of "Protected Area Sizes", the protected areas are more

flexible which may protect various area by setting value of

BP0-BP3 bits.

-

Power-up

Write Disable (WRDI) command completion

Write Status Register (WRSR) command completion

Page Program (PP) command completion

Sector Erase (SE) command completion

Please refer to table of "protected area sizes".

- The Hardware Protected Mode (HPM) uses WP# to protect the

BP3-BP0 bits and SRWD bit.

Table2. Protected Area Sizes

Status bit

Protect Level

BP3

0

BP2

BP1

0

BP0

0

1

0

1

0 (none)

0

1

1 (1block, block 31th)

2 (2blocks, block 30th-31th)

3 (4blocks, block 28th-31th)

4 (8blocks, block 24th-31th)

5 (16blocks, block 16th-31th)

6 (32blocks, all)

0

1

0

1

0

1

0

1

0

1

7 (32blocks, all)

1

0

8 (32blocks, all)

1

0

1

9 (32blocks, all)

1

0

10 (16blocks, block 0th-15th)

11 (24blocks, block 0th-23th)

12 (28blocks, block 0th-27th)

13 (30blocks, block 0th-29th)

14 (31blocks, block 0th-30th)

15 (32blocks, all)

1

0

1

0

1

0

1

II. Additional 512 bit secured OTP for unique identifier: to

provide 512 bit one-time program area for setting device unique

serial number - Which may be set by factory or system customer.

Please refer to table 3. 512 bit secured OTP definition.

-

Security register bit 0 indicates whether the chip is locked

by factory or not.

To program the 512 bit secured OTP by entering 512 bit

secured OTP mode (with ENSO command), and going

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through normal program procedure, and then exiting 512 bit

secured OTP mode by writing EXSO command.

definition and table of "512 bit secured OTP definition" for

address range definition.

Note: Once lock-down whatever by factory or customer, it cannot be

changed any more. While in 512 bit secured OTP mode, array

access is not allowed.

-

Customer may lock-down the customer lockable secured

OTP by writing WRSCUR(write security register) command

to set customer lock-down bit1 as "1". Please refer to

table of "security register definition" for security register bit

Table3. 512 bit Secured OTP Definition

Address range

Size

Standard Factory Lock

ESN (electrical serial number)

N/A

Customer Lock

xxxx00~xxxx0F

128-bit

384-bit

Determined by customer

xxxx10~xxxx3F

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9. HOLD FEATURE

HOLD# pin signal goes low to hold any serial communications with

the device. The HOLD feature will not stop the operation of write

status register, programming, or erasing in progress.

HOLD operation will not start until Serial Clock signal being low).

The HOLD condition ends on the rising edge of HOLD# pin signal

while Serial Clock (SCLK) signal is being low (if Serial Clock signal

is not being low, HOLD operation will not end until Serial Clock

being low), see Figure 2.

The operation of HOLD requires Chip Select (CS#) keeping low

and starts on falling edge of HOLD# pin signal while Serial Clock

(SCLK) signal is being low (if Serial Clock signal is not being low,

Figure1. Hold Condition Operation

The Serial Data Output (SO) is high impedance, both Serial Data

Input (SI) and Serial Clock (SCLK) are don't care during the HOLD

communication with chip, the HOLD# must be at high and CS#

must be at low.

operation.

If Chip Select (CS#) drives high during HOLD

operation, it will reset the internal logic of the device. To re-start

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10. COMMAND DESCRIPTION

Table4. Command Definition

WRSR

RDID

RDSR

FAST READ

READ

Command

(byte)

WREN

WRDI

(write status (read

(read status

(fast

read

(write enable)

(write disable)

(read data)

register)

identification) register)

data)

1st byte

2nd byte

3rd byte

4th byte

5th byte

Action

06 (hex)

04 (hex)

01 (hex)

9F (hex)

05 (hex)

03 (hex)

AD1

AD2

AD3

-

0B (hex)

AD1

-

AD2

AD3

Dummy

sets the (WEL) resets the (WEL) to write new outputs

write enable latch write enable values to the JEDEC

to read out n bytes read n bytes read

ID: the values of out until CS# out until CS#

bit

latch bit

status

1-byte

the

status goes high

goes high

register

Manufacturer

register

ID

& 2-byte

Device ID

Command

(byte)

RES

REMS

DREAD

SE

BE

CE

PP

(page program)

(read

(read electronic (Double Output (sector erase) (block erase)

(chip erase)

electronic ID) manufacturer & Mode

device ID)

command)

1st byte

AB (hex)

90 (hex)

3B (hex)

20 (hex)

52

or

D8 60

(hex)

or

C7 02 (hex)

(hex)

AD1

AD2

AD3

2nd byte

3rd byte

4th byte

5th byte

Action

x

AD1

AD2

AD3

AD1

AD2

AD3

x

AD2

ADD (Note 1)

AD3

Dummy

to read out output

the

Manufacturer

ID & Device ID

n

bytes read to erase the to erase the to

erase to

program

1-byte

out by Dual selected

selected block whole chip

the selected

page

Device ID

Output

until sector

CS# goes high

Command

(byte)

RDSCUR (read WRSCUR (write ENSO (enter EXSO

(exit DP

(Deep RDP (Release

from deep

security

register)

security register)

secured OTP) secured OTP) power down)

power down)

1st byte

2nd byte

3rd byte

4th byte

5th byte

Action

2B (hex)

2F (hex)

B1 (hex)

C1 (hex)

B9 (hex)

AB (hex)

to read value of to

set

the to enter the to exit the 512 enters

deep release

down deep

from

security register lock-down bit as 512

bit bit secured OTP power

mode

power

"1"

(once secured OTP mode

down mode

lock-down, cannot mode

be updated)

Note1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.

Note2: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode.

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10.1. Write Enable (WREN)

whether the device is busy in program/erase/write status register

progress. When WIP bit sets to 1, which means the device is

busy in program/erase/write status register progress. When WIP

bit sets to 0, which means the device is not in progress of

program/erase/write status register cycle.

The Write Enable (WREN) instruction is for setting Write Enable

Latch (WEL) bit. For those instructions like PP, SE, BE, CE, and

WRSR, which are intended to change the device content, should

be set every time after the WREN instruction setting the WEL bit.

The sequence is shown as Figure 11.

WEL bit. The Write Enable Latch (WEL) bit, a volatile bit,

indicates whether the device is set to internal write enable latch.

When WEL bit sets to 1, which means the internal write enable

latch is set, the device can accept program/erase/write status

register instruction. When WEL bit sets to 0, which means no

internal write enable latch; the device will not accept

10.2. Write Disable (WRDI)

The Write Disable (WRDI) instruction is for resetting Write Enable

Latch (WEL) bit.

The sequence is shown as Figure 12.

The WEL bit is reset by following situations:

- Power-up

program/erase/write

status

register

instruction.

The

program/erase command will be ignored and not affect value of

WEL bit if it is applied to a protected memory area.

- Write Disable (WRDI) instruction completion

- Write Status Register (WRSR) instruction completion

- Page Program (PP) instruction completion

- Sector Erase (SE) instruction completion

- Block Erase (BE) instruction completion

- Chip Erase (CE) instruction completion

BP3, BP2, BP1, BP0 bits. The Block Protect (BP3-BP0) bits,

non-volatile bits, indicate the protected area(as defined in table 2)

of the device to against the program/erase instruction without

hardware protection mode being set. To write the Block Protect

(BP3-BP0) bits requires the Write Status Register (WRSR)

instruction to be executed. Those bits define the protected area

of the memory to against Page Program (PP), Sector Erase (SE),

Block Erase (BE) and Chip Erase(CE) instructions (only if all Block

Protect bits set to 0, the CE instruction can be executed).

10.3. Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The

Read Status Register can be read at any time (even in

program/erase/write status register condition) and continuously.

It is recommended to check the Write in Progress (WIP) bit before

sending a new instruction when a program, erase, or write status

register operation is in progress.

SRWD bit. The Status Register Write Disable (SRWD) bit,

non-volatile bit, is operated together with Write Protection (WP#)

pin for providing hardware protection mode. The hardware

protection mode requires SRWD sets to 1 and WP# pin signal is

low stage. In the hardware protection mode, the Write Status

Register (WRSR) instruction is no longer accepted for execution

and the SRWD bit and Block Protect bits (BP3-BP0) are read only.

The sequence is shown as Figure 13.

The definition of the status register bits is as below:

WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates

Status Register for GPR25L162B

bit7

bit6

0

bit5

bit4

BP2

bit3

BP1

bit2

BP0

bit1

bit0

SRWD (status

register write

protect)

BP3

WEL

WIP

(level

of (level

of

(write enable (write

in

protected

block)

(note 1)

protected

latch)

progress bit)

block)

1=status

0

(note 1)

1=write

enable

0=not

1=write

register write

disable

operation

write 0=not in write

operation

enable

volatile bit

Non-volatile bit

0

Non-volatile bit

volatile bit

Note1: see the table "Protected Area Size".

10.4. Write Status Register (WRSR)

the Write Enable Latch (WEL) bit in advance. The WRSR

instruction can change the value of Block Protect (BP3-BP0) bits

to define the protected area of memory (as shown in table 1).

The WRSR also can set or reset the Status Register Write Disable

The WRSR instruction is for changing the values of Status

Register Bits. Before sending WRSR instruction, the Write

Enable (WREN) instruction must be decoded and executed to set

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(SRWD) bit in accordance with Write Protection (WP#) pin signal.

The WRSR instruction cannot be executed once the Hardware

Protected Mode (HPM) is entered.

Write Status Register cycle time (tW) is initiated as soon as Chip

Select (CS#) goes high. The Write in Progress (WIP) bit still can

be check out during the Write Status Register cycle is in progress.

The WIP sets 1 during the tW timing, and sets 0 when Write Status

Register Cycle is completed, and the Write Enable Latch (WEL) bit

is reset.

The sequence is shown as Figure 14.

The WRSR instruction has no effect on b6, b1, b0 of the status

register.

The CS# must go high exactly at the byte boundary; otherwise,

the instruction will be rejected and not executed. The self-timed

Table 5. Protection Modes

Mode

Status register condition

Status register can be written

in (WEL bit is set to "1") and

the SRWD, BP3-BP0 bits can be

changed

WP# and SRWD bit status

Memory

WP#=1 and SRWD bit=0, or

WP#=0 and SRWD bit=0, or

WP#=1 and SRWD=1

Software protection

mode (SPM)

The protected area cannot

be program or erase.

The SRWD, BP3-BP0 of

status register bits cannot be

changed

Hardware protection

mode (HPM)

The protected area cannot

be program or erase.

WP#=0, SRWD bit=1

Note:

1. As defined by the values in the Block Protect (BP3-BP0) bits of the Status Register, as shown in Table 1.

As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).

Software Protected Mode (SPM):

- When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3-BP0. The protected

area, which is defined by BP3-BP0 is at software protected mode (SPM).

- When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3-BP0. The protected area, which is

defined by BP3-BP0, is at software protected mode (SPM)

Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status

Register and not be executed.

Hardware Protected Mode (HPM):

- When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is

protected by software protected mode by BP3-BP0 and hardware protected mode by the WP# to against data modification.

Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. If the WP# pin is permanently connected

to high, the hardware protected mode can never be entered; only can use software protected mode via BP3-BP0.

10.5. Read Data Bytes (READ)

shifts out on the falling edge of SCLK at a maximum frequency fC.

The first address byte can be at any location. The address is

automatically increased to the next higher address after each byte

data is shifted out, so the whole memory can be read out at a

single FAST_READ instruction. The address counter rolls over

to 0 when the highest address has been reached.

The read instruction is for reading data out. The address is

latched on rising edge of SCLK, and data shifts out on the falling

edge of SCLK at a maximum frequency fR. The first address

byte can be at any location. The address is automatically

increased to the next higher address after each byte data is

shifted out, so the whole memory can be read out at a single

READ instruction. The address counter rolls over to 0 when the

highest address has been reached.

The sequence is shown as Figure 16.

While Program/Erase/Write Status Register cycle is in progress,

FAST_READ instruction is rejected without any impact on the

Program/Erase/Write Status Register current cycle.

The sequence is shown as Figure 15.

10.7. Dual Output Mode (DREAD)

10.6. Read Data Bytes at Higher Speed (FAST_READ)

The DREAD instruction enable double throughput of Serial Flash

in read mode. The address is latched on rising edge of SCLK,

The FAST_READ instruction is for quickly reading data out. The

address is latched on rising edge of SCLK, and data of each bit

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and data of every two bits(interleave on 1I/2O pins) shift out on the

falling edge of SCLK at a maximum frequency fT. The first

The self-timed Block Erase Cycle time (tBE) is initiated as soon as

Chip Select (CS#) goes high. The Write in Progress (WIP) bit still

can be check out during the Sector Erase cycle is in progress.

The WIP sets 1 during the tBE timing, and sets 0 when Sector

Erase Cycle is completed, and the Write Enable Latch (WEL) bit is

reset. If the page is protected by BP3-BP0 bits, the Block Erase

(BE) instruction will not be executed on the page.

address byte can be at any location.

The address is

automatically increased to the next higher address after each byte

data is shifted out, so the whole memory can be read out at a

single DREAD instruction. The address counter rolls over to 0

when the highest address has been reached. Once writing

DREAD instruction, the data out will perform as 2-bit instead of

previous 1-bit.

10.10.Chip Erase (CE)

The sequence is shown as Figure 17.

The Chip Erase (CE) instruction is for erasing the data of the

whole chip to be "1". A Write Enable (WREN) instruction must

execute to set the Write Enable Latch (WEL) bit before sending

the Chip Erase (CE). Any address of the sector (see table 3) is a

valid address for Chip Erase (CE) instruction. The CS# must go

high exactly at the byte boundary( the latest eighth of address byte

been latched-in); otherwise, the instruction will be rejected and not

executed.

While Program/Erase/Write Status Register cycle is in progress,

DREAD instruction is rejected without any impact on the

Program/Erase/Write Status Register current cycle.

The DREAD only perform read operation. Program/Erase /Read

ID/Read status....operation do not support DREAD throughputs.

10.8. Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the

chosen sector to be "1". The instruction is used for any 4K-byte

sector. A Write Enable (WREN) instruction must execute to set

the Write Enable Latch (WEL) bit before sending the Sector Erase

(SE). Any address of the sector (see table 3) is a valid address

for Sector Erase (SE) instruction. The CS# must go high exactly

at the byte boundary (the latest eighth of address byte been

latched-in); otherwise, the instruction will be rejected and not

executed.

The sequence is shown as Figure 20.

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as

Chip Select (CS#) goes high. The Write in Progress (WIP) bit still

can be check out during the Chip Erase cycle is in progress. The

WIP sets 1 during the tCE timing, and sets 0 when Chip Erase

Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

If the chip is protected by BP3-BP0 bits, the Chip Erase (CE)

instruction will not be executed. It will be only executed when

BP3-BP0 all set to "0".

Address bits [Am-A12] (Am is the most significant address) select

the sector address.

10.11.Page Program (PP)

The sequence is shown as Figure 18.

The Page Program (PP) instruction is for programming the

memory to be "0". A Write Enable (WREN) instruction must

execute to set the Write Enable Latch (WEL) bit before sending

the Page Program (PP). If the eight least significant address bits

(A7-A0) are not all 0, all transmitted data which goes beyond the

end of the current page are programmed from the start address if

the same page (from the address whose 8 least significant

address bits (A7-A0) are all 0). The CS# must keep during the

whole Page Program cycle. The CS# must go high exactly at the

byte boundary( the latest eighth of address byte been latched-in);

otherwise, the instruction will be rejected and not executed. If

more than 256 bytes are sent to the device, the data of the last

256-byte is programmed at the request page and previous data

will be disregarded. If less than 256 bytes are sent to the device,

the data is programmed at the request address of the page

without effect on other address of the same page.

The self-timed Sector Erase Cycle time (tSE) is initiated as soon

as Chip Select (CS#) goes high. The Write in Progress (WIP) bit

still can be check out during the Sector Erase cycle is in progress.

The WIP sets 1 during the tSE timing, and sets 0 when Sector

Erase Cycle is completed, and the Write Enable Latch (WEL) bit is

reset. If the page is protected by BP3-BP0 bits, the Sector Erase

(SE) instruction will not be executed on the page.

10.9. Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the

chosen block to be "1". The instruction is used for 64K-byte

sector erase operation. A Write Enable (WREN) instruction must

execute to set the Write Enable Latch (WEL) bit before sending

the Block Erase (BE). Any address of the block (see table 3) is a

valid address for Block Erase (BE) instruction. The CS# must go

high exactly at the byte boundary (the latest eighth of address byte

been latched-in); otherwise, the instruction will be rejected and not

executed.

The sequence is shown as Figure 21.

The self-timed Page Program Cycle time (tPP) is initiated as soon

as Chip Select (CS#) goes high. The Write in Progress (WIP) bit

still can be check out during the Page Program cycle is in

The sequence is shown as Figure 19.

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progress. The WIP sets 1 during the tPP timing, and sets 0 when

Page Program Cycle is completed, and the Write Enable Latch

(WEL) bit is reset. If the page is protected by BP3-BP0 bits, the

Page Program (PP) instruction will not be executed.

are also allowed to be executed, only except the device is in

progress of program/erase/write cycle; there's no effect on the

current program/erase/write cycle in progress.

The sequence is shown in Figure 23 and Figure 24.

The RES instruction is ended by CS# goes high after the ID been

read out at least once. The ID outputs repeatedly if continuously

send the additional clock cycles on SCLK while CS# is at low. If

the device was not previously in Deep Power-down mode, the

device transition to standby mode is immediate. If the device

was previously in Deep Power-down mode, there's a delay of

tRES2 to transit to standby mode, and CS# must remain to high at

least tRES2(max). Once in the standby mode, the device waits

to be selected, so it can be receive, decode, and execute

instruction.

10.12.Deep Power-down (DP)

The Deep Power-down (DP) instruction is for setting the device on

the minimizing the power consumption (to entering the Deep

Power-down mode), the standby current is reduced from ISB1 to

ISB2).

The Deep Power-down mode requires the Deep

Power-down (DP) instruction to enter, during the Deep

Power-down mode, the device is not active and all

Write/Program/Erase instruction are ignored. When CS# goes

high, it's only in standby mode not deep power-down mode. It's

different from Standby mode.

The RDP instruction is for releasing from Deep Power Down

Mode.

The sequence is shown as Figure 22.

Once the DP instruction is set, all instruction will be ignored except

the Release from Deep Power-down mode (RDP) and Read

Electronic Signature (RES) instruction. (those instructions allow

10.14.Read Identification (RDID)

The RDID instruction is for reading the manufacturer ID of 1-byte

and followed by Device ID of 2-byte. The Manufacturer ID and

Device ID are listed as table of "ID Definitions".

the ID being reading out).

When Power-down, the deep

power-down mode automatically stops, and when power-up, the

device automatically is in standby mode. For RDP instruction the

CS# must go high exactly at the byte boundary (the latest eighth

bit of instruction code been latched-in); otherwise, the instruction

will not executed. As soon as Chip Select (CS#) goes high, a

delay of tDP is required before entering the Deep Power-down

mode and reducing the current to ISB2.

The sequence is shown as Figure 25.

While Program/Erase operation is in progress, it will not decode

the RDID instruction, so there's no effect on the cycle of

program/erase operation which is currently in progress. When

CS# goes high, the device is at standby stage.

10.15.Read Electronic Manufacturer ID & Device ID

(REMS)

10.13.Release from Deep Power-down (RDP), Read

Electronic Signature (RES)

The REMS instruction is an alternative to the Release from

Power-down/Device ID instruction that provides both the JEDEC

assigned manufacturer ID and the specific device ID.

The Release from Deep Power-down (RDP) instruction is

terminated by driving Chip Select (CS#) High. When Chip Select

(CS#) is driven High, the device is put in the Stand-by Power

mode. If the device was not previously in the Deep Power-down

mode, the transition to the Stand-by Power mode is immediate. If

the device was previously in the Deep Power-down mode, though,

the transition to the Stand-by Power mode is delayed by tRES2,

and Chip Select (CS#) must remain High for at least tRES2(max),

as specified in Table 9. Once in the Stand-by Power mode, the

device waits to be selected, so that it can receive, decode and

execute instructions.

The REMS instruction is very similar to the Release from

Power-down/Device ID instruction. The instruction is initiated by

driving the CS# pin low and shift the instruction code "90h"

followed by two dummy bytes and one bytes address (A7~A0).

After which, the Manufacturer ID and the Device ID are shifted out

on the falling edge of SCLK with most significant bit (MSB) first as

shown in Figure 26. The Device ID values are listed in Table of

ID Definitions. If the one-byte address is initially set to 01h, then

the device ID will be read first and then followed by the

Manufacturer ID. The Manufacturer and Device IDs can be read

continuously, alternating from one to the other. The instruction is

completed by driving CS# high.

RES instruction is for reading out the old style of 8-bit Electronic

Signature, whose values are shown as table of ID Definitions.

This is not the same as RDID instruction. It is not recommended

to use for new design. For new design, please use RDID

instruction. Even in Deep power-down mode, the RDP and RES

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Table6. ID Definitions

Command Type

GPR25L162B

memory type

20

electronic ID

14

manufacturer ID

C2

memory density

15

RDID Command

RES Command

REMS

manufacturer ID

C2

device ID

14

10.16.Enter Secured OTP (ENSO)

10.18.Read Security Register (RDSCUR)

The ENSO instruction is for entering the additional 512 bit secured

OTP mode. The additional 512 bit secured OTP is independent

from main array, which may use to store unique serial number for

system identifier. After entering the Secured OTP mode, and

then follow standard read or program, procedure to read out the

data or update data. The Secured OTP data cannot be updated

again once it is lock-down.

The RDSCUR instruction is for reading the value of Security

Register bits. The Read Security Register can be read at any

time (even in program/erase/write status register/write security

register condition) and continuously.

The definition of the Security Register bits is as below:

Secured OTP Indicator bit. The Secured OTP indicator bit shows

the chip is locked by factory before ex- factory or not. When it is

"0", it indicates non- factory lock; "1" indicates factory- lock.

Lock-down Secured OTP (LDSO) bit. By writing WRSCUR

instruction, the LDSO bit may be set to "1" for customer lock-down

purpose. However, once the bit is set to "1" (lock-down), the

LDSO bit and the 512 bit Secured OTP area cannot be update any

more. While it is in 512 bit secured OTP mode, array access is

not allowed.

Please note that WRSR/WRSCUR commands are not acceptable

during the access of secure OTP region, once security OTP is lock

down, only read related commands are valid.

10.17.Exit Secured OTP (EXSO)

The EXSO instruction is for exiting the additional 512 bit secured

OTP mode.

Table7. Security Register Definition

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

x

LDSO (indicate if lock-down)

0 = not lockdown

Secured OTP indicator bit

0 = non-factory lock

1 = factory lock

reserved

1 = lock-down

(cannot program/erase OTP)

volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit

non-volatile bit

10.19.Write Security Register (WRSCUR)

The WRSCUR instruction is for changing the values of Security

Register Bits. Unlike write status register, the WREN instruction

LDSO bit is set to "1", the Secured OTP area cannot be updated

any more.

is not required before sending WRSCUR instruction.

The

The CS# must go high exactly at the boundary; otherwise, the

instruction will be rejected and not executed.

WRSCUR instruction may change the values of bit1 (LDSO bit) for

customer to lock-down the 512 bit Secured OTP area. Once the

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11. POWER-ON STATE

The device is at below states when power-up:

VCC minimum level, the correct operation is not guaranteed.

The read, write, erase, and program command should be sent

after the below time delay:

-

Standby mode ( please note it is not deep power-down mode)

Write Enable Latch (WEL) bit is reset

-

tVSL after VCC reached VCC minimum level

The device must not be selected during power-up and

power-down stage unless the VCC achieves below correct level:

The device can accept read command after VCC reached VCC

minimum and a time delay of tVSL.

-

VCC minimum at power-up stage and then after a delay of

Please refer to the figure of "power-up timing".

Note:

tVSL

To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor

close to package pins is recommended.(generally around 0.1uF)

-

GND at power-down

Please note that a pull-up resistor on CS# may ensure a safe and

proper power-up/down level.

11.1. Initial Delivery State

The device is delivered with the memory array erased: all bits are

set to 1 (each byte contains FFh). The Status Register contains

00h (all Status Register bits are 0).

An internal power-on reset (POR) circuit may protect the device

from data corruption and inadvertent data change during power up

state.

For further protection on the device, if the VCC does not reach the

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12. ELECTRICAL SPECIFICATIONS

12.1. Absolute Maximum Ratings

Rating

Value

Ambient Operating Temperature

Storage Temperature

Applied Input Voltage

Applied Output Voltage

Industrial grade

-40°C to 85°C

-55°C to 125°C

-0.5V to 4.6V

VCC to Ground Potential

Notice:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and

functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.

2. Specifications contained within the following tables are subject to change.

3. During voltage transitions, all pins may overshoot V_SSto -2.0V and V_CCto +2.0V for periods up to 20ns, see Figure 3 and 4.

12.2. Capacitance TA = 25°C, f = 1.0 MHz

Symbol

CIN

Parameter

Min.

Typ.

Max.

Unit

pF

Conditions

VIN = 0V

Input Capacitance

Output Capacitance

-

6

8

COUT

pF

VOUT = 0V

Figure5. Input Test Waveforms and Measurement Level

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Figure6. Output Loading

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12.3. DC Characteristics

Symbol

Parameter

Notes

Min.

Typ.

Max.

Units

Test Conditions

VCC = VCC Max,

VIN = VCC or GND

VCC = VCC Max,

VIN = VCC or GND

VIN = VCC or GND,

CS# = VCC

ILI

Input Load Current

1

-

± 2

uA

ILO

Output Leakage Current

VCC Standby Current

Deep Power-down Current

1

-

± 2

25

20

uA

ISB1

ISB2

VIN = VCC or GND,

CS# = VCC

5

f=86MHz

fT=80MHz

(2

x

I/O

1

-

25

20

mA

read)SCLK=0.1VCC/0.9VCC,

SO=Open

f=66MHz,

ICC1

VCC Read

SCLK=0.1VCC/0.9VCC,

SO=Open

f=33MHz,

1

-

10

20

mA

SCLK=0.1VCC/0.9VCC,

SO=Open

Program in Progress,

CS# = VCC

ICC2

ICC3

ICC4

VCC Program Current (PP)

VCC Write Status Register

(WRSR) Current

Program

status

register

in

progress, CS#=VCC

VCC Sector Erase Current

(SE)

Erase in Progress, CS#=VCC

ICC5

VIL

VCC Chip Erase Current (CE)

Input Low Voltage

1

-

20

0.3VCC

VCC+0.4

0.4

mA

V

-0.5

VIH

Input High Voltage

-

0.7VCC

-

V

VOL

Output Low Voltage

Output High Voltage

-

V

IOL = 1.6mA

IOH = -100uA

VOH

-

VCC-0.2

-

V

Notes:

1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).

2. Not 100% tested.

12.4. AC Characteristics

Symbol

Alt.

Parameter

Min.

Typ.

Max.

Unit

Clock Frequency for the following instructions:

FAST_READ, PP, SE, BE, CE, DP, RES, RDP, WREN,

WRDI, RDID, RDSR, WRSR

fSCLK

fC

DC

-

86

MHz

fRSCLK

fTSCLK

tCH(1)

fR

Clock Frequency for READ instructions

Clock Frequency for DREAD instructions

DC

5.5

13

-

33

80

-

MHz

ns

fT

tCLH

Clock High Time

fC=86MHz

fR=33MHz

fC=86MHz

fR=33MHz

-

ns

tCL(1)

tCLL

Clock Low Time

5.5

13

-

ns

-

ns

tCLCH(2)

Clock Rise Time (3) (peak to peak)

0.1

-

V/ns

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Symbol

tCHCL(2)

tSLCH

Alt.

Parameter

Clock Fall Time (3) (peak to peak)

CS# Active Setup Time (relative to SCLK)

CS# Not Active Hold Time (relative to SCLK)

Data In Setup Time

Min.

0.1

5

Typ.

Max.

Unit

V/ns

ns

us

-

tCSS

tCHSL

5

-

tDVCH

tCHDX

tCHSH

tSHCH

tSHSL

tDSU

tDH

2

-

Data In Hold Time

5

-

CS# Active Hold Time (relative to SCLK)

CS# Not Active Setup Time (relative to SCLK)

5

-

5

-

tCSH

CS# Deselect Time

Read

Write

15

40

-

tSHQZ(2)

tCLQV

tDIS

tV

Output Disable Time

6

8/6

-

Clock Low to Output Valid, Loading 30pF/15pF

Output Hold Time

-

tCLQX

tHO

0

tHLCH

HOLD# Setup Time (relative to SCLK)

HOLD# Hold Time (relative to SCLK)

HOLD Setup Time (relative to SCLK)

HOLD Hold Time (relative to SCLK)

HOLD to Output Low-Z

5

-

tCHHH

5

-

tHHCH

5

-

tCHHL

5

-

tHHQX(2)

tHLQZ(2)

tWHSL(4)

tSHWL (4)

tDP(2)

tLZ

-

6

-

tHZ

HOLD# to Output High-Z

-

Write Protect Setup Time

20

100

-

Write Protect Hold Time

-

CS# High to Deep Power-down Mode

CS# High to Standby Mode without Electronic Signature

Read

10

tRES1(2)

-

8.8

us

tRES2(2)

tW

CS# High to Standby Mode with Electronic Signature Read

Write Status Register Cycle Time

Byte-Program

-

8.8

40

300

5

us

ms

us

ms

s

5

tBP

9

tPP

Page Program Cycle Time

1.4

60

0.7

14

tSE

Sector Erase Cycle Time

300

2

tBE

Block Erase Cycle Time

tCE

Chip Erase Cycle Time

30

s

Notes:

1. tCH + tCL must be greater than or equal to 1/ fC. For Fast Read, tCL/tCH=5.5/5.5.

2. Value guaranteed by characterization, not 100% tested in production.

3. Expressed as a slew-rate.

4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

5. Test condition is shown as Figure 5.

6. The CS# rising time needs to follow tCHCL spec and CS# falling time needs to follow tCHCL spec.

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12.5. Timing Analysis

Figure7. Serial Input Timing

Figure8. Output Timing

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Figure9. Hold Timing

* SI is "don't care" during HOLD operation.

Figure10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1

Figure11. Write Enable (WREN) Sequence (Command 06)

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Figure12. Write Disable (WRDI) Sequence (Command 04)

Figure13. Read Status Register (RDSR) Sequence (Command 05)

Figure14. Write Status Register (WRSR) Sequence (Command 01)

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Figure15. Read Data Bytes (READ) Sequence (Command 03)

Figure16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)

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Figure17. Dual Output Read Mode Sequence (Command 3B)

Figure18. Sector Erase (SE) Sequence (Command 20)

Note: SE command is 20(hex).

Figure19. Block Erase (BE) Sequence (Command 52 or D8)

Note: BE command is 52 or D8(hex).

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Figure20. Chip Erase (CE) Sequence (Command 60 or C7)

Note: CE command is 60(hex) or C7(hex).

Figure21. Page Program (PP) Sequence (Command 02)

Figure22. Deep Power-down (DP) Sequence (Command B9)

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Figure23. Release from Deep Power-down (RDP) Sequence (Command AB)

Figure24. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)

Figure25. Read Identification (RDID) Sequence (Command 9F)

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Figure26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)

Notes:

(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first

(2) Instruction is either 90(hex).

Figure 27. Read Security Register (RDSCUR) Sequence (Command 2B)

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Figure 28. Write Security Register (WRSCUR) Sequence (Command 2F)

Figure29. Power-up Timing

Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.

Table10. Power-Up Timing

Symbol

Parameter

Min.

Max.

Unit

tVSL(1)

VCC(min) to CS# low

200

-

us

Note: 1.The parameter is characterized only.

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13. RECOMMENDED OPERATING CONDITIONS

13.1. At Device Power-Up and Power-down

AC timing illustrated in Figure 28 and Figure 29 are the supply voltages and the control signals at device power-up and power-down. If the

timing in the figures is ignored, the device will not operate correctly.

During power-up and power down, CS# need to follow the voltage applied on VCC to keep the device not be selected. The CS# can be

driven low when VCC reach V_CC(min.) and wait a period of tVSL.

Figure 30. AC Timing at Device Power-Up

Symbol

Parameter

Notes

Min.

Max.

Unit

tVR

VCC Rise Time

1

20

500000

us/V

Notes:

1. Sampled, not 100% tested.

2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table.

Figure 31. Power-Down Sequence

During power down, CS# need to follow the voltage drop on VCC to avoid mis-operation.

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14. ERASE AND PROGRAMMING PERFORMANCE

Parameter

Min.

Typ. (1)

Max. (2)

Unit

ms

s

Write Status Register Time

Sector Erase Time

-

5

60

40

300

2

Block Erase Time

0.7

Chip Erase Time

14

30

300

5

s

Byte Program Time (via page program command)

Page Program Time

9

us

1.4

ms

cycles

Erase/Program Cycle

100,000

-

Note:

1. Typical program and erase time assumes the following conditions: 25℃, 3.3V, and checker board pattern.

2. Under worst conditions of 85℃ and 2.7V.

3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.

4. Erase/Program cycles comply with JEDEC JESD-47 & JESD22-A117A standard.

14.1. Data Retention

Parameter

Condition

Min.

Max.

UNIT

Data retention

55˚C

20

-

years

15. LATCH-UP CHARACTERISTICS

Min.

Max.

Input Voltage with respect to GND on all power pins, SI, CS#

Input Voltage with respect to GND on SO

Current

-1.0V

2 VCCmax

VCC + 1.0V

+100mA

-100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

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16. PACKAGE/PAD LOCATIONS

16.1. Ordering Information

Product Number

Package Type

GPR25L162B-QS01x

SOP 8L 150mil-Halogen Free Package

SOP 8L 200mil-Halogen Free Package

GPR25L162B-QS13x

Note: x = 1 - 9, serial number.

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16.2. Package Information

16.2.1. Package Outline for SOP 8L (150MIL)

16.2.1.1. Dimensions (Inch dimensions are derived from the original mm dimensions)

Symbol

Θ

A

A1

A2

b

C

D

E

E1

e

L

L1

S

Unit

Min.

Nom.

Max.

Min.

-

0.10

0.15

1.35

1.45

0.36

0.41

0.15

0.20

4.77

4.90

5.80

5.99

3.80

3.90

-

0.46

0.66

0.85

1.05

0.41

0.54

0

5

8

0

5

8

mm

-

1.27

1.75

0.20

1.55

0.51

0.25

5.03

6.20

4.00

-

0.86

1.25

0.67

-

0.004

0.006

0.008

0.053

0.057

0.061

0.014

0.016

0.020

0.006

0.008

0.010

0.188

0.193

0.198

0.228

0.236

0.244

0.150

0.154

0.158

-

0.050

-

0.018

0.026

0.034

0.033

0.041

0.049

0.016

0.021

0.026

inch

Nom.

Max.

0.069

Reference

DWG. NO.

Revision

Issue Date

JEDEC

EIAJ

6110-1401

6

MS-012

-

11-26-03

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16.2.2. Package Outline for SOP 8L (200MIL)

16.2.2.1. Dimensions (Inch dimensions are derived from the original mm dimensions)

Symbol

Θ

A

A1

A2

b

C

D

E

E1

e

L

L1

S

Unit

Min.

Nom.

Max.

Min.

-

0.05

0.15

1.70

1.80

0.36

0.41

0.19

0.20

5.13

5.23

7.70

7.90

5.18

5.28

-

0.50

0.65

1.21

1.31

0.62

0.74

0

5

8

0

5

8

mm

-

1.27

2.16

0.20

1.91

0.51

0.25

5.33

8.10

5.38

-

0.80

1.41

0.88

-

0.002

0.006

0.008

0.067

0.071

0.075

0.014

0.016

0.020

0.007

0.008

0.010

0.202

0.206

0.210

0.303

0.311

0.319

0.204

0.208

0.212

-

0.050

-

0.020

0.026

0.031

0.048

0.052

0.056

0.024

0.029

0.035

inch

Nom.

Max.

0.085

Reference

DWG. NO.

Revision

Issue Date

JEDEC

EIAJ

6110-1406

3

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17. DISCLAIMER

The information appearing in this publication is believed to be accurate.

Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms

of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication

or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY

OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the

specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other

information in this publication are current before placing orders. Products described herein are intended for use in normal commercial

applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support

equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that

application circuits illustrated in this document are for reference purposes only.

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18. REVISION HISTORY

Date

Revision

1.4

Description

Page

Apr. 09, 2014

Oct. 20, 2011

Add 200mi; SOP8 information.

1.3

1. Added RDSCUR & WRSCUR diagram form.

2. Added CS# rising and falling time description.

3. Modified tW from 40(typ.)/100(max.) to 5(typ.)/40(max.).

1. Changed ISB1(MAX.) from 50uA to 25uA.

2. Modified GENERAL DESCRIPTION.

3. Modified COMMAND DESCRIPTION.

4. Changed Min. of fC, fR, fT from 10KHz to DC.

5. Modified Figure 8,19,26,28.

30,31

8,22

22,32

Feb. 10, 2011

1.2

4,21

5

12~17

21

23,27,30,31

6. Add Figure 29.

31

4

Dec. 14, 2010

Mar. 22, 2010

1.1

1.0

Add writer compatible information in section 1.1

Original

38

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型号：	GPR25L162B
厂家：	Generalplus Technology Inc.
描述：	16M-BIT [x1 / x2] CMOS SERIAL FLASH
文件：	总38页 (文件大小：1059K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GPR25L162B [GENERALPLUS]

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