GPR25L25606F-QS12X [GENERALPLUS]
3V, 256M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY;
| 型号： | GPR25L25606F-QS12X |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 3V, 256M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY |
| 文件： | 总73页 (文件大小：1317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3V, 256M-BIT [x 1/x 2/x 4] CMOS
MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
Jul. 30, 2018
Version 1.0
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPR25L25606F
Contents
CONTENTS .........................................................................................................................................................2
1. FEATURES ..................................................................................................................................................4
2. GENERAL DESCRIPTION ..........................................................................................................................5
3. MEMORY ORGANIZATION.........................................................................................................................7
4. DEVICE OPERATION..................................................................................................................................9
5. DATA PROTECTION .................................................................................................................................11
5.1.
BLOCK PROTECTION .............................................................................................................................11
6. STATUS AND EXTENDED ADDRESS REGISTERS................................................................................12
6.1.
6.2.
STATUS REGISTERS..............................................................................................................................12
EXTENDED ADDRESS REGISTER ............................................................................................................16
7. COMMANDS DESCRIPTION ....................................................................................................................17
TABLE OF ID DEFINITIONS:................................................................................................................................21
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
WRITE ENABLE (WREN) (06H).............................................................................................................21
WRITE DISABLE (WRDI) (04H)..............................................................................................................21
READ STATUS REGISTER (RDSR) (05H OR 35H OR 15H)......................................................................22
WRITE STATUS REGISTER (WRSR) (01H OR 31H OR 11H)....................................................................22
READ DATA BYTES (READ 03H OR 4READ 13H) .................................................................................23
READ DATA BYTES AT HIGHER SPEED (FAST READ 0BH OR 4FAST READ 0CH)......................................24
DUAL OUTPUT FAST READ (DOFR 3BH OR 4DOFR 3CH).....................................................................26
QUAD OUTPUT FAST READ (QOFR 6BH OR 4QOFR 6CH)....................................................................28
DUAL I/O FAST READ (DIOFR BBH OR 4DIOFR BCH)..........................................................................30
7.10. QUAD I/O FAST READ (QIOFR EBH OR 4QIOFR ECH).........................................................................34
7.11. SET BURST WITH WRAP (77H) ..............................................................................................................37
7.12. PAGE PROGRAM (PP 02H OR 4PP 12H) ...............................................................................................38
7.13. QUAD PAGE PROGRAM (QPP 32H OR 4QPP 3EH)................................................................................41
7.14. SECTOR ERASE (SE 20H OR 4SE 21H).................................................................................................43
7.15. 32KB BLOCK ERASE (BE32 52H OR 4BE32 5CH) ................................................................................44
7.16. 64KB BLOCK ERASE (BE64 D8H OR 4BE64 DCH) ...............................................................................45
7.17. CHIP ERASE (CE) (60/C7H)..................................................................................................................46
7.18. DEEP POWER-DOWN (DP) (B9H)..........................................................................................................47
7.19. READ UNIQUE ID (4BH) ........................................................................................................................48
7.20. ENTER 4-BYTE ADDRESS MODE (B7H)..................................................................................................49
7.21. EXIT 4-BYTE ADDRESS MODE (E9H) .....................................................................................................49
7.22. CLEAR SR FLAGS (30H) .......................................................................................................................49
7.23. RELEASE FROM DEEP POWER-DOWN AND READ DEVICE ID (RDI) (ABH) ...............................................50
7.24. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ..............................................................................51
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GPR25L25606F
7.25. READ IDENTIFICATION (RDID) (9FH) .....................................................................................................51
7.26. PROGRAM/ERASE SUSPEND (PES) (75H)..............................................................................................52
7.27. PROGRAM/ERASE RESUME (PER) (7AH)...............................................................................................54
7.28. ERASE SECURITY REGISTERS (44H)......................................................................................................54
7.29. PROGRAM SECURITY REGISTERS (42H).................................................................................................55
7.30. READ SECURITY REGISTERS (48H)........................................................................................................57
7.31. ENABLE RESET (66H) AND RESET (99H) ...............................................................................................58
7.32. READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH)........................................................................59
8. ELECTRICAL CHARACTERISTICS.........................................................................................................64
8.1. POWER-ON TIMING ..........................................................................................................................64
8.2. INITIAL DELIVERY STATE.................................................................................................................64
8.3. ABSOLUTE MAXIMUM RATINGS .....................................................................................................64
8.4. CAPACITANCE MEASUREMENT CONDITIONS..............................................................................65
8.5. DC CHARACTERISTICS....................................................................................................................66
8.6. AC CHARACTERISTICS....................................................................................................................67
9. ORDERING INFORMATION......................................................................................................................70
9.1.
10.
VALID PART NUMBERS ..........................................................................................................................70
PACKAGE INFORMATION....................................................................................................................71
10.1. PACKAGE OUTLINE FOR SOP 16L (300MIL)..........................................................................................71
11.
12.
DISCLAIMER .........................................................................................................................................72
REVISION HISTORY..............................................................................................................................73
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GPR25L25606F
1. FEATURES
◆ 256M-bit Serial Flash
-32M-byte
◆ Program/Erase Speed
-Page Program time: 0.6ms typical
-Sector Erase time: 50ms typical
-Block Erase time: 0.2/0.3s typical
-Chip Erase time: 100s typical
-256 bytes per programmable page
◆ Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#/ RESET#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#/ RESET#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
-3 or 4-Byte Addressing Mode
◆ Flexible Architecture
-Sector of 4K-byte
-Block of 32/64k-byte
◆ High Speed Clock Frequency
◆ Low Power Consumption
-30uA typical standby current
-1uA typical power down current
-Maximum 80MHz for fast read on 3.0 - 3.6V power supply
◆
◆
Dual I/O Data transfer up to 160Mbits/s
Quad I/O Data transfer up to 320Mbits/s
-Maximum 60MHz for fast read on 2.7 - 3.6V power supply
◆ Advanced Security Features
◆
◆
Dual I/O Data transfer up to 120Mbits/s
Quad I/O Data transfer up to 240Mbits/s
-3*256-Byte Security Registers With OTP Locks
-128-bit Unique ID for each device
-Serial Flash Discoverable parameters(SFDP) register
◆ Software/Hardware Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
◆ Single Power Supply Voltage
-Top or Bottom, Complement Block selection
-768-Byte (3*256-Byte) Security Registers With OTP Locks
-Full voltage range:2.7~3.6V
◆ Package Information
◆ Allows XIP(execute in place)operation(1)
-SOP16 (300mil)
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GPR25L25606F
2. GENERAL DESCRIPTION
The GPR25L25606F (256M-bit) Serial flash supports the
standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI),
I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#/ RESET#). The Dual
I/O data is transferred with speed of 160Mbits/s and the Quad
I/O & Quad output data is transferred with speed of 320Mbits/s.
CONNECTION DIAGRAM
Figure 1 Connection Diagram
HOLD#
1
16
SCLK
SI
VCC
RESET#
NC
2
3
4
5
6
7
8
15
14
13
12
11
10
9
NC
NC
Top View
NC
NC
NC
CS#
SO
NC
VSS
WP#
16-LEAD SOP
PIN DESCRIPTION
Table 1 Pin Description for SOP16 package and TFBGA24 package
Pin Name
CS#
I/O
I
Description
Chip Select Input
SO (IO1)
WP# (IO2)
VSS
I/O
I/O
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
SI (IO0)
SCLK
I/O
Data Input (Data Input Output 0)
Serial Clock Input
I
HOLD#/(IO3)
RESET#
VCC
I/O
I
Hold Input (Data Input Output 3)
Reset Input
Power Supply
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GPR25L25606F
BLOCK DIAGRAM
Figure 2 Block Diagram
Write Control
Logic
WP#(IO2)
Status
Register
Flash
Memory
HOLD#
RESET#(IO3)
High Voltage
Generators
SPI
Command &
Control Logic
SCLK
CS#
Page Address
Latch/Counter
Column Decode And
256-Byte Page Buffer
SI(IO0)
SO(IO1)
Byte Address
Latch/Counter
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GPR25L25606F
3. MEMORY ORGANIZATION
GPR25L25606F
Table 1 GPR25L25606F Memory Organization
Each sector has
Each device has
32M
Each block has
Each page has
64/32K
4K
16
-
256
bytes
pages
sectors
blocks
128K
256/128
-
-
-
8192
16/8
-
512/1024
-
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UNIFORM BLOCK SECTOR ARCHITECTURE
GPR25L25606F
Table 2 GPR25L25606F 64K Bytes Block Sector Architecture
Block
511
510
509
……
……
2
Sector
Address range
Advanced Block
Protection unit
8191
……
8176
8175
……
8160
8159
……
8144
……
……
……
……
……
……
47
01FF F000H
……
01FF FFFFH
4KB
……
4KB
……
01FF 0FFFH
01FE FFFFH
……
01FF 0000H
01FE F000H
……
64KB
64KB
01FE 0000H
01FD F000H
……
01FE 0FFFH
01FD FFFFH
……
01FD 0000H
……
01FD 0FFFH
……
……
……
……
……
……
……
……
……
……
……
……
0002 F000H
……
0002 FFFFH
……
……
32
64KB
64KB
0002 0000H
0001 F000H
……
0002 0FFFH
0001 FFFFH
……
31
1
……
16
0001 0000H
0000 F000H
……
0001 0FFFH
0000 FFFFH
……
15
4KB
……
4KB
0
……
0
0000 0000H
0000 0FFFH
Note:
1. Advanced Block Protection unit for block 511 and block 0 is 4KB sector, while unit for block 1 to block 510 is 64KB blocks (512Kbit).
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GPR25L25606F
4. DEVICE OPERATION
SPI Mode
Standard SPI
The GPR25L25606F features a serial peripheral interface on 4
signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data
Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and
3 are supported. Input data is latched on the rising edge of SCLK
and data shifts out on the falling edge of SCLK.
Dual SPI
The GPR25L25606F supports Dual SPI operation when using the
“Dual Output Fast Read”, “Dual Output Fast Read with 4-byte
address”, “Dual I/O Fast Read” and “Dual I/O Fast Read with 4-
byte address” commands (3BH 3CH BBH and BCH). These
commands allow data to be transferred to or from the device at two
times the rate of the standard SPI. When using the Dual SPI
command the SI and SO pins become bidirectional I/O pins: IO0
and IO1.
Quad SPI
The GPR25L25606F supports Quad SPI operation when using the
“Quad Output Fast Read”, “Quad Output Fast Read with 4-byte
address”, “Quad I/O Fast Read”, “Quad I/O Fast Read with 4-byte
address” (6BH, 6CH, EBH and ECH) commands. These
commands allow data to be transferred to or from the device at
four times the rate of the standard SPI. When using the Quad SPI
command the SI and SO pins become bidirectional I/O pins: IO0
and IO1, and WP# and HOLD#/RESET# pins become IO2 and IO3.
Quad SPI commands require the non-volatile Quad Enable bit (QE)
in Status Register to be set.
Hold
The HOLD/RST bit is used to determine whether HOLD# or
RESET# function should be implemented on the hardware pin for
8-pin packages. When HOLD/RST=0, the pin7 acts as HOLD#, the
HOLD# function is only available when QE=0, If QE=1, The
HOLD# functions is disabled, the pin acts as dedicated data I/O
pin.
edge of the HOLD# signal, with SCLK signal being low (if SCLK is
not being low, HOLD operation will not start until SCLK being low).
The HOLD condition ends on rising edge of HOLD# signal with
SCLK being low (If SCLK is not being low, HOLD operation will not
end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during
the HOLD operation, if CS# drives high during HOLD operation, it
will reset the internal logic of the device. To re-start communication
with chip, the HOLD# must be at high and then CS# must be at
low.
The HOLD# signal goes low to stop any serial communications
with the device, but doesn’t stop the operation of write status
register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling
Figure 3 Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
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RESET
The RESET# pin allows the device to be reset by the control. For
the WSON8 package, the pin7 can be configured as a RESET#
pin depending on the status register setting, which need QE=0 and
HOLD/RST=1. On the SOP16 package, a dedicated RESET# pin
is provided and it is independent of QE bit setting.
The RESET# pin goes low for a period of tRLRH or longer will reset
the flash. After reset cycle, the flash is at the following states:
-Standby mode
-All the volatile bits will return to the default status as power on.
Figure 4 RESET Condition
CS#
RESET#
RESET
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GPR25L25606F
5. DATA PROTECTION
The GPR25L25606F provides the following data protection
methods:
-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
Software Protection Mode:
◆
◆
Write Enable (WREN) command: The WREN command
is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up
-The Block Protect (BP3, BP2, BP1, and BP0) bits and
Top Bottom (TB) bit define the section of the memory
array that can be read but not change.
◆
◆
Hardware Protection Mode: WP# going low to protected
the BP0~BP3 bits, TB bit and SRP bit.
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
Deep Power-Down Mode: In Deep Power-Down Mode,
all commands are ignored except the Release from Deep
Power-Down Mode command.
-Quad Page Program (QPP)
5.1.
Block Protection
Table 3. GPR25L25606F Protected area size (WPS=0)
Memory Content
Addresses
Status Register Content
TB
BP3
BP2
BP1
BP0
Blocks
NONE
Density
NONE
64KB
Portion
NONE
X
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
X
X
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
NONE
511
01FF0000H-01FFFFFFH
01FE0000H-01FFFFFFH
01FC0000H-01FFFFFFH
01F80000H-01FFFFFFH
01F00000H-01FFFFFFH
01E00000H-01FFFFFFH
01C00000H-01FFFFFFH
01800000H-01FFFFFFH
01000000H-01FFFFFFH
00000000H-0000FFFFH
00000000H-0001FFFFH
00000000H-0003FFFFH
00000000H-0007FFFFH
00000000H-000FFFFFH
00000000H-001FFFFFH
00000000H-003FFFFFH
00000000H-007FFFFFH
00000000H-00FFFFFFH
00000000H-01FFFFFFH
00000000H-01FFFFFFH
Upper 1/512
Upper 1/256
Upper 1/128
510 to 511
508 to 511
128KB
256KB
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
1
X
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
X
X
504 to 511
496 to 511
480 to 511
448 to 511
384 to 511
256 to 511
0
512KB
1MB
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/512
Lower 1/256
Lower 1/128
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
2MB
4MB
8MB
16MB
64KB
128KB
256KB
512KB
1MB
0 to 1
0 to 3
0 to 7
0 to 15
0 to 31
0 to 63
0 to 127
0 to 255
ALL
2MB
4MB
8MB
16MB
32MB
32MB
ALL
ALL
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GPR25L25606F
6. STATUS AND EXTENDED ADDRESS REGISTERS
6.1.
Status Registers
Table 4 Status Register-1
Note
No.
Bit Name
WIP
Description
Volatile, read only
Volatile, read only
Non-volatile writable
Non-volatile writable
Non-volatile writable
Non-volatile writable
Non-volatile writable
Non-volatile writable
S0
S1
S2
S3
S4
S5
S6
S7
Erase/Write In Progress
Write Enable Latch
Block Protect Bits
Block Protect Bits
Block Protect Bits
Block Protect Bits
Quad Enable
WEL
BP0
BP1
BP2
BP3
QE
SRP
Status Register Protection
Table 5 Status Register-2
Note
No.
S8
Bit Name
DRV0
DRV1
HOLD/RST
TB
Description
Non-volatile writable
Non-volatile writable
Non-volatile writable
Non-volatile writable
Non-volatile writable
Volatile, read only
Output Driver Strength
Output Driver Strength
HOLD# or Reset# Function
Top/Bottom Protect Bit
Power Up Address Mode
Current Address Mode
Latency Code 0
S9
S10
S11
S12
S13
S14
S15
ADP
ADS
LC0
Non-volatile writable
Non-volatile writable
LC1
Latency Code 1
Table 6 Status Register-3
Note
No.
S16
S17
S18
S19
S20
S21
S22
S23
Bit Name
LB1
Description
Non-volatile writable (OTP)
Non-volatile writable (OTP)
Volatile, read only
OTP lock bit
LB2
OTP lock bit
SUS_P
SUS_E
LB3
Program Suspend
Erase Suspend
OTP lock bit
Volatile, read only
Non-volatile writable (OTP)
Volatile, read only
PE
Program Error bit
Erase Error bit
Write Protect Selection
Volatile, read only
EE
Non-volatile writable
WPS
The status and control bits of the Status Register are as follows:
WIP bit
The Write in Progress (WIP) bit indicates whether the memory is
busy in program/erase/write status register progress. When WIP
bit sets to 1, means the device is busy in program/erase/write
status register progress, when WIP bit sets 0, means the device is
not in program/erase/write status register progress.
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WEL bit
The Write Enable Latch (WEL) bit indicates the status of the
internal Write Enable Latch. When set to 1 the internal Write
Enable Latch is set, when set to 0 the internal Write Enable Latch
TB bit
is reset and no Write Status Register, Program or Erase command
is accepted.
The Top Bottom (TB) bit is non-volatile (OTP). The Top/Bottom
(TB) bit is used to configure the Block Protect area by BP bit (BP3,
BP2, BP1, and BP0), starting from Top or Bottom of the memory
array. The TB bit is defaulted as “0”, which means Top area protect.
BP3, BP2, BP1, BP0 bits
When it is set to “1”, the protect area will change to Bottom area of
the memory device. This bit is written with the Write Status
Register (WRSR) command.
The Block Protect (BP3, BP2, BP1, and BP0) bits are non-volatile.
They define the size of the area to be software protected against
Program and Erase commands. These bits are written with the
Write Status Register (WRSR) command. When the Block Protect
(BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory
SRP bit
area becomes protected against Page Program (PP), Sector
Erase (SE) and Block Erase (BE) commands. The Block Protect
(BP4, BP3, BP2, BP1, and BP0) bits can be written provided that
the Hardware Protected mode has not been set. The Chip Erase
(CE) command is executed only if none sector or block is protected.
The Status Register Protect (SRP) bit is non-volatile Read/Write
bits in the status register. The SRP bit controls the method of write
protection: software protection and hardware protection.
Table 7 Status Register Protect (SRP) bit
SRP
#WP
Status Register
Description
The Status Register can be written to after a Write Enable command,
WEL=1.(Default)
0
X
Software Protected
WP#=0, the Status Register locked and can not be written to.
1
1
0
1
Hardware Protected
WP#=1, the Status Register is unlocked and can be written to after a Write
Enable command, WEL=1.
Hardware Unprotected
QE bit
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the
Status Register that allows Quad operation. When the QE bit is set
to 0 (Default) the WP# pin and HOLD# / RESET# pin are enable.
When the QE pin is set to 1, the Quad IO2 and IO3 pins are
LB3, LB2, LB1, bits.
enabled. (The QE bit should never be set to 1 during standard SPI
or Dual SPI operation if the WP# or HOLD# / RESET# pins are tied
directly to the power supply or ground)
The LB3, LB2, LB1, bits are non-volatile One Time Program (OTP)
bits in Status Register (S16, S17, S20) that provide the write
protect control and status to the Security Registers. The default
state of LB3-LB1 are 0, the security registers are unlocked. The
SUS_E, SUS_P bit
LB3-LB1 bits can be set to 1 individually using the Write Register
instruction. The LB3-LB1 bits are One Time Programmable, once
its set to 1, the Security Registers will become read-only
permanently.
The SUS_E and SUS_P bit are read only bit in the status register
(S18 and S19) that are set to 1 after executing an Program/Erase
Suspend (75H) command (The Erase Suspend will set the SUS_E
to 1,and the Program Suspend will set the SUS_P to 1). The
SUS_E and SUS_P bit are cleared to 0 by Program/Erase Resume
(7AH) command as well as a power-down, power-up cycle.
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GPR25L25606F
WPS
The WPS Bit is used to select which Write Protect scheme should
be used. When WPS=0, the device will use the combination of TB,
BP (3:0) bits to protect a specific area of the memory array. When
DRV1/DRV0
WPS=1, the device will utilize the Advanced Block Protection to
protect any individual sector or blocks. The default value for all
Individual Block Lock bits is 1 upon device power on or after reset.
The DRV1&DRV0 bits are used to determine the output driver
strength for the Read operations.
Table 8 Driver Strength for Read Operations
DRV1,DRV0
Driver Strength
100%
00
01
10
11
75%
50% (Default)
25%
HOLD/RST
The HOLD/RST bit is used to determine whether HOLD# or
RESET# function should be implemented on the hardware pin for
8-pin packages. When HOLD/RST=0, the pin acts as HOLD#,
When the HOLD/RST=1, the pin acts as RESET#. However, the
PE
HOLD# or RESET# function are only available when QE=0, If
QE=1, The HOLD# and RESET# functions are disabled, the pin
acts as dedicated data I/O pin.
The Program Error (PE) bit is a read only bit that indicates a
program failure. It will also be set when the user attempts to
program a protected array sector or access the locked OTP space.
EE
Error bits must be reset by CLEAR FLAG STATUS REGISTER
command (30H).
The Erase Error (EE) bit is a read only bit that indicates an erase
failure. It will also be set when the user attempts to erase a
protected array sector or access the locked OTP space.
LC1, LC0 bits
Error bits must be reset by CLEAR FLAG STATUS REGISTER
command (30H).
The Latency Code (LC) selects the mode and number of dummy
cycles between the end of address and the start of read data
output for all read commands.
when the same command type is repeated in a sequence of
commands.
Dummy cycles provide additional latency that is needed to
complete the initial read access of the flash array before data can
be returned to the host system. Some read commands require
additional latency cycles as the SCLK frequency is increased.
The following latency code tables provide different latency settings
that are configured by GigaDevice.
Some read commands send mode bits following the address to
indicate that the next command will be of the same type with an
implied, rather than an explicit, instruction. The next command
thus does not provide an instruction byte, only a new address and
mode bits. This reduces the time needed to send each command
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GPR25L25606F
Table 9 Latency Code and Frequency Table
Read
Fast Read
(0Bh, 0Ch)
Read Dual Out Read Quad Out Dual I/O Read Quad I/O Read
Freq.
Freq.
Freq.
LC
(03h, 13h)
(3Bh, 3Ch)
(6Bh, 6Ch)
(BBh, BCh)
(EBh, ECh)
(MHz)
(MHz)
(MHz)
Mode Dummy
Mode Dummy
Mode Dummy Mode Dummy Mode Dummy Mode Dummy
11
00
≤50
≤80
0
0
-
0
0
-
≤50
≤104
≤104
0
0
0
0
8
8
≤80
≤80
0
0
0
6
8
8
0
0
0
6
8
8
4
4
4
0
0
2
2
2
2
4
4
6
01 or 10 ≤104
≤104
Note:
1. The default value of latency code is 00.
2. Not 100% tested in production.
ADS
The Address Status (ADS) bit is a read only bit that indicates the
current address mode the device is operating in. The device is in
ADP
3-byte address mode when ADS=0 (default), and in 4-byte address
mode when ADS=1.
The Address Power-up (ADP) bit is a non-volatile writable bit that
determines the initial address mode when the device is powered
on or reset. This bit is only used during the power on or device
reset initialization period. When ADP=0(factory default), the device
will power up into 3-byte address mode, the Extended Address
Register must be used to access memory regions beyond 128Mb.
When ADP=1, the device will power up into 4-byte address mode
directly.
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6.2.
Extended Address Register
Table 10 Extended Address Register
EA7
A31
EA6
A30
EA5
A29
EA4
A28
EA3
A27
EA2
A26
EA1
A25
EA0
A24
The extended address register is only used when the address mode is 3-byte mode, as to set the higher address.
When the device is 256Mb, A24 is the highest address bit. A31~A26 are reserved for higher density from 1Gb ~ 32Gb.
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7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the
device, beginning with the most significant bit on the first rising
edge of SCLK after CS# is driven low. Then, the one-byte
command code must be shifted in to the device, most significant
bit first on SI, each bit being latched on the rising edges of SCLK.
Every command sequence starts with a one-byte command code.
Depending on the command, this might be followed by address
bytes, or by data bytes, or by both or none. CS# must be driven
high after the last bit of the command sequence has been shifted
in. For the command of Read, Fast Read, Read Status Register or
Release from Deep Power-Down, and Read Device ID, the shifted-
in command sequence is followed by a data-out sequence. CS#
can be driven high after any bit of the data-out sequence is being
shifted out.
Deep Power-Down command, CS# must be driven high exactly at
a byte boundary, otherwise the command is rejected, and is not
executed. That is CS# must driven high when the number of clock
pulses after CS# being driven low is an exact multiple of eight. For
Page Program, if at any time the input byte is not a full byte,
nothing will happen and WEL will not be reset.
When the device is in 3-byte address mode (ADS=0), please refer
to command set in table13 & table14. When the device is in 4-byte
address mode (ADS=1), please refer to command set in table13 &
table15.
Extended Address Register setting is effective to achieve A31-A24,
accompanying A23-A0 within the instruction, when commands
listed in table14 are executed.
Extended Address Register setting is ignored when A31-A24 are
given in the instruction listed in table 3 and some specific
instruction from table13 (13H, 0CH, 3CH, 6CH, BCH, ECH).
For the command of Page Program, Sector Erase, Block Erase,
Chip Erase, Write Status Register, Write Enable, Write Disable or
Table 11. Commands (Standard/Dual/Quad SPI, 3-byte & 4-byte address mode)
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6
Command
Name
Add
n-Bytes
Mode
Write Enable
Write Disable
Read Status
Register-1
3 & 4
3 & 4
3 & 4
06H
04H
05H
35H
15H
01H
31H
11H
C8H
C5H
(S7-S0)
(cont.)
(cont.)
Read Status
Register-2
3 & 4
3 & 4
3 & 4
3 & 4
3 & 4
(S15-S8)
(S23-S16)
(S7-S0)
Read Status
Register-3
Write Status
Register-1
Write Status
Register-2
(S15-S8)
(S23-S16)
(EA7-EA0)
(EA7-EA0)
Write Status
Register-3
Read Extended 3 & 4
Addr. Register
Write Extended 3 & 4
Addr. Register
Chip Erase
Enable Reset
Reset
3 & 4
3 & 4
3 & 4
C7/60H
66H
99H
Program/Erase 3 & 4
Suspend
75H
Program/Erase 3 & 4
Resume
7AH
77H
Set Burst with 3 & 4
Wrap (5)
dummy
W7-W0
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Release From 3 & 4
Deep
ABH
Power-Down
Read Device ID 3 & 4
ABH
B9H
dummy
dummy
dummy
dummy
dummy
00H
(DID7-DID0)
(cont.)
Deep
Down
Power- 3 & 4
Manufacturer/
Device ID
3 & 4
3 & 4
3 & 4
3 & 4
90H
(MID7-MID0) (DID7-DID0)
(cont.)
(cont.)
Read
9FH
B7H
(MID7-MID0) (JDID15-JDID8) (JDID7-JDID0)
Identification
Enter 4-Byte
Address Mode
Exit 4-Byte
Address Mode
E9H
13H
Read Data with 3 & 4
4-Byte Address
A31-A24
A31-A24
A31-A24
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
(D7-D0)
dummy
dummy
Fast Read with 3 & 4
4-Byte Address
0CH
3CH
(D7-D0)
(D7-D0)
Fast Read Dual 3 & 4
Output with 4-
Byte Address (1)
Fast Read Quad 3 & 4
Output with 4-
6CH
BCH
ECH
A31-A24
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
Byte Address (3)
Fast Read Dual 3 & 4
I/O with 4-Byte
A31-A24
A23-A 16
A15-A8
A7-A0
M7-M0
(D7-D0)
Address (2)
Fast Read Quad 3 & 4
I/O with 4-Byte
A31-A24
A23-A 16
A15-A8
A7-A0
M7-M0
dummy
dummy
(D7-D0)
Address (4)
Page Program
with 4-Byte
Address
3 & 4
12H
3EH
21H
5CH
A31-A24
A31-A24
A31-A24
A31-A24
A31-A24
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
(D7-D0)
Next byte
Quad Page
Program with 4- 3 & 4
Byte Address
(D7-D0)(3)
Sector Erase
with 4-Byte
Address
Block
3 & 4
Erase(32K) with 3 & 4
4-Byte Address
Block
Erase(64K) with 3 & 4
4-Byte Address
DCH
30H
Clear SR Flags 3 & 4
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Table 12 Commands (Standard/Dual/Quad SPI, 3-byte address)
Command
Name
Add
Byte 1 Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
Mode
Read Data
Fast Read
Dual Output
Fast Read (1)
Dual I/O
3
3
03H
0BH
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
(D7-D0)
dummy
(Next byte)
(D7-D0)
(cont.)
(cont.)
3
3
3
3BH
BBH
6BH
A23-A16
A23-A8(2)
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)(1)
(cont.)
(cont.)
(cont.)
(cont.)
A7-A0
M7-M0(2)
(D7-D0)(1)
A7-A0
Fast Read (2)
Quad Output
Fast Read (3)
Quad I/O
A15-A8
dummy
(D7-D0)(3)
Next byte
A23-A0
M7-M0(4)
3
3
3
3
3
EBH
02H
32H
20H
52H
dummy
A15-A8
A15-A8
A15-A8
A15-A8
(D7-D0)(3)
A7-A0
Fast Read (4)
Page Program
Quad Page
Program
A23-A16
(D7-D0)
A23-A16
A23-A16
A23-A16
A7-A0
(D7-D0)(3)
Sector Erase
Block
A7-A0
A7-A0
Erase(32K)
Block
3
3
D8H
5AH
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
Erase(64K)
Read Serial
Flash
dummy
dummy
(D7-D0)
(cont.)
Discoverable
Parameter
(UID127-
UID120)
dummy
dummy
A15-A8
dummy
A7-A0
Read Unique ID
3
3
4BH
44H
Erase Security
Registers (6)
Program
A23-A16
Security
3
3
42H
48H
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
(D7-D0)
dummy
(D7-D0)
(D7-D0)
Registers (6)
Read Security
Registers (6)
Table 13. Commands (Standard/Dual/Quad SPI, 4-byte address)
Command
Name
Add
Byte 1 Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Bytes-7
n-Bytes
Mode
Read Data
4
4
03H
0BH
A31-A24
A31-A24
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
(D7-D0)
dummy
(cont.)
(cont.)
Fast Read
(D7-D0)
Dual Output
Fast Read (1)
Dual I/O
4
4
4
3BH
BBH
6BH
A31-A24
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)(1)
(cont.)
A31-A24
A23-A16
A15-A8
A7-A0
M7-M0(2)
dummy
(D7-D0)(1)
A7-A0
Fast Read (2)
Quad Output
Fast Read (3)
A31-A24
A23-A16
A15-A8
dummy
(D7-D0)(1)
(cont.)
A31-A24
A23-A16
A15-A8
A7-A0
M7-M0(4)
dummy
Quad I/O
4
4
EBH
02H
(cont.)
(cont.)
Fast Read (4)
dummy
(D7-D0)(3)
Page Program
A31-A24
A23-A16
A15-A8
19
A7-A0
(D7-D0)
(D7-D0)
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Quad Page
Program
4
4
4
32H
20H
52H
A31-A24
A31-A24
A31-A24
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
(D7-D0)(3)
(cont.)
Sector Erase
Block
Erase(32K)
Block
4
4
D8H
5AH
A31-A24
A31-A24
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
Erase(64K)
Read Serial
Flash
dummy
dummy
(D7-D0)
(cont.)
Discoverable
Parameter
(UID127-
UID120)
dummy
dummy
dummy
A15-A8
dummy
A7-A0
Read Unique ID
4
4
4BH
44H
Erase Security
Registers (6)
Program
A31-A24
A23-A16
Security
4
4
42H
48H
A31-A24
A31-A24
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
(D7-D0)
dummy
(D7-D0)
(D7-D0)
(cont.)
(cont.)
Registers (6)
Read Security
Registers (6)
NOTE:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8
IO1 = A23, A21, A19, A17, A15, A13, A11, A9
A6, A4, A2, A0, M6, M4, M2, M0
A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3,…..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Dummy bits and Wrap Bits
IO0 = (x, x, x, x, x, x, W4, x)
IO1 = (x, x, x, x, x, x, W5, x)
IO2 = (x, x, x, x, x, x, W6, x)
IO3 = (x, x, x, x, x, x, W7, x)
6. Security Registers Address
Security Register1: A23-A16=00H, A15-A8=10H, A7-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A8=20H, A7-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A8=30H, A7-A0= Byte Address.
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GPR25L25606F
Table of ID Definitions:
GPR25L25606F
Operation Code
MID7-MID0
ID15-ID8
ID7-ID0
19
9FH
90H
ABH
C8
C8
40
18
18
7.1.
Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable
Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set
prior to every Page Program (PP), Quad Page Program (QPP),
Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write
Status Register (WRSR). The Write Enable (WREN) command
sequence: CS# goes low sending the Write Enable command
CS# goes high.
Figure 5 Write Enable Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
Command
06H
High-Z
SO
7.2.
Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable
of the memory. The WRDI command is ignored during an
embedded operation while WIP bit =1.
Latch (WEL) bit. The Write Enable Latch (WEL) bit may be set to
a 0 by issuing the Write Disable (WRDI) command to disable
Page Program (PP), Quad Page Program (QPP), Sector Erase
(SE), Block Erase (BE), Chip Erase (CE), Write Status Register
(WRSR), that require WEL be set to 1 for execution. The WRDI
command can be used by the user to protect memory areas
against inadvertent writes that can possibly corrupt the contents
The WEL bit is reset by following condition: Write Disable
command (WRDI), Power-up, and upon completion of the Write
Status Register, Page Program, Sector Erase, Block Erase and
Chip Erase commands.
The Write Disable command sequence: CS# goes low Sending
the Write Disable command CS# goes high.
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Figure 6 Write Disable Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
Command
04H
High-Z
SO
7.3.
Read Status Register (RDSR) (05H or 35H or 15H)
The Read Status Register (RDSR) command is for reading the
Status Register. The Status Register may be read at any time,
even while a Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress, it is
recommended to check the Write in Progress (WIP) bit before
sending a new command to the device. It is also possible to read
the Status Register continuously. For command code “05H” / “35H”
/ “15H”, the SO will output Status Register bits S7~S0 / S15-S8 /
S16-S23.
Figure 7 Read Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Command
SI
05H or 35H or 15H
Register0/1/2
Register0/1/2
SO
High-Z
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
7.4.
Write Status Register (WRSR) (01H or 31H or 11H)
The Write Status Register (WRSR) command allows new values
to be written to the Status Register. Before it can be accepted, a
Write Enable (WREN) command must previously have been
executed. After the Write Enable (WREN) command has been
decoded and executed, the device sets the Write Enable Latch
(WEL).
The Write In Progress (WIP) bit is 1 during the self-timed Write
Status Register cycle, and is 0 when it is completed. When the
cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to
change the values of the Block Protect (BP4, BP3, BP2, BP1, and
BP0) bits, to define the size of the area that is to be treated as
read-only. The Write Status Register (WRSR) command also
allows the user to set or reset the Status Register Protect (SRP)
bits in accordance with the Write Protect (WP#) signal. The Status
Register Protect (SRP) bits and Write Protect (WP#) signal allow
the device to be put in the Hardware Protected Mode. The Write
Status Register (WRSR) command is not executed once the
Hardware Protected Mode is entered.
The Write Status Register (WRSR) command has no effect on S22,
S21, S19, S18, S13, S1 and S0 of the Status Register. CS# must
be driven high after the eighth of the data byte has been latched
in. If not, the Write Status Register (WRSR) command is not
executed. As soon as CS# is driven high, the self-timed Write
Status Register cycle (whose duration is tW) is initiated. While the
Write Status Register cycle is in progress, the Status Register may
still be read to check the value of the Write In Progress (WIP) bit.
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Figure 8 Write Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Status Register in
SCLK
Command
01H/31H/11H
SI
7
6
5
4
3
2 1 0
MSB
High-Z
SO
7.5.
Read Data Bytes (READ 03H or 4READ 13H)
The Read Data Bytes (READ) command is followed by a 3-byte
address (A23-A0), each bit being latched-in during the rising edge
of SCLK. Then the memory content, at that address, is shifted out
on SO, each bit being shifted out, at a Max frequency fR, during the
falling edge of SCLK. The first byte addressed can be at any
location. The address is automatically incremented to the next
higher address after each byte of data is shifted out. The whole
memory can, therefore, be read with a single Read Data Bytes
(READ) command. Any Read Data Bytes (READ) command, while
an Erase, Program or Write cycle is in progress, is rejected without
having any effects on the cycle that is in progress.
Figure 9 Read Data Bytes Sequence Diagram (ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
03H
24-bit address
23 22 21
MSB
SI
3
2
1
0
Data Out1
Data Out2
High-Z
SO
7
6
5
4
3
2
1
0
MSB
Figure 10 Read Data Bytes Sequence Diagram (ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Command
03H
32-bit address
31 30 29
MSB
SI
3
2
1
0
Data Out1
Data Out2
High-Z
SO
7
6
5
4
3
2
1
0
MSB
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Figure 11 Read Data with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Command
13H
32-bit address
31 30 29
MSB
SI
3
2
1
0
Data Out1
Data Out2
High-Z
SO
7
6
5
4
3
2
1
0
MSB
7.6.
Read Data Bytes at Higher Speed (Fast Read 0BH or 4Fast Read 0CH)
The Read Data Bytes at Higher Speed (Fast Read) command is
for quickly reading data out. It is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising
edge of SCLK. Then the memory content, at that address, is
shifted out on SO, each bit being shifted out, at a Max frequency
fC, during the falling edge of SCLK. The first byte addressed can
be at any location. The address is automatically incremented to the
next higher address after each byte of data is shifted out.
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Figure 12 Read Data Bytes at Higher Speed Sequence Diagram (ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
0BH
24-bit address
23 22 21
SI
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
Note:
1. The dummy clock number is configurable.
Figure 13 Read Data Bytes at Higher Speed Sequence Diagram (ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39
SCLK
Command
0BH
32-bit address
31 30 29
SI
3
2
1
0
High-Z
SO
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
Note:
1. The dummy clock number is configurable.
© Generalplus Technology Inc.
Proprietary & Confidential
25
Jul. 30, 2018
Version: 1.0
GPR25L25606F
Figure 14 Fast Read with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39
SCLK
Command
0CH
32-bit address
31 30 29
SI
3
2
1
0
High-Z
SO
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
Note:
1. The dummy clock number is configurable.
7.7.
Dual Output Fast Read (DOFR 3BH or 4DOFR 3CH)
The Dual Output Fast Read command is followed by 3-byte
address (A23-A0) and a dummy byte, each bit being latched in
during the rising edge of SCLK, then the memory contents are
shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure 16. The first
byte addressed can be at any location. The address is
automatically incremented to the next higher address after each
byte of data is shifted out.
Figure 15 Dual Output Fast Read Sequence Diagram (ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
3BH
24-bit address
23 22 21
SI
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
SCLK
SI
6
4
2
0
6
4
2
0
6
7
Data Out1
Data Out2
SO
7
5
3
1
7
5
3
1
MSB
MSB
Note:
1. The dummy clock number is configurable.
© Generalplus Technology Inc.
Proprietary & Confidential
26
Jul. 30, 2018
Version: 1.0
GPR25L25606F
Figure 16 Dual Output Fast Read Sequence Diagram (ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39
SCLK
Command
3BH
32-bit address
31 30 29
SI
3
2
1
0
High-Z
SO
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
6
4
2
0
6
4
2
0
6
Data Out1
Data Out2
SO
7
5
3
1
7
5
3
1
7
MSB
MSB
Note:
1. The dummy clock number is configurable.
Figure 17 Dual Output Fast Read with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39
SCLK
SI
Command
3CH
32-bit address
31 30 29
3
2
1
0
High-Z
SO
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
6
4
2
0
6
4
2
0
6
Data Out1
Data Out2
SO
7
5
3
1
7
5
3
1
7
MSB
MSB
Note:
1. The dummy clock number is configurable.
© Generalplus Technology Inc.
Proprietary & Confidential
27
Jul. 30, 2018
Version: 1.0
GPR25L25606F
7.8.
Quad Output Fast Read (QOFR 6BH or 4QOFR 6CH)
The Quad Output Fast Read command is followed by 3-byte
address (A23-A0) and a dummy byte, each bit being latched in
during the rising edge of SCLK, then the memory contents are
shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The
command sequence is shown in followed Figure19. The first byte
addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is
shifted out.
Figure 18 Quad Output Fast Read Sequence Diagram (ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
6BH
24-bit address
23 22 21
SI(IO0)
3
2
1
0
SO(IO1)
High-Z
High-Z
High-Z
WP#(IO2)
HOLD#(IO3)
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
SCLK
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Byte1 Byte2 Byte3 Byte4
Note:
1. The dummy clock number is configurable.
© Generalplus Technology Inc.
Proprietary & Confidential
28
Jul. 30, 2018
Version: 1.0
GPR25L25606F
Figure 19 Quad Output Fast Read Sequence Diagram (ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39
SCLK
Command
6BH
32-bit address
31 30 29
SI(IO0)
3
2
1
0
SO(IO1)
High-Z
High-Z
High-Z
WP#(IO2)
HOLD#(IO3)
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Dummy Clocks
SCLK
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Byte1 Byte2 Byte3 Byte4
Note:
1. The dummy clock number is configurable.
© Generalplus Technology Inc.
Proprietary & Confidential
29
Jul. 30, 2018
Version: 1.0
GPR25L25606F
Figure 20 Fast Read Quad Output with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39
SCLK
Command
6CH
32-bit address
31 30 29
SI(IO0)
3
2
1
0
SO(IO1)
High-Z
High-Z
High-Z
WP#(IO2)
HOLD#(IO3)
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Dummy Clocks
SCLK
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Byte1 Byte2 Byte3 Byte4
Note:
1. The dummy clock number is configurable.
7.9.
Dual I/O Fast Read (DIOFR BBH or 4DIOFR BCH)
The Dual I/O Fast Read command is similar to the Dual Output
Fast Read command but with the capability to input the 3-byte
address (A23-0) and a “Continuous Read Mode” byte 2-bit per
clock by SI and SO, each bit being latched in during the rising edge
of SCLK, then the memory contents are shifted out 2-bit per clock
Dual I/O Fast Read with “Continuous Read Mode”
cycle from SI and SO. The command sequence is shown in
followed Figure22. The first byte addressed can be at any location.
The address is automatically incremented to the next higher
address after each byte of data is shifted out.
The Dual I/O Fast Read command can further reduce command
overhead through setting the “Continuous Read Mode” bits (M7-4)
after the input 3-byte address (A23-A0). If the “Continuous Read
Mode” bits (M5-4) = (1, 0), then the next Dual I/O Fast Read
command (after CS# is raised and then lowered) does not require
the BBH command code. The command sequence is shown in
followed Figure23. If the “Continuous Read Mode” bits (M5-4) do
not equal (1, 0), the next command requires the first BBH
command code, thus returning to normal operation. A Reset
command can be used to reset (M5-4) before issuing normal
command.
© Generalplus Technology Inc.
Proprietary & Confidential
30
Jul. 30, 2018
Version: 1.0
GPR25L25606F
Figure 21 Dual I/O Fast Read Sequence Diagram (M5-4≠ (1, 0), ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
BBH
SI(IO0)
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
7
A23-16
A15-8
A7-0
M7-4
M3-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
SO(IO1)
Byte1
Byte2
Byte3
Byte4
Note:
1. The dummy clock number is configurable.
Figure 22 Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0), ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
6
4
2
0
6
4
2
0
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
7
5
3
1
7
5
3
1
7
A23-16
A15-8
A7-0
M7-4
M3-0
CS#
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
SO(IO1)
Byte1
Byte2
Byte3
Byte4
Note:
1. The dummy clock number is configurable.
© Generalplus Technology Inc.
Proprietary & Confidential
31
Jul. 30, 2018
Version: 1.0
GPR25L25606F
Figure 23 Dual I/O Fast Read Sequence Diagram (M5-4≠ (1, 0), ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
BBH
SI(IO0)
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
7
A31-24
A23-16
A15-8
A7-0
CS#
24 25 26 27 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
SO(IO1)
M7-4 M3-0
Byte1
Byte2
Byte3
Byte4
Note:
1. The dummy clock number is configurable.
Figure 24 Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0) ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
SCLK
6
4
2
0
6
4
2
0
6
4
5
2
3
0
1
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
7
5
3
1
7
5
3
1
7
A23-16
A15-8
M3-0
M7-4
A7-0
A31-24
CS#
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
SO(IO1)
7
Byte1
Byte2
Byte3
Byte4
Note:
1. The dummy clock number is configurable.
© Generalplus Technology Inc.
Proprietary & Confidential
32
Jul. 30, 2018
Version: 1.0
GPR25L25606F
Figure 25 Dual I/O Fast Read with 4-Byte Address Sequence Diagram (M5-4≠ (1, 0), ADS=0 or ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
BCH
SI(IO0)
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
7
A31-24
A23-16
A15-8
A7-0
CS#
24 25 26 27 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
SO(IO1)
M7-4 M3-0
Byte1
Byte2
Byte3
Byte4
Note:
1. The dummy clock number is configurable.
Figure 26 Dual I/O Fast Read with 4-Byte Address Sequence Diagram (M5-4= (1, 0) ADS=0 or ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
SCLK
6
4
2
0
6
4
2
0
6
4
5
2
3
0
1
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
7
5
3
1
7
5
3
1
7
A23-16
A15-8
M3-0
M7-4
A7-0
A31-24
CS#
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
SO(IO1)
7
Byte1
Byte2
Byte3
Byte4
Note:
1. The dummy clock number is configurable.
© Generalplus Technology Inc.
Proprietary & Confidential
33
Jul. 30, 2018
Version: 1.0
GPR25L25606F
7.10. Quad I/O Fast Read (QIOFR EBH or 4QIOFR ECH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast
Read command but with the capability to input the 3-byte address
(A23-0) and a “Continuous Read Mode” byte and 4-dummy clock
4-bit per clock by IO0, IO1, IO2, IO3, each bit being latched in
during the rising edge of SCLK, then the memory contents are
shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The first
Quad I/O Fast Read with “Continuous Read Mode”
byte addressed can be at any location. The address is
automatically incremented to the next higher address after each
byte of data is shifted out. The Quad Enable bit (QE) of Status
Register (S6) must be set to enable for the Quad I/O Fast read
command.
The Quad I/O Fast Read command can further reduce command
overhead through setting the “Continuous Read Mode” bits (M7-0)
after the input 3-byte address (A23-A0). If the “Continuous Read
Mode” bits (M5-4) = (1, 0), then the next Quad I/O Fast Read
command (after CS# is raised and then lowered) does not require
the EBH command code. If the “Continuous Read Mode” bits (M5-
4) do not equal to (1, 0), the next command requires the first EBH
command code, thus returning to normal operation. A Reset
command can be used to reset (M5-4) before issuing normal
command.
Figure 27 Quad I/O Fast Read Sequence Diagram (M5-4≠ (1, 0), ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
EBH
SI(IO0)
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SO(IO1)
5
6
7
WP#(IO2)
HOLD#(IO3)
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
Note:
1. The dummy clock number is configurable.
© Generalplus Technology Inc.
Proprietary & Confidential
34
Jul. 30, 2018
Version: 1.0
GPR25L25606F
Figure 28 Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0), ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI(IO0)
4
0
4
0
4
0
4
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SO(IO1)
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
WP#(IO2)
HOLD#(IO3)
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
Note:
1. The dummy clock number is configurable.
Figure 29 Quad I/O Fast Read Sequence Diagram (M5-4≠ (1, 0), ADS=1)
CS#
24 25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0
SCLK
Command
EBH
4
5
6
7
0
1
2
3
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SI(IO0)
5
6
7
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Dummy Byte1 Byte2
A31-24A23-16A15-8 A7-0 M7-0
Note:
1. The dummy clock number is configurable.
© Generalplus Technology Inc.
Proprietary & Confidential
35
Jul. 30, 2018
Version: 1.0
GPR25L25606F
Figure 30 Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0), ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
SCLK
SI(IO0)
4
0
4
0
4
0
4
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
4
0
1
2
3
SO(IO1)
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
WP#(IO2)
HOLD#(IO3)
A31-24A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
Note:
1. The dummy clock number is configurable.
Figure 31 Quad I/O Fast Read with 4-Byte Address Sequence Diagram (M5-4≠ (1, 0), ADS=0 or ADS=1)
CS#
24 25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0
SCLK
Command
ECH
4
5
6
7
0
1
2
3
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SI(IO0)
5
6
7
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Dummy Byte1 Byte2
A31-24A23-16A15-8 A7-0 M7-0
Note:
1. The dummy clock number is configurable.
© Generalplus Technology Inc.
Proprietary & Confidential
36
Jul. 30, 2018
Version: 1.0
GPR25L25606F
Figure 32 Quad I/O Fast Read with 4-Byte Address Sequence Diagram (M5-4= (1, 0), ADS=0 or ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
SCLK
SI(IO0)
4
0
4
0
4
0
4
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
4
0
1
2
3
SO(IO1)
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
WP#(IO2)
HOLD#(IO3)
A31-24A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
Note:
1. The dummy clock number is configurable.
Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Fast Read command can be used to access a
specific portion within a page by issuing “Set Burst with Wrap” (77H)
commands prior to EBH or ECH. The “Set Burst with Wrap” (77H)
command can either enable or disable the “Wrap Around” feature
for the following EBH or ECH commands. When “Wrap Around” is
enabled, the data being accessed can be limited to either an
8/16/32/64-byte section of a 256-byte page. The output data starts
at the initial address specified in the command, once it reaches the
ending boundary of the 8/16/32/64-byte section, the output will
wrap around the beginning boundary automatically until CS# is
pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to
quickly fetch a critical address and then fill the cache afterwards
within a fixed length (8/16/32/64-byte) of data without issuing
multiple read commands. The “Set Burst with Wrap” command
allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-W5 is
used to specify the length of the wrap around section within a page.
7.11. Set Burst with Wrap (77H)
The Set Burst with Wrap command is used in conjunction with
“Quad I/O Fast Read” command to access a fixed length of
8/16/32/64-byte section within a 256-byte page, in standard SPI
mode.
The Set Burst with Wrap command sequence: CS# goes low
Send Set Burst with Wrap command Send 24 dummy bits
Send 8 bits “Wrap bits” CS# goes high.
Table 14 Set Burst with Wrap configuration
W4=0
W4=1 (default)
W6,W5
Wrap Around
Wrap Length
8-byte
Wrap Around
Wrap Length
0, 0
0, 1
1, 0
1, 1
Yes
Yes
Yes
Yes
No
No
No
No
N/A
N/A
N/A
N/A
16-byte
32-byte
64-byte
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If the W6-W4 bits are set by the Set Burst with Wrap command, all
the following “Quad I/O Fast Read” command will use the W6-W4
setting to access the 8/16/32/64-byte section within any page. To
exit the “Wrap Around” function and return to normal read
operation, another Set Burst with Wrap command should be issued
to set W4=1.
Figure 33 Set Burst with Wrap Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Command
77H
SI(IO0)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
5
6
x
x
x
x
x
SO(IO1)
x
x
x
WP#(IO2)
HOLD#(IO3)
W6-W4
7.12. Page Program (PP 02H or 4PP 12H)
The Page Program (PP) command is for programming the memory.
A Write Enable (WREN) command must previously have been
executed to set the Write Enable Latch (WEL) bit before sending
the Page Program command.
correctly within the same page. If less than 256 data bytes are sent
to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the
same page. CS# must be driven high after the eighth bit of the last
data byte has been latched in; otherwise the Page Program (PP)
command is not executed.
The Page Program (PP) command is entered by driving CS# Low,
followed by the command code, three address bytes and at least
one data byte on SI. If the 8 least significant address bits (A7-A0)
are not all zero, all transmitted data that goes beyond the end of
the current page are programmed from the start address of the
same page (from the address whose 8 least significant bits (A7-
A0) are all zero). CS# must be driven low for the entire duration of
the sequence. The Page Program command sequence: CS# goes
low sending Page Program command 3-byte address on SI
at least 1 byte data on SI CS# goes high. If more than 256
bytes are sent to the device, previously latched data are discarded
and the last 256 data bytes are guaranteed to be programmed
As soon as CS# is driven high, the self-timed Page Program cycle
(whose duration is tPP) is initiated. While the Page Program cycle
is in progress, the Status Register may be read to check the value
of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit
is 1 during the self-timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed,
the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) is
not executed.
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Figure 34 Page Program Sequence Diagram (ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
02H
24-bit address
23 22 21
MSB
Data Byte 1
SI
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
Figure 35 Page Program Sequence Diagram (ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Command
02H
32-bit address
31 30 29
MSB
Data Byte 1
SI
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
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Figure 36 Page Program with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Command
12H
32-bit address
31 30 29
MSB
Data Byte 1
SI
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
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7.13. Quad Page Program (QPP 32H or 4QPP 3EH)
The Quad Page Program command is for programming the
memory using four pins: IO0, IO1, IO2, and IO3. To use Quad Page
Program the Quad enable in status register Bit6 must be set
(QE=1). A Write Enable (WREN) command must previously have
been executed to set the Write Enable Latch (WEL) bit before
sending the Page Program command. The quad Page Program
command is entered by driving CS# Low, followed by the
command code (32H), three address bytes and at least one data
byte on IO pins.
be driven high after the eighth bit of the last data byte has been
latched in; otherwise the Quad Page Program (PP) command is
not executed.
As soon as CS# is driven high, the self-timed Quad Page Program
cycle (whose duration is tPP) is initiated. While the Quad Page
Program cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write in
Progress (WIP) bit is 1 during the self-timed Quad Page Program
cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
The command sequence is shown below. If more than 256 bytes
are sent to the device, previously latched data are discarded and
the last 256 data bytes are guaranteed to be programmed correctly
within the same page. If less than 256 data bytes are sent to device,
they are correctly programmed at the requested addresses without
having any effects on the other bytes of the same page. CS# must
A Quad Page Program command applied to a page which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) is
not executed.
Figure 37 Quad Page Program Sequence Diagram (ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
32H
24-bit address
23 22 21
MSB
Byte1 Byte2
SI(IO0)
3
2
1
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Byte11Byte12
SCLK
Byte253
Byte256
SI(IO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
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Figure 38 Quad Page Program Sequence Diagram (ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Command
32H
32-bit address
31 30 29
MSB
Byte1 Byte2
SI(IO0)
3
2
1
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
CS#
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Byte11Byte12
SCLK
Byte253
Byte256
SI(IO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
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Figure 39 Quad Page Program with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Command
3EH
32-bit address
31 30 29
MSB
Byte1 Byte2
SI(IO0)
3
2
1
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
CS#
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Byte11Byte12
SCLK
Byte253
Byte256
SI(IO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
7.14. Sector Erase (SE 20H or 4SE 21H)
The Sector Erase (SE) command is erased the all data of the
chosen sector. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit. The
Sector Erase (SE) command is entered by driving CS# low,
followed by the command code, and 3-address byte on SI. Any
address inside the sector is a valid address for the Sector Erase
(SE) command. CS# must be driven low for the entire duration of
the sequence.
byte has been latched in; otherwise the Sector Erase (SE)
command is not executed. As soon as CS# is driven high, the self-
timed Sector Erase cycle (whose duration is tSE) is initiated. While
the Sector Erase cycle is in progress, the Status Register may be
read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Sector Erase
cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is
reset. A Sector Erase (SE) command applied to a sector which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit
is not executed.
The Sector Erase command sequence: CS# goes low sending
Sector Erase command 3-byte address on SI CS# goes high.
CS# must be driven high after the eighth bit of the last address
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GPR25L25606F
Figure 40 Sector Erase Sequence Diagram (ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
20H
24 Bits Address
23 22
MSB
SI
2
1
0
Figure 41 Sector Erase Sequence Diagram (ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9
37 38 39
SCLK
Command
20H
32 Bits Address
31 30
MSB
SI
2
1
0
Figure 42 Sector Erase with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9
37 38 39
SCLK
Command
21H
32 Bits Address
31 30
MSB
SI
2
1
0
7.15. 32KB Block Erase (BE32 52H or 4BE32 5CH)
The 32KB Block Erase (BE) command is erased the all data of the
chosen block. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit. The
32KB Block Erase (BE) command is entered by driving CS# low,
followed by the command code, and three address bytes on SI.
Any address inside the block is a valid address for the 32KB Block
Erase (BE) command. CS# must be driven low for the entire
duration of the sequence.
last address byte has been latched in; otherwise the 32KB Block
Erase (BE) command is not executed. As soon as CS# is driven
high, the self-timed Block Erase cycle (whose duration is tBE) is
initiated. While the Block Erase cycle is in progress, the Status
Register may be read to check the value of the Write in Progress
(WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed
Block Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset. A 32KB Block Erase (BE) command
applied to a block which is protected by the Block Protect (BP4,
BP3, BP2, BP1, and BP0) bits is not executed.
The 32KB Block Erase command sequence: CS# goes low
sending 32KB Block Erase command 3-byte address on SI
CS# goes high. CS# must be driven high after the eighth bit of the
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GPR25L25606F
Figure 43 32KB Block Erase Sequence Diagram (ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
52H
24 Bits Address
23 22
MSB
SI
2
1
0
Figure 44 32KB Block Erase Sequence Diagram (ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9
37 38 39
SCLK
Command
52H
32 Bits Address
31 30
MSB
SI
2
1
0
Figure 45 32KB Block Erase with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9
37 38 39
SCLK
SI
Command
5CH
32 Bits Address
31 30
MSB
2
1
0
7.16. 64KB Block Erase (BE64 D8H or 4BE64 DCH)
The 64KB Block Erase (BE) command is erased the all data of the
chosen block. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit. The
64KB Block Erase (BE) command is entered by driving CS# low,
followed by the command code, and three address bytes on SI.
Any address inside the block is a valid address for the 64KB Block
Erase (BE) command. CS# must be driven low for the entire
duration of the sequence.
last address byte has been latched in; otherwise the 64KB Block
Erase (BE) command is not executed. As soon as CS# is driven
high, the self-timed Block Erase cycle (whose duration is tBE) is
initiated. While the Block Erase cycle is in progress, the Status
Register may be read to check the value of the Write in Progress
(WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed
Block Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset. A 64KB Block Erase (BE) command
applied to a block which is protected by the Block Protect (BP4,
BP3, BP2, BP1, and BP0) bits is not executed.
The 64KB Block Erase command sequence: CS# goes low
sending 64KB Block Erase command 3-byte address on SI
CS# goes high. CS# must be driven high after the eighth bit of the
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GPR25L25606F
Figure 46 64KB Block Erase Sequence Diagram (ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
D8H
24 Bits Address
23 22
MSB
SI
2
1
0
Figure 47 64KB Block Erase Sequence Diagram (ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9
37 38 39
SCLK
Command
D8H
32 Bits Address
31 30
MSB
SI
2
1
0
Figure 48 64KB Block Erase with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9
37 38 39
SCLK
SI
Command
DCH
32 Bits Address
31 30
MSB
2
1
0
7.17. Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is erased the all data of the chip.
A Write Enable (WREN) command must previously have been
executed to set the Write Enable Latch (WEL) bit .The Chip Erase
(CE) command is entered by driving CS# Low, followed by the
command code on Serial Data Input (SI). CS# must be driven Low
for the entire duration of the sequence.
otherwise the Chip Erase command is not executed. As soon as
CS# is driven high, the self-timed Chip Erase cycle (whose
duration is tCE) is initiated. While the Chip Erase cycle is in progress,
the Status Register may be read to check the value of the Write in
Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the
self-timed Chip Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset. The Chip Erase (CE) command is ignored
if one or more sectors/blocks are protected.
The Chip Erase command sequence: CS# goes low sending
Chip Erase command CS# goes high. CS# must be driven high
after the eighth bit of the command code has been latched in;
Figure 49 Chip Erase Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
Command
60H or C7H
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7.18. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way
to put the device in the lowest consumption mode (the Deep
Power-Down Mode). It can also be used as an extra software
protection mechanism, while the device is not in active use, since
in this mode, the device ignores all Write, Program and Erase
commands. Driving CS# high deselects the device, and puts the
device in the Standby Mode (if there is no internal cycle currently
in progress). But this mode is not the Deep Power-Down Mode.
The Deep Power-Down Mode can only be entered by executing
the Deep Power-Down (DP) command. Once the device has
entered the Deep Power-Down Mode, all commands are ignored
except the Release from Deep Power-Down and Read Device ID
(RDI) command. This releases the device from this mode. The
Release from Deep Power-Down and Read Device ID (RDI)
command also allows the Device ID of the device to be output on
SO.
The Deep Power-Down Mode automatically stops at Power-Down,
and the device always Power-Up in the Standby Mode. The Deep
Power-Down (DP) command is entered by driving CS# low,
followed by the command code on SI. CS# must be driven low for
the entire duration of the sequence.
The Deep Power-Down command sequence: CS# goes low
sending Deep Power-Down command CS# goes high. CS#
must be driven high after the eighth bit of the command code has
been latched in; otherwise the Deep Power-Down (DP) command
is not executed. As soon as CS# is driven high, it requires a delay
of tDP before the supply current is reduced to ICC2 and the Deep
Power-Down Mode is entered. Any Deep Power-Down (DP)
command, while an Erase, Program or Write cycle is in progress,
is rejected without having any effects on the cycle that is in
progress.
Figure 50 Deep Power-Down Sequence Diagram
CS#
SCLK
SI
tDP
0
1 2 3 4 5 6 7
Command
B9H
Stand-by mode Deep Power-down mode
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7.19. Read Unique ID (4BH)
The Read Unique ID command accesses a factory-set read-only
128bit number that is unique to each device. The Unique ID can
be used in conjunction with user software methods to help prevent
copying or cloning of a system.
Byte1 Dummy Byte2 Dummy Byte3 Dummy Byte4128bit
Unique ID Out CS# goes high.
The Read Unique ID command sequence in 4 byte mode (ADS=0):
CS# goes low sending Read Unique ID command Dummy
Byte1 Dummy Byte2 Dummy Byte3 Dummy Byte4
Dummy Byte5128bit Unique ID Out CS# goes high.
The Read Unique ID command sequence in 3 byte mode (ADS=0):
CS# goes low sending Read Unique ID command Dummy
Figure 51 Read Unique ID Sequence Diagram (ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39
SCLK
Command
4BH
4-Byte Dummy
SI
7
6
5
3
2
1
0
High-Z
SO
CS#
40 41 42 43 44 45 46 47
SCLK
SI
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
Figure 52 Read Unique ID Sequence Diagram (ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10
44 45 46 47
SCLK
Command
4BH
5-Byte Dummy
SI
7
6
5
3
2
1
0
High-Z
SO
CS#
48 49 50 51 52 53 54 55
SCLK
SI
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
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7.20. Enter 4-Byte Address Mode (B7H)
The Enter 4-byte Address Mode command enables accessing the
address length of 32-bit for the memory area of higher density
(larger than 128Mb). The device default is in 24-bit address mode;
after sending out the EN4B instruction, the bit13 (ADS bit) of status
register will be automatically set to “1” to indicate the 4-byte
address mode has been enabled. Once the 4-byte address mode
is enabled, the address length becomes 32-bit instead of the
default 24-bit.
All instructions are accepted normally, and just the address bit is
changed from 24-bit to 32-bit.
The sequence of issuing EN4B instruction is: CS# goes low
sending Enter 4-byte mode command CS# goes high.
Figure 53 Enter 4-Byte Address Mode Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
Command
B7H
High-Z
SO
7.21. Exit 4-Byte Address Mode (E9H)
The Exit 4-byte Address Mode command is executed to exit the 4-
byte address mode and return to the default 3-byte address mode.
After sending out the EX4B instruction, the bit13 (ADS bit) of status
register will be cleared to “0” to indicate the exit of the 4-byte
address mode. Once exiting the 4-byte address mode, the address
length will return to 24-bit.
The sequence of issuing EN4B instruction is: CS# goes low
sending Exit 4-byte Address Mode command CS# goes high.
Figure 54 Exit 4-Byte Address Mode Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
Command
E9H
High-Z
SO
7.22. Clear SR Flags (30H)
The Clear Status Register Flags command resets bit S21
(Program Error bit) and S22 (Erase Error bit) from status register.
It is not necessary to set the WEL bit before the Clear Status
Register command is executed. The Clear SR command will be
accepted even when the device remains busy with WIP set to 1,
as the device does remain busy when either error bit is set. The
WEL bit will be unchanged after this command is executed.
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Figure 55 Clear Status Register Flags Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
Command
30H
High-Z
SO
7.23. Release from Deep Power-Down and Read Device ID (RDI) (ABH)
with most significant bit (MSB) first as shown below. The Device
ID value for the GPR25L25606F is listed in Manufacturer and
Device Identification table. The Device ID can be read
continuously. The command is completed by driving CS# high.
When used to release the device from the Power-Down state
and obtain the Device ID, the command is the same as
previously described, except that after CS# is driven high it
The Release from Power-Down and Read Device ID command is a
multi-purpose command. It can be used to release the device from
the Power-Down state or obtain the devices electronic identification
(ID) number.
To release the device from the Power-Down state, the command
is issued by driving the CS# pin low, shifting the instruction code
“ABH” and driving CS# high as shown below. Release from
Power-Down will take the time duration of tRES1 (See AC
Characteristics) before the device will resume normal operation
and other command are accepted. The CS# pin must remain
high during the tRES1 time duration.
must remain high for
a time duration of tRES2 (See AC
Characteristics). After this time duration the device will resume
normal operation and other command will be accepted. If the
Release from Power-Down / Device ID command is issued while
an Erase, Program or Write cycle is in process (when WIP equal
1) the command is ignored and will not have any effects on the
current cycle.
When used only to obtain the Device ID while not in the Power-
Down state, the command is initiated by driving the CS# pin low
and shifting the instruction code “ABH” followed by 3-dummy byte.
The Device ID bits are then shifted out on the falling edge of SCLK
Figure 56 Release Power-Down Sequence Diagram
CS#
SCLK
SI
tRES1
0
1
2
3
4
5
6
7
Command
ABH
Deep Power-down mode
Stand-by mode
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Figure 57 Release Power-Down/Read Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38
SCLK
tRES2
Command
ABH
3 Dummy Bytes
SI
23 22
MSB
2
1
0
Device ID
SO
High-Z
7
6
5
4
3
2
1
0
MSB
Deep Power-down Mode Stand-by Mode
7.24. Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to
the Release from Power-Down / Device ID command that provides
both the JEDEC assigned Manufacturer ID and the specific Device
ID.
the command code “90H” followed by a 24-bit address (A23-A0) of
000000H. After which, the Manufacturer ID and the Device ID are
shifted out on the falling edge of SCLK with most significant bit
(MSB) first as shown below.
The command is initiated by driving the CS# pin low and shifting
Figure 58 Read Manufacture ID/ Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
24-bit address
23 22 21
SI
90H
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
Device ID
Manufacturer ID
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
7.25. Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit
manufacturer identification to be read, followed by two bytes of
device identification. The device identification indicates the
memory type in the first byte, and the memory capacity of the
device in the second byte. The Read Identification (RDID)
command while an Erase or Program cycle is in progress is not
decoded, and has no effect on the cycle that is in progress. The
Read Identification (RDID) command should not be issued while
the device is in Deep Power-Down Mode.
The device is first selected by driving CS# to low. Then, the 8-bit
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command code for the command is shifted in. This is followed by
the 24-bit device identification, stored in the memory, being shifted
out on Serial Data Output, each bit being shifted out during the
falling edge of Serial Clock. The Read Identification (RDID)
command is terminated by driving CS# to high at any time during
data output. When CS# is driven high, the device is put in the
Standby Mode. Once in the Standby Mode, the device waits to be
selected, so that it can receive, decode and execute commands.
Figure 59 Read Identification ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
9FH
Command
Manufacturer ID
7
6
5
4
3
2
1
0
SO
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Memory Type
JDID15-JDID8
Capacity
JDID7-JDID0
MSB
7.26. Program/Erase Suspend (PES) (75H)
MSB
The Program/Erase Suspend command “75H”, allows the system
to interrupt a page program or sector/block erase operation and
then read data from any other sector or block. The Write Status
Register command (01H/31H/11H) and Erase commands (20H,
52H, D8H, C7H, 60H) and Page Program command (02H / 32H)
are not allowed during Program/Erase suspend. Program/Erase
Suspend is valid only during the page program or sector/block
erase operation.
A maximum of time of “tsus” (See AC
Characteristics) is required to suspend the program/erase
operation.
Table 15 Commands Allowed During Program or Erase Suspend
Allowed Allowed
Code During
(Hex) Erase
During
Command Name
Comment
Program
Suspend Suspend
Write Enable
06
05
Yes
Required for program command within erase suspend.
Needed to read WIP to determine end of suspend process.
Read Status Register-1
Yes
Yes
Yes
Yes
Needed to read suspend status to determine whether the operation is
suspended or complete.
Read Status Register-2
Read Status Register-3
35
15
Needed to read suspend status to determine whether the operation is
suspended or complete.
Yes
Yes
Yes
Yes
Read Extended Addr.
Register
Extended Addr. Register may need to be changed during a suspend to
reach a sector needed for read or program.
C8
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Write Extended Addr.
Register
Extended Addr. Register may need to be changed during a suspend to
reach a sector needed for read or program.
C5
Yes
Yes
Read
03
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
All array reads allowed in suspend.
All array reads allowed in suspend.
All array reads allowed in suspend.
All array reads allowed in suspend.
All array reads allowed in suspend.
All array reads allowed in suspend.
All array reads allowed in suspend.
All array reads allowed in suspend.
All array reads allowed in suspend.
All array reads allowed in suspend.
All array reads allowed in suspend.
All array reads allowed in suspend.
Required for array program during erase suspend.
Required for array program during erase suspend.
Required for array program during erase suspend.
Required for array program during erase suspend.
Program suspend allowed during erase suspend.
Required to resume from erase/program suspend.
Reset allowed anytime.
4Read
13
Fast Read
0B
0C
BB
BC
3B
3C
EB
EC
6B
4Fast Read
Dual I/O Fast Read
4Dual I/O Fast Read
Dual Output Fast Read
4Dual Output Fast Read
Quad I/O Fast Read
4Quad I/O Fast Read
Quad Output Fast Read
4Quad Output Fast Read 6C
Page Program
02
12
32
3E
75
7A
66
99
4Page Program
Quad Page Program
4Quad Page Program
Program/Erase Suspend
Program/Erase Resume
Enable Reset
Yes
Yes
Reset
Reset allowed anytime.
The Program/Erase Suspend command will be accepted by the
device only if the SUS_P/SUS_E bit in the Status Register equal
to 0 and WIP bit equal to 1 while a Page Program or a Sector or
Block Erase operation is on-going. If the SUS_P/SUS_E bit equal
to 1 or WIP bit equal to 0, the Suspend command will be ignored
by the device. The WIP bit will be cleared from 1 to 0 within “tsus”
and the SUS_P/SUS_E bit will be set from 0 to 1 immediately after
Program/Erase Suspend. A power-off during the suspend period
will reset the device and release the suspend state.
Figure 60 Program/Erase Suspend Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
tSUS
Command
75H
High-Z
SO
Accept read command
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7.27. Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume
the program or sector/block erase operation after a Program/Erase
Suspend command. The Program/Erase command will be
accepted by the device only if the SUS_P/SUS_E bit equal to 1
and the WIP bit equal to 0. After issued the SUS_P/SUS_E bit in
the status register will be cleared from 1 to 0 immediately, the WIP
bit will be set from 0 to 1 within 200ns and the Sector or Block will
complete the erase operation or the page will complete the
program operation. The Program/Erase Resume command will be
ignored unless a Program/Erase Suspend is active.
Figure 61 Program/Erase Resume Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
Command
7AH
SO
Resume Erase/Program
7.28. Erase Security Registers (44H)
The GPR25L25606F provides three 256-byte Security Registers
which can be erased and programmed individually. These
registers may be used by the system manufacturers to store
security and other important information separately from the main
memory array.
command is not executed. As soon as CS# is driven high, the self-
timed Erase Security Registers cycle (whose duration is tSE) is
initiated. While the Erase Security Registers cycle is in progress,
the Status Register may be read to check the value of the Write in
Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the
self-timed Erase Security Registers cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed,
the Write Enable Latch (WEL) bit is reset. The Security Registers
Lock Bit (LB3-1) in the Status Register can be used to OTP protect
the security registers. Once the LB bit is set to 1, the Security
Registers will be permanently locked; the Erase Security Registers
command will be ignored.
The Erase Security Registers command is similar to Sector/Block
Erase command. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL)
bit.
The Erase Security Registers command sequence: CS# goes low
sending Erase Security Registers command CS# goes high.
CS# must be driven high after the eighth bit of the command code
has been latched in; otherwise the Erase Security Registers
Table 16 Security Registers
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-8
0 0 0 0
0 0 0 0
0 0 0 0
A7-0
Security Register #1
Security Register #2
Security Register #3
Do not care
Do not care
Do not care
00H
00H
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Figure 62 Erase Security Registers command Sequence Diagram (ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
44H
24 Bits Address
23 22
MSB
SI
2
1
0
Figure 63 Erase Security Registers command Sequence Diagram (ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9
37 38 39
SCLK
Command
44H
32 Bits Address
31 30
MSB
SI
2
1
0
7.29. Program Security Registers (42H)
The Program Security Registers command is similar to the Page
Program command. It allows from 1 to 256 bytes Security
Registers data to be programmed. A Write Enable (WREN)
command must previously have been executed to set the Write
Enable Latch (WEL) bit before sending the Program Security
Registers command. The Program Security Registers command is
entered by driving CS# Low, followed by the command code (42H),
three address bytes and at least one data byte on SI. As soon as
CS# is driven high, the self-timed Program Security Registers
cycle (whose duration is tPP) is initiated. While the Program
Security Registers cycle is in progress, the Status Register may be
read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Program
Security Registers cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security
Registers will be permanently locked. Program Security Registers
command will be ignored.
Table 17 Security Registers
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-8
0 0 0 0
0 0 0 0
0 0 0 0
A7-0
Security Register #1
Security Register #2
Security Register #3
Byte Address
Byte Address
Byte Address
00H
00H
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Figure 64 Program Security Registers command Sequence Diagram (ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
42H
24-bit address
23 22 21
MSB
Data Byte 1
SI
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
Figure 65 Program Security Registers command Sequence Diagram (ADS=1)
CS#
46 47
36 37 38 39 40 41 42 43 44 45
0
1
2
3
4
5
6
7
8
9 10
SCLK
Command
42H
32-bit address
31 30 29
MSB
Data Byte 1
SI
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
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7.30. Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read
command. The command i is followed by a 3-byte address (A23-
A0) or 4-byte address (A31-A0) and a dummy byte, each bit being
latched-in during the rising edge of SCLK. Then the memory
content, at that address, is shifted out on SO, each bit being shifted
out, at a Max frequency fC, during the falling edge of SCLK. The
first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each
byte of data is shifted out. Once the A7-A0 address reaches the
last byte of the register (Byte 0FFH), it will reset to 000H, the
command is completed by driving CS# high.
Table 18 Security Registers
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-8
0 0 0 0
0 0 0 0
0 0 0 0
A7-0
Security Register #1
Security Register #2
Security Register #3
Byte Address
Byte Address
Byte Address
00H
00H
Figure 66 Read Security Registers command Sequence Diagram (ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
48H
24-bit address
23 22 21
SI
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
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Figure 67 Read Security Registers command Sequence Diagram (ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39
SCLK
Command
48H
32-bit address
31 30 29
SI
3
2
1
0
High-Z
SO
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
7.31. Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation
will be terminated and the device will return to its default power-on
state and lose all the current volatile settings, such as Volatile
Status Register bits, Write Enable Latch status (WEL),
Program/Erase Suspend status, Continuous Read Mode bit setting
(M7-M0) and Wrap Bit Setting (W6-W4).
goes high CS# goes low Sending Reset command CS#
goes high. Once the Reset command is accepted by the device,
the device will take approximately tRST =60us to reset. During this
period, no command will be accepted. Data corruption may
happen if there is an on-going or suspended internal Erase or
Program operation when Reset command sequence is accepted
by the device. It is recommended to check the BUSY bit and the
SUS bit in Status Register before issuing the Reset command
sequence.
The “Enable Reset (66H)” and the “Reset (99H)” commands can
be issued in SPI mode. The “Reset (99H)” command sequence as
follow: CS# goes low Sending Enable Reset command CS#
Figure 68 Enable Reset and Reset command Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6 7
Command
66H
Command
99H
High-Z
SO
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7.32. Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard
provides a consistent method of describing the functional and
feature capabilities of serial flash devices in a standard set of
internal parameter tables. These parameter tables can be
interrogated by host system software to enable adjustments
needed to accommodate divergent features from multiple vendors.
The concept is similar to the one found in the Introduction of
JEDEC Standard, JESD68 on CFI. SFDP is a standard of JEDEC
Standard No.216.
Figure 69 Read Serial Flash Discoverable Parameter command Sequence Diagram (ADS=0)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
5AH
24-bit address
23 22 21
SI
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
Figure 70 Read Serial Flash Discoverable Parameter command Sequence Diagram (ADS=1)
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39
SCLK
SI
Command
5AH
32-bit address
31 30 29
3
2
1
0
High-Z
SO
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
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Table 19 Signature and Parameter Identification Data Values
Description
Comment
Add(H)
(Byte)
DW Add
(Bit)
Data
Data
SFDP Signature
Fixed:50444653H
00H
01H
02H
03H
04H
05H
06H
07H
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
53H
46H
44H
50H
00H
01H
01H
FFH
53H
46H
44H
50H
00H
01H
01H
FFH
SFDP Minor Revision Number
SFDP Major Revision Number
Number of Parameters Headers
Unused
Start from 00H
Start from 01H
Start from 00H
Contains 0xFFH and can never be
changed
ID number (JEDEC)
00H: It indicates a JEDEC specified
header
08H
09H
0AH
0BH
07:00
15:08
23:16
31:24
00H
00H
01H
09H
00H
00H
01H
09H
Parameter Table Minor Revision
Number
Start from 0x00H
Parameter Table Major Revision
Number
Start from 0x01H
Parameter Table Length
(in double word)
How many DWORDs in the Parameter
table
Parameter Table Pointer (PTP)
First address of JEDEC Flash
Parameter table
0CH
0DH
0EH
0FH
07:00
15:08
23:16
31:24
30H
00H
00H
FFH
30H
00H
00H
FFH
Unused
Contains 0xFFH and can never be
changed
ID Number
It is indicates GigaDevice
manufacturer ID
10H
11H
12H
13H
07:00
15:08
23:16
31:24
C8H
00H
01H
03H
C8H
00H
01H
03H
(GigaDevice Manufacturer ID)
Parameter Table Minor Revision
Number
Start from 0x00H
Parameter Table Major Revision
Number
Start from 0x01H
Parameter Table Length
(in double word)
How many DWORDs in the Parameter
table
Parameter Table Pointer (PTP)
First address of GigaDevice Flash
Parameter table
14H
15H
16H
17H
07:00
15:08
23:16
31:24
60H
00H
00H
FFH
60H
00H
00H
FFH
Unused
Contains 0xFFH and can never be
changed
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Table 20 Parameter Table (0): JEDEC Flash Parameter Tables
Description
Comment
Add(H)
(Byte)
DW Add
(Bit)
Data
Data
00: Reserved; 01: 4KB erase;
10: Reserved;
Block/Sector Erase Size
01:00
02
01b
1b
11: not support 4KB erase
0: 1Byte, 1: 64Byte or larger
0: Nonvolatile status bit
1: Volatile status bit
Write Granularity
Write Enable Instruction
Requested for Writing to Volatile
Status Registers
03
0b
(BP status register bit)
0: Use 50H Opcode,
30H
E5H
1: Use 06H Opcode,
Write Enable Opcode Select for
Writing to Volatile Status Registers
Note: If target flash status register is
Nonvolatile, then bits 3 and 4 must be
set to 00b.
04
0b
Contains 111b and can never be
changed
Unused
07:05
111b
4KB Erase Opcode
31H
32H
15:08
16
20H
1b
20H
F3H
FFH
(1-1-2) Fast Read
0=Not support, 1=Support
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
Address Bytes Number used in
addressing flash array
18:17
01b
Double Transfer Rate (DTR) clocking 0=Not support, 1=Support
19
20
0b
1b
(1-2-2) Fast Read
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
0=Not support, 1=Support
0=Not support, 1=Support
0=Not support, 1=Support
21
1b
22
1b
23
1b
Unused
33H
31:24
31:00
FFH
Flash Memory Density
37H:34H
0FFFFFFFH
(1-4-4) Fast Read Number of Wait
0 0000b: Wait states (Dummy Clocks)
not support
04:00
00100b
states
38H
39H
3AH
3BH
44H
EBH
08H
6BH
(1-4-4) Fast Read Number of Mode
Bits
000b:Mode Bits not support
07:05
15:08
20:16
010b
EBH
(1-4-4) Fast Read Opcode
(1-1-4) Fast Read Number of Wait
states
0 0000b: Wait states (Dummy Clocks)
not support
01000b
(1-1-4) Fast Read Number of Mode
Bits
000b:Mode Bits not support
23:21
31:24
000b
6BH
(1-1-4) Fast Read Opcode
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Add(H)
(Byte)
DW Add
Description
Comment
Data
Data
(Bit)
(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy Clocks)
04:00
01000b
states
not support
3CH
3DH
3EH
3FH
08H
3BH
42H
BBH
(1-1-2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
07:05
15:08
20:16
000b
3BH
(1-1-2) Fast Read Opcode
(1-2-2) Fast Read Number
of Wait states
0 0000b: Wait states (Dummy Clocks)
not support
00010b
(1-2-2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
23:21
010b
(1-2-2) Fast Read Opcode
31:24
00
BBH
0b
(2-2-2) Fast Read
Unused
0=not support 1=support
0=not support 1=support
03:01
04
111b
0b
40H
EEH
(4-4-4) Fast Read
Unused
07:05
31:08
15:00
111b
0xFFH
0xFFH
Unused
43H:41H
45H:44H
0xFFH
0xFFH
Unused
(2-2-2) Fast Read Number
of Wait states
0 0000b: Wait states (Dummy Clocks)
not support
20:16
23:21
00000b
000b
46H
00H
(2-2-2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
(2-2-2) Fast Read Opcode
47H
31:24
15:00
FFH
FFH
Unused
49H:48H
0xFFH
0xFFH
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy Clocks)
20:16
00000b
states
not support
4AH
00H
(4-4-4) Fast Read Number
of Mode Bits
000b: Mode Bits not support
23:21
31:24
07:00
15:08
23:16
31:24
07:00
000b
FFH
0CH
20H
0FH
52H
10H
(4-4-4) Fast Read Opcode
4BH
4CH
4DH
4EH
4FH
50H
FFH
0CH
20H
0FH
52H
10H
Sector/block size=2^N bytes 0x00b:
Sector Type 1 Size
this sector type don’t exist
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size=2^N bytes 0x00b:
this sector type don’t exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size=2^N bytes 0x00b:
this sector type don’t exist
Sector Type 3 erase Opcode
Sector Type 4 Size
51H
52H
15:08
23:16
D8H
00H
D8H
00H
Sector/block size=2^N bytes 0x00b:
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this sector type don’t exist
Sector Type 4 erase Opcode
53H
31:24
FFH
FFH
Table 21 Parameter Table (1): GigaDevice Flash Parameter Tables
Add(H)
(Byte)
DW Add
Description
Comment
2000H=2.000V
Data
Data
(Bit)
Vcc Supply Maximum Voltage
2700H=2.700V
61H:60H
15:00
3600H
3600H
3600H=3.600V
1650H=1.650V
2250H=2.250V
Vcc Supply Minimum Voltage
63H:62H
31:16
2700H
2700H
2350H=2.350V
2700H=2.700V
HW Reset# pin
HW Hold# pin
0=not support 1=support
00
01
02
03
1b
1b
1b
0=not support 1=support
0=not support 1=support
Deep Power Down Mode
SW Reset
0=not support 1=support
Should be issue Reset Enable(66H)
before Reset cmd.
1b
1001 1001b
(99H)
SW Reset Opcode
65H:64H
11:04
F99FH
Program Suspend/Resume
Erase Suspend/Resume
Unused
0=not support 1=support
12
13
1b
0=not support 1=support
0=not support 1=support
1b
1b
14
Wrap-Around Read mode
Wrap-Around Read mode Opcode
15
1b
66H
67H
23:16
77H
77H
64H
08H:support 8B wrap-around read
16H:8B&16B
Wrap-Around Read data length
31:24
64H
32H:8B&16B&32B
64H:8B&16B&32B&64B
0=not support 1=support
Individual block lock
00
01
1b
1b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile 1=Nonvolatile
Individual block lock Opcode
09:02
10
E3H
1b
Individual block lock Volatile
protect bit default protect status
Secured OTP
0=protect 1=unprotect
C78FH
6BH:68H
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
0b
0b
Read Lock
Permanent Lock
Unused
13
0b
15:14
31:16
11b
Unused
FFFFH
FFFFH
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8. ELECTRICAL CHARACTERISTICS
8.1.
POWER-ON TIMING
Figure 71 Power-on Timing
Vcc(max)
Vcc(min)
VWI
Chip Selection is not allowed
Device is fully
accessible
tVSL
Time
Table 22 Power-Up Timing and Write Inhibit Threshold
Symbol
Parameter
Min
Max
Unit
ms
tVSL
VWI
VCC(min) To CS# Low
Write Inhibit Voltage
5
1.5
2.5
V
8.2.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH). The Status Register bits are set to
0, except DRV1 bit (S9) is set to 1.
8.3.
ABSOLUTE MAXIMUM RATINGS
Table 23 Absolute Maximum Ratings
Parameter
Ambient Operating Temperature
Storage Temperature
Applied Input/Output Voltage
VCC
Value
Unit
℃
℃
V
-40 to 85
-65 to 150
-0.5 to 4.0
-0.5 to 4.0
V
Figure 72 Input/Output Timing Reference Level
Input timing reference level
Output timing reference level
0.5VCC
0.8VCC
0.1VCC
0.7VCC
0.2VCC
AC Measurement Level
Note: Input pulse rise and fall time are<5ns
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8.4.
CAPACITANCE MEASUREMENT CONDITIONS
Table 24Capacitance Measurement Conditions
Symbol
CIN
Parameter
Min
Typ
Max
6
Unit
pF
pF
pF
ns
V
Conditions
VIN=0V
Input Capacitance
COUT
CL
Output Capacitance
8
VOUT=0V
Load Capacitance
30
Input Rise And Fall time
Input Pulse Voltage
5
0.1VCC to 0.8VCC
0.2VCC to 0.7VCC
0.5VCC
Input Timing Reference Voltage
Output Timing Reference Voltage
V
V
Figure 73 Input Test Waveform and Measurement Level
Maximum Negative Overshoot Waveform
20ns
Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
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8.5.
DC CHARACTERISTICS
Table 25 DC CHARACTERISTICS (T= -40℃~85℃, VCC=2.7~3.6V)
Symbol
ILI
ILO
Parameter
Test Condition
Min.
Typ
Max.
±2
Unit.
μA
Input Leakage Current
Output Leakage Current
Standby Current
±2
μA
ICC1
CS#=VCC,
30
1
100
μA
VIN=VCC or VSS
CS#=VCC,
ICC2
Deep Power-Down Current
5
μA
mA
mA
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 80MHz,
15
13
20
18
Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC / 0.9VCC
at 60MHz,
ICC3
Operating Current (Read)
Q=Open(*1,*2,*4 I/O)
CS#=VCC
ICC4
ICC5
ICC6
ICC7
VIL
Operating Current (PP)
Operating Current(WRSR)
Operating Current (SE)
Operating Current (BE)
Input Low Voltage
20
20
mA
mA
mA
mA
V
CS#=VCC
CS#=VCC
20
CS#=VCC
20
-0.5
0.2VCC
VCC+0.4
0.2
VIH
Input High Voltage
0.7VCC
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL =100uA
V
IOH =-100μA
VCC-0.2
V
Note:
1. Typical values given for TA=25°C.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
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8.6.
AC CHARACTERISTICS
Table 26 AC CHARACTERISTICS (T= -40℃~85℃, VCC=2.7~3.6V, CL=30pf)
Symbol
Parameter
Serial Clock Frequency for All Instructions Except Read
Serial Clock Frequency for Dual I/O (BBH, BCH), Quad I/O (EBH,
ECH), Dual Output(3BH, 3CH), Quad Output(6BH, 6CH), Fast Read
(0BH, 0CH) Instructions, on 3.0 - 3.6V power supply
Serial Clock Frequency for Dual I/O (BBH, BCH), Quad I/O (EBH,
ECH), Dual Output(3BH, 3CH), Quad Output(6BH, 6CH), Fast Read
(0BH, 0CH) Instructions, on 2.7 - 3.0V power supply
Serial Clock Frequency For: Read(03H, 13H)
Serial Clock High Time
Min.
Typ.
Max.
Unit.
fC
DC.
80
MHz
fC1
DC.
DC.
80
MHz
MHz
fC2
60
60
fR
DC.
5
MHz
ns
tCLH
tCLL
Serial Clock Low Time
5
ns
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
tCLQV
tWHSL
tSHWL
tDP
Serial Clock Rise Time (Slew Rate)
0.2
0.2
8
V/ns
V/ns
ns
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
CS# Active Hold Time
5
ns
CS# Not Active Setup Time
5
ns
CS# Not Active Hold Time
5
ns
CS# High Time (read/write)
20
ns
Output Disable Time
6
ns
Output Hold Time
1.2
2
ns
Data In Setup Time
ns
Data In Hold Time
2
ns
HOLD# Low Setup Time (relative to Clock)
HOLD# High Setup Time (relative to Clock)
HOLD# High Hold Time (relative to Clock)
HOLD# Low Hold Time (relative to Clock)
HOLD# Low To High-Z Output
5
ns
5
ns
5
ns
5
ns
6
8
7
ns
HOLD# Low To Low-Z Output
ns
Clock Low To Output Valid
ns
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High To Deep Power-Down Mode
CS# High To Standby Mode Without Electronic Signature Read
CS# High To Standby Mode With Electronic Signature Read
CS# High To Next Command After Suspend
CS# High To Next Command After Reset
Write Status Register Cycle Time
20
ns
100
ns
20
30
30
20
60
30
μs
μs
μs
us
tRES1
tRES2
tSUS
tRST
us
tW
5
ms
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tBP1
tBP2
tPP
tSE
tBE
tBE
tCE
Byte Program Time( First Byte)
Additional Byte Program Time ( After First Byte)
Page Programming Time
30
2.5
0.6
50
50
12
4
us
us
ms
ms
s
Sector Erase Time
500
1.2
2
Block Erase Time(32K Bytes)
Block Erase Time(64K Bytes)
Chip Erase Time(GPR25L25606F)
0.2
0.3
100
s
300
s
Note:
1. Typical values given for TA=25°C.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
Figure 74 Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tCLCH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
SI
MSB
High-Z
LSB
SO
Figure 75 Output Timing
CS#
tCLH
tSHQZ
SCLK
tCLQV
tCLQV
tCLQX
tCLL
tCLQX
SO
SI
LSB
Least significant address bit (LIB) in
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Figure 76 Hold Timing
CS#
tCHHL
tHLCH
tCHHH
tHHCH
tHHQX
SCLK
tHLQZ
SO
HOLD#
SI do not care during HOLD operation.
Figure 77 RESET Timing
tRB
CS#
RESET#
tRLRH
tRHSL
Table 27 Reset Timing
Parameter
Symbol
tRLRH
tRHSL
tRB
Setup
MIN
Speed
1
Unit.
us
Reset pulse width
Reset high time before read
Reset recovery time
MIN
50
ns
MAX
60
us
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9. ORDERING INFORMATION
9.1.
Valid Part Numbers
Product Number
GPR25L25606F-QS12x
Package Type
SOP 16L 300mil-Halogen Free Package
Note: x = 1 - 9, serial number.
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10. PACKAGE INFORMATION
10.1. Package Outline for SOP 16L (300MIL)
D
16
9
E1
E
h
L1
L
1
8
h
θ
“A”
b
c
Base Metal
A
A2
A1
Detail “A”
b
e
Dimensions
Symbol
Unit
A
A1
A2
b
c
D
E
E1
e
L
L1
h
θ
Min
-
-
0.10
0.20
0.30
2.05
-
0.31
0.41
0.51
0.10
0.25
0.33
10.20
10.30
10.40
10.10
10.30
10.50
7.40
7.50
7.60
0.40
-
0.25
-
0
-
mm
Nom
Max
1.27
1.40
2.65
2.55
1.27
0.75
8
Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.
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GPR25L25606F
11. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
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12. REVISION HISTORY
Date
Revision
Description
Page
Jul. 30, 2018
1.0
Original
All
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