GPR25L3203F [GENERALPLUS]
3V, 32M-BIT [x 1/x 2/x 4] CMOS MXSMIO(SERIAL MULTI I/O) FLASH MEMORY;
| 型号： | GPR25L3203F |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 3V, 32M-BIT [x 1/x 2/x 4] CMOS MXSMIO(SERIAL MULTI I/O) FLASH MEMORY |
| 文件： | 总47页 (文件大小：3713K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPR25L3203F
3V, 32M-BIT [x 1/x 2/x 4] CMOS
MXSMIO® (SERIAL MULTI I/O)
FLASH MEMORY
Jul. 09, 2015
Version 1.0
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPR25L3203F
Table of Contents
PAGE
1. FEATURES.................................................................................................................................................................................................. 4
1.1. GENERAL............................................................................................................................................................................................ 4
1.2. PERFORMANCE................................................................................................................................................................................. 4
1.3. SOFTWARE FEATURES..................................................................................................................................................................... 4
1.4. HARDWARE FEATURES .................................................................................................................................................................... 4
2. GENERAL DESCRIPTION.......................................................................................................................................................................... 4
3. PIN CONFIGURATIONS ............................................................................................................................................................................. 5
3.1. 8-PIN SOP (200MIL) ............................................................................................................................................................................. 5
4. PIN DESCRIPTION...................................................................................................................................................................................... 5
5. BLOCK DIAGRAM ...................................................................................................................................................................................... 6
6. DATA PROTECTION................................................................................................................................................................................... 7
7. MEMORY ORGANIZATION ........................................................................................................................................................................ 9
8. DEVICE OPERATION ............................................................................................................................................................................... 10
9. HOLD FEATURE....................................................................................................................................................................................... 11
10.COMMAND DESCRIPTION ...................................................................................................................................................................... 12
10.1.WRITE ENABLE (WREN)...................................................................................................................................................................... 13
10.2.WRITE DISABLE (WRDI) ...................................................................................................................................................................... 13
10.3.READ IDENTIFICATION (RDID).............................................................................................................................................................. 14
10.4.READ STATUS REGISTER (RDSR)........................................................................................................................................................ 14
10.5.READ CONFIGURATION REGISTER (RDCR)........................................................................................................................................... 14
10.6.WRITE STATUS REGISTER (WRSR)...................................................................................................................................................... 16
10.7.READ DATA BYTES (READ)................................................................................................................................................................. 18
10.8.READ DATA BYTES AT HIGHER SPEED (FAST_READ) ......................................................................................................................... 18
10.9.DUAL OUTPUT MODE (DREAD) ........................................................................................................................................................... 18
10.10. 2 X I/O READ MODE (2READ) ......................................................................................................................................................... 18
10.11. QUAD READ MODE (QREAD).......................................................................................................................................................... 19
10.12. 4 X I/O READ MODE (4READ) ......................................................................................................................................................... 19
10.13. PERFORMANCE ENHANCE MODE ..................................................................................................................................................... 20
10.14. PERFORMANCE ENHANCE MODE RESET .......................................................................................................................................... 20
10.15. BURST READ................................................................................................................................................................................... 20
10.16. SECTOR ERASE (SE)....................................................................................................................................................................... 21
10.17. BLOCK ERASE (BE)......................................................................................................................................................................... 21
10.18. BLOCK ERASE (BE32K) .................................................................................................................................................................. 21
10.19. CHIP ERASE (CE) ........................................................................................................................................................................... 21
10.20. PAGE PROGRAM (PP) ..................................................................................................................................................................... 22
10.21. 4 X I/O PAGE PROGRAM (4PP) ........................................................................................................................................................ 22
10.22. DEEP POWER-DOWN (DP)............................................................................................................................................................... 25
10.23. RELEASE FROM DEEP POWER-DOWN (RDP), READ ELECTRONIC SIGNATURE (RES)......................................................................... 25
10.24. READ ELECTRONIC MANUFACTURER ID & DEVICE ID (REMS).......................................................................................................... 25
10.25. ENTER SECURED OTP (ENSO)....................................................................................................................................................... 26
10.26. EXIT SECURED OTP (EXSO) .......................................................................................................................................................... 26
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10.27. READ SECURITY REGISTER (RDSCUR)........................................................................................................................................... 26
10.28. WRITE SECURITY REGISTER (WRSCUR)......................................................................................................................................... 27
10.29. PROGRAM SUSPEND AND ERASE SUSPEND...................................................................................................................................... 27
10.29.1. Program Suspend............................................................................................................................................................... 28
10.30. PROGRAM RESUME AND ERASE RESUME ......................................................................................................................................... 28
10.31. NO OPERATION (NOP) .................................................................................................................................................................... 28
10.32. SOFTWARE RESET (RESET-ENABLE (RSTEN) AND RESET (RST)) .................................................................................................... 28
10.33. READ SFDP MODE (RDSFDP) ....................................................................................................................................................... 29
11.POWER-ON STATE .................................................................................................................................................................................. 34
12.ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 35
12.1.ABSOLUTE MAXIMUM RATINGS............................................................................................................................................................. 35
12.2.CAPACITANCE TA = 25°C, F = 1.0 MHZ................................................................................................................................................ 35
13.TIMING ANALYSIS.................................................................................................................................................................................... 39
14.OPERATING CONDITIONS ...................................................................................................................................................................... 41
14.1.INITIAL DELIVERY STATE ....................................................................................................................................................................... 43
15.ERASE AND PROGRAMMING PERFORMANCE.................................................................................................................................... 43
16.DATA RETENTION ........................................................................................................................................................................................ 43
17.LATCH-UP CHARACTERISTICS ............................................................................................................................................................. 43
18.PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 44
18.1.ORDERING INFORMATION ..................................................................................................................................................................... 44
18.2.PACKAGE INFORMATION ....................................................................................................................................................................... 45
18.2.1. Package Outline for SOP 8L (200MIL)............................................................................................................................... 45
19.DISCLAIMER............................................................................................................................................................................................. 46
20.REVISION HISTORY................................................................................................................................................................................. 47
© Generalplus Technology Inc.
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Version: 1.0
GPR25L3203F
3V, 32M-BIT [x 1/x 2/x 4] CMOS MXSMIO®
(SERIAL MULTI I/O) FLASH MEMORY
1. FEATURES
1.1. GENERAL
• Auto Erase and Auto Program Algorithms
Automatically erases and verifies data at selected sector
Automatically programs and verifies data at selected page
by an internal algorithm that automatically times the
program pulse width (Any page to be programmed should
have page in the erased state first.)
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3
• 33,554,432 x 1 bit structure or 16,777,216 x 2 bits (two I/O
read mode) structure or 8,388,608 x 4 bits (four I/O mode)
structure
• Status Register Feature
• Command Reset
• Program/Erase Suspend
• Program/Erase Resume
• Electronic Identification
• 1024 Equal Sectors with 4K bytes each
Any Sector can be erased individually
• 128 Equal Blocks with 32K bytes each
Any Block can be erased individually
• 64 Equal Blocks with 64K bytes each
Any Block can be erased individually
• Power Supply Operation
2.65 ~ 3.6 volt for read, erase, and program operations
JEDEC 1-byte Manufacturer ID and 2-byte Device ID
RES command for 1-byte Device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
• Latch-up protected to 100mA from -1V to Vcc +1V
1.4. HARDWARE FEATURES
• SCLK Input
1.2. PERFORMANCE
Serial clock input
• SI/SIO0
Serial Data Input or Serial Data Input/Output for 2 x I/O
mode or Serial Data Input/Output for 4 x I/O mode
• SO/SIO1
Serial Data Output or Serial Data Input/Output for 2 x I/O
mode or Serial Data Input/Output for 4 x I/O mode
• WP#/SIO2
Hardware write protection or serial data Input/Output for 4 x
I/O mode
• HOLD#/SIO3
To pause the device without deselecting the device or serial
data Input/Output for 4 x I/O mode
• PACKAGE
• High Performance
VCC = 2.65~3.6V
Normal read
50MHz
Fast read
FAST_READ, DREAD, QREAD: 133MHz with 8 dummy
cycles
2READ: 104MHz with 4 dummy cycle, 133MHz with 8
dummy cycle
4READ: 104MHz with 6 dummy cycle, 133MHz with 10
dummy cycle
Configurable dummy cycle number for 2READ and 4READ
operation
8/16/32/64 byte Wrap-Around Burst Read Mode
8-pin SOP (200mil)
• Low Power Consumption
• Typical 100,000 erase/program cycles
All devices are RoHS Compliant and Halogen-free
1.3. SOFTWARE FEATURES
2. GENERAL DESCRIPTION
• Input Data Format
GPR25L3203F is 32Mb bits Serial Flash memory, which is
configured as 4,194,304 x 8 internally. When it is in four I/O mode,
the structure becomes 8,388,608 bits x 4. When it is in two I/O
mode, the structure becomes 16,777,216 bits x 2. GPR25L3203F
features a serial peripheral interface and software protocol
allowing operation on a simple 3-wire bus while it is in single I/O
mode. The three bus signals are a clock input (SCLK), a serial
data input (SI), and a serial data output (SO). Serial access to the
1-byte Command code
• Advanced Security Features
Block Lock Protection
The BP0-BP3 and T/B status bits define the site of the area to be
protected against program and erase instructions.
• Additional 4K bits secured OTP
Features unique identifier
Factory locked identifiable and customer lockable
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3. PIN CONFIGURATIONS
device is enabled by CS# input.
GPR25L3203F, MXSMIO® (Serial Multi I/O) flash memory,
provides sequential read operation on the whole chip and
multi-I/O features.
3.1. 8-PIN SOP (200mil)
When it is in quad I/O mode, the SI pin, SO pin, WP# pin and
HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin
for address/dummy bits input and data Input/Output.
After program/erase command is issued, auto program/erase
algorithms which program/erase and verify the specified page or
sector/block locations will be executed. Program command is
executed on byte basis, or page (256 bytes) basis. Erase
command is executed on 4K-byte sector, 32K-byte/64K-byte
block, or whole chip basis.
4. PIN DESCRIPTION
SYMBOL
CS#
DESCRIPTION
To provide user with ease of interface, a status register is
included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program
or erase operation via WIP bit.
Chip Select
SI/SIO0
Serial Data Input (for 1xI/O)/ Serial Data
Input & Output (for 2xI/O mode and
4xI/O mode)
When the device is not in operation and CS# is high, it is put in
standby mode.
SO/SIO1
Serial Data Output (for 1xI/O)/Serial
Data Input & Output (for 2xI/O mode and
4xI/O mode)
The GPR25L3203F utilizes Macronix's proprietary memory cell,
which reliably stores memory contents even after 100,000
program and erase cycles.
SCLK
Clock Input
WP#/SIO2
Write protection Active Low or Serial
Data Input & Output (for 4xI/O mode)
To pause the device without deselecting
the device or Serial data Input/Output for
4 x I/O mode
HOLD#/SIO3
VCC
GND
NC
+ 3.0V Power Supply
Ground
No Connection
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5. BLOCK DIAGRAM
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GPR25L3203F
6. DATA PROTECTION
During power transition, there may be some false system level
signals which result in inadvertent erasure or programming. The
device is designed to protect itself from these accidental write
cycles.
set the Write Enable Latch bit (WEL) before other command to
change data.
• Deep Power Down Mode: By entering deep power down mode,
the flash device also is under protected from writing all commands
except Release from Deep Power Down mode command (RDP)
and Read Electronic Signature command (RES).
The state machine will be reset as standby mode automatically
during power up. In addition, the control register architecture of the
device constrains that the memory contents can only be changed
after specific command sequences have completed successfully.
In the following, there are several features to protect the system
from the accidental write cycles during VCC power-up and
power-down or from system noise.
I. Block lock protection
- The Software Protected Mode (SPM) uses (TB, BP3, BP2, BP1,
BP0) bits to allow part of memory to be protected as read only. The
protected area definition is shown as table of "Table 1. Protected
Area Sizes", the protected areas are more flexible which may
protect various areas by setting value of TB, BP0-BP3 bits.
- The Hardware Protected Mode (HPM) uses WP#/SIO2 to protect
the (BP3, BP2, BP1, BP0, TB) bits and SRWD bit.
• Valid command length checking: The command length will be
checked whether it is at byte base and completed on byte
boundary.
• Write Enable (WREN) command: WREN command is required to
Table1. Protected Area Sizes
Protected Area Sizes (T/B bit = 0)
Status bit
Protect Level
BP3
0
BP2
0
BP1
0
BP0
0
32Mb
0 (none)
0
0
0
1
1 (1block, block 63rd)
0
0
1
0
2 (2blocks, block 62nd-63rd)
3 (4blocks, block 60th-63rd)
4 (8blocks, block 56th-63rd)
5 (16blocks, block 48th-63rd)
6 (32blocks, block 32nd-63rd)
7 (64blocks, protect all)
8 (64blocks, protect all)
9 (64blocks, protect all)
10 (64blocks, protect all)
11 (64blocks, protect all)
12 (64blocks, protect all)
13 (64blocks, protect all)
14 (64blocks, protect all)
15 (64blocks, protect all)
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Protected Area Sizes (T/B bit = 1)
Status bit
Protect Level
32Mb
BP3
BP2
BP1
BP0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0 (none)
1 (1block, block 0th)
2 (2blocks, block 0th-1st)
3 (4blocks, block 0th-3rd)
4 (8blocks, block 0th-7th)
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GPR25L3203F
Status bit
Protect Level
32Mb
BP3
0
BP2
1
BP1
0
BP0
1
5 (16blocks, block 0th-15th)
0
1
1
0
6 (32blocks, block 0th-31st)
7 (64blocks, protect all)
8 (64blocks, protect all)
9 (64blocks, protect all)
10 (64blocks, protect all)
11 (64blocks, protect all)
12 (64blocks, protect all)
13 (64blocks, protect all)
14 (64blocks, protect all)
15 (64blocks, protect all)
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0.
II. Additional 4K-bit secured OTP for unique identifier: to provide
4K-bit One-Time Program area for setting device unique serial
number - Which may be set by factory or system maker.
- Security register bit 0 indicates whether the chip is locked by
factory or not.
- Customer may lock-down the customer lockable secured OTP by
writing WRSCUR(write security register) command to set customer
lock-down bit1 as "1". Please refer to "Table 7. Security Register
Definition" for security register bit definition and "Table 2. 4K-bit
Secured OTP Definition" for address range definition.
Note: Once lock-down whatever by factory or customer, it cannot be
changed any more. While in 4K-bit Secured OTP mode, array access is not
allowed.
- To program the 4K-bit secured OTP by entering 4K-bit secured
OTP mode (with ENSO command), and going through normal
program procedure, and then exiting 4K-bit secured OTP mode by
writing EXSO command.
Table2. 4K-bit Secured OTP Definition
Address range
Size
Standard Factory Lock
Customer Lock
xxx000~xxx1FF
4096-bit
Determined by Customer
Determined by customer
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7. MEMORY ORGANIZATION
Table 3. Memory Organization
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8. DEVICE OPERATION
1. Before a command is issued, status register should be checked
to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this device, it enters
standby mode and remains in standby mode until next CS#
falling edge. In standby mode, SO pin of the device is High-Z.
3. When correct command is inputted to this device, it enters
active mode and remains in active mode until next CS# rising
edge.
5. For the following instructions: RDID, RDSR, RDSCUR, READ,
FAST_READ, RDSFDP, 4READ, QREAD, 2READ, DREAD,
RDCR, RES, and REMS the shifted-in instruction sequence is
followed by a data-out sequence. After any bit of data being
shifted out, the CS# can be high. For the following instructions:
WREN, WRDI, WRSR, SE, BE, BE32K, CE, PP, 4PP, Suspend,
Resume, NOP, RSTEN, RST, ENSO, EXSO, WRSCUR, the
CS# must go high exactly at the byte boundary; otherwise, the
instruction will be rejected and not executed.
4. For standard single data rate serial mode, input data is latched
on the rising edge of Serial Clock(SCLK) and data is shifted out
on the falling edge of SCLK. The difference of Serial mode 0
and mode 3 is shown as "Figure 1. Serial Modes Supported (for
Normal Serial mode)".
6. While a Write Status Register, Program, or Erase operation is in
progress, access to the memory array is neglected and will not
affect the current operation of Write Status Register, Program,
Erase.
Figure 1. Serial Modes Supported (for Normal Serial mode)
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase.
The combination of CPOL bit and CPHA bit decides which Serial mode is supported.
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GPR25L3203F
9. HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with
the device. The HOLD feature will not stop the operation of write
status register, programming, or erasing in progress.
HOLD operation will not start until Serial Clock signal being low).
The HOLD condition ends on the rising edge of HOLD# pin signal
while Serial Clock(SCLK) signal is being low (if Serial Clock signal
is not being low, HOLD operation will not end until Serial Clock
being low).
The operation of HOLD requires Chip Select (CS#) keeping low
and starts on falling edge of HOLD# pin signal while Serial Clock
(SCLK) signal is being low (if Serial Clock signal is not being low,
Figure2. Hold Condition Operation
During the HOLD operation, the Serial Data Output (SO) is high
impedance when Hold# pin goes low and will keep high
impedance until Hold# pin goes high. The Serial Data Input (SI) is
don't care if both Serial Clock (SCLK) and Hold# pin goes low and
will keep the state until SCLK goes low and Hold# pin goes high. If
Chip Select (CS#) drives high during HOLD operation, it will reset
the internal logic of the device. To re-start communication with chip,
the HOLD# must be at high and CS# must be at low.
Note: The HOLD feature is disabled during Quad I/O mode.
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GPR25L3203F
10. COMMAND DESCRIPTION
Table4. Command Sets
Read Commands
I/O
1
1
2
2
4
4
Command
READ
FAST READ
2READ
(2 x I/O read
command)
BB (hex)
ADD1(4)
ADD2(4)
ADD3(4)
Dummy*
DREAD
(1I / 2O read
command)
3B (hex)
4READ
(4 x I/O read
command)
EB (hex)
ADD1(2)
ADD2(2)
ADD3(2)
Dummy*
QREAD (1I/4O
read command)
(normal read)
(fast read data)
1st byte
2nd byte
3rd byte
4th byte
5th byte
03 (hex)
ADD1(8)
ADD2(8)
ADD3(8)
0B (hex)
ADD1(8)
ADD2(8)
ADD3(8)
Dummy(8)
6B (hex)
ADD1(8)
ADD2(8)
ADD3(8)
Dummy(8)
ADD1(8)
ADD2(8)
ADD3(8)
Dummy(8)
Action
n bytes read out n bytes read out n bytes read out n bytes read out Quad I/O read
until CS# goes until CS# goes by 2 x I/O until by Dual Output with configurable
high
high
CS# goes high
until CS# goes dummy cycles
high
Note: *Dummy cycle number will be different, depending on the bit6 (DC) setting of Configuration Register. Please refer to "Configuration Register" Table.
Other Commands
WRSR (write
WRDI
(write
RDSR (read RDCR (read
4PP (quad
page
WREN
status/
configuration
register)
SE
Command
status
configuration
register)
(write enable)
(sector erase)
disable)
register)
program)
1st byte
2nd byte
3rd byte
4th byte
06 (hex)
04 (hex)
05 (hex)
15 (hex)
01 (hex)
Values
Values
38 (hex)
ADD1
ADD2
ADD3
20 (hex)
ADD1
ADD2
ADD3
Action
sets the (WEL) resets
the to read out the to read out the to write new quad input to to erase the
write values of the values of the values of the program the selected
latch status register configuration configuration/ selected page sector
write
enable (WEL)
enable
latch bit
bit
register
status register
PGM/ERS
Suspend
BE 32K
BE
RDP (Release
from deep
CE
PP
DP (Deep
Command
(block erase
32KB)
(block erase
64KB)
(chip erase) (page program) power down)
(Suspends
power down)
Program/ Erase)
1st byte
2nd byte
3rd byte
4th byte
Action
52 (hex)
ADD1
ADD2
ADD3
D8 (hex)
ADD1
60 or C7 (hex)
02 (hex)
ADD1
ADD2
ADD3
B9 (hex)
AB (hex)
75/B0 (hex)
ADD2
ADD3
to erase the to erase the to erase whole to program the enters
deep release
down deep
from program/erase
power operation
selected 32KB selected 64KB chip
block block
selected page
power
mode
is
down mode
interrupted
suspend
by
command
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GPR25L3203F
Command
PGM/ERS
RDID
RES
(read REMS
(read ENSO
(enter
Resume
(read
electronic ID)
electronic secured OTP)
(Resumes
Program/Erase)
identification)
manufacturer &
device ID)
1st byte
2nd byte
3rd byte
4th byte
Action
7A/30 (hex)
9F (hex)
AB (hex)
90 (hex)
B1 (hex)
x
x
x
x
x
ADD
to
continue outputs JEDEC to read out 1-byte output
the to enter the 4K-bit
performing
suspended
program/erase
sequence
the ID:
1-byte Device ID
Manufacturer ID secured
OTP
Manufacturer ID
& Device ID
mode
& 2-byte Device
ID
Command EXSO (exit RDSCUR
WRSCUR
(write
RSTEN
RST
RDSFDP
SBL
(Set NOP
(No
(byte)
secured
OTP)
(read
(Reset
(Reset
Memory)
Burst
Length)
security
register)
security
register)
Enable)
Operation)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
C1 (hex)
2B (hex)
2F (hex)
66 (hex)
99 (hex)
5A (hex) C0/ 77 (hex)
ADD1(8)
00 (hex)
ADD2(8)
Value
ADD3(8)
Dummy(8)
to exit the
4K-bit
to read value to set the
of security lock-down
register
n bytes read to set Burst
out until CS# length
goes high
secured
OTP mode
bit as "1"
(once
lock-down,
cannot
be
update)
Note 1: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode.
Note 2: Before executing RST command, RSTEN command must be executed. If there is any other command to interfere, the reset operation will be disabled.
10.1. Write Enable (WREN)
10.2. Write Disable (WRDI)
The Write Enable (WREN) instruction is for setting Write Enable
Latch (WEL) bit. For those instructions like PP, 4PP, SE, BE,
BE32K, CE, and WRSR which are intended to change the device
content, should be set every time after the WREN instruction
setting the WEL bit.
The Write Disable (WRDI) instruction is for resetting Write Enable
Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→
sending WRDI instruction code→ CS# goes high.
The WEL bit is reset by following situations:
- Power-up
The sequence of issuing WREN instruction is: CS# goes low→
sending WREN instruction code→ CS# goes high.
The SIO[3:1] are don't care.
- WRDI command completion
- WRSR command completion
Figure 3. Write Enable (WREN) Sequence (Command 06)
- PP command completion
- 4PP command completion
- SE command completion
- BE32K command completion
- BE command completion
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- CE command completion
- PGM/ERS Suspend command completion
- Softreset command completion
- WRSCUR command completion
Figure 4. Write Disable (WRDI) Sequence (Command 04)
10.5. Read Configuration Register (RDCR)
The RDCR instruction is for reading Configuration Register Bits.
The Read Configuration Register can be read at any time (even in
program/erase/write configuration register condition). It is
recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write
configuration register operation is in progress.
10.3. Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte
and followed by Device ID of 2-byte. The Macronix Manufacturer
ID and Device ID are listed as table of "Table 6. ID Definitions".
The sequence of issuing RDID instruction is: CS# goes low→
sending RDID instruction code → 24-bits ID data out on SO→ to
end RDID operation can use CS# to high at any time during data
out.
The sequence of issuing RDCR instruction is: CS# goes
low→ sending RDCR instruction code→ Configuration
Register data out on SO.
The SIO[3:1] are don't care.
Figure 7. Read Configuration Register (RDCR) Sequence
While Program/Erase operation is in progress, it will not decode
the RDID instruction, so there's no effect on the cycle of
program/erase operation which is currently in progress. When
CS# goes high, the device is at standby stage.
Figure 5. Read Identification (RDID) Sequence (Command 9F)
Status Register
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates
whether the device is busy in program/erase/ write status register
progress. When WIP bit sets to 1, which means the device is busy
in program/erase/write status register progress. When WIP bit sets
to 0, which means the device is not in progress of program/erase/
write status register cycle.
10.4. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register. The Read
Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It
is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write status
register operation is in progress.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates
whether the device is set to internal write enable latch. When WEL
bit sets to "1", which means the internal write enable latch is set,
the device can accept program/erase/write status register
instruction. When WEL bit sets to 0, which means no internal write
enable latch; the device will not accept program/erase/write status
register instruction. The program/erase command will be ignored
and will reset WEL bit if it is applied to a protected memory area.
To ensure both WIP bit & WEL bit are both set to 0 and available
for next program/erase/operations, WIP bit needs to be confirm to
be 0 before polling WEL bit. After WIP bit confirmed, WEL bit
needs to be confirm to be 0.
The sequence of issuing RDSR instruction is: CS# goes low→
sending RDSR instruction code→ Status Register data out on SO.
The SIO[3:1] are don't care.
Figure 6. Read Status Register (RDSR) Sequence (Command
05)
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1,
BP0) bits, non-volatile bits, indicate the protected area (as defined
in "Table 1. Protected Area Sizes") of the device to against the
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program/erase instruction without hardware protection mode being
set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires
the Write Status Register (WRSR) instruction to be executed.
Those bits define the protected area of the memory to against
Page Program (PP), Sector Erase (SE), Block Erase (BE) and
Chip Erase (CE) instructions (only if all Block Protect bits set to 0,
the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits
are "0" as default. Which is un-protected.
other word, if the system goes into four I/O mode (QE=1), the
feature of HPM will be disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit,
non-volatile bit, default value is "0". SRWD bit is operated together
with Write Protection (WP#/SIO2) pin for providing hardware
protection mode. The hardware protection mode requires SRWD
sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware
protection mode, the Write Status Register (WRSR) instruction is
no longer accepted for execution and the SRWD bit and Block
Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit
defaults to be "0".
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0"
(factory default), it performs non-Quad and WP# is enable. While
QE is "1", it performs Quad I/O mode and WP# is disabled. In the
Status Register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SRWD (status
register write
protect)
BP3
BP2
BP1
BP0
WEL
(write enable
latch)
WIP
QE
(level of
(level of
(level of
(level of
(write in
(Quad Enable)
protected block) protected block) protected block) protected block)
progress bit)
1=write
1=status
register write
disable
1= Quad Enable
0=not Quad
Enable
1=write enable
0=not write
enable
operation
0=not in write
operation
volatile bit
(note 1)
(note 1)
(note 1)
(note 1)
Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit
volatile bit
Note: see the "Table 1. Protected Area Sizes".
Configuration Register
executed.
The Configuration Register is able to change the default status of
Flash memory. Flash memory will be configured after the CR bit is
set.
TB bit
The Top/Bottom (TB) bit is a OTP bit. The Top/Bottom (TB) bit is
used to configure the Block Protect area by BP bit (BP3, BP2, BP1,
BP0), starting from TOP or Bottom of the memory array. The TB bit
is defaulted as “0”, which means Top area protect. When it is set
as “1”, the protect area will change to Bottom area of the memory
device. To write the TB bit requires the Write Status Register
(WRSR) instruction to be executed.
ODS bit
The output driver strength ODS bit are volatile bits, which indicate
the output driver level of the device. The Output Driver Strength is
defaulted=1 when delivered from factory. To write the ODS bit
requires the Write Status Register (WRSR) instruction to be
Configuration Register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DC
TB
Reserved
Reserved
Reserved
Reserved
Reserved
ODS
(Dummy Cycle)
(top/bottom selected)
0,Output driver
strength=1
0=Top area protect
1=Bottom area protect
(Default=0)
2READ/4READ
Dummy Cycle
x
x
x
x
x
x
x
x
x
x
1,Output driver
strength=1/4
(Default=0)
volatile
volatile
OTP
Note: See "Dummy Cycle and Frequency Table", with "Don't Care" on other Reserved Configuration Registers.
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Dummy Cycle and Frequency Table
DC
Numbers of Dummy Cycles
Freq. (MHz)
104
0 (default)
4
8
2READ
4READ
1
0 (default)
1
133
6
104
10
133
10.6. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status
Register Bits and Configuration Register Bits. Before sending
WRSR instruction, the Write Enable (WREN) instruction must be
decoded and executed to set the Write Enable Latch (WEL) bit in
advance. The WRSR instruction can change the value of Block
Protect (BP3, BP2, BP1, BP0) bits to define the protected area of
memory (as shown in "Table 1. Protected Area Sizes"). The WRSR
also can set or reset the Quad enable (QE) bit and set or reset the
Status Register Write Disable (SRWD) bit in accordance with Write
Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL)
and bit0 (WIP) of the status register. The WRSR instruction cannot
be executed once the Hardware Protected Mode (HPM) is en-
tered.
Figure 8. Write Status Register (WRSR) Sequence (Command 01)
The CS# must go high exactly at the byte boundary; otherwise, the
instruction will be rejected and not executed. The self-timed Write
Status Register cycle time (tW) is initiated as soon as Chip Select
(CS#) goes high. The Write in Progress (WIP) bit still can be
checked out during the Write Status Register cycle is in progress.
The WIP sets 1 during the tW timing, and sets 0 when Write Status
Register Cycle is completed, and the Write Enable Latch (WEL) bit
is reset.
The sequence of issuing WRSR instruction is: CS# goes low→
sending WRSR instruction code→ Status Register data on SI→
CS# goes high.
Table 5. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Status register can be written in (WEL WP#=1 and SRWD bit=0, or
bit is set to "1") and the SRWD, WP#=0 and SRWD bit=0, or
Software protection
mode (SPM)
The protected area cannot
be program or erase.
BP0-BP3 bits can be changed
The SRWD, BP0-BP3, TB of
status register bits cannot be
changed
WP#=1 and SRWD=1
Hardware protection
mode (HPM)
The protected area cannot
be program or erase.
WP#=0, SRWD bit=1
Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0, TB) bits of the Status Register, as shown in "Table 1. Protected Area Sizes".
As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM):
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD,
BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM).
- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1,
BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM)
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM).
The data of the protected area is protected by software protected mode by BP3, BP2, BP1, BP0, TB and hardware protected mode by the
WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently
connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0, TB.
If the system goes into four I/O mode, the feature of HPM will be disabled.
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Figure 9. WRSR flow
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10.7. Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched
on rising edge of SCLK, and data shifts out on the falling edge of
SCLK at a maximum frequency fR. The first address byte can be
at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole
memory can be read out at a single READ instruction. The
address counter rolls over to 0 when the highest address has
been reached.
The sequence of issuing READ instruction is: CS# goes low→
sending READ instruction code→3-byte address on SI →data out
on SO→ to end READ operation can use CS# to high at any time
during data out.
10.9. Dual Output Mode (DREAD)
Figure 10. Read Data Bytes (READ) Sequence (Command 03)
The DREAD instruction enable double throughput of Serial Flash
in read mode. The address is latched on rising edge of SCLK, and
data of every two bits (interleave on 2 I/O pins) shift out on the
falling edge of SCLK at a maximum frequency fT. The first address
byte can be at any location. The address is automatically
increased to the next higher address after each byte data is
shifted out, so the whole memory can be read out at a single
DREAD instruction. The address counter rolls over to 0 when the
highest address has been reached. Once writing DREAD
instruction, the following data out will perform as 2-bit instead of
previous 1-bit.
10.8. Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The
address is latched on rising edge of SCLK, and data of each bit
shifts out on the falling edge of SCLK at a maximum frequency fC.
The first address byte can be at any location. The address is
automatically increased to the next higher address after each byte
data is shifted out, so the whole memory can be read out at a
single FAST_READ instruction. The address counter rolls over to
0 when the highest address has been reached.
The sequence of issuing DREAD instruction is: CS# goes low →
sending DREAD instruction → 3-byte address on SI → 8-bit
dummy cycle → data out interleave on SO1 & SO0 → to end
DREAD operation can use CS# to high at any time during data
out.
While Program/Erase/Write Status Register cycle is in progress,
DREAD instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
The sequence of issuing FAST_READ instruction is: CS# goes
low→ sending FAST_READ instruction code→ 3-byte address on
SI→1-dummy byte (default) address on SI→ data out on SO→ to
end FAST_READ operation can use CS# to high at any time
during data out. (Please refer to "Figure 11. Read at Higher Speed
(FAST_ READ) Sequence (Command 0B)")
Figure 12.Dual Read Mode Sequence (Command 3B)
While Program/Erase/Write Status Register cycle is in progress,
FAST_READ instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
Figure 11. Read at Higher Speed (FAST_READ) Sequence
(Command 0B)
10.10.2 x I/O Read Mode (2READ)
The 2READ instruction enables Double Transfer Rate of Serial
Flash in read mode. The address is latched on rising edge of
SCLK, and data of every two bits (interleave on 2 I/O pins) shift
out on the falling edge of SCLK at a maximum frequency fT. The
first address byte can be at any location. The address is
automatically increased to the next higher address after each byte
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data is shifted out, so the whole memory can be read out at a
single 2READ instruction. The address counter rolls over to 0
when the highest address has been reached. Once writing 2READ
instruction, the following address/dummy/data out will perform as
2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→
sending 2READ instruction→ 24-bit address interleave on SIO1 &
SIO0→ 4 dummy cycles(default) on SIO1 & SIO0→ data out
interleave on SIO1 & SIO0→ to end 2READ operation can use
CS# to high at any time during data out.
10.12.4 x I/O Read Mode (4READ)
While Program/Erase/Write Status Register cycle is in progress,
2READ instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
The 4READ instruction enables quad throughput of Serial Flash in
read mode. A Quad Enable (QE) bit of status Register must be set
to "1" before sending the 4READ instruction. The address is
latched on rising edge of SCLK, and data of every four bits
(interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The first address byte can be at any
location. The address is automatically increased to the next higher
address after each byte data is shifted out, so the whole memory
can be read out at a single 4READ instruction. The address
counter rolls over to 0 when the highest address has been
reached. Once writing 4READ instruction, the following
address/dummy/data out will perform as 4-bit instead of previous
1-bit.
Figure 13. 2 x I/O Read Mode Sequence (Command BB)
Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two
dummy cycles. In other words, P2=P0 or P3=P1 is necessary.
The sequence of issuing 4READ instruction is: CS# goes low→
sending 4READ instruction→ 24-bit address interleave on SIO3,
SIO2, SIO1 & SIO0→2+4 dummy cycles (default) →data out
interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ
operation can use CS# to high at any time during data out.
(Please refer to figure below)
10.11.Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial Flash in
read mode. The address is latched on rising edge of SCLK, and
data of every four bits (interleave on 4 I/O pins) shift out on the
falling edge of SCLK at a maximum frequency fQ. The first
address byte can be at any location. The address is automatically
increased to the next higher address after each byte data is
shifted out, so the whole memory can be read out at a single
QREAD instruction. The address counter rolls over to 0 when the
highest address has been reached. Once writing QREAD
instruction, the following data out will perform as 4-bit instead of
previous 1-bit.
Figure 15. 4 x I/O Read Mode Sequence (Command EB)
The sequence of issuing QREAD instruction is: CS# goes low→
sending QREAD instruction → 3-byte address on SI → 8-bit
dummy cycle → data out interleave on SIO3, SIO2, SIO1 &
SIO0→ to end QREAD operation can use CS# to high at any time
during data out.
Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
3. The Configurable Dummy Cycle is set by Configuration Register Bit.
Please see "Dummy Cycle and Frequency Table"
While Program/Erase/Write Status Register cycle is in progress,
QREAD instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
Another sequence of issuing 4READ instruction especially useful
Figure 14. Quad Read Mode Sequence (Command 6B)
in random access is
: CS# goes low→ sending 4READ
instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 &
SIO0 →performance enhance toggling bit P[7:0]→ 4 dummy
cycles → data out until CS# goes high → CS# goes low (reduce
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P4=P0, ex: AA, 00, FF
4READ instruction) → 24-bit random access address (Please refer
to "Figure 16. 4 x I/O Read enhance performance Mode Sequence
(Command EB) (SPI Mode)" ).
2. The Configurable Dummy Cycle is set by Configuration Register Bit.
Please see "Dummy Cycle and Frequency Table"
In the performance-enhancing mode (Notes of "Figure 16. 4 x I/O
Read enhance performance Mode Sequence (Command EB) (SPI
Mode)"), P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h,
5Ah, F0h or 0Fh can make this mode continue and reduce the
next 4READ instruction. Once P[7:4] is no longer toggling with
P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h. These commands
will reset the performance enhance mode. And afterwards CS# is
raised and then lowered, the system then will return to normal
operation.
10.14.Performance Enhance Mode Reset
To conduct the Performance Enhance Mode Reset operation in
SPI mode, FFh data cycle, 8 clocks, should be issued in 1I/O
sequence.
If the system controller is being Reset during operation, the flash
device will return to the standard SPI operation.
The SIO[3:1] are don't care.
Figure 17. Performance Enhance Mode Reset for Fast Read Quad
I/O
While Program/Erase/Write Status Register cycle is in progress,
4READ instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
10.13.Performance Enhance Mode
The device could waive the command cycle bits if the two cycle
bits after address cycle toggles. (Please note "Figure 16. 4 x I/O
Read enhance performance Mode Sequence (Command EB) (SPI
Mode)")
10.15.Burst Read
Performance enhance mode is supported for 4READ mode.
“EBh” commands support enhance mode.
To set the Burst length, following command operation is required.
Issuing command: “C0h” or “77h” in the first Byte (8-clocks),
following 4 clocks defining wrap around enable with “0h” and
disable with“1h”.
After entering enhance mode, following CS# go high, the device
will stay in the read mode and treat CS# go low of the first clock as
address instead of command cycle.
Next 4 clocks is to define wrap around depth. Definition as
following table:
To exit enhance mode, a new fast read command whose first two
dummy cycles is not toggle then exit. Or issue ”FFh” data cycles to
exit enhance mode.
Data
00h
01h
02h
03h
1xh
Wrap Around
Wrap Depth
8-byte
Yes
Yes
Yes
Yes
No
Figure 16. 4 x I/O Read enhance performance Mode Sequence
(Command EB) (SPI Mode)
16-byte
32-byte
64-byte
X
The wrap around unit is defined within the wrap-around depth
specified region. For example, if it is set to 32- byte wrap depth,
then address above A5 will be kept, it will read wrap around within
A[21:A5] specified page. To exit wrap around, it is required to
issue another “C0h” or “77h” command in which data=‘1xh”.
Otherwise, wrap around status will be retained until power down or
reset command. To change wrap around depth, it is requried to
issue another “C0h” or “77h” command in which data=“0xh”. “EBh”
support wrap around feature after wrap around enable. The
Device ID default without Burst read.
Note:
1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0
(Toggling), ex: A5, 5A, 0F, if not using performance enhance recommend to
keep 1 or 0 in performance enhance indicator.
Figure 18. Burst Read
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or
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Chip Select (CS#) goes high. The Write in Progress (WIP) bit still
can be checked while the Sector Erase cycle is in progress. The
WIP sets during the tBE timing, and clears when Sector Erase
Cycle is completed, and the Write Enable Latch (WEL) bit is
cleared. If the block is protected by BP3~0, the array data will be
protected (no change) and the WEL bit still be reset.
10.16.Sector Erase (SE)
Figure 20. Block Erase (BE) Sequence (Command D8)
The Sector Erase (SE) instruction is for erasing the data of the
chosen sector to be "1". The instruction is used for any 4K-byte
sector. A Write Enable (WREN) instruction must execute to set the
Write Enable Latch (WEL) bit before sending the Sector Erase
(SE). Any address of the sector (see "Table 3. Memory
Organization" ) is a valid address for Sector Erase (SE) instruction.
The CS# must go high exactly at the byte boundary (the least
significant bit of the address has been latched-in); otherwise, the
instruction will be rejected and not executed.
10.18.Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the
chosen block to be "1". The instruction is used for 32K-byte block
erase operation. A Write Enable (WREN) instruction must be
executed to set the Write Enable Latch (WEL) bit before sending
the Block Erase (BE32K). Any address of the block (see "Table 3.
Memory Organization" ) is a valid address for Block Erase (BE32K)
instruction. The CS# must go high exactly at the byte boundary
(the least significant bit of address byte has been latched-in);
otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32K instruction is: CS# goes low →
sending BE32K instruction code → 3-byte address on SI → CS#
goes high.
The sequence of issuing SE instruction is: CS# goes low →
sending SE instruction code→ 3-byte address on SI →CS# goes
high.
The SIO[3:1] are don't care.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon
as Chip Select (CS#) goes high. The Write in Progress (WIP) bit
still can be checked while the Sector Erase cycle is in progress.
The WIP sets during the tSE timing, and clears when Sector Erase
Cycle is completed, and the Write Enable Latch (WEL) bit is
cleared. If the sector is protected by BP3~0, the array data will be
protected (no change) and the WEL bit still be reset.
The SIO[3:1] are don't care.
Figure 19. Sector Erase (SE) Sequence (Command 20)
The self-timed Block Erase Cycle time (tBE32K) is initiated as
soon as Chip Select (CS#) goes high. The Write in Progress (WIP)
bit still can be checked while the Sector Erase cycle is in progress.
The WIP sets during the tBE32K timing, and clears 0 when Sector
Erase Cycle is completed, and the Write Enable Latch (WEL) bit is
cleared. If the block is protected by BP3~0, the array data will be
protected (no change) and the WEL bit still be reset.
10.17.Block Erase (BE)
Figure 21. Block Erase 32KB (BE32K) Sequence (Command 52)
The Block Erase (BE) instruction is for erasing the data of the
chosen block to be "1". The instruction is used for 64K-byte block
erase operation. A Write Enable (WREN) instruction must be
executed to set the Write Enable Latch (WEL) bit before sending
the Block Erase (BE). Any address of the block (see "Table 3.
Memory Organization") is a valid address for Block Erase (BE)
instruction. The CS# must go high exactly at the byte boundary
(the least significant bit of address byte has been latched-in);
otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low →
sending BE instruction code → 3-byte address on SI → CS# goes
high.
10.19.Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the
whole chip to be "1". A Write Enable (WREN) instruction must be
executed to set the Write Enable Latch (WEL) bit before sending
the Chip Erase (CE). The CS# must go high exactly at the byte
boundary; otherwise, the instruction will be rejected and not
executed.
The SIO[3:1] are don't care.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as
The sequence of issuing CE instruction is: CS# goes low →
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sending CE instruction code → CS# goes high.
be protected (no change) and the WEL bit will still be reset.
The SIO[3:1] are don't care.
The SIO[3:1] are don't care.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as
Chip Select (CS#) goes high. The Write in Progress (WIP) bit still
can be checked while the Chip Erase cycle is in progress. The
WIP sets during the tCE timing, and clears when Chip Erase Cycle
is completed, and the Write Enable Latch (WEL) bit is cleared. If
the chip is protected the Chip Erase (CE) instruction will not be
executed, but WEL will be reset.
Figure 23. Page Program (PP) Sequence (Command 02)
Figure 22. Chip Erase (CE) Sequence (Command 60 or C7)
10.21.4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the
memory to be "0". A Write Enable (WREN) instruction must be
executed to set the Write Enable Latch (WEL) bit and Quad
Enable (QE) bit must be set to "1" before sending the Quad Page
Program (4PP). The Quad Page Programming takes four pins:
SIO0, SIO1, SIO2, and SIO3, which can raise programmer
performance and the effectiveness of application of lower clock
less than 133MHz. For system with faster clock, the Quad page
program cannot provide more performance, because the required
internal page program time is far more than the time data flows in.
Therefore, we suggest that while executing this command
(especially during sending data), user can slow the clock speed
down to 133MHz below. The other function descriptions are as
same as standard page program.
10.20.Page Program (PP)
The Page Program (PP) instruction is for programming the
memory to be "0". A Write Enable (WREN) instruction must be
executed to set the Write Enable Latch (WEL) bit before sending
the Page Program (PP). The device programs only the last 256
data bytes sent to the device. The last address byte (the eight
least significant address bits, A7-A0) should be set to 0 for 256
bytes page program. If A7-A0 are not all zero, transmitted data
that exceed page length are programmed from the starting
address (24-bit address that last 8 bit are all 0) of currently
selected page. If the data bytes sent to the device exceeds 256,
the last 256 data byte is programmed at the requested page and
previous data will be disregarded. If the data bytes sent to the
device has not exceeded 256, the data will be programmed at the
request address of the page. There will be no effort on the other
data bytes of the same page.
The sequence of issuing 4PP instruction is: CS# goes low→
sending 4PP instruction code→ 3-byte address on SIO[3:0]→ at
least 1-byte on data on SIO[3:0]→ CS# goes high.
The sequence of issuing PP instruction is: CS# goes low→
sending PP instruction code→ 3-byte address on SI→ at least
1-byte on data on SI→ CS# goes high.
If the page is protected by BP3~0, the array data will be protected
(no change) and the WEL bit will still be reset.
Figure 24. 4 x I/O Page Program (4PP) Sequence (Command 38)
The CS# must be kept to low during the whole Page Program
cycle; The CS# must go high exactly at the byte boundary (the
latest eighth bit of data being latched in), otherwise, the instruction
will be rejected and will not be executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon
as Chip Select (CS#) goes high. The Write in Progress (WIP) bit
still can be checked while the Page Program cycle is in progress.
The WIP sets during the tPP timing, and clears when Page
Program Cycle is completed, and the Write Enable Latch (WEL)
bit is cleared. If the page is protected by BP3~0, the array data will
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The Program/Erase function instruction function flow is as follows:
Figure 25. Program/Erase Flow(1) with read array data
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Figure 26. Program/Erase Flow(2) without read array data
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10.22.Deep Power-down (DP)
program/erase/write cycles in progress.
The SIO[3:1] are don't care when during this mode.
The Deep Power-down (DP) instruction is for setting the device to
minimum power consumption (the standby current is reduced from
ISB1 to ISB2). The Deep Power-down mode requires the Deep
Power-down (DP) instruction to enter, during the Deep
Power-down mode, the device is not active and all
Write/Program/Erase instructions are ignored. When CS# goes
high, the device is in standby mode not deep power-down mode.
The sequence of issuing DP instruction is: CS# goes low→
sending DP instruction code→ CS# goes high.
The RES instruction is ended by CS# goes high after the ID been
read out at least once. The ID outputs repeatedly if continuously
send the additional clock cycles on SCLK while CS# is at low. If
the device was not previously in Deep Power-down mode, the
device transition to standby mode is immediate. If the device was
previously in Deep Power-down mode, there's a delay of tRES2 to
transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be
selected, so it can receive, decode, and execute instruction.
The RDP instruction is for releasing from Deep Power-down Mode.
Figure 28. Release from Deep Power-down and Read Electronic
Signature (RES) Sequence (Command AB)
The SIO[3:1] are don't care when during this mode.
Once the DP instruction is set, all instructions will be ignored
except the Release from Deep Power-down mode (RDP) and
Read Electronic Signature (RES) instruction. (those instructions
allow the ID being reading out). When Power-down, the deep
power-down mode automatically stops, and when power-up, the
device automatically is in standby mode. For RDP instruction the
CS# must go high exactly at the byte boundary (the latest eighth
bit of instruction code has been latched-in); otherwise, the
instruction will not be executed. As soon as Chip Select (CS#)
goes high, a delay of tDP is required before entering the Deep
Power-down mode and reducing the current to ISB2.
Figure 29. Release from Deep Power-down (RDP) Sequence
Figure 27. Deep Power-down (DP) Sequence (Command B9)
10.24.Read Electronic Manufacturer ID & Device ID
(REMS)
10.23.Release from Deep Power-down (RDP), Read
Electronic Signature (RES)
The REMS instruction is an alternative to the Release from
Power-down/Device ID instruction that provides both the JEDEC
assigned manufacturer ID and the specific device ID.
The Release from Deep Power-down (RDP) instruction is
completed by driving Chip Select (CS#) High. When Chip Select
(CS#) is driven High, the device is put in the standby Power mode.
If the device was not previously in the Deep Power-down mode,
the transition to the standby Power mode is immediate. If the
device was previously in the Deep Power-down mode, though, the
transition to the standby Power mode is delayed by tRES2, and
Chip Select (CS#) must remain High for at least tRES2(max), as
specified in "Table 15. AC Characteristics". Once in the standby
mode, the device waits to be selected, so that it can receive,
decode and execute instructions.
The REMS instruction is very similar to the Release from
Power-down/Device ID instruction. The instruction is initiated by
driving the CS# pin low and shift the instruction code "90h"
followed by two dummy bytes and one bytes address (A7~A0).
After which, the Manufacturer ID for Macronix (C2h) and the
Device ID are shifted out on the falling edge of SCLK with most
significant bit (MSB) first. The Device ID values are listed in "Table
6. ID Definitions". If the one-byte address is initially set to 01h,
then the device ID will be read first and then followed by the
Manufacturer ID. The Manufacturer and Device IDs can be read
continuously, alternating from one to the other. The instruction is
completed by driving CS# high.
RES instruction is for reading out the old style of 8-bit Electronic
Signature, whose values are shown as "Table 6. ID Definitions".
This is not the same as RDID instruction. It is not recommended to
use for new design. For new design, please use RDID instruction.
Even in Deep power-down mode, the RDP and RES are also
allowed to be executed, only except the device is in progress of
program/erase/write cycles; there's no effect on the current
Figure 30. Read Electronic Manufacturer & Device ID (REMS)
Sequence
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The sequence of issuing EXSO instruction is: CS# goes low→
sending EXSO instruction to exit Secured OTP mode→ CS# goes
high.
The SIO[3:1] are don't care.
10.27.Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security
Register. The Read Security Register can be read at any time
(even in program/erase/write status register/write security register
condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→
sending RDSCUR instruction → Security Register data out on
SO→ CS# goes high.
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output
device ID first.
The SIO[3:1] are don't care.
Table 6. ID Definitions
Figure 31. Read Security Register (RDSCUR) Sequence
(Command 2B)
Command Type
GPR25L3203F
Manufactory
Memory
Memory
density
16
RDID
ID
type
C2
20
Electronic ID
15
RES
Manufactory
Device ID
15
REMS
ID
The definition of the Security Register is as below:
C2
Secured OTP Indicator bit. The Secured OTP indicator bit shows
the chip is locked by factory or not. When it is "0", it indicates
non-factory lock; "1" indicates factory- lock.
10.25.Enter Secured OTP (ENSO)
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR
instruction, the LDSO bit may be set to "1" for customer lock-down
purpose. However, once the bit is set to "1" (lock-down), the LDSO
bit and the 4K-bit Secured OTP area cannot be updated any more.
Program Suspend Status bit. Program Suspend Bit (PSB)
indicates the status of Program Suspend operation. Users may
use PSB to identify the state of flash memory. After the flash
memory is suspended by Program Suspend command, PSB is set
to "1". PSB is cleared to "0" after program operation resumes.
Erase Suspend Status bit. Erase Suspend Bit (ESB) indicates
the status of Erase Suspend operation. Users may use ESB to
identify the state of flash memory. After the flash memory is
suspended by Erase Suspend command, ESB is set to "1". ESB is
cleared to "0" after erase operation resumes.
The ENSO instruction is for entering the additional 4K-bit Secured
OTP mode. While the device is in 4K-bit Secured OTP mode, array
access is not available. The additional 4K-bit Secured OTP is
independent from main array, and may be used to store unique
serial number for system identifier. After entering the Secured OTP
mode, follow standard read or program procedure to read out the
data or update data. The Secured OTP data cannot be updated
again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→
sending ENSO instruction to enter Secured OTP mode→ CS#
goes high.
The SIO[3:1] are don't care.
Please note that WRSR/WRSCUR/CE/BE/SE/BE32K commands
are not acceptable during the access of secure OTP region, once
Security OTP is locked down, only read related commands are
valid.
Program Fail Flag bit. While a program failure happened, the
Program Fail Flag bit would be set. If the program operation fails
on a protected memory region or locked OTP region, this bit will
also be set. This bit can be the failure indication of one or more
program operations. This fail flag bit will be cleared automatically
after the next successful program operation.
10.26.Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit Secured
OTP mode.
Erase Fail Flag bit. While an erase failure happened, the Erase
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Fail Flag bit would be set. If the erase operation fails on a
protected memory region or locked OTP region, this bit will also be
set. This bit can be the failure indication of one or more erase
operations. This fail flag bit will be cleared automatically after the
next successful erase operation.
Table 7. Security Register Definition
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
LDSO
(lock-down
4K-bit
Secured OTP
Indicator bit
(4K-bit
ESB (Erase
PSB (Program
Reserved
E_FAIL
P_FAIL
Reserved
Suspend status) Suspend status)
Secured OTP) Secured OTP)
0 = not
0=normal
Program
0=normal Erase
succeed
0=Erase is not
suspended
1=Erase is
suspended
(default=0)
0=Program is
not suspended
1=Program is
suspended
lockdown
1 = lock-down
(cannot
0 = nonfactory
lock
succeed
Reserved
1=indicate
Reserved
volatile bit
1=indicate
Program failed
(default=0)
volatile bit
Read Only
1 = factory
lock
Erase failed
(default=0)
program/ erase
OTP)
(default=0)
non-volatile bit
Reserved
volatile bit
Read Only
volatile bit
Read Only
volatile bit
Read Only
non-volatile bit non-volatile bit
OTP Read Only
10.28. Write Security Register (WRSCUR)
Table 8. Readable Area of Memory While a Program or Erase
Operation is Suspended
The WRSCUR instruction is for changing the values of Security
Register Bits. Unlike write status register, the WREN instruction is
required before sending WRSCUR instruction. The WRSCUR
instruction may change the values of bit1 (LDSO bit) for customer
to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is
set to "1", the Secured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→
sending WRSCUR instruction → CS# goes high.
Suspended Operation Readable Region of Memory Array
Page Program
All but the Page being programmed
All but the 4KB Sector being erased
All but the 32KB Block being erased
All but the 64KB Block being erased
Sector Erase (4KB)
Block Erase (32KB)
Block Erase (64KB)
When the serial flash receives the Suspend instruction, there is a
latency of tPSL or tESL ("Figure 33. Suspend to Read Latency")
before the Write Enable Latch (WEL) bit clears to “0” and the PSB
or ESB sets to “1”, after which the device is ready to accept one of
the commands listed in "Table 9. Acceptable Commands During
Program/Erase Suspend after tPSL/tESL" (e.g. FAST READ).
Refer to "Table 15. AC Characteristics" for tPSL and tESL timings.
"Table 10. Acceptable Commands During Suspend (tPSL/tESL not
required)" lists the commands for which the tPSL and tESL
latencies do not apply. For example, RDSR, RDSCUR, RSTEN,
and RST can be issued at any time after the Suspend instruction.
Security Register bit 2 (PSB) and bit 3 (ESB) can be read to check
the suspend status. The PSB (Program Suspend Bit) sets to “1”
when a program operation is suspended. The ESB (Erase
Suspend Bit) sets to “1” when an erase operation is suspended.
The PSB or ESB clears to “0” when the program or erase
operation is resumed.
The SIO[3:1] are don't care.
The CS# must go high exactly at the boundary; otherwise, the
instruction will be rejected and not executed.
Figure 32. Write Security Register (WRSCUR) Sequence
(Command 2F) (SPI mode)
10.29. Program Suspend and Erase Suspend
The Suspend instruction interrupts a Page Program, Sector Erase,
or Block Erase operation to allow access to the memory array.
After the program or erase operation has entered the suspended
state, the memory array can be read except for the page being
programmed or the sector or block being erased ("Table 8.
Readable Area of Memory While a Program or Erase Operation is
Suspended").
Table 9. Acceptable Commands During Program/Erase Suspend
after tPSL/tESL
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Programming is permitted in any unprotected memory except
within the sector of a suspended Sector Erase operation or within
the block of a suspended Block Erase operation. The Write Enable
(WREN) instruction must be issued before any Page Program
instruction.
Suspend Type
Command
Name
Command
Code
Program
Erase
Suspend
Suspend
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
READ
FAST READ
DREAD
QREAD
2READ
4READ
RDSFDP
RDID
03h
0Bh
A Page Program operation initiated within a suspended erase
cannot itself be suspended and must be allowed to finish before
the suspended erase can be resumed. The Status Register can be
polled to determine the status of the Page Program operation. The
WEL and WIP bits of the Status Register will remain “1” while the
Page Program operation is in progress and will both clear to “0”
when the Page Program operation completes.
3Bh
6Bh
BBh
EBh
5Ah
9Fh
REMS
90h
Figure 35.Suspend to Program Latency
ENSO
B1h
EXSO
C1h
SBL
C0h or 77h
06h
WREN
RESUME
PP
•
7Ah or 30h
02h
10.30. Program Resume and Erase Resume
The Resume instruction resumes a suspended Page Program,
Sector Erase, or Block Erase operation. Before issuing the
Resume instruction to restart a suspended erase operation, make
sure that there is no Page Program operation in progress.
Immediately after the serial flash receives the Resume instruction,
the WEL and WIP bits are set to “1” and the PSB or ESB is cleared
to “0”. The program or erase operation will continue until finished
("Figure 36. Resume to Read Latency") or until another Suspend
instruction is received. A resume-to-suspend latency of tPRS or
tERS must be observed before issuing another Suspend
instruction ("Figure 34. Resume to Suspend Latency").
4PP
38h
Table 10.Acceptable Commands During Suspend (tPSL/tESL not
required)
Suspend Type
Suspend
Type
Suspend
Type
Program
Suspend
Erase
Suspend
WRDI
RDSR
RDCR
RDSCUR
RES
04h
05h
15h
2Bh
ABh
66h
99h
00h
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Please note that the Resume instruction will be ignored if the serial
flash is in “Performance Enhance Mode”. Make sure the serial
flash is not in “Performance Enhance Mode” before issuing the
Resume instruction.
RSTEN
RST
Figure 36.Resume to Read Latency
NOP
Figure 33.Suspend to Read Latency
10.31. No Operation (NOP)
The "No Operation" command is only able to terminate the Reset
Enable (RSTEN) command and will not affect any other command.
Figure 34.Resume to Suspend Latency
10.32. Software Reset (Reset-Enable (RSTEN) and
Reset (RST))
The Software Reset operation combines two instructions:
Reset-Enable (RSTEN) command and Reset (RST) command. It
returns the device to a standby mode. All the volatile bits and
settings will be cleared then, which makes the device return to the
10.29.1. Program Suspend
The “Erase Suspend to Program” feature allows Page
Programming while an erase operation is suspended. Page
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default status as power on.
The concept is similar to the one found in the Introduction of
JEDEC Standard, JESD68 on CFI.
To execute Reset command (RST), the Reset-Enable (RSTEN)
command must be executed first to perform the Reset operation. If
there is any other command to interrupt after the Reset-Enable
command, the Reset-Enable will be invalid.
The sequence of issuing RDSFDP instruction is CS# goes
low→send RDSFDP instruction (5Ah)→send 3 address bytes on
SI pin→send 1 dummy byte on SI pin→read SFDP code on
SO→to end RDSFDP operation can use CS# to high at any time
during data out.
If the Reset command is executed during program or erase
operation, the operation will be disabled, the data under
processing could be damaged or lost.
SFDP is a JEDEC Standard, JESD216.
The reset time is different depending on the last operation. Longer
latency time is required to recover from a program operation than
from other operations.
Figure 38.Read Serial Flash Discoverable Parameter (RDSFDP)
Sequence
Figure 37.Software Reset Recovery
10.33. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard
provides a consistent method of describing the functional and
feature capabilities of serial flash devices in a standard set of
internal parameter tables. These parameter tables can be
interrogated by host system software to enable adjustments
needed to accommodate divergent features from multiple vendors.
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Table 11. Signature and Parameter Identification Data Values
Add (h)
(Byte)
DW Add
(Bit)
Data (h/b)
(Note1)
Data
(h)
Description
Comment
00h
01h
02h
03h
04h
05h
07:00
15:08
23:16
31:24
07:00
15:08
53h
46h
44h
50h
00h
01h
53h
46h
44h
50h
00h
01h
SFDP Signature
Fixed: 50444653h
SFDP Minor Revision Number
SFDP Major Revision Number
Start from 00h
Start from 01h
This number is 0-based. Therefore,
indicates 1 parameter header.
0
Number of Parameter Headers
06h
23:16
01h
01h
Unused
07h
08h
31:24
07:00
FFh
00h
FFh
00h
ID number (JEDEC)
Parameter Table Minor Revision
Number
00h: it indicates a JEDEC specified header.
Start from 00h
09h
0Ah
0Bh
15:08
23:16
31:24
00h
01h
09h
00h
01h
09h
Parameter Table Major Revision
Number
Start from 01h
Parameter Table Length
(in double word)
How many DWORDs in the Parameter table
0Ch
0Dh
0Eh
0Fh
07:00
15:08
23:16
31:24
30h
00h
00h
FFh
30h
00h
00h
FFh
First address of JEDEC Flash Parameter
table
Parameter Table Pointer (PTP)
Unused
ID number
it indicates Macronix manufacturer ID
Start from 00h
10h
11h
12h
13h
07:00
15:08
23:16
31:24
C2h
00h
01h
04h
C2h
00h
01h
04h
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Start from 01h
Parameter Table Length
(in double word)
How many DWORDs in the Parameter table
14h
15h
16h
17h
07:00
15:08
23:16
31:24
60h
00h
00h
FFh
60h
00h
00h
FFh
First address of Macronix Flash Parameter
table
Parameter Table Pointer (PTP)
Unused
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Table 12. Parameter Table (0): JEDEC Flash Parameter Tables
Add (h)
(Byte)
DW Add
(Bit)
Data (h/b)
(Note1)
Data
(h)
Description
Comment
00: Reserved, 01: 4KB erase, 10: Reserved,
11: not support 4KB erase
Block/Sector Erase sizes
Write Granularity
01:00
02
01b
1b
E5h
0: 1Byte, 1: 64Byte or larger
Write
Required for Writing to Volatile 1: required 00h to be written to the status
Status Registers register
Enable
Instruction 0: not required
03
04
0b
0b
30h
Write Enable Opcode Select for 0: use 50h opcode,1: use 06h opcodeNote:
Writing to Volatile Status If target flash status register is nonvolatile,
Registers
then bits 3 and 4 must be set to 00b.
Unused
Contains 111b and can never be changed
07:05
15:08
16
111b
20h
1b
4KB Erase Opcode
(1-1-2) Fast Read (Note2)
31h
32h
20h
F1h
FFh
0=not support 1=support
Address Bytes Number used in 00: 3Byte only, 01: 3 or 4Byte,10: 4Byte
18:17
19
00b
0b
addressing flash array
Double Transfer Rate (DTR)
Clocking
only, 11: Reserved
0=not support 1=support
(1-2-2) Fast Read
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
20
21
1b
1b
22
1b
23
1b
Unused
33h
31:24
31:00
FFh
Flash Memory Density
37h:34h
01FF FFFFh
(1-4-4) Fast Read Number of 0 0000b: Not supported; 0 0100b: 4
Wait states (Note3) 0 0110b: 6; 0 1000b: 8
(1-4-4) Fast Read Number of Mode Bits:
04:00
0 0100b
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
44h
EBh
08h
6Bh
08h
3Bh
04h
07:05
15:08
20:16
010b
EBh
Mode Bits (Note4)
000b: Not supported; 010b: 2 bits
(1-4-4) Fast Read Opcode
(1-1-4) Fast Read Number of 0 0000b: Not supported; 0 0100b: 4
0 1000b
Wait states
0 0110b: 6; 0 1000b: 8
(1-1-4) Fast Read Number of Mode Bits:
23:21
31:24
04:00
000b
6Bh
Mode Bits
000b: Not supported; 010b: 2 bits
(1-1-4) Fast Read Opcode
(1-1-2) Fast Read Number of 0 0000b: Not supported; 0 0100b: 4
0 1000b
Wait states
0 0110b: 6; 0 1000b: 8
(1-1-2) Fast Read Number of Mode Bits:
07:05
15:08
20:16
000b
3Bh
Mode Bits
000b: Not supported; 010b: 2 bits
(1-1-2) Fast Read Opcode
(1-2-2) Fast Read Number of 0 0000b: Not supported; 0 0100b: 4
0 0100b
Wait states
0 0110b: 6; 0 1000b: 8
(1-2-2) Fast Read Number of Mode Bits:
23:21
000b
Mode Bits
000b: Not supported; 010b: 2 bits
(1-2-2) Fast Read Opcode
(2-2-2) Fast Read
Unused
3Fh
40h
31:24
00
BBh
0b
BBh
EEh
0=not support 1=support
03:01
111b
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Add (h)
(Byte)
DW Add
(Bit)
Data (h/b)
(Note1)
Data
(h)
Description
Comment
(4-4-4) Fast Read
Unused
0=not support 1=support
04
0b
07:05
31:08
15:00
111b
FFh
FFh
Unused
43h:41h
45h:44h
FFh
FFh
Unused
(2-2-2) Fast Read Number of 0 0000b: Not supported; 0 0100b: 4
Wait states 0 0110b: 6; 0 1000b: 8
(2-2-2) Fast Read Number of Mode Bits:
20:16
23:21
0 0000b
000b
46h
00h
Mode Bits
000b: Not supported; 010b: 2 bits
(2-2-2) Fast Read Opcode
47h
31:24
15:00
FFh
FFh
FFh
FFh
Unused
49h:48h
(4-4-4) Fast Read Number of 0 0000b: Not supported; 0 0100b: 4
20:16
0 0000b
Wait states
0 0110b: 6; 0 1000b: 8
4Ah
00h
(4-4-4) Fast Read Number of Mode Bits:
23:21
31:24
07:00
15:08
23:16
31:24
07:00
000b
FFh
0Ch
20h
0Fh
52h
10h
Mode Bits
000b: Not supported; 010b: 2 bits
(4-4-4) Fast Read Opcode
4Bh
4Ch
4Dh
4Eh
4Fh
50h
FFh
0Ch
20h
0Fh
52h
10h
Sector/block size = 2^N bytes (Note5)0Ch:
4KB; 0Fh: 32KB; 10h: 64KB
Sector Type 1 Size
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
00h: N/A; 0Fh: 32KB; 10h: 64KB
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
00h: N/A; 0Fh: 32KB; 10h: 64KB
Sector Type 3 erase Opcode
Sector Type 4 Size
51h
52h
53h
15:08
23:16
31:24
D8h
00h
FFh
D8h
00h
FFh
00h: N/A, This sector type doesn't exist
Sector Type 4 erase Opcode
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Table 13. Parameter Table (1): Macronix Flash Parameter Tables
Add (h)
(Byte)
DW Add
(Bit)
Data (h/b)
(Note1)
Data
(h)
Description
Comment
07:00
15:08
00h
36h
00h
36h
Vcc Supply Maximum Voltage
2000h=2.000V2700h=2.700V3600h=3.600V
61h:60h
1650h=1.650V, 1750h=1.750V
2250h=2.250V, 2300h=2.300V
23:16
31:24
50h
26h
50h
26h
Vcc Supply Minimum Voltage
63h:62h
2350h=2.350V,
2650h=2.650V
2700h=2.700V
H/W Reset# pin
H/W Hold# pin
0=not support 1=support
0=not support 1=support
0=not support 1=support
0=not support 1=support
00
01
02
03
0b
1b
Deep Power Down Mode
S/W Reset
1b
1b
1001
1001b
(99h)
1b
Reset Enable (66h) should be issued before
Reset Opcode
65h:64h
F99Eh
S/W Reset Opcode
11:04
Program Suspend/Resume
Erase Suspend/Resume
Unused
0=not support 1=support
0=not support 1=support
12
13
14
15
1b
1b
Wrap-Around Read mode
0=not support 1=support
1b
Wrap-Around
Opcode
Read
mode
66h
67h
23:16
77h
77h
64h
08h:support
8B
wrap-around
Wrap-Around Read data length
read16h:8B&16B32h:8B&16B&32B64h:8B&
16B&32B&64B
31:24
64h
Individual block lock
Individual block lock bit
(Volatile/Nonvolatile)
0=not support 1=support
00
01
0b
1b
0=Volatile 1=Nonvolatile
1111 1111b
(FFh)
Individual block lock Opcode
09:02
10
Individual block lock Volatile
protect bit default protect status
Secured OTP
CFFEh
0=protect 1=unprotect
1b
6Bh:68h
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
1b
0b
Read Lock
Permanent Lock
Unused
13
0b
15:14
31:16
31:00
11b
FFh
FFh
Unused
FFh
FFh
Unused
6Fh:6Ch
Notes:
1: h/b is hexadecimal or binary.
2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the
only valid Read SFDP instruction modes are: (1-1- 1), (2-2-2), and (4-4-4)
3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system
controller if they are specified. (eg, read performance enhance toggling bits)
5: 4KB=2^0Ch, 32KB=2^0Fh, 64KB=2^10h
6: All unused and undefined area data is blank FFh for SFDP Tables that are defined in Parameter. Identification Header. All other areas beyond defined
SFDP Table are reserved by Macronix.
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11. POWER-ON STATE
The device is at the following states after power-up:
- Standby mode
For further protection on the device, if the VCC does not reach the
VCC minimum level, the correct operation is not guaranteed. The
read, write, erase, and program command should be sent after the
time delay:
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and
power-down stage until the VCC reaches the following levels:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC
minimum and a time delay of tVSL.
Please note that a pull-up resistor on CS# may ensure a safe and
proper power-up/down level.
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable
capacitor close to package pins is recommended. (generally
around 0.1uF)
An internal Power-on Reset (POR) circuit may protect the device
from data corruption and inadvertent data change during power up
state.
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12. ELECTRICAL SPECIFICATIONS
12.1. Absolute Maximum Ratings
Rating
Value
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
Industrial grade
-40°C to 85°C
-65°C to 150°C
-0.5V to 4.6V
-0.5V to 4.6V
-0.5V to 4.6V
VCC to Ground Potential
NOTICE:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only and functional
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see the figures below.
12.2. Capacitance TA = 25°C, f = 1.0 MHz
Symbol
CIN
Parameter
Min.
Typ.
Max.
Unit
pF
Conditions
VIN = 0V
Input Capacitance
Output Capacitance
-
-
-
-
6
8
COUT
pF
VOUT = 0V
Figure 41. Input Test Waveforms and Measurement Level
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Figure 42.Output Loading
Table 14. DC Characteristics
Temperature = -40°C to 85°C for Industrial grade
Symbol
Parameter
Notes
Min.
Typ.
Max.
Units
Test Conditions
VCC = VCC Max,
VIN = VCC or GND
VCC = VCC Max,
VOUT = VCC or GND
VIN = VCC or GND,
CS# = VCC
ILI
Input Load Current
1
± 2
uA
ILO
Output Leakage Current
VCC Standby Current
1
1
± 2
50
20
uA
uA
uA
ISB1
ISB2
10
3
VIN = VCC or GND,
CS# = VCC
Deep Power-down Current
f=50MHz,
2.5
10
5
mA
mA
SCLK=0.1VCC/0.9VCC,
SO=Open
ICC1
VCC Read
1
1
fQ=133MHz
(4
x
I/O
17
read)SCLK=0.1VCC/0.9VCC,
SO=Open
Program in Progress,
CS# = VCC
ICC2
ICC3
ICC4
ICC5
VCC Program Current (PP)
10
10
10
10
15
15
15
15
mA
mA
mA
mA
VCC Write Status Register
(WRSR) Current
Program status register in
progress, CS#=VCC
Erase in Progress,
CS#=VCC
VCC Sector Erase Current
(SE)
1
1
VCC Chip Erase Current
(CE)
Erase in Progress,
CS#=VCC
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-0.5
0.8
VCC+0.4
0.4
V
V
V
V
VIH
VOL
0.7VCC
IOL = 1.6mA
IOH = -100uA
VOH
VCC-0.2
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
3. The value guaranteed by characterization, not 100% tested in production.
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Table 15. AC Characteristics
Temperature = -40°C to 85°C for Industrial grade
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for the following instructions:
FAST_READ, PP, SE, BE32K, BE, CE, RES,
WREN, WRDI, RDID, RDSR, WRSR
fSCLK
fC
D.C.
133
MHz
fRSCLK
fR
fT
Clock Frequency for READ instructions
50
MHz
MHz
Clock
Frequency
for
2READ/DREAD
133
instructions
fTSCLK
Clock
Frequency
for
4READ/QREAD
fQ
133
133
MHz
MHz
ns
instructions
f4PP
Clock Frequency for 4PP (Quad page program)
Clock High Time
Others (fSCLK)
45% x
tCH(1)
tCLH
tCLL
(1/fSCLK)
Normal Read (fRSCLK)
Others (fSCLK)
9
ns
Clock Low Time
45% x
ns
tCL(1)
(1/fSCLK)
Normal Read (fRSCLK)
9
0.1
0.1
4
ns
V/ns
V/ns
ns
tCLCH (2)
tCHCL (2)
tSLCH
Clock Rise Time (peak to peak)
Clock Fall Time (peak to peak)
tCSS
CS# Active Setup Time (relative to SCLK)
CS# Not Active Hold Time (relative to SCLK)
Data In Setup Time
tCHSL
4
ns
tDVCH
tCHDX
tCHSH
tSHCH
tDSU
tDH
2
ns
Data In Hold Time
3
ns
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
4
ns
4
ns
CS# Deselect Time
Read
15
50
ns
tSHSL
tCSH
tDIS
Write/Erase/Program
2.65V-3.6V
3.0V-3.6V
ns
Output Disable Time
10
8
ns
tSHQZ (2)
ns
tHLCH
tCHHH
tHHCH
tCHHL
HOLD# Setup Time (relative to SCLK)
HOLD# Hold Time (relative to SCLK)
HOLD Setup Time (relative to SCLK)
HOLD Hold Time (relative to SCLK)
5
5
5
5
ns
ns
ns
ns
HOLD to Output Low-Z
Loading=30pF
2.65V-3.6V
3.0V-3.6V
2.65V-3.6V
3.0V-3.6V
10
8
ns
tHHQX
tHLQZ
tLZ
ns
HOLD# to Output High-Z
Loading=30pF
10
8
ns
tHZ
ns
Clock Low to Output Loading: 15pF
6
ns
tCLQV
tV
Valid
Loading: 30pF
8
ns
VCC=2.65V~3.6V
tCLQX
tHO
Output Hold Time
1
ns
ns
ns
us
us
tWHSL (3)
tSHWL (3)
tESL(4)
Write Protect Setup Time
Write Protect Hold Time
Erase Suspend Latency
Program Suspend Latency
20
100
20
20
tPSL(4)
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Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
Latency between Program Resume and next
Suspend
tPRS (5)
0.3
100
us
Latency between Erase Resume and next
Suspend
tERS (6)
0.3
200
us
tRCR
tRCP
tRCE
tDP
Recovery Time from Read
20
20
12
us
us
ms
us
Recovery Time from Program
Recovery Time from Erase
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic
Signature Read
10
tRES1
tRES2
100
us
us
CS# High to Standby Mode with Electronic
Signature Read
100
tW
Write Status Register Cycle Time
Byte-Program
40
50
1.2
200
0.6
1
ms
us
ms
ms
s
tBP
10
0.33
25
tPP
Page Program Cycle Time
tSE
Sector Erase Cycle Time (4KB)
Block Erase Cycle Time (32KB)
Block Erase Cycle Time (64KB)
Chip Erase Cycle Time
tBE32K
tBE
0.14
0.25
10
s
tCE
30
1
s
tWSR
Write Security Register Time
ms
Notes:
1. tCH + tCL must be greater than or equal to 1/ fC.
2. The value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
4. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0".
5. For tPRS, minimum timing must be observed before issuing the next program suspend command. However, a period equal to or longer than the typical
timing is required in order for the program operation to make progress.
6. For tERS, minimum timing must be observed before issuing the next erase suspend command. However, a period equal to or longer than the typical timing is
required in order for the erase operation to make progress.
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13. TIMING ANALYSIS
Figure 43. Serial Input Timing
Figure 44.Output Timing
Figure 45.Hold Timing
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Figure 46.WP# Setup Timing and Hold Timing during WRSR when SRWD=1
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14. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in "Figure 47. AC Timing at Device Power-Up" and "Figure 48. Power-Down Sequence" are for the supply voltages and
the control signals at device power-up and power-down. If the timing in the figures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be selected. The CS# can be
driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 47. AC Timing at Device Power-Up
Symbol
Parameter
VCC Rise Time
Notes
Min.
Max.
Unit
tVR
1
20
500000
us/V
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "Table 15. AC Characteristics".
Figure 48. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
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Figure 49.Power-up Timing
Figure 50.Power Up/Down and Voltage Drop
For Power-down to Power-up operation, the VCC of flash device must below VPWD for at least tPWD timing. Please check the table below
for more detail.
Table 16. Power-Up/Down Voltage and Timing
Symbol
tVSL
Parameter
Min.
800
1.5
Max.
Unit
us
V
VCC(min.) to device operation
Write Inhibit Voltage
VWI
2.5
0.9
VPWD
tPWD
tVR
VCC voltage needed to below VPWD for ensuring initialization will occur
The minimum duration for ensuring initialization will occur
VCC Rise Time
V
300
20
us
us/V
V
500000
3.6
VCC
VCC Power Supply
2.65
Note: These parameters are characterized only.
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14.1. Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all
Status Register bits are 0).
15. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ. (1)
Max. (2)
40
Unit
ms
ms
s
Write Status Register Cycle Time
Sector Erase Time (4KB)
Block Erase Time (64KB)
Block Erase Time (32KB)
Chip Erase Time
25
0.25
0.14
10
200
1
0.6
30
s
s
Byte Program Time (via page program command)
Page Program Time
10
50
us
0.33
100,000
1.2
ms
cycles
Erase/Program Cycle
Notes:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checkerboard pattern.
2. Under worst conditions of 85°C and 2.65V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.
16. Data Retention
Parameter
Condition
Min.
Max.
UNIT
years
Data retention
55˚C
20
-
17. LATCH-UP CHARACTERISTICS
Min.
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
Current
-1.0V
-1.0V
2 VCCmax
VCC + 1.0V
+100mA
-100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
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18. PACKAGE/PAD LOCATIONS
18.1. Ordering Information
Product Number
Package Type
SOP 8L 200mil-Halogen Free Package
GPR25L3203F-QS13x
Note: x = 1 - 9, serial number.
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18.2. Package Information
18.2.1. Package Outline for SOP 8L (200MIL)
18.2.1.1. Dimensions (Inch dimensions are derived from the original mm dimensions)
Reference
DWG. NO.
Revision
Issue Date
JEDEC
EIAJ
6110-1406
5
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19. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms
of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication
or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY
OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the
specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
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20. REVISION HISTORY
Date
Revision
Description
Page
Jul. 09, 2015
1.0
Original
47
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相关型号：
GPR25V0805F-QS13x
2.3V-3.6V, 8M-Bit [x 1/x 2/x 4] CMOS MXSMIO (Serial Multi I/O) Flash Memory
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