GPY0050A1-HG08x [GENERALPLUS]
12--bit ADC with Microphone Preamplifier;
| 型号： | GPY0050A1-HG08x |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 12--bit ADC with Microphone Preamplifier |
| 文件： | 总21页 (文件大小：953K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPY0050A1
12-bit ADC with Microphone
Preamplifier
Sep. 25, 2017
Version 1.1
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPY0050A1
Table of Contents
PAGE
1. GENERAL DESCRIPTION......................................................................................................................................................................3
2. FEATURES .............................................................................................................................................................................................3
3. BLOCK DIAGRAM..................................................................................................................................................................................3
4. SIGNAL DESCRIPTIONS .......................................................................................................................................................................4
4.1. PAD ASSIGNMENT.............................................................................................................................................................................5
4.2. PACKAGE PIN ASSIGNMENT ................................................................................................................................................................5
5. FUNCTIONAL DECRIPTIONS ................................................................................................................................................................6
5.1. SPI SERIAL INTERFACE......................................................................................................................................................................6
5.1.1. SPI Command Mode Setting.................................................................................................................................................6
5.1.2. Command Mode Address Format..........................................................................................................................................6
5.1.3. Command Mode Data Format...............................................................................................................................................7
5.1.4. SPI Timing ............................................................................................................................................................................8
5.2. ANALOG-TO-DIGITAL CONVERTER.....................................................................................................................................................13
5.3. ADC S/H TIME................................................................................................................................................................................14
5.4. MICROPHONE PREAMPLIFIER............................................................................................................................................................15
6. ELECTRICAL SPECIFICATIONS..........................................................................................................................................................16
6.1. ABSOLUTE MAXIMUM RATINGS .........................................................................................................................................................16
6.2. DC CHARACTERISTICS (VDD=5.0V, TA = 25C) ..................................................................................................................................16
7. APPLICATION CIRCUIT .......................................................................................................................................................................17
8. PACKAGE/PAD LOCATIONS ...............................................................................................................................................................18
8.1. ORDERING INFORMATION .................................................................................................................................................................18
8.2. PACKAGE INFORMATION ...................................................................................................................................................................18
8.2.1. SSOP 20.............................................................................................................................................................................18
8.2.2. SSOP 16.............................................................................................................................................................................19
9. DISCLAIMER........................................................................................................................................................................................20
10.REVISION HISTORY.............................................................................................................................................................................21
© Generalplus Technology Inc.
Proprietary & Confidential
2
Sep 25, 2017
Version: 1.1
GPY0050A1
12-BITS ADC WITH MICROPHONE PREAMPLIFIER
1. GENERAL DESCRIPTION
2. FEATURES
The GPY0050A1 is a 12-bit sampling Analog-to-Digital Converter
Wide operating range: 2.2V – 5.5V
(ADC) with
a
synchronous serial interface and differential
SPI Serial Interface
One 12-bit ADC (12-bit SAR ADC)
ADC Sampling Up to 125KHz
microphone input preamplifier. The device contains an on-chip
control register allowing control of ADC and microphone amplifier
via the SPI interface.
One Microphone Preamplifier with AGC
3. BLOCK DIAGRAM
VDD
4
IN[3:0]
S/H
4
Comparator
IN[7:4]
DCLK
CSN
VDD
SAR
SPI
ENMICB
VDD/2
12 bit DAC
Control
Interface
Logic
VMIC
VCM
DIN
DOUT
R2 60k
MICP
MICN
R1 1.5k
MIC
PreAmp
AGC
OPA
Control
VCM
MICOUT
(IN7)
OPI
OPO
(IN4)
AGC VSS
(IN6)
Note: When user needs 8 channels ADC, we recommend replacing GPY0050A1 with GPY0050B.
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Version: 1.1
GPY0050A1
4. SIGNAL DESCRIPTIONS
GPY0050A1-HG08x (SSOP-20)
Mnemonic
PIN No.
Type
Description
Electrical Characteristics
Serial data output. Data is shifted out on the falling edge of
DCLK. This output is high impedance when CSN is high.
Serial data input. If CSN is low, data is latched on the rising
edge of DCLK.
DOUT
1
O
-
DIN
2
I
-
DCLK
3
4
I
Data Clock input
-
CSN
I
Chip select. Active Low
-
VDD / VDDA
IN0
5 / 6
7
P
Power VDD
VDD=2.2V ~ 5.5V
I
ADC input channel 0
-
IN1
8
I
ADC input channel 1
-
IN2
9
I
ADC input channel 2
-
IN3
10
11
12
13
14
15
16
17
18
19 / 20
I
ADC input channel 3
-
OPO / IN4
OPI
O / I
OPA Output. / ADC input channel 4
OPA inverting input.
-
I
O / I
O / I
I
-
AGC / IN6
MICOUT / IN7
MICN
AGC control pin. / ADC input channel 6
Microphone preamplifier output. / ADC input channel 7
Inverting input of the differential microphone signal
Non-inverting input of the differential microphone signal
VDD/2. MIC Preamplifier signal ground
Power Switch for Microphone bias
Power Ground
-
-
-
MICP
I
-
VCM
O
VDD/2
VMIC
O
-
-
VSSA / VSS
P
GPY0050A1-HG01x (SSOP-16)
Mnemonic
PIN No.
Type
Description
Electrical Characteristics
Serial data output. Data is shifted out on the falling edge of
DCLK. This output is high impedance, when CSN is high.
Serial data input t. If CSN is low, data is latched on the rising
edge of DCLK.
DOUT
1
O
-
DIN
2
I
-
DCLK
CSN
3
4
I
Data Clock input
-
I
Chip select. Active Low
-
VDD
5
P
Power VDD
VDD=2.2V ~ 5.5V
IN0
6
I
ADC input channel 0
-
IN1
7
I
ADC input channel 1
-
IN2
-
I
ADC input channel 2
-
IN3
-
I
ADC input channel 3
-
OPO / IN4
OPI
8
O / I
OPA Output. / ADC input channel 4
OPA inverting input.
-
9
I
O / I
O / I
I
-
AGC / IN6
MICOUT / IN7
MICN
MICP
VCM
10
11
12
13
14
15
16
AGC control pin. / ADC input channel 6
Microphone preamplifier output. / ADC input channel 7
Inverting input of the differential microphone signal
Non-inverting input of the differential microphone signal
VDD/2. MIC Preamplifier signal ground
Power Switch for Microphone bias
Power Ground
-
-
-
I
-
O
VDD/2
VMIC
VSS
O
-
-
P
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GPY0050A1
4.1. PAD Assignment
3
2
1
18
18
17
CSN
4
5
VCM
16
15
VDD
MICP
MICN
VDDA
IN0
5
6
14
GFG507
MICOUT / IN7
13
7
8
9
10
11
12
4.2. Package Pin Assignment
GPY0050A1-HG08x
GPY0050A1-HG01x
1
2
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DOUT
DIN
VSS
DOUT
DIN
VSS
VSSA
VMIC
VCM
MICP
MICN
VMIC
3
DCLK
CSN
VDD
VDDA
IN0
DCLK
CSN
VDD
IN0
VCM
4
MICP
5
MICN
6
MICOUT / IN7
AGC / IN6
OPI
7
MICOUT / IN7
AGC / IN6
OPI / IN5
IN1
8
IN1
OPO / IN4
9
IN2
10
SSOP-16 150mil
IN3
OPO / IN4
SSOP-20 150mil
Note: When user needs 8 channels ADC, we recommend replacing GPY0050A1 with GPY0050B.
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Version: 1.1
GPY0050A1
5. FUNCTIONAL DECRIPTIONS
5.1. SPI Serial Interface
The GPY0050A1 supports SPI Mode 0 and Mode 3 waveform.
When CSN is low, the DIN is latched on the rising of DCLK and
DOUT is shifted out on the falling edge of DCLK. If CSN is high,
it will disable SPI interface, set DOUT pin in high impedance state
and maintain the register data. When the GPY0050A1 is power
on, the power on reset (POR) will set all of register to default
value.
Shift-in
Shift-out
CSN
DCLK
(SPI Mode 0)
DCLK
(SPI Mode 3)
The first command bit, the ‘S’ bit, must always be high and
indicate the start of command input. The second bit, ‘R/W’ bit,
controls Read or Write register. The next two bits (CMM_ADDR)
select register address. The last 4 bits (CMD_DATA) of data will
be written to register.
MSB
DIN
MSB
DOUT
High Impendence
5.1.1. SPI Command Mode Setting
Bit
7(MSB)
6
5
4
3
2
1
0(LSB)
Function
S
R/W
CMD_ADDR
CMD_DATA
Bit
Function
Type
Description
Condition
7
6
S
W
Start Bit. Control byte starts with first High bit on DIN.
R/W
R/W
Read / Write signal.
0 = write
1 = read
4-5
0-3
CMD_ADDR
CMD_DATA
R/W
R/W
Command Address
00 ADC_CHSEL
01 EN_CTRL
10 Test Mode
11 Test Mode
Command Data
5.1.2. Command Mode Address Format
CMD_ADDR
Function
ADC_CHSEL
EN_CTRL
Type
Description
00
01
10
R/W ADC channel selection signals
R/W ADC / MIC enable controlling signals.
R/W Test mode
Test Mode
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GPY0050A1
5.1.3. Command Mode Data Format
CMD_ADDR = 00：ADC_CHSEL
CMD_DATA
Function
Description
Conditions
111 = IN7
110 = IN6
101 = IN5 - Not available
100 = IN4
[3:1]
ADC_CHSEL
ADC channel select signals.
011 = IN3
010 = IN2
001 = IN1
000 = IN0 (Default)
1 = Reset
[0]
SFT_RST
Software reset
0 = Active (Default)
Note: When microphone preamplifier enable (EN_MIC=1), ADC_CHSEL cannot be set IN5~IN7 channel.
CMD_ADDR = 01: EN_CTRL
CMD_DATA
Function
Description
Conditions
1 = Enable
[3]
EN_ADBIAS
ADC and ADC bias enable signal.
0 = Disable (Default)
1 = 10-bit mode
0 = 12-bit mode (Default)
1 = Enable
[2]
[1]
[0]
MOD_ADC
EN_AGC
EN _MIC
ADC bit mode select signal.
Microphone AGC Control
Microphone enable signal.
0 = Disable (Default)
1 = Enable
0 = Disable (Default)
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GPY0050A1
5.1.4. SPI Timing
CSN
1
8
1
8
1
8
1
8
1
DCLK
Command
Hi Byte
Low Byte
Hi Byte
Low Byte
DIN
S W 0 1
1 0 0 0
S W 0 0
0 0 1 0
Enable ADC
Select IN1
(MSB)
11 10 9
(LSB)
DOUT
8 7 6 5 4 3 2 1 0
IN1 ADC Data
ADC
MUX
ADC Select IN0
ADC Select IN1
ADC
S/H
Sampling Time = 3*DCLKs
Figure 1. SPI Model 0 – ADC 12 bit Conversion Timing
CSN
1
8
1
8
1
8
1
8
1
DCLK
Command
Hi Byte
Low Byte
Hi Byte
Low Byte
DIN
S W 0 1
1 0 0 0
S W 0 0
0 0 1 0
Enable ADC
Select IN1
(MSB)
11 10 9
(LSB)
DOUT
8 7 6 5 4 3 2 1 0
IN1 ADC Data
ADC
MUX
ADC Select IN0
ADC Select IN1
ADC
S/H
Sampling Time = 3*DCLKs
Figure 2. SPI Model 3 – ADC 12-bit Conversion Timing
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GPY0050A1
CSN
1
8
1
8
1
8
1
8
1
DCLK
Command
Hi Byte
Low Byte
Hi Byte
Low Byte
DIN
S W 0 1
1 1 0 0
S W 0 0
0 0 1 0
Enable ADC
Select IN1
(MSB)
9
(LSB)
DOUT
8 7 6 5 4 3 2 1 0
IN1 ADC Data
ADC
MUX
ADC Select IN0
ADC Select IN1
ADC
S/H
Sampling Time = 3*DCLKs
Figure 3. SPI Model 0 – ADC 10-bit Conversion Timing
CSN
1
8
1
8
1
8
1
8
1
DCLK
Command
Hi Byte
Low Byte
Hi Byte
Low Byte
DIN
S W 0 1
1 1 0 0
S W 0 0
0 0 1 0
Enable ADC
Select IN1
(MSB)
9
(LSB)
0
DOUT
8 7 6 5 4 3 2 1
IN1 ADC Data
ADC
MUX
ADC Select IN0
ADC Select IN1
ADC
S/H
Sampling Time = 3*DCLKs
Figure 4. SPI Model 3 – ADC 10-bit Conversion Timing
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GPY0050A1
CSN = Low
1
8
1
8
1
8
1
8
1
DCLK
Hi Byte
Low Byte
Hi Byte
Low Byte
Hi Byte
DIN
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
S W 0 0
0 0 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Select IN1
DOUT 11 10 9
8
7
6
5
4
3
2
1
0
11 10 9
8
7
6
5
4
3
2
1
0
11 9 8 7 6
IN0 ADC Data
IN0 ADC Data
IN1 ADC Data
ADC MUX
ADC MUX Select IN0
ADC MUX Select IN1
ADC S/H
Sampling Time = 3*DCLKs
Figure 5. Channel switch during continuous ADC 12-bit conversion.
CSN = Low
1
8
1
8
1
8
1
8
1
DCLK
Hi Byte
Low Byte
Hi Byte
Low Byte
Hi Byte
DIN
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
S W 0 0
0 0 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Select IN1
DOUT
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9 8 7 6 5
IN0 ADC Data
IN0 ADC Data
IN1 ADC Data
ADC MUX Select IN0
ADC MUX Select IN1
ADC MUX
ADC S/H
Sampling Time = 3*DCLKs
Figure 6. Channel switch during continuous ADC 10-bit conversion.
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GPY0050A1
CSN
1
8
1
8
1
8
1
8
DCLK
Command
(Dummy)
Command
(Dummy)
Hi Byte
Low Byte
DIN
S
R
0 0 0 0 0 0
S W 0 0
0 0 1 0
0 0 0 0 0 0 0 0
S
R
0 0 0 0 0 0
Select IN1
DOUT
11 10 9
8 7 6 5 4 3 2 1 0
IN0 ADC Data
ADC MUX
ADC S/H
ADC MUX Select IN0
ADC MUX Select IN1
Figure 7. Channel switch during discontinuous ADC 12-bit conversion.
CSN
1
8
1
8
1
8
1
8
DCLK
Command
(Dummy)
Command
(Dummy)
Hi Byte
Low Byte
DIN
S
R
0 0 0 0 0 0
S W 0 0
0 0 1 0
0 0 0 0 0 0 0 0
S
R
0 0 0 0 0 0
Select IN1
DOUT
9
8
7
6
5
4
3
2
1
0
IN0 ADC Data
ADC MUX
ADC S/H
ADC MUX Select IN0
ADC MUX Select IN1
Figure 8. Channel switch during discontinuous ADC 10-bit conversion.
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GPY0050A1
CSN = Low
1
8
1
8
1
8
1
8
1
DCLK
Hi Byte
Low Byte
Hi Byte
Low Byte
Hi Byte
DIN
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
S W 0 0
0 0 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Select IN1
DOUT
9
8
7
6
5
4
3
2
1
0
9 8 7 6 5 4 3 2
IN1 ADC Data
IN1 ADC Data
Software
Reset
EN_ADBIAS
MOD_ADC
ADC MUX
ADC S/H
ADC MUX Select IN1
ADC MUX Select IN0
Figure 9. Software Reset Trigger.
CSN
DCLK
DIN
1
8
1
8
1
8
S
R
0 0
X X X X
S
R
0 1
X X X X
S
R
0 1
X X X X
DOUT
3
2
1
0
3
2
1
0
3 2 1 0
Register
ADC_CHSEL
Register
EN_CTRL
Register
Test_Mode
X: Don’t Care
Figure 11. Control registers read-back.
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GPY0050A1
5.2. Analog-to-Digital Converter
GPY0050A1 ADC is a 12-bit Successive Approximation Register
(SAR) ADC. The ADC provides 12-bit / 10-bit conversion mode
operation and 8 analog input channels (see Figure 12). The
converter digitizes the input signal from 0V to full-scale voltage
(see Figure 13). The internal applied voltage reference value
FS = Full Scale Voltage = VDD
1LSB=VDD / ( 212 – 1 ) = VDD / 4095 12bit Mode
1LSB=VDD / ( 210 – 1 ) = VDD / 1023 10bit Mode
11…111
11…110
11…101
11…100
1LSB
determines the full-scale input voltage range.
reference of the GPY0050A1 is fixed to VDD
The voltage
.
User can operate the ADC in continuing or discontinuing
conversion mode by CSN pin. In continuing conversion mode,
CSN pin is always kept low.
The GPY0050A1 requires
00…011
00…010
00…001
00…000
16-DCLKs per conversion (see Figure 5 & 6).
Continuous Mode Sampling Rate = fDCLK / 16
In discontinuing conversion mode, the ADC sampling and holding
signal (ADC_S/H) is controlled by CSN pin. The ADC will hold
analog value on CSN falling edge, and need 24-DCLKs to
complete conversion (see Figure 7 & 8). In discontinuing
conversion mode, user can easily control sampling and holding
time by CSN pin.
0V
VDD (FS)
Input voltage
Figure 13. Ideal Input Voltage and Output Codes
The ADC_CHSEL register is used to select ADC input channel
(IN0 ~ IN7). The IN5 ~ IN7 pins are shared with microphone
preamplifier block. Therefore, the MUX cannot be set to IN5 ~
IN7 channel when microphone preamplifier is enabled. When
user needs
8
channels ADC, we recommend replacing
GPY0050A1 with GPY0050B.
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
MUX
S/H
Comp
SAR
Control
Logic
12-bit
DAC
Figure 12. ADC Function Block Diagram
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GPY0050A1
5.3. ADC S/H Time
Using the input equivalent circuit in Figure 14, the capacitance
The Sample and Hold error must be less than LSB/2.
charging voltage is given by:
tc
1LSB = VDD / (2N -1)
VIN VS (1 eRt C
)
IN
LSB/2 ≈ VDD / 2N+1 > Error x VS.MAX
where
Rt = RS + RIN
N = 10 ADC 10 bits Mode
tc = ADC S/H time
N = 12 ADC 12 bits Mode
Error: Refer Table 1 to find the minimum time constant to meet the
above conditions
Input Signal
GPY0050A1
VIN
Find minimal S/H Time
≥ M x (Rt x CIN)
RS
INx
RIN
VS
VS: Input Signal
RS: Equivalent impedance of Input Signal
Example: VDD=5V, VS.MAX=5V, RS=10kΩ, RIN=200Ω & CIN=15pF,
CIN
RIN: S/H Switch-On Resistance (200Ω)
ADC 12bits Mode.
CIN: S/H Capacitance (15pF)
VIN: The voltage across Capacitor
Select 10 time constants,
LSB/2 ≈ VDD / 2N+1 = 5 / 213 = 0.61mV
Figure 14. ADC input equivalent circuit
Error x VS.MAX = 0.00167% x 5 = 0.23mV < LSB / 2
Then we can show in the following table the percentage voltage
value for the capacitor in a RC charging circuit for a given time
constant.
The minimal S/H time must be greater than 10 time constants.
10 time RC constants = Rt xCIN = 10 x (10k + 200) x 15p = 1.53us
M x (Rt x CIN)
VIN / VS
Error : ( 1-VIN / VS )
Time Constant
When the ADC works in continues mode, sampling time =
3*(1/DCLK) must be greater than or equal to 1.53us.
1 time constant
3 time constants
5 time constants
7 time constants
9 time constants
10 time constants
11 time constants
63.212%
95.021%
99.326%
99.909%
99.988%
99.995%
99.998%
36.78794%
4.97871%
0.67379%
0.09119%
0.01234%
0.00454%
0.00167%
Find SPI Clock DCLK ≤ 3 / 1.53us = 1.96MHz
Table 1. RC Charging Table
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GPY0050A1
5.4. Microphone Preamplifier
The GPY0050A1 Microphone Preamplifier consists of several
distinct circuits: microphone bias switch (M1), first stage amplifier
(MIC Preamplifier), second stage amplifier (OP-Amplifier) and
AGC control circuitry, shown in Figure 15.
set to maximum value (Gain=15 @ VDD=3.3V).
The second stage amplifier consists of R1, R2 and OPA. The
default gain is (1+R2/R1) = 41. Users can make a series
resistance reduce the gain of second stage amplifier.
When register EN_MIC is set to ‘1’, the internal switch M1 will be
turned on and VMIC pin will be shorted to VDD. In order to
reduce power noise, recommend RC time constant of (RVMIC×CVMIC
Gain of second stage amplifier = 1 + R2 / (R1+ROP1)
)
The AGC Control senses OPO pin output waveform. When “VOPO
> VDD – 0.3” or “VOPO < 0.3”, the AGC will pump CAGC capacitor.
The AGC voltage will rise to reduce gain of first stage amplifier
until “VOPO < VDD – 0.3” or “VOPO > 0.3”. In order to avoid the
noise generated by the AGC Control, recommend capacitance of
the CAGC must be greater than 2.2uF and resistance of the RAGC
must be greater than 470kΩ.
must be greater than 8ms and resistance of the RVMIC must be less
than 2kΩ.
The first stage microphone amplifier (MIC Preamplifier) is
difference input preamplifier. The gain can be varied by the AGC.
When AGC pin voltage rises, the MIC preamplifier will reduce the
gain. If AGC function is turned off (EN_AGC=’0’), the gain will be
VDD
VDD
RVMIC
1k
ENMICB
VDD/2
M1
VMIC
VCM
CVMIC
10uF
RMIC1 CVCM
3k
1uF
CMICP
0.22uF
MICP
MICN
R2 60k
R1 1.5k
MIC
PreAmp
MIC
AGC
OPA
Control
CMICN
0.22uF
RMIC2
3k
VCM
MICOUT
OPO
OPI
AGC
COP1
VSS
0.22uF
ROP1
3k
COP2
4.7nF
CAGC
4.7uF
RAGC
470k
Figure 15. Microphone Preamplifier Block Diagram and Application Circuit
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Sep 25, 2017
Version: 1.1
GPY0050A1
6. ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics
Symbol
Ratings
DC Supply Voltage
V+
VIN
TA
< 7.0V
Input Voltage Range
-0.5V to V+ + 0.5V
0℃ to + 60℃
Operating free-air Temperature Range
Storage Temperature
-50℃ to + 150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to the device. For normal operational conditions,
see AC/DC Electrical Characteristics.
6.2. DC Characteristics (VDD=5.0V, TA = 25C)
Item
Operation Voltage
Test Conditions
Symbol
VDD
Min.
Typ.
Max.
5.5
1.0
3.5
2
Unit
V
2.2
-
Shutdown Current
ISTBY
IDD
-
-
0.1
uA
Operating Current
VDD = 5.0V
2.2
mA
DCLK Frequency
-
-
-
-
-
-
MHz
DCLKs
DCLKs
KHz
bits
ADC Conversion Time
ADC Acquisition Time
ADC Conversion Rate
Resolution of ADC
-
16
3
-
-
DCLK/16
FCONV
125
12
RESO
-
Signal-to-Noise Plus Distortion of
ADC from Line In
SINAD
-
64
-
dB
Effective Number of Bit
Integral Non-Linearity of ADC
Differential Non-Linearity of ADC
No Missing Code
ENOB
INL
-
-
10.5
±1.0
±0.8
12
-
-
bits
LSB
LSB
bits
KΩ
DNL
-
-
-
-
Microphone Input Impedance
Microphone AGC Gain
Microphone Total Harmonic
Distortion
RIN
-
10
-
VIN=15mV~300mV, CAGC=47uF
VIN=20mV, f = 1.0KHz
Gain
6
-
40
dB
THD+N
-
60
-
dB
© Generalplus Technology Inc.
Proprietary & Confidential
16
Sep 25, 2017
Version: 1.1
GPY0050A1
7. APPLICATION CIRCUIT
The demo board circuit of the GPY0050A1 is shown in Figure 16. User can easily evaluate GPY0050A1 performance by the demo board.
In order to reduce power noise from other device, suggest connecting Power and GND Line from power source, adding power filter for the
GPY0050A1 and don’t share power and ground line with other devices. (See Figure 17 & 18)
GPY0050A1
Figure 16. Demo Board Circuit of the GPY0050A1
Power Source
Power Source
MCU
And other
circuit
MCU
And other
circuit
BAT
CPWR
BAT
CPWR
Power Noise Filter
Power Noise Filter
GND
GND
Bead
RFLT
100
GPY0050A1
with
GPY0050A1
with
CFLT
CFLT
100uF
RFLT
100
100uF
application
circuit
application
circuit
Bead
Notice: Connect Power and GND from Power Source
Notice: Connect Power and GND from Power Source
Figure 17. Application Suggestions for Reducing Power Noise
Figure 18. Application Suggestions for reducing power noise
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Proprietary & Confidential
17
Sep 25, 2017
Version: 1.1
GPY0050A1
8. PACKAGE/PAD LOCATIONS
8.1. Ordering Information
Product Number
Package Type
GPY0050A1 - C
Chip form
GPY0050A1 - HG08x
GPY0050A1 - HG01x
GPY0050A1 - EG08x
Green Package - SSOP20 (150mil)
Green Package - SSOP16 (150mil)
Green Package (Tape & Reel) - SSOP20 (150mil)
Green Package (Tape & Reel) - SSOP16 (150mil)
GPY0050A1 - EG01x
Note: Package form number (x = 1 - 9, serial number).
8.2. Package Information
8.2.1. SSOP 20
Dimension in inch
Symbol
Min.
0.053
0.004
-
Typ.
Max.
0.069
0.010
0.059
0.012
0.010
0.344
0.244
0.157
A
A1
A2
b
0.064
0.006
-
0.008
0.007
0.337
0.291
0.150
-
-
C
D
0.341-
0.236
E
E1
e
0.154
0.025 BASIC
0.025
L
0.016
0
0.050
8
L1
θº
0.014 BASIC
-
© Generalplus Technology Inc.
Proprietary & Confidential
18
Sep 25, 2017
Version: 1.1
GPY0050A1
8.2.2. SSOP 16
Dimension in inch
Symbol
Min.
0.053
0.004
0.008
0.008
0.189
0.228
0.150
0.016
Typ.
Max.
0.069
0.010
0.012
0.011
0.197
0.244
0.157
0.050
A
A1
b
-
-
-
b1
D
-
-
E
-
E1
L
-
-
e
0.025 BASIC
-
θº
0
8
© Generalplus Technology Inc.
Proprietary & Confidential
19
Sep 25, 2017
Version: 1.1
GPY0050A1
9. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
Proprietary & Confidential
20
Sep 25, 2017
Version: 1.1
GPY0050A1
10. REVISION HISTORY
Date
Revision #
Description
Page
3
Modify BLOCK DIAGRAN in section 3.
Modify SIGNAL DESCRIPTIONS in section 4.
Modify Package Pin Assignment in section 4.2.
Modify Command Mode Data Format in section 5.1.3.
Add ADC S/H Time in section 5.3.
4
5
Sep. 25, 2017
1.1
7
14
17
17
20
Modify APPLICATION CIRCUIT in section 7.
Modify Order Information in section 8.1.
Original
Nov. 03, 2016
JUL. 11, 2016
1.0
0.1
© Generalplus Technology Inc.
Proprietary & Confidential
21
Sep 25, 2017
Version: 1.1
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