GX4002-INE3 [GENNUM]
Dynamic on-chip power management control;
| 型号： | GX4002-INE3 |
| 厂家： | 
GENNUM CORPORATION |
| 描述： | Dynamic on-chip power management control |
| 文件： | 总74页 (文件大小：3209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace Equalization and Output
De-Emphasis
Key Features
Description
•
•
2 x 2 crosspoint switch architecture
Integrated CDR with 9.95 to 11.3Gb/s and 14.025Gb/s
reference-free operation
The GX4002 is a low-power, high-speed 2 x 2 crosspoint
switch, with robust signal conditioning circuits for driving
and receiving high-speed signals through backplanes.
•
•
•
Automatic rate detect
The device consumes as low as 600mW of power (typical)
with all channels operational. Unused portions of the chip
can be turned off in order to further reduce power
consumption.
Dynamic on-chip power management control
Multiple user-programmable power-down saving
modes
•
•
Independent programmable input trace equalization to
reduce deterministic jitter (ISI)
The signal conditioning features of the GX4002 include
per-input clock and data recovery (CDR), programmable
equalization and per-output programmable de-emphasis.
The input equalizer removes ISI jitter—typically caused by
PCB trace losses—by opening the input data eye in
applications where long PCB traces are used. The
integrated CDR “resets” the jitter budget, effectively
erasing the signal distortion that can occur during
transmission.
Independent programmable output pre-emphasis for
driving long board traces
2
•
•
Digital control through I C interface
Integrated analog-to-digital converter, which provides
access to digital diagnostic information on supply
voltage and die temperature
•
•
•
•
•
Integrated eye monitor and PRBS7 generator/checker
Polarity invert, output mute functions available
Single 3.3V supply (±5%)
Output pre-emphasis capability provides a boost of the
high-frequency content of the output signal, such that the
data eye remains open after passing through a long
interconnect of PCB traces and connectors.
On-chip I/O termination
Low power consumption: 600mW typical
The GX4002 features an integrated analog-to-digital
converter, which, through the serial interface, provides
digital diagnostic information about supply voltage and die
temperature.
Low power option for 4.25 & 8.5Gb/s operation:
415mW typical
•
•
•
5mm x 5mm 32-pin QFN package
-40°C to +100°C case operation
RoHS-compliant
The GX4002 device is packaged in a small-outline 5mm ×
5mm 32-pin, high-frequency QFN package with exposed
pad.
Applications
The GX4002 is Pb-free, and the encapsulation compound
does not contain halogenated flame retardant. This
component and all homogeneous sub components are
RoHS-compliant.
•
•
•
•
Enterprise and carrier applications
10GbE, Fibre Channel and InfiniBand networks
Redundancy switching
Retimer for 10Gb/s and 14Gb/s backplane and
linecards
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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I2C
Temp Sensor
Supply Sensor
Digital Core
CDR with
Eye Monitor
Trace
EQ
SDI0/SDI0
Ch0
Driver
SDO0/SDO0
2 x 2
PRBS 7
Generator
PRBS 7
Checker
Differential
Cross-point
Switch Matrix
Ch1
Driver
SDO1/SDO1
Trace
EQ
CDR with
Eye Monitor
SDI1/SDI1
Figure A: GX4002 Functional Block Diagram
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
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Revision History
Version
ECR
Date
Changes and / or Modifications
Ability to propagate loss of lock to Ch0FAULT pin
was added.
0
157889
March 2012
Converted document to a Data Sheet. Updates
throughout. Removed typical temperature
monitor accuracy. Removed typical voltage
monitor accuracy. Added AC common-mode
channel characteristics. Added register 101 bits
[5:3] to Table 7-1: Configuration and Status
Register Map.
November
2011
C
157185
Correction to pin 21 and 23 in Table 1-1: Pin
Descriptions.
B
155955
155765
March 2011
A
February 2011
New document.
Contents
Key Features........................................................................................................................................................1
Applications.........................................................................................................................................................1
Description...........................................................................................................................................................1
1. Pin Out...............................................................................................................................................................5
1.1 Pin Assignment ..................................................................................................................................5
1.2 Pin Descriptions ................................................................................................................................6
2. Electrical Characteristics ............................................................................................................................8
2.1 Absolute Maximum Ratings ..........................................................................................................8
2.2 DC Electrical Characteristics ........................................................................................................8
2.2.1 Power Features......................................................................................................................9
2.3 AC Electrical Characteristics ..................................................................................................... 10
2.4 Required Initialization Settings ................................................................................................ 12
3. Detailed Description.................................................................................................................................. 13
3.1 Multirate CDR Functionality ...................................................................................................... 13
3.1.1 Rate Selection and Rate Detection............................................................................... 13
3.1.2 Auto Retimer Bypass ........................................................................................................ 16
3.2 Channel 0 Path (Ch0) .................................................................................................................... 17
3.2.1 Ch0 Equalization................................................................................................................ 17
3.2.2 Ch0 PLL Variable Loop Bandwidth.............................................................................. 18
3.2.3 Channel 0 Output Polarity Invert................................................................................. 18
3.3 Channel 1 Path (Ch1) .................................................................................................................... 19
3.3.1 Integrated Limiting Amplifier ....................................................................................... 19
3.3.2 Ch1 Equalization................................................................................................................ 19
3.3.3 Ch1 PLL Variable Loop Bandwidth.............................................................................. 20
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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3.3.4 Pre-Emphasis Driver with Auto-Mute........................................................................ 21
3.3.5 Channel 1 Output Polarity Invert................................................................................. 22
3.4 Crosspoint ........................................................................................................................................ 23
3.5 Status Indicators ............................................................................................................................ 27
3.5.1 Ch0 Loss Of Signal (LOS) ................................................................................................. 27
3.5.2 Ch1 Loss Of Signal............................................................................................................. 29
3.5.3 Loss Of Lock (LOL)............................................................................................................. 32
3.5.4 Ch0FAULT - Channel 0 Fault......................................................................................... 33
3.6 Test Features ................................................................................................................................... 33
3.6.1 PRBS Generator and Checker........................................................................................ 34
3.6.2 Eye Monitor & Peak Detector......................................................................................... 36
3.7 Digital Diagnostics ........................................................................................................................ 38
3.7.1 Analog to Digital Converter (ADC) .............................................................................. 38
3.8 Power Control Options ................................................................................................................ 48
3.9 Device Reset .................................................................................................................................... 49
3.9.1 Reset State During Power-up......................................................................................... 49
3.9.2 RESET Timing...................................................................................................................... 50
3.9.3 I/O and Register States During and After Reset ...................................................... 51
3.10 Digital Control Interface ........................................................................................................... 51
3.10.1 I2C Host Interface Mode................................................................................................ 51
4. Typical Application Circuit ..................................................................................................................... 53
4.1 Power Supply Filter Recommendations ................................................................................ 53
4.2 Power Supply Domains ............................................................................................................... 54
5. Layout Considerations.............................................................................................................................. 55
6. Input/Output Equivalent Circuits......................................................................................................... 56
7. Package and Ordering Information...................................................................................................... 59
7.1 Package Dimensions ..................................................................................................................... 59
7.2 Recommended PCB Footprint ................................................................................................... 59
7.3 Packaging Data ............................................................................................................................... 60
7.4 Solder Reflow Profile .................................................................................................................... 60
7.5 Marking Diagram ........................................................................................................................... 61
7.6 Ordering Information ................................................................................................................... 61
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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1. Pin Out
1.1 Pin Assignment
32
25
31
26
30
29
28
27
SDO0VCC
SDO0VEE
NC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
Ch0LF
Ch0VCOVEE
Ch0VCOFILT
SDI0
GX4002
32-pin QFN
(top view)
NC
RS1
SDI1
SDI0
SDI1
Ch0VEE
Ch0VCC
Ch1LOS
9
10
11
12
13
14
15
16
Ground Pad
(bottom of package)
Figure 1-1: GX4002 Pin Assignment
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin #
Name
Type
Description
1
2
SDO0VCC
SDO0VEE
NC
Power
Ground
—
Power supply for channel 0 path output.
Ground for channel 0 path output.
No connect.
3, 4
Input Digital LVTTL/LVCMOS-compliant input.
Rate Select Input for the Ch1 Signal Path.
Digital
Input
5
RS1
See Section 3.1 Multirate CDR Functionality for more details.
6, 7
SDI1, SDI1
Input
High-speed input for the channel 1 signal path.
SFP+-compliant active-high digital output. Open-collector Loss-Of-Signal indicator for
the channel 1 signal path. Requires an external pull-up resistor.
Digital
Output
When Ch1LOS is LOW, a valid channel 1 input signal has been detected.
When Ch1LOS is high-impedance, a valid channel 1 input signal has not been detected.
Configurable as LVTTL/LVCMOS-compliant output.
8
Ch1LOS
9
Ch1LF
Ch1VCOVEE
Ch1VCOFILT
Ch1VEE
Passive
Ground
Passive
Ground
Power
Loop filter capacitor connection for the channel 1 signal path.
Ground for the channel 1 signal path VCO.
10
11
12
13
Filter for the channel 1 signal path VCO supply.
Ground for the channel 1 signal path and output.
Power supply for the channel 1 signal path and output.
Ch1VCC
SDO1,
SDO1
14, 15
Output
High-speed differential output for the channel 1 signal path.
Digital active-low LVTTL/LVCMOS-compliant Schmitt-trigger input.
Device reset control pin.
Digital
Input
16
RESET
Includes an internal pull-down resistor to hold the device in a reset state during
power-up, should this pin be externally disconnected.
17
18
Ch0VCC
Ch0VEE
Power
Ground
Input
Power supply for the channel 0 signal path.
Ground for the channel 0 signal path.
19, 20
21
SDI0, SDI0
Ch0VCOFILT
Ch0VCOVEE
Ch0LF
High-speed input for the channel 0 signal path.
Filter for the channel 0 signal path VCO supply.
Ground for the channel 0 signal path VCO.
Loop filter capacitor connection for the Ch0 signal path.
Connect to GND.
Passive
Ground
Passive
Ground
22
23
24
GND
Digital
Input/
Output
Digital active-high serial data signal for the host interface.
Bi-directional, I2C-compliant, open-drain driver/receiver.
25
26
SDA
SCL
Digital
Input
Digital active-high clock input signal for the serial host interface.
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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Table 1-1: Pin Descriptions (Continued)
Pin #
Name
Type
Description
27
28
VREG
Passive
LDO regulator capacitor connection. (1.8V)
DIGVSS
Ground
Ground for low-speed digital I/O and internal logic.
Input Digital LVTTL/LVCMOS-compliant input.
Rate Select Input for the Ch0 Signal Path.
Digital
Input
29
RS0
See Section 3.1 Multirate CDR Functionality for more details.
SDO0,
SDO0
30, 31
Output
High-speed differential output for the channel 0 signal path.
SFP+-compliant active-high digital output. Open-collector Ch0FAULT indicator. Requires
an external pull-up resistor.
When Ch0FAULT is LOW, the channel 0 path output is operating properly.
When Ch0FAULT is high-impedance, the device has detected a fault condition.
Digital
Output
32
Ch0FAULT
The Ch0FAULT is latched, and may be cleared via the host interface or by strobing the
Ch0DSBL pin.
Can be configured as a LVTTL/LVCMOS compatible output.
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Parameter
Value
Supply Voltage
-0.5 to +3.8VDC
Input ESD Voltage
2kV
Storage Temperature Range
-50°C < TA < 125°C
Input Voltage Range (any input pin)
Solder Reflow Temperature
-0.3 to 3.8VDC*
260°C
*NOTE: Stress above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only, and functional operation of the device at
these or any other conditions above those listed in the operational sections of this
specification is not applied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2.2 DC Electrical Characteristics
Table 2-1: DC Electrical Characteristics
VCC = +2.8V to +3.47V, TC = -40°C to 100°C. Typical values are VCC = +3.3V and TA = 25°C, unless otherwise specified.
Specifications assume default setting to end-terminated 50Ω transmission lines, unless otherwise stated. Typical Data Rate = 14.025Gb/s
Note: mApp refers to mA peak-to-peak value.
Parameter
Conditions
Symbol
Min
Typ
Max
Units
Notes
VCC
Supply Voltage
Power
2.8
—
3.3
3.47
800
V
—
600
mW
1, 2
Control Logic Input Specifications
VIL
VIH
IIL
Input Low Voltage
Input High Voltage
0
—
—
0.4
V
V
—
—
—
VCC
2.0
—
VIL = 0V
Input Low Current
Input High Current
-100
—
—
μA
VIH = 3.3V,
VCC = 3.3V
IIH
—
100
0.2
μA
—
Status Indicator Output Specifications
Indicator Output Logic
LOW
I
SINK(max) = 3mA
VOL
—
0.4
V
—
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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Table 2-1: DC Electrical Characteristics (Continued)
VCC = +2.8V to +3.47V, TC = -40°C to 100°C. Typical values are VCC = +3.3V and TA = 25°C, unless otherwise specified.
Specifications assume default setting to end-terminated 50Ω transmission lines, unless otherwise stated. Typical Data Rate = 14.025Gb/s
Note: mApp refers to mA peak-to-peak value.
Parameter
Conditions
Symbol
Min
Typ
Max
Units
Notes
Channel 0 Specifications
Input Termination (SDI0)
Differential
80
—
100
50
120
—
Ω
Ω
—
—
Output Termination (SDO0)
Channel 1 Specifications
Input Termination
(Ch1SDIP/N)
Differential
Differential
80
80
100
100
120
120
Ω
Ω
—
—
Output Termination
(Ch1SDOP/N)
NOTES:
1. Typical Conditions: T = 25°C, V = 3.3V. Maximum Conditions: T = 100°C, V = 3.467V.
2. Each output terminated.
2.2.1 Power Features
Table 2-2: Power Features
Typical
Baseline
Power
(mW)
Typical
Incremental
Power
Feature
Section
Configuration
Description
(mW)
GX4002 Base
600
SDO1 Pre-emphasis = 3dB @ 600mVppd
PRBS7 Generator
—
20
—
3.3.4
3.6.1
Path for PRBS7 generator to
Ch1SDO is on.
—
115
PRBS7 Checker
Diag + ADC
—
—
125
14
PRBS7 checker is on.
3.6.1
3.7
Temperature, Supply Sensor, ADC.
All, Ch0 and Ch1 horizontal and
vertical eye monitors are on.
Eye Monitor + ADC
Ch0 EQ Boost
—
—
—
50
0
3.6.2
3.2.1
—
—
—
GX4002 with Ch0 CDR bypassed and
powered-down
-90mW
GX4002 with Ch1 & Ch0 CDR bypassed and
powered-down
—
-185mW
—
—
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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2.3 AC Electrical Characteristics
Table 2-3: AC Electrical Characteristics
VCC = +2.8V to +3.47V, TC = -40°C to 100°C. Typical values are VCC = +3.3V and TA = 25°C, unless otherwise specified.
Specifications assume default setting to end-terminated 50Ω transmission lines, unless otherwise stated. Typical Data Rate = 14.025Gb/s
Parameter
Conditions
Symbol
Min
Typ
Max
Units
Notes
10G configuration
9.95
—
—
11.3
—
Gb/s
Gb/s
1
1
Data Rate
16GFC configuration
14.025
Channel 0 Specifications
Input Amplitude Range
differential
120
20
—
1
—
—
6
850
100
—
mVppd
mVppd
dB
—
—
6
LOS Threshold Level Setting
Range
Equalization Gain
Jitter Transfer Bandwidth
Setting Range
PRBS31 data
—
0.1
—
23
MHz
UIpp
ms
—
—
—
Total Output Jitter
—
—
0.25
0.5
16G FC mode: loop
filter cap = 100nF
Ch0 CDR Lock Time
Ch0SDO Output Rise/Fall
Time (minimum)
tr, tf
tr, tf
20% - 80%
20% - 80%
—
—
—
20
—
ps
ps
7
8
Ch0SDO Output Rise/Fall
Time (maximum)
40
Channel 1 Specifications
Input Sensitivity
—
—
—
10
—
mVppd
mVppd
—
—
Input Overload
1200
Limiting Amplifier
Equalization
maximum EQ setting
14
—
—
dB
2
Jitter Transfer Bandwidth
Setting Range
1
—
0.1
—
23
0.25
—
MHz
UIpp
ps
—
—
—
Ch1SDO Output Total Jitter
PRBS31 data
TJ
—
20
Ch1SDO Output Rise/Fall
time
tr, tf
20% - 80%
Ch1SDO Output AC
Common Mode Voltage
—
—
—
5
7.5
—
mVrms
mVppd
3
minimum
programmable
setting
—
Ch1LOS De-assert
Threshold Level Setting
Range
maximum
programmable
setting
—
400
—
mVppd
—
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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Table 2-3: AC Electrical Characteristics (Continued)
VCC = +2.8V to +3.47V, TC = -40°C to 100°C. Typical values are VCC = +3.3V and TA = 25°C, unless otherwise specified.
Specifications assume default setting to end-terminated 50Ω transmission lines, unless otherwise stated. Typical Data Rate = 14.025Gb/s
Parameter
Conditions
Symbol
Min
Typ
Max
Units
Notes
1 sigma, IC to IC
over VCC Range
—
—
1.50
+0.5
—
—
mVrms
dB
—
—
Ch1LOS Threshold Level
Variation
over temperature
range -40°C to
+100°C
—
+0.5
—
dB
—
Ch1LOS Threshold Level
Hysteresis Setting Range
electrical
0
3
—
5
6
dB
μs
—
—
4
Ch1LOS Response Time
Ch1 CDR Lock Time
20
0.5
16G FC mode: loop
filter cap = 100nF
—
—
ms
minimum swing
setting
—
—
3
100
850
—
—
—
—
mVppd
mVppd
dB
—
—
5
Differential Output Voltage
Setting Range
maximum swing
setting
Output Pre-emphasis
Setting Range
maximum setting
NOTES:
1. See Table 3-1 for details.
2. At 7GHz.
3. 600mVppd swing.
4. For loop bandwidth = 13MHz (as detailed in Table 3-4).
5. 600mVppd swing.
6. At 7GHz (dielectric loss).
7. Reg89[7:0] = "11001000" = Reg110[7:0]. Reg90[1:0] = "00" = Reg111[7:0]. Reg102[1:0] = "00". Reg118[4:3] = "11" = Reg119[4:3].
Reg80[7:0] = "11101110". Reg81[4:0] = "11100" = Reg103[4:0]. Reg82[4:0] = "11010" = Reg104[4:0].
8. Reg89[7:0] = "11111111" = Reg110[7:0]. Reg90[1:0] = "11" = Reg111[7:0]. Reg102[1:0] = "00". Reg118[4:3] = "00" = Reg119[4:3].
Reg80[7:0] = "01000100". Reg81[4:0] = "01000" = Reg103[4:0]. Reg82[4:0] = "10000" = Reg104[4:0].
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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2.4 Required Initialization Settings
The GX4002 configuration registers must be set as described in Table 2-4 below to meet
the power specification listed in Table 2-1. The AC parametric specifications in Table 2-3
are also based on these settings:
Table 2-4: Required Initialization Settings
Register
Address
(decimal)
New
Value
(binary)
Valid
Range
(decimal)
Register
Name
Bit
Position
Parameter Name
Function
CH1_REG17
CH1_REG18
CH0_REG15
CH0_REG16
64
65
45
46
CH1PWR1
CH1PWR2
CH0PWR1
CH0PWR2
4:0
6:5
4:0
4:3
10101
10
0-31
0-3
Channel 1 power control
Channel 1 power control
Channel 0 power control
Channel 0 power control
10101
10
0-31
0-3
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Equalization and Output De-Emphasis
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3. Detailed Description
3.1 Multirate CDR Functionality
There are two data rate ranges available for selection, so that a single part can be used
for multiple applications. The GX4002 does not require a reference clock. Some example
applications are as follows:
•
•
•
•
•
•
10Gb/s Ethernet (10.3Gb/s)
10Gb/s Ethernet with FEC (11.1Gb/s)
10G Fibre Channel (10.5Gb/s)
10G Fibre Channel with FEC (11.3Gb/s)
Fibre Channel over Ethernet (10.3Gb/s)
16G Fibre Channel (14.025Gb/s)
Table 3-1: Mode Details
Mode
Description
10G
The part will retime in a continuous range from 9.95Gb/s to 11.3Gb/s.
Through the serial interface, the part can be placed in 14G mode. In this
mode, the CDRs will retime at 14.025Gb/s, and is intended for use in 16G Fibre
Channel applications. An automatic rate detect circuit can be used that will
determine if the incoming data rate is a legacy Fibre Channel rate, and will
automatically bypass the CDRs. By using the automatic rate detect feature,
RS0 and RS1 pins are not required. The automatic rate detect feature is not
enabled by default when the device is configured in 14G mode.
14G
3.1.1 Rate Selection and Rate Detection
The GX4002 has three different methods to select the data rate. The rate can be selected
through the use of the RS0/RS1 pins, through the use of registers, or through automatic
detection. The rate selection methods are described in more detail below.
The GX4002 also contains a set of data-dependent registers. This enables parameters
such as rise and fall times to be automatically configured based on the data rate. There
are two profiles, one for low data rates such as 4G or 8G Fibre Channel, and one for high
data rates such as 10GbE or 16G Fibre Channel. The register map (Appendix:
Configuration and Status Register Map) shows which registers contain both low data
rate and high data rate options.
A configuration profile is invoked by one of three methods:
1. Using input pins RS0 and RS1 to invoke a “hard” rate select for either the Ch0 path
or Ch1 path respectively (CH0PLLRATESELVAL is HIGH and/or
CH1PLLRATESELVAL is HIGH).
2. Using host interface commands to invoke a “soft” rate select for either the Ch1 or
Ch0 path, or for both Ch1 and Ch0 paths together using the CH1PLLRATESEL and
CH0PLLRATESEL bits (CH1PLLRATESELVAL is HIGH and/or
CH0PLLRATESELVAL is HIGH).
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Equalization and Output De-Emphasis
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3. Using on-chip automatic rate detection circuitry to detect the new data rate, and to
invoke an internal rate select in either the Ch1 or Ch0 path independently. The
application is defined using the RATEDETFCGBEN bits (CH1PLLRATESELVAL is
LOW and/or CH0PLLRATESELVAL is LOW).
Rate
Select
Valid
Fibre
Rate
Selection
Method
Rate
Select
Registers
Data Rate
Dependent
Register Set Used
RS0/RS1
Pins
Channel/
Ethernet
Register
Operation
Register
The CDRs are placed in bypass
mode. Intended for 2G/4G/8G Fibre
Channel or 1GbE
Not
Applicable
Low Data Rate
Profile
LOW
LOW
Hard Rate
Select
HIGH
Fibre
Channel
The CDR will lock to 14.025Gb/s
High Data Rate
data
Profile
Not
Applicable
HIGH
The CDR will lock to 9.95G to
11.3Gb/s data
High Data Rate
Ethernet
Profile
The CDRs are place in bypass mode.
Intended for 2G/4G/8G Fibre
Channel or 1GbE
Low or
High Z
Not
Applicable
Low Data Rate
Profile
LOW
Soft Rate
Select
HIGH
Fibre
Channel
The CDR will lock to 14.025Gb/s
High Data Rate
data
Profile
Not
Applicable
High
The CDR will lock to 9.95G to
11.3Gb/s data
High Data Rate
Ethernet
Profile
If 14.025Gb/s is
detected: High Data
Rate Profile
If the input data is 14.025Gb/s, the
CDR will lock to it. Otherwise, the
CDRs are automatically bypassed
Fibre
Channel
If 14.025Gb/s is not
detected: Low Data
Rate Profile
Automatic
Rate
Detect
Not
Applicable
Not
Applicable
LOW
If 9.95G to 11.3Gb/s
is detected: High
Data Rate Profile
If the input data is 9.95G to 11.3G,
the CDR will lock to it. Otherwise,
the CDRs are automatically
bypassed
Ethernet
If 9.95G to 11.3Gb/s
is not detected: Low
Data Rate Profile
3.1.1.1 Hard Rate Select (Rate Select Pins)
The RS0 pin controls the rate-dependent profile of the Ch0 path, and the RS1 pin
controls the rate-dependent profile of the Ch1 path. The rate select valid bit,
CH0PLLRATESELVAL (or CH1PLLRATESELVAL), must be HIGH for RS0 (or RS1) to
control the rate.
When the RS0 (or RS1) pin is held LOW, the low-speed rate-dependent registers of the
channel 0 (or channel 1) path are active. When the RS0 (or RS1) pin is held HIGH, the
high-speed rate-dependent profile of the channel 0 (or channel 1) path is active. RS0 is
logically OR'ed with CH0PLLRATESEL, while RS1 is logically OR'ed with
CH1PLLRATESEL. Due to the OR'ing operation, when RS0 and RS1 are used for rate
control, CH0PLLRATESEL and CH1PLLRATESEL must be set LOW.
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3.1.1.2 Soft Rate Select
The CH1PLLRATESEL and CH0PLLRATESEL bits can be programmed to select a rate
profile using the host interface. Setting these parameters and their associated valid
parameters (CH1PLLRATESELVAL and CH0PLLRATESELVAL) override the on-chip
automatic rate detection circuitry. CH0PLLRATESEL is logically OR'd with the RS0 pin,
while CH1PLLRATESEL is logically OR'd with RS1, so RS0 and RS1 must be LOW or
hi-impedance for the PLLRATESEL bits to function properly.
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
Selects data rates:
0 = 1.25 - 8.5G, 1= 10.3G or 14.025G.
14
CH0PLLRATESEL
CH0PLLRATESELVAL
CH1PLLRATESEL
3:3
4:4
3:3
4:4
RW
RW
RW
RW
1
1
1
1
0-1
0-1
0-1
0-1
CH0PLL_REG5
When HIGH, CH0PLLRATESEL or RS0 are
valid, otherwise they are ignored.
14
24
24
Selects data rates:
0 = 1.25 - 8.5G, 1= 10.3G or 14.025G.
CH1PLL_REG5
When HIGH, CH1PLLRATESEL or RS1 are
valid, otherwise they are ignored.
CH1PLLRATESELVAL
The default setting is the high (10Gb/s or 14.025Gb/s) data-rate profile, with the on-chip
automatic rate detection circuitry overridden.
3.1.1.3 Automatic Rate Detection
In addition to the controls outlined in the preceding tables, the auto rate detection
circuitry has the following controls. To enable operation of the auto rate detection
function, CH0RATEDETEN (or CH1RATEDETEN) can be set HIGH.
Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
When HIGH, the Ch0 path rate detector is
reset.
CH0RATEDETRESET
CH0RATEDETEN
0
1
RW
RW
RW
0
1
0-1
0-1
CH0RDET_REG1
CH0RDET_REG2
CH1RDET_REG1
CH1RDET_REG2
67
When HIGH, enables the rate detector.
Rate detector rate period (0.3µs to 13ms,
100µs default).
68
72
73
CH0RATEDETRATEPER
3:0
1000
0-15
When HIGH, the Ch1 path rate detector is
reset.
CH1RATEDETRESET
CH1RATEDETEN
0
1
RW
RW
RW
0
1
0-1
0-1
When HIGH, enables the rate detector
Rate detector rate period (0.3µs to 13ms,
100µs default).
CH1RATEDETRATEPER
3:0
1000
0-15
If CH1RATEDETEN (or CH0RATEDETEN) is LOW, the CH1PLLRATESELVAL (or
CH0PLLRATESELVAL) bit must be HIGH, otherwise the device will be in an undefined
state.
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CH0RATEDETPERIOD(address 68) and CH1RATEDETPERIOD(address 73) control the
frequency at which the automatic rate detection block checks the lock state of the PLL.
The recommended setting for shortest lock time is 1001b.
3.1.1.4 Application-Dependent Rate Select Profiles
The RATEDETFCGBEN and RATEDETFCGBENVAL bits indicate whether the
application traffic is running Fibre Channel, Ethernet or unspecified (for example: the
transceiver may be required to handle either Fibre Channel or Ethernet traffic in mission
mode). The default setting is Fibre Channel traffic.
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
When HIGH, the application is Fibre
Channel. When LOW, the application is
Ethernet.
RATEDETFCGBEN
2:2
3:3
RW
RW
1
1
0-1
0-1
CH0RDET_REG1
67
When HIGH, indicates that RATEDETFCGBEN
is valid. When LOW, it is ignored.
RATEDETFCGBENVAL
Table 3-2: Summary of Rate Selection and Rate Detection Control
CH1PLLRATESELVAL
RATEDETFCGBENVAL
Data Rate
Configuration Profile
CH0PLLRATESELVAL
0
0
1
Undefined
Undefined
Profile selected based on
detected rate
0
1
Auto Rate Detect
Auto Rate Detect
Profile selected by hard or soft
rate select
0
1
Fixed rate determined by the
combination of
RATEDETFCGBEN and rate
select (hard or soft)
Profile selected by hard or soft
rate select
1
3.1.2 Auto Retimer Bypass
The GX4002 supports an automatic rate detect feature for legacy Fibre Channel data
rates when configured in 16G mode. Upon enabling the automatic rate detect feature,
the device constantly monitors incoming data for a valid 14.025Gb/s data rate. If the
input data rate is a legacy Fibre Channel rate, the CDR is automatically bypassed.
While the automatic rate detect feature is enabled, and the CDR is in bypass mode, the
device continues monitoring the incoming data rate. If the data rate changes to
14.025Gb/s, the CDR goes back into retimed mode.
The auto retimer bypass feature also applies to Ethernet mode.
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The following registers enable and configure the automatic rate detect feature:
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
CH0PLLBYPASS
1:1
2:2
RW
RW
0
1
0-1
0-1
When HIGH, forces CDR into bypass mode.
CH0PLL_REG5
14
When HIGH, enables automatic bypass
mode for the Ch0 CDR.
CH0PLLAUTOBYPASSEN
When HIGH, resets the Ch0 path rate
detector.
CH0RATEDETRESET
CH0RATEDETEN
0:0
1:1
0:0
1:1
RW
RW
RW
RW
0
1
0
1
0-1
0-1
0-1
0-1
CH0RDET_REG1
CH1RDET_REG1
67
72
When HIGH, enables the Ch0 path
automatic rate detector.
When HIGH, resets the Ch1 path rate
detector.
CH1RATEDETRESET
CH1RATEDETEN
When HIGH, enables the Ch1 path
automatic rate detector.
The device can be configured to manually bypass each of the Ch1 and Ch0 CDRs
through the CH0PLLBYPASS and CH1PLLBYPASS controls when the automatic bypass
is disabled.
3.2 Channel 0 Path (Ch0)
The channel 0 path is comprised of a trace equalizer, a multi-rate CDR and an output
driver.
Ch0 Disable
Input
Output
EQ
CDR
DR
Figure 3-1: Channel 0 Path
3.2.1 Ch0 Equalization
The channel 0 path input has an equalizer with 6dB gain at 7GHz. The equalizer can be
bypassed through the following register:
Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
When HIGH, applies a fixed CH0 EQ boost of
6dB. 0dB if LOW.
CH0_REG3
33
CH0EQBOOST
0:0
RW
1
0-1
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3.2.2 Ch0 PLL Variable Loop Bandwidth
The loop bandwidth of the channel 0 Phase Locked Loop (PLL) can be varied through the
digital control interface. The loop bandwidths are individually controlled, and can cover
the range of 1MHz to 23MHz through following five-bit registers (recommended settings
are shown):
Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Adjusts LBW positive temperature
coefficient control.
CH0PLL_REG1
CH0PLL_REG2
CH0PLL_REG9
10
CH0PLLLBWCURVT
CH0PLLLBWCURVBE
CH0PLLLBWMULT
4:0
4:0
1:0
RW
RW
RW
10011
01110
10
0-31
0-31
0-3
Adjusts LBW negative temperature
coefficient control.
11
18
LBW multiplier;
00 = 0.67, 10 = 1, 01 = 1.33, 11 = 1.67
The temperature coefficient of the loop bandwidth can be adjusted by weighted
summation of CH0PLLLBWCURVT, which has a positive temperature coefficient and
CH0PLLLBWCURVBE, which has a negative temperature coefficient. The default reset
values of the registers above produce an approximate loop bandwidth of 7MHz.
Table 3-3: Typical Loop Bandwidths for Various Register Settings
Loop
CH0PLLLBWMULT
CH0PLLLBWCURVT
CH0PLLLBWCURVBE
Bandwidth
00
10011
10011
10011
11111
11000
01110
01110
01110
10110
11000
4.6MHz
7.3MHz
9.9MHz
13MHz
10 (default)
01
10
11
22.7MHz
3.2.3 Channel 0 Output Polarity Invert
The channel 0 output polarity can be inverted through the following register:
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
When HIGH, inverts the Ch0 data path
polarity.
CH0PLL_REG5
14
CH0PLLPOLINV
0:0
RW
0
0-1
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3.3 Channel 1 Path (Ch1)
The GX4002 channel 1 path contains a high-sensitivity limiting amplifier with optional
equalization, a multi-rate CDR, and a pre-emphasis driver.
Ch1 LOS
Input
Output
LA
CDR
DR
Chip Control & Status
I2C
Figure 3-2: Channel 1 Path
3.3.1 Integrated Limiting Amplifier
The GX4002 has an integrated Limiting Amplifier (LA), with better than 10mV
sensitivity. Optional equalization is available on the limiting amplifier input.
3.3.2 Ch1 Equalization
The channel 1 input implements an equalizer that provides peaking at 7GHz. This
feature allows for optimal performance with extended reach connections.
The equalizer implements 0dB to 14dB of high-frequency boost in fifteen steps, while
achieving optimal receive sensitivity at any given equalization setting. The equalization
setting is set through the CH1LABOOST control.
Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
CH1_REG1
48
CH1LABOOST
3:0
RW
0000
0-15
0: 0dB to 15: 14dB.
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When the equalization setting is 0dB, the equalization function is bypassed and the
receive sensitivity performance is the same as that of a limiting amplifier.
8dB
14dB
Boost
-6dB
7GHz
Figure 3-3: Channel 1 Equalization
3.3.3 Ch1 PLL Variable Loop Bandwidth
The loop bandwidth of the channel 1 Phase Locked Loops (PLLs) can be varied through
the digital control interface. The loop bandwidths are individually controlled, and can
cover a range of 1MHz to 23MHz through the following 5-bit registers:
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
Adjusts LBW positive temperature
coefficient control.
CH1PLL_REG1
CH1PLL_REG2
CH1PLL_REG9
20
CH1PLLLBWCURVT
CH1PLLLBWCURVBE
CH1PLLLBWMULT
4:0
4:0
7:6
RW
RW
RW
10011
01110
10
0-31
0-31
0-3
Adjusts LBW negative temperature
coefficient control.
21
28
LBW multiplier;
00 = 0.67, 10 = 1, 01 = 1.33, 11 = 1.67
The temperature coefficient of the loop bandwidth can be adjusted by a weighted
summation of CH1PLLLBWCURVT, which has a positive temperature coefficient, and
CH1PLLLBWCURVBE, which has a negative temperature coefficient. The default reset
values of the above registers produce an approximate loop bandwidth of 7MHz.
Table 3-4: Typical Loop Bandwidths for Various Register Settings
Loop
CH1PLLLBWMULT
CH1PLLLBWCURVT
CH1PLLLBWCURVBE
Bandwidth
00
10 (default)
01
10011
10011
10011
01110
01110
01110
4.6MHz
7.3MHz
9.9MHz
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Table 3-4: Typical Loop Bandwidths for Various Register Settings (Continued)
Loop
CH1PLLLBWMULT
CH1PLLLBWCURVT
CH1PLLLBWCURVBE
Bandwidth
10
11
11111
11000
10110
11000
13MHz
22.7MHz
3.3.4 Pre-Emphasis Driver with Auto-Mute
The channel 1 driver is a pre-emphasis driver that can be used to compensate for losses
in the connector and trace between the module and ASIC. The pre-emphasis can
compensate for up to 6dB of loss. The output swing can be set from 100mV to 800mV in
steps of 50mV through the CH1SDOSWING[3:0] register. The pre-emphasis amplitude
can be varied from 0dB to 6dB in eight non-linear steps through CH1SDOPECTRL[4:2].
Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Driver swing.
CH1SDO_REG1
CH1SDO_REG2
77
CH1SDOSWING
CH1SDOPECTRL
3:0
4:2
RW
RW
1010
000
0-15
0-7
0-15: 100-850mVppd, Default = 10: 600mV
Pre-emphasis amplitude.
78
0: 0dB, 7: 6dB for 200mVppd swing.
Ch1 signal after Pre-emphasis
0.6
V1
0.4
0.2
Pre-emphasis
V2
0.0
-V2
-0.2
-0.4
-0.6
-V1
11110000 pattern
268
269
270
271
272
273
274
275
UI
Figure 3-4: Pre-Emphasis Waveform Description
Figure 3-4 above shows the pre-emphasis waveform. Amplitudes V1, V2 and
pre-emphasis in dB are defined as follows:
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V1, V2 and Pre-emphasis are defined as follows:
V1 which represents the “peak”
V2 which represents DC or Steady State
Pre-emphasis [dB] = 20 x log(V1/V2)
The amount of pre-emphasis varies with CH1SDOSWING as shown in Table 3-5:
Table 3-5: Pre-Emphasis vs. Ch1 SDO Swing
CH1SDOSWING
CH1SDOPECTRL
Pre-emphasis
0010 (200mV)
0101 (350mV)
1010 (600mV)
0010 (200mV)
0101 (350mV)
1010 (600mV)
0010 (200mV)
0101 (350mV)
1010 (600mV)
001
001
001
011
011
011
111
111
111
2.3dB
1.8dB
1.0dB
4.7dB
3.8dB
3.1dB
6.2dB
5.5dB
3.4dB
The output can be configured to automatically mute if Ch1 LOS is detected through the
following registers. When muted, the output driver remains powered-up, and the output
common mode is maintained. The output driver can be configured to power-down
when muted by setting the CH1SDOPWRDNONMUTE bit:
Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
When HIGH, mutes driver and maintains
output common mode when not in auto
mute mode.
CH1SDOMUTE
5:5
6:6
7:7
RW
RW
RW
0
1
1
0-1
0-1
0-1
When HIGH, enables muting the driver
upon LOS. LOW disables muting.
CH1SDO_REG3
79
CH1SDOAUTOMUTEEN
CH1SDOPWRDNONMUTE
When HIGH, enables power-down on mute
for output stage. LOW disables
power-down.
3.3.5 Channel 1 Output Polarity Invert
The channel 1 output polarity can be inverted through the following register:
Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
CH1PLL_REG5
24
CH1PLLPOLINV
0:0
RW
0
0-1
When HIGH, inverts the Ch1 data path
polarity.
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3.4 Crosspoint
The GX4002 provides eight different crosspoint paths, as shown in Table 3-6. The blocks
referenced in the different crosspoint paths are shown in Figure 3-5.
EQ
LA
DR
DR
SDI0
SDI1
Ch0 CDR
Ch1 CDR
SDO0
SDO1
Figure 3-5: Crosspoint Block Diagram
Table 3-6: Crosspoint Paths
Mode
Crosspoint Path
Reference
1
2
3
4
5
6
7
8
SDI1 =>LA=>DR=>SDO0
Figure 3-6
Figure 3-6
Figure 3-7
Figure 3-7
Figure 3-8
Figure 3-8
Figure 3-9
Figure 3-9
SDI1 =>LA=>CH1CDR=>DR=>SDO0
SDI1 =>LA=>CH0CDR=>DR=>SDO0
SDI1 =>LA=>CH1CDR=>CH0CDR=>DR=>SDO0
SDI0=>EQ=>DR=>SDO1
SDI0=>EQ=>CH0CDR=>DR=>SDO1
SDI0=>EQ=>CH1CDR=>DR=>SDO1
SDI0=>EQ=>CH0CDR=>CH1CDR=>DR=>SDO1
When the crosspoint is enabled, the standard data path is not interrupted. For example:
in Mode 1, the input to SDI1 will also be accessible at SDO1. When using crosspoint
modes, the automute feature for SDO1 or SDO0 may have to be disabled if the
corresponding SDI1 or SDI0 inputs are unused.
The relevant parameters in these registers and their values required to enable each of
the crosspoint options indicated above, are shown in Table 3-7.
The selection of a crosspoint path impacts the following feature:
•
Polarity inversion
Table 3-7 also captures the impact on these features in each crosspoint mode.
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Table 3-7: Crosspoint Options
1
2
3
4
5
6
7
8
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Y
Y
Y
Y
7
0
7
1
7
2
7
4
7
5
7
6
7
7
24
1
8
0
8
1
8
2
8
4
8
5
8
6
8
7
14
1
—
—
—
—
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Peak
Detector
VEye
Monitor
Ch0 EQ
Recovered
Clock
HEye Monitor
0
1
Ch0 CDR (10G/14G)
SDI0
Retimed
Input
Data
Data
0
1
LBCH0OUTEN = 1
0
0
1
SDO0
Ch0 Driver
1
CH0PLLPOLINV
Ch0Clk
PRBS 7
LBCH0OUTCH1DATA = 1
PRBS 7
Generator
Checker
Ch1Clk
Peak
Detector
1
0
0
1
Ch1 Driver
SDO1
VEye
Monitor
1
0
CH1PLLBYPASS = 1 (Mode 1)
CH1PLLBYPASS = 0 (Mode 2)
Ch1 LA
1
Input
Data
Retimed
Data
Mode 1: SDI1 => LA => LD => SDO0
0
SDI1
Ch1 CDR (10G/14G)
Mode 2: SDI1 => LA => Ch1 CDR => LD => SDO0
LBCH1INEN = 0
Recovered
Standard data path:
can be enabled in crosspoint mode
HEye Monitor
Clock
Figure 3-6: Crosspoint Modes 1 & 2
Peak
Detector
VEye
Monitor
Recovered
Clock
Ch0 EQ
HEye Monitor
LBCH0INEN = 1
Ch0 CDR (10G/14G)
0
1
SDI0
Retimed
Input
Data
Data
0
LBCH0OUTEN = 0
CH0PLLBYPASS = 0
1
0
0
Ch0 Driver
SDO0
1
1
CHPLLPOLINV
Ch0Clk
LBCH0INCH1DATA = 1
PRBS 7
Generator
PRBS 7
Checker
Ch1Clk
Peak
Detector
1
0
Ch1 Driver
SDO1
VEye
Monitor
1
0
1
0
CH1PLLBYPASS = 1 (Mode 3)
CH1PLLBYPASS = 0 (Mode 4)
Ch1 LA
1
0
Input
Data
Retimed
Data
Mode 3: SDI1 => LA => Ch0 CDR => LD => SDO0
SDI1
Ch1 CDR (10G/14G)
Mode 4: SDI1 => LA => Ch1 CDR => Ch0 CDR => LD => SDO0
LBCH1INEN = 0
Recovered
Standard data path:
can be enabled in crosspoint mode
HEye Monitor
Clock
Figure 3-7: Crosspoint Modes 3 & 4
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Peak
Detector
VEye
Monitor
Recovered
Clock
Ch0 EQ
HEye Monitor
LBCH0INEN = 0
0
Ch0 CDR (10G/14G)
SDI0
Retimed
Data
Input
Data
1
0
1
CH0PLLBYPASS = 1 (MODE 5)
CH0PLLBYPASS = 0 (MODE 6)
0
1
0
1
Ch0 Driver
SDO0
Ch0Clk
PRBS 7
PRBS 7
Generator
Checker
LBCH1OUTCH0DATA = 1
Ch1Clk
Peak
Detector
CH1PLLPOLINV
1
0
1
Ch1 Driver
SDO1
VEye
Monitor
1
0
0
LBCH1OUTEN = 1
Ch1 LA
1
0
Retimed
Data
Input
Data
Mode 5: SDI0 => EQ => DR => SDO1
SDI1
Ch1 CDR (10G/14G)
Mode 6: SDI0 => EQ => Ch0 CDR => DR => SDO1
Recovered
Standard data path:
can be enabled in crosspoint mode
HEye Monitor
Clock
Figure 3-8: Crosspoint Modes 5 & 6
Peak
Detector
VEye
Monitor
Recovered
Clock
Ch0 EQ
HEye Monitor
LBCH0INEN = 0
Ch0 CDR (10G/14G)
0
1
SDI0
Retimed
Input
Data
Data
0
1
CH0PLLBYPASS = 1 (MODE 7)
CH0PLLBYPASS = 0 (MODE 8)
0
0
1
Ch0 Driver
SDO0
1
Ch0 Clk
PRBS 7
Generator
PRBS 7
Checker
LBCH1INCH0DATA = 1
Ch1 Clk
CH1PLLPOLINV
0
Peak
Detector
1
0
SDO1
Ch1 Driver
VEye
1
0
1
Monitor
CH1PLLBYPASS = 0
LBCH1OUTEN = 0
Ch1 LA
1
0
Retimed
Data
Input
Data
Mode 7: SDI0 => EQ => Ch1 CDR => DR => SDO1
SDI1
Ch1 CDR (10G/14G)
Mode 8: SDI0 => EQ => Ch0 CDR = > Ch1 CDR => DR => SDO1
LBCH1INEN = 1
Recovered
Standard data path:
can be enabled in crosspoint mode
HEye Monitor
Clock
Figure 3-9: Crosspoint Modes 7 & 8
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3.5 Status Indicators
The GX4002 supports three status indicators: Loss of Signal (LOS), Loss of Lock (LOL) and
Channel 0 Fault (Ch0FAULT). LOS and LOL indicators are available on both the Ch1 and
the Ch0 paths.
3.5.1 Ch0 Loss Of Signal (LOS)
The Ch0 LOS indicator status is available through a register. If desired, its status can be
included in the generation of the Ch0FAULT output pin. The LOS assert threshold can be
set from 20mV to 100mV in <1mV steps. In addition, the temperature coefficient of the
LOS threshold can be adjusted to ensure consistent LOS operation over temperature.
The LOS also has hysteresis that is programmable from 0dB to 6dB in steps of 0.5dB.
The following registers are used to control the Ch0 LOS feature:
Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Negative temperature coefficient LOS
threshold setting.
CH0_REG9
CH0_REG10
CH0_REG11
39
CH0LOSTHNEG
CH0LOSTHPOS
CH0LOSHYS
7:0
7:0
3:0
RW
RW
RW
01010011
00000000
1001
0-255
0-255
0-15
Positive temperature coefficient LOS
threshold setting.
40
41
Sets LOS hysteresis from 0dB to 6dB in steps
of 0.5dB.
When HIGH, asserts LOS for internal
functions, asserts LOS register (CH0PLLLOS)
and asserts external indication through
Ch0FAULT.
CH0LOSSOFTASSERT
3:3
4:4
RW
RW
0
0
0-1
0-1
CH0_REG12
42
When HIGH, LOS is controlled by
CH0LOSSOFTASSERT.
CH0LOSSOFTASSERTEN
3.5.1.1 Ch0 LOS Threshold
Figure 3-10 and Figure 3-11 show the typical recommended range of Ch0 LOS assert
thresholds and corresponding CH0LOSTHNEG[7:0] setting to achieve these thresholds.
It is recommended to keep CH0LOSPOS[7:0] = 0 to achieve a flat temperature
coefficient for LOS threshold. The Ch0 LOS de-assert thresholds are the same as the Ch0
LOS assert thresholds for a hysteresis setting of 0.
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Hys = 0
Hys = 9
Hys = 15
160
140
120
100
80
0dB
3dB
6dB
60
40
20
0
0
50
100
150
200
250
300
CH0LOSTHNEG
Figure 3-10: Ch0 LOS Assert Threshold – Typical
Hys = 0
Hys = 9
160
140
120
100
80
60
40
20
0
0
50
100
150
200
CH0LOSTHNEG
Figure 3-11: Ch0 LOS De-Assert Threshold – Typical
The LOS threshold will have a slight dependence on data rate.
3.5.1.2 Manual LOS Assert
The on-chip LOS circuit can be bypassed, and LOS asserted, through the host interface.
This operation is initiated when CH0LOSSOFTASSERTEN is HIGH. The state of
CH0LOSSOFTASSERT then controls the LOS register CH0PLLLOS and external
indication through Ch0FAULT.
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
When HIGH, asserts LOS.
CH0LOSSOFTASSERTEN must be HIGH to use
this bit.
CH0LOSSOFTASSERT
3:3
4:4
RW
RW
0
0
0-1
0-1
CH0_REG12
61
When HIGH, LOS is controlled by
CH0LOSSOFTASSERT.
CH0LOSSOFTASSERTEN
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3.5.2 Ch1 Loss Of Signal
The Ch1 Loss Of Signal (LOS) indicator status is available through a register and the
Ch1LOS pin. The Ch1LOS pin is by default open-drain, active-high. However, the pin
can be configured in a LVCMOS/LVTTL compatible mode by setting
OPENDRAINCH1LOS to 0. In addition, Ch1LOS can be configured to be active-low by
setting POLINVCH1LOS HIGH. The status of Ch1LOS can be read out through
CH1PLLLOS.
Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
When HIGH, inverts polarity of Ch1LOS
output.
POLINVCH1LOS
1:1
RW
0
0-1
TOP_REG2
2
When HIGH, makes Ch1LOS output driver
open-drain.
OPENDRAINCH1LOS
CH1PLLLOS
2:2
0:0
RW
RO
1
0
0-1
0-1
CH1PLL_REG10
29
Ch1 CDR loss of signal when HIGH.
The LOS assert threshold can be set from 5mV to 400mV in three distinct ranges. The LOS
assert threshold is a function of the CH1LABOOST setting. Figure 3-8 describes the
selection of CH1LOSRANGE based on the required LOS assert threshold and
CH1LABOOST settings.
Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
1:0 - LOS range 0: highest - 3: lowest, 2
(MSB) unused.
CH1_REG14
61
CH1LOSRANGE
2:0
RW
001
0-7
Table 3-8: LOS Assert Ranges
LOS Assert Threshold Range
Resolution
(controlled by
CH1LOSTHNEG/POS)
CH1LABOOST
[3:0]
CH1LOSRANGE
[1:0]
Unit
Min
Max
LOS Threshold -
Total Range
5
400
—
mVppd
0-7
0-7
—
5
—
30
11 - Unused
10 - Low Range
01 - Mid Range
00 - High Range
11 - Low Range
10 - Mid Range
01 - Unused
—
—
<0.1mV
<1.0mV
<2.0mV
<0.1mV
<1.0mV
—
mVppd
mVppd
mVppd
mVppd
mVppd
—
0-7
30
100
5
100
400
30
0-7
8-15
8-15
8-15
8-15
30
—
100
—
100
400
00 - High Range
<2.0mV
mVppd
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3.5.2.1 Ch1 LOS Threshold
The LOS assert threshold is set using the following registers. Apart from setting the assert
thresholds, these registers also set the temperature coefficient. Through weighted
summing of the CH1LOSTHNEG[7:0] and CH1LOSTHPOS[7:0] values, a range of
temperature coefficients can be achieved to ensure consistent LOS operation over
temperature:
Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Negative temperature coefficient LOS
threshold setting.
CH1_REG9
56
CH1LOSTHNEG
CH1LOSTHPOS
7:0
7:0
RW
RW
10000011
00010001
0-255
0-255
Positive temperature coefficient LOS
threshold setting.
CH1_REG10
57
Figure 3-12 to Figure 3-15 show the typical recommended range of CH1LOSASSERT
thresholds and corresponding CH1LOSTHNEG[7:0] setting to achieve these thresholds.
It is recommended to keep CH1LOSPOS[7:0] = 0. The CH1LOSDEASSERT thresholds
are the same as the CH1LOSASSERT thresholds for a hysteresis setting of 0.
CH1LOSHYS = 0
CH1LOSHYS = 9
CH1LOSHYS = 15
700
600
500
400
300
200
100
0
0dB
3.5dB
6dB
0
50
100
150
200
250
300
CH1LOSTHNEG
Figure 3-12: Ch1 LOS Threshold vs. Hysteresis (CH1LOSRANGE = 0)
CH1LOSHYS = 0
CH1LOSHYS = 9
CH1LOSHYS = 15
160
140
120
100
80
60
40
20
0
0
50
100
150
200
250
300
CH1LOSTHNEG
Figure 3-13: Ch1 LOS Threshold vs. Hysteresis (CH1LOSRANGE = 1)
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CH1LOSHYS = 0
CH1LOSHYS = 9
CH1LOSHYS = 15
70
60
50
40
30
20
10
0
0
50
100
150
200
250
300
CH1LOSTHNEG
Figure 3-14: Ch1 LOS Threshold vs. Hysteresis (CH1LOSRANGE = 2)
CH1LOSHYS = 0
CH1LOSHYS = 9
CH1LOSHYS = 15
35
30
25
20
15
10
5
0
0
50
100
150
200
250
300
CH1LOSTHNEG
Figure 3-15: Ch1 LOS Threshold vs. Hysteresis (CH1LOSRANGE = 3)
3.5.2.2 Ch1 LOS Hysteresis
The LOS detector supports programmable hysteresis ranging from 0dB to 6dB,
adjustable in steps of less than 0.5dB. The following register can be used to program the
hysteresis. Note that the effective hysteresis is somewhat dependent on the threshold
value:
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
Sets LOS hysteresis from 0dB to 6dB in steps
of 0.5dB.
CH1_REG13
60
CH1LOSHYS
3:0
RW
1001
0-15
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Hysteresis control only affects the assert threshold. The LOS de-assert threshold is set by
CH1LOSTHNEG and CH1LOSTHPOS controls only. Figure 3-16 shows the hysteresis
characteristics and the impact of CH1LOSHYS[3:0]:
LOS Asserted
CH1LOSHYS
Hys (dB)
The LOS de-assert
threshold stays constant,
and only the LOS assert
threshold level varies with
the hysteresis setting,
CH1LOSHYS.
0
1
0.1
0.3
0.7
1.1
1.4
1.8
2.1
2.5
3.0
3.4
3.9
4.4
4.8
5.4
6.7
LOS O/P
2
CH1LOSHYS 15 to 0
LOS De-asserted
3
LOS Assert
Threshold
LOS De-assert
Threshold
4
5
Vin (mVppd)
6
LOS Asserted
7
8
LOS O/P
9
10
11
12
13
15
CH1LOSHYS 15 to 0
LOS De-asserted
LOS Assert
Threshold
LOS De-assert
Threshold
CH1LOSTHNEG
(for fixed Vin)
Hys (dB) = 20*log10(Vth_assert/Vth_deassert)
Figure 3-16: Ch1 LOS Hysteresis
3.5.2.3 Manual LOS Assert
The on-chip LOS circuit can be bypassed, and LOS asserted, through the host interface.
This operation is initiated when CH1LOSSOFTASSERTEN is HIGH. The state of
CH1LOSSOFTASSERT then controls the LOS register CH1PLLLOS and external
indication through Ch1LOS.
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
When HIGH, asserts LOS.
CH1LOSSOFTASSERTEN must be HIGH to use
this bit.
CH1LOSSOFTASSERT
6:6
7:7
RW
RW
0
0
0-1
0-1
CH1_REG14
61
When HIGH, LOS is controlled by
CH1LOSSOFTASSERT.
CH1LOSSOFTASSERTEN
3.5.3 Loss Of Lock (LOL)
The channel 0 and channel 1 LOL status indicators are both available in registers as
shown below:
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Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
CH0PLL_REG10
CH1PLL_REG10
19
29
CH0PLLLOL
CH1PLLLOL
1:1
1:1
RO
RO
0
0
0-1
0-1
Ch0 CDR loss of lock when HIGH.
Ch1 CDR loss of lock when HIGH.
3.5.4 Ch0FAULT - Channel 0 Fault
Various status indicator pins are combined to generate a single Ch0FAULT indicator
output. The Ch0FAULT output is, by default, an open-drain output. It can be configured
in a LVCMOS/LVTTL compliant mode through register 2, bit 3
(OPENDRAINCH0FAULT). When set LOW, the Ch0FAULT output is configured as
LVCMOS/LVTTL compatible output.
The Ch0FAULT output is active-high by default. Its polarity can be changed to make it
active-low through register 2, bit 0 (POLINVCH0FAULT). When set HIGH, Ch0FAULT is
configured as an active-low output.
The following status indicator controls can be combined to generate the Ch0FAULT
output. Each of the indicators can be independently masked through the register
controls. By default, the Ch0FAULT output combines (ORs) the status of all indicators.
The following registers control the masking of the various indicators for Ch0FAULT and
the configuration of Ch0FAULT pin.
Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
When HIGH, masks out Ch1LOS from
asserting CH0FAULT.
FAULTMASKCH1LOS
FAULTMASKCH1LOL
FAULTMASKCH0LOS
FAULTMASKCH0LOL
FAULTMASKCH0FAULT
POLINVCH0FAULT
0:0
1:1
2:2
3:3
4:4
0:0
3:3
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
0
0
1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
When HIGH, masks Ch1LOL from asserting
Ch0FAULT.
When HIGH, masks outCh0LOS from
asserting CH0FAULT.
TOP_REG1
1
When HIGH, masks Ch0LOL from asserting
Ch0FAULT.
When HIGH, masks out Ch0Fault from
asserting CH0FAULT.
When HIGH, inverts polarity of CH0FAULT
output.
TOP_REG2
2
When HIGH, makes CH0FAULT output driver
open drain.
OPENDRAINCH0FAULT
NOTE: To support system diagnostics, a manual Ch0FAULT assert feature is available through the following register:
TOP_REG4 FORCECH0FAULT 4:4 RW
4
0
0-1
When HIGH, asserts CH0FAULT.
3.6 Test Features
The GX4002 contains built-in test features that can be used during module test, mission
mode, or system testing.
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3.6.1 PRBS Generator and Checker
The GX4002 has a built in PRBS7 generator and checker. The generator and checker are
disabled by default to save power, and can be enabled through the digital control
interface. There are multiple ways to use the PRBS generator/checker, as shown in
Table 3-9 below:
Table 3-9: PRBS Generator/Checker Modes of Operation
Mode
Description
A data pattern, such as PRBS data or Fibre Channel/10GbE traffic, can be sent to the Ch1 path
input. A PRBS7 pattern can be viewed at the Ch1 path output, or can be looped back to the
Ch0 side to use the PRBS checker.
Lock to data pattern on Ch1 input
A data pattern, such as PRBS data or Fibre Channel/10GbE traffic, can be sent to the Ch0 path
input. A PRBS7 pattern can be viewed at the Ch0 path output, or can be looped back to the
Ch1 side to use the PRBS checker.
Lock to data pattern on Ch0 input
A reference at 1/8 (14G) or 1/4 (10G) of the desired rate can be sent to the Ch1 input. A PRBS7
pattern can be viewed at the Ch1 path output, or can be looped back to the Ch0 side to use
the PRBS checker. This mode can be used when testing a module so that high-speed test
equipment is not required. See Figure 3-17.
Lock to low-speed reference on
Ch1 input
A reference at 1/8 (14G) or 1/4 (10G) of the desired rate can be sent to the Ch0 input. A PRBS7
pattern can be viewed at the Ch0 path output, or can be looped back to the Ch1 side to use
the PRBS checker. This mode can be used when testing a module so that high-speed test
equipment is not required. See Figure 3-18.
Lock to low-speed reference on
Ch0 input
Peak
Detector
VEye
Monitor
Recovered
Clock
Ch0 EQ
HEye Monitor
LBCH0INEN = 0
0
Ch0 CDR (10G/14G)
SDI0
Input
Data
Retimed
Data
1
CH0PLLBYPASS = 0
0
1
LBCH0OUTEN = 0
PRBS Out
SDO0
PRBSCHKCLKSEL = 1
0
0
1
External
Loopback
Ch0 Driver
1
CH0PLLPOLINV
Ch0Clk
PRBS 7
PRBS 7
Generator
Checker
LBCH1OUTPRBSGEN = 1
Ch1Clk
0
1
Peak
Detector
CH1PLLPOLINV
1
0
1
Ch1 Driver
SDO1
VEye
Monitor
1
0
0
LBCH1OUTEN = 1
Ch1 LA
1
0
Input
Data
Retimed
Data
High-speed Data
fclk/8 (14G)
fclk/4 (10G)
SDI1
Ch1 CDR (10G/14G)
High-speed Clock
LBCH1INEN = 0
Recovered
Low-speed Reference
Clock
PRBSGENCLKSEL = 0
HEye Monitor
Figure 3-17: PRBS Generator on Ch1 Output and PRBS Check Monitoring Ch0 Input
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Peak
Detector
VEye
Monitor
Recovered
Clock
Ch0 EQ
HEye Monitor
LBCH0INEN = 0
0
fclk/8 (14G)
fclk/4 (10G)
Ch0 CDR (10G/14G)
SDI0
Input
Data
Retimed
Data
1
0
1
LBCH0OUTEN = 1
LBCH0OUTPRBSGEN
= 1
PRBSGENCLKSEL = 1
Ch0Clk
0
0
1
SDO0
Ch0 Driver
1
1
0
CH0PLLPOLINV
PRBS 7
PRBS 7
Generator
Checker
Ch1Clk
External
Loopback
Peak
Detector
CH1PLLPOLINV
PRBS Out
SDO1
1
0
1
Ch1 Drv
VEye
Monitor
1
0
0
CH1PLLBYPASS = 0
LBCH1OUTEN = 0
Ch1 LA
1
0
Input
Data
Retimed
Data
High-speed Data
SDI1
Ch1 CDR (10G/14G)
Recovered
Clock
High-speed Clock
LBCH1INEN = 0
Low-speed Reference
PRBSCHKCLKSEL = 0
HEye Monitor
Figure 3-18: PRBS Generator on Ch0 Output and PRBS Check Monitoring Ch1 Input
The following registers enable and configure the PRBS generator and checker:
Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
When pulsed HIGH and LOW, starts off the
PRBS generator.
PRBSGENSTART
0:0
RW
0
0-1
TOP_REG3
TOP_REG6
3
6
7
When HIGH, clears the latched error flag
from checker.
PRBSCHKCLEARERR
PRBSCHKSTATUS
LBCH1INPRBSGEN
1:1
0:0
1:1
RW
RO
0
0
0
0-1
0-1
0-1
When HIGH, checker detected an error.
Selects PRBS generator output into Ch1
CDR.
RW
LOOPBK_REG1
Selects PRBS generator output into Ch1
Driver.
LBCH1OUTPRBSGEN
LBCH0INPRBSGEN
LBCH0OUTPRBSGEN
PRBSGENCLKSEL
PRBSCHKCLKSEL
PDPRBSGEN
6:6
1:1
6:6
0:0
1:1
1:1
2:2
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
1
1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
Selects PRBS generator output into Ch0
CDR.
LOOPBK_REG2
LOOPBK_REG3
PWRDN_REG2
8
9
Selects PRBS generator output into Ch0
Driver.
When HIGH, selects Ch0 recovered clock.
LOW selects Ch1 clock.
When HIGH, selects Ch0 recovered clock.
LOW selects Ch1 clock.
When HIGH, power-down the PRBS
generator and associated buffers.
161
When HIGH, power-down the PRBS
generator and associated checkers.
PDPRBSCHK
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To ensure proper operation of the PRBS7 generator, PRBSGENSTART needs to be set
HIGH and then LOW once after the generator is powered-up through PDPRBSGEN.
To ensure proper operation of the PRBS7 checker, PRBSCHKCLEARERR needs to be set
HIGH and then LOW after application of valid PRBS7 pattern to clear any spurious
errors. PRBSCHKSTATUS, may be polled to check for errors flagged by the checker.
The PRBS generator can be configured to apply the PRBS7 pattern to SDO1 or SDO0 or
internally. Apply to either the Ch1 or the Ch0 CDR for retiming before transmitting out
through SDO. Controls LBCH1INPRBSGEN, LBCH1OUTPRBSGEN,
LBCH0INPRBSGEN and LBCH0OUTPRBSGEN determine the path of the PRBS pattern.
Both PRBS generator and checker can be clocked off either the Ch0 or Ch1 recovered
clocks independently through controls PRBSGENCLKSEL and PRBSCHKCLKSEL. The
PRBS checker automatically selects retimed data from the CDR which is chosen to
provide its clock through PRBSCHKCLKSEL.
3.6.2 Eye Monitor & Peak Detector
The GX4002 has built-in eye monitors in both the horizontal and vertical direction for
the inner eye. These eye monitors are available for both Ch1 and Ch0 paths. In addition,
both Ch1 and Ch0 inputs have peak detectors available to provide outer eye
information. The information from these monitors can be used to indicate if the input to
the module has degraded. These features can be used during mission mode.
Figure 3-19 shows where the eye monitoring functions are implemented:
EQ
Ch0 CDR
DR
SDO0
SDO1
SDI0
Vertical Eye
Monitor,
Peak Detect
Horizontal
Eye Monitor
SDI1
LA
Ch1 CDR
DR
Figure 3-19: Eye Monitor Implementation
The vertical eye monitor outputs a value proportional to the inner eye opening. The
output of the eye monitor can be sampled and read out digitally through the ADC (see
Section 3.7.1). The acquisition time for the eye monitor is approximately 10ms.
The peak detector outputs a value proportional to the outer eye amplitude. The output
of the peak detector can be sampled and read out digitally through the ADC. The
acquisition time is approximately 10ms.
The horizontal eye monitor outputs a value that is proportional to the horizontal eye
opening, as shown in Figure 3-20 below. The output of the horizontal eye monitor can
be sampled and read out digitally through the ADC. The acquisition time is
approximately 10ms.
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0.25
0.5
Data Jitter, UIpp
Figure 3-20: Horizontal Eye Monitor
All eye monitoring functions can be independently enabled to optimize power. The
following register can be used to enable and control the eye monitors. See Section 3.7 for
details on sampling and reading out the monitors:
Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Vertical eye monitor threshold adjustment,
0-255.
CH0_REG13
43
CH0VEYETHADJ
CH0VEYETHPOL
7:0
0:0
1:1
2:2
7:0
0:0
1:1
2:2
1:1
RW
RW
RW
RW
RW
RW
RW
RW
RW
00000000
0-255
0-1
Vertical eye monitor threshold polarity.
HIGH is positive.
0
When HIGH, reduces the range to
0-600mVppd.
CH0_REG14
CH1_REG15
CH1_REG16
44
62
63
CH0VEYELORANGE
CH0VEYEOFFCALEN
CH1VEYETHADJ
0
0-1
Vertical eye monitor offset calibration
enable.
0
0-1
Vertical eye monitor threshold adjustment,
0-255.
00000000
0-255
0-1
Vertical eye monitor threshold polarity.
HIGH is positive.
CH1VEYETHPOL
0
0
0
1
When HIGH, reduces the range to
0-600mVppd.
CH1VEYELORANGE
CH1VEYEOFFCALEN
CH0PDVEYEMON
0-1
Vertical eye monitor offset calibration
enable.
0-1
Power-down for the Ch0 vertical eye
monitor.
0-1
CH0PWRDN_REG3
CH1PWRDN_REG3
153
158
Power-down for the Ch0 horizontal eye
monitor.
CH0PDHEYEMON
CH0PDPKDET
2:2
3:3
1:1
RW
RW
RW
1
1
1
0-1
0-1
0-1
Power-down for the Ch0 peak detector.
Power-down for the Ch1 vertical eye
monitor.
CH1PDVEYEMON
Power-down for the Ch1 horizontal eye
monitor.
CH1PDHEYEMON
CH1PDPKDET
2:2
3:3
RW
RW
1
1
0-1
0-1
Power-down for the Ch1 peak detector.
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3.7 Digital Diagnostics
The GX4002 has an on-chip ADC to provide diagnostic information through the digital
interface. Temperature and voltage can be monitored.
3.7.1 Analog to Digital Converter (ADC)
The ADC converts several analog quantities including temperature, supply, vertical and
horizontal eye monitor outputs, and peak detector outputs.
The ADC is a sigma-delta converter with programmable resolution allowing trade-off
between conversion time and accuracy. The full scale dynamic range of the ADC is 0 to
1.8V. The various sources can be selected into the ADC for conversion and read-out.
Offset calibration signals are provided to zero-out the selected sources to facilitate the
calibration. Calibrated offsets can be programmed-in, such that the data read-out has
corrected offsets.
Furthermore, a user-defined offset can be programmed-in to account for external
systemic shifts. For example: if the temperature at the case is desired instead of the
device temperature, the temperature delta between device and case can be
programmed-in. Subsequent temperature read-outs will account for the temperature
delta, and provide the case temperature.
3.7.1.1 Usage Model
Two usage models are possible, manual conversion and auto conversion.
3.7.1.1.1 MANUAL CONVERSION MODE
For manual conversion mode, register controls provide a conversion-on-demand
interface. Polling or timing is required at the master end to read out the converted values
in manual mode.
The user is expected to select the desired source and to write a 1 to the
ADCSTARTCONVbit to initiate the conversion. The user can poll the ADCDONECONV
bit or time the conversion based on the requested resolution before reading out the data.
To read out the data in the timed mode, a block read transfer can be performed on the
ADCDONECONV, ADCOUTLO and ADCOUTHI registers. If the ADCDONECONV bit
is HIGH, then the data is valid.
The ADCSTARTCONVbit does not have to be reset before initiating another conversion.
Similarly, the ADCDONECONV bit does not have to be reset before initiating another
conversion. This minimizes the host interface transaction overhead while using the
ADC.
3.7.1.1.2 AUTO CONVERSION MODE
The user selects the desired source, and enables the auto conversion mode by setting
ADCAUTOCONVENHIGH. The ADC will continuously convert the selected source and
update the ADCOUTHI/LO registers.
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The ADCDONECONV bit will always remain HIGH, indicating a valid converted value
is available for read-out. This flag may be cleared by writing to the ADCSTARTCONVbit
if positive indication of valid data is required.
3.7.1.2 ADC Control Registers
The following registers are used to select the various sources for conversion and
read-out through the ADC. The offset calibration controls ADCOFFCALEN[3:0]
facilitate calibrating the offsets of the selected sources:
Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Selects input for ADC (see Table 3-3: ADC
Source Select).
ADCSRCSEL
3:0
7:4
RW
RW
0000
0000
0-15
0-15
ADC_REG1
143
Selects source for offset calibration (see
Table 3-2).
ADCOFFCALEN
Table 3-3: ADC Source Select
ADCSRCSEL[3:0]
Source
0000
0001
0010
0.9V
Ch0 Vertical Eye
Ch1 Vertical Eye
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Ch0 Horizontal Eye
Ch1 Horizontal Eye
Ch0 Peak Detector
Ch1 Peak Detector
RSVD
RSVD
RSVD
Temperature Sensor
Supply Sensor
0.45V
1.35V
RSVD
RSVD
The following registers are used to program a calibrated offset for automatic offset
correction. ADCOFFMODE and ADCRESOLUTION determine how the offset values
are interpreted.
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Register
Address
b
d
Register Name
Parameter Name
Bit Position
Access
Function
Reset Value
Valid Range
d
ADC_REG7
ADC_REG8
149
150
ADCOFFSETLO
ADCOFFSETHI
7:0
7:0
RW
RW
00000000
00000000
0-255
0-255
ADC offset LSB, unsigned binary.
ADC offset MSB, unsigned binary.
The following registers are used to configure the ADC:
Register
Address
b
d
Register Name
Parameter Name
Bit Position
Access
Function
Reset Value
Valid Range
d
ADCRESET
0:0
1:1
RW
RW
1
1
0-1
0-1
Reset for the ADC.
When HIGH, enables auto conversion.
Set LOW for manual.
ADCAUTOCONVEN
When HIGH, justify towards LSB. LOW
justifies towards MSB.
ADCJUSTLSB
2:2
RW
1
0-1
ADC_REG0
142
When LOW, offset is subtracted from the
ADC output. When HIGH, offset is added
to the ADC output.
ADCOFFMODE
3:3
RW
0
0-1
NOTE: When HIGH, ADCOFFSETHI[7] is
sign and rest of the bits are magnitude.
A sign value of 1 represents negative
numbers.
ADCRESOLUTION
ADCCLKRATE
2:0
5:3
RW
RW
001
0-7
ADC resolution control.
ADC clock divide ratio.
ADC_REG2
143
0101
0-15
Table 3-4: ADC Resolution
ADCRESOLUTION
Number of ADC Clocks
for Conversion
ADC Resolution (bits)
000
001
010
011
100
101
110
111
4
15
63
6
8
255
10
1023
4095
16383
65535
Unused
12
14
16
Unused
Table 3-5: ADC Clock Rate
ADCCLKRATE[2:0]
ADC Sampling Clock Rate
(MHz)
ADC Conversion Time
(μs) Res = 10 bits
000
001
1
1023
651
1.6
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Table 3-5: ADC Clock Rate (Continued)
ADC Sampling Clock Rate
ADC Conversion Time
(μs) Res = 10 bits
ADCCLKRATE[2:0]
(MHz)
010
011
100
101
110
111
2.1
2.7
3.3
3.9
4.4
5
477
377
311
265 (default)
231
205
The following registers are used to control the conversion, and read-out the converted
data:
Register
Address
b
d
Register Name
Parameter Name
Bit Position
Access
Function
Reset Value
Valid Range
d
ADC_REG3
ADC_REG4
ADC_REG5
ADC_REG6
145
146
147
148
ADCSTARTCONV
ADCDONECONV
ADCOUTLO
0:0
0:0
7:0
7:0
RW
RO
RO
RO
0
0-1
0-1
ADC starts conversion.
ADC conversion done flag.
ADC output LOW MSB.
ADC output HIGH MSB.
0
00000000
00000000
0-255
0-255
ADCOUTHI
When HIGH, power-down the
temperature sensor.
PDTEMPSENSOR
3:3
RW
1
0-1
PWRDN_REG2
161
When HIGH, power-down the supply
sensor.
PDSUPPLYSENSOR
PDADC
4:4
5:5
RW
RW
1
1
0-1
0-1
When HIGH, power-down the ADC.
3.7.1.3 ADC Offset Calibration
The ADC supports conversion of several different sources. Each source can have a
different offset associated with it. To allow accurate conversion for each source, it is
recommended that the offset be calibrated for each source, so that the appropriate
correction can be applied when converting a given source.
There are two steps involved in the calibration of offsets:
1. Offset measurement.
2. Offset correction.
3.7.1.3.1 OFFSET MEASUREMENT
Offset measurement of any source requires zeroing-out the source, such that its output
constitutes the offset only. With the source zeroed-out, the output of the ADC is then the
cumulative offset. This offset is subtracted from subsequent measurements of the same
source to get an accurate offset corrected conversion.
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The device supports offset measurement of each source through the ADCSRCSEL and
ADCOFFCALEN register controls. ADCOFFCALEN selects the source to zero-out, as
shown in Table 3-2:
Table 3-2: Offset Measurement Sources
ADC Offset Calibration
ADCOFFCALEN[3:0]
Source
Input (Vcal)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0.9V
Ch0 Vertical Eye
Ch1 Vertical Eye
Ch0 Horizontal Eye
Ch1 Horizontal Eye
Ch0 Peak Detector
Ch1 Peak Detector
RSVD
0.9V
0.9V
0.9V
0.9V
0.9V
0.45V
0.45V
N/A
RSVD
N/A
RSVD
N/A
Temperature Sensor
Supply Sensor
0.45V
0.9V
0.9V
0.45V
1.35V
N/A
1.35V
RSVD
RSVD
N/A
When a selected source is zeroed-out, the input to the ADC is set to its calibration voltage
(Vcal) as per Table 3-2. The ideal code for that calibration voltage for a given resolution,
can be subtracted from the output code to get the offset. Refer to the formula shown
below:
Equation 3-1
Vcal
1.8
Offset = ADCOut −(2N
−1)
For example: if the temperature sensor is selected as the source, then it’s Vcal = 0.9V.
Assuming that the ADC resolution (N) is set to 10 bits; by setting ADCOFFCALEN =
“1010”, and reading-out the ADC, (in this example) ADCOUT = 521.
Therefore, Offset = 521 - 511 = 10.
This measured offset can be subtracted from subsequent measurements automatically,
as described in the next section.
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3.7.1.3.2 OFFSET CORRECTION
The ADC supports offset correction for both internal offsets as well as external
systematic offsets through the ADCOFFSETLO and ADCOFFSETHI registers.
The offset correction behaviour depends on the ADCOFFMODE control bit. Table 3-3
describes the offset correction operation:
Table 3-3: Offset Correction Operation
ADCOFFMODE
Operation
Description
ADCOUTLO,HI = uncorrected
ADC Out[15:0] -
ADCOFFSETLO,HI is un-signed.
Result is unsigned. Output is all 0s
for negative results.
0
ADCOFFSETLO,HI
ADCOFFSETLO,HI is sign + mag.
ADCOUTLO,HI = uncorrected
ADC Out[15:0] +
Bit 15 is sign, and 1 represents
positive. Result is unsigned. Output
is all 0s for negative results.
1
ADCOFFSETLO,HI
Supporting both subtraction and addition of offsets allows the user the flexibility to
adjust for systematic shifts. However, the default mode 0 (subtraction) should suffice for
most applications.
In the previous example, the offset was measured to be 10 for ADCOUT = 521 for the
temperature sensor. This offset can be automatically subtracted for all subsequent
measurements of the temperature sensor by setting ADCOFFSETLO = 10 and
ADCOFFSETHI = 0. With these values, ADCOUT will read 511 (instead of 521).
3.7.1.4 ADC Conversion Sequence
The following sequence is recommended for ADC conversions:
1. Power-up the ADC.
2. Bring the ADC out of reset.
3. Setup the ADC mode of operation (Auto or Manual).
4. Setup the ADC resolution.
5. Setup the ADC conversion rate (clock rate).
6. Select the ADC source to convert.
7. Setup the ADC offset and offset modes.
8. Start the ADC conversion.
9. Read the ADC-done conversion flag to confirm a successful conversion.
10. Read the ADC output, first the low byte, immediately followed by high byte.
The following section gives a detailed example of performing an ADC conversion in
manual mode.
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Example ADC Conversion in Manual Mode
The following example illustrates how to use the ADC to read-out the supply sensor in
manual conversion mode:
1. Power-up the ADC and the supply sensor.
Register: PWRDN_REG2, Address: 161, PDADC = 0.
Register: PWRDN_REG2, Address: 161, PDSUPPLYSENSOR = 0.
2. Bring the ADC out of reset.
Register: ADC_REG0, Address: 142, ADCRESET = 0
3. Set the ADC mode of operation to manual mode.
Register: ADC_REG0, Address: 142, ADCAUTOCONVEN = 0.
Note that this must be a separate write operation than the reset exit, even though
it's the same register.
4. Set the ADC resolution to 12 bits.
Register: ADC_REG2, Address: 144, ADCRESOLUTION = 4.
5. Set the ADC conversion rate.
Register: ADC_REG2, Address: 144, ADCCLKRATE = 5 (default).
6. Select the ADC source as the supply sensor.
Register: ADC_REG1, Address: 143, ADCSRCSEL = 11 (decimal).
7. Set the ADC offset and offset mode (in this example, an offset of 0 is assumed).
Register: ADC_REG0, Address: 142, ADCOFFMODE = 0 (default).
Register: ADC_REG7, Address: 149, ADCOFFSETLO = 0.
Register: ADC_REG8, Address: 150, ADCOFFSETHI = 0.
8. Start the ADC conversion.
Register: ADC_REG3, Address: 145, ADCSTARTCONV = 1.
Note that it is not required to reset the ADCSTARTCONV to 0 before starting
another conversion. Writing a value of 1 to the ADCSTARTCONV bit again will
initiate a new conversion.
Read the ADC-done flag and output.
Register: ADC_REG4,5,6 Address: 146-148, ADCDONECONV, ADCOUTLO,
ADCOUTHI.
These three registers can be read-out as burst read. Note that it is important that the
LOW byte be read-out first, immediately followed by a HIGH byte. This is required to
ensure data consistency. The ADCDONECONV flag can be checked to confirm
successful conversion.
3.7.1.5 ADC Transfer Functions for Each Source
The following subsections show the typical transfer functions for each source that can
be read-out from ADC.
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Peak Detectors
Table 3-4 and Figure 3-21 show typical peak detector outputs:
Table 3-4: Peak Detector Outputs
Peak Detector Input
ADC (12-bit resolution)
Amplitude (mVppd)
ADC (10-bit resolution)
10
30
806
810
201
202
204
207
212
222
233
244
250
261
273
285
296
457
498
50
817
75
830
100
140
180
220
240
280
320
360
400
1000
1200
849
887
931
975
998
1044
1092
1139
1184
1828
1993
Peak Detector Output (Res=12b)
2000
1750
1500
1250
1000
750
0
200
400
600
800
1000
1200
1400
Ch1 Input (mVppd)
Figure 3-21: Peak Detector Output
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Temperature Sensor
Table 3-5 and Figure 3-22 show typical temperature sensor outputs:
Table 3-5: Typical Temperature Sensor Output
Temperature (°C)
ADC (12-bit resolution)
ADC (10-bit resolution)
-20.00
0.00
653
896
163
223
284
345
405
466
496
587
20.00
40.00
60.00
80.00
90.00
120.00
1138
1381
1623
1866
1987
2351
ADC Temp Monitor Transfer Function
700
600
500
400
300
200
100
0
10-bit
-40.00 -20.00 0.00 20.00 40.00 60.00 80.00 100.00 120.00 140.00
Temp(°C)
Figure 3-22: ADC Temperature Monitor Transfer Function
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Supply Sensor
Table 3-6 and Figure 3-23 show typical Ch0SDOVCC supply sensor outputs:
Table 3-6: Typical Ch0SDOVCC Supply Sensor Output
Ch0SDOVCC (V)
ADC (12-bit resolution)
ADC (10-bit resolution)
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
644
771
161
192
224
256
288
319
351
383
414
446
478
510
605
573
605
898
1025
1152
1279
1406
1532
1659
1786
1913
2040
2167
2294
2421
ADC Supply Monitor Transfer Function
700
600
500
400
300
200
100
0
10-bit
2.0
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Supply Voltage (V)
Figure 3-23: ADC Supply Monitor Transfer Function
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3.8 Power Control Options
The GX4002 provides a high-degree of flexibility in configuring the device for optimal
power through power-down and power adjustment registers. Typical usage scenarios
are shown. For further description on each of the individual control bits, see Table 7-1,
registers 134 to 137. This section describes the power-down controls for the following
sub-systems:
1. Ch1 CDR & SDO Power-Down
2. Ch0 CDR Power-Down
3. Ch0 SDO Power-Down
Table 3-7: Ch1 CDR & SDO Power-Down
Description
0
0
1
1
x
0
x
1
x
x
x
x
x
x
x
1
1
0
Completely powers-down the Ch1 CDR and Ch1 SDO.
Completely powers-down the Ch1 CDR and Ch1 SDO
Main data path through Ch1 CDR and Ch1 SDO is powered-up for bypass
mode. (Ch1LA has to be powered-up).
0
0
0
0
0
0
1
1
1
1
0
0
Mission mode, Ch1 CDR & SDO enabled in low-power mode.
Mission mode for fibre channel. Ch1 CDR & SDO are enabled with
automatic bypass through rate detection.
0
0
0
0
0
0
0
1
1
0
0
0
Diagnostic mode with horizontal eye monitor enabled.
Diagnostic mode with divided recovered clock available through Ch1 SDO.
Requires appropriate configuration of loopback registers.
Table 3-8: Ch0 CDR Power-Down
Description
0
1
1
0
1
1
x
x
x
x
1
0
Completely powers-down the Ch0 CDR
Main data path through Ch0 CDR is powered-up for bypass mode. (Ch0Eq
has to be powered-up).
0
0
0
1
1
0
Mission mode, Ch0 CDR is enabled in low power mode.
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Table 3-8: Ch0 CDR Power-Down (Continued)
Description
0
0
0
0
0
0
0
1
1
0
0
0
Diagnostic mode with horizontal eye monitor enabled.
Diagnostic mode with divided recovered clock available through Ch0 SDO.
Requires appropriate configuration of loopback registers.
Table 3-9: Ch0 SDO Power-Down
Description
1
x
0
0
x
1
0
0
x
x
x
0
x
x
1
0
Completely powers-down the Ch0 SDO.
Completely powers-down the Ch0 SDO.
Independently powers-down the Ch0 SDO cross point adjust feature.
Ch0 SDO with all features enabled.
3.9 Device Reset
RESET is an active-low signal with LVTTL/LVCMOS compatible signalling levels. RESET
has a weak pull-down to keep the device in reset upon power-up. RESET does not have
schmitt trigger since reset negation is internally synchronized. See Figure 6-7.
3.9.1 Reset State During Power-up
The device requires RESET to be continuously asserted LOW during power ramp up.
RESET must continue to be held in an asserted LOW state for the minimum specified
time after the power supply has reached 90% of its final settling value. Following a
RESET assertion at power-up, the device may be reset again at any time with the
minimum specified pulse width on RESET. Refer to Figure 3-24.
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Vcc
0.9*Vcc
RESET
Minimum pulse width
on RESET = t_chip_reset*
for subsequent resets
following reset
t_chip_reset*
*NOTE: Refer to Section 3.8.2
assertion at power-up
Figure 3-24: Reset State During Power-up
3.9.2 RESET Timing
The following RESET timing specifications apply:
t_chip_reset: 10μs
Defined as the minimum duration that RESET must be asserted after the supply has
reached 90% of final settling value. The device can be accessed 1μs after RESET goes
HIGH.
0.9*VCC
t_chip_reset
V
CC
RESET
Figure 3-25: GX4002 Device Reset Timing Diagram
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3.9.3 I/O and Register States During and After Reset
All configuration registers are set to their post-reset defaults state immediately
following RESET assertion.
The following I/O states are applicable upon RESET assertion:
Table 3-10: I/O and Register States During and After Reset
Pin Name
I/O State upon RESET Assertion
This pin is configured as an input while RESET is asserted and
immediately following RESET negation. When configured as an
input, this pin is high-impedance.
SDA
This pin is configured as an input while RESET is asserted, and
immediately following RESET negation. When configured as an
input, this pin is high-impedance.
SCL
This pin is configured as an open-drain output while RESET is
asserted and immediately following RESET negation.
Ch0FAULT
This output will be high-impedance, and its state will depend on
the external pull-up.
This pin is configured as an open-drain output while RESET is
asserted and immediately following RESET negation. If a signal
is present, the output will be pulled LOW. Otherwise, this output
will be high-impedance and it’s state will depend on the
external pull-up.
Ch1LOS
3.10 Digital Control Interface
2
The GX4002 has a serial control interface to communicate with the part. An I C protocol
can be used.
2
3.10.1 I C Host Interface Mode
2
The I C mode supports standard-mode (100kb/s) and fast-mode (400kb/s) signalling.
The device only supports slave mode. The pins SDA and SCL are used for bi-directional
serial data and clock respectively.
The GX4002 device slave address is 24h (= 0100100x).
2
The I C protocol is implemented as per the following description:
2
Each access begins with a 7-bit I C slave address word, an 8-bit register address word,
followed by two 8-bit data words written to, or read from, the GX4002.
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2
S
W
A
register address
A
register’s data
A
P
I
C Slave Address
Single 8-bit-Register Write Cycle - Over I 2C Bus
Legend:
A = Acknowledge (SDA LOW)
N = No Acknowledge (SDA HIGH)
S = Start Condition
R = Read mode (=1)
W = Write mode (=0)
From Master to Slave
From Slave to Master
Sr = Restart Condition
P = Stop Condition
2
Figure 3-26: Single Register Write Cycle over I C Bus
2
2
S
W
A
register address
A
Sr
R
A
register’s data
N P
I
C Slave Address
I C Slave Address
Single 8-bit-Register Read Cycle - Over I2C Bus
Legend:
A = Acknowledge (SDA LOW)
N = No Acknowledge (SDA HIGH)
S = Start Condition
R = Read mode (=1)
W = Write mode (=0)
From Master to Slave
From Slave to Master
Sr = Restart Condition
P = Stop Condition
2
Figure 3-27: Single Register Read Cycle over I C Bus
2
S
W
A
register address (RA)
A
data (RA)
A
data (RA + 1)
A
data (RA + 2)
A
I
C Slave Address
A
data (RA + n - 4)
A
data (RA + n - 3)
A
data (RA + n - 2)
A
data (RA + n - 1) A P
Multiple 8-bit-Registers (consecutive address) Write Cycle - Over I2C Bus
Legend:
A = Acknowledge (SDA LOW)
N = No Acknowledge (SDA HIGH)
S = Start Condition
R = Read mode (=1)
W = Write mode (=0)
From Master to Slave
From Slave to Master
Sr = Restart Condition
P = Stop Condition
2
Figure 3-28: Bulk Register Write Cycle over I C Bus
2
2
S
W
A
register address (RA)
A
Sr
R
A
data (RA)
A
I
C Slave Address
I
C Slave Address
A
data (RA + n - 4) data (RA + n - 3)
A
A
data (RA + n - 2)
A
data (RA + n - 1)
N P
Multiple Registers (consecutive address) Read Cycle - Over I2C Bus
Legend:
A = Acknowledge (SDA LOW)
N = No Acknowledge (SDA HIGH)
S = Start Condition
R = Read mode (=1)
W = Write mode (=0)
From Master to Slave
From Slave to Master
Sr = Restart Condition
P = Stop Condition
2
Figure 3-29: Bulk Register Read Cycle over I C Bus
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
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4. Typical Application Circuit
Populate for
open-collector
mode
DIG_3V3
SDO0_3V3
Ch1_3V3
Ch0_3V3
To/from
controller
From SFP+
connector
or to/from
13
17
1
controller
16
RESET
SDO1
8
Ch1LOS
RESET
SDO1
Ch1LOS
32 Ch0FAULT
Ch0FAULT
100nF
100nF
15
6Ω
100nF
100Ω differential pair
1kΩ
1kΩ
6
Ch1 Output
SDI1
SDI1
SDI1
14
10Ω
SDO1
SDO1
100Ω differential pair
Ch1 Input
AC Common Mode
Enhancement
100nF
1µF
7
Ch1LF
9
SDI1
Ch1LF
100nF
Ch1VCOFILT 11
Place close to chip
100nF
Ch1VCOFILT
100nF
SDI0
19
20
31 SDO0
SDO0
SDO0
SDI0
100Ω differential pair
100Ω differential pair
30
Ch0 Input
Ch0 Output
GX4002
100nF
SDI0
SDO0
SDI0
100nF
100nF
Ch0LF
Ch0VCOFILT
GND
23
21
24
Ch0LF
Place close to chip
DIG_3V3
1µF
Ch0VCOFILT
4.7kΩ
4.7kΩ
GND
SDA 25
SCL 26
RS0 29
SDA
SCL
From SFP+
connector
or to/from
controller
3
NC
RS0
RS1
NC
RS1
5
4
27
VREG
220nF
2
10 12 18 22 28
Figure 4-1: GX4002 Typical Application Circuit
•
•
Place lowest value decoupling capacitor closest to the device
Status indicator connections are shown for a LVCMOS/LVTTL compatible mode.
These I/Os can be configured as open-drain with pull-up
4.1 Power Supply Filter Recommendations
RC filters for isolating supplies are not recommended due to the large currents drawn
from each supply.
•
The Ch0 and Ch1 VCOs do not have independent supplies. Both of the Ch0 and Ch1
VCOs have internal regulators sourced from Ch0VCC and Ch1VCC respectively. As
a result, additional filtering for the VCOs is not required
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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For improved isolation between the Ch0 and Ch1 paths, and to achieve the best Ch1
Sensitivity and Ch0 Jitter Generation, a supply filter such as the one shown in Figure 4-2
is recommended.
Ch0SDOVCC
L9
C21
1µF
C22
L9: Ferrite Bead (0603)
1k, Rdc = 0.35Ω
Example: Murata
100nF
Ch0VCC
Ch1VCC
P/N BLM18HE102SN1
L10
C23
1µF
C24
L10: Ferrite Bead (0603)
1k, Rdc = 0.35Ω
Example: Murata
V3.3
100nF
P/N BLM18HE102SN1
L11
C25
1µF
C26
L11: Ferrite Bead (0603)
1k, RDC = 0.35Ω
Example: Murata
100nF
P/N BLM18HE102SN1
Figure 4-2: Power Supply Filter Recommendations
4.2 Power Supply Domains
Figure 4-3 shows the power supply domains for the GX4002:
Power Domains
Legend
1.8V
Regulator
Digital I/Os
Host I/F
Supply
Sensor
Ch0SDOVCC
Diagnostics
(ADC, Ch0Fault)
Ch0VCC
Ch1VCC
Reg
VCO
Trace Driver
O/P Stage
Pre-Driver
Ch0EQ
Ch0 CDR
PRBS Generator
+ Checker
Reg
VCO
Ch1 LA
Trace Driver
Ch1 CDR
Ch1VCOFILT
Figure 4-3: Power Supply Domains
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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5. Layout Considerations
The following high-frequency design rules should be considered to achieve optimum
performance of the GX4002:
•
Use carefully designed controlled-impedance transmission lines with minimal local
discontinuities for all high-speed data signals
•
•
Place decoupling capacitors as close as possible to the supply pins
For optimal electrical and thermal performance, the QFN’S exposed pad should be
soldered to the module ground plane
•
It is recommended to have LF cap ground and VCO caps ground to be common with
multiple stitching of vias to ground. Capacitors should be placed from smallest
value to largest value away from chip
•
•
All supply decoupling capacitors should have multiple vias to ground/power
planes, and placed as close to chip as possible
All supplies/grounds should be routed to corresponding decoupling capacitors
pads, and never to the centre pad
•
•
The recommended PCB layout for the GX4002 device is shown in Section 7.2
Some sample layouts are shown in Figure 5-1
32
31
26
25
30
29
28
27
SDO0VCC
SDO0VEE
NC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
Ch0LF
Ch0VCOVEE
Ch0VCOFILT
SDI0
NC
XPOINT
RS1
SDI1
SDI0
SDI1
Ch0VEE
Ch0VCC
Ch1LOS
9
10
11
12
13
14
15
16
Ground Pad
(bottom of package)
OUT
IN
OUT
IN
IN
OUT
IN
OUT
Figure 5-1: Sample Layouts
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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6. Input/Output Equivalent Circuits
Ch1VCC
Ch1VCC
Ch1VCC
SDI1
SDI1
50Ω
50Ω
Ch1VEE
Ch1VEE
Ch1VEE
Figure 6-1: SDI1
Ch0VCC
Ch0VCC
Ch0VCC
50Ω
50Ω
SDI0
SDI0
Ch0VEE
Ch0VEE
Ch0VEE
Figure 6-2: SDI0
Ch1VCC
Ch1VCC
50Ω
50Ω
SDO
SDO
Pre-emphasis
Control
2mA
Swing Control
Ch1VEE
Ch1VEE Ch1VEE
Figure 6-3: SDO1
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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Ch0SDOVCC
Ch0SDOVCC
50Ω
50Ω
SDO
SDO
Ch0SDOVEE
Ch0SDOVEE
Figure 6-4: SDO0
Ch0SDOVCC
Ch0SDOVCC
Ch0FAULT
ch0FAULT
Ch0SDOVEE Ch0SDOVEE
Ch0SDOVEE Ch0SDOVEE
Configured as open-drain
Figure 6-5: Ch0FAULT
Configured as LVCMOS
Ch1VCC
Ch1VCC
Ch1LOS
Ch1LOS
Ch1VEE
Ch1VEE
Ch1VEE
Ch1VEE
Configured as LVCMOS
Configured as open-drain
Figure 6-6: Ch1LOS
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
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Ch1VCC
Ch1VCC
Ch1VCC
Ch1VCC
RESET
50Ω
5µA
Ch1VEE
Ch1VEE
Ch1VEE
Ch1VEE
Ch1VEE
Figure 6-7: RESET
Ch0SDOVCC
Ch0SDOVCC
Ch0SDOVCC
VREG
50Ω
I2C Clock Input
SCL
Schmitt
Ch0SDOVEE
Ch0SDOVEE
Ch0SDOVEE
Ch0SDOVEE
Ch0SDOVCC
1kΩ
Ch0SDOVCC
Ch0SDOVEE
VREG
I2C Clock Output
Ch0SDOVEE
Ch0SDOVEE
Ch0SDOVEE
2
Figure 6-8: I C, SCL, SDA
Ch1VCC
Ch1VCC
Ch1VCC
Ch1VCC
50Ω
RS0
RS1
To Rate Select Logic
Schmitt
25µA
Ch1VEE
Ch1VEE
Ch1VEE
Ch1VEE
Ch1VEE
Figure 6-9: RS0, RS1
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
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7. Package and Ordering Information
7.1 Package Dimensions
The GX4002 is a 5mm x 5mm, 32-pin QFN.
Pin #1 identification
chamfer 0.400 x 45°
5.000 0.050
3.300 0.050
Exp.DAP
Pin 1 dot
by marking
0.400 0.050
0.500 Bsc
32L QFN
(5 x 5mm)
3.300 0.050
Exp.DAP
5.000 0.050
0.230 0.050
3.500
Ref.
Top View
Bottom View
A
0.203 Ref
0.000-0.050
MAX.
NOM.
MIN.
0.900
0.850
0.800
A
Side View
7.2 Recommended PCB Footprint
0.50
Pin #1
0.3
0.6
0.40 x 45°
4.20
3.30
Notes:
1. All dimensions in mm.
2. Drawing not to scale.
3. 16 thermal relief pins, evenly spaced on centre paddle,
connected to ground plane.
4. Drill size: 0.254mm.
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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7.3 Packaging Data
Parameter
Value
32-pin QFN / 5mm x 5mm
/ 0.5mm pad pitch
Package Type
Moisture Sensitivity Level
3
Junction to Case Thermal Resistance, θj-c
17.8°C/W
Junction to Air Thermal Resistance (at zero airflow), θj-a
26.4°C/W
0.4°C/W
Yes
Psi = Junction-to-Top (of Package) Characterization Parameter, Ψ
Pb-free and RoHS compliant
7.4 Solder Reflow Profile
The device is manufactured with Matte-Sn terminations and is compatible with both
standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed
using the maximum Pb-free reflow profile shown in Figure 7-1.
Temperature
60s to 150s
20s to 40s
260°C
250°C
3°C/s maximum
217°C
6°C/s maximum
200°C
150°C
25°C
Time
60s to180s maximum
8m maximum
Figure 7-1: Maximum Pb-free Solder Reflow Profile
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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7.5 Marking Diagram
Pin 1 ID
XXXX - Last 4 digits (excluding decimal)
of SAP Batch Assembly (FIN) as listed
on Packing Slip.
E3 - Pb-free & Green indicator
YYWW - Date Code
GX4002
XXXXE3
YYWW
7.6 Ordering Information
Part Number
Package
Temperature Range
GX4002-INE3
32-pin QFN
-40°C to 100°C
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
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Appendix: Configuration and Status Register Map
NOTE: *Indicates bits for lower data rates (below 10G operation).
Table 7-1: Configuration and Status Register Map
Register
Address
Valid
Range
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
RSVD
0
RSVD
7:0
0:0
RW
RW
00000000
1
0-255
0-1
Reserved. Do not change.
When HIGH, masks out Ch1LOS from asserting
Ch0FAULT.
FAULTMASKCH1LOS
FAULTMASKCH1LOL
FAULTMASKCH0LOS
FAULTMASKCH0LOL
When HIGH, masks Ch1LOL from asserting
Ch0FAULT.
1:1
2:2
3:3
RW
RW
RW
1
1
1
0-1
0-1
0-1
When HIGH, masks out Ch0LOS from asserting
Ch0FAULT.
TOP_REG1
1
When HIGH, masks Ch0LOL from asserting
Ch0FAULT.
When HIGH masks out Ch0FAULT from
asserting Ch0FAULT.
FAULTMASKCH0FAULT
RSVD
4:4
7:5
0:0
1:1
2:2
RW
RW
RW
RW
RW
0
000
0
0-1
0-7
0-1
0-1
0-1
Reserved. Do not change.
When HIGH, inverts polarity of Ch0FAULT
output.
POLINVCH0FAULT
POLINVCH1LOS
OPENDRAINCH1LOS
0
When HIGH, inverts polarity of Ch1LOS output.
When HIGH, makes Ch1LOS output driver
open-drain.
TOP_REG2
2
1
When HIGH, makes Ch0FAULT output driver
open-drain.
OPENDRAINCH0FAULT
RSVD
3:3
7:4
0:0
RW
RW
RW
1
0000
0
0-1
0-15
0-1
Reserved. Do not change.
When pulsed HIGH and LOW, starts off the
PRBS generator.
PRBSGENSTART
TOP_REG3
TOP_REG4
3
4
When HIGH, clears the latched error flag from
checker.
PRBSCHKCLEARERR
1:1
RW
0
0-1
RSVD
7:2
3:0
4:4
7:5
7:0
0:0
7:1
RW
RW
RW
RW
RW
RO
000000
1111
0-63
0-15
0-1
Reserved. Do not change.
RSVD
Reserved. Do not change.
FORCECH0FAULT
RSVD
0
When HIGH, asserts CH0FAULT.
Reserved. Do not change.
000
0-7
RSVD
5
6
RSVD
00001111
0
0-255
0-1
Reserved. Do not change.
PRBSCHKSTATUS
RSVD
When HIGH, checker detected an error.
Reserved. Do not change.
TOP_REG6
RW
0000000
0-127
NOTE: * Indicates bits for lower data rates (below 10G operation)
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
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Table 7-1: Configuration and Status Register Map (Continued)
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
LBCH1INEN
0:0
1:1
2:2
3:3
4:4
5:5
6:6
7:7
0:0
1:1
2:2
3:3
4:4
5:5
6:6
7:7
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
0-1
Selects LB input into Ch1 CDR.
LBCH1INPRBSGEN
LBCH1INCH0DATA
RSVD
Selects PRBS generator output into Ch1 CDR.
Selects Ch0 data into Ch1 CDR.
Reserved. Do not change.
LOOPBK_REG1
7
LBCH1OUTEN
Selects LB input into Ch1 Driver.
Selects Ch0 data into Ch1 Driver.
Selects PRBS generator output into Ch1 Driver.
Selects Ch1 Clock into Ch1 Driver.
Selects LB input into Ch0 CDR.
LBCH1OUTCH0DATA
LBCH1OUTPRBSGEN
LBCH1OUTCH1CLK
LBCH0INEN
LBCH0INPRBSGEN
LBCH0INCH0DATA
RSVD
Selects PRBS generator output into Ch0 CDR.
Selects Ch0 data into Ch0 CDR.
Reserved. Do not change.
LOOPBK_REG2
8
LBCH0OUTEN
Selects LB input into Ch0 Driver.
Selects Ch1 data into Ch0 Driver.
Selects PRBS generator output into Ch0 Driver.
Selects Ch1 clock into Ch0 Driver.
LBCH0OUTCH0DATA
LBCH0OUTPRBSGEN
LBCH0OUTCH1CLK
When HIGH, selects Ch0 recovered clock. LOW
selects Ch1 clock.
PRBSGENCLKSEL
0:0
RW
0
0-1
LOOPBK_REG3
9
When HIGH selects Ch0 recovered clock. LOW
selects Ch1 clock.
PRBSCHKCLKSEL
RSVD
1:1
7:2
4:0
7:5
4:0
RW
RW
RW
RW
RW
0
0-1
0-63
0-31
0-7
000111
10011
000
Reserved. Do not change.
Adjusts LBW positive temperature coefficient
control.
CH0PLLLBWCURVT
RSVD
CH0PLL_REG1
CH0PLL_REG2
10
11
Reserved. Do not change.
Adjusts LBW negative temperature coefficient
control.
CH0PLLLBWCURVBE
01110
0-31
RSVD
7:5
1:0
3:2
7:4
7:0
RW
RW
RW
RW
RW
000
01
0-7
0-3
Reserved. Do not change.
Reserved. Do not change.
CH0PLL control current.
Reserved. Do not change.
Reserved. Do not change.
RSVD
RSVD
RSVD
12
13
CH0PLLCUR
RSVD
01
0-3
0000
00100000
0-15
RSVD
0-255
NOTE: * Indicates bits for lower data rates (below 10G operation)
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
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Table 7-1: Configuration and Status Register Map (Continued)
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
CH0PLLPOLINV
0:0
1:1
2:2
RW
RW
RW
0
0
1
0-1
0-1
0-1
When HIGH, inverts data path polarity.
When HIGH, forces CDR into bypass mode.
When HIGH, enables automatic bypass mode.
CH0PLLBYPASS
CH0PLLAUTOBYPASSEN
CH0PLL_REG5
14
Selects data rates:
CH0PLLRATESEL
3:3
4:4
RW
RW
1
1
0-1
0 = 1.25 - 8.5G, 1= 10.3G or 14.025G
When HIGH, CH0PLLRATESEL is valid, otherwise
it is ignored.
CH0PLLRATESELVAL
0-1
0-7
RSVD
RSVD
RSVD
RSVD
RSVD
7:5
7:0
7:0
7:0
5:0
RW
RW
RW
RW
RW
000
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
RSVD
RSVD
RSVD
15
16
17
00001010
00100000
00000101
000000
0-255
0-255
0-255
0-63
CH0PLL_REG9
CH0PLL_REG10
18
19
LBW multiplier:
00 = 0.67, 10 = 1, 01 = 1.33, 11 = 1.67
CH0PLLBWMULT
7:6
RW
10
0-3
CH0PLLLOS
CH0PLLLOL
RSVD
0:0
1:1
7:2
RO
RO
RW
0
0
0-1
0-1
Loss of signal when HIGH.
Loss of lock when HIGH.
Reserved. Do not change.
000000
0-63
Adjusts LBW positive temperature coefficient
control.
CH1PLLLBWCURVT
RSVD
4:0
7:5
4:0
RW
RW
RW
10011
000
0-31
0-7
CH1PLL_REG1
CH1PLL_REG2
20
21
Reserved. Do not change.
Adjusts LBW negative temperature coefficient
control.
CH1PLLLBWCURVBE
01110
0-31
RSVD
7:5
1:0
3:2
7:4
7:0
0:0
1:1
2:2
RW
RW
RW
RW
RW
RW
RW
RW
000
0-7
0-3
Reserved. Do not change.
RSVD
01
Reserved. Do not change.
CH1PLL_REG3
RSVD
22
23
CH1PLLCUR
RSVD
01
0-3
Ch1 PLL control current.
0000
0-15
0-255
0-1
Reserved. Do not change.
RSVD
00100000
Reserved. Do not change.
CH1PLLPOLINV
CH1PLLBYPASS
CH1PLLAUTOBYPASSEN
0
0
1
When HIGH, inverts data path polarity.
When HIGH, forces CDR into bypass mode.
When HIGH, enables automatic bypass mode.
0-1
0-1
CH1PLL_REG5
24
Selects data rates:
CH1PLLRATESEL
3:3
4:4
RW
RW
1
1
0-1
0-1
0 = 1.25 - 8.5G, 1 = 10.3G or 14.025G
When HIGH, CH1PLLRATESEL is valid.
Otherwise, it is ignored.
CH1PLLRATESELVAL
RSVD
RSVD
RSVD
RSVD
7:5
7:0
7:0
7:0
RW
RW
RW
RW
000
0-7
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
RSVD
RSVD
RSVD
25
26
27
00001010
00100000
00000101
0-255
0-255
0-255
NOTE: * Indicates bits for lower data rates (below 10G operation)
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
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Table 7-1: Configuration and Status Register Map (Continued)
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
RSVD
5:0
7:6
RW
RW
001000
10
0-63
0-3
Reserved. Do not change.
CH1PLL_REG9
28
LBW multiplier:
00 = 0.67, 10 = 1, 01 = 1.33, 11 = 1.67
CH1PLLBWMULT
CH1PLLLOS
CH1PLLLOL
RSVD
0:0
1:1
7:2
7:0
7:0
7:0
RO
RO
0
0-1
0-1
Loss of signal when HIGH.
Loss of lock when HIGH.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
CH1PLL_REG10
29
0
RW
RW
RW
RW
000000
00000000
00000000
00000000
0-63
RSVD
RSVD
RSVD
30
31
32
RSVD
0-255
0-255
0-255
RSVD
RSVD
When HIGH, applies fixed Ch0 equalizer boost
of 6dB. 0dB if LOW.
Valid for below 10G operation.
CH0EQBOOST*
CH0EQBOOST
0:0
1:1
RW
RW
1
1
0-1
0-1
CH0_REG3
33
When HIGH, applies a fixed Ch0 Equalizer
boost of 6dB, 0dB if LOW.
Valid for 10G to 14G operation.
RSVD
7:2
6:0
RW
RW
000000
0-63
Reserved. Do not change.
Offset correction. 63 for 0 correction
with +64/-63 steps.
CH0EQOFFOVRVAL
0111111
0-127
CH0_REG4
34
RSVD
RSVD
RSVD
RSVD
RSVD
7:7
7:0
7:0
7:0
7:0
RW
RW
RW
RW
RW
0
0-1
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
RSVD
RSVD
RSVD
RSVD
35
36
37
38
00000000
00000101
00000000
00000000
0-255
0-255
0-255
0-255
Negative temperature coefficient LOS
threshold setting.
CH0_REG9
39
40
CH0LOSTHNEG
CH0LOSTHPOS
7:0
7:0
RW
RW
01010011
00000000
0-255
0-255
Positive temperature coefficient LOS threshold
setting.
CH0_REG10
CH0LOSHYS
RSVD
3:0
7:4
2:0
3:3
RW
RW
RW
RW
1001
0000
000
0
0-15
0-15
0-7
0: minimum hysteresis, 15: maximum hysteresis.
Reserved. Do not change.
CH0_REG11
41
RSVD
Reserved. Do not change.
CH0LOSSOFTASSERT
0-1
When HIGH, does a software LOS assert.
CH0_REG12
CH0_REG13
42
43
When HIGH, selects software LOS. LOW selects
hardware LOS.
CH0LOSSOFTASSERTEN
RSVD
4:4
7:5
7:0
RW
RW
RW
0
0-1
0-7
000
Reserved. Do not change.
Vertical eye monitor threshold adjustment,
0-255.
CH0VEYETHADJ
00000000
0-255
Vertical eye monitor threshold polarity. HIGH is
positive.
CH0VEYETHPOL
0:0
1:1
RW
RW
0
0
0-1
0-1
When HIGH, reduces the range to
0-600mVppd.
CH0VEYELORANGE
CH0_REG14
44
CH0VEYEOFFCALEN
RSVD
2:2
7:3
RW
RW
0
0-1
Vertical eye monitor offset calibration enable.
Reserved. Do not change.
00000
0-31
NOTE: * Indicates bits for lower data rates (below 10G operation)
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
65 of 74
Proprietary & Confidential
55972 - 0
March 2012
Table 7-1: Configuration and Status Register Map (Continued)
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
Main power configuration register for the Ch0
path. Default is the high-power setting. Refer
to Section 2.4.
CH0PWR1
4:0
RW
01010
0-31
CH0_REG15
45
RSVD
RSVD
7:5
2:0
RW
RW
000
111
0-7
Reserved. Do not change.
Reserved. Do not change.
0-31
Secondary power configuration register for the
Ch0 path. Default is the high-power setting.
Refer to Section 2.4.
CH0_REG16
46
CH0PWR2
4:3
RW
01
0-3
0-1
RSVD
RSVD
7:5
7:0
RW
RW
000
Reserved. Do not change.
Reserved. Do not change.
RSVD
47
48
00000000
0-255
0-15
0-15
0-15
0: 0dB to 15: 14dB.
Valid for below 10G operation.
CH1LABOOST*
RSVD
3:0
7:4
3:0
RW
RW
RW
0000
0000
0000
CH1_REG1
Reserved. Do not change.
0: 0dB to 15: 14dB.
Valid for 10G to 14G operation.
CH1LABOOST
CH1_REG2
RSVD
49
50
51
RSVD
RSVD
7:4
7:0
RW
RW
0000
0-15
Reserved. Do not change.
Reserved. Do not change.
00000000
0-255
Offset correction. 63 for 0 correction with
+64/-63 steps.
CH1LAOFFOVRVAL
6:0
RW
0111111
0-127
CH1_REG4
RSVD
RSVD
RSVD
RSVD
RSVD
7:7
7:0
7:0
7:0
7:0
RW
RW
RW
RW
RW
0
0-1
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
RSVD
RSVD
RSVD
RSVD
52
53
54
55
00010000
00000000
00000000
00001010
0-255
0-255
0-255
0-255
Negative temperature coefficient LOS
threshold setting.
Valid for below 10G operation.
CH1_REG9
CH1_REG10
CH1_REG11
56
57
58
CH1LOSTHNEG*
CH1LOSTHPOS*
CH1LOSTHNEG
7:0
7:0
7:0
RW
RW
RW
10000011
00010001
10000011
0-255
0-255
0-255
Positive temperature coefficient LOS threshold
setting. Valid for below 10G operation.
Negative temperature coefficient LOS
threshold setting.
Valid for 10G to 14G operation.
Positive temperature coefficient LOS threshold
setting.
Valid for 10G to 14G operation.
CH1_REG12
CH1_REG13
59
60
CH1LOSTHPOS
7:0
RW
00010001
0-255
0: minimum hysteresis, 15: maximum hysteresis.
Valid for below 10G operation.
CH1LOSHYS*
CH1LOSHYS
3:0
7:4
RW
RW
1001
1001
0-15
0-15
0: minimum hysteresis, 15: maximum hysteresis.
Valid for 10G to 14G operation.
NOTE: * Indicates bits for lower data rates (below 10G operation)
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
66 of 74
Proprietary & Confidential
55972 - 0
March 2012
Table 7-1: Configuration and Status Register Map (Continued)
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
RW
Function
Reset Value
d
d
Address
Range
1:0 - LOS range 0: highest - 3: lowest, 2 (MSB)
unused. Valid for below 10G operation.
CH1LOSRANGE*
2:0
5:3
001
0-7
0-7
1:0 - LOS range 0: highest - 3: lowest, 2 (MSB)
unused.
CH1LOSRANGE
RW
001
Valid for 10G to 14G operation.
CH1_REG14
61
When HIGH, selects a software LOS. LOW
selects hardware LOS.
CH1LOSSOFTASSERT
CH1LOSSOFTASSERTEN
CH1VEYETHADJ
6:6
7:7
7:0
0:0
RW
RW
RW
RW
0
0-1
0-1
When HIGH, selects software LOS. LOW selects
hardware LOS.
0
00000000
0
Vertical eye monitor threshold adjustment,
0-255.
CH1_REG15
CH1_REG16
62
63
0-255
0-1
Vertical eye monitor threshold polarity. HIGH is
positive.
CH1VEYETHPOL
CH1VEYELORANGE
CH1VEYEOFFCALEN
RSVD
1:1
2:2
7:3
RW
RW
RW
0
0
0-1
0-1
When HIGH, reduces the range to 0-600mVppd
Vertical eye monitor offset calibration enable.
Reserved. Do not change.
00000
0-31
Main power configuration register for the Ch1
path. Default is the high-power setting. Refer
to Section 2.4.
CH1PWR1
4:0
RW
01010
0-31
CH1_REG17
64
RSVD
RSVD
7:5
4:0
RW
RW
000
0-7
Reserved. Do not change.
Reserved. Do not change.
11100
0-31
Secondary power configuration register for the
Ch1 path. Default is the high-power setting.
Refer to Section 2.4.
CH1_REG18
CH1_REG19
65
66
CH1PWR2
6:5
RW
00
0-3
RSVD
7:7
7:0
0:0
1:1
RW
RW
RW
RW
0
0-1
0-255
0-1
Reserved. Do not change.
RSVD
00000000
Reserved. Do not change.
CH0RATEDETRESET
CH0RATEDETEN
0
1
When HIGH, the rate detector is reset.
When HIGH, the rate detector is enabled.
0-1
When HIGH, the application is Fibre Channel,
when LOW the application is Ethernet.
CH0RDET_REG1
67
RATEDETFCGBEN
2:2
RW
1
0-1
RATEDETFCGBENVAL
RSVD
3:3
7:4
RW
RW
1
0-1
When HIGH, FCGBEn is valid.
Reserved. Do not change.
0000
0-15
Rate detector rate period (0.3µs to 13ms, 100µs
default).
CH0RATEDETRATEPER
3:0
RW
1000
0-15
CH0RDET_REG2
68
RSVD
7:4
7:0
7:0
7:0
0:0
1:1
7:2
RW
RW
RW
RW
RW
RW
RW
0000
00000000
00000000
00000000
0
0-15
0-255
0-255
0-255
0-1
Reserved. Do not change.
RSVD
RSVD
RSVD
69
70
71
RSVD
Reserved. Do not change.
RSVD
Reserved. Do not change.
RSVD
Reserved. Do not change.
CH1RATEDETRESET
CH1RATEDETEN
RSVD
When HIGH, the rate detector is reset.
When HIGH, the rate detector is enabled.
Reserved. Do not change.
CH1RDET_REG1
72
1
0-1
000000
0-63
NOTE: * Indicates bits for lower data rates (below 10G operation)
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
67 of 74
Proprietary & Confidential
55972 - 0
March 2012
Table 7-1: Configuration and Status Register Map (Continued)
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
Rate detector rate period (0.3µs to 13ms, 100µs
default).
CH1RATEDETRATEPER
3:0
RW
1000
0-15
0-15
CH1RDET_REG2
73
RSVD
RSVD
RSVD
RSVD
7:4
7:0
7:0
7:0
RW
RW
RW
RW
0000
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Driver swing.
RSVD
RSVD
RSVD
74
75
76
00000000
00000000
00000000
0-255
0-255
0-255
CH1SDOSWING*
CH1SDOSWING
3:0
7:4
1:0
RW
RW
RW
1010
1010
00
0-15
0-15
0-3
0-15: 100-850mVppd, default=10: 600mV.
Valid for below 10G operation.
CH1SDO_REG1
77
Driver swing.
0-15: 100-850mVppd, default=10: 600mV.
Valid for 10G to 14G operation.
Rise time control.
CH1SDOPERTCTRL*
0:18ps, 1 & 2:22ps, 3: 30ps for 450mVppd
swing. Valid for below 10G operation.
CH1SDO_REG2
78
Pre-emphasis amplitude.
CH1SDOPECTRL*
RSVD
4:2
7:5
RW
RW
000
000
0-7
0-7
0: 1.3dB, 7: 6dB for 450mVppd swing.
Valid for below 10G operation.
Reserved. Do not change.
Rise time control.
0:18ps, 1 & 2:22ps, 3: 30ps for 450mVppd
swing.
Valid for 10G to 14G operation.
CH1SDOPERTCTRL
CH1SDOPECTRL
1:0
4:2
RW
RW
00
0-3
Pre-emphasis amplitude.
000
0-31
0: 1.3dB, 7: 6dB for 450mVppd swing.
Valid for 10G to 14G operation.
CH1SDO_REG3
79
When HIGH, mutes driver and maintains
common mode when not in auto mute mode.
CH1SDOMUTE
5:5
6:6
7:7
RW
RW
RW
0
1
1
0-1
0-1
0-1
When HIGH, enables muting the driver upon
LOS.
CH1SDOAUTOMUTEEN
CH1SDOPWRDNONMUTE
When HIGH, enables power-down on mute for
output stage.
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
80
81
82
83
84
85
86
87
88
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
7:0
7:0
7:0
7:0
70
RW
RW
RW
RW
RW
RW
RW
RW
RW
0000000
0000000
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
00000000
00000100
00000010
00000100
10000010
00101111
01010000
7:5
7:0
7:0
7:0
Ch0 swing setting LSB. 0x0 = 0mVppd, 0xC8 =
400mVppd, 0x190 = 800mVppd swing.
Valid for below 10G operation.
SDO0_REG10
89
CH0SWINGSETLO
7:0
RW
00000000
0-255
NOTE: * Indicates bits for lower data rates (below 10G operation)
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
68 of 74
Proprietary & Confidential
55972 - 0
March 2012
Table 7-1: Configuration and Status Register Map (Continued)
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
Ch0 swing setting MSB. 0x0 = 0mVppd, 0xC8 =
400mVppd, 0x190 = 800mVppd swing.
Valid for below 10G operation.
CH0SWINGSETHI
1:0
RW
00
0-3
SDO0_REG11
90
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
7:2
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
2:0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
000000
00011111
00011111
00000000
00000000
00000000
00000000
00000000
11110000
01010101
00000000
000
0-63
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
91
92
93
94
95
96
97
98
99
100
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-7
When HIGH, mutes driver and maintains
common mode when not in auto mute mode.
CH0SDOMUTE
3:3
4:4
5:5
RW
RW
RW
0
1
1
0-1
0-1
0-1
When HIGH, enables muting the driver upon
LOS.
CH0SDO_REG25
101
CH0SDOAUTOMUTEEN
CH0SDOPWRDNONMUTE
When HIGH, enables power-down on mute for
output stage.
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
7:6
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
RW
RW
RW
RW
RW
RW
RW
RW
RW
00
0-3
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
102
103
104
105
106
107
108
109
00010011
00000000
00000000
00000010
00000100
10000010
00101111
01010000
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
Ch0 swing setting LSB. 0x0 = 0mVppd, 0xC8 =
400mVppd, 0x190 = 800mVppd swing.
Valid for 10G to 14G operation.
SDO0_REG34
SDO0_REG35
110
111
CH0SWINGSETLO
CH0SWINGSETHI
7:0
1:0
RW
RW
00000000
00
0-255
0-3
Ch0 swing setting MSB. 0x0 = 0mVppd, 0xC8 =
400mVppd, 0x190 = 800mVppd swing.
Valid for 10G to 14G operation.
RSVD
RSVD
RSVD
RSVD
7:2
7:0
7:0
7:0
RW
RW
RW
RW
000000
0-63
0-255
0-255
0-255
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
RSVD
RSVD
RSVD
112
113
114
00000000
00000000
00000000
NOTE: * Indicates bits for lower data rates (below 10G operation)
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
69 of 74
Proprietary & Confidential
55972 - 0
March 2012
Table 7-1: Configuration and Status Register Map (Continued)
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
0:0
5:1
6:6
7:7
7:0
7:0
7:0
7:0
7:0
4:0
5:5
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
00000000
00000000
11110000
11111010
11111010
00000001
01010000
01010000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
1
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-255
0-1
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Enable all Ch0 Faults.
CH0FAULTEN
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RSVD
01111
0-31
Reserved. Do not change.
When HIGH, clears the latched Ch0 fault status.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Hardware Fault mask.
CH0FLT_REG1
134
CH0FAULTCLEARSTATUS
0
0-1
RSVD
0
0-1
RSVD
RSVD
RSVD
RSVD
RSVD
135
136
137
138
139
RSVD
00000000
11111111
11111111
11111111
00001111
00000
0-255
0-255
0-255
0-255
0-255
0-31
RSVD
RSVD
RSVD
RSVD
RSVD
CH0FAULTMUTE
RO
0
0-1
CH0FLT_REG7
140
141
Latched signal from CH0FAULT output pin of
Ch0Fault.
CH0FAULTCH0FAULT
6:6
RO
0
0-1
RSVD
RSVD
7:7
7:0
RW
RW
0
0-1
Reserved. Do not change.
Reserved. Do not change.
RSVD
00000000
0-255
NOTE: * Indicates bits for lower data rates (below 10G operation)
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
70 of 74
Proprietary & Confidential
55972 - 0
March 2012
Table 7-1: Configuration and Status Register Map (Continued)
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
ADCRESET
0:0
1:1
RW
RW
1
1
0-1
0-1
Reset for the ADC.
When HIGH, enables auto conversion. Set LOW
for manual.
ADCAUTOCONVEN
ADCJUSTLSB
When HIGH, justify towards LSB. LOW justifies
towards MSB.
2:2
3:3
RW
RW
1
0
0-1
0-1
ADC_REG0
142
When LOW, offset is subtracted from the ADC
output. When HIGH, offset is added to the ADC
output.
ADCOFFMODE
NOTE: When HIGH, ADCOFFSETHI[7] is sign and
rest of the bits are magnitude. A sign value of 1
represents negative numbers.
RSVD
7:4
3:0
7:4
2:0
5:3
7:6
0:0
7:1
0:0
7:1
7:0
7:0
7:0
7:0
RW
RW
RW
RW
RW
RW
RW
RW
RO
0000
0000
0-15
0-15
0-15
0-7
Reserved. Do not change.
ADCSRCSEL
ADCOFFCALEN
ADCRESOLUTION
ADCCLKRATE
RSVD
Select input for ADC (see Section 3.7.1).
Select source for offset calibration.
ADC resolution control: 0-7 -> 4b to 16b.
ADC clock divide ratio.
ADC_REG1
ADC_REG2
143
144
0000
001
101
0-7
00
0-3
Reserved. Do not change.
ADCSTARTCONV
RSVD
0
0-1
ADC start conversion.
ADC_REG3
ADC_REG4
145
146
0000000
0
0-127
0-1
Reserved. Do not change.
ADCDONECONV
RSVD
ADC conversion done flag.
Reserved. Do not change.
RW
RO
0000000
00000000
00000000
00000000
00000000
0-127
0-255
0-255
0-255
0-255
ADC_REG5
ADC_REG6
ADC_REG7
ADC_REG8
147
148
149
150
ADCOUTLO
ADCOUTHI
ADCOFFSETLO
ADCOFFSETHI
ADC output LOW MSB.
RO
ADC output HIGH MSB.
RW
RW
ADC offset LSB, unsigned binary.
ADC offset MSB, unsigned binary
When HIGH, power-down for the entire Ch0
path.
CH0PDCH0PATH
CH0PDCH0CDR*
CH0PDCH0CDR
0:0
1:1
2:2
RW
RW
RW
0
0
0
0-1
0-1
When HIGH, power-down for the entire CDR.
Valid for below 10G operation.
CH0PWRDN_REG1
151
When HIGH, power-down for the entire CDR.
Valid for 10G to 14G operation.
CH0PDCH0SDO
RSVD
3:3
7:4
0:0
1:1
7:2
RW
RW
RW
RW
RW
1
0010
0
0-1
0-15
0-1
When HIGH, power-down for the entire driver.
Reserved. Do not change.
CH0PDEQ
CH0PDLOS
RSVD
When HIGH, power-down for the equalizer.
When HIGH, power-down for the LOS.
Reserved. Do not change.
CH0PWRDN_REG2
152
0
0-1
100000
0-63
NOTE: * Indicates bits for lower data rates (below 10G operation)
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
71 of 74
Proprietary & Confidential
55972 - 0
March 2012
Table 7-1: Configuration and Status Register Map (Continued)
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
CH0PDRATEDET
0:0
1:1
RW
RW
1
1
0-1
0-1
When HIGH, power-down for rate detector.
When HIGH, power-down for the Ch0 vertical
eye monitor.
CH0PDVEYEMON
CH0PDHEYEMON
When HIGH, power-down for the Ch0
horizontal eye monitor.
2:2
RW
1
0-1
CH0PWRDN_REG3
153
When HIGH, power-down for the Ch0 peak
detector.
CH0PDPKDET
RSVD
3:3
4:4
5:5
RW
RW
RW
1
1
1
0-1
0-1
0-1
0-3
Reserved. Do not change.
When HIGH, power-down for the divided Ch0
clock divider.
CH0PDCKDIVOUT
RSVD
RSVD
7:6
7:0
RW
RW
01
Reserved. Do not change.
Reserved. Do not change.
RSVD
154
155
00001111
0-255
0-1
When HIGH, power-down for the entire Ch1
path.
CH1PDCH1PATH
CH1PDCH1CDR*
CH1PDCH1CDR
0:0
1:1
2:2
RW
RW
RW
0
0
0
When HIGH, power-down for the entire CDR.
Valid for below 10G operation.
0-1
0-1
CH1PWRDN_REG0
When HIGH, power-down for the entire CDR.
Valid for 10G to 14G operation.
CH1PDCH1SDO
RSVD
3:3
7:4
7:0
0:0
1:1
2:2
7:3
0:0
RW
RW
RW
RW
RW
RW
RW
RW
0
0-1
0-15
0-255
0-1
When HIGH, power-down the trace driver.
Reserved. Do not change.
0001
CH1PWRDN_REG1
CH1PWRDN_REG2
156
157
RSVD
00000000
Reserved. Do not change.
CH1PDLA
RSVD
0
When HIGH, power-down for the LA.
Reserved. Do not change.
1
0-1
CH1PDLOS
RSVD
0
00000
1
0-1
When HIGH, power-down for the LOS.
Reserved. Do not change.
0-31
0-1
CH1PDRATEDET
When HIGH, power-down for rate detector.
When HIGH, power-down for the Ch1 vertical
eye monitor.
CH1PDVEYEMON
CH1PDHEYEMON
CH1PDPKDET
1:1
2:2
3:3
4:4
5:5
RW
RW
RW
RW
RW
1
1
1
1
1
0-1
0-1
0-1
0-1
0-1
When HIGH, power-down for the Ch1
horizontal eye monitor.
When HIGH, power-down for the Ch0 peak
detector.
CH1PWRDN_REG3
158
When HIGH, power-down for the delay
monitor.
CH1PDDELMON
CH1PDCKDIVOUT
When HIGH, power-down for the divided Ch1
clock divider.
RSVD
RSVD
RSVD
7:6
7:0
7:0
RW
RW
RW
01
0-3
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
RSVD
RSVD
159
160
00001111
00011111
0-255
0-255
NOTE: * Indicates bits for lower data rates (below 10G operation)
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
72 of 74
Proprietary & Confidential
55972 - 0
March 2012
Table 7-1: Configuration and Status Register Map (Continued)
Register
Valid
Bit
Position
b
Register Name
Parameter Name
Access
Function
Reset Value
d
d
Address
Range
RSVD
0:0
1:1
RW
RW
1
1
0-1
0-1
Reserved. Do not change.
When HIGH, power-down the PRBS generator
and associated buffers.
PDPRBSGEN
When HIGH, power-down the PRBS checker
and associated buffers.
PDPRBSCHK
2:2
3:3
RW
RW
1
1
0-1
0-1
PWRDN_REG2
161
When HIGH, power-down the temperature
sensor(s).
PDTEMPSENSOR
PDSUPPLYSENSOR
PDADC
4:4
5:5
7:6
7:0
RW
RW
RW
RW
1
1
0-1
0-1
0-3
When HIGH, power-down the supply sensor.
When HIGH, power-down the ADC.
Reserved. Do not change.
RSVD
00
N/A
RSVD
162 to 195
RSVD
0-255
Reserved. Do not change.
NOTE: * Indicates bits for lower data rates (below 10G operation)
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
73 of 74
Proprietary & Confidential
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March 2012
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DATA SHEET
The product is in production. Gennum reserves the right to make changes to
the product at any time without notice to improve reliability, function or
design, in order to provide the best product possible.
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A
STATIC-FREE WORKSTATION
Phone: +1 (905) 632-2996
E-mail: sales@gennum.com
Fax: +1 (905) 632-2055
www.gennum.com
GENNUM CORPORATE HEADQUARTERS
4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada
CANADA
JAPAN KK
TAIWAN
Suite 320, 3553 31st St. N.W.
Calgary, Alberta T2L 2K7
Canada
Shinjuku Green Tower Building 27F
6-14-1, Nishi Shinjuku
Shinjuku-ku, Tokyo, 160-0023
Japan
6F-4, No.51, Sec.2, Keelung Rd.
Sinyi District, Taipei City 11502
Taiwan R.O.C.
Phone: +1 (403) 284-2672
Fax: +1 (905) 632-2055
Phone: (886) 2-8732-8879
Fax: (886) 2-8732-8870
E-mail: gennum-taiwan@gennum.com
Phone: +81 (03) 3349-5501
Fax: +81 (03) 3349-5505
415 Legget Drive, Suite 200
Kanata, Ontario K2K 2B2
Canada
E-mail: gennum-japan@gennum.com
UNITED KINGDOM
South Building, Walden Court
Parsonage Lane,
Bishop’s Stortford Hertfordshire, CM23 5DB
United Kingdom
Web Site: http://www.gennum.co.jp
MEXICO
Phone: +1 (613) 270-0458
Fax: +1 (613) 270-0429
Venustiano Carranza 122 Int. 1
Centro, Aguascalientes
Mexico CP 20000
GERMANY
Phone: +44 1279 714170
Fax: +44 1279 714171
Gennum Canada Limited
Niederlassung Deutschland
München, Germany
Phone: +1 (416) 848-0328
2, West Point Court, Great Park Road
Bradley Stoke, Bristol BS32 4PY
Great Britain
NORTH AMERICA WESTERN REGION
691 South Milpitas Blvd., Suite #200
Milpitas, CA 95035
Phone: +49 89 309040 290
Fax: +49 89 309040 293
E-mail: gennum-germany@gennum.com
United States
Phone: +44 1454 462200
Fax: +44 1454 462201
Phone: +1 (408) 934-1301
Fax: +1 (408) 934-1029
E-mail: naw_sales@gennum.com
INDIA
SNOWBUSH IP - A DIVISION OF GENNUM
#208(A), Nirmala Plaza,
Airport Road, Forest Park Square
Bhubaneswar 751009
India
439 University Ave. Suite 1700
Toronto, Ontario M5G 1Y8
Canada
NORTH AMERICA EASTERN REGION
4281 Harvester Road
Burlington, Ontario L7L 5M4
Canada
Phone: +91 (674) 65304815
Fax: +91 (674) 259-5733
Phone: +1 (416) 925-5643
Fax: +1 (416) 925-0581
E-mail: sales@snowbush.com
Phone: +1 (905) 632-2996
Fax: +1 (905) 632-2055
E-mail: nae_sales@gennum.com
Web Site: http://www.snowbush.com
Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of
the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent
infringement.
All other trademarks mentioned are the properties of their respective owners.
GENNUM and the Gennum logo are registered trademarks of Gennum Corporation.
© Copyright 2011 Gennum Corporation. All rights reserved.
www.gennum.com
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
74 of 74
74
Proprietary & Confidential
55972 - 0
March 2012
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