GD25LQ32DSJG [GIGADEVICE]
1.8V Uniform Sector Dual and Quad Serial Flash;
| 型号： | GD25LQ32DSJG |
| 厂家： | 
GigaDevice |
| 描述： | 1.8V Uniform Sector Dual and Quad Serial Flash |
| 文件： | 总72页 (文件大小：1402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
GD25LQ32D
DATASHEET
1
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
Contents
1. FEATURES .........................................................................................................................................................4
2. GENERAL DESCRIPTION................................................................................................................................5
3. MEMORY ORGANIZATION...............................................................................................................................7
4. DEVICE OPERATION ........................................................................................................................................8
5. DATA PROTECTION..........................................................................................................................................9
6. STATUS REGISTER.........................................................................................................................................11
7. COMMANDS DESCRIPTION..........................................................................................................................13
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
WRITE ENABLE (WREN) (06H)................................................................................................................................ 17
WRITE DISABLE (WRDI) (04H) ................................................................................................................................ 18
WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ................................................................................................. 19
READ STATUS REGISTER (RDSR) (05H OR 35H OR 15H) .............................................................................................. 20
WRITE STATUS REGISTER (WRSR) (01H)................................................................................................................... 21
READ DATA BYTES (READ) (03H)............................................................................................................................. 22
READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH).............................................................................................. 22
FAST READ (0BH) IN QPI MODE ............................................................................................................................... 23
DUAL OUTPUT FAST READ (3BH).............................................................................................................................. 23
7.10. QUAD OUTPUT FAST READ (6BH)............................................................................................................................. 24
7.11. DUAL I/O FAST READ (BBH).................................................................................................................................... 24
7.12. QUAD I/O FAST READ (EBH) ................................................................................................................................... 26
7.13. QUAD I/O WORD FAST READ (E7H) ......................................................................................................................... 28
7.14. SET BURST WITH WRAP (77H) ................................................................................................................................. 29
7.15. PAGE PROGRAM (PP) (02H).................................................................................................................................... 30
7.16. QUAD PAGE PROGRAM (32H).................................................................................................................................. 31
7.17. SECTOR ERASE (SE) (20H)....................................................................................................................................... 33
7.18. 32KB BLOCK ERASE (BE) (52H)............................................................................................................................... 34
7.19. 64KB BLOCK ERASE (BE) (D8H)............................................................................................................................... 35
7.20. CHIP ERASE (CE) (60/C7H)..................................................................................................................................... 36
7.21. DEEP POWER-DOWN (DP) (B9H)............................................................................................................................. 37
7.22. RELEASE FROM DEEP POWER-DOWN AND READ DEVICE ID (RDI) (ABH) ......................................................................... 38
7.23. READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ................................................................................................... 40
7.24. READ MANUFACTURE ID/ DEVICE ID DUAL I/O (92H) ................................................................................................. 41
7.25. READ MANUFACTURE ID/ DEVICE ID QUAD I/O (94H)................................................................................................. 42
7.26. READ IDENTIFICATION (RDID) (9FH)......................................................................................................................... 43
7.27. PROGRAM/ERASE SUSPEND (PES) (75H)...................................................................................................................44
7.28. PROGRAM/ERASE RESUME (PER) (7AH) ................................................................................................................... 45
7.29. READ UNIQUE ID (4BH).......................................................................................................................................... 46
7.30. ERASE SECURITY REGISTERS (44H) ............................................................................................................................ 46
7.31. PROGRAM SECURITY REGISTERS (42H)....................................................................................................................... 47
2
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.32. READ SECURITY REGISTERS (48H) ............................................................................................................................. 48
7.33. SET READ PARAMETERS (C0H) ................................................................................................................................. 49
7.34. BURST READ WITH WRAP (0CH)............................................................................................................................... 50
7.35. ENABLE QPI (38H)................................................................................................................................................. 50
7.36. DISABLE QPI (FFH) ................................................................................................................................................ 51
7.37. ENABLE RESET (66H) AND RESET (99H)..................................................................................................................... 52
8. LECTRICAL CHARACTERISTICS.................................................................................................................53
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
POWER-ON TIMING................................................................................................................................................ 53
INITIAL DELIVERY STATE ........................................................................................................................................... 53
ABSOLUTE MAXIMUM RATINGS................................................................................................................................. 53
CAPACITANCE MEASUREMENT CONDITIONS................................................................................................................. 54
DC CHARACTERISTICS......................................................................................................................................... 55
AC CHARACTERISTICS......................................................................................................................................... 58
9. ORDERING INFORMATION............................................................................................................................62
9.1.
10.
VALID PART NUMBERS ............................................................................................................................................ 63
PACKAGE INFORMATION .........................................................................................................................65
10.1. PACKAGE SOP8 208MIL ........................................................................................................................................ 65
10.2. PACKAGE VSOP8 208MIL ...................................................................................................................................... 66
10.3. PACKAGE USON8 (3*4MM).................................................................................................................................... 67
10.4. PACKAGE USON8 (4*4MM, THICKNESS 0.45MM) ...................................................................................................... 68
10.5. PACKAGE WSON8 (6*5MM)................................................................................................................................... 69
11.
REVISION HISTORY....................................................................................................................................70
3
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
1. FEATURES
◆ 32M-bit Serial Flash
- 4096K-Byte
◆ Fast Program/Erase Speed
- Page Program time: 0.7ms typical
- Sector Erase time: 90ms typical
- Block Erase time: 0.3/0.45s typical
- Chip Erase time: 20s typical
- 256 Bytes per programmable page
◆ Standard, Dual, Quad SPI, QPI
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
- Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
- QPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆ Flexible Architecture
- Uniform Sector of 4K-Byte
- Uniform Block of 32/64K-Byte
- Erase/Program Suspend/Resume
◆ High Speed Clock Frequency
◆ Low Power Consumption
- 120MHz for fast read with 30PF load
- Dual I/O Data transfer up to 240Mbits/s
- Quad I/O Data transfer up to 480Mbits/s
- QPI Mode Data transfer up to 480Mbits/s
- 35uA typical stand-by current
- 1μA typical power down current
◆ Advanced security Features
◆Allows XIP (execute in place) Operation
- 128-bit Unique ID for each device
- Continuous Read With 8/16/32/64-byte Wrap
- 3x1024-Byte Security Registers With OTP Lock
◆ Software/Hardware Write Protection
- Write protect all/portion of memory via software
- Enable/Disable protection with WP# Pin
- Top/Bottom Block protection
◆ Single Power Supply Voltage
- Full voltage range: 1.65~2.0V
◆ Minimum 100,000 Program/Erase Cycles
◆ Data Retention
- 20-year data retention typical
4
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
2. GENERAL DESCRIPTION
The GD25LQ32D (32M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI and QPI mode: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#).
The Dual I/O data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of
480Mbits/s.
CONNECTION DIAGRAM
CS#
1
2
3
4
8
7
6
5
VCC
CS#
1
2
3
8
7
VCC
SO
(IO1)
SO
(IO1)
HOLD#
(IO3)
HOLD#
(IO3)
Top View
Top View
WP#
(IO2)
WP#
(IO2)
SCLK
6 SCLK
SI
(IO0)
SI
5
VSS
VSS 4
(IO0)
8–LEAD
USON/WSON
8–LEAD SOP
PIN DESCRIPTION
Pin Name
CS#
I/O
Description
I
Chip Select Input
SO (IO1)
WP# (IO2)
VSS
I/O
I/O
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
SI (IO0)
SCLK
I/O
I
Data Input (Data Input Output 0)
Serial Clock Input
HOLD# (IO3)
VCC
I/O
Hold Input (Data Input Output 3)
Power Supply
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
5
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
BLOCK DIAGRAM
Write Control
Logic
WP#(IO2)
Status
Register
Flash
Memory
High Voltage
Generators
HOLD#(IO3)
SCLK
SPI
Command &
Control Logic
Page Address
Latch/Counter
CS#
Column Decode And
256-Byte Page Buffer
SI(IO0)
SO(IO1)
Byte Address
Latch/Counter
6
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
3. MEMORY ORGANIZATION
GD25LQ32D
Each device has
Each block has
Each sector has
Each page has
4M
16K
64/32K
256/128
16/8
4K
16
-
256
bytes
pages
sectors
blocks
-
-
-
1024
64/128
-
-
UNIFORM BLOCK SECTOR ARCHITECTURE
GD25LQ32D 64K Bytes Block Sector Architecture
Block
Sector
Address range
1023
……
1008
1007
……
992
……
……
……
……
……
……
47
3FF000H
……
3FFFFFH
……
63
3F0000H
3EF000H
……
3F0FFFH
3EFFFFH
……
62
……
……
2
3E0000H
……
3E0FFFH
……
……
……
……
……
……
……
……
……
……
……
02F000H
……
02FFFFH
……
……
32
020000H
01F000H
……
020FFFH
01FFFFH
……
31
1
……
16
010000H
00F000H
……
010FFFH
00FFFFH
……
15
0
……
0
000000H
000FFFH
7
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
4. DEVICE OPERATION
SPI Mode
Standard SPI
The GD25LQ32D features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the
rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25LQ32D supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read”
(3BH and BBH) commands. These commands allow data to be transferred to or from the device at twice times the rate of
the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The GD25LQ32D supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”,
“Quad I/O Word Fast Read”, “Quad Page Program” (6BH, EBH, E7H, 32H) commands. These commands allow data to be
transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and
SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI
commands require the non-volatile Quad Enable bit (QE) in Status Register to be set.
QPI
The GD25LQ32D supports Quad Peripheral Interface (QPI) operations only when the device is switched from
Standard/Dual/Quad SPI mode to QPI mode using the “Enable the QPI (38H)” command. The QPI mode utilizes all four IO
pins to input the command code. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be
active at any given times. “Enable the QPI (38H)” and “Disable the QPI (FFH)” commands are used to switch between
these two modes. Upon power-up and after software reset using “”Reset (99H)” command, the default state of the device is
Standard/Dual/Quad SPI mode. The QPI mode requires the non-volatile Quad Enable bit (QE) in Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being
low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge
of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
8
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
5. DATA PROTECTION
The GD25LQ32D provide the following data protection methods:
◆
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
-Software reset (66H+99H)
-Erase Security Registers / Program Security Registers
Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the
memory array that can be read but not change.
◆
◆
◆
Hardware Protection Mode: WP# goes low to protect the writable bit of Status Register.
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command and reset command (66H+99H).
Table1. GD25LQ32D Protected area size (CMP=0)
Status Register Content
Memory Content
Addresses
BP4
X
BP3
X
BP2
0
BP1
0
BP0
0
Blocks
NONE
Density
NONE
64KB
Portion
NONE
NONE
0
0
0
0
1
63
3F0000H-3FFFFFH
3E0000H-3FFFFFH
3C0000H-3FFFFFH
380000H-3FFFFFH
300000H-3FFFFFH
200000H-3FFFFFH
000000H-00FFFFH
000000H-01FFFFH
000000H-03FFFFH
000000H-07FFFFH
000000H-0FFFFFH
000000H-1FFFFFH
000000H-3FFFFFH
3FF000H-3FFFFFH
3FE000H-3FFFFFH
3FC000H-3FFFFFH
3F8000H-3FFFFFH
3F8000H-3FFFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
0
0
0
1
0
62 to 63
60 to 63
56 to 63
48 to 63
32 to 63
128KB
256KB
512KB
1MB
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
2MB
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
1
0
1
0
1
0
1
1
0
1
X
0
1
0
1
0
0 to 1
0 to 3
0 to 7
0 to 15
0 to 31
0 to 63
63
64KB
128KB
256KB
512KB
1MB
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
2MB
4MB
4KB
Top Block
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
63
8KB
63
16KB
32KB
32KB
4KB
63
63
0
0
8KB
0
16KB
9
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
Bottom Block
1
1
1
1
1
0
X
0
000000H-007FFFH
32KB
32KB
1
1
0
0
000000H-007FFFH
Bottom Block
Table1a. GD25LQ32D Protected area size (CMP=1)
Memory Content
Status Register Content
BP4
X
BP3
X
BP2
0
BP1
0
BP0
0
Blocks
ALL
Addresses
Density
4MB
Portion
ALL
000000H-3FFFFFH
000000H-3EFFFFH
000000H-3DFFFFH
000000H-3BFFFFH
000000H-37FFFFH
000000H-2FFFFFH
000000H-1FFFFFH
0
0
0
0
1
0 to 62
0 to 61
0 to 59
0 to 55
0 to 47
0 to 31
4032KB
3968KB
3840KB
3584KB
3MB
Lower 63/64
Lower 31/32
Lower 15/16
Lower 7/8
Lower 3/4
Lower 1/2
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
2MB
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
1
0
1
0
1
1
0
1
X
0
1
0
1
X
0
1 to 63
2 to 63
4 to 63
8 to 63
16 to 63
32 to 63
NONE
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
0 to 63
010000H-3FFFFFH
020000H-3FFFFFH
040000H-3FFFFFH
080000H-3FFFFFH
100000H-3FFFFFH
200000H-3FFFFFH
NONE
4032KB
3968KB
3840KB
3584KB
3MB
Upper 63/64
Upper 31/32
Upper 15/16
Upper 7/8
Upper 3/4
Upper 1/2
NONE
2MB
NONE
000000H-3FEFFFH
000000H-3FDFFFH
000000H-3FBFFFH
000000H-3F7FFFH
000000H-3F7FFFH
001000H-3FFFFFH
002000H-3FFFFFH
004000H-3FFFFFH
008000H-3FFFFFH
008000H-3FFFFFH
4092KB
4088KB
4080KB
4064KB
4064KB
4092KB
4088KB
4080KB
4064KB
4064KB
L-1023/1024
L-511/512
L-255/256
L-127/128
L-127/128
U-1023/1024
U-511/512
U-255/256
U-127/128
U-127/128
10
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
6. STATUS REGISTER
S15
S14
S13
LB3
S12
LB2
S11
LB1
S10
S9
S8
SUS1
CMP
SUS2
QE
SRP1
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
BP4
BP3
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,
means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in
Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block
Protect (BP4, BP3, BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set.
The Chip Erase (CE) command is executed, if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block
Protect (BP2, BP1, and BP0) bits are 1 and CMP=1.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time
programmable protection.
SRP1 SRP0 #WP
Status Register
Description
The Status Register can be written to after a Write Enable
command, WEL=1.(Default)
0
0
0
1
0
1
1
0
1
X
0
Software Protected
WP#=0, the Status Register locked and cannot be written to.
Hardware Protected
Hardware Unprotected
Power Supply Lock-Down(1)(2)
One Time Program(2)
WP#=1, the Status Register is unlocked and can be written to
after a Write Enable command, WEL=1.
1
Status Register is protected and cannot be written to again
until the next Power-Down, Power-Up cycle.
Status Register is permanently protected and cannot be
written to.
X
X
1
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order. Please contact GigaDevice for details.
11
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When
the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3
pins are enabled. (It is best to set the QE bit to 0 to avoid short issues if the WP# or HOLD# pin is tied directly to the power
supply or ground.)
LB3, LB2, LB1 bits.
The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the
write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are
unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One
Time Programmable, once they are set to 1, the Security Registers will become read-only permanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the BP4-BP0
bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details.
The default setting is CMP=0.
SUS1, SUS2 bits
The SUS1 and SUS2 bits are read only bits in the status register (S15 and S10) that are set to 1 after executing an
Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set
the SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command, software reset
(66H+99H) command as well as a power-down, power-up cycle.
12
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the
first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, with
most significant bit first on SI, and each bit is latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this might be
followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command
sequence has been completed. For the command of Read, Fast Read, Read Status Register or Release from Deep
Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read
instruction can be completed after any bit of the data-out sequence is being shifted out, and then CS# must be driven high
to return to deselected status.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the
command is rejected, and is not executed. That is CS# must be driven high when the number of clock pulses after CS#
being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will
happen and WEL will not be reset.
Table2. Commands (Standard/Dual/Quad SPI)
Command Name
Byte 1
06H
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
Write Enable
Write Disable
Volatile SR
04H
50H
Write Enable
Read Status Register
Read Status
Register-1
05H
35H
(S7-S0)
(S15-S8)
S7-S0
(continuous)
(continuous)
Write Status Register
Read Data
01H
03H
0BH
3BH
S15-S8
A23-A16 A15-A8
A23-A16 A15-A8
A23-A16 A15-A8
A7-A0
A7-A0
A7-A0
(D7-D0)
dummy
dummy
(Next byte)
(D7-D0)
(D7-D0)(1)
(continuous)
(continuous)
(continuous)
Fast Read
Dual Output
Fast Read
Dual I/O
Fast Read
BBH
6BH
EBH
E7H
A23-A8(2) A7-A0
M7-M0(2)
(D7-D0)(1)
A7-A0
(continuous)
(continuous)
(continuous)
(continuous)
Quad Output
Fast Read
A23-A16 A15-A8
dummy
(D7-D0)(3)
Quad I/O
Fast Read
A23-A0
M7-M0(4)
A23-A0
M7-M0(4)
dummy(5)
dummy(6)
(D7-D0)(3)
(D7-D0)(3)
Quad I/O Word
Fast Read(7)
Page Program
Quad Page Program
Sector Erase
Block Erase(32K)
Block Erase(64K)
Chip Erase
02H
32H
20H
52H
D8H
C7/60H
38H
66H
99H
77H
A23-A16 A15-A8
A23-A16 A15-A8
A23-A16 A15-A8
A23-A16 A15-A8
A23-A16 A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
D7-D0
D7-D0
Next byte
Enable QPI
Enable Reset
Reset
Set Burst with Wrap
W6-W4
13
1.8V Uniform Sector
Dual and Quad Serial Flash
75H
GD25LQ32D
Program/Erase
Suspend
Program/Erase
Resume
7AH
Release From Deep
Power-Down, And
Read Device ID
Release From Deep
Power-Down
ABH
ABH
dummy
dummy
dummy
(ID7-ID0)
(M7-M0)
(continuous)
Deep Power-Down
Manufacturer/
Device ID
B9H
90H
dummy
A23-A8
dummy
00H
(ID7-ID0)
(continuous)
(continuous)
(continuous)
Manufacturer/
Device ID by Dual I/O
Manufacturer/
Device ID by Quad
I/O
A7-A0,
M[7:0]
dummy
(M7-M0)
(ID7-ID0)
92H
94H
A23-A0,
M[7:0]
(M7-M0)
(ID7-ID0)
Read Identification
Read Unique ID
9FH
4BH
44H
(M7-M0)
00H
(ID15-ID8) (ID7-ID0)
(continuous)
(continuous)
00H
00H
dummy
(UID7-UID0)
Erase Security
Registers(8)
A23-A16 A15-A8
A23-A16 A15-A8
A23-A16 A15-A8
A7-A0
Program Security
Registers(8)
42H
48H
A7-A0
A7-A0
D7-D0
D7-D0
Read Security
Registers(8)
dummy
(D7-D0)
Table2a. Commands (QPI)
Command Name
Byte 1
(0,1)
06H
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Clock Number
(2,3)
(4,5)
(6,7)
(8,9)
(10,11)
(12,13)
Write Enable
Volatile SR Write Enable
Write Disable
50H
04H
Read Status Register
Read Status Register-1
Read Status Register-2
Write Status Register
Page Program
05H
(S7-S0)
(S15-S8)
(S1-S0)
S7-S0
35H
15H
01H
S15-S8
A15-A8
A15-A8
A15-A8
A15-A8
02H
A23-A16
A23-A16
A23-A16
A23-A16
A7-A0
A7-A0
A7-A0
A7-A0
D7-D0
Next byte
Sector Erase
20H
Block Erase(32K)
Block Erase(64K)
Chip Erase
52H
D8H
C7/60H
75H
Program/Erase Suspend
Program/Erase Resume
Deep Power-Down
Set Read Parameters
Fast Read
7AH
B9H
C0H
0BH
0CH
EBH
ABH
P7-P0
A23-A16
A23-A16
A23-A16
dummy
A15-A8
A15-A8
A15-A8
dummy
A7-A0
A7-A0
A7-A0
dummy
dummy
dummy
M7-M0
dummy
dummy
dummy
(D7-D0)
(D7-D0)
(D7-D0)
Burst Read with Wrap
Quad I/O Fast Read
Release From Deep
Power-Down, And
Read Device ID
(ID7-ID0)
Manufacturer/
Device ID
90H
dummy
dummy
00H
(M7-M0)
(ID7-ID0)
14
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
Read Identification
Disable QPI
Enable Reset
Reset
9FH
FFH
66H
99H
(M7-M0)
(ID15-ID8) (ID7-ID0)
NOTE:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8
IO1 = A23, A21, A19, A17, A15, A13, A11, A9
A6, A4, A2, A0, M6, M4, M2, M0
A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3,…..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
6. Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x, D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
7. Fast Word Read Quad I/O Data: the lowest address bit must be 0.
8. Security Registers Address:
Security Register1: A23-A16=00H, A15-A10=000100b, A9-A0=Byte Address;
Security Register2: A23-A16=00H, A15-A10=001000b, A9-A0=Byte Address;
Security Register3: A23-A16=00H, A15-A10=001100b, A9-A0=Byte Address.
9. QPI Command, Address, Data input/output format:
CLK #0
1
2
3
4
5
6
7
8
9
10 11
IO0= C4, C0, A20, A16, A12, A8,
IO1= C5, C1, A21, A17, A13, A9,
A4, A0, D4, D0, D4, D0,
A5, A1, D5, D1, D5, D1
IO2= C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2
IO3= C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3
15
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
Table of ID Definitions:
GD25LQ32D
Operation Code
M7-M0
C8
ID15-ID8
ID7-ID0
16
9FH
90H
ABH
60
C8
15
15
16
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.1. Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL)
bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status
Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS#
goes low sending the Write Enable command CS# goes high.
Figure2. Write Enable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
06H
High-Z
SO
Figure2a. Write Enable Sequence Diagram (QPI)
CS#
0
1
SCLK
Command
06H
IO0
IO1
IO2
IO3
17
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence:
CS# goes low Sending the Write Disable command CS# goes high. The WEL bit is reset by following condition:
Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase,
Erase/Program Security Registers and Reset commands.
Figure3. Write Disable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
04H
High-Z
SO
Figure3a. Write Disable Sequence Diagram (QPI)
CS#
0
1
SCLK
Command
04H
IO0
IO1
IO2
IO3
18
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.3. Write Enable for Volatile Status Register (50H)
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the
system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or
affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command
must be issued prior to a Write Status Register command, and any other commands can't be inserted between them.
Otherwise, Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register
command will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the
volatile Status Register bit values.
Figure4. Write Enable for Volatile Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
Command(50H)
High-Z
SI
SO
Figure4a. Write Enable for Volatile Status Register Sequence Diagram (QPI)
CS#
0
1
SCLK
Command
50H
IO0
IO1
IO2
IO3
19
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.4. Read Status Register (RDSR) (05H or 35H or 15H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at
any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in
progress, it is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is
also possible to read the Status Register continuously. For command code “05H” / “35H”, the SO will output Status
Register bits S7~S0 / S15-S8. The command code “15H” only supports the QPI mode, the I/O0 will output Status Register
S1-S0. (For 120MHz Frequency, the 15H will better than 05H to check the WIP bit)
Figure5. Read Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
Command
05H or 35H
S7~S0 or S15~S8 out
S7~S0 or S15~S8 out
SO
High-Z
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure5a. Read Status Register Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
SCLK
IO0
Command
05H or 35H
4
5
0
1
2
3
4
5
6
7
0
1
4
5
6
7
IO1
IO2
IO3
6
2
7
3
S7-S0 or S15-S8 out
Figure5b. Read Status Register Sequence Diagram (QPI) (15H)
CS#
0
1
2
3
4
5
SCLK
Command
15H
S1
S0
S1
S0
IO0
S1-S0 out
IO1
IO2
IO3
20
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.5. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)
command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S15, S10, S1 and S0 of the Status Register. CS# must
be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register (WRSR)
command is not executed. If CS# is driven high after eighth bit of the data byte, the CMP and QE bits will be cleared to 0 in
SPI mode, while only CMP will be cleared to 0 in QPI mode. As soon as CS# is driven high, the self-timed Write Status
Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register
may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch
(WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3,
BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write
Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in
accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect
(WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is
not executed once the Hardware Protected Mode is entered.
Figure6. Write Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Status Register in
SCLK
Command
01H
SI
7
6
5
4
3
2
1
0
11 10 9
8
15 14 13 12
MSB
High-Z
SO
Figure6a. Write Status Register Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
SCLK
Command
01H
4
5
6
7
0
1
2
3
12
8
9
IO0
13
IO1
IO2
IO3
14 10
15 11
Status Register in
21
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.6. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit is latched-in on the
rising edge of SCLK. Then the memory content at that address is shifted out on SO, and each bit is shifted out, at a Max
frequency fR, on the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure7. Read Data Bytes Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI
Command
03H
24-bit address
23 22 21
MSB
3
2
1
0
Data Out1
Data Out2
High-Z
SO
7
6
5
4
3
2
1
0
MSB
7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte
address (A23-A0) and a dummy byte, and each bit is latched-in on the rising edge of SCLK. Then the memory content, at
that address, is shifted out on SO, and each bit is shifted out, at a Max frequency fC, on the falling edge of SCLK. The first
byte addressed can be at any location. The address is automatically incremented to the next higher address after each
byte of data is shifted out.
Figure8. Read Data Bytes at Higher Speed Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
0BH
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
22
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.8. Fast Read (0BH) in QPI mode
The Fast Read command is also supported in QPI mode. In QPI mode, the number of dummy clocks is configured by
the “Set Read Parameters (C0H)” command to accommodate a wide range application with different needs for either
maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting,
the number of dummy clocks can be configured as either 4/6/8.
Figure8a. Read Data Bytes at Higher Speed Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13
SCLK
IO0
Command
0BH
IOs switch from
Input to output
Dummy* Dummy*
A23-16 A15-8 A7-0
20 16 12
8
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
IO1
IO2
IO3
21 17 13
9
5
6
7
22 18 14 10
23 19 15 11
Byte1
*"Set Read Parameters" Command (C0H)
can set the number of dummy clocks
7.9. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit is
latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure9. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure9. Dual Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
3BH
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
SCLK
SI
6
4
2
0
6
4
2
0
6
7
Data Out1
Data Out2
SO
7
5
3
1
7
5
3
1
MSB
MSB
23
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.10. Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit is
latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1
and IO0. The command sequence is shown in followed Figure10. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit
(QE) of Status Register (S9) must be set to enable for the Quad Output Fast Read command.
Figure10. Quad Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
6BH
24-bit address
23 22 21
SI(IO0)
3
2
1
0
SO(IO1)
High-Z
High-Z
High-Z
WP#(IO2)
HOLD#(IO3)
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
SCLK
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Byte1 Byte2 Byte3 Byte4
7.11. Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input
the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, and each bit is latched in on
the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command
sequence is shown in followed Figure11. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read
Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next
Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The
command sequence is shown in followed Figure11a. If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the
next command requires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode”
Reset command can be used to reset (M5-4) before issuing normal command.
24
1.8V Uniform Sector
Dual and Quad Serial Flash
Figure11. Dual I/O Fast Read Sequence Diagram (M5-4≠ (1, 0))
GD25LQ32D
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
BBH
SI(IO0)
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
7
A23-16
A15-8
A7-0
M7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
SO(IO1)
Byte1
Byte2
Byte3
Byte4
Figure11a. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
6
4
2
0
6
4
2
0
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
7
5
3
1
7
5
3
1
7
A23-16
A15-8
A7-0
M7-0
CS#
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
SO(IO1)
Byte1
Byte2
Byte3
Byte4
25
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.12. Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the
3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, and
each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0,
IO1, IO2, IO3. The command sequence is shown in followed Figure12. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit
(QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command.
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read
Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next
Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The
command sequence is shown in followed Figure12a. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the
next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read Mode”
Reset command can be used to reset (M5-4) before issuing normal command.
Figure12. Quad I/O Fast Read Sequence Diagram (M5-4≠ (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
EBH
SI(IO0)
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SO(IO1)
5
6
7
WP#(IO2)
HOLD#(IO3)
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
Figure12a. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI(IO0)
4
0
4
0
4
0
4
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
SO(IO1)
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
WP#(IO2)
HOLD#(IO3)
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
26
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with
Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap
Around” feature for the following EBH commands. When “Wrap Around” is enabled, the data being accessed can be limited
to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the
command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning
boundary automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the
cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst
with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around”
operation while W6-W5 is used to specify the length of the wrap around section within a page.
Quad I/O Fast Read (EBH) in QPI mode
The Quad I/O Fast Read command is also supported in QPI mode. See Figure12b. In QPI mode, the number of
dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with
different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read
Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8. In QPI mode, the
“Continuous Read Mode” bits M7-M0 are also considered as dummy clocks. “Continuous Read Mode” feature is also
available in QPI mode for Quad I/O Fast Read command. “Wrap Around” feature is not available in QPI mode for Quad I/O
Fast Read command. To perform a read operation with fixed data length wrap around in QPI mode, a dedicated “Burst
Read with Wrap” (0CH) command must be used.
Figure12b. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0) QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCLK
IO0
Command
EBH
IOs switch from
Input to output
20 16 12
21 17 13
8
9
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
IO1
IO2
IO3
5
22 18 14 10
6
7
*"Set Read Parameters"
Command (C0H) can
set the number of
dummy clocks
23 19 15 11
A23-16 A15-8 A7-0
M7-0* dummy* Byte1 Byte2
27
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.13. Quad I/O Word Fast Read (E7H)
The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest
address bit (A0) must be equal 0 and there are only 2-dummy clocks. The command sequence is shown in followed
Figure13. The first byte addressed can be at any location. The address is automatically incremented to the next higher
address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for
the Quad I/O Word Fast read command.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then
the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command
code. The command sequence is shown in followed Figure13a. If the “Continuous Read Mode” bits (M5-4) do not equal to
(1, 0), the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read
Mode” Reset command can be used to reset (M5-4) before issuing normal command.
Figure13. Quad I/O Word Fast Read Sequence Diagram (M5-4≠ (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
E7H
SI(IO0)
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SO(IO1)
5
6
7
WP#(IO2)
HOLD#(IO3)
Dummy
A23-16 A15-8 A7-0 M7-0
Byte1 Byte2 Byte3
Figure13a. Quad I/O Word Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI(IO0)
4
0
4
0
4
0
4
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SO(IO1)
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
WP#(IO2)
HOLD#(IO3)
Dummy
A23-16 A15-8 A7-0 M7-0
Byte1 Byte2 Byte3
28
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set Burst
with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable or disable the
“Wrap Around” feature for the following E7H commands. When “Wrap Around” is enabled, the data being accessed can be
limited to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the
command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning
boundary automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the
cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst
with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around”
operation while W6-W5 is used to specify the length of the wrap around section within a page.
7.14. Set Burst with Wrap (77H)
The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word Fast Read”
command to access a fixed length of 8/16/32/64-byte section within a 256-byte page.
The Set Burst with Wrap command sequence: CS# goes low Send Set Burst with Wrap command Send 24
dummy bits Send 8 bits “Wrap bits” CS# goes high.
W4=0
W4=1 (default)
W6,W5
Wrap Around
Wrap Length
8-byte
Wrap Around
Wrap Length
0, 0
0, 1
1, 0
1, 1
Yes
Yes
Yes
Yes
No
No
No
No
N/A
N/A
N/A
N/A
16-byte
32-byte
64-byte
If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and “Quad I/O
Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the
“Wrap Around” function and return to normal read operation, another Set Burst with Wrap command should be issued to set
W4=1. In QPI mode, the “Burst Read with Wrap (0CH)” command should be used to perform the Read Operation with
“Wrap Around” feature. The Wrap Length set by W5-W6 in Standard SPI mode is still valid in QPI mode and can also be
re-configured by “Set Read Parameters (C0H) command.
Figure14. Set Burst with Wrap Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Command
77H
SI(IO0)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
5
6
x
x
x
x
x
SO(IO1)
x
x
x
WP#(IO2)
HOLD#(IO3)
W6-W4
29
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.15. Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address
bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data
that goes beyond the end of the current page are programmed from the start address of the same page (from the address
whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The
Page Program command sequence: CS# goes low sending Page Program command 3-byte address on SI at least
1 byte data on SI CS# goes high. The command sequence is shown in Figure15. If more than 256 bytes are sent to the
device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly
within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of
the last data byte has been latched in; otherwise the Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and
BP0) is not executed.
Figure15. Page Program Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI
Command
02H
24-bit address
23 22 21
MSB
Data Byte 1
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
30
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
Figure15a. Page Program Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13
SCLK
Command
02H
Byte1 Byte2
Byte3
Byte255 Byte256
A23-16 A15-8 A7-0
IO0
20 16 12
8
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO1
IO2
IO3
21 17 13
9
5
6
7
22 18 14 10
23 19 15 11
7.16. Quad Page Program (32H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. To use
Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The
quad Page Program command is entered by driving CS# Low, followed by the command code (32H), three address bytes
and at least one data byte on IO pins.
The command sequence is shown in Figure16. If more than 256 bytes are sent to the device, previously latched data
are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than
256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on
the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in;
otherwise the Quad Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the
Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) is not executed.
31
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
Figure16.Quad Page Program Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
32H
24-bit address
23 22 21
MSB
Byte1 Byte2
SI(IO0)
3
2
1
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Byte11Byte12
SCLK
Byte253
Byte256
SI(IO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
32
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.17. Sector Erase (SE) (20H)
The Sector Erase (SE) command is erased the all data of the chosen sector. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by
driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid
address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low sending Sector Erase command 3-byte address on SI
CS# goes high. The command sequence is shown in Figure17. CS# must be driven high after the eighth bit of the last
address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven
high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the
Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected
by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bit (see Table1&1a) is not executed.
Figure17. Sector Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
20H
24 Bits Address
23 22
MSB
2
1
0
Figure17a. Sector Erase Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
20H
A23-16 A12-8 A7-0
20 16 12
8
4
0
1
2
3
IO0
21 17 13
9
5
IO1
IO2
IO3
22 18 14 10
23 19 15 11
6
7
33
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.18. 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is
entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is
a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low sending 32KB Block Erase command 3-byte
address on SI CS# goes high. The command sequence is shown in Figure18. CS# must be driven high after the eighth
bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon
as CS# is driven high, the self-timed Block Erase cycle (whose duration is tSE) is initiated. While the Block Erase cycle is in
progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress
(WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which
is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
Figure18. 32KB Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
52H
24 Bits Address
23 22
MSB
2
1
0
Figure18a. 32KB Block Erase Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
52H
A23-16 A12-8 A7-0
20 16 12
8
4
0
1
2
3
IO0
21 17 13
9
5
IO1
IO2
IO3
22 18 14 10
23 19 15 11
6
7
34
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.19. 64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is
entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is
a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low sending 64KB Block Erase command 3-byte
address on SI CS# goes high. The command sequence is shown in Figure19. CS# must be driven high after the eighth
bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon
as CS# is driven high, the self-timed Block Erase cycle (whose duration is tSE) is initiated. While the Block Erase cycle is in
progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress
(WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which
is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
Figure19. 64KB Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
D8H
24 Bits Address
23 22
MSB
2
1
0
Figure19a. 64KB Block Erase Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
D8H
A23-16 A15-8
A7-0
IO0
20 16 12
8
4
0
1
2
3
21 17 13
9
IO1
IO2
IO3
5
6
7
22
14 10
18
23 19 15 11
35
1.8V Uniform Sector
Dual and Quad Serial Flash
Chip Erase (CE) (60/C7H)
GD25LQ32D
7.20.
The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS#
Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the
sequence.
The Chip Erase command sequence: CS# goes low sending Chip Erase command CS# goes high. The
command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the command code has been
latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase
cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to
check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)
bit is reset. The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or
the Block Protect (BP2, BP1, and BP0) bits are 1 and CMP=1. The Chip Erase (CE) command is ignored if one or more
sectors are protected.
Figure20. Chip Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
60H or C7H
Figure20a. Chip Erase Sequence Diagram (QPI)
CS#
0
1
SCLK
Instruction
C7H/60H
IO0
IO1
IO2
IO3
36
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.21. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode
(the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in
active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the
device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the
Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP)
command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down and Read Device ID (RDI) (ABH) or Enable Reset (66H) and Reset (99H) commands. These
commands can release the device from this mode. The Release from Deep Power-Down and Read Device ID (RDI)
command releases the device from deep power down mode , also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device is in the Standby Mode after
Power-Up.
The Deep Power-Down command sequence: CS# goes low sending Deep Power-Down command CS# goes
high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command code has
been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it
requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep
Power-Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects
on the cycle that is in progress.
Figure21. Deep Power-Down Sequence Diagram
CS#
tDP
0
1
2
3
4
5
6
7
SCLK
SI
Command
B9H
Stand-by mode Deep Power-down mode
Figure21a. Deep Power-Down Sequence Diagram (QPI)
CS#
tDP
0
1
SCLK
Command
B9H
IO0
IO1
IO2
IO3
Stand-by mode
Deep Power-down mode
37
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.22. Release from Deep Power-Down and Read Device ID (RDI) (ABH)
The Release from Power-Down and Read Device ID command is a multi-purpose command. It can be used to release
the device from the Power-Down state or obtain the devices electronic identification (ID) number.
To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the
instruction code “ABH” and driving CS# high as shown in Figure22. Release from Power-Down will take the time duration
of tRES1 (See AC Characteristics) before the device will resume normal operation and other command are accepted. The
CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the
CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure23. The Device ID value for the
GD25LQ32D is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The
command is completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the same
as previously described, and shown in Figure23, except that after CS# is driven high it must remain high for a time
duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other
command will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or
Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle.
Figure22. Release Power-Down Sequence Diagram
CS#
tRES1
0
1
2
3
4
5
6
7
SCLK
SI
Command
ABH
Deep Power-down mode
Stand-by mode
Figure22a. Release Power-Down Sequence Diagram (QPI)
CS#
tRES1
0
1
SCLK
Command
ABH
IO0
IO1
IO2
IO3
Deep Power-down mode
Stand-by mode
38
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
Figure23. Release Power-Down/Read Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38
SCLK
tRES2
Command
ABH
3 Dummy Bytes
23 22
MSB
SI
2
1
0
Device ID
SO
High-Z
7
6
5
4
3
2
1
0
MSB
Deep Power-down Mode Stand-by Mode
Figure23a. Release Power-Down/Read Device ID Sequence Diagram (QPI)
CS#
tRES2
0
1
2
3
4
5
6
7
8
SCLK
Command
ABH
IOs switch from
Input to Output
3 Dummy Bytes
IO0
4
5
0
1
2
3
IO1
IO2
IO3
6
7
Device
ID
Deep Power-down mode
Stand-by mode
39
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.23. Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit
address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of
SCLK with most significant bit (MSB) first as shown in Figure24. If the 24-bit address is initially set to 000001H, the Device
ID will be read first.
Figure24. Read Manufacture ID/ Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
24-bit address
23 22 21
SI
90H
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
Device ID
Manufacturer ID
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
Figure24a. Read Manufacture ID/ Device ID Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10
IOs switch from
SCLK
Command
90H
A7-0
(00H)
Input to Output
A23-16 A15-8
IO0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
12
8
4
5
6
7
20 16
IO1
IO2
IO3
1
2
3
9
1
2
3
21 17 13
18
14 10
15 11
22
23 19
Device
ID
MID
40
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.24. Read Manufacture ID/ Device ID Dual I/O (92H)
The Read Manufacturer/Device ID Dual I/O command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by dual I/O.
The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a 24-bit
address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of
SCLK with most significant bit (MSB) first as shown in Figure25. If the 24-bit address is initially set to 000001H, the Device
ID will be read first.
Figure25. Read Manufacture ID/ Device ID Dual I/O Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
92H
SI(IO0)
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
7
A23-16
A15-8
A7-0
M7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
MFR ID
(Repeat)
MFR ID
Device ID
Device ID
(Repeat)
MFR ID
(Repeat)
Device ID
(Repeat)
41
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.25. Read Manufacture ID/ Device ID Quad I/O (94H)
The Read Manufacturer/Device ID Quad I/O command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O.
The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a 24-bit
address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of
SCLK with most significant bit (MSB) first as shown in Figure26. If the 24-bit address is initially set to 000001H, the Device
ID will be read first.
Figure26. Read Manufacture ID/ Device ID Quad I/O Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
94H
SI(IO0)
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
5
6
7
WP#(IO2)
HOLD#(IO3)
MFR ID DID
A23-16 A15-8 A7-0 M7-0
Dummy
CS#
24 25 26 27 28 29 30 31
SCLK
SI(IO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
MFR ID DID
MFR ID DID
(Repeat()Repeat)
(Repeat()Repeat)
42
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.26. Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two
bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity
of the device in the second byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress,
is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be
issued while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This is
followed by the 24-bit device identification, stored in the memory. Each bit is shifted out on the falling edge of Serial Clock.
The command sequence is shown in Figure27. The Read Identification (RDID) command is terminated by driving CS# high
at any time during data output. When CS# is driven high, the device is in the Standby Mode. Once in the Standby Mode,
the device waits to be selected, so that it can receive, decode and execute commands.
Figure27. Read Identification ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
9FH
Manufacturer ID
7
6
5
4
3
2
1
0
SO
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
Memory Type ID15-ID8
Capacity ID7-ID0
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
Figure27a. Read Identification ID Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
SCLK
IOs switch from
Input to Output
Command
9FH
4
0
12
8
4
0
1
2
3
IO0
5
1
2
3
13
9
5
IO1
IO2
IO3
6
14 10
15 11
6
7
7
MID ID15-8 ID7-0
43
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.27. Program/Erase Suspend (PES) (75H)
The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase
operation and then read data from any other sector or block. The Write Status Register command (01H) and
Erase/Program Security Registers command (44H,42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page
Program command (02H, 32H) are not allowed during Program suspend. The Write Status Register command (01H) and
Erase Security Registers command (44H) and Erase commands (20H, 52H, D8H, C7H, 60H) are not allowed during
Erase suspend. Program/Erase Suspend is valid only during the page program or sector/block erase operation. A
maximum of time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation.
The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status
Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the
SUS2/SUS1 bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be
cleared from 1 to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1 immediately after Program/Erase Suspend.
A power-off during the suspend period will reset the device and release the suspend state. The command sequence is
show in Figure28.
Figure28. Program/Erase Suspend Sequence Diagram
CS#
0
1
2
3
4
5
6
7
tSUS
SCLK
SI
Command
75H
High-Z
SO
Accept read command
Figure28a. Program/Erase Suspend Sequence Diagram (QPI)
CS#
tSUS
0
1
SCLK
Command
75H
IO0
IO1
IO2
IO3
Accept Read
44
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.28. Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the program or sector/block erase operation after
a Program/Erase Suspend command. The Program/Erase Resume command will be accepted by the device only if the
SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register will be cleared
from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase
operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a
Program/Erase Suspend is active. The command sequence is show in Figure29.
Figure29. Program/Erase Resume Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
7AH
SO
Resume Erase/Program
Figure29a. Program/Erase Resume Sequence Diagram (QPI)
CS#
0
1
SCLK
Command
7AH
IO0
IO1
IO2
IO3
Resume previously suspended
program or Erase
45
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.29. Read Unique ID (4BH)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The
Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low sending Read Unique ID command 3-Byte Address
(000000H) Dummy Byte128bit Unique ID Out CS# goes high.
Figure30. Read Unique ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
24-bit address
Command
4BH
(000000H)
3
23 22 21
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
7.30. Erase Security Registers (44H)
The GD25LQ32D provides three 1024-byte Security Registers which can be erased and programmed individually.
These registers may be used by the system manufacturers to store security and other important information separately
from the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low sending Erase Security Registers command
3-byte address on SI CS# goes high. The command sequence is shown in Figure31. CS# must be driven high after the
eighth bit of the last address byte has been latched in; otherwise the Erase Security Registers command is not executed.
As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the
Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress
(WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security
Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set
to 1, the Security Registers will be permanently locked; the Erase Security Registers command will be ignored.
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-10
0 0
A9-0
Security Register #1
Security Register #2
Security Register #3
Don’t care
Don’t care
Don’t care
00H
0 0
00H
0 0
46
1.8V Uniform Sector
Dual and Quad Serial Flash
Figure31. Erase Security Registers command Sequence Diagram
GD25LQ32D
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
44H
24 Bits Address
23 22
MSB
2
1
0
7.31. Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. Each security register contains
four pages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch
(WEL) bit before sending the Program Security Registers command. The Program Security Registers command is entered
by driving CS# Low, followed by the command code (42H), three address bytes and at least one data byte on SI. As soon
as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the
Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in
Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0
when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program
Security Registers command will be ignored.
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-10
0 0
A9-0
Security Register #1
Security Register #2
Security Register #3
Byte Address
Byte Address
Byte Address
00H
0 0
00H
0 0
Figure32. Program Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
42H
24-bit address
23 22 21
MSB
Data Byte 1
SI
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
SI
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
47
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.32. Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-byte
address (A23-A0) and a dummy byte, and each bit is latched-in on the rising edge of SCLK. Then the memory content, at
that address, is shifted out on SO, and each bit is shifted out, at a Max frequency fC, on the falling edge of SCLK. The first
byte addressed can be at any location. The address is automatically incremented to the next higher address after each
byte of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H,
the command is completed by driving CS# high.
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-10
0 0
A9-0
Security Register #1
Security Register #2
Security Register #3
Byte Address
Byte Address
Byte Address
00H
0 0
00H
0 0
Figure33. Read Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
48H
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
48
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.33. Set Read Parameters (C0H)
In QPI mode the “Set Read Parameters (C0H)” command can be used to configure the number of dummy clocks for
“Fast Read (0BH)”, “Quad I/O Fast Read (EBH)” and “Burst Read with Wrap (0CH)” command, and to configure the
number of bytes of “Wrap Length” for the “Burst Read with Wrap (0CH)” command. The “Wrap Length” is set by W5-6 bit in
the “Set Burst with Wrap (77H)” command. This setting will remain unchanged when the device is switched from Standard
SPI mode to QPI mode.
Maximum Read Freq.
-40℃~105℃
-40℃~125℃
P5-P4
Dummy Clocks
P1-P0
Wrap Length
-40℃~85℃
0 0
0 1
1 0
1 1
4
4
6
8
80MHz
80MHz
60MHz
60MHz
70MHz
80MHz
0 0
0 1
1 0
1 1
8-byte
16-byte
32-byte
64-byte
108MHz
120MHz
Figure34. Set Read Parameters command Sequence Diagram
CS#
0
1
2
3
SCLK
Command
C0H
Read
Parameters
P4 P0
IO0
P5 P1
P6 P2
P7 P3
IO1
IO2
IO3
49
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.34. Burst Read with Wrap (0CH)
The “Burst Read with Wrap (0CH)” command provides an alternative way to perform the read operation with “Wrap
Around” in QPI mode. This command is similar to the “Fast Read (0BH)” command in QPI mode, except the addressing of
the read operation will “Wrap Around” to the beginning boundary of the “Wrap Around” once the ending boundary is
reached. The “Wrap Length” and the number of dummy clocks can be configured by the “Set Read Parameters (C0H)”
command.
Figure35. Burst Read with Wrap command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCLK
IO0
Command
0CH
IOs switch from
Input to output
20 16 12
21 17 13
8
9
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
IO1
IO2
IO3
5
6
7
22 18 14 10
23 19 15 11
A23-16 A15-8
Dummy*
A7-0
Byte1 Byte2
*"Set Read Parameters" Command (C0H)
can set the number of dummy clocks
7.35. Enable QPI (38H)
The device support both Standard/Dual/Quad SPI and QPI mode. The “Enable QPI (38H)” command can switch the
device from SPI mode to QPI mode. See the command Table 2a for all support QPI commands. In order to switch the
device to QPI mode, the Quad Enable (QE) bit in Status Register-1 must be set to 1 first, and “Enable QPI (38H)”
command must be issued. If the QE bit is 0, the “Enable QPI (38H)” command will be ignored and the device will remain in
SPI mode. When the device is switched from SPI mode to QPI mode, the existing Write Enable Latch and Program/Erase
Suspend status, and the Wrap Length setting will remain unchanged.
Figure36. Enable QPI mode command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
38H
50
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.36. Disable QPI (FFH)
To exit the QPI mode and return to Standard/Dual/Quad SPI mode, the “Disable QPI (FFH)” command must be
issued. When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch and Program/Erase
Suspend status, and the Wrap Length setting will remain unchanged.
Figure37. Disable QPI mode command Sequence Diagram
CS#
0
1
SCLK
Command
FFH
IO0
IO1
IO2
IO3
51
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
7.37. Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its
default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch
status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Deep Power Down Mode, Continuous
Read Mode bit setting (M7-M0) and Wrap Bit Setting (W6-W4).
The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in either SPI or QPI mode. The “Reset
(99H)” and the “Reset (99H)” command sequence is as followed: CS# goes low Sending Enable Reset command
CS# goes high CS# goes low Sending Reset command CS# goes high. Once the Reset command is accepted by
the device, the device will take approximately tRST =30μs / tRST_E =12ms to reset. During this period, no command will be
accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when
Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status
Register before issuing the Reset command sequence.
Figure38. Enable Reset and Reset command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCLK
SI
Command
66H
Command
99H
High-Z
SO
Figure39. Enable Reset and Reset command Sequence Diagram (QPI)
CS#
0
0
1
1
SCLK
Command
66H
Command
99H
IO0
IO1
IO2
IO3
52
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
8. LECTRICAL CHARACTERISTICS
8.1. Power-On Timing
Figure40. Power-On Timing Sequence Diagram
Vcc(max)
Vcc(min)
VWI
Chip Selection is not allowed
Device is fully
accessible
tVSL
Time
Table3. Power-Up Timing and Write Inhibit Threshold
Parameter
Symbol
tVSL
Min
1.8
Max
Unit
ms
VCC (min) To CS# Low
Write Inhibit Voltage
VWI
1
1.4
V
8.2. Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFH). The Status
Register contains 00H (all Status Register bits are 0).
8.3. Absolute Maximum Ratings
Parameter
Value
Unit
Ambient Operating Temperature
-40 to 85
-40 to 105
℃
-40 to 125
Storage Temperature
-65 to 150
℃
V
Applied Input/Output Voltage
Transient Input/Output Voltage (note: overshoot)
VCC
-0.6 to VCC+0.4
-2.0 to VCC+2.0
-0.6 to 2.5
V
V
53
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
Figure41. Input Test Waveform and Measurement Level
Maximum Negative Overshoot Waveform
20ns
Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
8.4. Capacitance Measurement Conditions
Symbol
CIN
Parameter
Min
Typ
Max
6
Unit
Conditions
Input Capacitance
pF
pF
pF
ns
V
VIN=0V
COUT
CL
Output Capacitance
8
VOUT=0V
Load Capacitance
30
Input Rise And Fall time
Input Pause Voltage
5
0.1VCC to 0.8VCC
0.2VCC to 0.7VCC
0.5VCC
Input Timing Reference Voltage
Output Timing Reference Voltage
V
V
Figure42. Input Test Waveform and Measurement Level
Input timing reference level
0.7VCC
Output timing reference level
0.5VCC
0.8VCC
0.1VCC
AC Measurement Level
0.2VCC
Note: Input pulse rise and fall time are<5ns
54
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
8.5. DC CHARACTERISTICS
(T= -40℃~85℃, VCC=1.65~2.0V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Standby Current
Test Condition
Min.
Typ.
Max.
±2
Unit.
μA
ILO
±2
μA
ICC1
CS#=VCC,
VIN=VCC or VSS
Deep Power-Down Current CS#=VCC,
VIN=VCC or VSS
35
1
50
μA
ICC2
8
μA
CLK=0.1VCC /
0.9VCC
15
13
20
mA
at 120MHz,
Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC /
0.9VCC
ICC3
Operating Current (Read)
Operating Current (PP)
18
mA
at 80MHz,
Q=Open(*1,*2,*4 I/O)
CS#=VCC
ICC4
ICC5
ICC6
ICC7
VIL
20
20
mA
mA
mA
mA
V
Operating Current (WRSR) CS#=VCC
Operating Current (SE)
Operating Current (BE)
Input Low Voltage
CS#=VCC
CS#=VCC
20
20
0.2VCC
VIH
Input High Voltage
0.7VCC
VCC-0.2
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL =100μA
IOH =-100μA
0.2
V
V
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
55
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
(T= -40℃~105℃, VCC=1.65~2.0V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Standby Current
Test Condition
Min.
Typ.
Max.
±2
Unit.
μA
ILO
±2
μA
ICC1
CS#=VCC,
VIN=VCC or VSS
Deep Power-Down Current CS#=VCC,
VIN=VCC or VSS
35
1
70
μA
ICC2
20
20
μA
CLK=0.1VCC /
0.9VCC
15
13
mA
at 80MHz,
Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC /
0.9VCC
ICC3
Operating Current (Read)
Operating Current (PP)
18
mA
at 60MHz,
Q=Open(*1,*2,*4 I/O)
CS#=VCC
ICC4
ICC5
ICC6
ICC7
VIL
25
25
mA
mA
mA
mA
V
Operating Current (WRSR) CS#=VCC
Operating Current (SE)
Operating Current (BE)
Input Low Voltage
CS#=VCC
CS#=VCC
25
25
0.2VCC
VIH
Input High Voltage
0.7VCC
VCC-0.2
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL =100μA
IOH =-100μA
0.2
V
V
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
56
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
(T= -40℃~125℃, VCC=1.65~2.0V)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Standby Current
Test Condition
Min.
Typ.
Max.
±2
Unit.
μA
ILO
±2
μA
ICC1
CS#=VCC,
VIN=VCC or VSS
Deep Power-Down Current CS#=VCC,
VIN=VCC or VSS
35
1
90
μA
ICC2
35
20
μA
CLK=0.1VCC /
0.9VCC
15
13
mA
at 80MHz,
Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC /
0.9VCC
ICC3
Operating Current (Read)
Operating Current (PP)
18
mA
at 60MHz,
Q=Open(*1,*2,*4 I/O)
CS#=VCC
ICC4
ICC5
ICC6
ICC7
VIL
25
25
mA
mA
mA
mA
V
Operating Current (WRSR) CS#=VCC
Operating Current (SE)
Operating Current (BE)
Input Low Voltage
CS#=VCC
CS#=VCC
25
25
0.2VCC
VIH
Input High Voltage
0.8VCC
VCC-0.2
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL =100μA
IOH =-100μA
0.2
V
V
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
57
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
8.6. AC CHARACTERISTICS
(T= -40℃~85℃, VCC=1.65~2.0V, CL=30pf)
Symbol
FC
Parameter
Min.
Typ.
Max.
120
80
Unit.
MHz
MHz
ns
Serial Clock Frequency For: all command except for 03H
Serial Clock Frequency For: Read (03H)
Serial Clock High Time
fR
tCLH
3.5
3.5
0.1
0.1
5
tCLL
Serial Clock Low Time
ns
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
V/ns
V/ns
ns
CS# Active Hold Time
5
ns
CS# Not Active Setup Time
5
ns
CS# Not Active Hold Time
5
ns
CS# High Time (Read/Write)
20
ns
Output Disable Time
6
ns
Output Hold Time
1.2
2
ns
Data In Setup Time
ns
Data In Hold Time
2
ns
Hold# Low Setup Time (Relative To Clock)
Hold# High Setup Time (Relative To Clock)
Hold# High Hold Time (Relative To Clock)
Hold# Low Hold Time (Relative To Clock)
Hold# Low To High-Z Output
5
ns
5
ns
5
ns
5
ns
6
6
7
6
ns
Hold# High To Low-Z Output
ns
Clock Low To Output Valid (CL = 30pF)
Clock Low To Output Valid (CL = 15pF)
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High To Deep Power-Down Mode
CS# High To Standby Mode Without Electronic Signature Read
CS# High To Standby Mode With Electronic Signature Read
CS# High To Next Command After Suspend
Latency Between Resume And Next Suspend
Write Status Register Cycle Time
CS# High To Next Command After Reset (Except From Erase)
CS# High To Next Command After Reset (From Erase)
Page Programming Time
ns
tCLQV
ns
tWHSL
tSHWL
tDP
20
ns
100
ns
20
20
20
20
μs
μs
μs
μs
μs
ms
μs
ms
ms
ms
s
tRES1
tRES2
tSUS
tRS
100
tW
5
35
30
tRST
tRST_E
tPP
12
0.7
90
2.4
500
0.8
1.2
40
tSE
Sector Erase Time
tBE1
tBE2
tCE
Block Erase Time (32K Bytes)
0.3
0.45
20
Block Erase Time (64K Bytes)
s
Chip Erase Time (GD25LQ32D)
s
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
58
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
(T= -40℃~105℃, VCC=1.65~2.0V, CL=30pf)
Symbol
FC
Parameter
Serial Clock Frequency For: all command except for 03H
Serial Clock Frequency For: Read (03H)
Serial Clock High Time
Min.
Typ.
Max.
80
Unit.
MHz
MHz
ns
fR
60
tCLH
4
4
tCLL
Serial Clock Low Time
ns
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
0.1
0.1
5
V/ns
V/ns
ns
CS# Active Hold Time
5
ns
CS# Not Active Setup Time
5
ns
CS# Not Active Hold Time
5
ns
CS# High Time (Read/Write)
20
ns
Output Disable Time
6
ns
Output Hold Time
1.2
2
ns
Data In Setup Time
ns
Data In Hold Time
2
ns
Hold# Low Setup Time (Relative To Clock)
Hold# High Setup Time (Relative To Clock)
Hold# High Hold Time (Relative To Clock)
Hold# Low Hold Time (Relative To Clock)
Hold# Low To High-Z Output
5
ns
5
ns
5
ns
5
ns
7
7
7
6
ns
Hold# High To Low-Z Output
ns
Clock Low To Output Valid (CL = 30pF)
Clock Low To Output Valid (CL = 15pF)
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High To Deep Power-Down Mode
CS# High To Standby Mode Without Electronic Signature Read
CS# High To Standby Mode With Electronic Signature Read
CS# High To Next Command After Suspend
Latency Between Resume And Next Suspend
Write Status Register Cycle Time
CS# High To Next Command After Reset (Except From Erase)
CS# High To Next Command After Reset (From Erase)
Page Programming Time
ns
tCLQV
ns
tWHSL
tSHWL
tDP
20
ns
100
ns
20
22
22
20
μs
μs
μs
μs
μs
ms
μs
ms
ms
ms
s
tRES1
tRES2
tSUS
tRS
100
tW
5
35
30
tRST
tRST_E
tPP
12
0.7
90
3.5
600
1.4
2.5
80
tSE
Sector Erase Time
tBE1
tBE2
tCE
Block Erase Time (32K Bytes)
0.3
0.45
20
Block Erase Time (64K Bytes)
s
Chip Erase Time (GD25LQ32D)
s
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
59
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
(T= -40℃~125℃, VCC=1.65~2.0V, CL=30pf)
Symbol
FC
Parameter
Serial Clock Frequency For: all command except for 03H
Serial Clock Frequency For: Read (03H)
Serial Clock High Time
Min.
Typ.
Max.
80
Unit.
MHz
MHz
ns
fR
60
tCLH
4
4
tCLL
Serial Clock Low Time
ns
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
0.1
0.1
5
V/ns
V/ns
ns
CS# Active Hold Time
5
ns
CS# Not Active Setup Time
5
ns
CS# Not Active Hold Time
5
ns
CS# High Time (Read/Write)
20
ns
Output Disable Time
6
ns
Output Hold Time
1.2
2
ns
Data In Setup Time
ns
Data In Hold Time
2
ns
Hold# Low Setup Time (Relative To Clock)
Hold# High Setup Time (Relative To Clock)
Hold# High Hold Time (Relative To Clock)
Hold# Low Hold Time (Relative To Clock)
Hold# Low To High-Z Output
5
ns
5
ns
5
ns
5
ns
7
7
7
6
ns
Hold# High To Low-Z Output
ns
Clock Low To Output Valid (CL = 30pF)
Clock Low To Output Valid (CL = 15pF)
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High To Deep Power-Down Mode
CS# High To Standby Mode Without Electronic Signature Read
CS# High To Standby Mode With Electronic Signature Read
CS# High To Next Command After Suspend
Latency Between Resume And Next Suspend
Write Status Register Cycle Time
CS# High To Next Command After Reset (Except From Erase)
CS# High To Next Command After Reset (From Erase)
Page Programming Time
ns
tCLQV
ns
tWHSL
tSHWL
tDP
20
ns
100
ns
20
22
22
20
μs
μs
μs
μs
μs
ms
μs
ms
ms
ms
s
tRES1
tRES2
tSUS
tRS
100
tW
5
35
30
12
4
tRST
tRST_E
tPP
0.7
90
tSE
Sector Erase Time
600
1.6
3.0
80
tBE1
tBE2
tCE
Block Erase Time (32K Bytes)
0.3
0.45
20
Block Erase Time (64K Bytes)
s
Chip Erase Time (GD25LQ32D)
s
Note:
1. Typical value tested at T = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
60
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
Figure43. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tCLCH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
SI
MSB
High-Z
LSB
SO
Figure44. Output Timing
CS#
tCLH
tSHQZ
SCLK
tCLQV
tCLQV
tCLQX
tCLL
tCLQX
SO
SI
LSB
Least significant address bit (LIB) in
Figure45. Resume to Suspend Timing Diagram
tRS
Resume
Command
Suspend
Command
CS#
Figure46. Hold Timing
CS#
tCHHL
tHLCH
tCHHH
tHHCH
tHHQX
SCLK
tHLQZ
SO
HOLD#
SI do not care during HOLD operation.
61
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
9. ORDERING INFORMATION
GD XX XX XX X X X X X
Packing
T or no mark: Tube
Y: Tray
R: Tape and Reel
Green Code
G: Pb Free + Halogen Free Green Package
S: Pb Free + Halogen Free Green Package + SRP1
Function
Temperature Range
I: Industrial (-40℃ to +85℃)
J: Industrial (-40℃ to +105℃)
E: Industrial (-40℃ to +125℃)
F: Industrial+ (-40℃ to +85℃)
3: Automotive (-40℃ to +85℃)*
2: Automotive (-40℃ to +105℃)*
A: Automotive (-40℃ to +125℃)*
Package Type
S: SOP8 208mil
V: VSOP8 208mil
N: USON8 (3x4mm)
Q: USON8 (4x4mm, 0.45mm thickness)
W: WSON8 (6x5mm)
Generation
D: D Version
Density
32: 32M bit
Series
LQ: 1.8V, 4KB Uniform Sector
Product Family
25: SPI Interface Flash
* Please contact GigaDevice sales for automotive products.
62
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
9.1. Valid Part Numbers
Please contact GigaDevice regional sales for the latest product selection and available form factors.
Temperature Range I: Industrial (-40℃ to +85℃)
Product Number
Density
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
Package Type
SOP8 208mil
GD25LQ32DSIG
GD25LQ32DSIS
GD25LQ32DVIG
GD25LQ32DVIS
GD25LQ32DNIG
GD25LQ32DNIS
GD25LQ32DQIG
GD25LQ32DQIS
GD25LQ32DWIG
GD25LQ32DWIS
VSOP8 208mil
USON8 (3x4mm)
USON8 (4x4mm, 0.45mm thickness)
WSON8 (6x5mm)
Temperature Range J: Industrial (-40℃ to +105℃)
Product Number
Density
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
Package Type
SOP8 208mil
GD25LQ32DSJG
GD25LQ32DSJS
GD25LQ32DVJG
GD25LQ32DVJS
GD25LQ32DNJG
GD25LQ32DNJS
GD25LQ32DQJG
GD25LQ32DQJS
GD25LQ32DWJG
GD25LQ32DWJS
VSOP8 208mil
USON8 (3x4mm)
USON8 (4x4mm, 0.45mm thickness)
WSON8 (6x5mm)
63
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
Temperature Range E: Industrial (-40℃ to +125℃)
Product Number
Density
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
Package Type
SOP8 208mil
VSOP8 208mil
GD25LQ32DSEG
GD25LQ32DSES
GD25LQ32DVEG
GD25LQ32DVES
GD25LQ32DNEG
GD25LQ32DNES
GD25LQ32DQEG
GD25LQ32DQES
GD25LQ32DWEG
GD25LQ32DWES
USON8 (3x4mm)
USON8 (4x4mm, 0.45mm thickness)
WSON8 (6x5mm)
Temperature Range F: Industrial+ (-40℃ to +85℃)
Product Number
Density
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
Package Type
SOP8 208mil
GD25LQ32DSFG
GD25LQ32DSFS
GD25LQ32DVFG
GD25LQ32DVFS
GD25LQ32DNFG
GD25LQ32DNFS
GD25LQ32DQFG
GD25LQ32DQFS
GD25LQ32DWFG
GD25LQ32DWFS
VSOP8 208mil
USON8 (3x4mm)
USON8 (4x4mm, 0.45mm thickness)
WSON8 (6x5mm)
64
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
10.PACKAGE INFORMATION
10.1. Package SOP8 208MIL
D
8
5
E
E1
L1
L
1
4
“A”
θ
b
Base Metal
A
A2
c
Detail “A”
A1
b
e
Dimensions
Symbol
Unit
A
A1
A2
b
c
D
E
E1
e
L
L1
θ
Min
-
-
0.05
0.15
0.25
1.70
1.80
1.90
0.31
0.41
0.51
0.15
0.20
0.25
5.13
5.23
5.33
7.70
7.90
8.10
5.18
0.50
0°
-
mm Nom
Max
5.28
5.38
1.27
-
1.31
2.16
0.85
8°
Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.
65
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
10.2. Package VSOP8 208MIL
D
8
5
E
E1
L1
L
1
4
“A”
θ
b
Base Metal
A2
A1
A
c
b
e
Detail “A”
Dimensions
Symbol
Unit
A
A1
A2
b
c
D
E
E1
e
L
L1
θ
Min
-
-
0.05
0.10
0.15
0.75
0.80
0.85
0.35
0.42
0.50
0.09
0.15
0.20
5.18
5.28
5.38
7.70
7.90
8.10
5.18
5.28
5.38
0.50
-
0°
-
mm Nom
Max
1.27
1.31
1.00
0.80
10°
Note:
1. Both the package length and width include the mold flash.
2. Seating plane: Max. 0.1mm.
66
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
10.3. Package USON8 (3*4mm)
c
D
PIN 1#
E
A1
A
Top View
Side View
L
8
1
b
e
or
Note(4)
E1
5
4
D1
Bottom View
Dimensions
Symbol
Unit
A
A1
0.00
c
b
D
D1
E
E1
e
L
Min
0.50
0.55
0.60
0.10
0.15
0.20
0.25
0.30
0.35
2.90
3.00
3.10
0.10
0.20
0.30
3.90
4.00
4.10
0.70
0.80
0.90
0.50
0.60
0.70
mm
Nom
Max
0.02
0.05
0.80
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package factories. These lead shapes
are compatible with each other.
67
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
10.4. Package USON8 (4*4mm, thickness 0.45mm)
c
D
PIN 1#
E
A1
A
Top View
Side View
L
8
1
b
e
E1
5
4
D1
Bottom View
Dimensions
Symbol
Unit
A
A1
c
b
D
D1
E
E1
e
L
Min
0.40
0.45
0.50
0.00
0.02
0.05
0.10
0.15
0.20
0.25
0.30
0.35
3.90
4.00
4.10
2.20
2.30
2.40
3.90
4.00
4.10
2.90
3.00
3.10
0.35
0.40
0.45
mm
Nom
Max
0.80
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package factories. These lead shapes
are compatible with each other
68
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
10.5. Package WSON8 (6*5mm)
c
D
PIN 1#
E
A1
A
Top View
Side View
L
8
1
b
e
E2
5
4
D2
Bottom View
Dimensions
Symbol
A
A1
c
b
D
D2
E
E2
e
L
Unit
Min
0.70
0.75
0.80
0.00
0.02
0.05
0.180
0.203
0.250
0.35
0.40
0.50
5.90
6.00
6.10
3.30
3.40
3.50
4.90
5.00
5.10
3.90
4.00
4.10
0.50
0.60
0.75
mm
Nom
Max
1.27
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package lead frames. These lead
shapes are compatible with each other.
69
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
11.REVISION HISTORY
Version No
Description
Page
Date
1.0
1.1
Initial Release
All
2016-6-16
2016-6-22
Modify Deep Power-Down Current
P60
P4
Modify Features: Add Allows XIP(execute in place) operation
Modify Ordering information: Add Valid Part Numbers
Modify Write Enable for Volatile Status Register(50H) Description
Modify Read Data Bytes(READ)(03H) Description
Modify Data Bytes at Higher Speed(Fast Read)(0BH) Description
Modify Dual Output Fast Read(3BH) Description
Modify Quad Output Fast Read(6BH) Description
Modify Dual I/O Fast Read(BBH) Description
Modify Quad I/O Fast Read(EBH) Description
Modify Quad I/O Word Fast Read(E7H) Description
Modify Set Burst with Wrap(77H) Description
Modify Chip Erase(CE)(60/C7H) Description
Modify Deep Power-Down(DP)(B9H) Description
Modify Read Identification(RDID)(9FH) Description
Modify Program/Erase Suspend(PES)(75H) Description
Modify Erase Security Registers(44H) Description
Modify Program Security Registers(42H) Description
Modify Storage Temperature: -55 to125℃ Change to -65 to 150℃
Add Transient Input/Output Volatge (note:overshoot):-2.0 to
(VCC+2.0)V
P4
P19
P22
P23
P24
P25
P25
P27
P29
P30
P36
P37
P43
P44
P46
P47
P58
P58
1.2
2017-3-26
VCC:-0.6 to (VCC+0.4)V Change to -0.6 to 2.5V
Update Ordering information
P58
P63
P68
P69
P54
All
Update Package WSON8 6*5mm
Update Package USON8 3*4mm
Modify VIL max. value form 0.3VCC to 0.2VCC
Delete SFDP related contents
1.3
1.4
2017-5-12
2017-6-15
Modify the description of Program/Erase Resume (7AH) command
Add Industrial+ (F), Automotive Grade2 (2) and Grade3 (3) in the
ordering information
P44
P57
Modify tw max. value from 30ms to 35ms
P55
P55
P55
P53
Delete tRST_R and tRST_P
1.5
1.6
Add tRST, max. = 30us
2017-9-12
Modify Input Pause Voltage from “0.3VCC to 0.7VCC” to “0.2VCC to
0.7VCC”.
Modify Input Timing Reference Voltage from “0.2VCC to 0.8VCC” to
“0.1VCC to 0.8VCC”.
P53
Modify Icc2 max value from 5uA to 8uA
P54
2017-12-25
Update the description of all packages
P59-63
70
1.8V Uniform Sector
Dual and Quad Serial Flash
Add “E1” values to the dimension table of USON8 4x4 package
Add 4BH command
GD25LQ32D
1.7
1.8
P61
P46
P47
P53
P58
2018-3-2
Modify the sequence diagram of 42H command
Modify tVSL min value from 5ms to 1.8ms
Add tRS, of which the min value is 100us
Add DC/AC parameters @-40~105℃ and @-40~125℃
Add tCLQV (CL = 15pF), of which the max value is 6ns
Modify the sequence diagram of 0CH command
Modify the description of USON8 3x4mm
2018-8-14
P56,57,59,60
P58, 59, 60
P50
1.9
2.0
2018-10-29
2019-4-28
P67
71
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ32D
Important Notice
This document is the property of GigaDevice Semiconductor (Beijing) Inc. and its subsidiaries (the "Company"). This
document, including any product of the Company described in this document (the “Product”), is owned by the Company
under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide. The
Company reserves all rights under such laws and treaties and does not grant any license under its patents, copyrights,
trademarks, or other intellectual property rights. The names and brands of third party referred thereto (if any) are the
property of their respective owner and referred to for identification purposes only.
The Company makes no warranty of any kind, express or implied, with regard to this document or any Product,
including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The Company
does not assume any liability arising out of the application or use of any Product described in this document. Any
information provided in this document is provided only for reference purposes. It is the responsibility of the user of this
document to properly design, program, and test the functionality and safety of any application made of this information and
any resulting product. Except for customized products which has been expressly identified in the applicable agreement, the
Products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household
applications only. The Products are not designed, intended, or authorized for use as components in systems designed or
intended for the operation of weapons, weapons systems, nuclear installations, atomic energy control instruments,
combustion control instruments, airplane or spaceship instruments, traffic signal instruments, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or Product could cause personal injury,
death, property or environmental damage ("Unintended Uses"). Customers shall take any and all actions to ensure using
and selling the Products in accordance with the applicable laws and regulations. The Company is not liable, in whole or in
part, and customers shall and hereby do release the Company as well as it’s suppliers and/or distributors from any claim,
damage, or other liability arising from or related to all Unintended Uses of the Products. Customers shall indemnify and
hold the Company as well as it’s suppliers and/or distributors harmless from and against all claims, costs, damages, and
other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of the Products.
Customers shall discard the device according to the local environmental law.
Information in this document is provided solely in connection with the Products. The Company reserves the right to make
changes, corrections, modifications or improvements to this document and the Products and services described herein at any
time, without notice.
72
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