GD25LQ80CNFG [GIGADEVICE]
1.8V Uniform Sector Dual and Quad Serial Flash;
| 型号： | GD25LQ80CNFG |
| 厂家： | 
GigaDevice |
| 描述： | 1.8V Uniform Sector Dual and Quad Serial Flash |
| 文件： | 总68页 (文件大小：1529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
GD25LQ80C
DATASHEET
1
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
Contents
1
2
3
4
5
6
7
FEATURES .........................................................................................................................................................4
GENERAL DESCRIPTION................................................................................................................................5
MEMORY ORGANIZATION...............................................................................................................................7
DEVICE OPERATION ........................................................................................................................................8
DATA PROTECTION..........................................................................................................................................9
STATUS REGISTER.........................................................................................................................................11
COMMANDS DESCRIPTION..........................................................................................................................13
7.1
WRITE ENABLE (WREN) (06H)................................................................................................................................ 16
WRITE DISABLE (WRDI) (04H) ................................................................................................................................ 16
WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ................................................................................................. 16
READ STATUS REGISTER (RDSR) (05H OR 35H).......................................................................................................... 17
WRITE STATUS REGISTER (WRSR) (01H)................................................................................................................... 17
READ DATA BYTES (READ) (03H)............................................................................................................................. 18
READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH).............................................................................................. 18
DUAL OUTPUT FAST READ (3BH).............................................................................................................................. 19
QUAD OUTPUT FAST READ (6BH)............................................................................................................................. 20
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10 DUAL I/O FAST READ (BBH).................................................................................................................................... 20
7.11 QUAD I/O FAST READ (EBH) ................................................................................................................................... 22
7.12 SET BURST WITH WRAP (77H) ................................................................................................................................. 23
7.13 PAGE PROGRAM (PP) (02H).................................................................................................................................... 24
7.14 QUAD PAGE PROGRAM (32H).................................................................................................................................. 25
7.15 SECTOR ERASE (SE) (20H)....................................................................................................................................... 26
7.16 32KB BLOCK ERASE (BE) (52H)............................................................................................................................... 26
7.17 64KB BLOCK ERASE (BE) (D8H)............................................................................................................................... 27
7.18 CHIP ERASE (CE) (60/C7H)..................................................................................................................................... 27
7.19 ENABLE/DISABLE SO TO OUTPUT RY/BY# (ESRY/DSRY) (70H/80H) ........................................................................... 28
7.20 DEEP POWER-DOWN (DP) (B9H)............................................................................................................................. 29
7.21 RELEASE FROM DEEP POWER-DOWN AND READ DEVICE ID (RDI) (ABH) ......................................................................... 29
7.22 READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) .................................................................................................... 30
7.23 READ MANUFACTURE ID/ DEVICE ID DUAL I/O (92H) ................................................................................................. 31
7.24 READ MANUFACTURE ID/ DEVICE ID QUAD I/O (94H)................................................................................................. 32
7.25 READ IDENTIFICATION (RDID) (9FH)......................................................................................................................... 32
7.26 PROGRAM/ERASE SUSPEND (PES) (75H)................................................................................................................... 33
7.27 PROGRAM/ERASE RESUME (PER) (7AH) ................................................................................................................... 34
7.28 ERASE SECURITY REGISTERS (44H) ............................................................................................................................ 34
7.29 PROGRAM SECURITY REGISTERS (42H)....................................................................................................................... 35
7.30 READ SECURITY REGISTERS (48H) ............................................................................................................................. 36
2
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
7.31 ENABLE RESET (66H) AND RESET (99H)..................................................................................................................... 36
7.32 READ UNIQUE ID (4BH).......................................................................................................................................... 37
7.32 READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH)................................................................................................. 38
8
ELECTRICAL CHARACTERISTICS ..............................................................................................................43
8.1
8.2
8.3
8.4
8.5
8.6
POWER-ON TIMING ........................................................................................................................................... 43
INITIAL DELIVERY STATE ........................................................................................................................................... 43
ABSOLUTE MAXIMUM RATINGS................................................................................................................................. 43
CAPACITANCE MEASUREMENT CONDITIONS................................................................................................................. 44
DC CHARACTERISTICS......................................................................................................................................... 45
AC CHARACTERISTICS......................................................................................................................................... 48
9
ORDERING INFORMATION............................................................................................................................55
9.1 VALID PART NUMBERS ................................................................................................................................................... 56
PACKAGE INFORMATION .........................................................................................................................58
10
10.1 PACKAGE SOP8 150MIL ........................................................................................................................................ 58
10.2 PACKAGE SOP8 208MIL ........................................................................................................................................ 59
10.3 PACKAGE VSOP8 150MIL ...................................................................................................................................... 60
10.4 PACKAGE VSOP8 208MIL ...................................................................................................................................... 61
10.5 PACKAGE USON8 (3*2MM, THICKNESS 0.45MM) ...................................................................................................... 62
10.6 PACKAGE USON8 (3*2MM, THICKNESS 0.55MM) ...................................................................................................... 63
10.7 PACKAGE USON8 (3*4MM).................................................................................................................................... 64
10.8 PACKAGE USON8 (4*4MM, THICKNESS 0.45MM) ...................................................................................................... 65
10.9 PACKAGE WSON8 (6*5MM)................................................................................................................................... 66
11
REVISION HISTORY....................................................................................................................................67
3
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
1 FEATURES
◆ 8M-bit Serial Flash
◆ Fast Program/Erase Speed
- 1024K-Byte
- Page Program time: 0.7ms typical
- Sector Erase time: 40ms typical
- 256 Bytes per programmable page
- Block Erase time: 0.15/0.18s typical
- Chip Erase time: 2.5s typical
◆ Standard, Dual, Quad SPI
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
- Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆ Flexible Architecture
- Uniform Sector of 4K-Byte
- Uniform Block of 32/64K-Byte
- Erase/Program Suspend/Resume
◆ High Speed Clock Frequency
- 104MHz for fast read with 30PF load
- Dual I/O Data transfer up to 208Mbits/s
- Quad I/O Data transfer up to 416Mbits/s
◆ Low Power Consumption
- 9uA typical stand-by current
- 1uA typical power down current
◆ Allows XIP (execute in place) Operation
◆ Advanced security Features
- 128-bit Unique ID
- Continuous Read With 8/16/32/64-Byte Wrap
◆ Software/Hardware Write Protection
- Write protect all/portion of memory via software
- Enable/Disable protection with WP# Pin
- Top/Bottom Block protection
- 3x512-Byte Security Registers With OTP Lock
◆ Single Power Supply Voltage
- Full voltage range: 1.65~2.1V
◆ Minimum 100,000 Program/Erase Cycles
◆ Data Retention
- 20-year data retention typical
4
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
2
GENERAL DESCRIPTION
The GD25LQ80C (8M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 208Mbits/s, the Quad I/O & Quad output data is transferred with speed of 416Mbits/s.
CONNECTION DIAGRAM
CS#
1
2
3
4
8
7
6
5
VCC
CS#
1
2
3
4
8
7
6
5
VCC
SO
(IO1)
HOLD#
(IO3)
SO
(IO1)
HOLD#
(IO3)
Top View
Top View
WP#
(IO2)
WP#
(IO2)
SCLK
SCLK
SI
(IO0)
SI
(IO0)
VSS
VSS
8–LEAD VSOP/SOP
8–LEAD WSON/USON
PIN DESCRIPTION
Pin No.
Pin Name
CS#
I/O
I
Description
1
2
3
4
5
6
7
8
Chip Select Input
SO (IO1)
WP# (IO2)
VSS
I/O
I/O
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
SI (IO0)
SCLK
I/O
I
Data Input (Data Input Output 0)
Serial Clock Input
HOLD# (IO3)
VCC
I/O
Hold Input (Data Input Output 3)
Power Supply
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
5
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
BLOCK DIAGRAM
Write Control
Logic
WP#(IO2)
Status
Register
Flash
Memory
High Voltage
Generators
HOLD#(IO3)
SCLK
SPI
Command &
Control Logic
Page Address
Latch/Counter
CS#
Column Decode And
256-Byte Page Buffer
SI(IO0)
SO(IO1)
Byte Address
Latch/Counter
6
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
3 MEMORY ORGANIZATION
GD25LQ80C
Each device has
Each block has
Each sector has
Each page has
1M
4K
64/32K
256/128
16/8
4K
16
-
256
Bytes
pages
sectors
blocks
-
-
-
256
16/32
-
-
UNIFORM BLOCK SECTOR ARCHITECTURE
GD25LQ80C 64K Bytes Block Sector Architecture
Block
Sector
Address range
255
……
240
239
……
224
……
……
……
……
……
……
47
0FF000H
……
0FFFFFH
……
15
0F0000H
0EF000H
……
0F0FFFH
0EFFFFH
……
14
……
……
2
0E0000H
……
0E0FFFH
……
……
……
……
……
……
……
……
……
……
……
02F000H
……
02FFFFH
……
……
32
020000H
01F000H
……
020FFFH
01FFFFH
……
31
1
……
16
010000H
00F000H
……
010FFFH
00FFFFH
……
15
0
……
0
000000H
000FFFH
7
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
4 DEVICE OPERATION
SPI Mode
Standard SPI
The GD25LQ80C features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial
Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising
edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25LQ80C supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH
and BBH) commands. These commands allow data to be transferred to or from the device at twice the rate of the standard
SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The GD25LQ80C supports Quad SPI operation when using the “Quad Output Fast Read” (6BH),” Quad I/O Fast Read”
(EBH) commands. These commands allow data to be transferred to or from the device at four times the rate of the standard
SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and
HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status Register
to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status
register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (if
SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of
HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
8
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
5 Data Protection
The GD25LQ80C provide the following data protection methods:
◆
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up/-Software reset (66H+99H)
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory
array that can be read but not change.
◆
◆
◆
Hardware Protection Mode: WP# goes low to protect the BP0~BP4 bits and SRP0~1 bits.
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command and software reset (66H+99H).
Table1. GD25LQ80C Protected area size (CMP=0)
Status Register Content
Memory Content
Addresses
BP4
X
BP3
X
BP2
BP1
BP0
Blocks
NONE
15
Density
NONE
64KB
Portion
NONE
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
NONE
0
0
0F0000H-0FFFFFH
0E0000H-0FFFFFH
0C0000H-0FFFFFH
080000H-0FFFFFH
000000H-00FFFFH
000000H-01FFFFH
000000H-03FFFFH
000000H-07FFFFH
000000H-0FFFFFH
000000H-0FFFFFH
0FF000H-0FFFFFH
0FE000H-0FFFFFH
0FC000H-0FFFFFH
0F8000H-0FFFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
000000H-007FFFH
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
0
0
14 to 15
12 to 15
8 to 15
128KB
256KB
512KB
0
0
0
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
1
X
1
0
1
X
1
0
1
X
0
0 to 1
0 to 3
0 to 7
0 to 15
0 to 15
15
64KB
128KB
256KB
512KB
1MB
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
1MB
ALL
4KB
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
15
8KB
15
16KB
32KB
4KB
15
0
0
8KB
0
16KB
32KB
0
9
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
Table1a. GD25LQ80C Protected area size (CMP=1)
Status Register Content Memory Content
Addresses
BP4
X
BP3
X
BP2
BP1
BP0
Blocks
ALL
Density
1M
Portion
ALL
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
000000H-0FFFFFH
000000H-0EFFFFH
000000H-0DFFFFH
000000H-0BFFFFH
000000H-07FFFFH
010000H-0FFFFFH
020000H-0FFFFFH
040000H-0FFFFFH
080000H-0FFFFFH
NONE
0
0
0 to 14
0 to 13
0 to 11
0 to 7
960KB
896KB
768KB
512KB
Lower 15/16
Lower 7/8
Lower 3/4
Lower 1/2
0
0
0
0
0
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
1
X
1
0
1
X
1
0
1
X
1 to 15
2 to 15
4 to 15
8 to 15
NONE
NONE
0 to 15
0 to 15
0 to 15
0 to 15
0 to 15
0 to 15
0 to 15
0 to 15
960KB
896KB
768KB
512KB
NONE
Upper 15/16
Upper 7/8
Upper 3/4
Upper 1/2
NONE
NONE
NONE
NONE
000000H-0FEFFFH
000000H-0FDFFFH
000000H-0FBFFFH
000000H-0F7FFFH
001000H-0FFFFFH
002000H-0FFFFFH
004000H-0FFFFFH
008000H-0FFFFFH
1020KB
1016KB
1008KB
992KB
1020KB
1016KB
1008KB
992KB
Lower 255/256
Lower 127/128
Lower 63/64
Lower 31/32
Upper 255/156
Upper 127/128
Upper 63/64
Upper 31/32
10
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
6 Status Register
S15
S14
S13
LB3
S12
LB2
S11
LB1
S10
S9
S8
SUS1
CMP
SUS2
QE
SRP1
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
BP4
BP3
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When
WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means
the device is not in program/erase/write status register progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write
Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase
command is accepted.
BP4, BP3, BP2, BP1, BP0 bits
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in
Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block
Protect (BP4, BP3, BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set.
The Chip Erase (CE) command is executed, if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block
Protect (BP2, BP1, and BP0) bits are 1 and CMP=1.
SRP1, SRP0 bits
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits
control the method of write protection: software protection, hardware protection, power supply lock-down or one time
programmable protection.
SRP1 SRP0 #WP Status Register
Description
The Status Register can be written to after a Write Enable
command, WEL=1.(Default)
0
0
0
1
0
1
1
0
1
X
0
Software Protected
Hardware Protected
Hardware Unprotected
WP#=0, the Status Register locked and cannot be written
to.
WP#=1, the Status Register is unlocked and can be written
to after a Write Enable command, WEL=1.
Status Register is protected and cannot be written to again
until the next Power-Down, Power-Up cycle.
Status Register is permanently protected and cannot be
written to.
1
Power Supply Lock-
Down(1)(2)
X
X
1
One Time Program(2)
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order. Please contact GigaDevice for details.
11
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
QE bit
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE
bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are
enabled. (It is best to set the QE bit to 0 to avoid short issues if the WP# or HOLD# pin is tied directly to the power supply
or ground.)
LB3, LB2, LB1 bits
The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the write
protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are unlocked.
The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time
Programmable, once they are set to 1, the Security Registers will become read-only permanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the BP4-BP0 bits to
provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The
default setting is CMP=0.
SUS1, SUS2 bits
The SUS1 and SUS2 bits are read only bit in the status register (S15 and S10) that are set to 1 after executing an
Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the
SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command as well as a power-
down, power-up cycle.
12
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
7 COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first
rising edge of SCLK after CS# is driven low. Then, the one-Byte command code must be shifted in to the device, with most
significant bit first on SI, and each bit is latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-Byte command code. Depending on the command, this might be
followed by address Bytes, or by data Bytes, or by both or none. CS# must be driven high after the last bit of the command
sequence has been completed. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-
Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read instruction can
be completed after any bit of the data-out sequence is being shifted out, and then CS# must be driven high to return to
deselected status.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write
Disable or Deep Power-Down command, CS# must be driven high exactly at a Byte boundary, otherwise the command is
rejected, and is not executed. That is CS# must be driven high when the number of clock pulses after CS# being driven low
is an exact multiple of eight. For Page Program, if at any time the input Byte is not a full Byte, nothing will happen and WEL
will not be reset.
Table2. Commands (Standard/Dual/Quad SPI)
Command Name
Byte 1
06H
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
n-Bytes
Write Enable
Write Disable
04H
Volatile SR
50H
Write Enable
Read Status Register
Read Status Register-1
Write Status Register
Read Data
05H
35H
01H
03H
(S7-S0)
(S15-S8)
S7-S0
(continuous)
(continuous)
S15-S8
A15-A8
A23-A16
A7-A0
(D7-D0)
(Next
(continuous)
(continuous)
Byte)
Fast Read
0BH
3BH
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
dummy
dummy
(D7-D0)
Dual Output
Fast Read
(D7-D0)(1) (continuous)
Dual I/O
BBH
6BH
EBH
A23-A8(2)
A23-A16
A7-A0
(D7-D0)(1)
A7-A0
(continuous)
Fast Read
M7-M0(2)
Quad Output
Fast Read
A15-A8
dummy
(D7-
(continuous)
(continuous)
D0)(3)
Quad I/O
A23-A0
dummy(5)
(D7-D0)(3)
Fast Read
M7-M0(4)
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
Page Program
Quad Page Program
Sector Erase
Block Erase(32K)
Block Erase(64K)
Chip Erase
02H
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
D7-D0
D7-D0
Next Byte
32H
20H
52H
D8H
C7/60H
66H
Enable Reset
13
1.8V Uniform Sector
Dual and Quad Serial Flash
99H
GD25LQ80C
Reset
Set Burst with Wrap
Program/Erase
Suspend
77H
75H
W6-W4
Program/Erase Resume 7AH
Enable SO to output
70H
RY/BY#
Disable SO to output
80H
RY/BY#
Deep Power-Down
Release From Deep
Power-Down, And
Read Device ID
Release From Deep
Power-Down
B9H
ABH
dummy
dummy
dummy
dummy
(ID7-ID0)
(M7-M0)
(continuous)
ABH
90H
Manufacturer/
dummy
A23-A8
00H
(ID7-ID0) (continuous)
Device ID
Manufacturer/
A7-A0,
M[7:0]
(M7-M0)
(ID7-ID0)
(M7-M0)
(ID7-ID0)
dummy
92H
(continuous)
(continuous)
Device ID by Dual I/O
Manufacturer/
A23-A0,
M[7:0]
94H
4BH
dummy
dummy
Device ID by Quad I/O
Read Unique ID
dummy
dummy
dummy
(UID7-
UID0)
(continuous)
(continuous)
(continuous)
Read Serial Flash
Discoverable Parameter
5AH
A23-A16
A15-A8
A7-A0
(D7-D0)
Read Identification
Erase Security
Registers(6)
9FH
44H
(M7-M0)
A23-A16
(ID15-ID8) (ID7-ID0)
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
Program Security
Registers(6)
42H
48H
A23-A16
A23-A16
D7-D0
D7-D0
D7-D0
Read Security
Registers(6)
dummy
NOTE:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8
IO1 = A23, A21, A19, A17, A15, A13, A11, A9
3. Quad Output Data
A6, A4, A2, A0, M6, M4, M2, M0
A7, A5, A3, A1, M7, M5, M3, M1
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3,…..)
14
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
6. Security Registers Address:
Security Register1: A23-A16=00H, A15-A9=0001000b, A8-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A9=0010000b, A8-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A9=0011000b, A8-A0= Byte Address.
TABLE OF ID DEFINITIONS
GD25LQ80C
Operation Code
M7-M0
C8
ID15-ID8
ID7-ID0
14
9FH
90H
ABH
60
C8
13
13
15
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
7.1 Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must
be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register
(WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS# goes low
sending the Write Enable command CS# goes high.
Figure2. Write Enable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
06H
High-Z
SO
7.2 Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS#
goes low Sending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Power-up
and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase, Erase/Program
Security Registers and Reset commands.
Figure3. Write Disable Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
04H
High-Z
SO
7.3 Write Enable for Volatile Status Register (50H)
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the system
configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting
the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command must be
issued prior to a Write Status Register command and any other commands can't be inserted between them. Otherwise,
Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command will not set
the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register bit
values.
16
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
Figure4. Write Enable for Volatile Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
Command(50H)
High-Z
SI
SO
7.4 Read Status Register (RDSR) (05H or 35H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any
time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it
is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is also possible
to read the Status Register continuously. For command code “05H”, the SO will output Status Register bits S7~S0. The
command code “35H”, the SO will output Status Register bits S15~S8.
Figure5. Read Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
Command
05H or 35H
S7~S0 or S15~S8 out
S7~S0 or S15~S8 out
SO
High-Z
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
7.5 Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)
command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S15, S10, S1 and S0 of the Status Register. CS# must be
driven high after the eighth or sixteen bit of the data Byte has been latched in. If not, the Write Status Register (WRSR)
command is not executed. If CS# is driven high after eighth bit of the data Byte, the CMP and QE and SRP1 bits will be
cleared to 0. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated.
While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it
is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3, BP2,
BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write Status
17
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in
accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#)
signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not
executed once the Hardware Protected Mode is entered.
Figure6. Write Status Register Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Status Register in
SCLK
Command
01H
SI
7
6
5
4
3
2
1
0
11 10 9 8
12
14 13
15
MSB
High-Z
SO
7.6 Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-Byte address (A23-A0), and each bit is latched-in on the rising
edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit is shifted out, at a Max frequency
fR, on the falling edge of SCLK. The first Byte addressed can be at any location. The address is automatically incremented
to the next higher address after each Byte of data is shifted out. The whole memory can, therefore, be read with a single
Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure7. Read Data Bytes Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI
Command
03H
24-bit address
23 22 21
MSB
3
2
1
0
Data Out1
Data Out2
High-Z
SO
7
6
5
4
3
2
1
0
MSB
7.7 Read Data Bytes at Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-Byte
address (A23-A0) and a dummy Byte, and each bit is latched-in on the rising edge of SCLK. Then the memory content, at
that address, is shifted out on SO, and each bit is shifted out, at a Max frequency fC, on the falling edge of SCLK. The first
Byte addressed can be at any location. The address is automatically incremented to the next higher address after each
Byte of data is shifted out.
18
1.8V Uniform Sector
Dual and Quad Serial Flash
Figure8. Read Data Bytes at Higher Speed Sequence Diagram
GD25LQ80C
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
0BH
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
7.8 Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-Byte address (A23-A0) and a dummy Byte, and each bit is latched
in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure9. The first Byte addressed can be at any location. The address is
automatically incremented to the next higher address after each Byte of data is shifted out.
Figure9. Dual Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
3BH
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
SCLK
SI
6
4
2
0
6
4
2
0
6
7
Data Out1
Data Out2
SO
7
5
3
1
7
5
3
1
MSB
MSB
19
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
7.9 Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-Byte address (A23-A0) and a dummy Byte, and each bit is latched
in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0.
The command sequence is shown in followed Figure10. The first Byte addressed can be at any location. The address is
automatically incremented to the next higher address after each Byte of data is shifted out. The Quad Enable bit (QE) of
Status Register (S9) must be set to enable for the Quad Output Fast Read command.
Figure10. Quad Output Fast Read Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
6BH
24-bit address
23 22 21
SI(IO0)
3
2
1
0
SO(IO1)
High-Z
High-Z
High-Z
WP#(IO2)
HOLD#(IO3)
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
SCLK
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Byte1 Byte2 Byte3 Byte4
7.10 Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the 3-
Byte address (A23-0) and a “Continuous Read Mode” Byte 2-bit per clock by SI and SO, and each bit is latched in on the
rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence
is shown in followed Figure11. The first Byte addressed can be at any location. The address is automatically incremented
to the next higher address after each Byte of data is shifted out.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits
(M7-0) after the input 3-Byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Dual I/O
Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command
sequence is shown in followed Figure11. If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command
requires the command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used
to reset (M5-4) before issuing normal command.
20
1.8V Uniform Sector
Dual and Quad Serial Flash
Figure11. Dual I/O Fast Read Sequence Diagram (M5-4≠ (1, 0))
GD25LQ80C
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
BBH
SI(IO0)
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
7
A23-16
A15-8
A7-0
M7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
SO(IO1)
Byte1
Byte2
Byte3
Byte4
Figure11a. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
6
4
2
0
6
4
2
0
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
7
5
3
1
7
5
3
1
7
A23-16
A15-8
A7-0
M7-0
CS#
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
SO(IO1)
Byte1
Byte2
Byte3
Byte4
21
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
7.11 Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the 3-Byte
address (A23-0) and a “Continuous Read Mode” Byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, and each
bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1,
IO2, IO3. The command sequence is shown in followed Figure12. The first Byte addressed can be at any location. The
address is automatically incremented to the next higher address after each Byte of data is shifted out. The Quad Enable bit
(QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command.
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode”
bits (M7-0) after the input 3-Byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Quad
I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The command
sequence is shown in followed Figure12a. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next
command requires the command code, thus returning to normal operation. A “Continuous Read Mode” Reset command
can be used to reset (M5-4) before issuing normal command.
Figure12. Quad I/O Fast Read Sequence Diagram (M5-4≠ (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
EBH
SI(IO0)
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SO(IO1)
5
6
7
WP#(IO2)
HOLD#(IO3)
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
Figure12a. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI(IO0)
4
0
4
0
4
0
4
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
SO(IO1)
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
1
2
3
5
6
7
WP#(IO2)
HOLD#(IO3)
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
22
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap”
(77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around”
feature for the following EBH commands. When “Wrap Around” is enabled, the data being accessed can be limited to either
an 8/16/32/64-Byte section of a 256-Byte page. The output data starts at the initial address specified in the command, once
it reaches the ending boundary of the 8/16/32/64-Byte section, the output will wrap around the beginning boundary
automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache
afterwards within a fixed length (8/16/32/64-Byte) of data without issuing multiple read commands. The “Set Burst with Wrap”
command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation
while W6-W5 is used to specify the length of the wrap around section within a page.
7.12 Set Burst with Wrap (77H)
The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” command to access a fixed length of
8/16/32/64-Byte section within a 256-Byte page, in standard SPI mode.
The Set Burst with Wrap command sequence: CS# goes low Send Set Burst with Wrap command Send 24 dummy
bits Send 8 bits “Wrap bits” CS# goes high.
W4=0
W4=1 (default)
W6,W5
Wrap Around
Wrap Length
8-Byte
Wrap Around
Wrap Length
0, 0
0, 1
1, 0
1, 1
Yes
Yes
Yes
Yes
No
No
No
No
N/A
N/A
N/A
N/A
16-Byte
32-Byte
64-Byte
If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” command will use
the W6-W4 setting to access the 8/16/32/64-Byte section within any page. To exit the “Wrap Around” function and return to
normal read operation, another Set Burst with Wrap command should be issued to set W4=1.
Figure14 Set Burst with Wrap Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Command
77H
SI(IO0)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
5
6
x
x
x
x
x
SO(IO1)
x
x
x
WP#(IO2)
HOLD#(IO3)
W6-W4
23
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
7.13 Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address Bytes
and at least one data Byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same page (from the address whose 8
least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program
command sequence: CS# goes low sending Page Program command 3-Byte address on SI at least 1 Byte data
on SI CS# goes high. The command sequence is shown in Figure15If more than 256 Bytes are sent to the device,
previously latched data are discarded and the last 256 data Bytes are guaranteed to be programmed correctly within the
same page. If less than 256 data Bytes are sent to device, they are correctly programmed at the requested addresses
without having any effects on the other Bytes of the same page. CS# must be driven high after the eighth bit of the last data
Byte has been latched in; otherwise the Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0)
is not executed.
Figure15 Page Program Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI
Command
02H
24-bit address
23 22 21
MSB
Data Byte 1
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
24
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
7.14 Quad Page Program (32H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. To use Quad
Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The
quad Page Program command is entered by driving CS# Low, followed by the command code (32H), three address Bytes
and at least one data Byte on IO pins.
The command sequence is shown in Figure16 If more than 256 Bytes are sent to the device, previously latched data are
discarded and the last 256 data Bytes are guaranteed to be programmed correctly within the same page. If less than 256
data Bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the
other Bytes of the same page. CS# must be driven high after the eighth bit of the last data Byte has been latched in;
otherwise the Quad Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad
Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit.
The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0)
is not executed.
Figure16 Quad Page Program Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
32H
24-bit address
23 22 21
MSB
Byte1 Byte2
SI(IO0)
3
2
1
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Byte11Byte12
SCLK
Byte253
Byte256
SI(IO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
25
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
7.15 Sector Erase (SE) (20H)
The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by
driving CS# low, followed by the command code, and 3-address Byte on SI. Any address inside the sector is a valid address
for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low sending Sector Erase command 3-Byte address on SI CS#
goes high. The command sequence is shown in Figure17. CS# must be driven high after the eighth bit of the last address
Byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the
self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status
Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the
self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the
Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block
Protect (BP4, BP3, BP2, BP1, and BP0) bit (see Table1&1a) is not executed.
Figure17. Sector Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
20H
24 Bits Address
23 22
MSB
2
1
0
7.16 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is
entered by driving CS# low, followed by the command code, and three address Bytes on SI. Any address inside the block
is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low sending 32KB Block Erase command 3-Byte address on
SI CS# goes high. The command sequence is shown in Figure18. CS# must be driven high after the eighth bit of the last
address Byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is
driven high, the self-timed Block Erase cycle (whose duration is tSE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
Figure18. 32KB Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
52H
24 Bits Address
23 22
2
1
0
MSB
26
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
7.17 64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is
entered by driving CS# low, followed by the command code, and three address Bytes on SI. Any address inside the block
is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low sending 64KB Block Erase command 3-Byte address on
SI CS# goes high. The command sequence is shown in Figure 19. CS# must be driven high after the eighth bit of the
last address Byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is
driven high, the self-timed Block Erase cycle (whose duration is tSE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is
protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
Figure19. 64KB Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
SI
Command
D8H
24 Bits Address
23 22
MSB
2
1
0
7.18 Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS# Low,
followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low sending Chip Erase command CS# goes high. The command
sequence is shown in Figure20. CS# must be driven high after the eighth bit of the command code has been latched in;
otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase cycle (whose
duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of
the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when
it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip
Erase (CE) command is executed, if the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block Protect
(BP2, BP1, and BP0) bits are 1 and CMP=1.
Figure20. Chip Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
60H or C7H
27
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
7.19 Enable/Disable SO to Output RY/BY# (ESRY/DSRY) (70H/80H)
Besides SO pin is used to output data, it also can be used as the status pin of ready/busy. The ESRY command is for
outputting the ready/busy status to SO. When the device is in the process of power on, enter or exit deep power down
mode and erase/program, its status is busy, and the SO output 0. When the device is in the standby mode, the status of
device is ready, then SO output 1. The DSRY command is for resetting ESRY. The ready/busy status will not output to SO
after DSRY issued.
The Enable/Disable SO to Output RY/BY# command sequence: CS# goes low → sending ESRY command code → CS#
goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the command
code has been latched in; otherwise the Enable/Disable SO to Output RY/BY# command is not executed.
Figure21. Enable/Disable SO to Output RY/BY# Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
70H or 80H
28
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
7.20 Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (the
Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in active
use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device,
and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the Deep
Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command.
Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down and Read Device ID (RDI) command or software reset command. The Release from Deep Power-Down and
Read Device ID (RDI) command releases the device from Deep Power-Down mode, also allows the Device ID of the device
to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always in the Standby Mode after Power-
Up.
The Deep Power-Down command sequence: CS# goes low sending Deep Power-Down command CS# goes high.
The command sequence is shown in Figure22. CS# must be driven high after the eighth bit of the command code has been
latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires a
delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep Power-
Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the
cycle that is in progress.
Figure22. Deep Power-Down Sequence Diagram
CS#
tDP
0
1 2 3 4 5 6 7
SCLK
SI
Command
B9H
Stand-by mode Deep Power-down mode
7.21 Release from Deep Power-Down and Read Device ID (RDI) (ABH)
The Release from Power-Down and Read Device ID command is a multi-purpose command. It can be used to release the
device from the Power-Down state or obtain the devices electronic identification (ID) number.
To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the
instruction code “ABH” and driving CS# high as shown in Figure23. Release from Power-Down will take the time duration
of tRES1 (See AC Characteristics) before the device will resume normal operation and other command are accepted. The
CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS#
pin low and shifting the instruction code “ABH” followed by 3-dummy Byte. The Device ID bits are then shifted out on the
falling edge of SCLK with most significant bit (MSB) first as shown in Figure24. The Device ID value is listed in
Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by
driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the same as
previously described, and shown in Figure24, except that after CS# is driven high it must remain high for a time duration
of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other command will
be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or Write cycle is
29
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle.
Figure23. Release Power-Down Sequence Diagram
CS#
tRES1
0
1
2
3
4
5
6
7
SCLK
SI
Command
ABH
Deep Power-down mode
Stand-by mode
Figure24. Release Power-Down/Read Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38
SCLK
tRES2
Command
ABH
3 Dummy Bytes
23 22
MSB
SI
2
1
0
Device ID
SO
High-Z
7
6
5
4
3
2
1
0
MSB
Deep Power-down Mode Stand-by Mode
7.22 Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command that
provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure25. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
30
1.8V Uniform Sector
Dual and Quad Serial Flash
Figure25. Read Manufacture ID/ Device ID Sequence Diagram
GD25LQ80C
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
24-bit address
23 22 21
SI
90H
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
Device ID
Manufacturer ID
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
7.23 Read Manufacture ID/ Device ID Dual I/O (92H)
The Read Manufacturer/Device ID Dual I/O command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by dual I/O.
The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure26. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure26. Read Manufacture ID/ Device ID Dual I/O Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
92H
SI(IO0)
6
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
7
A23-16
A15-8
A7-0
M7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI(IO0)
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
SO(IO1)
MFR ID
(Repeat)
MFR ID
Device ID
Device ID
(Repeat)
MFR ID
(Repeat)
Device ID
(Repeat)
31
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
7.24 Read Manufacture ID/ Device ID Quad I/O (94H)
The Read Manufacturer/Device ID Quad I/O command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O.
The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a 24-bit address
(A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with
most significant bit (MSB) first as shown in Figure27. If the 24-bit address is initially set to 000001H, the Device ID will be
read first.
Figure27. Read Manufacture ID/ Device ID Quad I/O Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
94H
SI(IO0)
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
5
6
7
WP#(IO2)
HOLD#(IO3)
MFR ID DID
A23-16 A15-8 A7-0 M7-0
Dummy
CS#
24 25 26 27 28 29 30 31
SCLK
SI(IO0)
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
SO(IO1)
WP#(IO2)
HOLD#(IO3)
MFR ID DID
MFR ID DID
(Repeat()Repeat)
(Repeat()Repeat)
7.25 Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two Bytes of
device identification. The device identification indicates the memory type in the first Byte, and the memory capacity of the
device in the second Byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress, is not
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued
while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This is followed
32
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
by the 24-bit device identification, stored in the memory. Each bit is shifted out on the falling edge of Serial Clock. The
command sequence is shown in Figure 28. The Read Identification (RDID) command is terminated by driving CS# high at
any time during data output. When CS# is driven high, the device is in the Standby Mode. Once in the Standby Mode, the
device waits to be selected, so that it can receive, decode and execute commands.
Figure28. Read Identification ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
9FH
Manufacturer ID
7
6
5
4
3
2
1
0
SO
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
Memory Type ID15-ID8
Capacity ID7-ID0
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
7.26 Program/Erase Suspend (PES) (75H)
The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase
operation and then read data from any other sector or block. The Write Status Register command (01H) and Erase/Program
Security Registers command (44H,42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page Program command
(02H/32H) are not allowed during Program suspend. The Write Status Register command (01H) and Erase Security
Registers command (44H) and Erase commands (20H, 52H, D8H, C7H, 60H) are not allowed during Erase suspend.
Program/Erase Suspend is valid only during the page program or sector/block erase operation. A maximum of time of “tsus”
(See AC Characteristics) is required to suspend the program/erase operation.
The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status Register
equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the SUS2/SUS1
bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared form 1
to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off
during the suspend period will reset the device and release the suspend state. The command sequence is show in Figure29.
33
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
Figure29. Program/Erase Suspend Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
tSUS
Command
75H
High-Z
SO
Accept read command
7.27 Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the program or sector/block erase operation after a
Program/Erase Suspend command. The Program/Erase Resume command will be accepted by the device only if the
SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register will be cleared
from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase
operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a
Program/Erase Suspend is active. The command sequence is show in Figure30.
Figure30. Program/Erase Resume Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
7AH
SO
Resume Erase/Program
7.28 Erase Security Registers (44H)
The GD25LQ80C provides three 512-Byte Security Registers which can be erased and programmed individually. These
registers may be used by the system manufacturers to store security and other important information separately from the
main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low sending Erase Security Registers command The
Erase Security Registers command sequence: CS# goes low sending Erase Security Registers command 3-Byte
address on SI CS# goes high. The command sequence is shown below. CS# must be driven high after the eighth bit of
the last address Byte has been latched in; otherwise the Erase Security Registers command is not executed. As soon as
CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security
Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit
(LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security
34
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
Registers will be permanently locked; the Erase Security Registers command will be ignored.
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-9
0 0 0
0 0 0
0 0 0
A8-0
Security Register #1
Security Register #2
Security Register #3
Don‘t care
Don‘t care
Don‘t care
00H
00H
Figure 31. Erase Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
44H
24 Bits Address
23 22
MSB
SI
2
1
0
7.29 Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. Each security register contains four
pages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL)
bit before sending the Program Security Registers command. The Program Security Registers command is entered by
driving CS# Low, followed by the command code (42H), three address Bytes and at least one data Byte on SI. As soon as
CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program
Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed.
At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program Security
Registers command will be ignored.
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-9
0 0 0
0 0 0
0 0 0
A8-0
Security Register #1
Security Register #2
Security Register #3
Byte Address
Byte Address
Byte Address
00H
00H
Figure32. Program Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
42H
24-bit address
23 22 21
MSB
Data Byte 1
SI
3
2
1
0
7
6
5
4
3
2
1
0
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
SI
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
MSB
35
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
7.30 Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-Byte address
(A23-A0) and a dummy Byte, and each bit is latched-in on the rising edge of SCLK. Then the memory content, at that
address, is shifted out on SO, and each bit is shifted out, at a Max frequency fC, on the falling edge of SCLK. The first Byte
addressed can be at any location. The address is automatically incremented to the next higher address after each Byte of
data is shifted out. Once the A8-A0 address reaches the last Byte of the register (Byte 1FFH), it will reset to 000H, the
command is completed by driving CS# high.
Address
A23-16
00H
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-9
0 0 0
0 0 0
0 0 0
A8-0
Security Register #1
Security Register #2
Security Register #3
Byte Address
Byte Address
Byte Address
00H
00H
Figure33. Read Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
48H
24-bit address
23 22 21
SI
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
7.31 Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default
power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch status
(WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Deep Power Down Mode, Continuous Read Mode
bit setting (M7-M0) and Wrap Bit Setting (W6-W4).
The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in either SPI mode. The “Reset (99H)” command
sequence as follow: CS# goes low Sending Enable Reset command CS# goes high CS# goes low Sending
Reset command CS# goes high. Once the Reset command is accepted by the device, the device will take approximately
tRST / tRST_E to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going
or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is
recommended to check the WIP bit and the SUS bit in Status Register before issuing the Reset command sequence.
36
1.8V Uniform Sector
Dual and Quad Serial Flash
Figure34. Enable Reset and Reset command Sequence Diagram
GD25LQ80C
CS#
SCLK
SI
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6 7
Command
66H
Command
99H
High-Z
SO
7.32 Read Unique ID (4BH)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The Unique
ID can be used in conjunction with user software methods to help prevent copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low sending Read Unique ID command Dummy Byte1Dummy
Byte2 Dummy Byte3 Dummy Byte4128bit Unique ID Out CS# goes high.
Figure35 Read Unique ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
36 37 38 39
SCLK
SI
Command
4BH
4-Byte Dummy
7
6
5
3
2
1
0
High-Z
SO
CS#
40 41 42 43 44 45 46 47
SCLK
SI
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
37
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
7.32 Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and
feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be
interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple
vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard
of JEDEC Standard No.216.
Figure36. Read Serial Flash Discoverable Parameter command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
SI
Command
5AH
24-bit address
23 22 21
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SCLK
SI
7
6
5
4
3
2
1
0
Data Out1
Data Out2
SO
7
6
5
4
3
2
1
0
7
6
5
MSB
MSB
38
1.8V Uniform Sector
Dual and Quad Serial Flash
Table3. Signature and Parameter Identification Data Values
GD25LQ80C
Description
Comment
Add(H)
(Byte)
DW Add
(Bit)
Data
Data
SFDP Signature
Fixed:50444653H
00H
01H
02H
03H
04H
05H
06H
07H
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
53H
46H
44H
50H
00H
01H
01H
FFH
53H
46H
44H
50H
00H
01H
01H
FFH
SFDP Minor Revision Number
SFDP Major Revision Number
Number of Parameters Headers
Unused
Start from 00H
Start from 01H
Start from 00H
Contains 0xFFH and can never be
changed
ID number (JEDEC)
00H: It indicates a JEDEC
specified header
08H
09H
0AH
0BH
07:00
15:08
23:16
31:24
00H
00H
01H
09H
00H
00H
01H
09H
Parameter Table Minor Revision Start from 0x00H
Number
Parameter Table Major Revision Start from 0x01H
Number
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
Parameter Table Pointer (PTP)
First address of JEDEC Flash
Parameter table
0CH
0DH
0EH
0FH
07:00
15:08
23:16
31:24
30H
00H
00H
FFH
30H
00H
00H
FFH
Unused
Contains 0xFFH and can never be
changed
ID Number LSB
It is indicates GigaDevice
manufacturer ID
10H
11H
12H
13H
07:00
15:08
23:16
31:24
C8H
00H
01H
03H
C8H
00H
01H
03H
(GigaDevice Manufacturer ID)
Parameter Table Minor Revision Start from 0x00H
Number
Parameter Table Major Revision Start from 0x01H
Number
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
Parameter Table Pointer (PTP)
First address of GigaDevice Flash
Parameter table
14H
15H
16H
17H
07:00
15:08
23:16
31:24
60H
00H
00H
FFH
60H
00H
00H
FFH
Unused
Contains 0xFFH and can never be
changed
39
1.8V Uniform Sector
Dual and Quad Serial Flash
Table4. Parameter Table (0): JEDEC Flash Parameter Tables
GD25LQ80C
Description
Comment
Add(H)
(Byte)
DW Add
(Bit)
Data
Data
00: Reserved; 01: 4KB erase;
10: Reserved;
Block/Sector Erase Size
01:00
02
01b
1b
11: not support 4KB erase
0: 1Byte, 1: 64Byte or larger
0: Nonvolatile status bit
Write Granularity
Write Enable Instruction
Requested for Writing to Volatile 1: Volatile status bit
03
0b
Status Registers
(BP status register bit)
0: Use 50H Opcode,
30H
E5H
Write Enable Opcode Select for
Writing to Volatile Status
Registers
1: Use 06H Opcode,
Note: If target flash status register
is Nonvolatile, then bits 3 and 4
must be set to 00b.
04
0b
Contains 111b and can never be
changed
Unused
07:05
111b
4KB Erase Opcode
31H
32H
15:08
16
20H
1b
20H
F1H
FFH
(1-1-2) Fast Read
0=Not support, 1=Support
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
Address Bytes Number used in
addressing flash array
Double Transfer Rate (DTR)
clocking
18:17
19
00b
0b
0=Not support, 1=Support
(1-2-2) Fast Read
0=Not support, 1=Support
0=Not support, 1=Support
0=Not support, 1=Support
20
21
1b
1b
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
22
1b
23
1b
Unused
33H
31:24
31:00
FFH
Flash Memory Density
(1-4-4) Fast Read Number of
Wait states
37H:34H
007FFFFFH
0 0000b: Wait states (Dummy
Clocks) not support
04:00
00100b
38H
39H
3AH
44H
EBH
08H
(1-4-4) Fast Read Number of
Mode Bits
000b:Mode Bits not support
07:05
15:08
20:16
010b
EBH
(1-4-4) Fast Read Opcode
(1-1-4) Fast Read Number of
Wait states
0 0000b: Wait states (Dummy
Clocks) not support
01000b
(1-1-4) Fast Read Number of
Mode Bits
000b:Mode Bits not support
23:21
31:24
04:00
07:05
000b
6BH
(1-1-4) Fast Read Opcode
3BH
3CH
6BH
08H
(1-1-2) Fast Read Number of 0 0000b: Wait states (Dummy
01000b
000b
Wait states
Clocks) not support
(1-1-2) Fast Read Number
000b: Mode Bits not support
40
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
of Mode Bits
(1-1-2) Fast Read Opcode
(1-2-2) Fast Read Number
of Wait states
3DH
3EH
3FH
15:08
20:16
3BH
3BH
42H
BBH
0 0000b: Wait states (Dummy
Clocks) not support
00010b
(1-2-2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
23:21
010b
(1-2-2) Fast Read Opcode
31:24
00
BBH
0b
(2-2-2) Fast Read
Unused
0=not support 1=support
0=not support 1=support
03:01
04
111b
0b
40H
EEH
(4-4-4) Fast Read
Unused
07:05
31:08
15:00
111b
0xFFH
0xFFH
Unused
43H:41H
45H:44H
0xFFH
0xFFH
Unused
(2-2-2) Fast Read Number
of Wait states
0 0000b: Wait states (Dummy
Clocks) not support
20:16
23:21
00000b
000b
46H
00H
(2-2-2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
(2-2-2) Fast Read Opcode
47H
31:24
15:00
FFH
FFH
Unused
49H:48H
0xFFH
0xFFH
(4-4-4) Fast Read Number of 0 0000b: Wait states (Dummy
20:16
00000b
Wait states
Clocks) not support
4AH
00H
(4-4-4) Fast Read Number
of Mode Bits
000b: Mode Bits not support
23:21
31:24
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
000b
FFH
0CH
20H
0FH
52H
10H
D8H
00H
FFH
(4-4-4) Fast Read Opcode
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
FFH
0CH
20H
0FH
52H
10H
D8H
00H
FFH
Sector/block size=2^N Bytes
Sector Type 1 Size
0x00b: this sector type don’t exist
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size=2^N Bytes
0x00b: this sector type don’t exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size=2^N Bytes
0x00b: this sector type don’t exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size=2^N Bytes
0x00b: this sector type don’t exist
Sector Type 4 erase Opcode
41
1.8V Uniform Sector
Dual and Quad Serial Flash
Table5. Parameter Table (1): GigaDevice Flash Parameter Tables
GD25LQ80C
Add(H)
(Byte)
DW Add
(Bit)
Description
Comment
Data
Data
2000H=2.000V
2100H=2.100V
2700H=2.700V
3600H=3.600V
1650H=1.650V
2250H=2.250V
2350H=2.350V
2700H=2.700V
0=not support 1=support
Vcc Supply Maximum Voltage
61H:60H
63H:62H
15:00
31:16
2100H
2100H
Vcc Supply Minimum Voltage
1650H
1650H
HW Reset# pin
HW Hold# pin
00
01
02
03
0b
1b
1b
1b
0=not support 1=support
0=not support 1=support
Deep Power Down Mode
SW Reset
0=not support 1=support
Should be issue Reset Enable
(66H) before Reset cmd.
SW Reset Opcode
65H:64H
11:04
99H
F99EH
Program Suspend/Resume
Erase Suspend/Resume
Unused
0=not support 1=support
12
13
14
15
1b
1b
1b
1b
0=not support 1=support
0=not support 1=support
Wrap-Around Read mode
Wrap-Around
Opcode
Read
mode
66H
67H
23:16
77H
77H
64H
08H:support 8B wrap-around read
16H:8B&16B
Wrap-Around Read data length
31:24
64H
32H:8B&16B&32B
64H:8B&16B&32B&64B
0=not support 1=support
Individual block lock
00
01
0b
0b
Individual block lock bit
(Volatile/Nonvolatile)
0=Volatile
1=Nonvolatile
Individual block lock Opcode
09:02
10
FFH
0b
Individual block lock Volatile
EBFC
H
0=protect 1=unprotect
6BH:68
H
protect bit default protect status
Secured OTP
Read Lock
Permanent Lock
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
1b
0b
13
1b(1)
11b
15:14
31:16
Unused
FFFFH
FFFFH
NOTE:
1. GD25LQ80CxxSx supports Permanent Lock. Please contact GigaDevice for details.
42
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
8 ELECTRICAL CHARACTERISTICS
8.1 POWER-ON TIMING
Figure37. Power-On Timing Sequence Diagram
Vcc(max)
Vcc(min)
VWI
Chip Selection is not allowed
Device is fully
accessible
tVSL
Time
Table 6. Power-Up Timing and Write Inhibit Threshold
Parameter
Symbol
tVSL
Min
1.8
Max
Unit
ms
VCC (min) To CS# Low
Write Inhibit Voltage VCC (min)
VWI
1
1.4
V
8.2 Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1(each Byte contains FFH).The Status Register
contains 00H (all Status Register bits are 0).
8.3 Absolute Maximum Ratings
Parameter
Value
Unit
Ambient Operating Temperature
-40 to 85
℃
-40 to 105
-40 to 125
Storage Temperature
-65 to 150
℃
V
Applied Input/Output Voltage
Transient Input / Output Voltage (note: overshoot)
VCC
-0.6 to VCC+0.4
-2.0 to VCC+2.0
-0.6 to 2.5
V
V
43
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
Figure 38. Absolute Maximum Ratings Diagram
Maximum Negative Overshoot Waveform
20ns
Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
8.4 Capacitance Measurement Conditions
Symbol
CIN
Parameter
Min.
Typ.
Max.
Unit
Conditions
VIN=0V
Input Capacitance
6
8
pF
pF
pF
ns
V
COUT
CL
Output Capacitance
VOUT=0V
Load Capacitance
30
Input Rise And Fall time
Input Pause Voltage
5
0.1VCC to 0.8VCC
0.2VCC to 0.7VCC
0.5VCC
Input Timing Reference Voltage
Output Timing Reference Voltage
V
V
Figure39. Input Test Waveform and Measurement Level
Input timing reference level
0.7VCC
Output timing reference level
0.5VCC
0.8VCC
0.1VCC
AC Measurement Level
0.2VCC
Note: Input pulse rise and fall time are<5ns
44
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
8.5 DC CHARACTERISTICS
(T= -40℃~85℃, VCC=1.65~2.1V)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit.
μA
ILI
Input Leakage Current
Output Leakage Current
±2
±2
ILO
μA
CS#=VCC,
ICC1
Standby Current
9
1
28
8
μA
μA
VIN=VCC or VSS
CS#=VCC,
ICC2
Deep Power-Down Current
VIN=VCC or VSS
CLK=0.1VCC /
0.9VCC
10
13
10
mA
mA
at 104MHz,
Q=Open(*1,*2,*4 I/O)
ICC3
Operating Current (Read)
CLK=0.1VCC/
0.9VCC
8
at 80MHz,
Q=Open(*1,*2,*4 I/O)
ICC4
ICC5
ICC6
ICC7
ICC8
VIL
Operating Current (PP)
Operating Current (WRSR)
Operating Current (SE)
Operating Current (BE)
Operating Current (CE)
Input Low Voltage
CS#=VCC
CS#=VCC
CS#=VCC
CS#=VCC
CS#=VCC
15
15
15
15
15
20
20
mA
mA
mA
mA
mA
V
20
20
20
0.2VCC
VIH
Input High Voltage
0.7VCC
VCC-0.2
V
VOL
VOH
Output Low Voltage
IOL =100μA
IOH =-100μA
0.2
V
Output High Voltage
V
Note:
1. Typical values given for TA=25°C.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
45
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
(T= -40℃~105℃, VCC=1.65~2.1V)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit.
μA
ILI
Input Leakage Current
Output Leakage Current
±2
±2
ILO
μA
CS#=VCC,
ICC1
Standby Current
9
1
50
15
μA
μA
VIN=VCC or VSS
CS#=VCC,
ICC2
Deep Power-Down Current
VIN=VCC or VSS
CLK=0.1VCC /
0.9VCC
10
20
15
mA
mA
at 90MHz,
Q=Open(*1,*2,*4 I/O)
ICC3
Operating Current (Read)
CLK=0.1VCC/
0.9VCC
8
at 80MHz,
Q=Open(*1,*2,*4 I/O)
ICC4
ICC5
ICC6
ICC7
ICC8
VIL
Operating Current (PP)
Operating Current (WRSR)
Operating Current (SE)
Operating Current (BE)
Operating Current (CE)
Input Low Voltage
CS#=VCC
CS#=VCC
CS#=VCC
CS#=VCC
CS#=VCC
15
15
15
15
15
30
30
mA
mA
mA
mA
mA
V
30
30
30
0.2VCC
VIH
Input High Voltage
0.7VCC
VCC-0.2
V
VOL
VOH
Output Low Voltage
IOL =100μA
IOH =-100μA
0.2
V
Output High Voltage
V
Note:
1. Typical values given for TA=25°C.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
46
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
(T= -40℃~125℃, VCC=1.65~2.1V)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit.
μA
ILI
Input Leakage Current
Output Leakage Current
±2
±2
ILO
μA
CS#=VCC,
ICC1
Standby Current
9
1
60
20
μA
μA
VIN=VCC or VSS
CS#=VCC,
ICC2
Deep Power-Down Current
VIN=VCC or VSS
CLK=0.1VCC /
0.9VCC
10
20
15
mA
mA
at 90MHz,
Q=Open(*1,*2,*4 I/O)
ICC3
Operating Current (Read)
CLK=0.1VCC/
0.9VCC
8
at 80MHz,
Q=Open(*1,*2,*4 I/O)
ICC4
ICC5
ICC6
ICC7
ICC8
VIL
Operating Current (PP)
Operating Current (WRSR)
Operating Current (SE)
Operating Current (BE)
Operating Current (CE)
Input Low Voltage
CS#=VCC
CS#=VCC
CS#=VCC
CS#=VCC
CS#=VCC
15
15
15
15
15
30
30
mA
mA
mA
mA
mA
V
30
30
30
0.2VCC
VIH
Input High Voltage
0.7VCC
VCC-0.2
V
VOL
VOH
Output Low Voltage
IOL =100μA
IOH =-100μA
0.2
V
Output High Voltage
V
Note:
1. Typical values given for TA=25°C.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
47
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
8.6 AC CHARACTERISTICS
(T= -40℃~85℃, VCC=1.65~2.1V, CL=30pf)
Symbol
Parameter
Serial Clock Frequency For: 0BH, 3BH, BBH, 6BH,
EBH
Min.
Typ.
Max.
104
80
Unit.
fC
MHz
fR
Serial Clock Frequency For: Read (03H)
Serial Clock High Time
MHz
ns
tCLH
4
4
tCLL
Serial Clock Low Time
ns
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
0.1
0.1
5
V/ns
V/ns
ns
CS# Active Hold Time
5
ns
CS# Not Active Setup Time
5
ns
CS# Not Active Hold Time
5
ns
CS# High Time (read/write)
20
ns
Output Disable Time
6
ns
Output Hold Time
1.2
2
ns
Data In Setup Time
ns
Data In Hold Time
2
ns
Hold# Low Setup Time (Relative to Clock)
HOLD# High Setup Time (Relative to Clock)
Hold# High Hold Time (Relative to Clock)
Hold# Low Hold Time (Relative to Clock)
Hold# Low To High-Z Output
5
ns
5
ns
5
ns
5
ns
6
6
7
6
ns
Hold# Low To Low-Z Output
ns
Clock Low To Output Valid (CL = 30pF)
Clock Low To Output Valid (CL = 15pF)
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High To Deep Power-Down Mode
CS# High To Standby Mode Without Electronic
Signature Read
ns
tCLQV
ns
tWHSL
tSHWL
tDP
20
ns
100
ns
3
μs
tRES1
20
μs
μs
CS# High To Standby Mode With Electronic Signature
Read
tRES2
20
20
tSUS
tRS
CS# High To Next Command After Suspend
Latency Between Resume And Next Suspend
CS# High To Next Command After Reset (Except
From Erase)
μs
μs
100
tRST
30
12
μs
CS# High To Next Command After Reset (From
Erase)
tRST_E
ms
tW
Write Status Register Cycle Time
Byte Program Time (First Byte)
1
20
50
ms
tBP1
25
μs
48
1.8V Uniform Sector
Dual and Quad Serial Flash
Addition Byte Program Time (After First Byte)
Page Programming Time
GD25LQ80C
tBP2
tPP
2.5
0.7
5
2.4
300
0.8
1
μs
ms
ms
s
tSE
Sector Erase Time
40
tBE1
tBE2
tCE
Block Erase Time (32K Bytes)
0.15
0.18
2.5
Block Erase Time (64K Bytes)
s
Chip Erase Time (GD25LQ80C)
5
s
Note:
1. Typical values given for TA=25°C.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
49
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
(T= -40℃~105℃, VCC=1.65~2.1V, CL=30pf)
Symbol
Parameter
Serial Clock Frequency For: 0BH, 3BH, BBH, 6BH,
EBH
Min.
Typ.
Max.
90
Unit.
fC
MHz
fR
Serial Clock Frequency For: Read (03H)
Serial Clock High Time
80
MHz
ns
tCLH
4
4
tCLL
Serial Clock Low Time
ns
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
0.1
0.1
5
V/ns
V/ns
ns
CS# Active Hold Time
5
ns
CS# Not Active Setup Time
5
ns
CS# Not Active Hold Time
5
ns
CS# High Time (read/write)
20
ns
Output Disable Time
6
ns
Output Hold Time
1.2
2
ns
Data In Setup Time
ns
Data In Hold Time
2
ns
Hold# Low Setup Time (Relative to Clock)
HOLD# High Setup Time (Relative to Clock)
Hold# High Hold Time (Relative to Clock)
Hold# Low Hold Time (Relative to Clock)
Hold# Low To High-Z Output
5
ns
5
ns
5
ns
5
ns
6
6
7
6
ns
Hold# Low To Low-Z Output
ns
Clock Low To Output Valid (CL = 30pF)
Clock Low To Output Valid (CL = 15pF)
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High To Deep Power-Down Mode
CS# High To Standby Mode Without Electronic
Signature Read
ns
tCLQV
ns
tWHSL
tSHWL
tDP
20
ns
100
ns
3
μs
tRES1
20
μs
μs
CS# High To Standby Mode With Electronic Signature
Read
tRES2
20
20
tSUS
tRS
CS# High To Next Command After Suspend
Latency Between Resume And Next Suspend
CS# High To Next Command After Reset (Except
From Erase)
μs
μs
100
tRST
30
12
μs
CS# High To Next Command After Reset (From
Erase)
tRST_E
ms
tW
Write Status Register Cycle Time
Byte Program Time (First Byte)
Addition Byte Program Time (After First Byte)
Page Programming Time
1
25
80
8
ms
μs
tBP1
tBP2
tPP
25
2.5
0.7
μs
3
ms
50
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
tSE
tBE1
tBE2
tCE
Sector Erase Time
40
400
1.2
2
ms
Block Erase Time (32K Bytes)
Block Erase Time (64K Bytes)
Chip Erase Time (GD25LQ80C)
0.15
0.18
2.5
s
s
8
s
Note:
1. Typical values given for TA=25°C.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
51
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
(T= -40℃~125℃, VCC=1.65~2.1V, CL=30pf)
Symbol
Parameter
Serial Clock Frequency For: 0BH, 3BH, BBH, 6BH,
EBH
Min.
Typ.
Max.
90
Unit.
fC
MHz
fR
Serial Clock Frequency For: Read (03H)
Serial Clock High Time
80
MHz
ns
tCLH
4
4
tCLL
Serial Clock Low Time
ns
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CS# Active Setup Time
0.1
0.1
5
V/ns
V/ns
ns
CS# Active Hold Time
5
ns
CS# Not Active Setup Time
5
ns
CS# Not Active Hold Time
5
ns
CS# High Time (read/write)
20
ns
Output Disable Time
6
ns
Output Hold Time
1.2
2
ns
Data In Setup Time
ns
Data In Hold Time
2
ns
Hold# Low Setup Time (Relative to Clock)
HOLD# High Setup Time (Relative to Clock)
Hold# High Hold Time (Relative to Clock)
Hold# Low Hold Time (Relative to Clock)
Hold# Low To High-Z Output
5
ns
5
ns
5
ns
5
ns
6
6
7
6
ns
Hold# Low To Low-Z Output
ns
Clock Low To Output Valid (CL = 30pF)
Clock Low To Output Valid (CL = 15pF)
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High To Deep Power-Down Mode
CS# High To Standby Mode Without Electronic
Signature Read
ns
tCLQV
ns
tWHSL
tSHWL
tDP
20
ns
100
ns
3
μs
tRES1
20
μs
μs
CS# High To Standby Mode With Electronic Signature
Read
tRES2
20
20
tSUS
tRS
CS# High To Next Command After Suspend
Latency Between Resume And Next Suspend
CS# High To Next Command After Reset (Except
From Erase)
μs
μs
100
tRST
30
12
μs
CS# High To Next Command After Reset (From
Erase)
tRST_E
ms
tW
Write Status Register Cycle Time
Byte Program Time (First Byte)
Addition Byte Program Time (After First Byte)
Page Programming Time
1
25
80
8
ms
μs
tBP1
tBP2
tPP
25
2.5
0.7
μs
4
ms
52
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
tSE
tBE
tBE
tCE
Sector Erase Time
40
400
1.8
3.2
12
ms
Block Erase Time (32K Bytes)
Block Erase Time (64K Bytes)
Chip Erase Time (GD25LQ80C)
0.15
0.18
2.5
s
s
s
Note:
1. Typical values given for TA=25°C.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
Figure40. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tCLCH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
SI
MSB
High-Z
LSB
SO
Figure41. Output Timing
CS#
tCLH
tSHQZ
SCLK
tCLQV
tCLQV
tCLQX
tCLL
tCLQX
SO
SI
LSB
Least significant address bit (LIB) in
Figure42. Resume to Suspend Timing Diagram
tRS
Resume
Suspend
Command
Command
CS#
53
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
Figure43. Hold Timing
CS#
tCHHL
tHLCH
tHHCH
tHHQX
SCLK
tCHHH
tHLQZ
SO
HOLD#
SI do not care during HOLD operation.
54
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
9
ORDERING INFORMATION
GD XX XX XX X X X X X
Packing
T or no mark: Tube
Y: Tray
R: Tape and Reel
Green Code
G: Pb Free + Halogen Free Green Package
Temperature Range
I: Industrial (-40℃ to +85℃)
J: Industrial (-40℃ to +105℃)
E: Industrial (-40℃ to +125℃)
F: Industrial+ (-40℃ to +85℃)
3: Automotive (-40℃ to +85℃)*
2: Automotive (-40℃ to +105℃)*
A: Automotive (-40℃ to +125℃)*
Package Type
T: SOP8 150mil
S: SOP8 208mil
M: VSOP8 150mil
V: VSOP8 208mil
E: USON8 (3x2mm, 0.45mm thickness)
U: USON8 (3x2mm, 0.55mm thickness)
N: USON8 (3x4mm)
Q: USON8 (4x4mm, 0.45mm thickness)
W: WSON8 (6x5mm)
Generation
C: C Version
Density
80: 8M bit
Series
LQ: 1.8V, 4KB Uniform Sector
Product Family
25: SPI Interface Flash
* Please contact GigaDevice sales for automotive products.
55
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
9.1 Valid Part Numbers
Please contact GigaDevice regional sales for the latest product selection and available form factors.
Temperature Range I: Industrial (-40℃ to +85℃)
Product Number
Density
Package Type
GD25LQ80CTIG
GD25LQ80CSIG
GD25LQ80CMIG
GD25LQ80CVIG
GD25LQ80CEIG
GD25LQ80CUIG
GD25LQ80CNIG
GD25LQ80CQIG
GD25LQ80CWIG
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
SOP8 150mil
SOP8 208mil
VSOP8 150mil
VSOP8 208mil
USON8 (3x2mm, 0.45mm thickness)
USON8 (3x2mm, 0.55mm thickness)
USON8 (3x4mm)
USON8 (4x4mm, 0.45mm thickness)
WSON8 (6x5mm)
Temperature Range J: Industrial (-40℃ to +105℃)
Product Number
Density
Package Type
GD25LQ80CTJG
GD25LQ80CSJG
GD25LQ80CMJG
GD25LQ80CVJG
GD25LQ80CEJG
GD25LQ80CUJG
GD25LQ80CNJG
GD25LQ80CQJG
GD25LQ80CWJG
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
SOP8 150mil
SOP8 208mil
VSOP8 150mil
VSOP8 208mil
USON8 (3x2mm, 0.45mm thickness)
USON8 (3x2mm, 0.55mm thickness)
USON8 (3x4mm)
USON8 (4x4mm, 0.45mm thickness)
WSON8 (6x5mm)
Temperature Range E: Industrial (-40℃ to +125℃)
Product Number
Density
Package Type
GD25LQ80CTEG
GD25LQ80CSEG
GD25LQ80CMEG
GD25LQ80CVEG
GD25LQ80CEEG
GD25LQ80CUEG
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
SOP8 150mil
SOP8 208mil
VSOP8 150mil
VSOP8 208mil
USON8 (3x2mm, 0.45mm thickness)
USON8 (3x2mm, 0.55mm thickness)
56
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
GD25LQ80CNEG
8Mbit
8Mbit
8Mbit
USON8 (3x4mm)
GD25LQ80CQEG
GD25LQ80CWEG
USON8 (4x4mm, 0.45mm thickness)
WSON8 (6x5mm)
Temperature Range F: Industrial+ (-40℃ to +85℃)
Product Number
Density
Package Type
GD25LQ80CTFG
GD25LQ80CSFG
GD25LQ80CMFG
GD25LQ80CVFG
GD25LQ80CEFG
GD25LQ80CUFG
GD25LQ80CNFG
GD25LQ80CQFG
GD25LQ80CWFG
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
8Mbit
SOP8 150mil
SOP8 208mil
VSOP8 150mil
VSOP8 208mil
USON8 (3x2mm, 0.45mm thickness)
USON8 (3x2mm, 0.55mm thickness)
USON8 (3x4mm)
USON8 (4x4mm, 0.45mm thickness)
WSON8 (6x5mm)
57
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
10 PACKAGE INFORMATION
10.1 Package SOP8 150MIL
D
8
5
E
E1
h
L1
L
1
4
“A”
θ
b
Base Metal
A2
A
c
Detail “A”
A1
b
e
Dimensions
Symbol
Unit
A
A1
A2
b
c
D
E
E1
e
L
L1
h
θ
Min
-
-
0.10
0.15
0.25
1.25
1.45
1.55
0.31
0.41
0.51
0.10
0.20
0.25
4.80
4.90
5.00
5.80
6.00
6.20
3.80
3.90
4.00
0.40
-
0.25
-
0°
-
mm Nom
Max
1.27
1.04
1.75
0.90
0.50
8°
Note:
1. Both the package length and width include the mold flash.
2. Seating plane: Max. 0.1mm.
58
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
10.2 Package SOP8 208MIL
D
8
5
E
E1
L1
L
1
4
“A”
θ
b
Base Metal
A
A2
c
Detail “A”
A1
b
e
Dimensions
Symbol
Unit
A
A1
A2
b
c
D
E
E1
e
L
L1
θ
Min
-
-
0.05
0.15
0.25
1.70
1.80
1.90
0.31
0.41
0.51
0.15
0.20
0.25
5.13
5.23
5.33
7.70
7.90
8.10
5.18
5.28
5.38
0.50
-
0°
-
mm Nom
Max
1.27
1.31
2.16
0.85
8°
Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.
59
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
10.3 Package VSOP8 150MIL
D
8
5
E
E1
L1
L
1
4
“A”
θ
b
Base Metal
A2
A1
A
c
Detail “A”
e
b
Dimensions
Symbol
Unit
A
A1
A2
b
c
D
E
E1
e
L
L1
θ
Min
-
-
0.05
0.10
0.15
0.63
-
0.31
0.41
0.51
0.13
0.15
0.18
4.80
4.90
5.00
5.80
6.00
6.20
3.80
3.90
4.00
0.40
-
0°
-
mm Nom
Max
1.27
1.04
0.90
0.75
0.90
10°
Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.
60
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
10.4 Package VSOP8 208MIL
D
8
5
E
E1
L1
L
1
4
“A”
θ
b
Base Metal
A2
A1
A
c
b
e
Detail “A”
Dimensions
Symbol
Unit
A
A1
A2
b
c
D
E
E1
e
L
L1
θ
Min
-
-
0.05
0.10
0.15
0.75
0.80
0.85
0.35
0.42
0.50
0.09
0.15
0.20
5.18
5.28
5.38
7.70
7.90
8.10
5.18
5.28
5.38
0.50
-
0°
-
mm Nom
Max
1.27
1.31
1.00
0.80
10°
Note:
1. Both the package length and width include the mold flash.
2. Seating plane: Max. 0.1mm.
61
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
10.5 Package USON8 (3*2mm, thickness 0.45mm)
c
D
PIN 1#
E
A1
A
Top View
Side View
L
8
1
b
e
E1
5
4
L1
D1
Bottom View
Dimensions
Symbol
Unit
A
A1
c
b
D
D1
E
E1
e
L
L1
Min
0.40
0.45
0.50
0.00
0.02
0.05
0.10
0.15
0.20
0.20
0.25
0.30
2.90
3.00
3.10
0.15
0.20
0.25
1.90
2.00
2.10
1.55
1.60
1.65
0.30
0.35
0.40
mm Nom
Max
0.50
0.10
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package factories. These lead shapes
are compatible with each other.
62
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
10.6 Package USON8 (3*2mm, thickness 0.55mm)
c
D
PIN 1#
E
A
Top View
Side View
L
8
1
b
e
E1
5
4
L1
D1
Bottom View
Dimensions
Symbol
Unit
A
A1
c
b
D
D1
E
E1
e
L
L1
Min
0.50
0.55
0.60
0.00
0.02
0.05
0.10
0.15
0.20
0.20
0.25
0.30
2.90
3.00
3.10
0.15
0.20
0.25
1.90
2.00
2.10
1.55
1.60
1.65
0.30
0.35
0.40
mm Nom
Max
0.50
0.10
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package lead frames. These lead
shapes are compatible with each other.
63
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
10.7 Package USON8 (3*4mm)
c
D
PIN 1#
E
A1
A
Top View
Side View
L
8
1
b
e
or
Note(4)
E1
5
4
D1
Bottom View
Dimensions
Symbol
Unit
A
A1
c
b
D
D1
E
E1
e
L
Min
0.50
0.55
0.60
0.00
0.02
0.05
0.10
0.15
0.20
0.25
0.30
0.35
2.90
3.00
3.10
0.10
0.20
0.30
3.90
4.00
4.10
0.70
0.80
0.90
0.50
0.60
0.70
mm
Nom
Max
0.80
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package factories. These lead shapes
are compatible with each other.
64
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
10.8 Package USON8 (4*4mm, thickness 0.45mm)
c
D
PIN 1#
E
A1
A
Top View
Side View
L
8
1
b
e
E1
5
4
D1
Bottom View
Dimensions
Symbol
Unit
A
A1
c
b
D
D1
E
E1
e
L
Min
0.40
0.45
0.50
0.00
0.02
0.05
0.10
0.15
0.20
0.25
0.30
0.35
3.90
4.00
4.10
2.20
2.30
2.40
3.90
4.00
4.10
2.90
3.00
3.10
0.35
0.40
0.45
mm
Nom
Max
0.80
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package factories. These lead shapes
are compatible with each other
65
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
10.9 Package WSON8 (6*5mm)
c
D
PIN 1#
E
A1
A
Top View
Side View
L
8
1
b
e
E2
5
4
D2
Bottom View
Dimensions
Symbol
A
A1
c
b
D
D2
E
E2
e
L
Unit
Min
0.70
0.75
0.80
0.00
0.02
0.05
0.180
0.203
0.250
0.35
0.40
0.50
5.90
6.00
6.10
3.30
3.40
3.50
4.90
5.00
5.10
3.90
4.00
4.10
0.50
0.60
0.75
mm
Nom
Max
1.27
Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package lead frames. These lead
shapes are compatible with each other.
66
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
11 REVISION HISTORY
Version No
Description
Page
All
Date
1.0
1.1
Initial Release
2017-10-12
2017-10-24
Added Package: USON8 3*2mm, thickness 0.55mm
Modify the description of WSON8 and USON8 packages
Modify tBP1 from 15-30us to 25-50us
P59
P55-59
P47
1.2
2017-12-1
Delete E7H command
---
Modify tVSL min value from 5ms to 1.8ms
P42
1.3
Modify Icc2 max value from 5uA to 8uA
P44
2018-6-5
Add tRS, of which the min value is 100us
P45
Update the description of SOP8 and VSOP8 packages
Add DC parameters @-40℃~105℃ & @-40℃~125℃
Add AC parameters @-40℃~105℃ & @-40℃~125℃
Add valid part number of products @-40℃~105℃ & @-40℃~125℃
Add 4BH command
P50-53
P45-46
P49-52
P55
1.4
1.5
2018-6-27
2018-7-17
P37
Modify Icc1 max value @-40℃~85℃ from 25uA to 28uA
Modify Icc1 max value @-40℃~125℃ from 50uA to 60uA
Modify Icc2 max value @-40℃~125℃ from 15uA to 20uA
Modify tBE1 max value @-40℃~105℃ from 1s to 1.2s
Modify tBE2 max value @-40℃~105℃ from 1.2s to 2s
Modify tCE max value @-40℃~105℃ from 7s to 8s
Modify tPP max value @-40℃~125℃ from 3ms to 4ms
Modify tBE1 max value @-40℃~125℃ from 1s to 1.8s
Modify tBE2 max value @-40℃~125℃ from 1.2s to 3.2s
Modify tCE max value @-40℃~125℃ from 7s to 12s
Remove tSE max values for 50K cycling
P45
P47
P47
P51
P51
1.6
P51
2018-10-12
P52
P53
P53
P53
P49, 50, 52
1.7
Add tCLQV@15pF, of which the max value is 6ns
2019-3-26
67
1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ80C
Important Notice
This document is the property of GigaDevice Semiconductor (Beijing) Inc. and its subsidiaries (the "Company"). This
document, including any product of the Company described in this document (the “Product”), is owned by the Company
under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide. The
Company reserves all rights under such laws and treaties and does not grant any license under its patents, copyrights,
trademarks, or other intellectual property rights. The names and brands of third party referred thereto (if any) are the property
of their respective owner and referred to for identification purposes only.
The Company makes no warranty of any kind, express or implied, with regard to this document or any Product,
including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The Company
does not assume any liability arising out of the application or use of any Product described in this document. Any information
provided in this document is provided only for reference purposes. It is the responsibility of the user of this document to
properly design, program, and test the functionality and safety of any application made of this information and any resulting
product. Except for customized products which has been expressly identified in the applicable agreement, the Products are
designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only.
The Products are not designed, intended, or authorized for use as components in systems designed or intended for the
operation of weapons, weapons systems, nuclear installations, atomic energy control instruments, combustion control
instruments, airplane or spaceship instruments, traffic signal instruments, life-support devices or systems, other medical
devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or Product could cause personal injury, death, property or
environmental damage ("Unintended Uses"). Customers shall take any and all actions to ensure using and selling the
Products in accordance with the applicable laws and regulations. The Company is not liable, in whole or in part, and
customers shall and hereby do release the Company as well as it’s suppliers and/or distributors from any claim, damage,
or other liability arising from or related to all Unintended Uses of the Products. Customers shall indemnify and hold the
Company as well as it’s suppliers and/or distributors harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of the Products.
Customers shall discard the device according to the local environmental law.
Information in this document is provided solely in connection with the Products. The Company reserves the
right to make changes, corrections, modifications or improvements to this document and the Products and
services described herein at any time, without notice.
68
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明